drivers/gpu/drm/amd/display/dc/dc_dp_types.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef DC_DP_TYPES_H
  27 #define DC_DP_TYPES_H
  28
  29 #include "os_types.h"
  30 #include "dc_ddc_types.h"
  31
  32 enum dc_lane_count {
  33         LANE_COUNT_UNKNOWN = 0,
  34         LANE_COUNT_ONE = 1,
  35         LANE_COUNT_TWO = 2,
  36         LANE_COUNT_FOUR = 4,
  37         LANE_COUNT_EIGHT = 8,
  38         LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
  39 };
  40
  41 /* This is actually a reference clock (27MHz) multiplier
  42  * 162MBps bandwidth for 1.62GHz like rate,
  43  * 270MBps for 2.70GHz,
  44  * 324MBps for 3.24Ghz,
  45  * 540MBps for 5.40GHz
  46  * 810MBps for 8.10GHz
  47  */
  48 enum dc_link_rate {
  49         LINK_RATE_UNKNOWN = 0,
  50         LINK_RATE_LOW = 0x06,           // Rate_1 (RBR)  - 1.62 Gbps/Lane
  51         LINK_RATE_RATE_2 = 0x08,        // Rate_2        - 2.16 Gbps/Lane
  52         LINK_RATE_RATE_3 = 0x09,        // Rate_3        - 2.43 Gbps/Lane
  53         LINK_RATE_HIGH = 0x0A,          // Rate_4 (HBR)  - 2.70 Gbps/Lane
  54         LINK_RATE_RBR2 = 0x0C,          // Rate_5 (RBR2) - 3.24 Gbps/Lane
  55         LINK_RATE_RATE_6 = 0x10,        // Rate_6        - 4.32 Gbps/Lane
  56         LINK_RATE_HIGH2 = 0x14,         // Rate_7 (HBR2) - 5.40 Gbps/Lane
  57         LINK_RATE_RATE_8 = 0x19,        // Rate_8        - 6.75 Gbps/Lane
  58         LINK_RATE_HIGH3 = 0x1E,         // Rate_9 (HBR3) - 8.10 Gbps/Lane
  59         /* Starting from DP2.0 link rate enum directly represents actual
  60          * link rate value in unit of 10 mbps
  61          */
  62         LINK_RATE_UHBR10 = 1000,        // UHBR10 - 10.0 Gbps/Lane
  63         LINK_RATE_UHBR13_5 = 1350,      // UHBR13.5 - 13.5 Gbps/Lane
  64         LINK_RATE_UHBR20 = 2000,        // UHBR10 - 20.0 Gbps/Lane
  65 };
  66
  67 enum dc_link_spread {
  68         LINK_SPREAD_DISABLED = 0x00,
  69         /* 0.5 % downspread 30 kHz */
  70         LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10,
  71         /* 0.5 % downspread 33 kHz */
  72         LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11
  73 };
  74
  75 enum dc_voltage_swing {
  76         VOLTAGE_SWING_LEVEL0 = 0,       /* direct HW translation! */
  77         VOLTAGE_SWING_LEVEL1,
  78         VOLTAGE_SWING_LEVEL2,
  79         VOLTAGE_SWING_LEVEL3,
  80         VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3
  81 };
  82
  83 enum dc_pre_emphasis {
  84         PRE_EMPHASIS_DISABLED = 0,      /* direct HW translation! */
  85         PRE_EMPHASIS_LEVEL1,
  86         PRE_EMPHASIS_LEVEL2,
  87         PRE_EMPHASIS_LEVEL3,
  88         PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3
  89 };
  90 /* Post Cursor 2 is optional for transmitter
  91  * and it applies only to the main link operating at HBR2
  92  */
  93 enum dc_post_cursor2 {
  94         POST_CURSOR2_DISABLED = 0,      /* direct HW translation! */
  95         POST_CURSOR2_LEVEL1,
  96         POST_CURSOR2_LEVEL2,
  97         POST_CURSOR2_LEVEL3,
  98         POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
  99 };
 100
 101 enum dc_dp_ffe_preset_level {
 102         DP_FFE_PRESET_LEVEL0 = 0,
 103         DP_FFE_PRESET_LEVEL1,
 104         DP_FFE_PRESET_LEVEL2,
 105         DP_FFE_PRESET_LEVEL3,
 106         DP_FFE_PRESET_LEVEL4,
 107         DP_FFE_PRESET_LEVEL5,
 108         DP_FFE_PRESET_LEVEL6,
 109         DP_FFE_PRESET_LEVEL7,
 110         DP_FFE_PRESET_LEVEL8,
 111         DP_FFE_PRESET_LEVEL9,
 112         DP_FFE_PRESET_LEVEL10,
 113         DP_FFE_PRESET_LEVEL11,
 114         DP_FFE_PRESET_LEVEL12,
 115         DP_FFE_PRESET_LEVEL13,
 116         DP_FFE_PRESET_LEVEL14,
 117         DP_FFE_PRESET_LEVEL15,
 118         DP_FFE_PRESET_MAX_LEVEL = DP_FFE_PRESET_LEVEL15,
 119 };
 120
 121 enum dc_dp_training_pattern {
 122         DP_TRAINING_PATTERN_SEQUENCE_1 = 0,
 123         DP_TRAINING_PATTERN_SEQUENCE_2,
 124         DP_TRAINING_PATTERN_SEQUENCE_3,
 125         DP_TRAINING_PATTERN_SEQUENCE_4,
 126         DP_TRAINING_PATTERN_VIDEOIDLE,
 127         DP_128b_132b_TPS1,
 128         DP_128b_132b_TPS2,
 129         DP_128b_132b_TPS2_CDS,
 130 };
 131
 132 enum dp_link_encoding {
 133         DP_UNKNOWN_ENCODING = 0,
 134         DP_8b_10b_ENCODING = 1,
 135         DP_128b_132b_ENCODING = 2,
 136 };
 137
 138 enum dp_test_link_rate {
 139         DP_TEST_LINK_RATE_RBR           = 0x06,
 140         DP_TEST_LINK_RATE_HBR           = 0x0A,
 141         DP_TEST_LINK_RATE_HBR2          = 0x14,
 142         DP_TEST_LINK_RATE_HBR3          = 0x1E,
 143         DP_TEST_LINK_RATE_UHBR10        = 0x01,
 144         DP_TEST_LINK_RATE_UHBR20        = 0x02,
 145         DP_TEST_LINK_RATE_UHBR13_5      = 0x03,
 146 };
 147
 148 struct dc_link_settings {
 149         enum dc_lane_count lane_count;
 150         enum dc_link_rate link_rate;
 151         enum dc_link_spread link_spread;
 152         bool use_link_rate_set;
 153         uint8_t link_rate_set;
 154 };
 155
 156 union dc_dp_ffe_preset {
 157         struct {
 158                 uint8_t level           : 4;
 159                 uint8_t reserved        : 1;
 160                 uint8_t no_preshoot     : 1;
 161                 uint8_t no_deemphasis   : 1;
 162                 uint8_t method2         : 1;
 163         } settings;
 164         uint8_t raw;
 165 };
 166
 167 struct dc_lane_settings {
 168         enum dc_voltage_swing VOLTAGE_SWING;
 169         enum dc_pre_emphasis PRE_EMPHASIS;
 170         enum dc_post_cursor2 POST_CURSOR2;
 171         union dc_dp_ffe_preset FFE_PRESET;
 172 };
 173
 174 struct dc_link_training_overrides {
 175         enum dc_voltage_swing *voltage_swing;
 176         enum dc_pre_emphasis *pre_emphasis;
 177         enum dc_post_cursor2 *post_cursor2;
 178         union dc_dp_ffe_preset *ffe_preset;
 179
 180         uint16_t *cr_pattern_time;
 181         uint16_t *eq_pattern_time;
 182         enum dc_dp_training_pattern *pattern_for_cr;
 183         enum dc_dp_training_pattern *pattern_for_eq;
 184
 185         enum dc_link_spread *downspread;
 186         bool *alternate_scrambler_reset;
 187         bool *enhanced_framing;
 188         bool *mst_enable;
 189         bool *fec_enable;
 190 };
 191
 192 union payload_table_update_status {
 193         struct {
 194                 uint8_t  VC_PAYLOAD_TABLE_UPDATED:1;
 195                 uint8_t  ACT_HANDLED:1;
 196         } bits;
 197         uint8_t  raw;
 198 };
 199
 200 union dpcd_rev {
 201         struct {
 202                 uint8_t MINOR:4;
 203                 uint8_t MAJOR:4;
 204         } bits;
 205         uint8_t raw;
 206 };
 207
 208 union max_lane_count {
 209         struct {
 210                 uint8_t MAX_LANE_COUNT:5;
 211                 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;
 212                 uint8_t TPS3_SUPPORTED:1;
 213                 uint8_t ENHANCED_FRAME_CAP:1;
 214         } bits;
 215         uint8_t raw;
 216 };
 217
 218 union max_down_spread {
 219         struct {
 220                 uint8_t MAX_DOWN_SPREAD:1;
 221                 uint8_t RESERVED:5;
 222                 uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1;
 223                 uint8_t TPS4_SUPPORTED:1;
 224         } bits;
 225         uint8_t raw;
 226 };
 227
 228 union mstm_cap {
 229         struct {
 230                 uint8_t MST_CAP:1;
 231                 uint8_t RESERVED:7;
 232         } bits;
 233         uint8_t raw;
 234 };
 235
 236 union lane_count_set {
 237         struct {
 238                 uint8_t LANE_COUNT_SET:5;
 239                 uint8_t POST_LT_ADJ_REQ_GRANTED:1;
 240                 uint8_t RESERVED:1;
 241                 uint8_t ENHANCED_FRAMING:1;
 242         } bits;
 243         uint8_t raw;
 244 };
 245
 246 union lane_status {
 247         struct {
 248                 uint8_t CR_DONE_0:1;
 249                 uint8_t CHANNEL_EQ_DONE_0:1;
 250                 uint8_t SYMBOL_LOCKED_0:1;
 251                 uint8_t RESERVED0:1;
 252                 uint8_t CR_DONE_1:1;
 253                 uint8_t CHANNEL_EQ_DONE_1:1;
 254                 uint8_t SYMBOL_LOCKED_1:1;
 255                 uint8_t RESERVED_1:1;
 256         } bits;
 257         uint8_t raw;
 258 };
 259
 260 union device_service_irq {
 261         struct {
 262                 uint8_t REMOTE_CONTROL_CMD_PENDING:1;
 263                 uint8_t AUTOMATED_TEST:1;
 264                 uint8_t CP_IRQ:1;
 265                 uint8_t MCCS_IRQ:1;
 266                 uint8_t DOWN_REP_MSG_RDY:1;
 267                 uint8_t UP_REQ_MSG_RDY:1;
 268                 uint8_t SINK_SPECIFIC:1;
 269                 uint8_t reserved:1;
 270         } bits;
 271         uint8_t raw;
 272 };
 273
 274 union sink_count {
 275         struct {
 276                 uint8_t SINK_COUNT:6;
 277                 uint8_t CPREADY:1;
 278                 uint8_t RESERVED:1;
 279         } bits;
 280         uint8_t raw;
 281 };
 282
 283 union lane_align_status_updated {
 284         struct {
 285                 uint8_t INTERLANE_ALIGN_DONE:1;
 286                 uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1;
 287                 uint8_t EQ_INTERLANE_ALIGN_DONE_128b_132b:1;
 288                 uint8_t CDS_INTERLANE_ALIGN_DONE_128b_132b:1;
 289                 uint8_t LT_FAILED_128b_132b:1;
 290                 uint8_t RESERVED:1;
 291                 uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1;
 292                 uint8_t LINK_STATUS_UPDATED:1;
 293         } bits;
 294         uint8_t raw;
 295 };
 296
 297 union lane_adjust {
 298         struct {
 299                 uint8_t VOLTAGE_SWING_LANE:2;
 300                 uint8_t PRE_EMPHASIS_LANE:2;
 301                 uint8_t RESERVED:4;
 302         } bits;
 303         struct {
 304                 uint8_t PRESET_VALUE    :4;
 305                 uint8_t RESERVED        :4;
 306         } tx_ffe;
 307         uint8_t raw;
 308 };
 309
 310 union dpcd_training_pattern {
 311         struct {
 312                 uint8_t TRAINING_PATTERN_SET:4;
 313                 uint8_t RECOVERED_CLOCK_OUT_EN:1;
 314                 uint8_t SCRAMBLING_DISABLE:1;
 315                 uint8_t SYMBOL_ERROR_COUNT_SEL:2;
 316         } v1_4;
 317         struct {
 318                 uint8_t TRAINING_PATTERN_SET:2;
 319                 uint8_t LINK_QUAL_PATTERN_SET:2;
 320                 uint8_t RESERVED:4;
 321         } v1_3;
 322         uint8_t raw;
 323 };
 324
 325 /* Training Lane is used to configure downstream DP device's voltage swing
 326 and pre-emphasis levels*/
 327 /* The DPCD addresses are from 0x103 to 0x106*/
 328 union dpcd_training_lane {
 329         struct {
 330                 uint8_t VOLTAGE_SWING_SET:2;
 331                 uint8_t MAX_SWING_REACHED:1;
 332                 uint8_t PRE_EMPHASIS_SET:2;
 333                 uint8_t MAX_PRE_EMPHASIS_REACHED:1;
 334                 uint8_t RESERVED:2;
 335         } bits;
 336         struct {
 337                 uint8_t PRESET_VALUE    :4;
 338                 uint8_t RESERVED        :4;
 339         } tx_ffe;
 340         uint8_t raw;
 341 };
 342
 343 /* TMDS-converter related */
 344 union dwnstream_port_caps_byte0 {
 345         struct {
 346                 uint8_t DWN_STRM_PORTX_TYPE:3;
 347                 uint8_t DWN_STRM_PORTX_HPD:1;
 348                 uint8_t RESERVERD:4;
 349         } bits;
 350         uint8_t raw;
 351 };
 352
 353 /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/
 354 enum dpcd_downstream_port_detailed_type {
 355         DOWN_STREAM_DETAILED_DP = 0,
 356         DOWN_STREAM_DETAILED_VGA,
 357         DOWN_STREAM_DETAILED_DVI,
 358         DOWN_STREAM_DETAILED_HDMI,
 359         DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/
 360         DOWN_STREAM_DETAILED_DP_PLUS_PLUS
 361 };
 362
 363 union dwnstream_port_caps_byte2 {
 364         struct {
 365                 uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
 366                 uint8_t MAX_ENCODED_LINK_BW_SUPPORT:3;
 367                 uint8_t SOURCE_CONTROL_MODE_SUPPORT:1;
 368                 uint8_t CONCURRENT_LINK_BRING_UP_SEQ_SUPPORT:1;
 369                 uint8_t RESERVED:1;
 370         } bits;
 371         uint8_t raw;
 372 };
 373
 374 union dp_downstream_port_present {
 375         uint8_t byte;
 376         struct {
 377                 uint8_t PORT_PRESENT:1;
 378                 uint8_t PORT_TYPE:2;
 379                 uint8_t FMT_CONVERSION:1;
 380                 uint8_t DETAILED_CAPS:1;
 381                 uint8_t RESERVED:3;
 382         } fields;
 383 };
 384
 385 union dwnstream_port_caps_byte3_dvi {
 386         struct {
 387                 uint8_t RESERVED1:1;
 388                 uint8_t DUAL_LINK:1;
 389                 uint8_t HIGH_COLOR_DEPTH:1;
 390                 uint8_t RESERVED2:5;
 391         } bits;
 392         uint8_t raw;
 393 };
 394
 395 union dwnstream_port_caps_byte3_hdmi {
 396         struct {
 397                 uint8_t FRAME_SEQ_TO_FRAME_PACK:1;
 398                 uint8_t YCrCr422_PASS_THROUGH:1;
 399                 uint8_t YCrCr420_PASS_THROUGH:1;
 400                 uint8_t YCrCr422_CONVERSION:1;
 401                 uint8_t YCrCr420_CONVERSION:1;
 402                 uint8_t RESERVED:3;
 403         } bits;
 404         uint8_t raw;
 405 };
 406
 407 union hdmi_sink_encoded_link_bw_support {
 408         struct {
 409                 uint8_t HDMI_SINK_ENCODED_LINK_BW_SUPPORT:3;
 410                 uint8_t RESERVED:5;
 411         } bits;
 412         uint8_t raw;
 413 };
 414
 415 union hdmi_encoded_link_bw {
 416         struct {
 417                 uint8_t FRL_MODE:1; // Bit 0
 418                 uint8_t BW_9Gbps:1;
 419                 uint8_t BW_18Gbps:1;
 420                 uint8_t BW_24Gbps:1;
 421                 uint8_t BW_32Gbps:1;
 422                 uint8_t BW_40Gbps:1;
 423                 uint8_t BW_48Gbps:1;
 424                 uint8_t RESERVED:1; // Bit 7
 425         } bits;
 426         uint8_t raw;
 427 };
 428
 429 /*4-byte structure for detailed capabilities of a down-stream port
 430 (DP-to-TMDS converter).*/
 431 union dwnstream_portxcaps {
 432         struct {
 433                 union dwnstream_port_caps_byte0 byte0;
 434                 unsigned char max_TMDS_clock;   //byte1
 435                 union dwnstream_port_caps_byte2 byte2;
 436
 437                 union {
 438                         union dwnstream_port_caps_byte3_dvi byteDVI;
 439                         union dwnstream_port_caps_byte3_hdmi byteHDMI;
 440                 } byte3;
 441         } bytes;
 442
 443         unsigned char raw[4];
 444 };
 445
 446 union downstream_port {
 447         struct {
 448                 unsigned char   present:1;
 449                 unsigned char   type:2;
 450                 unsigned char   format_conv:1;
 451                 unsigned char   detailed_caps:1;
 452                 unsigned char   reserved:3;
 453         } bits;
 454         unsigned char raw;
 455 };
 456
 457
 458 union sink_status {
 459         struct {
 460                 uint8_t RX_PORT0_STATUS:1;
 461                 uint8_t RX_PORT1_STATUS:1;
 462                 uint8_t RESERVED:6;
 463         } bits;
 464         uint8_t raw;
 465 };
 466
 467 /*6-byte structure corresponding to 6 registers (200h-205h)
 468 read during handling of HPD-IRQ*/
 469 union hpd_irq_data {
 470         struct {
 471                 union sink_count sink_cnt;/* 200h */
 472                 union device_service_irq device_service_irq;/* 201h */
 473                 union lane_status lane01_status;/* 202h */
 474                 union lane_status lane23_status;/* 203h */
 475                 union lane_align_status_updated lane_status_updated;/* 204h */
 476                 union sink_status sink_status;
 477         } bytes;
 478         uint8_t raw[6];
 479 };
 480
 481 union down_stream_port_count {
 482         struct {
 483                 uint8_t DOWN_STR_PORT_COUNT:4;
 484                 uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/
 485                 /*Bit 6 = MSA_TIMING_PAR_IGNORED
 486                 0 = Sink device requires the MSA timing parameters
 487                 1 = Sink device is capable of rendering incoming video
 488                  stream without MSA timing parameters*/
 489                 uint8_t IGNORE_MSA_TIMING_PARAM:1;
 490                 /*Bit 7 = OUI Support
 491                 0 = OUI not supported
 492                 1 = OUI supported
 493                 (OUI and Device Identification mandatory for DP 1.2)*/
 494                 uint8_t OUI_SUPPORT:1;
 495         } bits;
 496         uint8_t raw;
 497 };
 498
 499 union down_spread_ctrl {
 500         struct {
 501                 uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/
 502         /* Bits 4 = SPREAD_AMP. Spreading amplitude
 503         0 = Main link signal is not downspread
 504         1 = Main link signal is downspread <= 0.5%
 505         with frequency in the range of 30kHz ~ 33kHz*/
 506                 uint8_t SPREAD_AMP:1;
 507                 uint8_t RESERVED2:1;/*Bit 5 = RESERVED. Read all 0s*/
 508         /* Bit 6 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE.
 509         0 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE is not enabled by the Source device (default)
 510         1 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE is enabled by Source device */
 511                 uint8_t FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE:1;
 512         /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN
 513         0 = Source device will send valid data for the MSA Timing Params
 514         1 = Source device may send invalid data for these MSA Timing Params*/
 515                 uint8_t IGNORE_MSA_TIMING_PARAM:1;
 516         } bits;
 517         uint8_t raw;
 518 };
 519
 520 union dpcd_edp_config {
 521         struct {
 522                 uint8_t PANEL_MODE_EDP:1;
 523                 uint8_t FRAMING_CHANGE_ENABLE:1;
 524                 uint8_t RESERVED:5;
 525                 uint8_t PANEL_SELF_TEST_ENABLE:1;
 526         } bits;
 527         uint8_t raw;
 528 };
 529
 530 struct dp_device_vendor_id {
 531         uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
 532         uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
 533 };
 534
 535 struct dp_sink_hw_fw_revision {
 536         uint8_t ieee_hw_rev;
 537         uint8_t ieee_fw_rev[2];
 538 };
 539
 540 struct dpcd_vendor_signature {
 541         bool is_valid;
 542
 543         union dpcd_ieee_vendor_signature {
 544                 struct {
 545                         uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
 546                         uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
 547                         uint8_t ieee_hw_rev;
 548                         uint8_t ieee_fw_rev[2];
 549                 };
 550                 uint8_t raw[12];
 551         } data;
 552 };
 553
 554 struct dpcd_amd_signature {
 555         uint8_t AMD_IEEE_TxSignature_byte1;
 556         uint8_t AMD_IEEE_TxSignature_byte2;
 557         uint8_t AMD_IEEE_TxSignature_byte3;
 558 };
 559
 560 struct dpcd_amd_device_id {
 561         uint8_t device_id_byte1;
 562         uint8_t device_id_byte2;
 563         uint8_t zero[4];
 564         uint8_t dce_version;
 565         uint8_t dal_version_byte1;
 566         uint8_t dal_version_byte2;
 567 };
 568
 569 struct dpcd_source_backlight_set {
 570         struct  {
 571                 uint8_t byte0;
 572                 uint8_t byte1;
 573                 uint8_t byte2;
 574                 uint8_t byte3;
 575         } backlight_level_millinits;
 576
 577         struct  {
 578                 uint8_t byte0;
 579                 uint8_t byte1;
 580         } backlight_transition_time_ms;
 581 };
 582
 583 union dpcd_source_backlight_get {
 584         struct {
 585                 uint32_t backlight_millinits_peak; /* 326h */
 586                 uint32_t backlight_millinits_avg; /* 32Ah */
 587         } bytes;
 588         uint8_t raw[8];
 589 };
 590
 591 /*DPCD register of DP receiver capability field bits-*/
 592 union edp_configuration_cap {
 593         struct {
 594                 uint8_t ALT_SCRAMBLER_RESET:1;
 595                 uint8_t FRAMING_CHANGE:1;
 596                 uint8_t RESERVED:1;
 597                 uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1;
 598                 uint8_t RESERVED2:4;
 599         } bits;
 600         uint8_t raw;
 601 };
 602
 603 union dprx_feature {
 604         struct {
 605                 uint8_t GTC_CAP:1;                             // bit 0: DP 1.3+
 606                 uint8_t SST_SPLIT_SDP_CAP:1;                   // bit 1: DP 1.4
 607                 uint8_t AV_SYNC_CAP:1;                         // bit 2: DP 1.3+
 608                 uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1;       // bit 3: DP 1.3+
 609                 uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1;          // bit 4: DP 1.4
 610                 uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4
 611                 uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1;           // bit 6: DP 1.4
 612                 uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1;  // bit 7: DP 1.4
 613         } bits;
 614         uint8_t raw;
 615 };
 616
 617 union training_aux_rd_interval {
 618         struct {
 619                 uint8_t TRAINIG_AUX_RD_INTERVAL:7;
 620                 uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1;
 621         } bits;
 622         uint8_t raw;
 623 };
 624
 625 /* Automated test structures */
 626 union test_request {
 627         struct {
 628         uint8_t LINK_TRAINING                :1;
 629         uint8_t LINK_TEST_PATTRN             :1;
 630         uint8_t EDID_READ                    :1;
 631         uint8_t PHY_TEST_PATTERN             :1;
 632         uint8_t PHY_TEST_CHANNEL_CODING_TYPE :2;
 633         uint8_t AUDIO_TEST_PATTERN           :1;
 634         uint8_t TEST_AUDIO_DISABLED_VIDEO    :1;
 635         } bits;
 636         uint8_t raw;
 637 };
 638
 639 union test_response {
 640         struct {
 641                 uint8_t ACK         :1;
 642                 uint8_t NO_ACK      :1;
 643                 uint8_t EDID_CHECKSUM_WRITE:1;
 644                 uint8_t RESERVED    :5;
 645         } bits;
 646         uint8_t raw;
 647 };
 648
 649 union phy_test_pattern {
 650         struct {
 651                 /* This field is 7 bits for DP2.0 */
 652                 uint8_t PATTERN     :7;
 653                 uint8_t RESERVED    :1;
 654         } bits;
 655         uint8_t raw;
 656 };
 657
 658 /* States of Compliance Test Specification (CTS DP1.2). */
 659 union compliance_test_state {
 660         struct {
 661                 unsigned char STEREO_3D_RUNNING        : 1;
 662                 unsigned char RESERVED                 : 7;
 663         } bits;
 664         unsigned char raw;
 665 };
 666
 667 union link_test_pattern {
 668         struct {
 669                 /* dpcd_link_test_patterns */
 670                 unsigned char PATTERN :2;
 671                 unsigned char RESERVED:6;
 672         } bits;
 673         unsigned char raw;
 674 };
 675
 676 union test_misc {
 677         struct dpcd_test_misc_bits {
 678                 unsigned char SYNC_CLOCK  :1;
 679                 /* dpcd_test_color_format */
 680                 unsigned char CLR_FORMAT  :2;
 681                 /* dpcd_test_dyn_range */
 682                 unsigned char DYN_RANGE   :1;
 683                 unsigned char YCBCR_COEFS :1;
 684                 /* dpcd_test_bit_depth */
 685                 unsigned char BPC         :3;
 686         } bits;
 687         unsigned char raw;
 688 };
 689
 690 union audio_test_mode {
 691         struct {
 692                 unsigned char sampling_rate   :4;
 693                 unsigned char channel_count   :4;
 694         } bits;
 695         unsigned char raw;
 696 };
 697
 698 union audio_test_pattern_period {
 699         struct {
 700                 unsigned char pattern_period   :4;
 701                 unsigned char reserved         :4;
 702         } bits;
 703         unsigned char raw;
 704 };
 705
 706 struct audio_test_pattern_type {
 707         unsigned char value;
 708 };
 709
 710 struct dp_audio_test_data_flags {
 711         uint8_t test_requested  :1;
 712         uint8_t disable_video   :1;
 713 };
 714
 715 struct dp_audio_test_data {
 716
 717         struct dp_audio_test_data_flags flags;
 718         uint8_t sampling_rate;
 719         uint8_t channel_count;
 720         uint8_t pattern_type;
 721         uint8_t pattern_period[8];
 722 };
 723
 724 /* FEC capability DPCD register field bits-*/
 725 union dpcd_fec_capability {
 726         struct {
 727                 uint8_t FEC_CAPABLE:1;
 728                 uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
 729                 uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1;
 730                 uint8_t BIT_ERROR_COUNT_CAPABLE:1;
 731                 uint8_t PARITY_BLOCK_ERROR_COUNT_CAPABLE:1;
 732                 uint8_t ARITY_BIT_ERROR_COUNT_CAPABLE:1;
 733                 uint8_t FEC_RUNNING_INDICATOR_SUPPORTED:1;
 734                 uint8_t FEC_ERROR_REPORTING_POLICY_SUPPORTED:1;
 735         } bits;
 736         uint8_t raw;
 737 };
 738
 739 /* DSC capability DPCD register field bits-*/
 740 struct dpcd_dsc_support {
 741         uint8_t DSC_SUPPORT             :1;
 742         uint8_t DSC_PASSTHROUGH_SUPPORT :1;
 743         uint8_t RESERVED                :6;
 744 };
 745
 746 struct dpcd_dsc_algorithm_revision {
 747         uint8_t DSC_VERSION_MAJOR       :4;
 748         uint8_t DSC_VERSION_MINOR       :4;
 749 };
 750
 751 struct dpcd_dsc_rc_buffer_block_size {
 752         uint8_t RC_BLOCK_BUFFER_SIZE    :2;
 753         uint8_t RESERVED                :6;
 754 };
 755
 756 struct dpcd_dsc_slice_capability1 {
 757         uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE        :1;
 758         uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE       :1;
 759         uint8_t RESERVED                                :1;
 760         uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE      :1;
 761         uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE       :1;
 762         uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE     :1;
 763         uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE       :1;
 764         uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE    :1;
 765 };
 766
 767 struct dpcd_dsc_line_buffer_bit_depth {
 768         uint8_t LINE_BUFFER_BIT_DEPTH   :4;
 769         uint8_t RESERVED                :4;
 770 };
 771
 772 struct dpcd_dsc_block_prediction_support {
 773         uint8_t BLOCK_PREDICTION_SUPPORT:1;
 774         uint8_t RESERVED                :7;
 775 };
 776
 777 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor {
 778         uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW        :7;
 779         uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH       :7;
 780         uint8_t RESERVED                                                        :2;
 781 };
 782
 783 struct dpcd_dsc_decoder_color_format_capabilities {
 784         uint8_t RGB_SUPPORT                     :1;
 785         uint8_t Y_CB_CR_444_SUPPORT             :1;
 786         uint8_t Y_CB_CR_SIMPLE_422_SUPPORT      :1;
 787         uint8_t Y_CB_CR_NATIVE_422_SUPPORT      :1;
 788         uint8_t Y_CB_CR_NATIVE_420_SUPPORT      :1;
 789         uint8_t RESERVED                        :3;
 790 };
 791
 792 struct dpcd_dsc_decoder_color_depth_capabilities {
 793         uint8_t RESERVED0                       :1;
 794         uint8_t EIGHT_BITS_PER_COLOR_SUPPORT    :1;
 795         uint8_t TEN_BITS_PER_COLOR_SUPPORT      :1;
 796         uint8_t TWELVE_BITS_PER_COLOR_SUPPORT   :1;
 797         uint8_t RESERVED1                       :4;
 798 };
 799
 800 struct dpcd_peak_dsc_throughput_dsc_sink {
 801         uint8_t THROUGHPUT_MODE_0:4;
 802         uint8_t THROUGHPUT_MODE_1:4;
 803 };
 804
 805 struct dpcd_dsc_slice_capabilities_2 {
 806         uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE      :1;
 807         uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE       :1;
 808         uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE   :1;
 809         uint8_t RESERVED                                :5;
 810 };
 811
 812 struct dpcd_bits_per_pixel_increment{
 813         uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED   :3;
 814         uint8_t RESERVED                                :5;
 815 };
 816 union dpcd_dsc_basic_capabilities {
 817         struct {
 818                 struct dpcd_dsc_support dsc_support;
 819                 struct dpcd_dsc_algorithm_revision dsc_algorithm_revision;
 820                 struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size;
 821                 uint8_t dsc_rc_buffer_size;
 822                 struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1;
 823                 struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth;
 824                 struct dpcd_dsc_block_prediction_support dsc_block_prediction_support;
 825                 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor;
 826                 struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities;
 827                 struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities;
 828                 struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink;
 829                 uint8_t dsc_maximum_slice_width;
 830                 struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2;
 831                 uint8_t reserved;
 832                 struct dpcd_bits_per_pixel_increment bits_per_pixel_increment;
 833         } fields;
 834         uint8_t raw[16];
 835 };
 836
 837 union dpcd_dsc_branch_decoder_capabilities {
 838         struct {
 839                 uint8_t BRANCH_OVERALL_THROUGHPUT_0;
 840                 uint8_t BRANCH_OVERALL_THROUGHPUT_1;
 841                 uint8_t BRANCH_MAX_LINE_WIDTH;
 842         } fields;
 843         uint8_t raw[3];
 844 };
 845
 846 struct dpcd_dsc_capabilities {
 847         union dpcd_dsc_basic_capabilities dsc_basic_caps;
 848         union dpcd_dsc_branch_decoder_capabilities dsc_branch_decoder_caps;
 849 };
 850
 851 /* These parameters are from PSR capabilities reported by Sink DPCD */
 852 struct psr_caps {
 853         unsigned char psr_version;
 854         unsigned int psr_rfb_setup_time;
 855         bool psr_exit_link_training_required;
 856         unsigned char edp_revision;
 857         unsigned char support_ver;
 858         bool su_granularity_required;
 859         bool y_coordinate_required;
 860         uint8_t su_y_granularity;
 861         bool alpm_cap;
 862         bool standby_support;
 863         uint8_t rate_control_caps;
 864         unsigned int psr_power_opt_flag;
 865 };
 866
 867 union dpcd_dprx_feature_enumeration_list_cont_1 {
 868         struct {
 869                 uint8_t ADAPTIVE_SYNC_SDP_SUPPORT:1;
 870                 uint8_t AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED: 1;
 871                 uint8_t RESERVED0: 2;
 872                 uint8_t VSC_EXT_SDP_VER1_SUPPORT: 1;
 873                 uint8_t RESERVED1: 3;
 874         } bits;
 875         uint8_t raw;
 876 };
 877
 878 struct adaptive_sync_caps {
 879         union dpcd_dprx_feature_enumeration_list_cont_1 dp_adap_sync_caps;
 880 };
 881
 882 /* Length of router topology ID read from DPCD in bytes. */
 883 #define DPCD_USB4_TOPOLOGY_ID_LEN 5
 884
 885 /* DPCD[0xE000D] DP_TUNNELING_CAPABILITIES SUPPORT register. */
 886 union dp_tun_cap_support {
 887         struct {
 888                 uint8_t dp_tunneling :1;
 889                 uint8_t rsvd :5;
 890                 uint8_t panel_replay_tun_opt :1;
 891                 uint8_t dpia_bw_alloc :1;
 892         } bits;
 893         uint8_t raw;
 894 };
 895
 896 /* DPCD[0xE000E] DP_IN_ADAPTER_INFO register. */
 897 union dpia_info {
 898         struct {
 899                 uint8_t dpia_num :5;
 900                 uint8_t rsvd :3;
 901         } bits;
 902         uint8_t raw;
 903 };
 904
 905 /* DP Tunneling over USB4 */
 906 struct dpcd_usb4_dp_tunneling_info {
 907         union dp_tun_cap_support dp_tun_cap;
 908         union dpia_info dpia_info;
 909         uint8_t usb4_driver_id;
 910         uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN];
 911 };
 912
 913 #ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP
 914 #define DP_MAIN_LINK_CHANNEL_CODING_CAP                 0x006
 915 #endif
 916 #ifndef DP_SINK_VIDEO_FALLBACK_FORMATS
 917 #define DP_SINK_VIDEO_FALLBACK_FORMATS                  0x020
 918 #endif
 919 #ifndef DP_FEC_CAPABILITY_1
 920 #define DP_FEC_CAPABILITY_1                             0x091
 921 #endif
 922 #ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT
 923 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT             0x0A3
 924 #endif
 925 #ifndef DP_DSC_CONFIGURATION
 926 #define DP_DSC_CONFIGURATION                            0x161
 927 #endif
 928 #ifndef DP_PHY_SQUARE_PATTERN
 929 #define DP_PHY_SQUARE_PATTERN                           0x249
 930 #endif
 931 #ifndef DP_128b_132b_SUPPORTED_LINK_RATES
 932 #define DP_128b_132b_SUPPORTED_LINK_RATES               0x2215
 933 #endif
 934 #ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL
 935 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL           0x2216
 936 #endif
 937 #ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0
 938 #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0               0X2230
 939 #endif
 940 #ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256
 941 #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256           0X2250
 942 #endif
 943 #ifndef DP_DSC_SUPPORT_AND_DECODER_COUNT
 944 #define DP_DSC_SUPPORT_AND_DECODER_COUNT                0x2260
 945 #endif
 946 #ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0
 947 #define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0        0x2270
 948 #endif
 949 #ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK
 950 #define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK       (1 << 0)
 951 #endif
 952 #ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK
 953 #define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK       (0b111 << 1)
 954 #endif
 955 #ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT
 956 #define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT      1
 957 #endif
 958 #ifndef DP_DSC_DECODER_COUNT_MASK
 959 #define DP_DSC_DECODER_COUNT_MASK                       (0b111 << 5)
 960 #endif
 961 #ifndef DP_DSC_DECODER_COUNT_SHIFT
 962 #define DP_DSC_DECODER_COUNT_SHIFT                      5
 963 #endif
 964 #ifndef DP_MAIN_LINK_CHANNEL_CODING_SET
 965 #define DP_MAIN_LINK_CHANNEL_CODING_SET                 0x108
 966 #endif
 967 #ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER
 968 #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER        0xF0006
 969 #endif
 970 #ifndef DP_PHY_REPEATER_128b_132b_RATES
 971 #define DP_PHY_REPEATER_128b_132b_RATES                 0xF0007
 972 #endif
 973 #ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1
 974 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1     0xF0022
 975 #endif
 976 #ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION
 977 #define DP_INTRA_HOP_AUX_REPLY_INDICATION               (1 << 3)
 978 /* TODO - Use DRM header to replace above once available */
 979 #endif // DP_INTRA_HOP_AUX_REPLY_INDICATION
 980 union dp_main_line_channel_coding_cap {
 981         struct {
 982                 uint8_t DP_8b_10b_SUPPORTED     :1;
 983                 uint8_t DP_128b_132b_SUPPORTED  :1;
 984                 uint8_t RESERVED                :6;
 985         } bits;
 986         uint8_t raw;
 987 };
 988
 989 union dp_main_link_channel_coding_lttpr_cap {
 990         struct {
 991                 uint8_t DP_128b_132b_SUPPORTED  :1;
 992                 uint8_t RESERVED                :7;
 993         } bits;
 994         uint8_t raw;
 995 };
 996
 997 union dp_128b_132b_supported_link_rates {
 998         struct {
 999                 uint8_t UHBR10  :1;
1000                 uint8_t UHBR20  :1;
1001                 uint8_t UHBR13_5:1;
1002                 uint8_t RESERVED:5;
1003         } bits;
1004         uint8_t raw;
1005 };
1006
1007 union dp_128b_132b_supported_lttpr_link_rates {
1008         struct {
1009                 uint8_t UHBR10  :1;
1010                 uint8_t UHBR20  :1;
1011                 uint8_t UHBR13_5:1;
1012                 uint8_t RESERVED:5;
1013         } bits;
1014         uint8_t raw;
1015 };
1016
1017 union dp_sink_video_fallback_formats {
1018         struct {
1019                 uint8_t dp_1024x768_60Hz_24bpp_support  :1;
1020                 uint8_t dp_1280x720_60Hz_24bpp_support  :1;
1021                 uint8_t dp_1920x1080_60Hz_24bpp_support :1;
1022                 uint8_t RESERVED                        :5;
1023         } bits;
1024         uint8_t raw;
1025 };
1026
1027 union dp_fec_capability1 {
1028         struct {
1029                 uint8_t AGGREGATED_ERROR_COUNTERS_CAPABLE       :1;
1030                 uint8_t RESERVED                                :7;
1031         } bits;
1032         uint8_t raw;
1033 };
1034
1035 union dp_cable_id {
1036         struct {
1037                 uint8_t UHBR10_20_CAPABILITY    :2;
1038                 uint8_t UHBR13_5_CAPABILITY     :1;
1039                 uint8_t CABLE_TYPE              :3;
1040                 uint8_t RESERVED                :2;
1041         } bits;
1042         uint8_t raw;
1043 };
1044
1045 struct dp_color_depth_caps {
1046         uint8_t support_6bpc    :1;
1047         uint8_t support_8bpc    :1;
1048         uint8_t support_10bpc   :1;
1049         uint8_t support_12bpc   :1;
1050         uint8_t support_16bpc   :1;
1051         uint8_t RESERVED        :3;
1052 };
1053
1054 struct dp_encoding_format_caps {
1055         uint8_t support_rgb     :1;
1056         uint8_t support_ycbcr444:1;
1057         uint8_t support_ycbcr422:1;
1058         uint8_t support_ycbcr420:1;
1059         uint8_t RESERVED        :4;
1060 };
1061
1062 union dp_dfp_cap_ext {
1063         struct {
1064                 uint8_t supported;
1065                 uint8_t max_pixel_rate_in_mps[2];
1066                 uint8_t max_video_h_active_width[2];
1067                 uint8_t max_video_v_active_height[2];
1068                 struct dp_encoding_format_caps encoding_format_caps;
1069                 struct dp_color_depth_caps rgb_color_depth_caps;
1070                 struct dp_color_depth_caps ycbcr444_color_depth_caps;
1071                 struct dp_color_depth_caps ycbcr422_color_depth_caps;
1072                 struct dp_color_depth_caps ycbcr420_color_depth_caps;
1073         } fields;
1074         uint8_t raw[12];
1075 };
1076
1077 union dp_128b_132b_training_aux_rd_interval {
1078         struct {
1079                 uint8_t VALUE   :7;
1080                 uint8_t UNIT    :1;
1081         } bits;
1082         uint8_t raw;
1083 };
1084
1085 union edp_alpm_caps {
1086         struct {
1087                 uint8_t AUX_WAKE_ALPM_CAP       :1;
1088                 uint8_t PM_STATE_2A_SUPPORT     :1;
1089                 uint8_t AUX_LESS_ALPM_CAP       :1;
1090                 uint8_t RESERVED                :5;
1091         } bits;
1092         uint8_t raw;
1093 };
1094
1095 union edp_psr_dpcd_caps {
1096         struct {
1097                 uint8_t LINK_TRAINING_ON_EXIT_NOT_REQUIRED      :1;
1098                 uint8_t PSR_SETUP_TIME  :3;
1099                 uint8_t Y_COORDINATE_REQUIRED   :1;
1100                 uint8_t SU_GRANULARITY_REQUIRED :1;
1101                 uint8_t FRAME_SYNC_IS_NOT_NEEDED_FOR_SU :1;
1102                 uint8_t RESERVED                :1;
1103         } bits;
1104         uint8_t raw;
1105 };
1106
1107 struct edp_psr_info {
1108         uint8_t psr_version;
1109         union edp_psr_dpcd_caps psr_dpcd_caps;
1110         uint8_t psr2_su_y_granularity_cap;
1111         uint8_t force_psrsu_cap;
1112 };
1113
1114 struct dprx_states {
1115         bool cable_id_written;
1116 };
1117
1118 enum dpcd_downstream_port_max_bpc {
1119         DOWN_STREAM_MAX_8BPC = 0,
1120         DOWN_STREAM_MAX_10BPC,
1121         DOWN_STREAM_MAX_12BPC,
1122         DOWN_STREAM_MAX_16BPC
1123 };
1124
1125 enum link_training_offset {
1126         DPRX                = 0,
1127         LTTPR_PHY_REPEATER1 = 1,
1128         LTTPR_PHY_REPEATER2 = 2,
1129         LTTPR_PHY_REPEATER3 = 3,
1130         LTTPR_PHY_REPEATER4 = 4,
1131         LTTPR_PHY_REPEATER5 = 5,
1132         LTTPR_PHY_REPEATER6 = 6,
1133         LTTPR_PHY_REPEATER7 = 7,
1134         LTTPR_PHY_REPEATER8 = 8
1135 };
1136
1137 #define MAX_REPEATER_CNT 8
1138
1139 struct dc_lttpr_caps {
1140         union dpcd_rev revision;
1141         uint8_t mode;
1142         uint8_t max_lane_count;
1143         uint8_t max_link_rate;
1144         uint8_t phy_repeater_cnt;
1145         uint8_t max_ext_timeout;
1146         union dp_main_link_channel_coding_lttpr_cap main_link_channel_coding;
1147         union dp_128b_132b_supported_lttpr_link_rates supported_128b_132b_rates;
1148         uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1];
1149 };
1150
1151 struct dc_dongle_dfp_cap_ext {
1152         bool supported;
1153         uint16_t max_pixel_rate_in_mps;
1154         uint16_t max_video_h_active_width;
1155         uint16_t max_video_v_active_height;
1156         struct dp_encoding_format_caps encoding_format_caps;
1157         struct dp_color_depth_caps rgb_color_depth_caps;
1158         struct dp_color_depth_caps ycbcr444_color_depth_caps;
1159         struct dp_color_depth_caps ycbcr422_color_depth_caps;
1160         struct dp_color_depth_caps ycbcr420_color_depth_caps;
1161 };
1162
1163 struct dc_dongle_caps {
1164         /* dongle type (DP converter, CV smart dongle) */
1165         enum display_dongle_type dongle_type;
1166         bool extendedCapValid;
1167         /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
1168         indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
1169         bool is_dp_hdmi_s3d_converter;
1170         bool is_dp_hdmi_ycbcr422_pass_through;
1171         bool is_dp_hdmi_ycbcr420_pass_through;
1172         bool is_dp_hdmi_ycbcr422_converter;
1173         bool is_dp_hdmi_ycbcr420_converter;
1174         uint32_t dp_hdmi_max_bpc;
1175         uint32_t dp_hdmi_max_pixel_clk_in_khz;
1176         uint32_t dp_hdmi_frl_max_link_bw_in_kbps;
1177         struct dc_dongle_dfp_cap_ext dfp_cap_ext;
1178 };
1179
1180 struct dpcd_caps {
1181         union dpcd_rev dpcd_rev;
1182         union max_lane_count max_ln_count;
1183         union max_down_spread max_down_spread;
1184         union dprx_feature dprx_feature;
1185
1186         /* valid only for eDP v1.4 or higher*/
1187         uint8_t edp_supported_link_rates_count;
1188         enum dc_link_rate edp_supported_link_rates[8];
1189
1190         /* dongle type (DP converter, CV smart dongle) */
1191         enum display_dongle_type dongle_type;
1192         bool is_dongle_type_one;
1193         /* branch device or sink device */
1194         bool is_branch_dev;
1195         /* Dongle's downstream count. */
1196         union sink_count sink_count;
1197         bool is_mst_capable;
1198         /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
1199         indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
1200         struct dc_dongle_caps dongle_caps;
1201
1202         uint32_t sink_dev_id;
1203         int8_t sink_dev_id_str[6];
1204         int8_t sink_hw_revision;
1205         int8_t sink_fw_revision[2];
1206
1207         uint32_t branch_dev_id;
1208         int8_t branch_dev_name[6];
1209         int8_t branch_hw_revision;
1210         int8_t branch_fw_revision[2];
1211
1212         bool allow_invalid_MSA_timing_param;
1213         bool panel_mode_edp;
1214         bool dpcd_display_control_capable;
1215         bool ext_receiver_cap_field_present;
1216         bool set_power_state_capable_edp;
1217         bool dynamic_backlight_capable_edp;
1218         union dpcd_fec_capability fec_cap;
1219         struct dpcd_dsc_capabilities dsc_caps;
1220         struct dc_lttpr_caps lttpr_caps;
1221         struct adaptive_sync_caps adaptive_sync_caps;
1222         struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info;
1223
1224         union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates;
1225         union dp_main_line_channel_coding_cap channel_coding_cap;
1226         union dp_sink_video_fallback_formats fallback_formats;
1227         union dp_fec_capability1 fec_cap1;
1228         union dp_cable_id cable_id;
1229         uint8_t edp_rev;
1230         union edp_alpm_caps alpm_caps;
1231         struct edp_psr_info psr_info;
1232 };
1233
1234 union dpcd_sink_ext_caps {
1235         struct {
1236                 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode
1237                  * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode.
1238                  */
1239                 uint8_t sdr_aux_backlight_control : 1;
1240                 uint8_t hdr_aux_backlight_control : 1;
1241                 uint8_t reserved_1 : 2;
1242                 uint8_t oled : 1;
1243                 uint8_t reserved_2 : 1;
1244                 uint8_t miniled : 1;
1245                 uint8_t reserved : 1;
1246         } bits;
1247         uint8_t raw;
1248 };
1249
1250 enum dc_link_fec_state {
1251         dc_link_fec_not_ready,
1252         dc_link_fec_ready,
1253         dc_link_fec_enabled
1254 };
1255
1256 union dpcd_psr_configuration {
1257         struct {
1258                 unsigned char ENABLE                    : 1;
1259                 unsigned char TRANSMITTER_ACTIVE_IN_PSR : 1;
1260                 unsigned char CRC_VERIFICATION          : 1;
1261                 unsigned char FRAME_CAPTURE_INDICATION  : 1;
1262                 /* For eDP 1.4, PSR v2*/
1263                 unsigned char LINE_CAPTURE_INDICATION   : 1;
1264                 /* For eDP 1.4, PSR v2*/
1265                 unsigned char IRQ_HPD_WITH_CRC_ERROR    : 1;
1266                 unsigned char ENABLE_PSR2               : 1;
1267                 unsigned char EARLY_TRANSPORT_ENABLE    : 1;
1268         } bits;
1269         unsigned char raw;
1270 };
1271
1272 union dpcd_alpm_configuration {
1273         struct {
1274                 unsigned char ENABLE                    : 1;
1275                 unsigned char IRQ_HPD_ENABLE            : 1;
1276                 unsigned char RESERVED                  : 6;
1277         } bits;
1278         unsigned char raw;
1279 };
1280
1281 union dpcd_sink_active_vtotal_control_mode {
1282         struct {
1283                 unsigned char ENABLE                    : 1;
1284                 unsigned char RESERVED                  : 7;
1285         } bits;
1286         unsigned char raw;
1287 };
1288
1289 union psr_error_status {
1290         struct {
1291                 unsigned char LINK_CRC_ERROR        :1;
1292                 unsigned char RFB_STORAGE_ERROR     :1;
1293                 unsigned char VSC_SDP_ERROR         :1;
1294                 unsigned char RESERVED              :5;
1295         } bits;
1296         unsigned char raw;
1297 };
1298
1299 union psr_sink_psr_status {
1300         struct {
1301         unsigned char SINK_SELF_REFRESH_STATUS  :3;
1302         unsigned char RESERVED                  :5;
1303         } bits;
1304         unsigned char raw;
1305 };
1306
1307 struct edp_trace_power_timestamps {
1308         uint64_t poweroff;
1309         uint64_t poweron;
1310 };
1311
1312 struct dp_trace_lt_counts {
1313         unsigned int total;
1314         unsigned int fail;
1315 };
1316
1317 enum link_training_result {
1318         LINK_TRAINING_SUCCESS,
1319         LINK_TRAINING_CR_FAIL_LANE0,
1320         LINK_TRAINING_CR_FAIL_LANE1,
1321         LINK_TRAINING_CR_FAIL_LANE23,
1322         /* CR DONE bit is cleared during EQ step */
1323         LINK_TRAINING_EQ_FAIL_CR,
1324         /* CR DONE bit is cleared but LANE0_CR_DONE is set during EQ step */
1325         LINK_TRAINING_EQ_FAIL_CR_PARTIAL,
1326         /* other failure during EQ step */
1327         LINK_TRAINING_EQ_FAIL_EQ,
1328         LINK_TRAINING_LQA_FAIL,
1329         /* one of the CR,EQ or symbol lock is dropped */
1330         LINK_TRAINING_LINK_LOSS,
1331         /* Abort link training (because sink unplugged) */
1332         LINK_TRAINING_ABORT,
1333         DP_128b_132b_LT_FAILED,
1334         DP_128b_132b_MAX_LOOP_COUNT_REACHED,
1335         DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT,
1336         DP_128b_132b_CDS_DONE_TIMEOUT,
1337 };
1338
1339 struct dp_trace_lt {
1340         struct dp_trace_lt_counts counts;
1341         struct dp_trace_timestamps {
1342                 unsigned long long start;
1343                 unsigned long long end;
1344         } timestamps;
1345         enum link_training_result result;
1346         bool is_logged;
1347 };
1348
1349 struct dp_trace {
1350         struct dp_trace_lt detect_lt_trace;
1351         struct dp_trace_lt commit_lt_trace;
1352         unsigned int link_loss_count;
1353         bool is_initialized;
1354         struct edp_trace_power_timestamps edp_trace_power_timestamps;
1355 };
1356
1357 /* TODO - This is a temporary location for any new DPCD definitions.
1358  * We should move these to drm_dp header.
1359  */
1360 #ifndef DP_LINK_SQUARE_PATTERN
1361 #define DP_LINK_SQUARE_PATTERN                          0x10F
1362 #endif
1363 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX
1364 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX             0x2217
1365 #endif
1366 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX
1367 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX             0x110
1368 #endif
1369 #ifndef DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE
1370 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE       0x50
1371 #endif
1372 #ifndef DP_TUNNELING_IRQ
1373 #define DP_TUNNELING_IRQ                                (1 << 5)
1374 #endif
1375 /** USB4 DPCD BW Allocation Registers Chapter 10.7 **/
1376 #ifndef DP_TUNNELING_CAPABILITIES
1377 #define DP_TUNNELING_CAPABILITIES                       0xE000D /* 1.4a */
1378 #endif
1379 #ifndef USB4_DRIVER_ID
1380 #define USB4_DRIVER_ID                                  0xE000F /* 1.4a */
1381 #endif
1382 #ifndef USB4_DRIVER_BW_CAPABILITY
1383 #define USB4_DRIVER_BW_CAPABILITY                       0xE0020 /* 1.4a */
1384 #endif
1385 #ifndef DP_IN_ADAPTER_TUNNEL_INFO
1386 #define DP_IN_ADAPTER_TUNNEL_INFO                       0xE0021 /* 1.4a */
1387 #endif
1388 #ifndef DP_BW_GRANULALITY
1389 #define DP_BW_GRANULALITY                               0xE0022 /* 1.4a */
1390 #endif
1391 #ifndef ESTIMATED_BW
1392 #define ESTIMATED_BW                                    0xE0023 /* 1.4a */
1393 #endif
1394 #ifndef ALLOCATED_BW
1395 #define ALLOCATED_BW                                    0xE0024 /* 1.4a */
1396 #endif
1397 #ifndef DP_TUNNELING_STATUS
1398 #define DP_TUNNELING_STATUS                             0xE0025 /* 1.4a */
1399 #endif
1400 #ifndef DPTX_BW_ALLOCATION_MODE_CONTROL
1401 #define DPTX_BW_ALLOCATION_MODE_CONTROL                 0xE0030 /* 1.4a */
1402 #endif
1403 #ifndef REQUESTED_BW
1404 #define REQUESTED_BW                                    0xE0031 /* 1.4a */
1405 #endif
1406 #endif /* DC_DP_TYPES_H */