drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "atomfirmware.h"
  30 #include "dm_helpers.h"
  31 #include "dc.h"
  32 #include "grph_object_id.h"
  33 #include "gpio_service_interface.h"
  34 #include "core_status.h"
  35 #include "dc_link_dp.h"
  36 #include "dc_link_dpia.h"
  37 #include "dc_link_ddc.h"
  38 #include "link_hwss.h"
  39 #include "opp.h"
  40
  41 #include "link_encoder.h"
  42 #include "hw_sequencer.h"
  43 #include "resource.h"
  44 #include "abm.h"
  45 #include "fixed31_32.h"
  46 #include "dpcd_defs.h"
  47 #include "dmcu.h"
  48 #include "hw/clk_mgr.h"
  49 #include "dce/dmub_psr.h"
  50 #include "dmub/dmub_srv.h"
  51 #include "inc/hw/panel_cntl.h"
  52 #include "inc/link_enc_cfg.h"
  53 #include "inc/link_dpcd.h"
  54 #include "link/link_dp_trace.h"
  55
  56 #include "dc/dcn30/dcn30_vpg.h"
  57
  58 #define DC_LOGGER_INIT(logger)
  59
  60 #define LINK_INFO(...) \
  61         DC_LOG_HW_HOTPLUG(  \
  62                 __VA_ARGS__)
  63
  64 #define RETIMER_REDRIVER_INFO(...) \
  65         DC_LOG_RETIMER_REDRIVER(  \
  66                 __VA_ARGS__)
  67
  68 /*******************************************************************************
  69  * Private functions
  70  ******************************************************************************/
  71 static void dc_link_destruct(struct dc_link *link)
  72 {
  73         int i;
  74
  75         if (link->hpd_gpio) {
  76                 dal_gpio_destroy_irq(&link->hpd_gpio);
  77                 link->hpd_gpio = NULL;
  78         }
  79
  80         if (link->ddc)
  81                 dal_ddc_service_destroy(&link->ddc);
  82
  83         if (link->panel_cntl)
  84                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
  85
  86         if (link->link_enc) {
  87                 /* Update link encoder resource tracking variables. These are used for
  88                  * the dynamic assignment of link encoders to streams. Virtual links
  89                  * are not assigned encoder resources on creation.
  90                  */
  91                 if (link->link_id.id != CONNECTOR_ID_VIRTUAL) {
  92                         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL;
  93                         link->dc->res_pool->dig_link_enc_count--;
  94                 }
  95                 link->link_enc->funcs->destroy(&link->link_enc);
  96         }
  97
  98         if (link->local_sink)
  99                 dc_sink_release(link->local_sink);
 100
 101         for (i = 0; i < link->sink_count; ++i)
 102                 dc_sink_release(link->remote_sinks[i]);
 103 }
 104
 105 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 106                           struct graphics_object_id link_id,
 107                           struct gpio_service *gpio_service)
 108 {
 109         enum bp_result bp_result;
 110         struct graphics_object_hpd_info hpd_info;
 111         struct gpio_pin_info pin_info;
 112
 113         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 114                 return NULL;
 115
 116         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 117                 hpd_info.hpd_int_gpio_uid, &pin_info);
 118
 119         if (bp_result != BP_RESULT_OK) {
 120                 ASSERT(bp_result == BP_RESULT_NORECORD);
 121                 return NULL;
 122         }
 123
 124         return dal_gpio_service_create_irq(gpio_service,
 125                                            pin_info.offset,
 126                                            pin_info.mask);
 127 }
 128
 129 /*
 130  *  Function: program_hpd_filter
 131  *
 132  *  @brief
 133  *     Programs HPD filter on associated HPD line
 134  *
 135  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 136  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 137  *
 138  *  @return
 139  *     true on success, false otherwise
 140  */
 141 static bool program_hpd_filter(const struct dc_link *link)
 142 {
 143         bool result = false;
 144         struct gpio *hpd;
 145         int delay_on_connect_in_ms = 0;
 146         int delay_on_disconnect_in_ms = 0;
 147
 148         if (link->is_hpd_filter_disabled)
 149                 return false;
 150         /* Verify feature is supported */
 151         switch (link->connector_signal) {
 152         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 153         case SIGNAL_TYPE_DVI_DUAL_LINK:
 154         case SIGNAL_TYPE_HDMI_TYPE_A:
 155                 /* Program hpd filter */
 156                 delay_on_connect_in_ms = 500;
 157                 delay_on_disconnect_in_ms = 100;
 158                 break;
 159         case SIGNAL_TYPE_DISPLAY_PORT:
 160         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 161                 /* Program hpd filter to allow DP signal to settle */
 162                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 163                  * only 100ms on DELL U2413
 164                  * 0: some passive dongle still show aux mode instead of i2c
 165                  * 20-50: not enough to hide bouncing HPD with passive dongle.
 166                  * also see intermittent i2c read issues.
 167                  */
 168                 delay_on_connect_in_ms = 80;
 169                 delay_on_disconnect_in_ms = 0;
 170                 break;
 171         case SIGNAL_TYPE_LVDS:
 172         case SIGNAL_TYPE_EDP:
 173         default:
 174                 /* Don't program hpd filter */
 175                 return false;
 176         }
 177
 178         /* Obtain HPD handle */
 179         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 180                            link->ctx->gpio_service);
 181
 182         if (!hpd)
 183                 return result;
 184
 185         /* Setup HPD filtering */
 186         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 187                 struct gpio_hpd_config config;
 188
 189                 config.delay_on_connect = delay_on_connect_in_ms;
 190                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 191
 192                 dal_irq_setup_hpd_filter(hpd, &config);
 193
 194                 dal_gpio_close(hpd);
 195
 196                 result = true;
 197         } else {
 198                 ASSERT_CRITICAL(false);
 199         }
 200
 201         /* Release HPD handle */
 202         dal_gpio_destroy_irq(&hpd);
 203
 204         return result;
 205 }
 206
 207 bool dc_link_wait_for_t12(struct dc_link *link)
 208 {
 209         if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
 210                 link->dc->hwss.edp_wait_for_T12(link);
 211
 212                 return true;
 213         }
 214
 215         return false;
 216 }
 217
 218 /**
 219  * dc_link_detect_sink() - Determine if there is a sink connected
 220  *
 221  * @link: pointer to the dc link
 222  * @type: Returned connection type
 223  * Does not detect downstream devices, such as MST sinks
 224  * or display connected through active dongles
 225  */
 226 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 227 {
 228         uint32_t is_hpd_high = 0;
 229         struct gpio *hpd_pin;
 230
 231         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 232                 *type = dc_connection_single;
 233                 return true;
 234         }
 235
 236         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 237                 /*in case it is not on*/
 238                 if (!link->dc->config.edp_no_power_sequencing)
 239                         link->dc->hwss.edp_power_control(link, true);
 240                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 241         }
 242
 243         /* Link may not have physical HPD pin. */
 244         if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
 245                 if (link->is_hpd_pending || !dc_link_dpia_query_hpd_status(link))
 246                         *type = dc_connection_none;
 247                 else
 248                         *type = dc_connection_single;
 249
 250                 return true;
 251         }
 252
 253         /* todo: may need to lock gpio access */
 254         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 255                                link->ctx->gpio_service);
 256         if (!hpd_pin)
 257                 goto hpd_gpio_failure;
 258
 259         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 260         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 261         dal_gpio_close(hpd_pin);
 262         dal_gpio_destroy_irq(&hpd_pin);
 263
 264         if (is_hpd_high) {
 265                 *type = dc_connection_single;
 266                 /* TODO: need to do the actual detection */
 267         } else {
 268                 *type = dc_connection_none;
 269         }
 270
 271         return true;
 272
 273 hpd_gpio_failure:
 274         return false;
 275 }
 276
 277 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
 278 {
 279         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 280
 281         switch (sink_signal) {
 282         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 283         case SIGNAL_TYPE_DVI_DUAL_LINK:
 284         case SIGNAL_TYPE_HDMI_TYPE_A:
 285         case SIGNAL_TYPE_LVDS:
 286         case SIGNAL_TYPE_RGB:
 287                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 288                 break;
 289
 290         case SIGNAL_TYPE_DISPLAY_PORT:
 291         case SIGNAL_TYPE_EDP:
 292                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 293                 break;
 294
 295         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 296                 /* MST does not use I2COverAux, but there is the
 297                  * SPECIAL use case for "immediate dwnstrm device
 298                  * access" (EPR#370830).
 299                  */
 300                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 301                 break;
 302
 303         default:
 304                 break;
 305         }
 306
 307         return transaction_type;
 308 }
 309
 310 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
 311                                               struct graphics_object_id downstream)
 312 {
 313         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 314                 switch (downstream.id) {
 315                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 316                         switch (encoder.id) {
 317                         case ENCODER_ID_INTERNAL_DAC1:
 318                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 319                         case ENCODER_ID_INTERNAL_DAC2:
 320                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 321                                 return SIGNAL_TYPE_RGB;
 322                         default:
 323                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 324                         }
 325                 break;
 326                 case CONNECTOR_ID_DUAL_LINK_DVII:
 327                 {
 328                         switch (encoder.id) {
 329                         case ENCODER_ID_INTERNAL_DAC1:
 330                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 331                         case ENCODER_ID_INTERNAL_DAC2:
 332                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 333                                 return SIGNAL_TYPE_RGB;
 334                         default:
 335                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 336                         }
 337                 }
 338                 break;
 339                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 340                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 341                 case CONNECTOR_ID_DUAL_LINK_DVID:
 342                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 343                 case CONNECTOR_ID_VGA:
 344                         return SIGNAL_TYPE_RGB;
 345                 case CONNECTOR_ID_HDMI_TYPE_A:
 346                         return SIGNAL_TYPE_HDMI_TYPE_A;
 347                 case CONNECTOR_ID_LVDS:
 348                         return SIGNAL_TYPE_LVDS;
 349                 case CONNECTOR_ID_DISPLAY_PORT:
 350                 case CONNECTOR_ID_USBC:
 351                         return SIGNAL_TYPE_DISPLAY_PORT;
 352                 case CONNECTOR_ID_EDP:
 353                         return SIGNAL_TYPE_EDP;
 354                 default:
 355                         return SIGNAL_TYPE_NONE;
 356                 }
 357         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 358                 switch (downstream.id) {
 359                 case ENCODER_ID_EXTERNAL_NUTMEG:
 360                 case ENCODER_ID_EXTERNAL_TRAVIS:
 361                         return SIGNAL_TYPE_DISPLAY_PORT;
 362                 default:
 363                         return SIGNAL_TYPE_NONE;
 364                 }
 365         }
 366
 367         return SIGNAL_TYPE_NONE;
 368 }
 369
 370 /*
 371  * dc_link_is_dp_sink_present() - Check if there is a native DP
 372  * or passive DP-HDMI dongle connected
 373  */
 374 bool dc_link_is_dp_sink_present(struct dc_link *link)
 375 {
 376         enum gpio_result gpio_result;
 377         uint32_t clock_pin = 0;
 378         uint8_t retry = 0;
 379         struct ddc *ddc;
 380
 381         enum connector_id connector_id =
 382                 dal_graphics_object_id_get_connector_id(link->link_id);
 383
 384         bool present =
 385                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 386                 (connector_id == CONNECTOR_ID_EDP) ||
 387                 (connector_id == CONNECTOR_ID_USBC));
 388
 389         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 390
 391         if (!ddc) {
 392                 BREAK_TO_DEBUGGER();
 393                 return present;
 394         }
 395
 396         /* Open GPIO and set it to I2C mode */
 397         /* Note: this GpioMode_Input will be converted
 398          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 399          * which indicates we need additional delay
 400          */
 401
 402         if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
 403                          GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
 404                 dal_ddc_close(ddc);
 405
 406                 return present;
 407         }
 408
 409         /*
 410          * Read GPIO: DP sink is present if both clock and data pins are zero
 411          *
 412          * [W/A] plug-unplug DP cable, sometimes customer board has
 413          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 414          * then monitor can't br light up. Add retry 3 times
 415          * But in real passive dongle, it need additional 3ms to detect
 416          */
 417         do {
 418                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 419                 ASSERT(gpio_result == GPIO_RESULT_OK);
 420                 if (clock_pin)
 421                         udelay(1000);
 422                 else
 423                         break;
 424         } while (retry++ < 3);
 425
 426         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 427
 428         dal_ddc_close(ddc);
 429
 430         return present;
 431 }
 432
 433 /*
 434  * @brief
 435  * Detect output sink type
 436  */
 437 static enum signal_type link_detect_sink(struct dc_link *link,
 438                                          enum dc_detect_reason reason)
 439 {
 440         enum signal_type result;
 441         struct graphics_object_id enc_id;
 442
 443         if (link->is_dig_mapping_flexible)
 444                 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
 445         else
 446                 enc_id = link->link_enc->id;
 447         result = get_basic_signal_type(enc_id, link->link_id);
 448
 449         /* Use basic signal type for link without physical connector. */
 450         if (link->ep_type != DISPLAY_ENDPOINT_PHY)
 451                 return result;
 452
 453         /* Internal digital encoder will detect only dongles
 454          * that require digital signal
 455          */
 456
 457         /* Detection mechanism is different
 458          * for different native connectors.
 459          * LVDS connector supports only LVDS signal;
 460          * PCIE is a bus slot, the actual connector needs to be detected first;
 461          * eDP connector supports only eDP signal;
 462          * HDMI should check straps for audio
 463          */
 464
 465         /* PCIE detects the actual connector on add-on board */
 466         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 467                 /* ZAZTODO implement PCIE add-on card detection */
 468         }
 469
 470         switch (link->link_id.id) {
 471         case CONNECTOR_ID_HDMI_TYPE_A: {
 472                 /* check audio support:
 473                  * if native HDMI is not supported, switch to DVI
 474                  */
 475                 struct audio_support *aud_support =
 476                                         &link->dc->res_pool->audio_support;
 477
 478                 if (!aud_support->hdmi_audio_native)
 479                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 480                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 481         }
 482         break;
 483         case CONNECTOR_ID_DISPLAY_PORT:
 484         case CONNECTOR_ID_USBC: {
 485                 /* DP HPD short pulse. Passive DP dongle will not
 486                  * have short pulse
 487                  */
 488                 if (reason != DETECT_REASON_HPDRX) {
 489                         /* Check whether DP signal detected: if not -
 490                          * we assume signal is DVI; it could be corrected
 491                          * to HDMI after dongle detection
 492                          */
 493                         if (!dm_helpers_is_dp_sink_present(link))
 494                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 495                 }
 496         }
 497         break;
 498         default:
 499         break;
 500         }
 501
 502         return result;
 503 }
 504
 505 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
 506                                                                  struct audio_support *audio_support)
 507 {
 508         enum signal_type signal = SIGNAL_TYPE_NONE;
 509
 510         switch (dongle_type) {
 511         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 512                 if (audio_support->hdmi_audio_on_dongle)
 513                         signal = SIGNAL_TYPE_HDMI_TYPE_A;
 514                 else
 515                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 516                 break;
 517         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 518                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 519                 break;
 520         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 521                 if (audio_support->hdmi_audio_native)
 522                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 523                 else
 524                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 525                 break;
 526         default:
 527                 signal = SIGNAL_TYPE_NONE;
 528                 break;
 529         }
 530
 531         return signal;
 532 }
 533
 534 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
 535                                                     struct display_sink_capability *sink_cap,
 536                                                     struct audio_support *audio_support)
 537 {
 538         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
 539
 540         return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
 541                                                         audio_support);
 542 }
 543
 544 static void link_disconnect_sink(struct dc_link *link)
 545 {
 546         if (link->local_sink) {
 547                 dc_sink_release(link->local_sink);
 548                 link->local_sink = NULL;
 549         }
 550
 551         link->dpcd_sink_count = 0;
 552         //link->dpcd_caps.dpcd_rev.raw = 0;
 553 }
 554
 555 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 556 {
 557         dc_sink_release(link->local_sink);
 558         link->local_sink = prev_sink;
 559 }
 560
 561 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 562 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
 563 {
 564         bool ret = false;
 565
 566         switch (signal) {
 567         case SIGNAL_TYPE_DISPLAY_PORT:
 568         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 569                 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
 570                 break;
 571         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 572         case SIGNAL_TYPE_DVI_DUAL_LINK:
 573         case SIGNAL_TYPE_HDMI_TYPE_A:
 574         /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
 575          * we can poll for bksv but some displays have an issue with this. Since its so rare
 576          * for a display to not be 1.4 capable, this assumtion is ok
 577          */
 578                 ret = true;
 579                 break;
 580         default:
 581                 break;
 582         }
 583         return ret;
 584 }
 585
 586 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
 587 {
 588         bool ret = false;
 589
 590         switch (signal) {
 591         case SIGNAL_TYPE_DISPLAY_PORT:
 592         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 593                 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
 594                                 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
 595                                 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
 596                 break;
 597         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 598         case SIGNAL_TYPE_DVI_DUAL_LINK:
 599         case SIGNAL_TYPE_HDMI_TYPE_A:
 600                 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
 601                 break;
 602         default:
 603                 break;
 604         }
 605
 606         return ret;
 607 }
 608
 609 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
 610 {
 611         struct hdcp_protection_message msg22;
 612         struct hdcp_protection_message msg14;
 613
 614         memset(&msg22, 0, sizeof(struct hdcp_protection_message));
 615         memset(&msg14, 0, sizeof(struct hdcp_protection_message));
 616         memset(link->hdcp_caps.rx_caps.raw, 0,
 617                 sizeof(link->hdcp_caps.rx_caps.raw));
 618
 619         if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 620                         link->ddc->transaction_type ==
 621                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
 622                         link->connector_signal == SIGNAL_TYPE_EDP) {
 623                 msg22.data = link->hdcp_caps.rx_caps.raw;
 624                 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
 625                 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
 626         } else {
 627                 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
 628                 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
 629                 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
 630         }
 631         msg22.version = HDCP_VERSION_22;
 632         msg22.link = HDCP_LINK_PRIMARY;
 633         msg22.max_retries = 5;
 634         dc_process_hdcp_msg(signal, link, &msg22);
 635
 636         if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 637                 msg14.data = &link->hdcp_caps.bcaps.raw;
 638                 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
 639                 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
 640                 msg14.version = HDCP_VERSION_14;
 641                 msg14.link = HDCP_LINK_PRIMARY;
 642                 msg14.max_retries = 5;
 643
 644                 dc_process_hdcp_msg(signal, link, &msg14);
 645         }
 646
 647 }
 648 #endif
 649
 650 static void read_current_link_settings_on_detect(struct dc_link *link)
 651 {
 652         union lane_count_set lane_count_set = {0};
 653         uint8_t link_bw_set;
 654         uint8_t link_rate_set;
 655         uint32_t read_dpcd_retry_cnt = 10;
 656         enum dc_status status = DC_ERROR_UNEXPECTED;
 657         int i;
 658         union max_down_spread max_down_spread = {0};
 659
 660         // Read DPCD 00101h to find out the number of lanes currently set
 661         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 662                 status = core_link_read_dpcd(link,
 663                                              DP_LANE_COUNT_SET,
 664                                              &lane_count_set.raw,
 665                                              sizeof(lane_count_set));
 666                 /* First DPCD read after VDD ON can fail if the particular board
 667                  * does not have HPD pin wired correctly. So if DPCD read fails,
 668                  * which it should never happen, retry a few times. Target worst
 669                  * case scenario of 80 ms.
 670                  */
 671                 if (status == DC_OK) {
 672                         link->cur_link_settings.lane_count =
 673                                         lane_count_set.bits.LANE_COUNT_SET;
 674                         break;
 675                 }
 676
 677                 msleep(8);
 678         }
 679
 680         // Read DPCD 00100h to find if standard link rates are set
 681         core_link_read_dpcd(link, DP_LINK_BW_SET,
 682                             &link_bw_set, sizeof(link_bw_set));
 683
 684         if (link_bw_set == 0) {
 685                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 686                         /* If standard link rates are not being used,
 687                          * Read DPCD 00115h to find the edp link rate set used
 688                          */
 689                         core_link_read_dpcd(link, DP_LINK_RATE_SET,
 690                                             &link_rate_set, sizeof(link_rate_set));
 691
 692                         // edp_supported_link_rates_count = 0 for DP
 693                         if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 694                                 link->cur_link_settings.link_rate =
 695                                         link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 696                                 link->cur_link_settings.link_rate_set = link_rate_set;
 697                                 link->cur_link_settings.use_link_rate_set = true;
 698                         }
 699                 } else {
 700                         // Link Rate not found. Seamless boot may not work.
 701                         ASSERT(false);
 702                 }
 703         } else {
 704                 link->cur_link_settings.link_rate = link_bw_set;
 705                 link->cur_link_settings.use_link_rate_set = false;
 706         }
 707         // Read DPCD 00003h to find the max down spread.
 708         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 709                             &max_down_spread.raw, sizeof(max_down_spread));
 710         link->cur_link_settings.link_spread =
 711                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 712                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 713 }
 714
 715 static bool detect_dp(struct dc_link *link,
 716                       struct display_sink_capability *sink_caps,
 717                       enum dc_detect_reason reason)
 718 {
 719         struct audio_support *audio_support = &link->dc->res_pool->audio_support;
 720
 721         sink_caps->signal = link_detect_sink(link, reason);
 722         sink_caps->transaction_type =
 723                 get_ddc_transaction_type(sink_caps->signal);
 724
 725         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 726                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 727                 if (!detect_dp_sink_caps(link))
 728                         return false;
 729
 730                 if (is_dp_branch_device(link))
 731                         /* DP SST branch */
 732                         link->type = dc_connection_sst_branch;
 733         } else {
 734                 /* DP passive dongles */
 735                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 736                                                                 sink_caps,
 737                                                                 audio_support);
 738                 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
 739                 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one;
 740                 link->dpcd_caps.dpcd_rev.raw = 0;
 741         }
 742
 743         return true;
 744 }
 745
 746 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 747 {
 748         if (old_edid->length != new_edid->length)
 749                 return false;
 750
 751         if (new_edid->length == 0)
 752                 return false;
 753
 754         return (memcmp(old_edid->raw_edid,
 755                        new_edid->raw_edid, new_edid->length) == 0);
 756 }
 757
 758 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
 759 {
 760         /**
 761          * something is terribly wrong if time out is > 200ms. (5Hz)
 762          * 500 microseconds * 400 tries us 200 ms
 763          **/
 764         unsigned int sleep_time_in_microseconds = 500;
 765         unsigned int tries_allowed = 400;
 766         bool is_in_alt_mode;
 767         unsigned long long enter_timestamp;
 768         unsigned long long finish_timestamp;
 769         unsigned long long time_taken_in_ns;
 770         int tries_taken;
 771
 772         DC_LOGGER_INIT(link->ctx->logger);
 773
 774         if (!link->link_enc->funcs->is_in_alt_mode)
 775                 return true;
 776
 777         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 778         DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 779
 780         if (is_in_alt_mode)
 781                 return true;
 782
 783         enter_timestamp = dm_get_timestamp(link->ctx);
 784
 785         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 786                 udelay(sleep_time_in_microseconds);
 787                 /* ask the link if alt mode is enabled, if so return ok */
 788                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 789                         finish_timestamp = dm_get_timestamp(link->ctx);
 790                         time_taken_in_ns =
 791                                 dm_get_elapse_time_in_ns(link->ctx,
 792                                                          finish_timestamp,
 793                                                          enter_timestamp);
 794                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 795                                        div_u64(time_taken_in_ns, 1000000));
 796                         return true;
 797                 }
 798         }
 799         finish_timestamp = dm_get_timestamp(link->ctx);
 800         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 801                                                     enter_timestamp);
 802         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 803                        div_u64(time_taken_in_ns, 1000000));
 804         return false;
 805 }
 806
 807 static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
 808 {
 809         /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
 810          * reports DSC support.
 811          */
 812         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
 813                         link->type == dc_connection_mst_branch &&
 814                         link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
 815                         link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 &&
 816                         link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
 817                         !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
 818                 link->wa_flags.dpia_mst_dsc_always_on = true;
 819 }
 820
 821 static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
 822 {
 823         /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */
 824         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
 825                 link->wa_flags.dpia_mst_dsc_always_on = false;
 826 }
 827
 828 static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason)
 829 {
 830         DC_LOGGER_INIT(link->ctx->logger);
 831
 832         LINK_INFO("link=%d, mst branch is now Connected\n",
 833                   link->link_index);
 834
 835         apply_dpia_mst_dsc_always_on_wa(link);
 836         link->type = dc_connection_mst_branch;
 837         dm_helpers_dp_update_branch_info(link->ctx, link);
 838         if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
 839                         link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) {
 840                 link_disconnect_sink(link);
 841         } else {
 842                 link->type = dc_connection_sst_branch;
 843         }
 844
 845         return link->type == dc_connection_mst_branch;
 846 }
 847
 848 bool reset_cur_dp_mst_topology(struct dc_link *link)
 849 {
 850         bool result = false;
 851         DC_LOGGER_INIT(link->ctx->logger);
 852
 853         LINK_INFO("link=%d, mst branch is now Disconnected\n",
 854                   link->link_index);
 855
 856         revert_dpia_mst_dsc_always_on_wa(link);
 857         result = dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 858
 859         link->mst_stream_alloc_table.stream_count = 0;
 860         memset(link->mst_stream_alloc_table.stream_allocations,
 861                         0,
 862                         sizeof(link->mst_stream_alloc_table.stream_allocations));
 863         return result;
 864 }
 865
 866 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,
 867                 enum dc_detect_reason reason)
 868 {
 869         int i;
 870         bool can_apply_seamless_boot = false;
 871
 872         for (i = 0; i < dc->current_state->stream_count; i++) {
 873                 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
 874                         can_apply_seamless_boot = true;
 875                         break;
 876                 }
 877         }
 878
 879         return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT;
 880 }
 881
 882 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc)
 883 {
 884         dc_z10_restore(dc);
 885         clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
 886 }
 887
 888 static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc)
 889 {
 890         clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
 891 }
 892
 893 static void set_all_streams_dpms_off_for_link(struct dc_link *link)
 894 {
 895         int i;
 896         struct pipe_ctx *pipe_ctx;
 897         struct dc_stream_update stream_update;
 898         bool dpms_off = true;
 899         struct link_resource link_res = {0};
 900
 901         memset(&stream_update, 0, sizeof(stream_update));
 902         stream_update.dpms_off = &dpms_off;
 903
 904         for (i = 0; i < MAX_PIPES; i++) {
 905                 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
 906                 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
 907                                 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe) {
 908                         stream_update.stream = pipe_ctx->stream;
 909                         dc_commit_updates_for_stream(link->ctx->dc, NULL, 0,
 910                                         pipe_ctx->stream, &stream_update,
 911                                         link->ctx->dc->current_state);
 912                 }
 913         }
 914
 915         /* link can be also enabled by vbios. In this case it is not recorded
 916          * in pipe_ctx. Disable link phy here to make sure it is completely off
 917          */
 918         dp_disable_link_phy(link, &link_res, link->connector_signal);
 919 }
 920
 921 static void verify_link_capability_destructive(struct dc_link *link,
 922                 struct dc_sink *sink,
 923                 enum dc_detect_reason reason)
 924 {
 925         bool should_prepare_phy_clocks =
 926                         should_prepare_phy_clocks_for_link_verification(link->dc, reason);
 927
 928         if (should_prepare_phy_clocks)
 929                 prepare_phy_clocks_for_destructive_link_verification(link->dc);
 930
 931         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 932                 struct dc_link_settings known_limit_link_setting =
 933                                 dp_get_max_link_cap(link);
 934                 set_all_streams_dpms_off_for_link(link);
 935                 dp_verify_link_cap_with_retries(
 936                                 link, &known_limit_link_setting,
 937                                 LINK_TRAINING_MAX_VERIFY_RETRY);
 938         } else {
 939                 ASSERT(0);
 940         }
 941
 942         if (should_prepare_phy_clocks)
 943                 restore_phy_clocks_for_destructive_link_verification(link->dc);
 944 }
 945
 946 static void verify_link_capability_non_destructive(struct dc_link *link)
 947 {
 948         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 949                 if (dc_is_embedded_signal(link->local_sink->sink_signal) ||
 950                                 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
 951                         /* TODO - should we check link encoder's max link caps here?
 952                          * How do we know which link encoder to check from?
 953                          */
 954                         link->verified_link_cap = link->reported_link_cap;
 955                 else
 956                         link->verified_link_cap = dp_get_max_link_cap(link);
 957         }
 958 }
 959
 960 static bool should_verify_link_capability_destructively(struct dc_link *link,
 961                 enum dc_detect_reason reason)
 962 {
 963         bool destrictive = false;
 964         struct dc_link_settings max_link_cap;
 965         bool is_link_enc_unavailable = link->link_enc &&
 966                         link->dc->res_pool->funcs->link_encs_assign &&
 967                         !link_enc_cfg_is_link_enc_avail(
 968                                         link->ctx->dc,
 969                                         link->link_enc->preferred_engine,
 970                                         link);
 971
 972         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 973                 max_link_cap = dp_get_max_link_cap(link);
 974                 destrictive = true;
 975
 976                 if (link->dc->debug.skip_detection_link_training ||
 977                                 dc_is_embedded_signal(link->local_sink->sink_signal) ||
 978                                 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
 979                         destrictive = false;
 980                 } else if (dp_get_link_encoding_format(&max_link_cap) ==
 981                                 DP_8b_10b_ENCODING) {
 982                         if (link->dpcd_caps.is_mst_capable ||
 983                                         is_link_enc_unavailable) {
 984                                 destrictive = false;
 985                         }
 986                 }
 987         }
 988
 989         return destrictive;
 990 }
 991
 992 static void verify_link_capability(struct dc_link *link, struct dc_sink *sink,
 993                 enum dc_detect_reason reason)
 994 {
 995         if (should_verify_link_capability_destructively(link, reason))
 996                 verify_link_capability_destructive(link, sink, reason);
 997         else
 998                 verify_link_capability_non_destructive(link);
 999 }
1000
1001
1002 /**
1003  * detect_link_and_local_sink() - Detect if a sink is attached to a given link
1004  *
1005  * link->local_sink is created or destroyed as needed.
1006  *
1007  * This does not create remote sinks.
1008  */
1009 static bool detect_link_and_local_sink(struct dc_link *link,
1010                                   enum dc_detect_reason reason)
1011 {
1012         struct dc_sink_init_data sink_init_data = { 0 };
1013         struct display_sink_capability sink_caps = { 0 };
1014         uint32_t i;
1015         bool converter_disable_audio = false;
1016         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
1017         bool same_edid = false;
1018         enum dc_edid_status edid_status;
1019         struct dc_context *dc_ctx = link->ctx;
1020         struct dc *dc = dc_ctx->dc;
1021         struct dc_sink *sink = NULL;
1022         struct dc_sink *prev_sink = NULL;
1023         struct dpcd_caps prev_dpcd_caps;
1024         enum dc_connection_type new_connection_type = dc_connection_none;
1025         const uint32_t post_oui_delay = 30; // 30ms
1026
1027         DC_LOGGER_INIT(link->ctx->logger);
1028
1029         if (dc_is_virtual_signal(link->connector_signal))
1030                 return false;
1031
1032         if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
1033                 link->connector_signal == SIGNAL_TYPE_EDP) &&
1034                 (!link->dc->config.allow_edp_hotplug_detection)) &&
1035                 link->local_sink) {
1036                 // need to re-write OUI and brightness in resume case
1037                 if (link->connector_signal == SIGNAL_TYPE_EDP &&
1038                         (link->dpcd_sink_ext_caps.bits.oled == 1)) {
1039                         dpcd_set_source_specific_data(link);
1040                         msleep(post_oui_delay);
1041                         dc_link_set_default_brightness_aux(link);
1042                         //TODO: use cached
1043                 }
1044
1045                 return true;
1046         }
1047
1048         if (!dc_link_detect_sink(link, &new_connection_type)) {
1049                 BREAK_TO_DEBUGGER();
1050                 return false;
1051         }
1052
1053         prev_sink = link->local_sink;
1054         if (prev_sink) {
1055                 dc_sink_retain(prev_sink);
1056                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
1057         }
1058
1059         link_disconnect_sink(link);
1060         if (new_connection_type != dc_connection_none) {
1061                 link->type = new_connection_type;
1062                 link->link_state_valid = false;
1063
1064                 /* From Disconnected-to-Connected. */
1065                 switch (link->connector_signal) {
1066                 case SIGNAL_TYPE_HDMI_TYPE_A: {
1067                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1068                         if (aud_support->hdmi_audio_native)
1069                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1070                         else
1071                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1072                         break;
1073                 }
1074
1075                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1076                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1077                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1078                         break;
1079                 }
1080
1081                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
1082                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1083                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1084                         break;
1085                 }
1086
1087                 case SIGNAL_TYPE_LVDS: {
1088                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1089                         sink_caps.signal = SIGNAL_TYPE_LVDS;
1090                         break;
1091                 }
1092
1093                 case SIGNAL_TYPE_EDP: {
1094                         read_current_link_settings_on_detect(link);
1095
1096                         detect_edp_sink_caps(link);
1097                         read_current_link_settings_on_detect(link);
1098
1099                         /* Disable power sequence on MIPI panel + converter
1100                          */
1101                         if (dc->config.enable_mipi_converter_optimization &&
1102                                 dc_ctx->dce_version == DCN_VERSION_3_01 &&
1103                                 link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 &&
1104                                 memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580,
1105                                         sizeof(link->dpcd_caps.branch_dev_name)) == 0) {
1106                                 dc->config.edp_no_power_sequencing = true;
1107
1108                                 if (!link->dpcd_caps.set_power_state_capable_edp)
1109                                         link->wa_flags.dp_keep_receiver_powered = true;
1110                         }
1111
1112                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1113                         sink_caps.signal = SIGNAL_TYPE_EDP;
1114                         break;
1115                 }
1116
1117                 case SIGNAL_TYPE_DISPLAY_PORT: {
1118                         /* wa HPD high coming too early*/
1119                         if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
1120                             link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
1121                                 /* if alt mode times out, return false */
1122                                 if (!wait_for_entering_dp_alt_mode(link))
1123                                         return false;
1124                         }
1125
1126                         if (!detect_dp(link, &sink_caps, reason)) {
1127                                 if (prev_sink)
1128                                         dc_sink_release(prev_sink);
1129                                 return false;
1130                         }
1131
1132                         /* Active SST downstream branch device unplug*/
1133                         if (link->type == dc_connection_sst_branch &&
1134                             link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
1135                                 if (prev_sink)
1136                                         /* Downstream unplug */
1137                                         dc_sink_release(prev_sink);
1138                                 return true;
1139                         }
1140
1141                         /* disable audio for non DP to HDMI active sst converter */
1142                         if (link->type == dc_connection_sst_branch &&
1143                                         is_dp_active_dongle(link) &&
1144                                         (link->dpcd_caps.dongle_type !=
1145                                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER))
1146                                 converter_disable_audio = true;
1147                         break;
1148                 }
1149
1150                 default:
1151                         DC_ERROR("Invalid connector type! signal:%d\n",
1152                                  link->connector_signal);
1153                         if (prev_sink)
1154                                 dc_sink_release(prev_sink);
1155                         return false;
1156                 } /* switch() */
1157
1158                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1159                         link->dpcd_sink_count =
1160                                 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1161                 else
1162                         link->dpcd_sink_count = 1;
1163
1164                 dal_ddc_service_set_transaction_type(link->ddc,
1165                                                      sink_caps.transaction_type);
1166
1167                 link->aux_mode =
1168                         dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1169
1170                 sink_init_data.link = link;
1171                 sink_init_data.sink_signal = sink_caps.signal;
1172
1173                 sink = dc_sink_create(&sink_init_data);
1174                 if (!sink) {
1175                         DC_ERROR("Failed to create sink!\n");
1176                         if (prev_sink)
1177                                 dc_sink_release(prev_sink);
1178                         return false;
1179                 }
1180
1181                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1182                 sink->converter_disable_audio = converter_disable_audio;
1183
1184                 /* dc_sink_create returns a new reference */
1185                 link->local_sink = sink;
1186
1187                 edid_status = dm_helpers_read_local_edid(link->ctx,
1188                                                          link, sink);
1189
1190                 switch (edid_status) {
1191                 case EDID_BAD_CHECKSUM:
1192                         DC_LOG_ERROR("EDID checksum invalid.\n");
1193                         break;
1194                 case EDID_PARTIAL_VALID:
1195                         DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n");
1196                         break;
1197                 case EDID_NO_RESPONSE:
1198                         DC_LOG_ERROR("No EDID read.\n");
1199                         /*
1200                          * Abort detection for non-DP connectors if we have
1201                          * no EDID
1202                          *
1203                          * DP needs to report as connected if HDP is high
1204                          * even if we have no EDID in order to go to
1205                          * fail-safe mode
1206                          */
1207                         if (dc_is_hdmi_signal(link->connector_signal) ||
1208                             dc_is_dvi_signal(link->connector_signal)) {
1209                                 if (prev_sink)
1210                                         dc_sink_release(prev_sink);
1211
1212                                 return false;
1213                         }
1214
1215                         if (link->type == dc_connection_sst_branch &&
1216                                         link->dpcd_caps.dongle_type ==
1217                                                 DISPLAY_DONGLE_DP_VGA_CONVERTER &&
1218                                         reason == DETECT_REASON_HPDRX) {
1219                                 /* Abort detection for DP-VGA adapters when EDID
1220                                  * can't be read and detection reason is VGA-side
1221                                  * hotplug
1222                                  */
1223                                 if (prev_sink)
1224                                         dc_sink_release(prev_sink);
1225                                 link_disconnect_sink(link);
1226
1227                                 return true;
1228                         }
1229
1230                         break;
1231                 default:
1232                         break;
1233                 }
1234
1235                 // Check if edid is the same
1236                 if ((prev_sink) &&
1237                     (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1238                         same_edid = is_same_edid(&prev_sink->dc_edid,
1239                                                  &sink->dc_edid);
1240
1241                 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1242                         link->ctx->dc->debug.hdmi20_disable = true;
1243
1244                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1245                     sink_caps.transaction_type ==
1246                     DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1247                         /*
1248                          * TODO debug why Dell 2413 doesn't like
1249                          *  two link trainings
1250                          */
1251 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1252                         query_hdcp_capability(sink->sink_signal, link);
1253 #endif
1254                 } else {
1255                         // If edid is the same, then discard new sink and revert back to original sink
1256                         if (same_edid) {
1257                                 link_disconnect_remap(prev_sink, link);
1258                                 sink = prev_sink;
1259                                 prev_sink = NULL;
1260                         }
1261 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1262                         query_hdcp_capability(sink->sink_signal, link);
1263 #endif
1264                 }
1265
1266                 /* HDMI-DVI Dongle */
1267                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1268                     !sink->edid_caps.edid_hdmi)
1269                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1270
1271                 if (link->local_sink && dc_is_dp_signal(sink_caps.signal))
1272                         dp_trace_init(link);
1273
1274                 /* Connectivity log: detection */
1275                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1276                         CONN_DATA_DETECT(link,
1277                                          &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1278                                          DC_EDID_BLOCK_SIZE,
1279                                          "%s: [Block %d] ", sink->edid_caps.display_name, i);
1280                 }
1281
1282                 DC_LOG_DETECTION_EDID_PARSER("%s: "
1283                         "manufacturer_id = %X, "
1284                         "product_id = %X, "
1285                         "serial_number = %X, "
1286                         "manufacture_week = %d, "
1287                         "manufacture_year = %d, "
1288                         "display_name = %s, "
1289                         "speaker_flag = %d, "
1290                         "audio_mode_count = %d\n",
1291                         __func__,
1292                         sink->edid_caps.manufacturer_id,
1293                         sink->edid_caps.product_id,
1294                         sink->edid_caps.serial_number,
1295                         sink->edid_caps.manufacture_week,
1296                         sink->edid_caps.manufacture_year,
1297                         sink->edid_caps.display_name,
1298                         sink->edid_caps.speaker_flags,
1299                         sink->edid_caps.audio_mode_count);
1300
1301                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1302                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1303                                 "format_code = %d, "
1304                                 "channel_count = %d, "
1305                                 "sample_rate = %d, "
1306                                 "sample_size = %d\n",
1307                                 __func__,
1308                                 i,
1309                                 sink->edid_caps.audio_modes[i].format_code,
1310                                 sink->edid_caps.audio_modes[i].channel_count,
1311                                 sink->edid_caps.audio_modes[i].sample_rate,
1312                                 sink->edid_caps.audio_modes[i].sample_size);
1313                 }
1314         } else {
1315                 /* From Connected-to-Disconnected. */
1316                 link->type = dc_connection_none;
1317                 sink_caps.signal = SIGNAL_TYPE_NONE;
1318                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1319                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1320                  *  the dongle is still there and limits the number of modes we can emulate.
1321                  *  Clear dongle_max_pix_clk on disconnect to fix this
1322                  */
1323                 link->dongle_max_pix_clk = 0;
1324
1325                 dc_link_clear_dprx_states(link);
1326                 dp_trace_reset(link);
1327         }
1328
1329         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1330                   link->link_index, sink,
1331                   (sink_caps.signal ==
1332                    SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1333                   prev_sink, same_edid);
1334
1335         if (prev_sink)
1336                 dc_sink_release(prev_sink);
1337
1338         return true;
1339 }
1340
1341 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1342 {
1343         bool is_local_sink_detect_success;
1344         bool is_delegated_to_mst_top_mgr = false;
1345         enum dc_connection_type pre_link_type = link->type;
1346
1347         is_local_sink_detect_success = detect_link_and_local_sink(link, reason);
1348
1349         if (is_local_sink_detect_success && link->local_sink)
1350                 verify_link_capability(link, link->local_sink, reason);
1351
1352         if (is_local_sink_detect_success && link->local_sink &&
1353                         dc_is_dp_signal(link->local_sink->sink_signal) &&
1354                         link->dpcd_caps.is_mst_capable)
1355                 is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason);
1356
1357         if (is_local_sink_detect_success &&
1358                         pre_link_type == dc_connection_mst_branch &&
1359                         link->type != dc_connection_mst_branch)
1360                 is_delegated_to_mst_top_mgr = reset_cur_dp_mst_topology(link);
1361
1362         return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr;
1363 }
1364
1365 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1366 {
1367         uint32_t state;
1368
1369         dal_gpio_lock_pin(dc_link->hpd_gpio);
1370         dal_gpio_get_value(dc_link->hpd_gpio, &state);
1371         dal_gpio_unlock_pin(dc_link->hpd_gpio);
1372
1373         return state;
1374 }
1375
1376 static enum hpd_source_id get_hpd_line(struct dc_link *link)
1377 {
1378         struct gpio *hpd;
1379         enum hpd_source_id hpd_id;
1380
1381         hpd_id = HPD_SOURCEID_UNKNOWN;
1382
1383         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1384                            link->ctx->gpio_service);
1385
1386         if (hpd) {
1387                 switch (dal_irq_get_source(hpd)) {
1388                 case DC_IRQ_SOURCE_HPD1:
1389                         hpd_id = HPD_SOURCEID1;
1390                 break;
1391                 case DC_IRQ_SOURCE_HPD2:
1392                         hpd_id = HPD_SOURCEID2;
1393                 break;
1394                 case DC_IRQ_SOURCE_HPD3:
1395                         hpd_id = HPD_SOURCEID3;
1396                 break;
1397                 case DC_IRQ_SOURCE_HPD4:
1398                         hpd_id = HPD_SOURCEID4;
1399                 break;
1400                 case DC_IRQ_SOURCE_HPD5:
1401                         hpd_id = HPD_SOURCEID5;
1402                 break;
1403                 case DC_IRQ_SOURCE_HPD6:
1404                         hpd_id = HPD_SOURCEID6;
1405                 break;
1406                 default:
1407                         BREAK_TO_DEBUGGER();
1408                 break;
1409                 }
1410
1411                 dal_gpio_destroy_irq(&hpd);
1412         }
1413
1414         return hpd_id;
1415 }
1416
1417 static enum channel_id get_ddc_line(struct dc_link *link)
1418 {
1419         struct ddc *ddc;
1420         enum channel_id channel;
1421
1422         channel = CHANNEL_ID_UNKNOWN;
1423
1424         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1425
1426         if (ddc) {
1427                 switch (dal_ddc_get_line(ddc)) {
1428                 case GPIO_DDC_LINE_DDC1:
1429                         channel = CHANNEL_ID_DDC1;
1430                         break;
1431                 case GPIO_DDC_LINE_DDC2:
1432                         channel = CHANNEL_ID_DDC2;
1433                         break;
1434                 case GPIO_DDC_LINE_DDC3:
1435                         channel = CHANNEL_ID_DDC3;
1436                         break;
1437                 case GPIO_DDC_LINE_DDC4:
1438                         channel = CHANNEL_ID_DDC4;
1439                         break;
1440                 case GPIO_DDC_LINE_DDC5:
1441                         channel = CHANNEL_ID_DDC5;
1442                         break;
1443                 case GPIO_DDC_LINE_DDC6:
1444                         channel = CHANNEL_ID_DDC6;
1445                         break;
1446                 case GPIO_DDC_LINE_DDC_VGA:
1447                         channel = CHANNEL_ID_DDC_VGA;
1448                         break;
1449                 case GPIO_DDC_LINE_I2C_PAD:
1450                         channel = CHANNEL_ID_I2C_PAD;
1451                         break;
1452                 default:
1453                         BREAK_TO_DEBUGGER();
1454                         break;
1455                 }
1456         }
1457
1458         return channel;
1459 }
1460
1461 static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1462 {
1463         switch (encoder.id) {
1464         case ENCODER_ID_INTERNAL_UNIPHY:
1465                 switch (encoder.enum_id) {
1466                 case ENUM_ID_1:
1467                         return TRANSMITTER_UNIPHY_A;
1468                 case ENUM_ID_2:
1469                         return TRANSMITTER_UNIPHY_B;
1470                 default:
1471                         return TRANSMITTER_UNKNOWN;
1472                 }
1473         break;
1474         case ENCODER_ID_INTERNAL_UNIPHY1:
1475                 switch (encoder.enum_id) {
1476                 case ENUM_ID_1:
1477                         return TRANSMITTER_UNIPHY_C;
1478                 case ENUM_ID_2:
1479                         return TRANSMITTER_UNIPHY_D;
1480                 default:
1481                         return TRANSMITTER_UNKNOWN;
1482                 }
1483         break;
1484         case ENCODER_ID_INTERNAL_UNIPHY2:
1485                 switch (encoder.enum_id) {
1486                 case ENUM_ID_1:
1487                         return TRANSMITTER_UNIPHY_E;
1488                 case ENUM_ID_2:
1489                         return TRANSMITTER_UNIPHY_F;
1490                 default:
1491                         return TRANSMITTER_UNKNOWN;
1492                 }
1493         break;
1494         case ENCODER_ID_INTERNAL_UNIPHY3:
1495                 switch (encoder.enum_id) {
1496                 case ENUM_ID_1:
1497                         return TRANSMITTER_UNIPHY_G;
1498                 default:
1499                         return TRANSMITTER_UNKNOWN;
1500                 }
1501         break;
1502         case ENCODER_ID_EXTERNAL_NUTMEG:
1503                 switch (encoder.enum_id) {
1504                 case ENUM_ID_1:
1505                         return TRANSMITTER_NUTMEG_CRT;
1506                 default:
1507                         return TRANSMITTER_UNKNOWN;
1508                 }
1509         break;
1510         case ENCODER_ID_EXTERNAL_TRAVIS:
1511                 switch (encoder.enum_id) {
1512                 case ENUM_ID_1:
1513                         return TRANSMITTER_TRAVIS_CRT;
1514                 case ENUM_ID_2:
1515                         return TRANSMITTER_TRAVIS_LCD;
1516                 default:
1517                         return TRANSMITTER_UNKNOWN;
1518                 }
1519         break;
1520         default:
1521                 return TRANSMITTER_UNKNOWN;
1522         }
1523 }
1524
1525 static bool dc_link_construct_legacy(struct dc_link *link,
1526                                      const struct link_init_data *init_params)
1527 {
1528         uint8_t i;
1529         struct ddc_service_init_data ddc_service_init_data = { 0 };
1530         struct dc_context *dc_ctx = init_params->ctx;
1531         struct encoder_init_data enc_init_data = { 0 };
1532         struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1533         struct integrated_info *info;
1534         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1535         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1536         struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
1537
1538         DC_LOGGER_INIT(dc_ctx->logger);
1539
1540         info = kzalloc(sizeof(*info), GFP_KERNEL);
1541         if (!info)
1542                 goto create_fail;
1543
1544         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1545         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1546
1547         link->link_status.dpcd_caps = &link->dpcd_caps;
1548
1549         link->dc = init_params->dc;
1550         link->ctx = dc_ctx;
1551         link->link_index = init_params->link_index;
1552
1553         memset(&link->preferred_training_settings, 0,
1554                sizeof(struct dc_link_training_overrides));
1555         memset(&link->preferred_link_setting, 0,
1556                sizeof(struct dc_link_settings));
1557
1558         link->link_id =
1559                 bios->funcs->get_connector_id(bios, init_params->connector_index);
1560
1561         link->ep_type = DISPLAY_ENDPOINT_PHY;
1562
1563         DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id);
1564
1565         if (bios->funcs->get_disp_connector_caps_info) {
1566                 bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
1567                 link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
1568                 DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
1569         }
1570
1571         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1572                 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1573                                      __func__, init_params->connector_index,
1574                                      link->link_id.type, OBJECT_TYPE_CONNECTOR);
1575                 goto create_fail;
1576         }
1577
1578         if (link->dc->res_pool->funcs->link_init)
1579                 link->dc->res_pool->funcs->link_init(link);
1580
1581         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1582                                       link->ctx->gpio_service);
1583
1584         if (link->hpd_gpio) {
1585                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1586                 dal_gpio_unlock_pin(link->hpd_gpio);
1587                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1588
1589                 DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id);
1590                 DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en);
1591         }
1592
1593         switch (link->link_id.id) {
1594         case CONNECTOR_ID_HDMI_TYPE_A:
1595                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1596
1597                 break;
1598         case CONNECTOR_ID_SINGLE_LINK_DVID:
1599         case CONNECTOR_ID_SINGLE_LINK_DVII:
1600                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1601                 break;
1602         case CONNECTOR_ID_DUAL_LINK_DVID:
1603         case CONNECTOR_ID_DUAL_LINK_DVII:
1604                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1605                 break;
1606         case CONNECTOR_ID_DISPLAY_PORT:
1607         case CONNECTOR_ID_USBC:
1608                 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1609
1610                 if (link->hpd_gpio)
1611                         link->irq_source_hpd_rx =
1612                                         dal_irq_get_rx_source(link->hpd_gpio);
1613
1614                 break;
1615         case CONNECTOR_ID_EDP:
1616                 link->connector_signal = SIGNAL_TYPE_EDP;
1617
1618                 if (link->hpd_gpio) {
1619                         if (!link->dc->config.allow_edp_hotplug_detection)
1620                                 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1621
1622                         switch (link->dc->config.allow_edp_hotplug_detection) {
1623                         case 1: // only the 1st eDP handles hotplug
1624                                 if (link->link_index == 0)
1625                                         link->irq_source_hpd_rx =
1626                                                 dal_irq_get_rx_source(link->hpd_gpio);
1627                                 else
1628                                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1629                                 break;
1630                         case 2: // only the 2nd eDP handles hotplug
1631                                 if (link->link_index == 1)
1632                                         link->irq_source_hpd_rx =
1633                                                 dal_irq_get_rx_source(link->hpd_gpio);
1634                                 else
1635                                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1636                                 break;
1637                         default:
1638                                 break;
1639                         }
1640                 }
1641
1642                 break;
1643         case CONNECTOR_ID_LVDS:
1644                 link->connector_signal = SIGNAL_TYPE_LVDS;
1645                 break;
1646         default:
1647                 DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1648                                link->link_id.id);
1649                 goto create_fail;
1650         }
1651
1652         /* TODO: #DAL3 Implement id to str function.*/
1653         LINK_INFO("Connector[%d] description:"
1654                   "signal %d\n",
1655                   init_params->connector_index,
1656                   link->connector_signal);
1657
1658         ddc_service_init_data.ctx = link->ctx;
1659         ddc_service_init_data.id = link->link_id;
1660         ddc_service_init_data.link = link;
1661         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1662
1663         if (!link->ddc) {
1664                 DC_ERROR("Failed to create ddc_service!\n");
1665                 goto ddc_create_fail;
1666         }
1667
1668         if (!link->ddc->ddc_pin) {
1669                 DC_ERROR("Failed to get I2C info for connector!\n");
1670                 goto ddc_create_fail;
1671         }
1672
1673         link->ddc_hw_inst =
1674                 dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1675
1676
1677         if (link->dc->res_pool->funcs->panel_cntl_create &&
1678                 (link->link_id.id == CONNECTOR_ID_EDP ||
1679                         link->link_id.id == CONNECTOR_ID_LVDS)) {
1680                 panel_cntl_init_data.ctx = dc_ctx;
1681                 panel_cntl_init_data.inst =
1682                         panel_cntl_init_data.ctx->dc_edp_id_count;
1683                 link->panel_cntl =
1684                         link->dc->res_pool->funcs->panel_cntl_create(
1685                                                                 &panel_cntl_init_data);
1686                 panel_cntl_init_data.ctx->dc_edp_id_count++;
1687
1688                 if (link->panel_cntl == NULL) {
1689                         DC_ERROR("Failed to create link panel_cntl!\n");
1690                         goto panel_cntl_create_fail;
1691                 }
1692         }
1693
1694         enc_init_data.ctx = dc_ctx;
1695         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1696                               &enc_init_data.encoder);
1697         enc_init_data.connector = link->link_id;
1698         enc_init_data.channel = get_ddc_line(link);
1699         enc_init_data.hpd_source = get_hpd_line(link);
1700
1701         link->hpd_src = enc_init_data.hpd_source;
1702
1703         enc_init_data.transmitter =
1704                 translate_encoder_to_transmitter(enc_init_data.encoder);
1705         link->link_enc =
1706                 link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data);
1707
1708         if (!link->link_enc) {
1709                 DC_ERROR("Failed to create link encoder!\n");
1710                 goto link_enc_create_fail;
1711         }
1712
1713         DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C);
1714         DC_LOG_DC("BIOS object table - IS_DP2_CAPABLE: %d", link->link_enc->features.flags.bits.IS_DP2_CAPABLE);
1715
1716         /* Update link encoder tracking variables. These are used for the dynamic
1717          * assignment of link encoders to streams.
1718          */
1719         link->eng_id = link->link_enc->preferred_engine;
1720         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;
1721         link->dc->res_pool->dig_link_enc_count++;
1722
1723         link->link_enc_hw_inst = link->link_enc->transmitter;
1724
1725         for (i = 0; i < 4; i++) {
1726                 if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1727                                              link->link_id, i,
1728                                              &link->device_tag) != BP_RESULT_OK) {
1729                         DC_ERROR("Failed to find device tag!\n");
1730                         goto device_tag_fail;
1731                 }
1732
1733                 /* Look for device tag that matches connector signal,
1734                  * CRT for rgb, LCD for other supported signal tyes
1735                  */
1736                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1737                                                       link->device_tag.dev_id))
1738                         continue;
1739                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1740                     link->connector_signal != SIGNAL_TYPE_RGB)
1741                         continue;
1742                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1743                     link->connector_signal == SIGNAL_TYPE_RGB)
1744                         continue;
1745
1746                 DC_LOG_DC("BIOS object table - device_tag.acpi_device: %d", link->device_tag.acpi_device);
1747                 DC_LOG_DC("BIOS object table - device_tag.dev_id.device_type: %d", link->device_tag.dev_id.device_type);
1748                 DC_LOG_DC("BIOS object table - device_tag.dev_id.enum_id: %d", link->device_tag.dev_id.enum_id);
1749                 break;
1750         }
1751
1752         if (bios->integrated_info)
1753                 memcpy(info, bios->integrated_info, sizeof(*info));
1754
1755         /* Look for channel mapping corresponding to connector and device tag */
1756         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1757                 struct external_display_path *path =
1758                         &info->ext_disp_conn_info.path[i];
1759
1760                 if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1761                     path->device_connector_id.id == link->link_id.id &&
1762                     path->device_connector_id.type == link->link_id.type) {
1763                         if (link->device_tag.acpi_device != 0 &&
1764                             path->device_acpi_enum == link->device_tag.acpi_device) {
1765                                 link->ddi_channel_mapping = path->channel_mapping;
1766                                 link->chip_caps = path->caps;
1767                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1768                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1769                         } else if (path->device_tag ==
1770                                    link->device_tag.dev_id.raw_device_tag) {
1771                                 link->ddi_channel_mapping = path->channel_mapping;
1772                                 link->chip_caps = path->caps;
1773                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1774                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1775                         }
1776
1777                         if (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) {
1778                                 link->bios_forced_drive_settings.VOLTAGE_SWING =
1779                                                 (info->ext_disp_conn_info.fixdpvoltageswing & 0x3);
1780                                 link->bios_forced_drive_settings.PRE_EMPHASIS =
1781                                                 ((info->ext_disp_conn_info.fixdpvoltageswing >> 2) & 0x3);
1782                         }
1783
1784                         break;
1785                 }
1786         }
1787
1788         if (bios->funcs->get_atom_dc_golden_table)
1789                 bios->funcs->get_atom_dc_golden_table(bios);
1790
1791         /*
1792          * TODO check if GPIO programmed correctly
1793          *
1794          * If GPIO isn't programmed correctly HPD might not rise or drain
1795          * fast enough, leading to bounces.
1796          */
1797         program_hpd_filter(link);
1798
1799         link->psr_settings.psr_vtotal_control_support = false;
1800         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1801
1802         DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
1803         kfree(info);
1804         return true;
1805 device_tag_fail:
1806         link->link_enc->funcs->destroy(&link->link_enc);
1807 link_enc_create_fail:
1808         if (link->panel_cntl != NULL)
1809                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
1810 panel_cntl_create_fail:
1811         dal_ddc_service_destroy(&link->ddc);
1812 ddc_create_fail:
1813 create_fail:
1814
1815         if (link->hpd_gpio) {
1816                 dal_gpio_destroy_irq(&link->hpd_gpio);
1817                 link->hpd_gpio = NULL;
1818         }
1819
1820         DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
1821         kfree(info);
1822
1823         return false;
1824 }
1825
1826 static bool dc_link_construct_dpia(struct dc_link *link,
1827                                    const struct link_init_data *init_params)
1828 {
1829         struct ddc_service_init_data ddc_service_init_data = { 0 };
1830         struct dc_context *dc_ctx = init_params->ctx;
1831
1832         DC_LOGGER_INIT(dc_ctx->logger);
1833
1834         /* Initialized irq source for hpd and hpd rx */
1835         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1836         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1837         link->link_status.dpcd_caps = &link->dpcd_caps;
1838
1839         link->dc = init_params->dc;
1840         link->ctx = dc_ctx;
1841         link->link_index = init_params->link_index;
1842
1843         memset(&link->preferred_training_settings, 0,
1844                sizeof(struct dc_link_training_overrides));
1845         memset(&link->preferred_link_setting, 0,
1846                sizeof(struct dc_link_settings));
1847
1848         /* Dummy Init for linkid */
1849         link->link_id.type = OBJECT_TYPE_CONNECTOR;
1850         link->link_id.id = CONNECTOR_ID_DISPLAY_PORT;
1851         link->link_id.enum_id = ENUM_ID_1 + init_params->connector_index;
1852         link->is_internal_display = false;
1853         link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1854         LINK_INFO("Connector[%d] description:signal %d\n",
1855                   init_params->connector_index,
1856                   link->connector_signal);
1857
1858         link->ep_type = DISPLAY_ENDPOINT_USB4_DPIA;
1859         link->is_dig_mapping_flexible = true;
1860
1861         /* TODO: Initialize link : funcs->link_init */
1862
1863         ddc_service_init_data.ctx = link->ctx;
1864         ddc_service_init_data.id = link->link_id;
1865         ddc_service_init_data.link = link;
1866         /* Set indicator for dpia link so that ddc won't be created */
1867         ddc_service_init_data.is_dpia_link = true;
1868
1869         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1870         if (!link->ddc) {
1871                 DC_ERROR("Failed to create ddc_service!\n");
1872                 goto ddc_create_fail;
1873         }
1874
1875         /* Set dpia port index : 0 to number of dpia ports */
1876         link->ddc_hw_inst = init_params->connector_index;
1877
1878         /* TODO: Create link encoder */
1879
1880         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1881
1882         /* Some docks seem to NAK I2C writes to segment pointer with mot=0. */
1883         link->wa_flags.dp_mot_reset_segment = true;
1884
1885         return true;
1886
1887 ddc_create_fail:
1888         return false;
1889 }
1890
1891 static bool dc_link_construct(struct dc_link *link,
1892                               const struct link_init_data *init_params)
1893 {
1894         /* Handle dpia case */
1895         if (init_params->is_dpia_link)
1896                 return dc_link_construct_dpia(link, init_params);
1897         else
1898                 return dc_link_construct_legacy(link, init_params);
1899 }
1900 /*******************************************************************************
1901  * Public functions
1902  ******************************************************************************/
1903 struct dc_link *link_create(const struct link_init_data *init_params)
1904 {
1905         struct dc_link *link =
1906                         kzalloc(sizeof(*link), GFP_KERNEL);
1907
1908         if (NULL == link)
1909                 goto alloc_fail;
1910
1911         if (false == dc_link_construct(link, init_params))
1912                 goto construct_fail;
1913
1914         /*
1915          * Must use preferred_link_setting, not reported_link_cap or verified_link_cap,
1916          * since struct preferred_link_setting won't be reset after S3.
1917          */
1918         link->preferred_link_setting.dpcd_source_device_specific_field_support = true;
1919
1920         return link;
1921
1922 construct_fail:
1923         kfree(link);
1924
1925 alloc_fail:
1926         return NULL;
1927 }
1928
1929 void link_destroy(struct dc_link **link)
1930 {
1931         dc_link_destruct(*link);
1932         kfree(*link);
1933         *link = NULL;
1934 }
1935
1936 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1937 {
1938         struct dc_stream_state *stream = pipe_ctx->stream;
1939
1940         if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {
1941                 struct dc_link *link = stream->link;
1942                 union down_spread_ctrl old_downspread;
1943                 union down_spread_ctrl new_downspread;
1944
1945                 memset(&old_downspread, 0, sizeof(old_downspread));
1946
1947                 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1948                                 &old_downspread.raw, sizeof(old_downspread));
1949
1950                 new_downspread.raw = old_downspread.raw;
1951
1952                 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1953                                 (stream->ignore_msa_timing_param) ? 1 : 0;
1954
1955                 if (new_downspread.raw != old_downspread.raw) {
1956                         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1957                                 &new_downspread.raw, sizeof(new_downspread));
1958                 }
1959
1960         } else {
1961                 dm_helpers_mst_enable_stream_features(stream);
1962         }
1963 }
1964
1965 static enum dc_status enable_link_dp(struct dc_state *state,
1966                                      struct pipe_ctx *pipe_ctx)
1967 {
1968         struct dc_stream_state *stream = pipe_ctx->stream;
1969         enum dc_status status;
1970         bool skip_video_pattern;
1971         struct dc_link *link = stream->link;
1972         const struct dc_link_settings *link_settings =
1973                         &pipe_ctx->link_config.dp_link_settings;
1974         bool fec_enable;
1975         int i;
1976         bool apply_seamless_boot_optimization = false;
1977         uint32_t bl_oled_enable_delay = 50; // in ms
1978         const uint32_t post_oui_delay = 30; // 30ms
1979         /* Reduce link bandwidth between failed link training attempts. */
1980         bool do_fallback = false;
1981
1982         // check for seamless boot
1983         for (i = 0; i < state->stream_count; i++) {
1984                 if (state->streams[i]->apply_seamless_boot_optimization) {
1985                         apply_seamless_boot_optimization = true;
1986                         break;
1987                 }
1988         }
1989
1990         /* Train with fallback when enabling DPIA link. Conventional links are
1991          * trained with fallback during sink detection.
1992          */
1993         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
1994                 do_fallback = true;
1995
1996         /*
1997          * Temporary w/a to get DP2.0 link rates to work with SST.
1998          * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved.
1999          */
2000         if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING &&
2001                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
2002                         link->dc->debug.set_mst_en_for_sst) {
2003                 dp_enable_mst_on_sink(link, true);
2004         }
2005
2006         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
2007                 /*in case it is not on*/
2008                 if (!link->dc->config.edp_no_power_sequencing)
2009                         link->dc->hwss.edp_power_control(link, true);
2010                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
2011         }
2012
2013         if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING) {
2014                 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */
2015         } else {
2016                 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
2017                                 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
2018                 if (state->clk_mgr && !apply_seamless_boot_optimization)
2019                         state->clk_mgr->funcs->update_clocks(state->clk_mgr,
2020                                         state, false);
2021         }
2022
2023         // during mode switch we do DP_SET_POWER off then on, and OUI is lost
2024         dpcd_set_source_specific_data(link);
2025         if (link->dpcd_sink_ext_caps.raw != 0)
2026                 msleep(post_oui_delay);
2027
2028         // similarly, mode switch can cause loss of cable ID
2029         dpcd_write_cable_id_to_dprx(link);
2030
2031         skip_video_pattern = true;
2032
2033         if (link_settings->link_rate == LINK_RATE_LOW)
2034                 skip_video_pattern = false;
2035
2036         if (perform_link_training_with_retries(link_settings,
2037                                                skip_video_pattern,
2038                                                LINK_TRAINING_ATTEMPTS,
2039                                                pipe_ctx,
2040                                                pipe_ctx->stream->signal,
2041                                                do_fallback)) {
2042                 status = DC_OK;
2043         } else {
2044                 status = DC_FAIL_DP_LINK_TRAINING;
2045         }
2046
2047         if (link->preferred_training_settings.fec_enable)
2048                 fec_enable = *link->preferred_training_settings.fec_enable;
2049         else
2050                 fec_enable = true;
2051
2052         if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
2053                 dp_set_fec_enable(link, fec_enable);
2054
2055         // during mode set we do DP_SET_POWER off then on, aux writes are lost
2056         if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
2057                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
2058                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
2059                 dc_link_set_default_brightness_aux(link); // TODO: use cached if known
2060                 if (link->dpcd_sink_ext_caps.bits.oled == 1)
2061                         msleep(bl_oled_enable_delay);
2062                 dc_link_backlight_enable_aux(link, true);
2063         }
2064
2065         return status;
2066 }
2067
2068 static enum dc_status enable_link_edp(
2069                 struct dc_state *state,
2070                 struct pipe_ctx *pipe_ctx)
2071 {
2072         enum dc_status status;
2073
2074         status = enable_link_dp(state, pipe_ctx);
2075
2076         return status;
2077 }
2078
2079 static enum dc_status enable_link_dp_mst(
2080                 struct dc_state *state,
2081                 struct pipe_ctx *pipe_ctx)
2082 {
2083         struct dc_link *link = pipe_ctx->stream->link;
2084
2085         /* sink signal type after MST branch is MST. Multiple MST sinks
2086          * share one link. Link DP PHY is enable or training only once.
2087          */
2088         if (link->link_status.link_active)
2089                 return DC_OK;
2090
2091         /* clear payload table */
2092         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
2093
2094         /* to make sure the pending down rep can be processed
2095          * before enabling the link
2096          */
2097         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
2098
2099         /* set the sink to MST mode before enabling the link */
2100         dp_enable_mst_on_sink(link, true);
2101
2102         return enable_link_dp(state, pipe_ctx);
2103 }
2104
2105 void dc_link_blank_all_dp_displays(struct dc *dc)
2106 {
2107         unsigned int i;
2108         uint8_t dpcd_power_state = '\0';
2109         enum dc_status status = DC_ERROR_UNEXPECTED;
2110
2111         for (i = 0; i < dc->link_count; i++) {
2112                 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) ||
2113                         (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL))
2114                         continue;
2115
2116                 /* DP 2.0 spec requires that we read LTTPR caps first */
2117                 dp_retrieve_lttpr_cap(dc->links[i]);
2118                 /* if any of the displays are lit up turn them off */
2119                 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
2120                                                         &dpcd_power_state, sizeof(dpcd_power_state));
2121
2122                 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0)
2123                         dc_link_blank_dp_stream(dc->links[i], true);
2124         }
2125
2126 }
2127
2128 void dc_link_blank_all_edp_displays(struct dc *dc)
2129 {
2130         unsigned int i;
2131         uint8_t dpcd_power_state = '\0';
2132         enum dc_status status = DC_ERROR_UNEXPECTED;
2133
2134         for (i = 0; i < dc->link_count; i++) {
2135                 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) ||
2136                         (!dc->links[i]->edp_sink_present))
2137                         continue;
2138
2139                 /* if any of the displays are lit up turn them off */
2140                 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
2141                                                         &dpcd_power_state, sizeof(dpcd_power_state));
2142
2143                 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0)
2144                         dc_link_blank_dp_stream(dc->links[i], true);
2145         }
2146 }
2147
2148 void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init)
2149 {
2150         unsigned int j;
2151         struct dc  *dc = link->ctx->dc;
2152         enum signal_type signal = link->connector_signal;
2153
2154         if ((signal == SIGNAL_TYPE_EDP) ||
2155                 (signal == SIGNAL_TYPE_DISPLAY_PORT)) {
2156                 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
2157                         link->link_enc->funcs->get_dig_frontend &&
2158                         link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
2159                         unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc);
2160
2161                         if (fe != ENGINE_ID_UNKNOWN)
2162                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
2163                                         if (fe == dc->res_pool->stream_enc[j]->id) {
2164                                                 dc->res_pool->stream_enc[j]->funcs->dp_blank(link,
2165                                                                         dc->res_pool->stream_enc[j]);
2166                                                 break;
2167                                         }
2168                                 }
2169                 }
2170
2171                 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)
2172                         dp_receiver_power_ctrl(link, false);
2173         }
2174 }
2175
2176 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
2177                 enum engine_id eng_id,
2178                 struct ext_hdmi_settings *settings)
2179 {
2180         bool result = false;
2181         int i = 0;
2182         struct integrated_info *integrated_info =
2183                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
2184
2185         if (integrated_info == NULL)
2186                 return false;
2187
2188         /*
2189          * Get retimer settings from sbios for passing SI eye test for DCE11
2190          * The setting values are varied based on board revision and port id
2191          * Therefore the setting values of each ports is passed by sbios.
2192          */
2193
2194         // Check if current bios contains ext Hdmi settings
2195         if (integrated_info->gpu_cap_info & 0x20) {
2196                 switch (eng_id) {
2197                 case ENGINE_ID_DIGA:
2198                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
2199                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
2200                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
2201                         memmove(settings->reg_settings,
2202                                         integrated_info->dp0_ext_hdmi_reg_settings,
2203                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
2204                         memmove(settings->reg_settings_6g,
2205                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
2206                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
2207                         result = true;
2208                         break;
2209                 case ENGINE_ID_DIGB:
2210                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
2211                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
2212                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
2213                         memmove(settings->reg_settings,
2214                                         integrated_info->dp1_ext_hdmi_reg_settings,
2215                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
2216                         memmove(settings->reg_settings_6g,
2217                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
2218                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
2219                         result = true;
2220                         break;
2221                 case ENGINE_ID_DIGC:
2222                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
2223                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
2224                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
2225                         memmove(settings->reg_settings,
2226                                         integrated_info->dp2_ext_hdmi_reg_settings,
2227                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
2228                         memmove(settings->reg_settings_6g,
2229                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
2230                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
2231                         result = true;
2232                         break;
2233                 case ENGINE_ID_DIGD:
2234                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
2235                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
2236                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
2237                         memmove(settings->reg_settings,
2238                                         integrated_info->dp3_ext_hdmi_reg_settings,
2239                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
2240                         memmove(settings->reg_settings_6g,
2241                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
2242                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
2243                         result = true;
2244                         break;
2245                 default:
2246                         break;
2247                 }
2248
2249                 if (result == true) {
2250                         // Validate settings from bios integrated info table
2251                         if (settings->slv_addr == 0)
2252                                 return false;
2253                         if (settings->reg_num > 9)
2254                                 return false;
2255                         if (settings->reg_num_6g > 3)
2256                                 return false;
2257
2258                         for (i = 0; i < settings->reg_num; i++) {
2259                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
2260                                         return false;
2261                         }
2262
2263                         for (i = 0; i < settings->reg_num_6g; i++) {
2264                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
2265                                         return false;
2266                         }
2267                 }
2268         }
2269
2270         return result;
2271 }
2272
2273 static bool i2c_write(struct pipe_ctx *pipe_ctx,
2274                 uint8_t address, uint8_t *buffer, uint32_t length)
2275 {
2276         struct i2c_command cmd = {0};
2277         struct i2c_payload payload = {0};
2278
2279         memset(&payload, 0, sizeof(payload));
2280         memset(&cmd, 0, sizeof(cmd));
2281
2282         cmd.number_of_payloads = 1;
2283         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
2284         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
2285
2286         payload.address = address;
2287         payload.data = buffer;
2288         payload.length = length;
2289         payload.write = true;
2290         cmd.payloads = &payload;
2291
2292         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
2293                         pipe_ctx->stream->link, &cmd))
2294                 return true;
2295
2296         return false;
2297 }
2298
2299 static void write_i2c_retimer_setting(
2300                 struct pipe_ctx *pipe_ctx,
2301                 bool is_vga_mode,
2302                 bool is_over_340mhz,
2303                 struct ext_hdmi_settings *settings)
2304 {
2305         uint8_t slave_address = (settings->slv_addr >> 1);
2306         uint8_t buffer[2];
2307         const uint8_t apply_rx_tx_change = 0x4;
2308         uint8_t offset = 0xA;
2309         uint8_t value = 0;
2310         int i = 0;
2311         bool i2c_success = false;
2312         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2313
2314         memset(&buffer, 0, sizeof(buffer));
2315
2316         /* Start Ext-Hdmi programming*/
2317
2318         for (i = 0; i < settings->reg_num; i++) {
2319                 /* Apply 3G settings */
2320                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2321
2322                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
2323                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
2324                         i2c_success = i2c_write(pipe_ctx, slave_address,
2325                                                 buffer, sizeof(buffer));
2326                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2327                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2328                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2329
2330                         if (!i2c_success)
2331                                 goto i2c_write_fail;
2332
2333                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2334                          * needs to be set to 1 on every 0xA-0xC write.
2335                          */
2336                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
2337                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
2338                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
2339
2340                                 /* Query current value from offset 0xA */
2341                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
2342                                         value = settings->reg_settings[i].i2c_reg_val;
2343                                 else {
2344                                         i2c_success =
2345                                                 dal_ddc_service_query_ddc_data(
2346                                                 pipe_ctx->stream->link->ddc,
2347                                                 slave_address, &offset, 1, &value, 1);
2348                                         if (!i2c_success)
2349                                                 goto i2c_write_fail;
2350                                 }
2351
2352                                 buffer[0] = offset;
2353                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
2354                                 buffer[1] = value | apply_rx_tx_change;
2355                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2356                                                 buffer, sizeof(buffer));
2357                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2358                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2359                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2360                                 if (!i2c_success)
2361                                         goto i2c_write_fail;
2362                         }
2363                 }
2364         }
2365
2366         /* Apply 3G settings */
2367         if (is_over_340mhz) {
2368                 for (i = 0; i < settings->reg_num_6g; i++) {
2369                         /* Apply 3G settings */
2370                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2371
2372                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
2373                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
2374                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2375                                                         buffer, sizeof(buffer));
2376                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
2377                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2378                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2379
2380                                 if (!i2c_success)
2381                                         goto i2c_write_fail;
2382
2383                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2384                                  * needs to be set to 1 on every 0xA-0xC write.
2385                                  */
2386                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
2387                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
2388                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
2389
2390                                         /* Query current value from offset 0xA */
2391                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
2392                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
2393                                         else {
2394                                                 i2c_success =
2395                                                                 dal_ddc_service_query_ddc_data(
2396                                                                 pipe_ctx->stream->link->ddc,
2397                                                                 slave_address, &offset, 1, &value, 1);
2398                                                 if (!i2c_success)
2399                                                         goto i2c_write_fail;
2400                                         }
2401
2402                                         buffer[0] = offset;
2403                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
2404                                         buffer[1] = value | apply_rx_tx_change;
2405                                         i2c_success = i2c_write(pipe_ctx, slave_address,
2406                                                         buffer, sizeof(buffer));
2407                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2408                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2409                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2410                                         if (!i2c_success)
2411                                                 goto i2c_write_fail;
2412                                 }
2413                         }
2414                 }
2415         }
2416
2417         if (is_vga_mode) {
2418                 /* Program additional settings if using 640x480 resolution */
2419
2420                 /* Write offset 0xFF to 0x01 */
2421                 buffer[0] = 0xff;
2422                 buffer[1] = 0x01;
2423                 i2c_success = i2c_write(pipe_ctx, slave_address,
2424                                 buffer, sizeof(buffer));
2425                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2426                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2427                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2428                 if (!i2c_success)
2429                         goto i2c_write_fail;
2430
2431                 /* Write offset 0x00 to 0x23 */
2432                 buffer[0] = 0x00;
2433                 buffer[1] = 0x23;
2434                 i2c_success = i2c_write(pipe_ctx, slave_address,
2435                                 buffer, sizeof(buffer));
2436                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2437                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2438                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2439                 if (!i2c_success)
2440                         goto i2c_write_fail;
2441
2442                 /* Write offset 0xff to 0x00 */
2443                 buffer[0] = 0xff;
2444                 buffer[1] = 0x00;
2445                 i2c_success = i2c_write(pipe_ctx, slave_address,
2446                                 buffer, sizeof(buffer));
2447                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2448                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2449                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2450                 if (!i2c_success)
2451                         goto i2c_write_fail;
2452
2453         }
2454
2455         return;
2456
2457 i2c_write_fail:
2458         DC_LOG_DEBUG("Set retimer failed");
2459 }
2460
2461 static void write_i2c_default_retimer_setting(
2462                 struct pipe_ctx *pipe_ctx,
2463                 bool is_vga_mode,
2464                 bool is_over_340mhz)
2465 {
2466         uint8_t slave_address = (0xBA >> 1);
2467         uint8_t buffer[2];
2468         bool i2c_success = false;
2469         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2470
2471         memset(&buffer, 0, sizeof(buffer));
2472
2473         /* Program Slave Address for tuning single integrity */
2474         /* Write offset 0x0A to 0x13 */
2475         buffer[0] = 0x0A;
2476         buffer[1] = 0x13;
2477         i2c_success = i2c_write(pipe_ctx, slave_address,
2478                         buffer, sizeof(buffer));
2479         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2480                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2481                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2482         if (!i2c_success)
2483                 goto i2c_write_fail;
2484
2485         /* Write offset 0x0A to 0x17 */
2486         buffer[0] = 0x0A;
2487         buffer[1] = 0x17;
2488         i2c_success = i2c_write(pipe_ctx, slave_address,
2489                         buffer, sizeof(buffer));
2490         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2491                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2492                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2493         if (!i2c_success)
2494                 goto i2c_write_fail;
2495
2496         /* Write offset 0x0B to 0xDA or 0xD8 */
2497         buffer[0] = 0x0B;
2498         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2499         i2c_success = i2c_write(pipe_ctx, slave_address,
2500                         buffer, sizeof(buffer));
2501         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2502                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2503                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2504         if (!i2c_success)
2505                 goto i2c_write_fail;
2506
2507         /* Write offset 0x0A to 0x17 */
2508         buffer[0] = 0x0A;
2509         buffer[1] = 0x17;
2510         i2c_success = i2c_write(pipe_ctx, slave_address,
2511                         buffer, sizeof(buffer));
2512         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2513                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2514                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2515         if (!i2c_success)
2516                 goto i2c_write_fail;
2517
2518         /* Write offset 0x0C to 0x1D or 0x91 */
2519         buffer[0] = 0x0C;
2520         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2521         i2c_success = i2c_write(pipe_ctx, slave_address,
2522                         buffer, sizeof(buffer));
2523         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2524                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2525                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2526         if (!i2c_success)
2527                 goto i2c_write_fail;
2528
2529         /* Write offset 0x0A to 0x17 */
2530         buffer[0] = 0x0A;
2531         buffer[1] = 0x17;
2532         i2c_success = i2c_write(pipe_ctx, slave_address,
2533                         buffer, sizeof(buffer));
2534         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2535                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2536                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2537         if (!i2c_success)
2538                 goto i2c_write_fail;
2539
2540
2541         if (is_vga_mode) {
2542                 /* Program additional settings if using 640x480 resolution */
2543
2544                 /* Write offset 0xFF to 0x01 */
2545                 buffer[0] = 0xff;
2546                 buffer[1] = 0x01;
2547                 i2c_success = i2c_write(pipe_ctx, slave_address,
2548                                 buffer, sizeof(buffer));
2549                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2550                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2551                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2552                 if (!i2c_success)
2553                         goto i2c_write_fail;
2554
2555                 /* Write offset 0x00 to 0x23 */
2556                 buffer[0] = 0x00;
2557                 buffer[1] = 0x23;
2558                 i2c_success = i2c_write(pipe_ctx, slave_address,
2559                                 buffer, sizeof(buffer));
2560                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2561                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2562                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2563                 if (!i2c_success)
2564                         goto i2c_write_fail;
2565
2566                 /* Write offset 0xff to 0x00 */
2567                 buffer[0] = 0xff;
2568                 buffer[1] = 0x00;
2569                 i2c_success = i2c_write(pipe_ctx, slave_address,
2570                                 buffer, sizeof(buffer));
2571                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2572                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2573                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2574                 if (!i2c_success)
2575                         goto i2c_write_fail;
2576         }
2577
2578         return;
2579
2580 i2c_write_fail:
2581         DC_LOG_DEBUG("Set default retimer failed");
2582 }
2583
2584 static void write_i2c_redriver_setting(
2585                 struct pipe_ctx *pipe_ctx,
2586                 bool is_over_340mhz)
2587 {
2588         uint8_t slave_address = (0xF0 >> 1);
2589         uint8_t buffer[16];
2590         bool i2c_success = false;
2591         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2592
2593         memset(&buffer, 0, sizeof(buffer));
2594
2595         // Program Slave Address for tuning single integrity
2596         buffer[3] = 0x4E;
2597         buffer[4] = 0x4E;
2598         buffer[5] = 0x4E;
2599         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2600
2601         i2c_success = i2c_write(pipe_ctx, slave_address,
2602                                         buffer, sizeof(buffer));
2603         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2604                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2605                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2606                 i2c_success = %d\n",
2607                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2608
2609         if (!i2c_success)
2610                 DC_LOG_DEBUG("Set redriver failed");
2611 }
2612
2613 static void disable_link(struct dc_link *link, const struct link_resource *link_res,
2614                 enum signal_type signal)
2615 {
2616         /*
2617          * TODO: implement call for dp_set_hw_test_pattern
2618          * it is needed for compliance testing
2619          */
2620
2621         /* Here we need to specify that encoder output settings
2622          * need to be calculated as for the set mode,
2623          * it will lead to querying dynamic link capabilities
2624          * which should be done before enable output
2625          */
2626
2627         if (dc_is_dp_signal(signal)) {
2628                 /* SST DP, eDP */
2629                 struct dc_link_settings link_settings = link->cur_link_settings;
2630                 if (dc_is_dp_sst_signal(signal))
2631                         dp_disable_link_phy(link, link_res, signal);
2632                 else
2633                         dp_disable_link_phy_mst(link, link_res, signal);
2634
2635                 if (dc_is_dp_sst_signal(signal) ||
2636                                 link->mst_stream_alloc_table.stream_count == 0) {
2637                         if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING) {
2638                                 dp_set_fec_enable(link, false);
2639                                 dp_set_fec_ready(link, link_res, false);
2640                         }
2641                 }
2642         } else {
2643                 if (signal != SIGNAL_TYPE_VIRTUAL)
2644                         link->link_enc->funcs->disable_output(link->link_enc, signal);
2645         }
2646
2647         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2648                 /* MST disable link only when no stream use the link */
2649                 if (link->mst_stream_alloc_table.stream_count <= 0)
2650                         link->link_status.link_active = false;
2651         } else {
2652                 link->link_status.link_active = false;
2653         }
2654 }
2655
2656 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2657 {
2658         struct dc_stream_state *stream = pipe_ctx->stream;
2659         struct dc_link *link = stream->link;
2660         enum dc_color_depth display_color_depth;
2661         enum engine_id eng_id;
2662         struct ext_hdmi_settings settings = {0};
2663         bool is_over_340mhz = false;
2664         bool is_vga_mode = (stream->timing.h_addressable == 640)
2665                         && (stream->timing.v_addressable == 480);
2666
2667         if (stream->phy_pix_clk == 0)
2668                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2669         if (stream->phy_pix_clk > 340000)
2670                 is_over_340mhz = true;
2671
2672         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2673                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2674                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2675                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2676                         /* DP159, Retimer settings */
2677                         eng_id = pipe_ctx->stream_res.stream_enc->id;
2678
2679                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2680                                 write_i2c_retimer_setting(pipe_ctx,
2681                                                 is_vga_mode, is_over_340mhz, &settings);
2682                         } else {
2683                                 write_i2c_default_retimer_setting(pipe_ctx,
2684                                                 is_vga_mode, is_over_340mhz);
2685                         }
2686                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2687                         /* PI3EQX1204, Redriver settings */
2688                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2689                 }
2690         }
2691
2692         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2693                 dal_ddc_service_write_scdc_data(
2694                         stream->link->ddc,
2695                         stream->phy_pix_clk,
2696                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2697
2698         memset(&stream->link->cur_link_settings, 0,
2699                         sizeof(struct dc_link_settings));
2700
2701         display_color_depth = stream->timing.display_color_depth;
2702         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2703                 display_color_depth = COLOR_DEPTH_888;
2704
2705         link->link_enc->funcs->enable_tmds_output(
2706                         link->link_enc,
2707                         pipe_ctx->clock_source->id,
2708                         display_color_depth,
2709                         pipe_ctx->stream->signal,
2710                         stream->phy_pix_clk);
2711
2712         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2713                 dal_ddc_service_read_scdc_data(link->ddc);
2714 }
2715
2716 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2717 {
2718         struct dc_stream_state *stream = pipe_ctx->stream;
2719         struct dc_link *link = stream->link;
2720
2721         if (stream->phy_pix_clk == 0)
2722                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2723
2724         memset(&stream->link->cur_link_settings, 0,
2725                         sizeof(struct dc_link_settings));
2726
2727         link->link_enc->funcs->enable_lvds_output(
2728                         link->link_enc,
2729                         pipe_ctx->clock_source->id,
2730                         stream->phy_pix_clk);
2731
2732 }
2733
2734 bool dc_power_alpm_dpcd_enable(struct dc_link *link, bool enable)
2735 {
2736         bool ret = false;
2737         union dpcd_alpm_configuration alpm_config;
2738
2739         if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
2740                 memset(&alpm_config, 0, sizeof(alpm_config));
2741
2742                 alpm_config.bits.ENABLE = (enable ? true : false);
2743                 ret = dm_helpers_dp_write_dpcd(link->ctx, link,
2744                                 DP_RECEIVER_ALPM_CONFIG, &alpm_config.raw,
2745                                 sizeof(alpm_config.raw));
2746         }
2747         return ret;
2748 }
2749
2750 /****************************enable_link***********************************/
2751 static enum dc_status enable_link(
2752                 struct dc_state *state,
2753                 struct pipe_ctx *pipe_ctx)
2754 {
2755         enum dc_status status = DC_ERROR_UNEXPECTED;
2756         struct dc_stream_state *stream = pipe_ctx->stream;
2757         struct dc_link *link = stream->link;
2758
2759         /* There's some scenarios where driver is unloaded with display
2760          * still enabled. When driver is reloaded, it may cause a display
2761          * to not light up if there is a mismatch between old and new
2762          * link settings. Need to call disable first before enabling at
2763          * new link settings.
2764          */
2765         if (link->link_status.link_active) {
2766                 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
2767         }
2768
2769         switch (pipe_ctx->stream->signal) {
2770         case SIGNAL_TYPE_DISPLAY_PORT:
2771                 status = enable_link_dp(state, pipe_ctx);
2772                 break;
2773         case SIGNAL_TYPE_EDP:
2774                 status = enable_link_edp(state, pipe_ctx);
2775                 break;
2776         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2777                 status = enable_link_dp_mst(state, pipe_ctx);
2778                 msleep(200);
2779                 break;
2780         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2781         case SIGNAL_TYPE_DVI_DUAL_LINK:
2782         case SIGNAL_TYPE_HDMI_TYPE_A:
2783                 enable_link_hdmi(pipe_ctx);
2784                 status = DC_OK;
2785                 break;
2786         case SIGNAL_TYPE_LVDS:
2787                 enable_link_lvds(pipe_ctx);
2788                 status = DC_OK;
2789                 break;
2790         case SIGNAL_TYPE_VIRTUAL:
2791                 status = DC_OK;
2792                 break;
2793         default:
2794                 break;
2795         }
2796
2797         if (status == DC_OK)
2798                 pipe_ctx->stream->link->link_status.link_active = true;
2799
2800         return status;
2801 }
2802
2803 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2804 {
2805
2806         uint32_t pxl_clk = timing->pix_clk_100hz;
2807
2808         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2809                 pxl_clk /= 2;
2810         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2811                 pxl_clk = pxl_clk * 2 / 3;
2812
2813         if (timing->display_color_depth == COLOR_DEPTH_101010)
2814                 pxl_clk = pxl_clk * 10 / 8;
2815         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2816                 pxl_clk = pxl_clk * 12 / 8;
2817
2818         return pxl_clk;
2819 }
2820
2821 static bool dp_active_dongle_validate_timing(
2822                 const struct dc_crtc_timing *timing,
2823                 const struct dpcd_caps *dpcd_caps)
2824 {
2825         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2826
2827         switch (dpcd_caps->dongle_type) {
2828         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2829         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2830         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2831                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2832                         return true;
2833                 else
2834                         return false;
2835         default:
2836                 break;
2837         }
2838
2839         if (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER &&
2840                         dongle_caps->extendedCapValid == true) {
2841                 /* Check Pixel Encoding */
2842                 switch (timing->pixel_encoding) {
2843                 case PIXEL_ENCODING_RGB:
2844                 case PIXEL_ENCODING_YCBCR444:
2845                         break;
2846                 case PIXEL_ENCODING_YCBCR422:
2847                         if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2848                                 return false;
2849                         break;
2850                 case PIXEL_ENCODING_YCBCR420:
2851                         if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2852                                 return false;
2853                         break;
2854                 default:
2855                         /* Invalid Pixel Encoding*/
2856                         return false;
2857                 }
2858
2859                 switch (timing->display_color_depth) {
2860                 case COLOR_DEPTH_666:
2861                 case COLOR_DEPTH_888:
2862                         /*888 and 666 should always be supported*/
2863                         break;
2864                 case COLOR_DEPTH_101010:
2865                         if (dongle_caps->dp_hdmi_max_bpc < 10)
2866                                 return false;
2867                         break;
2868                 case COLOR_DEPTH_121212:
2869                         if (dongle_caps->dp_hdmi_max_bpc < 12)
2870                                 return false;
2871                         break;
2872                 case COLOR_DEPTH_141414:
2873                 case COLOR_DEPTH_161616:
2874                 default:
2875                         /* These color depths are currently not supported */
2876                         return false;
2877                 }
2878
2879                 /* Check 3D format */
2880                 switch (timing->timing_3d_format) {
2881                 case TIMING_3D_FORMAT_NONE:
2882                 case TIMING_3D_FORMAT_FRAME_ALTERNATE:
2883                         /*Only frame alternate 3D is supported on active dongle*/
2884                         break;
2885                 default:
2886                         /*other 3D formats are not supported due to bad infoframe translation */
2887                         return false;
2888                 }
2889
2890 #if defined(CONFIG_DRM_AMD_DC_DCN)
2891                 if (dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps > 0) { // DP to HDMI FRL converter
2892                         struct dc_crtc_timing outputTiming = *timing;
2893
2894                         if (timing->flags.DSC && !timing->dsc_cfg.is_frl)
2895                                 /* DP input has DSC, HDMI FRL output doesn't have DSC, remove DSC from output timing */
2896                                 outputTiming.flags.DSC = 0;
2897                         if (dc_bandwidth_in_kbps_from_timing(&outputTiming) > dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps)
2898                                 return false;
2899                 } else { // DP to HDMI TMDS converter
2900                         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2901                                 return false;
2902                 }
2903 #else
2904                 if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2905                         return false;
2906 #endif
2907         }
2908
2909         if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 &&
2910                         dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 &&
2911                         dongle_caps->dfp_cap_ext.supported) {
2912
2913                 if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000))
2914                         return false;
2915
2916                 if (dongle_caps->dfp_cap_ext.max_video_h_active_width < timing->h_addressable)
2917                         return false;
2918
2919                 if (dongle_caps->dfp_cap_ext.max_video_v_active_height < timing->v_addressable)
2920                         return false;
2921
2922                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) {
2923                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2924                                 return false;
2925                         if (timing->display_color_depth == COLOR_DEPTH_666 &&
2926                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_6bpc)
2927                                 return false;
2928                         else if (timing->display_color_depth == COLOR_DEPTH_888 &&
2929                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_8bpc)
2930                                 return false;
2931                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2932                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_10bpc)
2933                                 return false;
2934                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2935                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_12bpc)
2936                                 return false;
2937                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2938                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_16bpc)
2939                                 return false;
2940                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
2941                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2942                                 return false;
2943                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2944                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_8bpc)
2945                                 return false;
2946                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2947                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_10bpc)
2948                                 return false;
2949                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2950                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_12bpc)
2951                                 return false;
2952                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2953                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_16bpc)
2954                                 return false;
2955                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
2956                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2957                                 return false;
2958                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2959                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_8bpc)
2960                                 return false;
2961                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2962                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_10bpc)
2963                                 return false;
2964                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2965                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_12bpc)
2966                                 return false;
2967                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2968                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_16bpc)
2969                                 return false;
2970                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
2971                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2972                                 return false;
2973                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2974                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_8bpc)
2975                                 return false;
2976                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2977                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_10bpc)
2978                                 return false;
2979                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2980                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_12bpc)
2981                                 return false;
2982                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2983                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_16bpc)
2984                                 return false;
2985                 }
2986         }
2987
2988         return true;
2989 }
2990
2991 enum dc_status dc_link_validate_mode_timing(
2992                 const struct dc_stream_state *stream,
2993                 struct dc_link *link,
2994                 const struct dc_crtc_timing *timing)
2995 {
2996         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2997         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2998
2999         /* A hack to avoid failing any modes for EDID override feature on
3000          * topology change such as lower quality cable for DP or different dongle
3001          */
3002         if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
3003                 return DC_OK;
3004
3005         /* Passive Dongle */
3006         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
3007                 return DC_EXCEED_DONGLE_CAP;
3008
3009         /* Active Dongle*/
3010         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
3011                 return DC_EXCEED_DONGLE_CAP;
3012
3013         switch (stream->signal) {
3014         case SIGNAL_TYPE_EDP:
3015         case SIGNAL_TYPE_DISPLAY_PORT:
3016                 if (!dp_validate_mode_timing(
3017                                 link,
3018                                 timing))
3019                         return DC_NO_DP_LINK_BANDWIDTH;
3020                 break;
3021
3022         default:
3023                 break;
3024         }
3025
3026         return DC_OK;
3027 }
3028
3029 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
3030 {
3031         int i;
3032         struct dc *dc = NULL;
3033         struct abm *abm = NULL;
3034
3035         if (!link || !link->ctx)
3036                 return NULL;
3037
3038         dc = link->ctx->dc;
3039
3040         for (i = 0; i < MAX_PIPES; i++) {
3041                 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
3042                 struct dc_stream_state *stream = pipe_ctx.stream;
3043
3044                 if (stream && stream->link == link) {
3045                         abm = pipe_ctx.stream_res.abm;
3046                         break;
3047                 }
3048         }
3049         return abm;
3050 }
3051
3052 int dc_link_get_backlight_level(const struct dc_link *link)
3053 {
3054         struct abm *abm = get_abm_from_stream_res(link);
3055         struct panel_cntl *panel_cntl = link->panel_cntl;
3056         struct dc  *dc = link->ctx->dc;
3057         struct dmcu *dmcu = dc->res_pool->dmcu;
3058         bool fw_set_brightness = true;
3059
3060         if (dmcu)
3061                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
3062
3063         if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
3064                 return panel_cntl->funcs->get_current_backlight(panel_cntl);
3065         else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
3066                 return (int) abm->funcs->get_current_backlight(abm);
3067         else
3068                 return DC_ERROR_UNEXPECTED;
3069 }
3070
3071 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
3072 {
3073         struct abm *abm = get_abm_from_stream_res(link);
3074
3075         if (abm == NULL || abm->funcs->get_target_backlight == NULL)
3076                 return DC_ERROR_UNEXPECTED;
3077
3078         return (int) abm->funcs->get_target_backlight(abm);
3079 }
3080
3081 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
3082 {
3083         int i;
3084         struct dc *dc = link->ctx->dc;
3085         struct pipe_ctx *pipe_ctx = NULL;
3086
3087         for (i = 0; i < MAX_PIPES; i++) {
3088                 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
3089                         if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
3090                                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
3091                                 break;
3092                         }
3093                 }
3094         }
3095
3096         return pipe_ctx;
3097 }
3098
3099 bool dc_link_set_backlight_level(const struct dc_link *link,
3100                 uint32_t backlight_pwm_u16_16,
3101                 uint32_t frame_ramp)
3102 {
3103         struct dc  *dc = link->ctx->dc;
3104
3105         DC_LOGGER_INIT(link->ctx->logger);
3106         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
3107                         backlight_pwm_u16_16, backlight_pwm_u16_16);
3108
3109         if (dc_is_embedded_signal(link->connector_signal)) {
3110                 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
3111
3112                 if (pipe_ctx) {
3113                         /* Disable brightness ramping when the display is blanked
3114                          * as it can hang the DMCU
3115                          */
3116                         if (pipe_ctx->plane_state == NULL)
3117                                 frame_ramp = 0;
3118                 } else {
3119                         return false;
3120                 }
3121
3122                 dc->hwss.set_backlight_level(
3123                                 pipe_ctx,
3124                                 backlight_pwm_u16_16,
3125                                 frame_ramp);
3126         }
3127         return true;
3128 }
3129
3130 bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
3131                 bool wait, bool force_static, const unsigned int *power_opts)
3132 {
3133         struct dc  *dc = link->ctx->dc;
3134         struct dmcu *dmcu = dc->res_pool->dmcu;
3135         struct dmub_psr *psr = dc->res_pool->psr;
3136         unsigned int panel_inst;
3137
3138         if (psr == NULL && force_static)
3139                 return false;
3140
3141         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3142                 return false;
3143
3144         if (allow_active && link->type == dc_connection_none) {
3145                 // Don't enter PSR if panel is not connected
3146                 return false;
3147         }
3148
3149         /* Set power optimization flag */
3150         if (power_opts && link->psr_settings.psr_power_opt != *power_opts) {
3151                 link->psr_settings.psr_power_opt = *power_opts;
3152
3153                 if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
3154                         psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);
3155         }
3156
3157         if (psr != NULL && link->psr_settings.psr_feature_enabled &&
3158                         force_static && psr->funcs->psr_force_static)
3159                 psr->funcs->psr_force_static(psr, panel_inst);
3160
3161         /* Enable or Disable PSR */
3162         if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
3163                 link->psr_settings.psr_allow_active = *allow_active;
3164
3165                 if (!link->psr_settings.psr_allow_active)
3166                         dc_z10_restore(dc);
3167
3168                 if (psr != NULL && link->psr_settings.psr_feature_enabled) {
3169                         psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
3170                 } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
3171                         link->psr_settings.psr_feature_enabled)
3172                         dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);
3173                 else
3174                         return false;
3175         }
3176
3177         return true;
3178 }
3179
3180 bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
3181 {
3182         struct dc  *dc = link->ctx->dc;
3183         struct dmcu *dmcu = dc->res_pool->dmcu;
3184         struct dmub_psr *psr = dc->res_pool->psr;
3185         unsigned int panel_inst;
3186
3187         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3188                 return false;
3189
3190         if (psr != NULL && link->psr_settings.psr_feature_enabled)
3191                 psr->funcs->psr_get_state(psr, state, panel_inst);
3192         else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
3193                 dmcu->funcs->get_psr_state(dmcu, state);
3194
3195         return true;
3196 }
3197
3198 static inline enum physical_phy_id
3199 transmitter_to_phy_id(enum transmitter transmitter_value)
3200 {
3201         switch (transmitter_value) {
3202         case TRANSMITTER_UNIPHY_A:
3203                 return PHYLD_0;
3204         case TRANSMITTER_UNIPHY_B:
3205                 return PHYLD_1;
3206         case TRANSMITTER_UNIPHY_C:
3207                 return PHYLD_2;
3208         case TRANSMITTER_UNIPHY_D:
3209                 return PHYLD_3;
3210         case TRANSMITTER_UNIPHY_E:
3211                 return PHYLD_4;
3212         case TRANSMITTER_UNIPHY_F:
3213                 return PHYLD_5;
3214         case TRANSMITTER_NUTMEG_CRT:
3215                 return PHYLD_6;
3216         case TRANSMITTER_TRAVIS_CRT:
3217                 return PHYLD_7;
3218         case TRANSMITTER_TRAVIS_LCD:
3219                 return PHYLD_8;
3220         case TRANSMITTER_UNIPHY_G:
3221                 return PHYLD_9;
3222         case TRANSMITTER_COUNT:
3223                 return PHYLD_COUNT;
3224         case TRANSMITTER_UNKNOWN:
3225                 return PHYLD_UNKNOWN;
3226         default:
3227                 WARN_ONCE(1, "Unknown transmitter value %d\n",
3228                           transmitter_value);
3229                 return PHYLD_UNKNOWN;
3230         }
3231 }
3232
3233 bool dc_link_setup_psr(struct dc_link *link,
3234                 const struct dc_stream_state *stream, struct psr_config *psr_config,
3235                 struct psr_context *psr_context)
3236 {
3237         struct dc *dc;
3238         struct dmcu *dmcu;
3239         struct dmub_psr *psr;
3240         int i;
3241         unsigned int panel_inst;
3242         /* updateSinkPsrDpcdConfig*/
3243         union dpcd_psr_configuration psr_configuration;
3244         union dpcd_sink_active_vtotal_control_mode vtotal_control = {0};
3245
3246         psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
3247
3248         if (!link)
3249                 return false;
3250
3251         dc = link->ctx->dc;
3252         dmcu = dc->res_pool->dmcu;
3253         psr = dc->res_pool->psr;
3254
3255         if (!dmcu && !psr)
3256                 return false;
3257
3258         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3259                 return false;
3260
3261
3262         memset(&psr_configuration, 0, sizeof(psr_configuration));
3263
3264         psr_configuration.bits.ENABLE                    = 1;
3265         psr_configuration.bits.CRC_VERIFICATION          = 1;
3266         psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
3267                         psr_config->psr_frame_capture_indication_req;
3268
3269         /* Check for PSR v2*/
3270         if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
3271                 /* For PSR v2 selective update.
3272                  * Indicates whether sink should start capturing
3273                  * immediately following active scan line,
3274                  * or starting with the 2nd active scan line.
3275                  */
3276                 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
3277                 /*For PSR v2, determines whether Sink should generate
3278                  * IRQ_HPD when CRC mismatch is detected.
3279                  */
3280                 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
3281                 /* For PSR v2, set the bit when the Source device will
3282                  * be enabling PSR2 operation.
3283                  */
3284                 psr_configuration.bits.ENABLE_PSR2    = 1;
3285                 /* For PSR v2, the Sink device must be able to receive
3286                  * SU region updates early in the frame time.
3287                  */
3288                 psr_configuration.bits.EARLY_TRANSPORT_ENABLE    = 1;
3289         }
3290
3291         dm_helpers_dp_write_dpcd(
3292                 link->ctx,
3293                 link,
3294                 368,
3295                 &psr_configuration.raw,
3296                 sizeof(psr_configuration.raw));
3297
3298         if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
3299                 dc_power_alpm_dpcd_enable(link, true);
3300                 psr_context->su_granularity_required =
3301                         psr_config->su_granularity_required;
3302                 psr_context->su_y_granularity =
3303                         psr_config->su_y_granularity;
3304                 psr_context->line_time_in_us =
3305                         psr_config->line_time_in_us;
3306
3307                 if (link->psr_settings.psr_vtotal_control_support) {
3308                         psr_context->rate_control_caps = psr_config->rate_control_caps;
3309                         vtotal_control.bits.ENABLE = true;
3310                         core_link_write_dpcd(link, DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE,
3311                                                         &vtotal_control.raw, sizeof(vtotal_control.raw));
3312                 }
3313         }
3314
3315         psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
3316         psr_context->transmitterId = link->link_enc->transmitter;
3317         psr_context->engineId = link->link_enc->preferred_engine;
3318
3319         for (i = 0; i < MAX_PIPES; i++) {
3320                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
3321                                 == stream) {
3322                         /* dmcu -1 for all controller id values,
3323                          * therefore +1 here
3324                          */
3325                         psr_context->controllerId =
3326                                 dc->current_state->res_ctx.
3327                                 pipe_ctx[i].stream_res.tg->inst + 1;
3328                         break;
3329                 }
3330         }
3331
3332         /* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
3333         psr_context->phyType = PHY_TYPE_UNIPHY;
3334         /*PhyId is associated with the transmitter id*/
3335         psr_context->smuPhyId =
3336                 transmitter_to_phy_id(link->link_enc->transmitter);
3337
3338         psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
3339         psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
3340                                         timing.pix_clk_100hz * 100),
3341                                         stream->timing.v_total),
3342                                         stream->timing.h_total);
3343
3344         psr_context->psrSupportedDisplayConfig = true;
3345         psr_context->psrExitLinkTrainingRequired =
3346                 psr_config->psr_exit_link_training_required;
3347         psr_context->sdpTransmitLineNumDeadline =
3348                 psr_config->psr_sdp_transmit_line_num_deadline;
3349         psr_context->psrFrameCaptureIndicationReq =
3350                 psr_config->psr_frame_capture_indication_req;
3351
3352         psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
3353
3354         psr_context->numberOfControllers =
3355                         link->dc->res_pool->timing_generator_count;
3356
3357         psr_context->rfb_update_auto_en = true;
3358
3359         /* 2 frames before enter PSR. */
3360         psr_context->timehyst_frames = 2;
3361         /* half a frame
3362          * (units in 100 lines, i.e. a value of 1 represents 100 lines)
3363          */
3364         psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
3365         psr_context->aux_repeats = 10;
3366
3367         psr_context->psr_level.u32all = 0;
3368
3369         /*skip power down the single pipe since it blocks the cstate*/
3370 #if defined(CONFIG_DRM_AMD_DC_DCN)
3371         if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
3372                 switch(link->ctx->asic_id.chip_family) {
3373                 case FAMILY_YELLOW_CARP:
3374                 case AMDGPU_FAMILY_GC_10_3_6:
3375                 case AMDGPU_FAMILY_GC_11_0_2:
3376                         if(!dc->debug.disable_z10)
3377                                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false;
3378                         break;
3379                 default:
3380                         psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3381                         break;
3382                 }
3383         }
3384 #else
3385         if (link->ctx->asic_id.chip_family >= FAMILY_RV)
3386                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3387 #endif
3388
3389         /* SMU will perform additional powerdown sequence.
3390          * For unsupported ASICs, set psr_level flag to skip PSR
3391          *  static screen notification to SMU.
3392          *  (Always set for DAL2, did not check ASIC)
3393          */
3394         psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
3395         psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
3396
3397         /* Complete PSR entry before aborting to prevent intermittent
3398          * freezes on certain eDPs
3399          */
3400         psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
3401
3402         /* enable ALPM */
3403         psr_context->psr_level.bits.DISABLE_ALPM = 0;
3404         psr_context->psr_level.bits.ALPM_DEFAULT_PD_MODE = 1;
3405
3406         /* Controls additional delay after remote frame capture before
3407          * continuing power down, default = 0
3408          */
3409         psr_context->frame_delay = 0;
3410
3411         if (psr) {
3412                 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
3413                         link, psr_context, panel_inst);
3414                 link->psr_settings.psr_power_opt = 0;
3415                 link->psr_settings.psr_allow_active = 0;
3416         }
3417         else
3418                 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
3419
3420         /* psr_enabled == 0 indicates setup_psr did not succeed, but this
3421          * should not happen since firmware should be running at this point
3422          */
3423         if (link->psr_settings.psr_feature_enabled == 0)
3424                 ASSERT(0);
3425
3426         return true;
3427
3428 }
3429
3430 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
3431 {
3432         struct dc  *dc = link->ctx->dc;
3433         struct dmub_psr *psr = dc->res_pool->psr;
3434         unsigned int panel_inst;
3435
3436         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3437                 return;
3438
3439         /* PSR residency measurements only supported on DMCUB */
3440         if (psr != NULL && link->psr_settings.psr_feature_enabled)
3441                 psr->funcs->psr_get_residency(psr, residency, panel_inst);
3442         else
3443                 *residency = 0;
3444 }
3445
3446 bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link, uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
3447 {
3448         struct dc *dc = link->ctx->dc;
3449         struct dmub_psr *psr = dc->res_pool->psr;
3450
3451         if (psr == NULL || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support)
3452                 return false;
3453
3454         psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su);
3455
3456         return true;
3457 }
3458
3459 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
3460 {
3461         return &link->link_status;
3462 }
3463
3464 void core_link_resume(struct dc_link *link)
3465 {
3466         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
3467                 program_hpd_filter(link);
3468 }
3469
3470 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
3471 {
3472         struct fixed31_32 mbytes_per_sec;
3473         uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
3474                         &stream->link->cur_link_settings);
3475         link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
3476
3477         mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
3478
3479         return dc_fixpt_div_int(mbytes_per_sec, 54);
3480 }
3481
3482 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
3483 {
3484         struct fixed31_32 peak_kbps;
3485         uint32_t numerator = 0;
3486         uint32_t denominator = 1;
3487
3488         /*
3489          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
3490          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
3491          * common multiplier to render an integer PBN for all link rate/lane
3492          * counts combinations
3493          * calculate
3494          * peak_kbps *= (1006/1000)
3495          * peak_kbps *= (64/54)
3496          * peak_kbps *= 8    convert to bytes
3497          */
3498
3499         numerator = 64 * PEAK_FACTOR_X1000;
3500         denominator = 54 * 8 * 1000 * 1000;
3501         kbps *= numerator;
3502         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
3503
3504         return peak_kbps;
3505 }
3506
3507 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
3508 {
3509         uint64_t kbps;
3510
3511         kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
3512         return get_pbn_from_bw_in_kbps(kbps);
3513 }
3514
3515 static void update_mst_stream_alloc_table(
3516         struct dc_link *link,
3517         struct stream_encoder *stream_enc,
3518         struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc?
3519         const struct dp_mst_stream_allocation_table *proposed_table)
3520 {
3521         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 };
3522         struct link_mst_stream_allocation *dc_alloc;
3523
3524         int i;
3525         int j;
3526
3527         /* if DRM proposed_table has more than one new payload */
3528         ASSERT(proposed_table->stream_count -
3529                         link->mst_stream_alloc_table.stream_count < 2);
3530
3531         /* copy proposed_table to link, add stream encoder */
3532         for (i = 0; i < proposed_table->stream_count; i++) {
3533
3534                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
3535                         dc_alloc =
3536                         &link->mst_stream_alloc_table.stream_allocations[j];
3537
3538                         if (dc_alloc->vcp_id ==
3539                                 proposed_table->stream_allocations[i].vcp_id) {
3540
3541                                 work_table[i] = *dc_alloc;
3542                                 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
3543                                 break; /* exit j loop */
3544                         }
3545                 }
3546
3547                 /* new vcp_id */
3548                 if (j == link->mst_stream_alloc_table.stream_count) {
3549                         work_table[i].vcp_id =
3550                                 proposed_table->stream_allocations[i].vcp_id;
3551                         work_table[i].slot_count =
3552                                 proposed_table->stream_allocations[i].slot_count;
3553                         work_table[i].stream_enc = stream_enc;
3554                         work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc;
3555                 }
3556         }
3557
3558         /* update link->mst_stream_alloc_table with work_table */
3559         link->mst_stream_alloc_table.stream_count =
3560                         proposed_table->stream_count;
3561         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
3562                 link->mst_stream_alloc_table.stream_allocations[i] =
3563                                 work_table[i];
3564 }
3565
3566 static void dc_log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp)
3567 {
3568         const uint32_t VCP_Y_PRECISION = 1000;
3569         uint64_t vcp_x, vcp_y;
3570
3571         // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision
3572         avg_time_slots_per_mtp = dc_fixpt_add(
3573                         avg_time_slots_per_mtp, dc_fixpt_from_fraction(1, 2 * VCP_Y_PRECISION));
3574
3575         vcp_x = dc_fixpt_floor(avg_time_slots_per_mtp);
3576         vcp_y = dc_fixpt_floor(
3577                         dc_fixpt_mul_int(
3578                                 dc_fixpt_sub_int(avg_time_slots_per_mtp, dc_fixpt_floor(avg_time_slots_per_mtp)),
3579                                 VCP_Y_PRECISION));
3580
3581         if (link->type == dc_connection_mst_branch)
3582                 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream "
3583                                 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3584         else
3585                 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream "
3586                                 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3587 }
3588
3589 /*
3590  * Payload allocation/deallocation for SST introduced in DP2.0
3591  */
3592 static enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx,
3593                                                  bool allocate)
3594 {
3595         struct dc_stream_state *stream = pipe_ctx->stream;
3596         struct dc_link *link = stream->link;
3597         struct link_mst_stream_allocation_table proposed_table = {0};
3598         struct fixed31_32 avg_time_slots_per_mtp;
3599         const struct dc_link_settings empty_link_settings = {0};
3600         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3601         DC_LOGGER_INIT(link->ctx->logger);
3602
3603         /* slot X.Y for SST payload deallocate */
3604         if (!allocate) {
3605                 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3606
3607                 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3608
3609                 if (link_hwss->ext.set_throttled_vcp_size)
3610                         link_hwss->ext.set_throttled_vcp_size(pipe_ctx,
3611                                         avg_time_slots_per_mtp);
3612                 if (link_hwss->ext.set_hblank_min_symbol_width)
3613                         link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3614                                         &empty_link_settings,
3615                                         avg_time_slots_per_mtp);
3616         }
3617
3618         /* calculate VC payload and update branch with new payload allocation table*/
3619         if (!dpcd_write_128b_132b_sst_payload_allocation_table(
3620                         stream,
3621                         link,
3622                         &proposed_table,
3623                         allocate)) {
3624                 DC_LOG_ERROR("SST Update Payload: Failed to update "
3625                                                 "allocation table for "
3626                                                 "pipe idx: %d\n",
3627                                                 pipe_ctx->pipe_idx);
3628                 return DC_FAIL_DP_PAYLOAD_ALLOCATION;
3629         }
3630
3631         proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
3632
3633         ASSERT(proposed_table.stream_count == 1);
3634
3635         //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id
3636         DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p      "
3637                 "vcp_id: %d      "
3638                 "slot_count: %d\n",
3639                 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc,
3640                 proposed_table.stream_allocations[0].vcp_id,
3641                 proposed_table.stream_allocations[0].slot_count);
3642
3643         /* program DP source TX for payload */
3644         link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
3645                         &proposed_table);
3646
3647         /* poll for ACT handled */
3648         if (!dpcd_poll_for_allocation_change_trigger(link)) {
3649                 // Failures will result in blackscreen and errors logged
3650                 BREAK_TO_DEBUGGER();
3651         }
3652
3653         /* slot X.Y for SST payload allocate */
3654         if (allocate && dp_get_link_encoding_format(&link->cur_link_settings) ==
3655                         DP_128b_132b_ENCODING) {
3656                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
3657
3658                 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3659
3660                 if (link_hwss->ext.set_throttled_vcp_size)
3661                         link_hwss->ext.set_throttled_vcp_size(pipe_ctx,
3662                                         avg_time_slots_per_mtp);
3663                 if (link_hwss->ext.set_hblank_min_symbol_width)
3664                         link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3665                                         &link->cur_link_settings,
3666                                         avg_time_slots_per_mtp);
3667         }
3668
3669         /* Always return DC_OK.
3670          * If part of sequence fails, log failure(s) and show blackscreen
3671          */
3672         return DC_OK;
3673 }
3674
3675 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
3676  * because stream_encoder is not exposed to dm
3677  */
3678 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
3679 {
3680         struct dc_stream_state *stream = pipe_ctx->stream;
3681         struct dc_link *link = stream->link;
3682         struct dp_mst_stream_allocation_table proposed_table = {0};
3683         struct fixed31_32 avg_time_slots_per_mtp;
3684         struct fixed31_32 pbn;
3685         struct fixed31_32 pbn_per_slot;
3686         int i;
3687         enum act_return_status ret;
3688         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3689         DC_LOGGER_INIT(link->ctx->logger);
3690
3691         /* enable_link_dp_mst already check link->enabled_stream_count
3692          * and stream is in link->stream[]. This is called during set mode,
3693          * stream_enc is available.
3694          */
3695
3696         /* get calculate VC payload for stream: stream_alloc */
3697         if (dm_helpers_dp_mst_write_payload_allocation_table(
3698                 stream->ctx,
3699                 stream,
3700                 &proposed_table,
3701                 true))
3702                 update_mst_stream_alloc_table(
3703                                         link,
3704                                         pipe_ctx->stream_res.stream_enc,
3705                                         pipe_ctx->stream_res.hpo_dp_stream_enc,
3706                                         &proposed_table);
3707         else
3708                 DC_LOG_WARNING("Failed to update"
3709                                 "MST allocation table for"
3710                                 "pipe idx:%d\n",
3711                                 pipe_ctx->pipe_idx);
3712
3713         DC_LOG_MST("%s  "
3714                         "stream_count: %d: \n ",
3715                         __func__,
3716                         link->mst_stream_alloc_table.stream_count);
3717
3718         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3719                 DC_LOG_MST("stream_enc[%d]: %p      "
3720                 "stream[%d].hpo_dp_stream_enc: %p      "
3721                 "stream[%d].vcp_id: %d      "
3722                 "stream[%d].slot_count: %d\n",
3723                 i,
3724                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3725                 i,
3726                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3727                 i,
3728                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3729                 i,
3730                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3731         }
3732
3733         ASSERT(proposed_table.stream_count > 0);
3734
3735         /* program DP source TX for payload */
3736         if (link_hwss->ext.update_stream_allocation_table == NULL ||
3737                         dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
3738                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3739                 return DC_ERROR_UNEXPECTED;
3740         }
3741
3742         link_hwss->ext.update_stream_allocation_table(link,
3743                         &pipe_ctx->link_res,
3744                         &link->mst_stream_alloc_table);
3745
3746         /* send down message */
3747         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3748                         stream->ctx,
3749                         stream);
3750
3751         if (ret != ACT_LINK_LOST) {
3752                 dm_helpers_dp_mst_send_payload_allocation(
3753                                 stream->ctx,
3754                                 stream,
3755                                 true);
3756         }
3757
3758         /* slot X.Y for only current stream */
3759         pbn_per_slot = get_pbn_per_slot(stream);
3760         if (pbn_per_slot.value == 0) {
3761                 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
3762                 return DC_UNSUPPORTED_VALUE;
3763         }
3764         pbn = get_pbn_from_timing(pipe_ctx);
3765         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3766
3767         dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3768
3769         if (link_hwss->ext.set_throttled_vcp_size)
3770                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3771         if (link_hwss->ext.set_hblank_min_symbol_width)
3772                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3773                                 &link->cur_link_settings,
3774                                 avg_time_slots_per_mtp);
3775
3776         return DC_OK;
3777
3778 }
3779
3780 enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3781 {
3782         struct dc_stream_state *stream = pipe_ctx->stream;
3783         struct dc_link *link = stream->link;
3784         struct fixed31_32 avg_time_slots_per_mtp;
3785         struct fixed31_32 pbn;
3786         struct fixed31_32 pbn_per_slot;
3787         struct dp_mst_stream_allocation_table proposed_table = {0};
3788         uint8_t i;
3789         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3790         DC_LOGGER_INIT(link->ctx->logger);
3791
3792         /* decrease throttled vcp size */
3793         pbn_per_slot = get_pbn_per_slot(stream);
3794         pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3795         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3796
3797         if (link_hwss->ext.set_throttled_vcp_size)
3798                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3799         if (link_hwss->ext.set_hblank_min_symbol_width)
3800                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3801                                 &link->cur_link_settings,
3802                                 avg_time_slots_per_mtp);
3803
3804         /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3805         dm_helpers_dp_mst_send_payload_allocation(
3806                         stream->ctx,
3807                         stream,
3808                         true);
3809
3810         /* notify immediate branch device table update */
3811         if (dm_helpers_dp_mst_write_payload_allocation_table(
3812                         stream->ctx,
3813                         stream,
3814                         &proposed_table,
3815                         true)) {
3816                 /* update mst stream allocation table software state */
3817                 update_mst_stream_alloc_table(
3818                                 link,
3819                                 pipe_ctx->stream_res.stream_enc,
3820                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3821                                 &proposed_table);
3822         } else {
3823                 DC_LOG_WARNING("Failed to update"
3824                                 "MST allocation table for"
3825                                 "pipe idx:%d\n",
3826                                 pipe_ctx->pipe_idx);
3827         }
3828
3829         DC_LOG_MST("%s  "
3830                         "stream_count: %d: \n ",
3831                         __func__,
3832                         link->mst_stream_alloc_table.stream_count);
3833
3834         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3835                 DC_LOG_MST("stream_enc[%d]: %p      "
3836                                 "stream[%d].hpo_dp_stream_enc: %p      "
3837                                 "stream[%d].vcp_id: %d      "
3838                                 "stream[%d].slot_count: %d\n",
3839                                 i,
3840                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3841                                 i,
3842                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3843                                 i,
3844                                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3845                                 i,
3846                                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3847         }
3848
3849         ASSERT(proposed_table.stream_count > 0);
3850
3851         /* update mst stream allocation table hardware state */
3852         if (link_hwss->ext.update_stream_allocation_table == NULL ||
3853                         dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
3854                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3855                 return DC_ERROR_UNEXPECTED;
3856         }
3857
3858         link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
3859                         &link->mst_stream_alloc_table);
3860
3861         /* poll for immediate branch device ACT handled */
3862         dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3863                         stream->ctx,
3864                         stream);
3865
3866         return DC_OK;
3867 }
3868
3869 enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3870 {
3871         struct dc_stream_state *stream = pipe_ctx->stream;
3872         struct dc_link *link = stream->link;
3873         struct fixed31_32 avg_time_slots_per_mtp;
3874         struct fixed31_32 pbn;
3875         struct fixed31_32 pbn_per_slot;
3876         struct dp_mst_stream_allocation_table proposed_table = {0};
3877         uint8_t i;
3878         enum act_return_status ret;
3879         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3880         DC_LOGGER_INIT(link->ctx->logger);
3881
3882         /* notify immediate branch device table update */
3883         if (dm_helpers_dp_mst_write_payload_allocation_table(
3884                                 stream->ctx,
3885                                 stream,
3886                                 &proposed_table,
3887                                 true)) {
3888                 /* update mst stream allocation table software state */
3889                 update_mst_stream_alloc_table(
3890                                 link,
3891                                 pipe_ctx->stream_res.stream_enc,
3892                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3893                                 &proposed_table);
3894         }
3895
3896         DC_LOG_MST("%s  "
3897                         "stream_count: %d: \n ",
3898                         __func__,
3899                         link->mst_stream_alloc_table.stream_count);
3900
3901         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3902                 DC_LOG_MST("stream_enc[%d]: %p      "
3903                                 "stream[%d].hpo_dp_stream_enc: %p      "
3904                                 "stream[%d].vcp_id: %d      "
3905                                 "stream[%d].slot_count: %d\n",
3906                                 i,
3907                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3908                                 i,
3909                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3910                                 i,
3911                                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3912                                 i,
3913                                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3914         }
3915
3916         ASSERT(proposed_table.stream_count > 0);
3917
3918         /* update mst stream allocation table hardware state */
3919         if (link_hwss->ext.update_stream_allocation_table == NULL ||
3920                         dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
3921                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3922                 return DC_ERROR_UNEXPECTED;
3923         }
3924
3925         link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
3926                         &link->mst_stream_alloc_table);
3927
3928         /* poll for immediate branch device ACT handled */
3929         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3930                         stream->ctx,
3931                         stream);
3932
3933         if (ret != ACT_LINK_LOST) {
3934                 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3935                 dm_helpers_dp_mst_send_payload_allocation(
3936                                 stream->ctx,
3937                                 stream,
3938                                 true);
3939         }
3940
3941         /* increase throttled vcp size */
3942         pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3943         pbn_per_slot = get_pbn_per_slot(stream);
3944         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3945
3946         if (link_hwss->ext.set_throttled_vcp_size)
3947                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3948         if (link_hwss->ext.set_hblank_min_symbol_width)
3949                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3950                                 &link->cur_link_settings,
3951                                 avg_time_slots_per_mtp);
3952
3953         return DC_OK;
3954 }
3955
3956 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
3957 {
3958         struct dc_stream_state *stream = pipe_ctx->stream;
3959         struct dc_link *link = stream->link;
3960         struct dp_mst_stream_allocation_table proposed_table = {0};
3961         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3962         int i;
3963         bool mst_mode = (link->type == dc_connection_mst_branch);
3964         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3965         const struct dc_link_settings empty_link_settings = {0};
3966         DC_LOGGER_INIT(link->ctx->logger);
3967
3968         /* deallocate_mst_payload is called before disable link. When mode or
3969          * disable/enable monitor, new stream is created which is not in link
3970          * stream[] yet. For this, payload is not allocated yet, so de-alloc
3971          * should not done. For new mode set, map_resources will get engine
3972          * for new stream, so stream_enc->id should be validated until here.
3973          */
3974
3975         /* slot X.Y */
3976         if (link_hwss->ext.set_throttled_vcp_size)
3977                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3978         if (link_hwss->ext.set_hblank_min_symbol_width)
3979                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3980                                 &empty_link_settings,
3981                                 avg_time_slots_per_mtp);
3982
3983         /* TODO: which component is responsible for remove payload table? */
3984         if (mst_mode) {
3985                 if (dm_helpers_dp_mst_write_payload_allocation_table(
3986                                 stream->ctx,
3987                                 stream,
3988                                 &proposed_table,
3989                                 false)) {
3990
3991                         update_mst_stream_alloc_table(
3992                                                 link,
3993                                                 pipe_ctx->stream_res.stream_enc,
3994                                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3995                                                 &proposed_table);
3996                 }
3997                 else {
3998                                 DC_LOG_WARNING("Failed to update"
3999                                                 "MST allocation table for"
4000                                                 "pipe idx:%d\n",
4001                                                 pipe_ctx->pipe_idx);
4002                 }
4003         }
4004
4005         DC_LOG_MST("%s"
4006                         "stream_count: %d: ",
4007                         __func__,
4008                         link->mst_stream_alloc_table.stream_count);
4009
4010         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
4011                 DC_LOG_MST("stream_enc[%d]: %p      "
4012                 "stream[%d].hpo_dp_stream_enc: %p      "
4013                 "stream[%d].vcp_id: %d      "
4014                 "stream[%d].slot_count: %d\n",
4015                 i,
4016                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
4017                 i,
4018                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
4019                 i,
4020                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
4021                 i,
4022                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
4023         }
4024
4025         /* update mst stream allocation table hardware state */
4026         if (link_hwss->ext.update_stream_allocation_table == NULL ||
4027                         dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
4028                 DC_LOG_DEBUG("Unknown encoding format\n");
4029                 return DC_ERROR_UNEXPECTED;
4030         }
4031
4032         link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
4033                         &link->mst_stream_alloc_table);
4034
4035         if (mst_mode) {
4036                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
4037                         stream->ctx,
4038                         stream);
4039
4040                 dm_helpers_dp_mst_send_payload_allocation(
4041                         stream->ctx,
4042                         stream,
4043                         false);
4044         }
4045
4046         return DC_OK;
4047 }
4048
4049
4050 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4051 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
4052 {
4053         struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
4054         struct link_encoder *link_enc = NULL;
4055         struct cp_psp_stream_config config = {0};
4056         enum dp_panel_mode panel_mode =
4057                         dp_get_panel_mode(pipe_ctx->stream->link);
4058
4059         if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL)
4060                 return;
4061
4062         link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
4063         ASSERT(link_enc);
4064         if (link_enc == NULL)
4065                 return;
4066
4067         /* otg instance */
4068         config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
4069
4070         /* dig front end */
4071         config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
4072
4073         /* stream encoder index */
4074         config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
4075         if (is_dp_128b_132b_signal(pipe_ctx))
4076                 config.stream_enc_idx =
4077                                 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;
4078
4079         /* dig back end */
4080         config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
4081
4082         /* link encoder index */
4083         config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4084         if (is_dp_128b_132b_signal(pipe_ctx))
4085                 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst;
4086
4087         /* dio output index is dpia index for DPIA endpoint & dcio index by default */
4088         if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
4089                 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1;
4090         else
4091                 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4092
4093
4094         /* phy index */
4095         config.phy_idx = resource_transmitter_to_phy_idx(
4096                         pipe_ctx->stream->link->dc, link_enc->transmitter);
4097         if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
4098                 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */
4099                 config.phy_idx = 0;
4100
4101         /* stream properties */
4102         config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0;
4103         config.mst_enabled = (pipe_ctx->stream->signal ==
4104                         SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0;
4105         config.dp2_enabled = is_dp_128b_132b_signal(pipe_ctx) ? 1 : 0;
4106         config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ?
4107                         1 : 0;
4108         config.dpms_off = dpms_off;
4109
4110         /* dm stream context */
4111         config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
4112
4113         cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
4114 }
4115 #endif
4116
4117 static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pipe_ctx *pipe_ctx)
4118 {
4119         struct dc *dc = pipe_ctx->stream->ctx->dc;
4120         struct dc_stream_state *stream = pipe_ctx->stream;
4121         struct link_mst_stream_allocation_table proposed_table = {0};
4122         struct fixed31_32 avg_time_slots_per_mtp;
4123         uint8_t req_slot_count = 0;
4124         uint8_t vc_id = 1; /// VC ID always 1 for SST
4125         struct dc_link_settings link_settings = pipe_ctx->link_config.dp_link_settings;
4126         const struct link_hwss *link_hwss = get_link_hwss(stream->link, &pipe_ctx->link_res);
4127         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4128
4129         stream->link->cur_link_settings = link_settings;
4130
4131         if (link_hwss->ext.enable_dp_link_output)
4132                 link_hwss->ext.enable_dp_link_output(stream->link, &pipe_ctx->link_res,
4133                                 stream->signal, pipe_ctx->clock_source->id,
4134                                 &link_settings);
4135
4136 #ifdef DIAGS_BUILD
4137         /* Workaround for FPGA HPO capture DP link data:
4138          * HPO capture will set link to active mode
4139          * This workaround is required to get a capture from start of frame
4140          */
4141         if (!dc->debug.fpga_hpo_capture_en) {
4142                 struct encoder_set_dp_phy_pattern_param params = {0};
4143                 params.dp_phy_pattern = DP_TEST_PATTERN_VIDEO_MODE;
4144
4145                 /* Set link active */
4146                 stream->link->hpo_dp_link_enc->funcs->set_link_test_pattern(
4147                                 stream->link->hpo_dp_link_enc,
4148                                 &params);
4149         }
4150 #endif
4151
4152         /* Enable DP_STREAM_ENC */
4153         dc->hwss.enable_stream(pipe_ctx);
4154
4155         /* Set DPS PPS SDP (AKA "info frames") */
4156         if (pipe_ctx->stream->timing.flags.DSC) {
4157                 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4158         }
4159
4160         /* Allocate Payload */
4161         if ((stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) && (state->stream_count > 1)) {
4162                 // MST case
4163                 uint8_t i;
4164
4165                 proposed_table.stream_count = state->stream_count;
4166                 for (i = 0; i < state->stream_count; i++) {
4167                         avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(state->streams[i], state->streams[i]->link);
4168                         req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4169                         proposed_table.stream_allocations[i].slot_count = req_slot_count;
4170                         proposed_table.stream_allocations[i].vcp_id = i+1;
4171                         /* NOTE: This makes assumption that pipe_ctx index is same as stream index */
4172                         proposed_table.stream_allocations[i].hpo_dp_stream_enc = state->res_ctx.pipe_ctx[i].stream_res.hpo_dp_stream_enc;
4173                 }
4174         } else {
4175                 // SST case
4176                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, stream->link);
4177                 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4178                 proposed_table.stream_count = 1; /// Always 1 stream for SST
4179                 proposed_table.stream_allocations[0].slot_count = req_slot_count;
4180                 proposed_table.stream_allocations[0].vcp_id = vc_id;
4181                 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
4182         }
4183
4184         link_hwss->ext.update_stream_allocation_table(stream->link,
4185                         &pipe_ctx->link_res,
4186                         &proposed_table);
4187
4188         if (link_hwss->ext.set_throttled_vcp_size)
4189                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
4190
4191         dc->hwss.unblank_stream(pipe_ctx, &stream->link->cur_link_settings);
4192 }
4193
4194 void core_link_enable_stream(
4195                 struct dc_state *state,
4196                 struct pipe_ctx *pipe_ctx)
4197 {
4198         struct dc *dc = pipe_ctx->stream->ctx->dc;
4199         struct dc_stream_state *stream = pipe_ctx->stream;
4200         struct dc_link *link = stream->sink->link;
4201         enum dc_status status;
4202         struct link_encoder *link_enc;
4203         enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
4204         struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4205         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
4206
4207         if (is_dp_128b_132b_signal(pipe_ctx))
4208                 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4209
4210         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4211
4212         if (pipe_ctx->stream->sink) {
4213                 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
4214                         pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
4215                         DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
4216                         pipe_ctx->stream->sink->edid_caps.display_name,
4217                         pipe_ctx->stream->signal);
4218                 }
4219         }
4220
4221         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4222                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4223                 return;
4224
4225         link_enc = link_enc_cfg_get_link_enc(link);
4226         ASSERT(link_enc);
4227
4228         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)
4229                         && !is_dp_128b_132b_signal(pipe_ctx)) {
4230                 if (link_enc)
4231                         link_enc->funcs->setup(
4232                                 link_enc,
4233                                 pipe_ctx->stream->signal);
4234         }
4235
4236         pipe_ctx->stream->link->link_state_valid = true;
4237
4238         if (pipe_ctx->stream_res.tg->funcs->set_out_mux) {
4239                 if (is_dp_128b_132b_signal(pipe_ctx))
4240                         otg_out_dest = OUT_MUX_HPO_DP;
4241                 else
4242                         otg_out_dest = OUT_MUX_DIO;
4243                 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
4244         }
4245
4246         link_hwss->setup_stream_attribute(pipe_ctx);
4247
4248         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
4249                 bool apply_edp_fast_boot_optimization =
4250                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
4251
4252                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
4253
4254                 // Enable VPG before building infoframe
4255                 if (vpg && vpg->funcs->vpg_poweron)
4256                         vpg->funcs->vpg_poweron(vpg);
4257
4258                 resource_build_info_frame(pipe_ctx);
4259                 dc->hwss.update_info_frame(pipe_ctx);
4260
4261                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4262                         dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
4263
4264                 /* Do not touch link on seamless boot optimization. */
4265                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
4266                         pipe_ctx->stream->dpms_off = false;
4267
4268                         /* Still enable stream features & audio on seamless boot for DP external displays */
4269                         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
4270                                 enable_stream_features(pipe_ctx);
4271                                 if (pipe_ctx->stream_res.audio != NULL) {
4272                                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
4273                                         dc->hwss.enable_audio_stream(pipe_ctx);
4274                                 }
4275                         }
4276
4277 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4278                         update_psp_stream_config(pipe_ctx, false);
4279 #endif
4280                         return;
4281                 }
4282
4283                 /* eDP lit up by bios already, no need to enable again. */
4284                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
4285                                         apply_edp_fast_boot_optimization &&
4286                                         !pipe_ctx->stream->timing.flags.DSC &&
4287                                         !pipe_ctx->next_odm_pipe) {
4288                         pipe_ctx->stream->dpms_off = false;
4289 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4290                         update_psp_stream_config(pipe_ctx, false);
4291 #endif
4292                         return;
4293                 }
4294
4295                 if (pipe_ctx->stream->dpms_off)
4296                         return;
4297
4298                 /* Have to setup DSC before DIG FE and BE are connected (which happens before the
4299                  * link training). This is to make sure the bandwidth sent to DIG BE won't be
4300                  * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
4301                  * will be automatically set at a later time when the video is enabled
4302                  * (DP_VID_STREAM_EN = 1).
4303                  */
4304                 if (pipe_ctx->stream->timing.flags.DSC) {
4305                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4306                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4307                                 dp_set_dsc_enable(pipe_ctx, true);
4308                 }
4309
4310                 status = enable_link(state, pipe_ctx);
4311
4312                 if (status != DC_OK) {
4313                         DC_LOG_WARNING("enabling link %u failed: %d\n",
4314                         pipe_ctx->stream->link->link_index,
4315                         status);
4316
4317                         /* Abort stream enable *unless* the failure was due to
4318                          * DP link training - some DP monitors will recover and
4319                          * show the stream anyway. But MST displays can't proceed
4320                          * without link training.
4321                          */
4322                         if (status != DC_FAIL_DP_LINK_TRAINING ||
4323                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
4324                                 if (false == stream->link->link_status.link_active)
4325                                         disable_link(stream->link, &pipe_ctx->link_res,
4326                                                         pipe_ctx->stream->signal);
4327                                 BREAK_TO_DEBUGGER();
4328                                 return;
4329                         }
4330                 }
4331
4332                 /* turn off otg test pattern if enable */
4333                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4334                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4335                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4336                                         COLOR_DEPTH_UNDEFINED);
4337
4338                 /* This second call is needed to reconfigure the DIG
4339                  * as a workaround for the incorrect value being applied
4340                  * from transmitter control.
4341                  */
4342                 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) ||
4343                                 is_dp_128b_132b_signal(pipe_ctx)))
4344                         if (link_enc)
4345                                 link_enc->funcs->setup(
4346                                         link_enc,
4347                                         pipe_ctx->stream->signal);
4348
4349                 dc->hwss.enable_stream(pipe_ctx);
4350
4351                 /* Set DPS PPS SDP (AKA "info frames") */
4352                 if (pipe_ctx->stream->timing.flags.DSC) {
4353                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4354                                         dc_is_virtual_signal(pipe_ctx->stream->signal)) {
4355                                 dp_set_dsc_on_rx(pipe_ctx, true);
4356                                 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4357                         }
4358                 }
4359
4360                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4361                         dc_link_allocate_mst_payload(pipe_ctx);
4362                 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4363                                 is_dp_128b_132b_signal(pipe_ctx))
4364                         dc_link_update_sst_payload(pipe_ctx, true);
4365
4366                 dc->hwss.unblank_stream(pipe_ctx,
4367                         &pipe_ctx->stream->link->cur_link_settings);
4368
4369                 if (stream->sink_patches.delay_ignore_msa > 0)
4370                         msleep(stream->sink_patches.delay_ignore_msa);
4371
4372                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4373                         enable_stream_features(pipe_ctx);
4374 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4375                 update_psp_stream_config(pipe_ctx, false);
4376 #endif
4377
4378                 dc->hwss.enable_audio_stream(pipe_ctx);
4379
4380         } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
4381                 if (is_dp_128b_132b_signal(pipe_ctx))
4382                         fpga_dp_hpo_enable_link_and_stream(state, pipe_ctx);
4383                 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4384                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
4385                         dp_set_dsc_enable(pipe_ctx, true);
4386         }
4387
4388         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
4389                 core_link_set_avmute(pipe_ctx, false);
4390         }
4391 }
4392
4393 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
4394 {
4395         struct dc  *dc = pipe_ctx->stream->ctx->dc;
4396         struct dc_stream_state *stream = pipe_ctx->stream;
4397         struct dc_link *link = stream->sink->link;
4398         struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4399
4400         if (is_dp_128b_132b_signal(pipe_ctx))
4401                 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4402
4403         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4404
4405         if (pipe_ctx->stream->sink) {
4406                 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
4407                         pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
4408                         DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
4409                         pipe_ctx->stream->sink->edid_caps.display_name,
4410                         pipe_ctx->stream->signal);
4411                 }
4412         }
4413
4414         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4415                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4416                 return;
4417
4418         if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
4419                 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
4420                         core_link_set_avmute(pipe_ctx, true);
4421         }
4422
4423         dc->hwss.disable_audio_stream(pipe_ctx);
4424
4425 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4426         update_psp_stream_config(pipe_ctx, true);
4427 #endif
4428         dc->hwss.blank_stream(pipe_ctx);
4429
4430         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4431                 deallocate_mst_payload(pipe_ctx);
4432         else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4433                         is_dp_128b_132b_signal(pipe_ctx))
4434                 dc_link_update_sst_payload(pipe_ctx, false);
4435
4436         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
4437                 struct ext_hdmi_settings settings = {0};
4438                 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
4439
4440                 unsigned short masked_chip_caps = link->chip_caps &
4441                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
4442                 //Need to inform that sink is going to use legacy HDMI mode.
4443                 dal_ddc_service_write_scdc_data(
4444                         link->ddc,
4445                         165000,//vbios only handles 165Mhz.
4446                         false);
4447                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
4448                         /* DP159, Retimer settings */
4449                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
4450                                 write_i2c_retimer_setting(pipe_ctx,
4451                                                 false, false, &settings);
4452                         else
4453                                 write_i2c_default_retimer_setting(pipe_ctx,
4454                                                 false, false);
4455                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
4456                         /* PI3EQX1204, Redriver settings */
4457                         write_i2c_redriver_setting(pipe_ctx, false);
4458                 }
4459         }
4460
4461         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4462                         !is_dp_128b_132b_signal(pipe_ctx)) {
4463
4464                 /* In DP1.x SST mode, our encoder will go to TPS1
4465                  * when link is on but stream is off.
4466                  * Disabling link before stream will avoid exposing TPS1 pattern
4467                  * during the disable sequence as it will confuse some receivers
4468                  * state machine.
4469                  * In DP2 or MST mode, our encoder will stay video active
4470                  */
4471                 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
4472                 dc->hwss.disable_stream(pipe_ctx);
4473         } else {
4474                 dc->hwss.disable_stream(pipe_ctx);
4475                 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
4476         }
4477
4478         if (pipe_ctx->stream->timing.flags.DSC) {
4479                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4480                         dp_set_dsc_enable(pipe_ctx, false);
4481         }
4482         if (is_dp_128b_132b_signal(pipe_ctx)) {
4483                 if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
4484                         pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);
4485         }
4486
4487         if (vpg && vpg->funcs->vpg_powerdown)
4488                 vpg->funcs->vpg_powerdown(vpg);
4489 }
4490
4491 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
4492 {
4493         struct dc  *dc = pipe_ctx->stream->ctx->dc;
4494
4495         if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
4496                 return;
4497
4498         dc->hwss.set_avmute(pipe_ctx, enable);
4499 }
4500
4501 /**
4502  *  dc_link_enable_hpd_filter:
4503  *     If enable is true, programs HPD filter on associated HPD line using
4504  *     delay_on_disconnect/delay_on_connect values dependent on
4505  *     link->connector_signal
4506  *
4507  *     If enable is false, programs HPD filter on associated HPD line with no
4508  *     delays on connect or disconnect
4509  *
4510  *  @link:   pointer to the dc link
4511  *  @enable: boolean specifying whether to enable hbd
4512  */
4513 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
4514 {
4515         struct gpio *hpd;
4516
4517         if (enable) {
4518                 link->is_hpd_filter_disabled = false;
4519                 program_hpd_filter(link);
4520         } else {
4521                 link->is_hpd_filter_disabled = true;
4522                 /* Obtain HPD handle */
4523                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
4524
4525                 if (!hpd)
4526                         return;
4527
4528                 /* Setup HPD filtering */
4529                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
4530                         struct gpio_hpd_config config;
4531
4532                         config.delay_on_connect = 0;
4533                         config.delay_on_disconnect = 0;
4534
4535                         dal_irq_setup_hpd_filter(hpd, &config);
4536
4537                         dal_gpio_close(hpd);
4538                 } else {
4539                         ASSERT_CRITICAL(false);
4540                 }
4541                 /* Release HPD handle */
4542                 dal_gpio_destroy_irq(&hpd);
4543         }
4544 }
4545
4546 void dc_link_set_drive_settings(struct dc *dc,
4547                                 struct link_training_settings *lt_settings,
4548                                 const struct dc_link *link)
4549 {
4550
4551         int i;
4552         struct link_resource link_res;
4553
4554         for (i = 0; i < dc->link_count; i++)
4555                 if (dc->links[i] == link)
4556                         break;
4557
4558         if (i >= dc->link_count)
4559                 ASSERT_CRITICAL(false);
4560
4561         dc_link_get_cur_link_res(link, &link_res);
4562         dc_link_dp_set_drive_settings(dc->links[i], &link_res, lt_settings);
4563 }
4564
4565 void dc_link_set_preferred_link_settings(struct dc *dc,
4566                                          struct dc_link_settings *link_setting,
4567                                          struct dc_link *link)
4568 {
4569         int i;
4570         struct pipe_ctx *pipe;
4571         struct dc_stream_state *link_stream;
4572         struct dc_link_settings store_settings = *link_setting;
4573
4574         link->preferred_link_setting = store_settings;
4575
4576         /* Retrain with preferred link settings only relevant for
4577          * DP signal type
4578          * Check for non-DP signal or if passive dongle present
4579          */
4580         if (!dc_is_dp_signal(link->connector_signal) ||
4581                 link->dongle_max_pix_clk > 0)
4582                 return;
4583
4584         for (i = 0; i < MAX_PIPES; i++) {
4585                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4586                 if (pipe->stream && pipe->stream->link) {
4587                         if (pipe->stream->link == link) {
4588                                 link_stream = pipe->stream;
4589                                 break;
4590                         }
4591                 }
4592         }
4593
4594         /* Stream not found */
4595         if (i == MAX_PIPES)
4596                 return;
4597
4598         /* Cannot retrain link if backend is off */
4599         if (link_stream->dpms_off)
4600                 return;
4601
4602         if (decide_link_settings(link_stream, &store_settings))
4603                 dp_retrain_link_dp_test(link, &store_settings, false);
4604 }
4605
4606 void dc_link_set_preferred_training_settings(struct dc *dc,
4607                                                  struct dc_link_settings *link_setting,
4608                                                  struct dc_link_training_overrides *lt_overrides,
4609                                                  struct dc_link *link,
4610                                                  bool skip_immediate_retrain)
4611 {
4612         if (lt_overrides != NULL)
4613                 link->preferred_training_settings = *lt_overrides;
4614         else
4615                 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
4616
4617         if (link_setting != NULL) {
4618                 link->preferred_link_setting = *link_setting;
4619                 if (dp_get_link_encoding_format(link_setting) == DP_128b_132b_ENCODING)
4620                         /* TODO: add dc update for acquiring link res  */
4621                         skip_immediate_retrain = true;
4622         } else {
4623                 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
4624                 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
4625         }
4626
4627         /* Retrain now, or wait until next stream update to apply */
4628         if (skip_immediate_retrain == false)
4629                 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
4630 }
4631
4632 void dc_link_enable_hpd(const struct dc_link *link)
4633 {
4634         dc_link_dp_enable_hpd(link);
4635 }
4636
4637 void dc_link_disable_hpd(const struct dc_link *link)
4638 {
4639         dc_link_dp_disable_hpd(link);
4640 }
4641
4642 void dc_link_set_test_pattern(struct dc_link *link,
4643                               enum dp_test_pattern test_pattern,
4644                               enum dp_test_pattern_color_space test_pattern_color_space,
4645                               const struct link_training_settings *p_link_settings,
4646                               const unsigned char *p_custom_pattern,
4647                               unsigned int cust_pattern_size)
4648 {
4649         if (link != NULL)
4650                 dc_link_dp_set_test_pattern(
4651                         link,
4652                         test_pattern,
4653                         test_pattern_color_space,
4654                         p_link_settings,
4655                         p_custom_pattern,
4656                         cust_pattern_size);
4657 }
4658
4659 uint32_t dc_link_bandwidth_kbps(
4660         const struct dc_link *link,
4661         const struct dc_link_settings *link_setting)
4662 {
4663         uint32_t total_data_bw_efficiency_x10000 = 0;
4664         uint32_t link_rate_per_lane_kbps = 0;
4665
4666         switch (dp_get_link_encoding_format(link_setting)) {
4667         case DP_8b_10b_ENCODING:
4668                 /* For 8b/10b encoding:
4669                  * link rate is defined in the unit of LINK_RATE_REF_FREQ_IN_KHZ per DP byte per lane.
4670                  * data bandwidth efficiency is 80% with additional 3% overhead if FEC is supported.
4671                  */
4672                 link_rate_per_lane_kbps = link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
4673                 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
4674                 if (dc_link_should_enable_fec(link)) {
4675                         total_data_bw_efficiency_x10000 /= 100;
4676                         total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
4677                 }
4678                 break;
4679         case DP_128b_132b_ENCODING:
4680                 /* For 128b/132b encoding:
4681                  * link rate is defined in the unit of 10mbps per lane.
4682                  * total data bandwidth efficiency is always 96.71%.
4683                  */
4684                 link_rate_per_lane_kbps = link_setting->link_rate * 10000;
4685                 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
4686                 break;
4687         default:
4688                 break;
4689         }
4690
4691         /* overall effective link bandwidth = link rate per lane * lane count * total data bandwidth efficiency */
4692         return link_rate_per_lane_kbps * link_setting->lane_count / 10000 * total_data_bw_efficiency_x10000;
4693 }
4694
4695 const struct dc_link_settings *dc_link_get_link_cap(
4696                 const struct dc_link *link)
4697 {
4698         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
4699                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
4700                 return &link->preferred_link_setting;
4701         return &link->verified_link_cap;
4702 }
4703
4704 void dc_link_overwrite_extended_receiver_cap(
4705                 struct dc_link *link)
4706 {
4707         dp_overwrite_extended_receiver_cap(link);
4708 }
4709
4710 bool dc_link_is_fec_supported(const struct dc_link *link)
4711 {
4712         /* TODO - use asic cap instead of link_enc->features
4713          * we no longer know which link enc to use for this link before commit
4714          */
4715         struct link_encoder *link_enc = NULL;
4716
4717         link_enc = link_enc_cfg_get_link_enc(link);
4718         ASSERT(link_enc);
4719
4720         return (dc_is_dp_signal(link->connector_signal) && link_enc &&
4721                         link_enc->features.fec_supported &&
4722                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
4723                         !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
4724 }
4725
4726 bool dc_link_should_enable_fec(const struct dc_link *link)
4727 {
4728         bool force_disable = false;
4729
4730         if (link->fec_state == dc_link_fec_enabled)
4731                 force_disable = false;
4732         else if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
4733                         link->local_sink &&
4734                         link->local_sink->edid_caps.panel_patch.disable_fec)
4735                 force_disable = true;
4736         else if (link->connector_signal == SIGNAL_TYPE_EDP
4737                         && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.
4738                          dsc_support.DSC_SUPPORT == false
4739                                 || link->dc->debug.disable_dsc_edp
4740                                 || !link->dc->caps.edp_dsc_support))
4741                 force_disable = true;
4742
4743         return !force_disable && dc_link_is_fec_supported(link);
4744 }
4745
4746 uint32_t dc_bandwidth_in_kbps_from_timing(
4747                 const struct dc_crtc_timing *timing)
4748 {
4749         uint32_t bits_per_channel = 0;
4750         uint32_t kbps;
4751
4752 #if defined(CONFIG_DRM_AMD_DC_DCN)
4753         if (timing->flags.DSC)
4754                 return dc_dsc_stream_bandwidth_in_kbps(timing,
4755                                 timing->dsc_cfg.bits_per_pixel,
4756                                 timing->dsc_cfg.num_slices_h,
4757                                 timing->dsc_cfg.is_dp);
4758 #endif /* CONFIG_DRM_AMD_DC_DCN */
4759
4760         switch (timing->display_color_depth) {
4761         case COLOR_DEPTH_666:
4762                 bits_per_channel = 6;
4763                 break;
4764         case COLOR_DEPTH_888:
4765                 bits_per_channel = 8;
4766                 break;
4767         case COLOR_DEPTH_101010:
4768                 bits_per_channel = 10;
4769                 break;
4770         case COLOR_DEPTH_121212:
4771                 bits_per_channel = 12;
4772                 break;
4773         case COLOR_DEPTH_141414:
4774                 bits_per_channel = 14;
4775                 break;
4776         case COLOR_DEPTH_161616:
4777                 bits_per_channel = 16;
4778                 break;
4779         default:
4780                 ASSERT(bits_per_channel != 0);
4781                 bits_per_channel = 8;
4782                 break;
4783         }
4784
4785         kbps = timing->pix_clk_100hz / 10;
4786         kbps *= bits_per_channel;
4787
4788         if (timing->flags.Y_ONLY != 1) {
4789                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
4790                 kbps *= 3;
4791                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
4792                         kbps /= 2;
4793                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
4794                         kbps = kbps * 2 / 3;
4795         }
4796
4797         return kbps;
4798
4799 }
4800
4801 void dc_link_get_cur_link_res(const struct dc_link *link,
4802                 struct link_resource *link_res)
4803 {
4804         int i;
4805         struct pipe_ctx *pipe = NULL;
4806
4807         memset(link_res, 0, sizeof(*link_res));
4808
4809         for (i = 0; i < MAX_PIPES; i++) {
4810                 pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];
4811                 if (pipe->stream && pipe->stream->link && pipe->top_pipe == NULL) {
4812                         if (pipe->stream->link == link) {
4813                                 *link_res = pipe->link_res;
4814                                 break;
4815                         }
4816                 }
4817         }
4818
4819 }
4820
4821 /**
4822  * dc_get_cur_link_res_map() - take a snapshot of current link resource allocation state
4823  * @dc: pointer to dc of the dm calling this
4824  * @map: a dc link resource snapshot defined internally to dc.
4825  *
4826  * DM needs to capture a snapshot of current link resource allocation mapping
4827  * and store it in its persistent storage.
4828  *
4829  * Some of the link resource is using first come first serve policy.
4830  * The allocation mapping depends on original hotplug order. This information
4831  * is lost after driver is loaded next time. The snapshot is used in order to
4832  * restore link resource to its previous state so user will get consistent
4833  * link capability allocation across reboot.
4834  *
4835  * Return: none (void function)
4836  *
4837  */
4838 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map)
4839 {
4840         struct dc_link *link;
4841         uint32_t i;
4842         uint32_t hpo_dp_recycle_map = 0;
4843
4844         *map = 0;
4845
4846         if (dc->caps.dp_hpo) {
4847                 for (i = 0; i < dc->caps.max_links; i++) {
4848                         link = dc->links[i];
4849                         if (link->link_status.link_active &&
4850                                         dp_get_link_encoding_format(&link->reported_link_cap) == DP_128b_132b_ENCODING &&
4851                                         dp_get_link_encoding_format(&link->cur_link_settings) != DP_128b_132b_ENCODING)
4852                                 /* hpo dp link encoder is considered as recycled, when RX reports 128b/132b encoding capability
4853                                  * but current link doesn't use it.
4854                                  */
4855                                 hpo_dp_recycle_map |= (1 << i);
4856                 }
4857                 *map |= (hpo_dp_recycle_map << LINK_RES_HPO_DP_REC_MAP__SHIFT);
4858         }
4859 }
4860
4861 /**
4862  * dc_restore_link_res_map() - restore link resource allocation state from a snapshot
4863  * @dc: pointer to dc of the dm calling this
4864  * @map: a dc link resource snapshot defined internally to dc.
4865  *
4866  * DM needs to call this function after initial link detection on boot and
4867  * before first commit streams to restore link resource allocation state
4868  * from previous boot session.
4869  *
4870  * Some of the link resource is using first come first serve policy.
4871  * The allocation mapping depends on original hotplug order. This information
4872  * is lost after driver is loaded next time. The snapshot is used in order to
4873  * restore link resource to its previous state so user will get consistent
4874  * link capability allocation across reboot.
4875  *
4876  * Return: none (void function)
4877  *
4878  */
4879 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map)
4880 {
4881         struct dc_link *link;
4882         uint32_t i;
4883         unsigned int available_hpo_dp_count;
4884         uint32_t hpo_dp_recycle_map = (*map & LINK_RES_HPO_DP_REC_MAP__MASK)
4885                         >> LINK_RES_HPO_DP_REC_MAP__SHIFT;
4886
4887         if (dc->caps.dp_hpo) {
4888                 available_hpo_dp_count = dc->res_pool->hpo_dp_link_enc_count;
4889                 /* remove excess 128b/132b encoding support for not recycled links */
4890                 for (i = 0; i < dc->caps.max_links; i++) {
4891                         if ((hpo_dp_recycle_map & (1 << i)) == 0) {
4892                                 link = dc->links[i];
4893                                 if (link->type != dc_connection_none &&
4894                                                 dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
4895                                         if (available_hpo_dp_count > 0)
4896                                                 available_hpo_dp_count--;
4897                                         else
4898                                                 /* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
4899                                                 link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
4900                                 }
4901                         }
4902                 }
4903                 /* remove excess 128b/132b encoding support for recycled links */
4904                 for (i = 0; i < dc->caps.max_links; i++) {
4905                         if ((hpo_dp_recycle_map & (1 << i)) != 0) {
4906                                 link = dc->links[i];
4907                                 if (link->type != dc_connection_none &&
4908                                                 dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
4909                                         if (available_hpo_dp_count > 0)
4910                                                 available_hpo_dp_count--;
4911                                         else
4912                                                 /* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
4913                                                 link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
4914                                 }
4915                         }
4916                 }
4917         }
4918 }