drivers/gpu/drm/amd/display/dc/core/dc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  */
  24
  25 #include "dm_services.h"
  26
  27 #include "dc.h"
  28
  29 #include "core_status.h"
  30 #include "core_types.h"
  31 #include "hw_sequencer.h"
  32 #include "dce/dce_hwseq.h"
  33
  34 #include "resource.h"
  35
  36 #include "gpio_service_interface.h"
  37 #include "clk_mgr.h"
  38 #include "clock_source.h"
  39 #include "dc_bios_types.h"
  40
  41 #include "bios_parser_interface.h"
  42 #include "bios/bios_parser_helper.h"
  43 #include "include/irq_service_interface.h"
  44 #include "transform.h"
  45 #include "dmcu.h"
  46 #include "dpp.h"
  47 #include "timing_generator.h"
  48 #include "abm.h"
  49 #include "virtual/virtual_link_encoder.h"
  50 #include "hubp.h"
  51
  52 #include "link_hwss.h"
  53 #include "link_encoder.h"
  54 #include "link_enc_cfg.h"
  55
  56 #include "link.h"
  57 #include "dm_helpers.h"
  58 #include "mem_input.h"
  59
  60 #include "dc_dmub_srv.h"
  61
  62 #include "dsc.h"
  63
  64 #include "vm_helper.h"
  65
  66 #include "dce/dce_i2c.h"
  67
  68 #include "dmub/dmub_srv.h"
  69
  70 #include "dce/dmub_psr.h"
  71
  72 #include "dce/dmub_hw_lock_mgr.h"
  73
  74 #include "dc_trace.h"
  75
  76 #include "hw_sequencer_private.h"
  77
  78 #include "dce/dmub_outbox.h"
  79
  80 #define CTX \
  81         dc->ctx
  82
  83 #define DC_LOGGER \
  84         dc->ctx->logger
  85
  86 static const char DC_BUILD_ID[] = "production-build";
  87
  88 /**
  89  * DOC: Overview
  90  *
  91  * DC is the OS-agnostic component of the amdgpu DC driver.
  92  *
  93  * DC maintains and validates a set of structs representing the state of the
  94  * driver and writes that state to AMD hardware
  95  *
  96  * Main DC HW structs:
  97  *
  98  * struct dc - The central struct.  One per driver.  Created on driver load,
  99  * destroyed on driver unload.
 100  *
 101  * struct dc_context - One per driver.
 102  * Used as a backpointer by most other structs in dc.
 103  *
 104  * struct dc_link - One per connector (the physical DP, HDMI, miniDP, or eDP
 105  * plugpoints).  Created on driver load, destroyed on driver unload.
 106  *
 107  * struct dc_sink - One per display.  Created on boot or hotplug.
 108  * Destroyed on shutdown or hotunplug.  A dc_link can have a local sink
 109  * (the display directly attached).  It may also have one or more remote
 110  * sinks (in the Multi-Stream Transport case)
 111  *
 112  * struct resource_pool - One per driver.  Represents the hw blocks not in the
 113  * main pipeline.  Not directly accessible by dm.
 114  *
 115  * Main dc state structs:
 116  *
 117  * These structs can be created and destroyed as needed.  There is a full set of
 118  * these structs in dc->current_state representing the currently programmed state.
 119  *
 120  * struct dc_state - The global DC state to track global state information,
 121  * such as bandwidth values.
 122  *
 123  * struct dc_stream_state - Represents the hw configuration for the pipeline from
 124  * a framebuffer to a display.  Maps one-to-one with dc_sink.
 125  *
 126  * struct dc_plane_state - Represents a framebuffer.  Each stream has at least one,
 127  * and may have more in the Multi-Plane Overlay case.
 128  *
 129  * struct resource_context - Represents the programmable state of everything in
 130  * the resource_pool.  Not directly accessible by dm.
 131  *
 132  * struct pipe_ctx - A member of struct resource_context.  Represents the
 133  * internal hardware pipeline components.  Each dc_plane_state has either
 134  * one or two (in the pipe-split case).
 135  */
 136
 137 /* Private functions */
 138
 139 static inline void elevate_update_type(enum surface_update_type *original, enum surface_update_type new)
 140 {
 141         if (new > *original)
 142                 *original = new;
 143 }
 144
 145 static void destroy_links(struct dc *dc)
 146 {
 147         uint32_t i;
 148
 149         for (i = 0; i < dc->link_count; i++) {
 150                 if (NULL != dc->links[i])
 151                         dc->link_srv->destroy_link(&dc->links[i]);
 152         }
 153 }
 154
 155 static uint32_t get_num_of_internal_disp(struct dc_link **links, uint32_t num_links)
 156 {
 157         int i;
 158         uint32_t count = 0;
 159
 160         for (i = 0; i < num_links; i++) {
 161                 if (links[i]->connector_signal == SIGNAL_TYPE_EDP ||
 162                                 links[i]->is_internal_display)
 163                         count++;
 164         }
 165
 166         return count;
 167 }
 168
 169 static int get_seamless_boot_stream_count(struct dc_state *ctx)
 170 {
 171         uint8_t i;
 172         uint8_t seamless_boot_stream_count = 0;
 173
 174         for (i = 0; i < ctx->stream_count; i++)
 175                 if (ctx->streams[i]->apply_seamless_boot_optimization)
 176                         seamless_boot_stream_count++;
 177
 178         return seamless_boot_stream_count;
 179 }
 180
 181 static bool create_links(
 182                 struct dc *dc,
 183                 uint32_t num_virtual_links)
 184 {
 185         int i;
 186         int connectors_num;
 187         struct dc_bios *bios = dc->ctx->dc_bios;
 188
 189         dc->link_count = 0;
 190
 191         connectors_num = bios->funcs->get_connectors_number(bios);
 192
 193         DC_LOG_DC("BIOS object table - number of connectors: %d", connectors_num);
 194
 195         if (connectors_num > ENUM_ID_COUNT) {
 196                 dm_error(
 197                         "DC: Number of connectors %d exceeds maximum of %d!\n",
 198                         connectors_num,
 199                         ENUM_ID_COUNT);
 200                 return false;
 201         }
 202
 203         dm_output_to_console(
 204                 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
 205                 __func__,
 206                 connectors_num,
 207                 num_virtual_links);
 208
 209         for (i = 0; i < connectors_num; i++) {
 210                 struct link_init_data link_init_params = {0};
 211                 struct dc_link *link;
 212
 213                 DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count);
 214
 215                 link_init_params.ctx = dc->ctx;
 216                 /* next BIOS object table connector */
 217                 link_init_params.connector_index = i;
 218                 link_init_params.link_index = dc->link_count;
 219                 link_init_params.dc = dc;
 220                 link = dc->link_srv->create_link(&link_init_params);
 221
 222                 if (link) {
 223                         dc->links[dc->link_count] = link;
 224                         link->dc = dc;
 225                         ++dc->link_count;
 226                 }
 227         }
 228
 229         DC_LOG_DC("BIOS object table - end");
 230
 231         /* Create a link for each usb4 dpia port */
 232         for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) {
 233                 struct link_init_data link_init_params = {0};
 234                 struct dc_link *link;
 235
 236                 link_init_params.ctx = dc->ctx;
 237                 link_init_params.connector_index = i;
 238                 link_init_params.link_index = dc->link_count;
 239                 link_init_params.dc = dc;
 240                 link_init_params.is_dpia_link = true;
 241
 242                 link = dc->link_srv->create_link(&link_init_params);
 243                 if (link) {
 244                         dc->links[dc->link_count] = link;
 245                         link->dc = dc;
 246                         ++dc->link_count;
 247                 }
 248         }
 249
 250         for (i = 0; i < num_virtual_links; i++) {
 251                 struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL);
 252                 struct encoder_init_data enc_init = {0};
 253
 254                 if (link == NULL) {
 255                         BREAK_TO_DEBUGGER();
 256                         goto failed_alloc;
 257                 }
 258
 259                 link->link_index = dc->link_count;
 260                 dc->links[dc->link_count] = link;
 261                 dc->link_count++;
 262
 263                 link->ctx = dc->ctx;
 264                 link->dc = dc;
 265                 link->connector_signal = SIGNAL_TYPE_VIRTUAL;
 266                 link->link_id.type = OBJECT_TYPE_CONNECTOR;
 267                 link->link_id.id = CONNECTOR_ID_VIRTUAL;
 268                 link->link_id.enum_id = ENUM_ID_1;
 269                 link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL);
 270
 271                 if (!link->link_enc) {
 272                         BREAK_TO_DEBUGGER();
 273                         goto failed_alloc;
 274                 }
 275
 276                 link->link_status.dpcd_caps = &link->dpcd_caps;
 277
 278                 enc_init.ctx = dc->ctx;
 279                 enc_init.channel = CHANNEL_ID_UNKNOWN;
 280                 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
 281                 enc_init.transmitter = TRANSMITTER_UNKNOWN;
 282                 enc_init.connector = link->link_id;
 283                 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
 284                 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
 285                 enc_init.encoder.enum_id = ENUM_ID_1;
 286                 virtual_link_encoder_construct(link->link_enc, &enc_init);
 287         }
 288
 289         dc->caps.num_of_internal_disp = get_num_of_internal_disp(dc->links, dc->link_count);
 290
 291         return true;
 292
 293 failed_alloc:
 294         return false;
 295 }
 296
 297 /* Create additional DIG link encoder objects if fewer than the platform
 298  * supports were created during link construction. This can happen if the
 299  * number of physical connectors is less than the number of DIGs.
 300  */
 301 static bool create_link_encoders(struct dc *dc)
 302 {
 303         bool res = true;
 304         unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia;
 305         unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc;
 306         int i;
 307
 308         /* A platform without USB4 DPIA endpoints has a fixed mapping between DIG
 309          * link encoders and physical display endpoints and does not require
 310          * additional link encoder objects.
 311          */
 312         if (num_usb4_dpia == 0)
 313                 return res;
 314
 315         /* Create as many link encoder objects as the platform supports. DPIA
 316          * endpoints can be programmably mapped to any DIG.
 317          */
 318         if (num_dig_link_enc > dc->res_pool->dig_link_enc_count) {
 319                 for (i = 0; i < num_dig_link_enc; i++) {
 320                         struct link_encoder *link_enc = dc->res_pool->link_encoders[i];
 321
 322                         if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) {
 323                                 link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx,
 324                                                 (enum engine_id)(ENGINE_ID_DIGA + i));
 325                                 if (link_enc) {
 326                                         dc->res_pool->link_encoders[i] = link_enc;
 327                                         dc->res_pool->dig_link_enc_count++;
 328                                 } else {
 329                                         res = false;
 330                                 }
 331                         }
 332                 }
 333         }
 334
 335         return res;
 336 }
 337
 338 /* Destroy any additional DIG link encoder objects created by
 339  * create_link_encoders().
 340  * NB: Must only be called after destroy_links().
 341  */
 342 static void destroy_link_encoders(struct dc *dc)
 343 {
 344         unsigned int num_usb4_dpia;
 345         unsigned int num_dig_link_enc;
 346         int i;
 347
 348         if (!dc->res_pool)
 349                 return;
 350
 351         num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia;
 352         num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc;
 353
 354         /* A platform without USB4 DPIA endpoints has a fixed mapping between DIG
 355          * link encoders and physical display endpoints and does not require
 356          * additional link encoder objects.
 357          */
 358         if (num_usb4_dpia == 0)
 359                 return;
 360
 361         for (i = 0; i < num_dig_link_enc; i++) {
 362                 struct link_encoder *link_enc = dc->res_pool->link_encoders[i];
 363
 364                 if (link_enc) {
 365                         link_enc->funcs->destroy(&link_enc);
 366                         dc->res_pool->link_encoders[i] = NULL;
 367                         dc->res_pool->dig_link_enc_count--;
 368                 }
 369         }
 370 }
 371
 372 static struct dc_perf_trace *dc_perf_trace_create(void)
 373 {
 374         return kzalloc(sizeof(struct dc_perf_trace), GFP_KERNEL);
 375 }
 376
 377 static void dc_perf_trace_destroy(struct dc_perf_trace **perf_trace)
 378 {
 379         kfree(*perf_trace);
 380         *perf_trace = NULL;
 381 }
 382
 383 /**
 384  *  dc_stream_adjust_vmin_vmax - look up pipe context & update parts of DRR
 385  *  @dc:     dc reference
 386  *  @stream: Initial dc stream state
 387  *  @adjust: Updated parameters for vertical_total_min and vertical_total_max
 388  *
 389  *  Looks up the pipe context of dc_stream_state and updates the
 390  *  vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh
 391  *  Rate, which is a power-saving feature that targets reducing panel
 392  *  refresh rate while the screen is static
 393  *
 394  *  Return: %true if the pipe context is found and adjusted;
 395  *          %false if the pipe context is not found.
 396  */
 397 bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 398                 struct dc_stream_state *stream,
 399                 struct dc_crtc_timing_adjust *adjust)
 400 {
 401         int i;
 402
 403         /*
 404          * Don't adjust DRR while there's bandwidth optimizations pending to
 405          * avoid conflicting with firmware updates.
 406          */
 407         if (dc->ctx->dce_version > DCE_VERSION_MAX)
 408                 if (dc->optimized_required || dc->wm_optimized_required)
 409                         return false;
 410
 411         stream->adjust.v_total_max = adjust->v_total_max;
 412         stream->adjust.v_total_mid = adjust->v_total_mid;
 413         stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num;
 414         stream->adjust.v_total_min = adjust->v_total_min;
 415
 416         for (i = 0; i < MAX_PIPES; i++) {
 417                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 418
 419                 if (pipe->stream == stream && pipe->stream_res.tg) {
 420                         dc->hwss.set_drr(&pipe,
 421                                         1,
 422                                         *adjust);
 423
 424                         return true;
 425                 }
 426         }
 427         return false;
 428 }
 429
 430 /**
 431  * dc_stream_get_last_used_drr_vtotal - Looks up the pipe context of
 432  * dc_stream_state and gets the last VTOTAL used by DRR (Dynamic Refresh Rate)
 433  *
 434  * @dc: [in] dc reference
 435  * @stream: [in] Initial dc stream state
 436  * @refresh_rate: [in] new refresh_rate
 437  *
 438  * Return: %true if the pipe context is found and there is an associated
 439  *         timing_generator for the DC;
 440  *         %false if the pipe context is not found or there is no
 441  *         timing_generator for the DC.
 442  */
 443 bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
 444                 struct dc_stream_state *stream,
 445                 uint32_t *refresh_rate)
 446 {
 447         bool status = false;
 448
 449         int i = 0;
 450
 451         for (i = 0; i < MAX_PIPES; i++) {
 452                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 453
 454                 if (pipe->stream == stream && pipe->stream_res.tg) {
 455                         /* Only execute if a function pointer has been defined for
 456                          * the DC version in question
 457                          */
 458                         if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) {
 459                                 pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate);
 460
 461                                 status = true;
 462
 463                                 break;
 464                         }
 465                 }
 466         }
 467
 468         return status;
 469 }
 470
 471 bool dc_stream_get_crtc_position(struct dc *dc,
 472                 struct dc_stream_state **streams, int num_streams,
 473                 unsigned int *v_pos, unsigned int *nom_v_pos)
 474 {
 475         /* TODO: Support multiple streams */
 476         const struct dc_stream_state *stream = streams[0];
 477         int i;
 478         bool ret = false;
 479         struct crtc_position position;
 480
 481         for (i = 0; i < MAX_PIPES; i++) {
 482                 struct pipe_ctx *pipe =
 483                                 &dc->current_state->res_ctx.pipe_ctx[i];
 484
 485                 if (pipe->stream == stream && pipe->stream_res.stream_enc) {
 486                         dc->hwss.get_position(&pipe, 1, &position);
 487
 488                         *v_pos = position.vertical_count;
 489                         *nom_v_pos = position.nominal_vcount;
 490                         ret = true;
 491                 }
 492         }
 493         return ret;
 494 }
 495
 496 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 497 static inline void
 498 dc_stream_forward_dmub_crc_window(struct dc_dmub_srv *dmub_srv,
 499                 struct rect *rect, struct otg_phy_mux *mux_mapping, bool is_stop)
 500 {
 501         union dmub_rb_cmd cmd = {0};
 502
 503         cmd.secure_display.roi_info.phy_id = mux_mapping->phy_output_num;
 504         cmd.secure_display.roi_info.otg_id = mux_mapping->otg_output_num;
 505
 506         if (is_stop) {
 507                 cmd.secure_display.header.type = DMUB_CMD__SECURE_DISPLAY;
 508                 cmd.secure_display.header.sub_type = DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE;
 509         } else {
 510                 cmd.secure_display.header.type = DMUB_CMD__SECURE_DISPLAY;
 511                 cmd.secure_display.header.sub_type = DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY;
 512                 cmd.secure_display.roi_info.x_start = rect->x;
 513                 cmd.secure_display.roi_info.y_start = rect->y;
 514                 cmd.secure_display.roi_info.x_end = rect->x + rect->width;
 515                 cmd.secure_display.roi_info.y_end = rect->y + rect->height;
 516         }
 517
 518         dm_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
 519 }
 520
 521 static inline void
 522 dc_stream_forward_dmcu_crc_window(struct dmcu *dmcu,
 523                 struct rect *rect, struct otg_phy_mux *mux_mapping, bool is_stop)
 524 {
 525         if (is_stop)
 526                 dmcu->funcs->stop_crc_win_update(dmcu, mux_mapping);
 527         else
 528                 dmcu->funcs->forward_crc_window(dmcu, rect, mux_mapping);
 529 }
 530
 531 bool
 532 dc_stream_forward_crc_window(struct dc_stream_state *stream,
 533                 struct rect *rect, bool is_stop)
 534 {
 535         struct dmcu *dmcu;
 536         struct dc_dmub_srv *dmub_srv;
 537         struct otg_phy_mux mux_mapping;
 538         struct pipe_ctx *pipe;
 539         int i;
 540         struct dc *dc = stream->ctx->dc;
 541
 542         for (i = 0; i < MAX_PIPES; i++) {
 543                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 544                 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 545                         break;
 546         }
 547
 548         /* Stream not found */
 549         if (i == MAX_PIPES)
 550                 return false;
 551
 552         mux_mapping.phy_output_num = stream->link->link_enc_hw_inst;
 553         mux_mapping.otg_output_num = pipe->stream_res.tg->inst;
 554
 555         dmcu = dc->res_pool->dmcu;
 556         dmub_srv = dc->ctx->dmub_srv;
 557
 558         /* forward to dmub */
 559         if (dmub_srv)
 560                 dc_stream_forward_dmub_crc_window(dmub_srv, rect, &mux_mapping, is_stop);
 561         /* forward to dmcu */
 562         else if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
 563                 dc_stream_forward_dmcu_crc_window(dmcu, rect, &mux_mapping, is_stop);
 564         else
 565                 return false;
 566
 567         return true;
 568 }
 569 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 570
 571 /**
 572  * dc_stream_configure_crc() - Configure CRC capture for the given stream.
 573  * @dc: DC Object
 574  * @stream: The stream to configure CRC on.
 575  * @enable: Enable CRC if true, disable otherwise.
 576  * @crc_window: CRC window (x/y start/end) information
 577  * @continuous: Capture CRC on every frame if true. Otherwise, only capture
 578  *              once.
 579  *
 580  * By default, only CRC0 is configured, and the entire frame is used to
 581  * calculate the CRC.
 582  *
 583  * Return: %false if the stream is not found or CRC capture is not supported;
 584  *         %true if the stream has been configured.
 585  */
 586 bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 587                              struct crc_params *crc_window, bool enable, bool continuous)
 588 {
 589         int i;
 590         struct pipe_ctx *pipe;
 591         struct crc_params param;
 592         struct timing_generator *tg;
 593
 594         for (i = 0; i < MAX_PIPES; i++) {
 595                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 596                 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe)
 597                         break;
 598         }
 599         /* Stream not found */
 600         if (i == MAX_PIPES)
 601                 return false;
 602
 603         /* By default, capture the full frame */
 604         param.windowa_x_start = 0;
 605         param.windowa_y_start = 0;
 606         param.windowa_x_end = pipe->stream->timing.h_addressable;
 607         param.windowa_y_end = pipe->stream->timing.v_addressable;
 608         param.windowb_x_start = 0;
 609         param.windowb_y_start = 0;
 610         param.windowb_x_end = pipe->stream->timing.h_addressable;
 611         param.windowb_y_end = pipe->stream->timing.v_addressable;
 612
 613         if (crc_window) {
 614                 param.windowa_x_start = crc_window->windowa_x_start;
 615                 param.windowa_y_start = crc_window->windowa_y_start;
 616                 param.windowa_x_end = crc_window->windowa_x_end;
 617                 param.windowa_y_end = crc_window->windowa_y_end;
 618                 param.windowb_x_start = crc_window->windowb_x_start;
 619                 param.windowb_y_start = crc_window->windowb_y_start;
 620                 param.windowb_x_end = crc_window->windowb_x_end;
 621                 param.windowb_y_end = crc_window->windowb_y_end;
 622         }
 623
 624         param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
 625         param.odm_mode = pipe->next_odm_pipe ? 1:0;
 626
 627         /* Default to the union of both windows */
 628         param.selection = UNION_WINDOW_A_B;
 629         param.continuous_mode = continuous;
 630         param.enable = enable;
 631
 632         tg = pipe->stream_res.tg;
 633
 634         /* Only call if supported */
 635         if (tg->funcs->configure_crc)
 636                 return tg->funcs->configure_crc(tg, &param);
 637         DC_LOG_WARNING("CRC capture not supported.");
 638         return false;
 639 }
 640
 641 /**
 642  * dc_stream_get_crc() - Get CRC values for the given stream.
 643  *
 644  * @dc: DC object.
 645  * @stream: The DC stream state of the stream to get CRCs from.
 646  * @r_cr: CRC value for the red component.
 647  * @g_y:  CRC value for the green component.
 648  * @b_cb: CRC value for the blue component.
 649  *
 650  * dc_stream_configure_crc needs to be called beforehand to enable CRCs.
 651  *
 652  * Return:
 653  * %false if stream is not found, or if CRCs are not enabled.
 654  */
 655 bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream,
 656                        uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
 657 {
 658         int i;
 659         struct pipe_ctx *pipe;
 660         struct timing_generator *tg;
 661
 662         for (i = 0; i < MAX_PIPES; i++) {
 663                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 664                 if (pipe->stream == stream)
 665                         break;
 666         }
 667         /* Stream not found */
 668         if (i == MAX_PIPES)
 669                 return false;
 670
 671         tg = pipe->stream_res.tg;
 672
 673         if (tg->funcs->get_crc)
 674                 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);
 675         DC_LOG_WARNING("CRC capture not supported.");
 676         return false;
 677 }
 678
 679 void dc_stream_set_dyn_expansion(struct dc *dc, struct dc_stream_state *stream,
 680                 enum dc_dynamic_expansion option)
 681 {
 682         /* OPP FMT dyn expansion updates*/
 683         int i;
 684         struct pipe_ctx *pipe_ctx;
 685
 686         for (i = 0; i < MAX_PIPES; i++) {
 687                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 688                                 == stream) {
 689                         pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 690                         pipe_ctx->stream_res.opp->dyn_expansion = option;
 691                         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
 692                                         pipe_ctx->stream_res.opp,
 693                                         COLOR_SPACE_YCBCR601,
 694                                         stream->timing.display_color_depth,
 695                                         stream->signal);
 696                 }
 697         }
 698 }
 699
 700 void dc_stream_set_dither_option(struct dc_stream_state *stream,
 701                 enum dc_dither_option option)
 702 {
 703         struct bit_depth_reduction_params params;
 704         struct dc_link *link = stream->link;
 705         struct pipe_ctx *pipes = NULL;
 706         int i;
 707
 708         for (i = 0; i < MAX_PIPES; i++) {
 709                 if (link->dc->current_state->res_ctx.pipe_ctx[i].stream ==
 710                                 stream) {
 711                         pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
 712                         break;
 713                 }
 714         }
 715
 716         if (!pipes)
 717                 return;
 718         if (option > DITHER_OPTION_MAX)
 719                 return;
 720
 721         stream->dither_option = option;
 722
 723         memset(&params, 0, sizeof(params));
 724         resource_build_bit_depth_reduction_params(stream, &params);
 725         stream->bit_depth_params = params;
 726
 727         if (pipes->plane_res.xfm &&
 728             pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
 729                 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
 730                         pipes->plane_res.xfm,
 731                         pipes->plane_res.scl_data.lb_params.depth,
 732                         &stream->bit_depth_params);
 733         }
 734
 735         pipes->stream_res.opp->funcs->
 736                 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params);
 737 }
 738
 739 bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream)
 740 {
 741         int i;
 742         bool ret = false;
 743         struct pipe_ctx *pipes;
 744
 745         for (i = 0; i < MAX_PIPES; i++) {
 746                 if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) {
 747                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 748                         dc->hwss.program_gamut_remap(pipes);
 749                         ret = true;
 750                 }
 751         }
 752
 753         return ret;
 754 }
 755
 756 bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 757 {
 758         int i;
 759         bool ret = false;
 760         struct pipe_ctx *pipes;
 761
 762         for (i = 0; i < MAX_PIPES; i++) {
 763                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
 764                                 == stream) {
 765
 766                         pipes = &dc->current_state->res_ctx.pipe_ctx[i];
 767                         dc->hwss.program_output_csc(dc,
 768                                         pipes,
 769                                         stream->output_color_space,
 770                                         stream->csc_color_matrix.matrix,
 771                                         pipes->stream_res.opp->inst);
 772                         ret = true;
 773                 }
 774         }
 775
 776         return ret;
 777 }
 778
 779 void dc_stream_set_static_screen_params(struct dc *dc,
 780                 struct dc_stream_state **streams,
 781                 int num_streams,
 782                 const struct dc_static_screen_params *params)
 783 {
 784         int i, j;
 785         struct pipe_ctx *pipes_affected[MAX_PIPES];
 786         int num_pipes_affected = 0;
 787
 788         for (i = 0; i < num_streams; i++) {
 789                 struct dc_stream_state *stream = streams[i];
 790
 791                 for (j = 0; j < MAX_PIPES; j++) {
 792                         if (dc->current_state->res_ctx.pipe_ctx[j].stream
 793                                         == stream) {
 794                                 pipes_affected[num_pipes_affected++] =
 795                                                 &dc->current_state->res_ctx.pipe_ctx[j];
 796                         }
 797                 }
 798         }
 799
 800         dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params);
 801 }
 802
 803 static void dc_destruct(struct dc *dc)
 804 {
 805         // reset link encoder assignment table on destruct
 806         if (dc->res_pool && dc->res_pool->funcs->link_encs_assign)
 807                 link_enc_cfg_init(dc, dc->current_state);
 808
 809         if (dc->current_state) {
 810                 dc_release_state(dc->current_state);
 811                 dc->current_state = NULL;
 812         }
 813
 814         destroy_links(dc);
 815
 816         destroy_link_encoders(dc);
 817
 818         if (dc->clk_mgr) {
 819                 dc_destroy_clk_mgr(dc->clk_mgr);
 820                 dc->clk_mgr = NULL;
 821         }
 822
 823         dc_destroy_resource_pool(dc);
 824
 825         if (dc->link_srv)
 826                 link_destroy_link_service(&dc->link_srv);
 827
 828         if (dc->ctx->gpio_service)
 829                 dal_gpio_service_destroy(&dc->ctx->gpio_service);
 830
 831         if (dc->ctx->created_bios)
 832                 dal_bios_parser_destroy(&dc->ctx->dc_bios);
 833
 834         dc_perf_trace_destroy(&dc->ctx->perf_trace);
 835
 836         kfree(dc->ctx);
 837         dc->ctx = NULL;
 838
 839         kfree(dc->bw_vbios);
 840         dc->bw_vbios = NULL;
 841
 842         kfree(dc->bw_dceip);
 843         dc->bw_dceip = NULL;
 844
 845         kfree(dc->dcn_soc);
 846         dc->dcn_soc = NULL;
 847
 848         kfree(dc->dcn_ip);
 849         dc->dcn_ip = NULL;
 850
 851         kfree(dc->vm_helper);
 852         dc->vm_helper = NULL;
 853
 854 }
 855
 856 static bool dc_construct_ctx(struct dc *dc,
 857                 const struct dc_init_data *init_params)
 858 {
 859         struct dc_context *dc_ctx;
 860
 861         dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
 862         if (!dc_ctx)
 863                 return false;
 864
 865         dc_ctx->cgs_device = init_params->cgs_device;
 866         dc_ctx->driver_context = init_params->driver;
 867         dc_ctx->dc = dc;
 868         dc_ctx->asic_id = init_params->asic_id;
 869         dc_ctx->dc_sink_id_count = 0;
 870         dc_ctx->dc_stream_id_count = 0;
 871         dc_ctx->dce_environment = init_params->dce_environment;
 872         dc_ctx->dcn_reg_offsets = init_params->dcn_reg_offsets;
 873         dc_ctx->nbio_reg_offsets = init_params->nbio_reg_offsets;
 874
 875         /* Create logger */
 876
 877         dc_ctx->dce_version = resource_parse_asic_id(init_params->asic_id);
 878
 879         dc_ctx->perf_trace = dc_perf_trace_create();
 880         if (!dc_ctx->perf_trace) {
 881                 kfree(dc_ctx);
 882                 ASSERT_CRITICAL(false);
 883                 return false;
 884         }
 885
 886         dc->ctx = dc_ctx;
 887
 888         dc->link_srv = link_create_link_service();
 889         if (!dc->link_srv)
 890                 return false;
 891
 892         return true;
 893 }
 894
 895 static bool dc_construct(struct dc *dc,
 896                 const struct dc_init_data *init_params)
 897 {
 898         struct dc_context *dc_ctx;
 899         struct bw_calcs_dceip *dc_dceip;
 900         struct bw_calcs_vbios *dc_vbios;
 901         struct dcn_soc_bounding_box *dcn_soc;
 902         struct dcn_ip_params *dcn_ip;
 903
 904         dc->config = init_params->flags;
 905
 906         // Allocate memory for the vm_helper
 907         dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
 908         if (!dc->vm_helper) {
 909                 dm_error("%s: failed to create dc->vm_helper\n", __func__);
 910                 goto fail;
 911         }
 912
 913         memcpy(&dc->bb_overrides, &init_params->bb_overrides, sizeof(dc->bb_overrides));
 914
 915         dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
 916         if (!dc_dceip) {
 917                 dm_error("%s: failed to create dceip\n", __func__);
 918                 goto fail;
 919         }
 920
 921         dc->bw_dceip = dc_dceip;
 922
 923         dc_vbios = kzalloc(sizeof(*dc_vbios), GFP_KERNEL);
 924         if (!dc_vbios) {
 925                 dm_error("%s: failed to create vbios\n", __func__);
 926                 goto fail;
 927         }
 928
 929         dc->bw_vbios = dc_vbios;
 930         dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
 931         if (!dcn_soc) {
 932                 dm_error("%s: failed to create dcn_soc\n", __func__);
 933                 goto fail;
 934         }
 935
 936         dc->dcn_soc = dcn_soc;
 937
 938         dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL);
 939         if (!dcn_ip) {
 940                 dm_error("%s: failed to create dcn_ip\n", __func__);
 941                 goto fail;
 942         }
 943
 944         dc->dcn_ip = dcn_ip;
 945
 946         if (!dc_construct_ctx(dc, init_params)) {
 947                 dm_error("%s: failed to create ctx\n", __func__);
 948                 goto fail;
 949         }
 950
 951         dc_ctx = dc->ctx;
 952
 953         /* Resource should construct all asic specific resources.
 954          * This should be the only place where we need to parse the asic id
 955          */
 956         if (init_params->vbios_override)
 957                 dc_ctx->dc_bios = init_params->vbios_override;
 958         else {
 959                 /* Create BIOS parser */
 960                 struct bp_init_data bp_init_data;
 961
 962                 bp_init_data.ctx = dc_ctx;
 963                 bp_init_data.bios = init_params->asic_id.atombios_base_address;
 964
 965                 dc_ctx->dc_bios = dal_bios_parser_create(
 966                                 &bp_init_data, dc_ctx->dce_version);
 967
 968                 if (!dc_ctx->dc_bios) {
 969                         ASSERT_CRITICAL(false);
 970                         goto fail;
 971                 }
 972
 973                 dc_ctx->created_bios = true;
 974         }
 975
 976         dc->vendor_signature = init_params->vendor_signature;
 977
 978         /* Create GPIO service */
 979         dc_ctx->gpio_service = dal_gpio_service_create(
 980                         dc_ctx->dce_version,
 981                         dc_ctx->dce_environment,
 982                         dc_ctx);
 983
 984         if (!dc_ctx->gpio_service) {
 985                 ASSERT_CRITICAL(false);
 986                 goto fail;
 987         }
 988
 989         dc->res_pool = dc_create_resource_pool(dc, init_params, dc_ctx->dce_version);
 990         if (!dc->res_pool)
 991                 goto fail;
 992
 993         /* set i2c speed if not done by the respective dcnxxx__resource.c */
 994         if (dc->caps.i2c_speed_in_khz_hdcp == 0)
 995                 dc->caps.i2c_speed_in_khz_hdcp = dc->caps.i2c_speed_in_khz;
 996
 997         dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
 998         if (!dc->clk_mgr)
 999                 goto fail;
1000 #ifdef CONFIG_DRM_AMD_DC_FP
1001         dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
1002
1003         if (dc->res_pool->funcs->update_bw_bounding_box) {
1004                 DC_FP_START();
1005                 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params);
1006                 DC_FP_END();
1007         }
1008 #endif
1009
1010         /* Creation of current_state must occur after dc->dml
1011          * is initialized in dc_create_resource_pool because
1012          * on creation it copies the contents of dc->dml
1013          */
1014
1015         dc->current_state = dc_create_state(dc);
1016
1017         if (!dc->current_state) {
1018                 dm_error("%s: failed to create validate ctx\n", __func__);
1019                 goto fail;
1020         }
1021
1022         if (!create_links(dc, init_params->num_virtual_links))
1023                 goto fail;
1024
1025         /* Create additional DIG link encoder objects if fewer than the platform
1026          * supports were created during link construction.
1027          */
1028         if (!create_link_encoders(dc))
1029                 goto fail;
1030
1031         dc_resource_state_construct(dc, dc->current_state);
1032
1033         return true;
1034
1035 fail:
1036         return false;
1037 }
1038
1039 static void disable_all_writeback_pipes_for_stream(
1040                 const struct dc *dc,
1041                 struct dc_stream_state *stream,
1042                 struct dc_state *context)
1043 {
1044         int i;
1045
1046         for (i = 0; i < stream->num_wb_info; i++)
1047                 stream->writeback_info[i].wb_enabled = false;
1048 }
1049
1050 static void apply_ctx_interdependent_lock(struct dc *dc, struct dc_state *context,
1051                                           struct dc_stream_state *stream, bool lock)
1052 {
1053         int i;
1054
1055         /* Checks if interdependent update function pointer is NULL or not, takes care of DCE110 case */
1056         if (dc->hwss.interdependent_update_lock)
1057                 dc->hwss.interdependent_update_lock(dc, context, lock);
1058         else {
1059                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1060                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1061                         struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1062
1063                         // Copied conditions that were previously in dce110_apply_ctx_for_surface
1064                         if (stream == pipe_ctx->stream) {
1065                                 if (!pipe_ctx->top_pipe &&
1066                                         (pipe_ctx->plane_state || old_pipe_ctx->plane_state))
1067                                         dc->hwss.pipe_control_lock(dc, pipe_ctx, lock);
1068                         }
1069                 }
1070         }
1071 }
1072
1073 static void phantom_pipe_blank(
1074                 struct dc *dc,
1075                 struct timing_generator *tg,
1076                 int width,
1077                 int height)
1078 {
1079         struct dce_hwseq *hws = dc->hwseq;
1080         enum dc_color_space color_space;
1081         struct tg_color black_color = {0};
1082         struct output_pixel_processor *opp = NULL;
1083         uint32_t num_opps, opp_id_src0, opp_id_src1;
1084         uint32_t otg_active_width, otg_active_height;
1085         uint32_t i;
1086
1087         /* program opp dpg blank color */
1088         color_space = COLOR_SPACE_SRGB;
1089         color_space_to_black_color(dc, color_space, &black_color);
1090
1091         otg_active_width = width;
1092         otg_active_height = height;
1093
1094         /* get the OPTC source */
1095         tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
1096         ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
1097
1098         for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
1099                 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) {
1100                         opp = dc->res_pool->opps[i];
1101                         break;
1102                 }
1103         }
1104
1105         if (opp && opp->funcs->opp_set_disp_pattern_generator)
1106                 opp->funcs->opp_set_disp_pattern_generator(
1107                                 opp,
1108                                 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
1109                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
1110                                 COLOR_DEPTH_UNDEFINED,
1111                                 &black_color,
1112                                 otg_active_width,
1113                                 otg_active_height,
1114                                 0);
1115
1116         if (tg->funcs->is_tg_enabled(tg))
1117                 hws->funcs.wait_for_blank_complete(opp);
1118 }
1119
1120 static void dc_update_viusal_confirm_color(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
1121 {
1122         if (dc->ctx->dce_version >= DCN_VERSION_1_0) {
1123                 memset(&pipe_ctx->visual_confirm_color, 0, sizeof(struct tg_color));
1124
1125                 if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
1126                         get_hdr_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1127                 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1128                         get_surface_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1129                 else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
1130                         get_surface_tile_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1131                 else {
1132                         if (dc->ctx->dce_version < DCN_VERSION_2_0)
1133                                 color_space_to_black_color(
1134                                         dc, pipe_ctx->stream->output_color_space, &(pipe_ctx->visual_confirm_color));
1135                 }
1136                 if (dc->ctx->dce_version >= DCN_VERSION_2_0) {
1137                         if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)
1138                                 get_mpctree_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color));
1139                         else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP)
1140                                 get_subvp_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));
1141                         else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH)
1142                                 get_mclk_switch_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color));
1143                 }
1144         }
1145 }
1146
1147 static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
1148 {
1149         int i, j;
1150         struct dc_state *dangling_context = dc_create_state(dc);
1151         struct dc_state *current_ctx;
1152         struct pipe_ctx *pipe;
1153         struct timing_generator *tg;
1154
1155         if (dangling_context == NULL)
1156                 return;
1157
1158         dc_resource_state_copy_construct(dc->current_state, dangling_context);
1159
1160         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1161                 struct dc_stream_state *old_stream =
1162                                 dc->current_state->res_ctx.pipe_ctx[i].stream;
1163                 bool should_disable = true;
1164                 bool pipe_split_change = false;
1165
1166                 if ((context->res_ctx.pipe_ctx[i].top_pipe) &&
1167                         (dc->current_state->res_ctx.pipe_ctx[i].top_pipe))
1168                         pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe->pipe_idx !=
1169                                 dc->current_state->res_ctx.pipe_ctx[i].top_pipe->pipe_idx;
1170                 else
1171                         pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe !=
1172                                 dc->current_state->res_ctx.pipe_ctx[i].top_pipe;
1173
1174                 for (j = 0; j < context->stream_count; j++) {
1175                         if (old_stream == context->streams[j]) {
1176                                 should_disable = false;
1177                                 break;
1178                         }
1179                 }
1180                 if (!should_disable && pipe_split_change &&
1181                                 dc->current_state->stream_count != context->stream_count)
1182                         should_disable = true;
1183
1184                 if (old_stream && !dc->current_state->res_ctx.pipe_ctx[i].top_pipe &&
1185                                 !dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe) {
1186                         struct pipe_ctx *old_pipe, *new_pipe;
1187
1188                         old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1189                         new_pipe = &context->res_ctx.pipe_ctx[i];
1190
1191                         if (old_pipe->plane_state && !new_pipe->plane_state)
1192                                 should_disable = true;
1193                 }
1194
1195                 if (should_disable && old_stream) {
1196                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1197                         tg = pipe->stream_res.tg;
1198                         /* When disabling plane for a phantom pipe, we must turn on the
1199                          * phantom OTG so the disable programming gets the double buffer
1200                          * update. Otherwise the pipe will be left in a partially disabled
1201                          * state that can result in underflow or hang when enabling it
1202                          * again for different use.
1203                          */
1204                         if (old_stream->mall_stream_config.type == SUBVP_PHANTOM) {
1205                                 if (tg->funcs->enable_crtc) {
1206                                         int main_pipe_width, main_pipe_height;
1207
1208                                         main_pipe_width = old_stream->mall_stream_config.paired_stream->dst.width;
1209                                         main_pipe_height = old_stream->mall_stream_config.paired_stream->dst.height;
1210                                         phantom_pipe_blank(dc, tg, main_pipe_width, main_pipe_height);
1211                                         tg->funcs->enable_crtc(tg);
1212                                 }
1213                         }
1214                         dc_rem_all_planes_for_stream(dc, old_stream, dangling_context);
1215                         disable_all_writeback_pipes_for_stream(dc, old_stream, dangling_context);
1216
1217                         if (pipe->stream && pipe->plane_state)
1218                                 dc_update_viusal_confirm_color(dc, context, pipe);
1219
1220                         if (dc->hwss.apply_ctx_for_surface) {
1221                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, true);
1222                                 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context);
1223                                 apply_ctx_interdependent_lock(dc, dc->current_state, old_stream, false);
1224                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
1225                         }
1226                         if (dc->hwss.program_front_end_for_ctx) {
1227                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, true);
1228                                 dc->hwss.program_front_end_for_ctx(dc, dangling_context);
1229                                 dc->hwss.interdependent_update_lock(dc, dc->current_state, false);
1230                                 dc->hwss.post_unlock_program_front_end(dc, dangling_context);
1231                         }
1232                         /* We need to put the phantom OTG back into it's default (disabled) state or we
1233                          * can get corruption when transition from one SubVP config to a different one.
1234                          * The OTG is set to disable on falling edge of VUPDATE so the plane disable
1235                          * will still get it's double buffer update.
1236                          */
1237                         if (old_stream->mall_stream_config.type == SUBVP_PHANTOM) {
1238                                 if (tg->funcs->disable_phantom_crtc)
1239                                         tg->funcs->disable_phantom_crtc(tg);
1240                         }
1241                 }
1242         }
1243
1244         current_ctx = dc->current_state;
1245         dc->current_state = dangling_context;
1246         dc_release_state(current_ctx);
1247 }
1248
1249 static void disable_vbios_mode_if_required(
1250                 struct dc *dc,
1251                 struct dc_state *context)
1252 {
1253         unsigned int i, j;
1254
1255         /* check if timing_changed, disable stream*/
1256         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1257                 struct dc_stream_state *stream = NULL;
1258                 struct dc_link *link = NULL;
1259                 struct pipe_ctx *pipe = NULL;
1260
1261                 pipe = &context->res_ctx.pipe_ctx[i];
1262                 stream = pipe->stream;
1263                 if (stream == NULL)
1264                         continue;
1265
1266                 // only looking for first odm pipe
1267                 if (pipe->prev_odm_pipe)
1268                         continue;
1269
1270                 if (stream->link->local_sink &&
1271                         stream->link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1272                         link = stream->link;
1273                 }
1274
1275                 if (link != NULL && link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
1276                         unsigned int enc_inst, tg_inst = 0;
1277                         unsigned int pix_clk_100hz;
1278
1279                         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1280                         if (enc_inst != ENGINE_ID_UNKNOWN) {
1281                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
1282                                         if (dc->res_pool->stream_enc[j]->id == enc_inst) {
1283                                                 tg_inst = dc->res_pool->stream_enc[j]->funcs->dig_source_otg(
1284                                                         dc->res_pool->stream_enc[j]);
1285                                                 break;
1286                                         }
1287                                 }
1288
1289                                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1290                                         dc->res_pool->dp_clock_source,
1291                                         tg_inst, &pix_clk_100hz);
1292
1293                                 if (link->link_status.link_active) {
1294                                         uint32_t requested_pix_clk_100hz =
1295                                                 pipe->stream_res.pix_clk_params.requested_pix_clk_100hz;
1296
1297                                         if (pix_clk_100hz != requested_pix_clk_100hz) {
1298                                                 dc->link_srv->set_dpms_off(pipe);
1299                                                 pipe->stream->dpms_off = false;
1300                                         }
1301                                 }
1302                         }
1303                 }
1304         }
1305 }
1306
1307 static void wait_for_no_pipes_pending(struct dc *dc, struct dc_state *context)
1308 {
1309         int i;
1310         PERF_TRACE();
1311         for (i = 0; i < MAX_PIPES; i++) {
1312                 int count = 0;
1313                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1314
1315                 if (!pipe->plane_state || pipe->stream->mall_stream_config.type == SUBVP_PHANTOM)
1316                         continue;
1317
1318                 /* Timeout 100 ms */
1319                 while (count < 100000) {
1320                         /* Must set to false to start with, due to OR in update function */
1321                         pipe->plane_state->status.is_flip_pending = false;
1322                         dc->hwss.update_pending_status(pipe);
1323                         if (!pipe->plane_state->status.is_flip_pending)
1324                                 break;
1325                         udelay(1);
1326                         count++;
1327                 }
1328                 ASSERT(!pipe->plane_state->status.is_flip_pending);
1329         }
1330         PERF_TRACE();
1331 }
1332
1333 /* Public functions */
1334
1335 struct dc *dc_create(const struct dc_init_data *init_params)
1336 {
1337         struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
1338         unsigned int full_pipe_count;
1339
1340         if (!dc)
1341                 return NULL;
1342
1343         if (init_params->dce_environment == DCE_ENV_VIRTUAL_HW) {
1344                 if (!dc_construct_ctx(dc, init_params))
1345                         goto destruct_dc;
1346         } else {
1347                 if (!dc_construct(dc, init_params))
1348                         goto destruct_dc;
1349
1350                 full_pipe_count = dc->res_pool->pipe_count;
1351                 if (dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
1352                         full_pipe_count--;
1353                 dc->caps.max_streams = min(
1354                                 full_pipe_count,
1355                                 dc->res_pool->stream_enc_count);
1356
1357                 dc->caps.max_links = dc->link_count;
1358                 dc->caps.max_audios = dc->res_pool->audio_count;
1359                 dc->caps.linear_pitch_alignment = 64;
1360
1361                 dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
1362
1363                 dc->caps.max_otg_num = dc->res_pool->res_cap->num_timing_generator;
1364
1365                 if (dc->res_pool->dmcu != NULL)
1366                         dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
1367         }
1368
1369         dc->dcn_reg_offsets = init_params->dcn_reg_offsets;
1370         dc->nbio_reg_offsets = init_params->nbio_reg_offsets;
1371
1372         /* Populate versioning information */
1373         dc->versions.dc_ver = DC_VER;
1374
1375         dc->build_id = DC_BUILD_ID;
1376
1377         DC_LOG_DC("Display Core initialized\n");
1378
1379
1380
1381         return dc;
1382
1383 destruct_dc:
1384         dc_destruct(dc);
1385         kfree(dc);
1386         return NULL;
1387 }
1388
1389 static void detect_edp_presence(struct dc *dc)
1390 {
1391         struct dc_link *edp_links[MAX_NUM_EDP];
1392         struct dc_link *edp_link = NULL;
1393         enum dc_connection_type type;
1394         int i;
1395         int edp_num;
1396
1397         dc_get_edp_links(dc, edp_links, &edp_num);
1398         if (!edp_num)
1399                 return;
1400
1401         for (i = 0; i < edp_num; i++) {
1402                 edp_link = edp_links[i];
1403                 if (dc->config.edp_not_connected) {
1404                         edp_link->edp_sink_present = false;
1405                 } else {
1406                         dc_link_detect_connection_type(edp_link, &type);
1407                         edp_link->edp_sink_present = (type != dc_connection_none);
1408                 }
1409         }
1410 }
1411
1412 void dc_hardware_init(struct dc *dc)
1413 {
1414
1415         detect_edp_presence(dc);
1416         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
1417                 dc->hwss.init_hw(dc);
1418 }
1419
1420 void dc_init_callbacks(struct dc *dc,
1421                 const struct dc_callback_init *init_params)
1422 {
1423         dc->ctx->cp_psp = init_params->cp_psp;
1424 }
1425
1426 void dc_deinit_callbacks(struct dc *dc)
1427 {
1428         memset(&dc->ctx->cp_psp, 0, sizeof(dc->ctx->cp_psp));
1429 }
1430
1431 void dc_destroy(struct dc **dc)
1432 {
1433         dc_destruct(*dc);
1434         kfree(*dc);
1435         *dc = NULL;
1436 }
1437
1438 static void enable_timing_multisync(
1439                 struct dc *dc,
1440                 struct dc_state *ctx)
1441 {
1442         int i, multisync_count = 0;
1443         int pipe_count = dc->res_pool->pipe_count;
1444         struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
1445
1446         for (i = 0; i < pipe_count; i++) {
1447                 if (!ctx->res_ctx.pipe_ctx[i].stream ||
1448                                 !ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.enabled)
1449                         continue;
1450                 if (ctx->res_ctx.pipe_ctx[i].stream == ctx->res_ctx.pipe_ctx[i].stream->triggered_crtc_reset.event_source)
1451                         continue;
1452                 multisync_pipes[multisync_count] = &ctx->res_ctx.pipe_ctx[i];
1453                 multisync_count++;
1454         }
1455
1456         if (multisync_count > 0) {
1457                 dc->hwss.enable_per_frame_crtc_position_reset(
1458                         dc, multisync_count, multisync_pipes);
1459         }
1460 }
1461
1462 static void program_timing_sync(
1463                 struct dc *dc,
1464                 struct dc_state *ctx)
1465 {
1466         int i, j, k;
1467         int group_index = 0;
1468         int num_group = 0;
1469         int pipe_count = dc->res_pool->pipe_count;
1470         struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
1471
1472         for (i = 0; i < pipe_count; i++) {
1473                 if (!ctx->res_ctx.pipe_ctx[i].stream
1474                                 || ctx->res_ctx.pipe_ctx[i].top_pipe
1475                                 || ctx->res_ctx.pipe_ctx[i].prev_odm_pipe)
1476                         continue;
1477
1478                 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
1479         }
1480
1481         for (i = 0; i < pipe_count; i++) {
1482                 int group_size = 1;
1483                 enum timing_synchronization_type sync_type = NOT_SYNCHRONIZABLE;
1484                 struct pipe_ctx *pipe_set[MAX_PIPES];
1485
1486                 if (!unsynced_pipes[i])
1487                         continue;
1488
1489                 pipe_set[0] = unsynced_pipes[i];
1490                 unsynced_pipes[i] = NULL;
1491
1492                 /* Add tg to the set, search rest of the tg's for ones with
1493                  * same timing, add all tgs with same timing to the group
1494                  */
1495                 for (j = i + 1; j < pipe_count; j++) {
1496                         if (!unsynced_pipes[j])
1497                                 continue;
1498                         if (sync_type != TIMING_SYNCHRONIZABLE &&
1499                                 dc->hwss.enable_vblanks_synchronization &&
1500                                 unsynced_pipes[j]->stream_res.tg->funcs->align_vblanks &&
1501                                 resource_are_vblanks_synchronizable(
1502                                         unsynced_pipes[j]->stream,
1503                                         pipe_set[0]->stream)) {
1504                                 sync_type = VBLANK_SYNCHRONIZABLE;
1505                                 pipe_set[group_size] = unsynced_pipes[j];
1506                                 unsynced_pipes[j] = NULL;
1507                                 group_size++;
1508                         } else
1509                         if (sync_type != VBLANK_SYNCHRONIZABLE &&
1510                                 resource_are_streams_timing_synchronizable(
1511                                         unsynced_pipes[j]->stream,
1512                                         pipe_set[0]->stream)) {
1513                                 sync_type = TIMING_SYNCHRONIZABLE;
1514                                 pipe_set[group_size] = unsynced_pipes[j];
1515                                 unsynced_pipes[j] = NULL;
1516                                 group_size++;
1517                         }
1518                 }
1519
1520                 /* set first unblanked pipe as master */
1521                 for (j = 0; j < group_size; j++) {
1522                         bool is_blanked;
1523
1524                         if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1525                                 is_blanked =
1526                                         pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1527                         else
1528                                 is_blanked =
1529                                         pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1530                         if (!is_blanked) {
1531                                 if (j == 0)
1532                                         break;
1533
1534                                 swap(pipe_set[0], pipe_set[j]);
1535                                 break;
1536                         }
1537                 }
1538
1539                 for (k = 0; k < group_size; k++) {
1540                         struct dc_stream_status *status = dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);
1541
1542                         status->timing_sync_info.group_id = num_group;
1543                         status->timing_sync_info.group_size = group_size;
1544                         if (k == 0)
1545                                 status->timing_sync_info.master = true;
1546                         else
1547                                 status->timing_sync_info.master = false;
1548
1549                 }
1550
1551                 /* remove any other pipes that are already been synced */
1552                 if (dc->config.use_pipe_ctx_sync_logic) {
1553                         /* check pipe's syncd to decide which pipe to be removed */
1554                         for (j = 1; j < group_size; j++) {
1555                                 if (pipe_set[j]->pipe_idx_syncd == pipe_set[0]->pipe_idx_syncd) {
1556                                         group_size--;
1557                                         pipe_set[j] = pipe_set[group_size];
1558                                         j--;
1559                                 } else
1560                                         /* link slave pipe's syncd with master pipe */
1561                                         pipe_set[j]->pipe_idx_syncd = pipe_set[0]->pipe_idx_syncd;
1562                         }
1563                 } else {
1564                         for (j = j + 1; j < group_size; j++) {
1565                                 bool is_blanked;
1566
1567                                 if (pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked)
1568                                         is_blanked =
1569                                                 pipe_set[j]->stream_res.opp->funcs->dpg_is_blanked(pipe_set[j]->stream_res.opp);
1570                                 else
1571                                         is_blanked =
1572                                                 pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg);
1573                                 if (!is_blanked) {
1574                                         group_size--;
1575                                         pipe_set[j] = pipe_set[group_size];
1576                                         j--;
1577                                 }
1578                         }
1579                 }
1580
1581                 if (group_size > 1) {
1582                         if (sync_type == TIMING_SYNCHRONIZABLE) {
1583                                 dc->hwss.enable_timing_synchronization(
1584                                         dc, group_index, group_size, pipe_set);
1585                         } else
1586                                 if (sync_type == VBLANK_SYNCHRONIZABLE) {
1587                                 dc->hwss.enable_vblanks_synchronization(
1588                                         dc, group_index, group_size, pipe_set);
1589                                 }
1590                         group_index++;
1591                 }
1592                 num_group++;
1593         }
1594 }
1595
1596 static bool streams_changed(struct dc *dc,
1597                             struct dc_stream_state *streams[],
1598                             uint8_t stream_count)
1599 {
1600         uint8_t i;
1601
1602         if (stream_count != dc->current_state->stream_count)
1603                 return true;
1604
1605         for (i = 0; i < dc->current_state->stream_count; i++) {
1606                 if (dc->current_state->streams[i] != streams[i])
1607                         return true;
1608                 if (!streams[i]->link->link_state_valid)
1609                         return true;
1610         }
1611
1612         return false;
1613 }
1614
1615 bool dc_validate_boot_timing(const struct dc *dc,
1616                                 const struct dc_sink *sink,
1617                                 struct dc_crtc_timing *crtc_timing)
1618 {
1619         struct timing_generator *tg;
1620         struct stream_encoder *se = NULL;
1621
1622         struct dc_crtc_timing hw_crtc_timing = {0};
1623
1624         struct dc_link *link = sink->link;
1625         unsigned int i, enc_inst, tg_inst = 0;
1626
1627         /* Support seamless boot on EDP displays only */
1628         if (sink->sink_signal != SIGNAL_TYPE_EDP) {
1629                 return false;
1630         }
1631
1632         if (dc->debug.force_odm_combine)
1633                 return false;
1634
1635         /* Check for enabled DIG to identify enabled display */
1636         if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
1637                 return false;
1638
1639         enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
1640
1641         if (enc_inst == ENGINE_ID_UNKNOWN)
1642                 return false;
1643
1644         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1645                 if (dc->res_pool->stream_enc[i]->id == enc_inst) {
1646
1647                         se = dc->res_pool->stream_enc[i];
1648
1649                         tg_inst = dc->res_pool->stream_enc[i]->funcs->dig_source_otg(
1650                                 dc->res_pool->stream_enc[i]);
1651                         break;
1652                 }
1653         }
1654
1655         // tg_inst not found
1656         if (i == dc->res_pool->stream_enc_count)
1657                 return false;
1658
1659         if (tg_inst >= dc->res_pool->timing_generator_count)
1660                 return false;
1661
1662         if (tg_inst != link->link_enc->preferred_engine)
1663                 return false;
1664
1665         tg = dc->res_pool->timing_generators[tg_inst];
1666
1667         if (!tg->funcs->get_hw_timing)
1668                 return false;
1669
1670         if (!tg->funcs->get_hw_timing(tg, &hw_crtc_timing))
1671                 return false;
1672
1673         if (crtc_timing->h_total != hw_crtc_timing.h_total)
1674                 return false;
1675
1676         if (crtc_timing->h_border_left != hw_crtc_timing.h_border_left)
1677                 return false;
1678
1679         if (crtc_timing->h_addressable != hw_crtc_timing.h_addressable)
1680                 return false;
1681
1682         if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right)
1683                 return false;
1684
1685         if (crtc_timing->h_front_porch != hw_crtc_timing.h_front_porch)
1686                 return false;
1687
1688         if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width)
1689                 return false;
1690
1691         if (crtc_timing->v_total != hw_crtc_timing.v_total)
1692                 return false;
1693
1694         if (crtc_timing->v_border_top != hw_crtc_timing.v_border_top)
1695                 return false;
1696
1697         if (crtc_timing->v_addressable != hw_crtc_timing.v_addressable)
1698                 return false;
1699
1700         if (crtc_timing->v_border_bottom != hw_crtc_timing.v_border_bottom)
1701                 return false;
1702
1703         if (crtc_timing->v_front_porch != hw_crtc_timing.v_front_porch)
1704                 return false;
1705
1706         if (crtc_timing->v_sync_width != hw_crtc_timing.v_sync_width)
1707                 return false;
1708
1709         /* block DSC for now, as VBIOS does not currently support DSC timings */
1710         if (crtc_timing->flags.DSC)
1711                 return false;
1712
1713         if (dc_is_dp_signal(link->connector_signal)) {
1714                 unsigned int pix_clk_100hz;
1715                 uint32_t numOdmPipes = 1;
1716                 uint32_t id_src[4] = {0};
1717
1718                 dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
1719                         dc->res_pool->dp_clock_source,
1720                         tg_inst, &pix_clk_100hz);
1721
1722                 if (tg->funcs->get_optc_source)
1723                         tg->funcs->get_optc_source(tg,
1724                                                 &numOdmPipes, &id_src[0], &id_src[1]);
1725
1726                 if (numOdmPipes == 2)
1727                         pix_clk_100hz *= 2;
1728                 if (numOdmPipes == 4)
1729                         pix_clk_100hz *= 4;
1730
1731                 // Note: In rare cases, HW pixclk may differ from crtc's pixclk
1732                 // slightly due to rounding issues in 10 kHz units.
1733                 if (crtc_timing->pix_clk_100hz != pix_clk_100hz)
1734                         return false;
1735
1736                 if (!se->funcs->dp_get_pixel_format)
1737                         return false;
1738
1739                 if (!se->funcs->dp_get_pixel_format(
1740                         se,
1741                         &hw_crtc_timing.pixel_encoding,
1742                         &hw_crtc_timing.display_color_depth))
1743                         return false;
1744
1745                 if (hw_crtc_timing.display_color_depth != crtc_timing->display_color_depth)
1746                         return false;
1747
1748                 if (hw_crtc_timing.pixel_encoding != crtc_timing->pixel_encoding)
1749                         return false;
1750         }
1751
1752         if (link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) {
1753                 return false;
1754         }
1755
1756         if (dc->link_srv->edp_is_ilr_optimization_required(link, crtc_timing)) {
1757                 DC_LOG_EVENT_LINK_TRAINING("Seamless boot disabled to optimize eDP link rate\n");
1758                 return false;
1759         }
1760
1761         return true;
1762 }
1763
1764 static inline bool should_update_pipe_for_stream(
1765                 struct dc_state *context,
1766                 struct pipe_ctx *pipe_ctx,
1767                 struct dc_stream_state *stream)
1768 {
1769         return (pipe_ctx->stream && pipe_ctx->stream == stream);
1770 }
1771
1772 static inline bool should_update_pipe_for_plane(
1773                 struct dc_state *context,
1774                 struct pipe_ctx *pipe_ctx,
1775                 struct dc_plane_state *plane_state)
1776 {
1777         return (pipe_ctx->plane_state == plane_state);
1778 }
1779
1780 void dc_enable_stereo(
1781         struct dc *dc,
1782         struct dc_state *context,
1783         struct dc_stream_state *streams[],
1784         uint8_t stream_count)
1785 {
1786         int i, j;
1787         struct pipe_ctx *pipe;
1788
1789         for (i = 0; i < MAX_PIPES; i++) {
1790                 if (context != NULL) {
1791                         pipe = &context->res_ctx.pipe_ctx[i];
1792                 } else {
1793                         context = dc->current_state;
1794                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1795                 }
1796
1797                 for (j = 0; pipe && j < stream_count; j++)  {
1798                         if (should_update_pipe_for_stream(context, pipe, streams[j]) &&
1799                                 dc->hwss.setup_stereo)
1800                                 dc->hwss.setup_stereo(pipe, dc);
1801                 }
1802         }
1803 }
1804
1805 void dc_trigger_sync(struct dc *dc, struct dc_state *context)
1806 {
1807         if (context->stream_count > 1 && !dc->debug.disable_timing_sync) {
1808                 enable_timing_multisync(dc, context);
1809                 program_timing_sync(dc, context);
1810         }
1811 }
1812
1813 static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
1814 {
1815         int i;
1816         unsigned int stream_mask = 0;
1817
1818         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1819                 if (context->res_ctx.pipe_ctx[i].stream)
1820                         stream_mask |= 1 << i;
1821         }
1822
1823         return stream_mask;
1824 }
1825
1826 void dc_z10_restore(const struct dc *dc)
1827 {
1828         if (dc->hwss.z10_restore)
1829                 dc->hwss.z10_restore(dc);
1830 }
1831
1832 void dc_z10_save_init(struct dc *dc)
1833 {
1834         if (dc->hwss.z10_save_init)
1835                 dc->hwss.z10_save_init(dc);
1836 }
1837
1838 /**
1839  * dc_commit_state_no_check - Apply context to the hardware
1840  *
1841  * @dc: DC object with the current status to be updated
1842  * @context: New state that will become the current status at the end of this function
1843  *
1844  * Applies given context to the hardware and copy it into current context.
1845  * It's up to the user to release the src context afterwards.
1846  *
1847  * Return: an enum dc_status result code for the operation
1848  */
1849 static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context)
1850 {
1851         struct dc_bios *dcb = dc->ctx->dc_bios;
1852         enum dc_status result = DC_ERROR_UNEXPECTED;
1853         struct pipe_ctx *pipe;
1854         int i, k, l;
1855         struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
1856         struct dc_state *old_state;
1857         bool subvp_prev_use = false;
1858
1859         dc_z10_restore(dc);
1860         dc_allow_idle_optimizations(dc, false);
1861
1862         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1863                 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1864
1865                 /* Check old context for SubVP */
1866                 subvp_prev_use |= (old_pipe->stream && old_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM);
1867                 if (subvp_prev_use)
1868                         break;
1869         }
1870
1871         for (i = 0; i < context->stream_count; i++)
1872                 dc_streams[i] =  context->streams[i];
1873
1874         if (!dcb->funcs->is_accelerated_mode(dcb)) {
1875                 disable_vbios_mode_if_required(dc, context);
1876                 dc->hwss.enable_accelerated_mode(dc, context);
1877         }
1878
1879         if (context->stream_count > get_seamless_boot_stream_count(context) ||
1880                 context->stream_count == 0)
1881                 dc->hwss.prepare_bandwidth(dc, context);
1882
1883         /* When SubVP is active, all HW programming must be done while
1884          * SubVP lock is acquired
1885          */
1886         if (dc->hwss.subvp_pipe_control_lock)
1887                 dc->hwss.subvp_pipe_control_lock(dc, context, true, true, NULL, subvp_prev_use);
1888
1889         if (dc->debug.enable_double_buffered_dsc_pg_support)
1890                 dc->hwss.update_dsc_pg(dc, context, false);
1891
1892         disable_dangling_plane(dc, context);
1893         /* re-program planes for existing stream, in case we need to
1894          * free up plane resource for later use
1895          */
1896         if (dc->hwss.apply_ctx_for_surface) {
1897                 for (i = 0; i < context->stream_count; i++) {
1898                         if (context->streams[i]->mode_changed)
1899                                 continue;
1900                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1901                         dc->hwss.apply_ctx_for_surface(
1902                                 dc, context->streams[i],
1903                                 context->stream_status[i].plane_count,
1904                                 context); /* use new pipe config in new context */
1905                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1906                         dc->hwss.post_unlock_program_front_end(dc, context);
1907                 }
1908         }
1909
1910         /* Program hardware */
1911         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1912                 pipe = &context->res_ctx.pipe_ctx[i];
1913                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
1914         }
1915
1916         result = dc->hwss.apply_ctx_to_hw(dc, context);
1917
1918         if (result != DC_OK) {
1919                 /* Application of dc_state to hardware stopped. */
1920                 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY;
1921                 return result;
1922         }
1923
1924         dc_trigger_sync(dc, context);
1925
1926         /* Program all planes within new context*/
1927         if (dc->hwss.program_front_end_for_ctx) {
1928                 dc->hwss.interdependent_update_lock(dc, context, true);
1929                 dc->hwss.program_front_end_for_ctx(dc, context);
1930                 dc->hwss.interdependent_update_lock(dc, context, false);
1931                 dc->hwss.post_unlock_program_front_end(dc, context);
1932         }
1933
1934         if (dc->hwss.commit_subvp_config)
1935                 dc->hwss.commit_subvp_config(dc, context);
1936         if (dc->hwss.subvp_pipe_control_lock)
1937                 dc->hwss.subvp_pipe_control_lock(dc, context, false, true, NULL, subvp_prev_use);
1938
1939         for (i = 0; i < context->stream_count; i++) {
1940                 const struct dc_link *link = context->streams[i]->link;
1941
1942                 if (!context->streams[i]->mode_changed)
1943                         continue;
1944
1945                 if (dc->hwss.apply_ctx_for_surface) {
1946                         apply_ctx_interdependent_lock(dc, context, context->streams[i], true);
1947                         dc->hwss.apply_ctx_for_surface(
1948                                         dc, context->streams[i],
1949                                         context->stream_status[i].plane_count,
1950                                         context);
1951                         apply_ctx_interdependent_lock(dc, context, context->streams[i], false);
1952                         dc->hwss.post_unlock_program_front_end(dc, context);
1953                 }
1954
1955                 /*
1956                  * enable stereo
1957                  * TODO rework dc_enable_stereo call to work with validation sets?
1958                  */
1959                 for (k = 0; k < MAX_PIPES; k++) {
1960                         pipe = &context->res_ctx.pipe_ctx[k];
1961
1962                         for (l = 0 ; pipe && l < context->stream_count; l++)  {
1963                                 if (context->streams[l] &&
1964                                         context->streams[l] == pipe->stream &&
1965                                         dc->hwss.setup_stereo)
1966                                         dc->hwss.setup_stereo(pipe, dc);
1967                         }
1968                 }
1969
1970                 CONN_MSG_MODE(link, "{%dx%d, %dx%d@%dKhz}",
1971                                 context->streams[i]->timing.h_addressable,
1972                                 context->streams[i]->timing.v_addressable,
1973                                 context->streams[i]->timing.h_total,
1974                                 context->streams[i]->timing.v_total,
1975                                 context->streams[i]->timing.pix_clk_100hz / 10);
1976         }
1977
1978         dc_enable_stereo(dc, context, dc_streams, context->stream_count);
1979
1980         if (context->stream_count > get_seamless_boot_stream_count(context) ||
1981                 context->stream_count == 0) {
1982                 /* Must wait for no flips to be pending before doing optimize bw */
1983                 wait_for_no_pipes_pending(dc, context);
1984                 /* pplib is notified if disp_num changed */
1985                 dc->hwss.optimize_bandwidth(dc, context);
1986         }
1987
1988         if (dc->debug.enable_double_buffered_dsc_pg_support)
1989                 dc->hwss.update_dsc_pg(dc, context, true);
1990
1991         if (dc->ctx->dce_version >= DCE_VERSION_MAX)
1992                 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
1993         else
1994                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
1995
1996         context->stream_mask = get_stream_mask(dc, context);
1997
1998         if (context->stream_mask != dc->current_state->stream_mask)
1999                 dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);
2000
2001         for (i = 0; i < context->stream_count; i++)
2002                 context->streams[i]->mode_changed = false;
2003
2004         old_state = dc->current_state;
2005         dc->current_state = context;
2006
2007         dc_release_state(old_state);
2008
2009         dc_retain_state(dc->current_state);
2010
2011         return result;
2012 }
2013
2014 static bool commit_minimal_transition_state(struct dc *dc,
2015                 struct dc_state *transition_base_context);
2016
2017 /**
2018  * dc_commit_streams - Commit current stream state
2019  *
2020  * @dc: DC object with the commit state to be configured in the hardware
2021  * @streams: Array with a list of stream state
2022  * @stream_count: Total of streams
2023  *
2024  * Function responsible for commit streams change to the hardware.
2025  *
2026  * Return:
2027  * Return DC_OK if everything work as expected, otherwise, return a dc_status
2028  * code.
2029  */
2030 enum dc_status dc_commit_streams(struct dc *dc,
2031                                  struct dc_stream_state *streams[],
2032                                  uint8_t stream_count)
2033 {
2034         int i, j;
2035         struct dc_state *context;
2036         enum dc_status res = DC_OK;
2037         struct dc_validation_set set[MAX_STREAMS] = {0};
2038         struct pipe_ctx *pipe;
2039         bool handle_exit_odm2to1 = false;
2040
2041         if (dc->ctx->dce_environment == DCE_ENV_VIRTUAL_HW)
2042                 return res;
2043
2044         if (!streams_changed(dc, streams, stream_count))
2045                 return res;
2046
2047         DC_LOG_DC("%s: %d streams\n", __func__, stream_count);
2048
2049         for (i = 0; i < stream_count; i++) {
2050                 struct dc_stream_state *stream = streams[i];
2051                 struct dc_stream_status *status = dc_stream_get_status(stream);
2052
2053                 dc_stream_log(dc, stream);
2054
2055                 set[i].stream = stream;
2056
2057                 if (status) {
2058                         set[i].plane_count = status->plane_count;
2059                         for (j = 0; j < status->plane_count; j++)
2060                                 set[i].plane_states[j] = status->plane_states[j];
2061                 }
2062         }
2063
2064         /* Check for case where we are going from odm 2:1 to max
2065          *  pipe scenario.  For these cases, we will call
2066          *  commit_minimal_transition_state() to exit out of odm 2:1
2067          *  first before processing new streams
2068          */
2069         if (stream_count == dc->res_pool->pipe_count) {
2070                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2071                         pipe = &dc->current_state->res_ctx.pipe_ctx[i];
2072                         if (pipe->next_odm_pipe)
2073                                 handle_exit_odm2to1 = true;
2074                 }
2075         }
2076
2077         if (handle_exit_odm2to1)
2078                 res = commit_minimal_transition_state(dc, dc->current_state);
2079
2080         context = dc_create_state(dc);
2081         if (!context)
2082                 goto context_alloc_fail;
2083
2084         dc_resource_state_copy_construct_current(dc, context);
2085
2086         res = dc_validate_with_context(dc, set, stream_count, context, false);
2087         if (res != DC_OK) {
2088                 BREAK_TO_DEBUGGER();
2089                 goto fail;
2090         }
2091
2092         res = dc_commit_state_no_check(dc, context);
2093
2094         for (i = 0; i < stream_count; i++) {
2095                 for (j = 0; j < context->stream_count; j++) {
2096                         if (streams[i]->stream_id == context->streams[j]->stream_id)
2097                                 streams[i]->out.otg_offset = context->stream_status[j].primary_otg_inst;
2098
2099                         if (dc_is_embedded_signal(streams[i]->signal)) {
2100                                 struct dc_stream_status *status = dc_stream_get_status_from_state(context, streams[i]);
2101
2102                                 if (dc->hwss.is_abm_supported)
2103                                         status->is_abm_supported = dc->hwss.is_abm_supported(dc, context, streams[i]);
2104                                 else
2105                                         status->is_abm_supported = true;
2106                         }
2107                 }
2108         }
2109
2110 fail:
2111         dc_release_state(context);
2112
2113 context_alloc_fail:
2114
2115         DC_LOG_DC("%s Finished.\n", __func__);
2116
2117         return res;
2118 }
2119
2120 bool dc_acquire_release_mpc_3dlut(
2121                 struct dc *dc, bool acquire,
2122                 struct dc_stream_state *stream,
2123                 struct dc_3dlut **lut,
2124                 struct dc_transfer_func **shaper)
2125 {
2126         int pipe_idx;
2127         bool ret = false;
2128         bool found_pipe_idx = false;
2129         const struct resource_pool *pool = dc->res_pool;
2130         struct resource_context *res_ctx = &dc->current_state->res_ctx;
2131         int mpcc_id = 0;
2132
2133         if (pool && res_ctx) {
2134                 if (acquire) {
2135                         /*find pipe idx for the given stream*/
2136                         for (pipe_idx = 0; pipe_idx < pool->pipe_count; pipe_idx++) {
2137                                 if (res_ctx->pipe_ctx[pipe_idx].stream == stream) {
2138                                         found_pipe_idx = true;
2139                                         mpcc_id = res_ctx->pipe_ctx[pipe_idx].plane_res.hubp->inst;
2140                                         break;
2141                                 }
2142                         }
2143                 } else
2144                         found_pipe_idx = true;/*for release pipe_idx is not required*/
2145
2146                 if (found_pipe_idx) {
2147                         if (acquire && pool->funcs->acquire_post_bldn_3dlut)
2148                                 ret = pool->funcs->acquire_post_bldn_3dlut(res_ctx, pool, mpcc_id, lut, shaper);
2149                         else if (!acquire && pool->funcs->release_post_bldn_3dlut)
2150                                 ret = pool->funcs->release_post_bldn_3dlut(res_ctx, pool, lut, shaper);
2151                 }
2152         }
2153         return ret;
2154 }
2155
2156 static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
2157 {
2158         int i;
2159         struct pipe_ctx *pipe;
2160
2161         for (i = 0; i < MAX_PIPES; i++) {
2162                 pipe = &context->res_ctx.pipe_ctx[i];
2163
2164                 // Don't check flip pending on phantom pipes
2165                 if (!pipe->plane_state || (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM))
2166                         continue;
2167
2168                 /* Must set to false to start with, due to OR in update function */
2169                 pipe->plane_state->status.is_flip_pending = false;
2170                 dc->hwss.update_pending_status(pipe);
2171                 if (pipe->plane_state->status.is_flip_pending)
2172                         return true;
2173         }
2174         return false;
2175 }
2176
2177 /* Perform updates here which need to be deferred until next vupdate
2178  *
2179  * i.e. blnd lut, 3dlut, and shaper lut bypass regs are double buffered
2180  * but forcing lut memory to shutdown state is immediate. This causes
2181  * single frame corruption as lut gets disabled mid-frame unless shutdown
2182  * is deferred until after entering bypass.
2183  */
2184 static void process_deferred_updates(struct dc *dc)
2185 {
2186         int i = 0;
2187
2188         if (dc->debug.enable_mem_low_power.bits.cm) {
2189                 ASSERT(dc->dcn_ip->max_num_dpp);
2190                 for (i = 0; i < dc->dcn_ip->max_num_dpp; i++)
2191                         if (dc->res_pool->dpps[i]->funcs->dpp_deferred_update)
2192                                 dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]);
2193         }
2194 }
2195
2196 void dc_post_update_surfaces_to_stream(struct dc *dc)
2197 {
2198         int i;
2199         struct dc_state *context = dc->current_state;
2200
2201         if ((!dc->optimized_required) || get_seamless_boot_stream_count(context) > 0)
2202                 return;
2203
2204         post_surface_trace(dc);
2205
2206         /*
2207          * Only relevant for DCN behavior where we can guarantee the optimization
2208          * is safe to apply - retain the legacy behavior for DCE.
2209          */
2210
2211         if (dc->ctx->dce_version < DCE_VERSION_MAX)
2212                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
2213         else {
2214                 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk);
2215
2216                 if (is_flip_pending_in_pipes(dc, context))
2217                         return;
2218
2219                 for (i = 0; i < dc->res_pool->pipe_count; i++)
2220                         if (context->res_ctx.pipe_ctx[i].stream == NULL ||
2221                                         context->res_ctx.pipe_ctx[i].plane_state == NULL) {
2222                                 context->res_ctx.pipe_ctx[i].pipe_idx = i;
2223                                 dc->hwss.disable_plane(dc, &context->res_ctx.pipe_ctx[i]);
2224                         }
2225
2226                 process_deferred_updates(dc);
2227
2228                 dc->hwss.optimize_bandwidth(dc, context);
2229
2230                 if (dc->debug.enable_double_buffered_dsc_pg_support)
2231                         dc->hwss.update_dsc_pg(dc, context, true);
2232         }
2233
2234         dc->optimized_required = false;
2235         dc->wm_optimized_required = false;
2236 }
2237
2238 static void init_state(struct dc *dc, struct dc_state *context)
2239 {
2240         /* Each context must have their own instance of VBA and in order to
2241          * initialize and obtain IP and SOC the base DML instance from DC is
2242          * initially copied into every context
2243          */
2244         memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
2245 }
2246
2247 struct dc_state *dc_create_state(struct dc *dc)
2248 {
2249         struct dc_state *context = kvzalloc(sizeof(struct dc_state),
2250                                             GFP_KERNEL);
2251
2252         if (!context)
2253                 return NULL;
2254
2255         init_state(dc, context);
2256
2257         kref_init(&context->refcount);
2258
2259         return context;
2260 }
2261
2262 struct dc_state *dc_copy_state(struct dc_state *src_ctx)
2263 {
2264         int i, j;
2265         struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL);
2266
2267         if (!new_ctx)
2268                 return NULL;
2269         memcpy(new_ctx, src_ctx, sizeof(struct dc_state));
2270
2271         for (i = 0; i < MAX_PIPES; i++) {
2272                         struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i];
2273
2274                         if (cur_pipe->top_pipe)
2275                                 cur_pipe->top_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2276
2277                         if (cur_pipe->bottom_pipe)
2278                                 cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2279
2280                         if (cur_pipe->prev_odm_pipe)
2281                                 cur_pipe->prev_odm_pipe =  &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
2282
2283                         if (cur_pipe->next_odm_pipe)
2284                                 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
2285
2286         }
2287
2288         for (i = 0; i < new_ctx->stream_count; i++) {
2289                         dc_stream_retain(new_ctx->streams[i]);
2290                         for (j = 0; j < new_ctx->stream_status[i].plane_count; j++)
2291                                 dc_plane_state_retain(
2292                                         new_ctx->stream_status[i].plane_states[j]);
2293         }
2294
2295         kref_init(&new_ctx->refcount);
2296
2297         return new_ctx;
2298 }
2299
2300 void dc_retain_state(struct dc_state *context)
2301 {
2302         kref_get(&context->refcount);
2303 }
2304
2305 static void dc_state_free(struct kref *kref)
2306 {
2307         struct dc_state *context = container_of(kref, struct dc_state, refcount);
2308         dc_resource_state_destruct(context);
2309         kvfree(context);
2310 }
2311
2312 void dc_release_state(struct dc_state *context)
2313 {
2314         kref_put(&context->refcount, dc_state_free);
2315 }
2316
2317 bool dc_set_generic_gpio_for_stereo(bool enable,
2318                 struct gpio_service *gpio_service)
2319 {
2320         enum gpio_result gpio_result = GPIO_RESULT_NON_SPECIFIC_ERROR;
2321         struct gpio_pin_info pin_info;
2322         struct gpio *generic;
2323         struct gpio_generic_mux_config *config = kzalloc(sizeof(struct gpio_generic_mux_config),
2324                            GFP_KERNEL);
2325
2326         if (!config)
2327                 return false;
2328         pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 0);
2329
2330         if (pin_info.mask == 0xFFFFFFFF || pin_info.offset == 0xFFFFFFFF) {
2331                 kfree(config);
2332                 return false;
2333         } else {
2334                 generic = dal_gpio_service_create_generic_mux(
2335                         gpio_service,
2336                         pin_info.offset,
2337                         pin_info.mask);
2338         }
2339
2340         if (!generic) {
2341                 kfree(config);
2342                 return false;
2343         }
2344
2345         gpio_result = dal_gpio_open(generic, GPIO_MODE_OUTPUT);
2346
2347         config->enable_output_from_mux = enable;
2348         config->mux_select = GPIO_SIGNAL_SOURCE_PASS_THROUGH_STEREO_SYNC;
2349
2350         if (gpio_result == GPIO_RESULT_OK)
2351                 gpio_result = dal_mux_setup_config(generic, config);
2352
2353         if (gpio_result == GPIO_RESULT_OK) {
2354                 dal_gpio_close(generic);
2355                 dal_gpio_destroy_generic_mux(&generic);
2356                 kfree(config);
2357                 return true;
2358         } else {
2359                 dal_gpio_close(generic);
2360                 dal_gpio_destroy_generic_mux(&generic);
2361                 kfree(config);
2362                 return false;
2363         }
2364 }
2365
2366 static bool is_surface_in_context(
2367                 const struct dc_state *context,
2368                 const struct dc_plane_state *plane_state)
2369 {
2370         int j;
2371
2372         for (j = 0; j < MAX_PIPES; j++) {
2373                 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2374
2375                 if (plane_state == pipe_ctx->plane_state) {
2376                         return true;
2377                 }
2378         }
2379
2380         return false;
2381 }
2382
2383 static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u)
2384 {
2385         union surface_update_flags *update_flags = &u->surface->update_flags;
2386         enum surface_update_type update_type = UPDATE_TYPE_FAST;
2387
2388         if (!u->plane_info)
2389                 return UPDATE_TYPE_FAST;
2390
2391         if (u->plane_info->color_space != u->surface->color_space) {
2392                 update_flags->bits.color_space_change = 1;
2393                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2394         }
2395
2396         if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror) {
2397                 update_flags->bits.horizontal_mirror_change = 1;
2398                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2399         }
2400
2401         if (u->plane_info->rotation != u->surface->rotation) {
2402                 update_flags->bits.rotation_change = 1;
2403                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2404         }
2405
2406         if (u->plane_info->format != u->surface->format) {
2407                 update_flags->bits.pixel_format_change = 1;
2408                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2409         }
2410
2411         if (u->plane_info->stereo_format != u->surface->stereo_format) {
2412                 update_flags->bits.stereo_format_change = 1;
2413                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2414         }
2415
2416         if (u->plane_info->per_pixel_alpha != u->surface->per_pixel_alpha) {
2417                 update_flags->bits.per_pixel_alpha_change = 1;
2418                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2419         }
2420
2421         if (u->plane_info->global_alpha_value != u->surface->global_alpha_value) {
2422                 update_flags->bits.global_alpha_change = 1;
2423                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2424         }
2425
2426         if (u->plane_info->dcc.enable != u->surface->dcc.enable
2427                         || u->plane_info->dcc.dcc_ind_blk != u->surface->dcc.dcc_ind_blk
2428                         || u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
2429                 /* During DCC on/off, stutter period is calculated before
2430                  * DCC has fully transitioned. This results in incorrect
2431                  * stutter period calculation. Triggering a full update will
2432                  * recalculate stutter period.
2433                  */
2434                 update_flags->bits.dcc_change = 1;
2435                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2436         }
2437
2438         if (resource_pixel_format_to_bpp(u->plane_info->format) !=
2439                         resource_pixel_format_to_bpp(u->surface->format)) {
2440                 /* different bytes per element will require full bandwidth
2441                  * and DML calculation
2442                  */
2443                 update_flags->bits.bpp_change = 1;
2444                 elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2445         }
2446
2447         if (u->plane_info->plane_size.surface_pitch != u->surface->plane_size.surface_pitch
2448                         || u->plane_info->plane_size.chroma_pitch != u->surface->plane_size.chroma_pitch) {
2449                 update_flags->bits.plane_size_change = 1;
2450                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2451         }
2452
2453
2454         if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info,
2455                         sizeof(union dc_tiling_info)) != 0) {
2456                 update_flags->bits.swizzle_change = 1;
2457                 elevate_update_type(&update_type, UPDATE_TYPE_MED);
2458
2459                 /* todo: below are HW dependent, we should add a hook to
2460                  * DCE/N resource and validated there.
2461                  */
2462                 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
2463                         /* swizzled mode requires RQ to be setup properly,
2464                          * thus need to run DML to calculate RQ settings
2465                          */
2466                         update_flags->bits.bandwidth_change = 1;
2467                         elevate_update_type(&update_type, UPDATE_TYPE_FULL);
2468                 }
2469         }
2470
2471         /* This should be UPDATE_TYPE_FAST if nothing has changed. */
2472         return update_type;
2473 }
2474
2475 static enum surface_update_type get_scaling_info_update_type(
2476                 const struct dc_surface_update *u)
2477 {
2478         union surface_update_flags *update_flags = &u->surface->update_flags;
2479
2480         if (!u->scaling_info)
2481                 return UPDATE_TYPE_FAST;
2482
2483         if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width
2484                         || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
2485                         || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
2486                         || u->scaling_info->dst_rect.height != u->surface->dst_rect.height
2487                         || u->scaling_info->scaling_quality.integer_scaling !=
2488                                 u->surface->scaling_quality.integer_scaling
2489                         ) {
2490                 update_flags->bits.scaling_change = 1;
2491
2492                 if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width
2493                         || u->scaling_info->dst_rect.height < u->surface->dst_rect.height)
2494                                 && (u->scaling_info->dst_rect.width < u->surface->src_rect.width
2495                                         || u->scaling_info->dst_rect.height < u->surface->src_rect.height))
2496                         /* Making dst rect smaller requires a bandwidth change */
2497                         update_flags->bits.bandwidth_change = 1;
2498         }
2499
2500         if (u->scaling_info->src_rect.width != u->surface->src_rect.width
2501                 || u->scaling_info->src_rect.height != u->surface->src_rect.height) {
2502
2503                 update_flags->bits.scaling_change = 1;
2504                 if (u->scaling_info->src_rect.width > u->surface->src_rect.width
2505                                 || u->scaling_info->src_rect.height > u->surface->src_rect.height)
2506                         /* Making src rect bigger requires a bandwidth change */
2507                         update_flags->bits.clock_change = 1;
2508         }
2509
2510         if (u->scaling_info->src_rect.x != u->surface->src_rect.x
2511                         || u->scaling_info->src_rect.y != u->surface->src_rect.y
2512                         || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
2513                         || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
2514                         || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
2515                         || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
2516                 update_flags->bits.position_change = 1;
2517
2518         if (update_flags->bits.clock_change
2519                         || update_flags->bits.bandwidth_change
2520                         || update_flags->bits.scaling_change)
2521                 return UPDATE_TYPE_FULL;
2522
2523         if (update_flags->bits.position_change)
2524                 return UPDATE_TYPE_MED;
2525
2526         return UPDATE_TYPE_FAST;
2527 }
2528
2529 static enum surface_update_type det_surface_update(const struct dc *dc,
2530                 const struct dc_surface_update *u)
2531 {
2532         const struct dc_state *context = dc->current_state;
2533         enum surface_update_type type;
2534         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2535         union surface_update_flags *update_flags = &u->surface->update_flags;
2536
2537         if (!is_surface_in_context(context, u->surface) || u->surface->force_full_update) {
2538                 update_flags->raw = 0xFFFFFFFF;
2539                 return UPDATE_TYPE_FULL;
2540         }
2541
2542         update_flags->raw = 0; // Reset all flags
2543
2544         type = get_plane_info_update_type(u);
2545         elevate_update_type(&overall_type, type);
2546
2547         type = get_scaling_info_update_type(u);
2548         elevate_update_type(&overall_type, type);
2549
2550         if (u->flip_addr) {
2551                 update_flags->bits.addr_update = 1;
2552                 if (u->flip_addr->address.tmz_surface != u->surface->address.tmz_surface) {
2553                         update_flags->bits.tmz_changed = 1;
2554                         elevate_update_type(&overall_type, UPDATE_TYPE_FULL);
2555                 }
2556         }
2557         if (u->in_transfer_func)
2558                 update_flags->bits.in_transfer_func_change = 1;
2559
2560         if (u->input_csc_color_matrix)
2561                 update_flags->bits.input_csc_change = 1;
2562
2563         if (u->coeff_reduction_factor)
2564                 update_flags->bits.coeff_reduction_change = 1;
2565
2566         if (u->gamut_remap_matrix)
2567                 update_flags->bits.gamut_remap_change = 1;
2568
2569         if (u->gamma) {
2570                 enum surface_pixel_format format = SURFACE_PIXEL_FORMAT_GRPH_BEGIN;
2571
2572                 if (u->plane_info)
2573                         format = u->plane_info->format;
2574                 else if (u->surface)
2575                         format = u->surface->format;
2576
2577                 if (dce_use_lut(format))
2578                         update_flags->bits.gamma_change = 1;
2579         }
2580
2581         if (u->lut3d_func || u->func_shaper)
2582                 update_flags->bits.lut_3d = 1;
2583
2584         if (u->hdr_mult.value)
2585                 if (u->hdr_mult.value != u->surface->hdr_mult.value) {
2586                         update_flags->bits.hdr_mult = 1;
2587                         elevate_update_type(&overall_type, UPDATE_TYPE_MED);
2588                 }
2589
2590         if (update_flags->bits.in_transfer_func_change) {
2591                 type = UPDATE_TYPE_MED;
2592                 elevate_update_type(&overall_type, type);
2593         }
2594
2595         if (update_flags->bits.lut_3d) {
2596                 type = UPDATE_TYPE_FULL;
2597                 elevate_update_type(&overall_type, type);
2598         }
2599
2600         if (dc->debug.enable_legacy_fast_update &&
2601                         (update_flags->bits.gamma_change ||
2602                         update_flags->bits.gamut_remap_change ||
2603                         update_flags->bits.input_csc_change ||
2604                         update_flags->bits.coeff_reduction_change)) {
2605                 type = UPDATE_TYPE_FULL;
2606                 elevate_update_type(&overall_type, type);
2607         }
2608         return overall_type;
2609 }
2610
2611 static enum surface_update_type check_update_surfaces_for_stream(
2612                 struct dc *dc,
2613                 struct dc_surface_update *updates,
2614                 int surface_count,
2615                 struct dc_stream_update *stream_update,
2616                 const struct dc_stream_status *stream_status)
2617 {
2618         int i;
2619         enum surface_update_type overall_type = UPDATE_TYPE_FAST;
2620
2621         if (dc->idle_optimizations_allowed)
2622                 overall_type = UPDATE_TYPE_FULL;
2623
2624         if (stream_status == NULL || stream_status->plane_count != surface_count)
2625                 overall_type = UPDATE_TYPE_FULL;
2626
2627         if (stream_update && stream_update->pending_test_pattern) {
2628                 overall_type = UPDATE_TYPE_FULL;
2629         }
2630
2631         /* some stream updates require passive update */
2632         if (stream_update) {
2633                 union stream_update_flags *su_flags = &stream_update->stream->update_flags;
2634
2635                 if ((stream_update->src.height != 0 && stream_update->src.width != 0) ||
2636                         (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
2637                         stream_update->integer_scaling_update)
2638                         su_flags->bits.scaling = 1;
2639
2640                 if (dc->debug.enable_legacy_fast_update && stream_update->out_transfer_func)
2641                         su_flags->bits.out_tf = 1;
2642
2643                 if (stream_update->abm_level)
2644                         su_flags->bits.abm_level = 1;
2645
2646                 if (stream_update->dpms_off)
2647                         su_flags->bits.dpms_off = 1;
2648
2649                 if (stream_update->gamut_remap)
2650                         su_flags->bits.gamut_remap = 1;
2651
2652                 if (stream_update->wb_update)
2653                         su_flags->bits.wb_update = 1;
2654
2655                 if (stream_update->dsc_config)
2656                         su_flags->bits.dsc_changed = 1;
2657
2658                 if (stream_update->mst_bw_update)
2659                         su_flags->bits.mst_bw = 1;
2660
2661                 if (stream_update->stream && stream_update->stream->freesync_on_desktop &&
2662                         (stream_update->vrr_infopacket || stream_update->allow_freesync ||
2663                                 stream_update->vrr_active_variable || stream_update->vrr_active_fixed))
2664                         su_flags->bits.fams_changed = 1;
2665
2666                 if (su_flags->raw != 0)
2667                         overall_type = UPDATE_TYPE_FULL;
2668
2669                 if (stream_update->output_csc_transform || stream_update->output_color_space)
2670                         su_flags->bits.out_csc = 1;
2671
2672                 /* Output transfer function changes do not require bandwidth recalculation,
2673                  * so don't trigger a full update
2674                  */
2675                 if (!dc->debug.enable_legacy_fast_update && stream_update->out_transfer_func)
2676                         su_flags->bits.out_tf = 1;
2677         }
2678
2679         for (i = 0 ; i < surface_count; i++) {
2680                 enum surface_update_type type =
2681                                 det_surface_update(dc, &updates[i]);
2682
2683                 elevate_update_type(&overall_type, type);
2684         }
2685
2686         return overall_type;
2687 }
2688
2689 static bool dc_check_is_fullscreen_video(struct rect src, struct rect clip_rect)
2690 {
2691         int view_height, view_width, clip_x, clip_y, clip_width, clip_height;
2692
2693         view_height = src.height;
2694         view_width = src.width;
2695
2696         clip_x = clip_rect.x;
2697         clip_y = clip_rect.y;
2698
2699         clip_width = clip_rect.width;
2700         clip_height = clip_rect.height;
2701
2702         /* check for centered video accounting for off by 1 scaling truncation */
2703         if ((view_height - clip_y - clip_height <= clip_y + 1) &&
2704                         (view_width - clip_x - clip_width <= clip_x + 1) &&
2705                         (view_height - clip_y - clip_height >= clip_y - 1) &&
2706                         (view_width - clip_x - clip_width >= clip_x - 1)) {
2707
2708                 /* when OS scales up/down to letter box, it may end up
2709                  * with few blank pixels on the border due to truncating.
2710                  * Add offset margin to account for this
2711                  */
2712                 if (clip_x <= 4 || clip_y <= 4)
2713                         return true;
2714         }
2715
2716         return false;
2717 }
2718
2719 static enum surface_update_type check_boundary_crossing_for_windowed_mpo_with_odm(struct dc *dc,
2720                 struct dc_surface_update *srf_updates, int surface_count,
2721                 enum surface_update_type update_type)
2722 {
2723         enum surface_update_type new_update_type = update_type;
2724         int i, j;
2725         struct pipe_ctx *pipe = NULL;
2726         struct dc_stream_state *stream;
2727
2728         /* Check that we are in windowed MPO with ODM
2729          * - look for MPO pipe by scanning pipes for first pipe matching
2730          *   surface that has moved ( position change )
2731          * - MPO pipe will have top pipe
2732          * - check that top pipe has ODM pointer
2733          */
2734         if ((surface_count > 1) && dc->config.enable_windowed_mpo_odm) {
2735                 for (i = 0; i < surface_count; i++) {
2736                         if (srf_updates[i].surface && srf_updates[i].scaling_info
2737                                         && srf_updates[i].surface->update_flags.bits.position_change) {
2738
2739                                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2740                                         if (srf_updates[i].surface == dc->current_state->res_ctx.pipe_ctx[j].plane_state) {
2741                                                 pipe = &dc->current_state->res_ctx.pipe_ctx[j];
2742                                                 stream = pipe->stream;
2743                                                 break;
2744                                         }
2745                                 }
2746
2747                                 if (pipe && pipe->top_pipe && (get_num_odm_splits(pipe->top_pipe) > 0) && stream
2748                                                 && !dc_check_is_fullscreen_video(stream->src, srf_updates[i].scaling_info->clip_rect)) {
2749                                         struct rect old_clip_rect, new_clip_rect;
2750                                         bool old_clip_rect_left, old_clip_rect_right, old_clip_rect_middle;
2751                                         bool new_clip_rect_left, new_clip_rect_right, new_clip_rect_middle;
2752
2753                                         old_clip_rect = srf_updates[i].surface->clip_rect;
2754                                         new_clip_rect = srf_updates[i].scaling_info->clip_rect;
2755
2756                                         old_clip_rect_left = ((old_clip_rect.x + old_clip_rect.width) <= (stream->src.x + (stream->src.width/2)));
2757                                         old_clip_rect_right = (old_clip_rect.x >= (stream->src.x + (stream->src.width/2)));
2758                                         old_clip_rect_middle = !old_clip_rect_left && !old_clip_rect_right;
2759
2760                                         new_clip_rect_left = ((new_clip_rect.x + new_clip_rect.width) <= (stream->src.x + (stream->src.width/2)));
2761                                         new_clip_rect_right = (new_clip_rect.x >= (stream->src.x + (stream->src.width/2)));
2762                                         new_clip_rect_middle = !new_clip_rect_left && !new_clip_rect_right;
2763
2764                                         if (old_clip_rect_left && new_clip_rect_middle)
2765                                                 new_update_type = UPDATE_TYPE_FULL;
2766                                         else if (old_clip_rect_middle && new_clip_rect_right)
2767                                                 new_update_type = UPDATE_TYPE_FULL;
2768                                         else if (old_clip_rect_right && new_clip_rect_middle)
2769                                                 new_update_type = UPDATE_TYPE_FULL;
2770                                         else if (old_clip_rect_middle && new_clip_rect_left)
2771                                                 new_update_type = UPDATE_TYPE_FULL;
2772                                 }
2773                         }
2774                 }
2775         }
2776         return new_update_type;
2777 }
2778
2779 /*
2780  * dc_check_update_surfaces_for_stream() - Determine update type (fast, med, or full)
2781  *
2782  * See :c:type:`enum surface_update_type <surface_update_type>` for explanation of update types
2783  */
2784 enum surface_update_type dc_check_update_surfaces_for_stream(
2785                 struct dc *dc,
2786                 struct dc_surface_update *updates,
2787                 int surface_count,
2788                 struct dc_stream_update *stream_update,
2789                 const struct dc_stream_status *stream_status)
2790 {
2791         int i;
2792         enum surface_update_type type;
2793
2794         if (stream_update)
2795                 stream_update->stream->update_flags.raw = 0;
2796         for (i = 0; i < surface_count; i++)
2797                 updates[i].surface->update_flags.raw = 0;
2798
2799         type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
2800         if (type == UPDATE_TYPE_FULL) {
2801                 if (stream_update) {
2802                         uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed;
2803                         stream_update->stream->update_flags.raw = 0xFFFFFFFF;
2804                         stream_update->stream->update_flags.bits.dsc_changed = dsc_changed;
2805                 }
2806                 for (i = 0; i < surface_count; i++)
2807                         updates[i].surface->update_flags.raw = 0xFFFFFFFF;
2808         }
2809
2810         if (type == UPDATE_TYPE_MED)
2811                 type = check_boundary_crossing_for_windowed_mpo_with_odm(dc,
2812                                 updates, surface_count, type);
2813
2814         if (type == UPDATE_TYPE_FAST) {
2815                 // If there's an available clock comparator, we use that.
2816                 if (dc->clk_mgr->funcs->are_clock_states_equal) {
2817                         if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.dcn.clk))
2818                                 dc->optimized_required = true;
2819                 // Else we fallback to mem compare.
2820                 } else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_clocks, prev_p_state_change_support)) != 0) {
2821                         dc->optimized_required = true;
2822                 }
2823
2824                 dc->optimized_required |= dc->wm_optimized_required;
2825         }
2826
2827         return type;
2828 }
2829
2830 static struct dc_stream_status *stream_get_status(
2831         struct dc_state *ctx,
2832         struct dc_stream_state *stream)
2833 {
2834         uint8_t i;
2835
2836         for (i = 0; i < ctx->stream_count; i++) {
2837                 if (stream == ctx->streams[i]) {
2838                         return &ctx->stream_status[i];
2839                 }
2840         }
2841
2842         return NULL;
2843 }
2844
2845 static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
2846
2847 static void copy_surface_update_to_plane(
2848                 struct dc_plane_state *surface,
2849                 struct dc_surface_update *srf_update)
2850 {
2851         if (srf_update->flip_addr) {
2852                 surface->address = srf_update->flip_addr->address;
2853                 surface->flip_immediate =
2854                         srf_update->flip_addr->flip_immediate;
2855                 surface->time.time_elapsed_in_us[surface->time.index] =
2856                         srf_update->flip_addr->flip_timestamp_in_us -
2857                                 surface->time.prev_update_time_in_us;
2858                 surface->time.prev_update_time_in_us =
2859                         srf_update->flip_addr->flip_timestamp_in_us;
2860                 surface->time.index++;
2861                 if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
2862                         surface->time.index = 0;
2863
2864                 surface->triplebuffer_flips = srf_update->flip_addr->triplebuffer_flips;
2865         }
2866
2867         if (srf_update->scaling_info) {
2868                 surface->scaling_quality =
2869                                 srf_update->scaling_info->scaling_quality;
2870                 surface->dst_rect =
2871                                 srf_update->scaling_info->dst_rect;
2872                 surface->src_rect =
2873                                 srf_update->scaling_info->src_rect;
2874                 surface->clip_rect =
2875                                 srf_update->scaling_info->clip_rect;
2876         }
2877
2878         if (srf_update->plane_info) {
2879                 surface->color_space =
2880                                 srf_update->plane_info->color_space;
2881                 surface->format =
2882                                 srf_update->plane_info->format;
2883                 surface->plane_size =
2884                                 srf_update->plane_info->plane_size;
2885                 surface->rotation =
2886                                 srf_update->plane_info->rotation;
2887                 surface->horizontal_mirror =
2888                                 srf_update->plane_info->horizontal_mirror;
2889                 surface->stereo_format =
2890                                 srf_update->plane_info->stereo_format;
2891                 surface->tiling_info =
2892                                 srf_update->plane_info->tiling_info;
2893                 surface->visible =
2894                                 srf_update->plane_info->visible;
2895                 surface->per_pixel_alpha =
2896                                 srf_update->plane_info->per_pixel_alpha;
2897                 surface->global_alpha =
2898                                 srf_update->plane_info->global_alpha;
2899                 surface->global_alpha_value =
2900                                 srf_update->plane_info->global_alpha_value;
2901                 surface->dcc =
2902                                 srf_update->plane_info->dcc;
2903                 surface->layer_index =
2904                                 srf_update->plane_info->layer_index;
2905         }
2906
2907         if (srf_update->gamma &&
2908                         (surface->gamma_correction !=
2909                                         srf_update->gamma)) {
2910                 memcpy(&surface->gamma_correction->entries,
2911                         &srf_update->gamma->entries,
2912                         sizeof(struct dc_gamma_entries));
2913                 surface->gamma_correction->is_identity =
2914                         srf_update->gamma->is_identity;
2915                 surface->gamma_correction->num_entries =
2916                         srf_update->gamma->num_entries;
2917                 surface->gamma_correction->type =
2918                         srf_update->gamma->type;
2919         }
2920
2921         if (srf_update->in_transfer_func &&
2922                         (surface->in_transfer_func !=
2923                                 srf_update->in_transfer_func)) {
2924                 surface->in_transfer_func->sdr_ref_white_level =
2925                         srf_update->in_transfer_func->sdr_ref_white_level;
2926                 surface->in_transfer_func->tf =
2927                         srf_update->in_transfer_func->tf;
2928                 surface->in_transfer_func->type =
2929                         srf_update->in_transfer_func->type;
2930                 memcpy(&surface->in_transfer_func->tf_pts,
2931                         &srf_update->in_transfer_func->tf_pts,
2932                         sizeof(struct dc_transfer_func_distributed_points));
2933         }
2934
2935         if (srf_update->func_shaper &&
2936                         (surface->in_shaper_func !=
2937                         srf_update->func_shaper))
2938                 memcpy(surface->in_shaper_func, srf_update->func_shaper,
2939                 sizeof(*surface->in_shaper_func));
2940
2941         if (srf_update->lut3d_func &&
2942                         (surface->lut3d_func !=
2943                         srf_update->lut3d_func))
2944                 memcpy(surface->lut3d_func, srf_update->lut3d_func,
2945                 sizeof(*surface->lut3d_func));
2946
2947         if (srf_update->hdr_mult.value)
2948                 surface->hdr_mult =
2949                                 srf_update->hdr_mult;
2950
2951         if (srf_update->blend_tf &&
2952                         (surface->blend_tf !=
2953                         srf_update->blend_tf))
2954                 memcpy(surface->blend_tf, srf_update->blend_tf,
2955                 sizeof(*surface->blend_tf));
2956
2957         if (srf_update->input_csc_color_matrix)
2958                 surface->input_csc_color_matrix =
2959                         *srf_update->input_csc_color_matrix;
2960
2961         if (srf_update->coeff_reduction_factor)
2962                 surface->coeff_reduction_factor =
2963                         *srf_update->coeff_reduction_factor;
2964
2965         if (srf_update->gamut_remap_matrix)
2966                 surface->gamut_remap_matrix =
2967                         *srf_update->gamut_remap_matrix;
2968 }
2969
2970 static void copy_stream_update_to_stream(struct dc *dc,
2971                                          struct dc_state *context,
2972                                          struct dc_stream_state *stream,
2973                                          struct dc_stream_update *update)
2974 {
2975         struct dc_context *dc_ctx = dc->ctx;
2976
2977         if (update == NULL || stream == NULL)
2978                 return;
2979
2980         if (update->src.height && update->src.width)
2981                 stream->src = update->src;
2982
2983         if (update->dst.height && update->dst.width)
2984                 stream->dst = update->dst;
2985
2986         if (update->out_transfer_func &&
2987             stream->out_transfer_func != update->out_transfer_func) {
2988                 stream->out_transfer_func->sdr_ref_white_level =
2989                         update->out_transfer_func->sdr_ref_white_level;
2990                 stream->out_transfer_func->tf = update->out_transfer_func->tf;
2991                 stream->out_transfer_func->type =
2992                         update->out_transfer_func->type;
2993                 memcpy(&stream->out_transfer_func->tf_pts,
2994                        &update->out_transfer_func->tf_pts,
2995                        sizeof(struct dc_transfer_func_distributed_points));
2996         }
2997
2998         if (update->hdr_static_metadata)
2999                 stream->hdr_static_metadata = *update->hdr_static_metadata;
3000
3001         if (update->abm_level)
3002                 stream->abm_level = *update->abm_level;
3003
3004         if (update->periodic_interrupt)
3005                 stream->periodic_interrupt = *update->periodic_interrupt;
3006
3007         if (update->gamut_remap)
3008                 stream->gamut_remap_matrix = *update->gamut_remap;
3009
3010         /* Note: this being updated after mode set is currently not a use case
3011          * however if it arises OCSC would need to be reprogrammed at the
3012          * minimum
3013          */
3014         if (update->output_color_space)
3015                 stream->output_color_space = *update->output_color_space;
3016
3017         if (update->output_csc_transform)
3018                 stream->csc_color_matrix = *update->output_csc_transform;
3019
3020         if (update->vrr_infopacket)
3021                 stream->vrr_infopacket = *update->vrr_infopacket;
3022
3023         if (update->allow_freesync)
3024                 stream->allow_freesync = *update->allow_freesync;
3025
3026         if (update->vrr_active_variable)
3027                 stream->vrr_active_variable = *update->vrr_active_variable;
3028
3029         if (update->vrr_active_fixed)
3030                 stream->vrr_active_fixed = *update->vrr_active_fixed;
3031
3032         if (update->crtc_timing_adjust)
3033                 stream->adjust = *update->crtc_timing_adjust;
3034
3035         if (update->dpms_off)
3036                 stream->dpms_off = *update->dpms_off;
3037
3038         if (update->hfvsif_infopacket)
3039                 stream->hfvsif_infopacket = *update->hfvsif_infopacket;
3040
3041         if (update->vtem_infopacket)
3042                 stream->vtem_infopacket = *update->vtem_infopacket;
3043
3044         if (update->vsc_infopacket)
3045                 stream->vsc_infopacket = *update->vsc_infopacket;
3046
3047         if (update->vsp_infopacket)
3048                 stream->vsp_infopacket = *update->vsp_infopacket;
3049
3050         if (update->adaptive_sync_infopacket)
3051                 stream->adaptive_sync_infopacket = *update->adaptive_sync_infopacket;
3052
3053         if (update->dither_option)
3054                 stream->dither_option = *update->dither_option;
3055
3056         if (update->pending_test_pattern)
3057                 stream->test_pattern = *update->pending_test_pattern;
3058         /* update current stream with writeback info */
3059         if (update->wb_update) {
3060                 int i;
3061
3062                 stream->num_wb_info = update->wb_update->num_wb_info;
3063                 ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);
3064                 for (i = 0; i < stream->num_wb_info; i++)
3065                         stream->writeback_info[i] =
3066                                 update->wb_update->writeback_info[i];
3067         }
3068         if (update->dsc_config) {
3069                 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg;
3070                 uint32_t old_dsc_enabled = stream->timing.flags.DSC;
3071                 uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&
3072                                        update->dsc_config->num_slices_v != 0);
3073
3074                 /* Use temporarry context for validating new DSC config */
3075                 struct dc_state *dsc_validate_context = dc_create_state(dc);
3076
3077                 if (dsc_validate_context) {
3078                         dc_resource_state_copy_construct(dc->current_state, dsc_validate_context);
3079
3080                         stream->timing.dsc_cfg = *update->dsc_config;
3081                         stream->timing.flags.DSC = enable_dsc;
3082                         if (!dc->res_pool->funcs->validate_bandwidth(dc, dsc_validate_context, true)) {
3083                                 stream->timing.dsc_cfg = old_dsc_cfg;
3084                                 stream->timing.flags.DSC = old_dsc_enabled;
3085                                 update->dsc_config = NULL;
3086                         }
3087
3088                         dc_release_state(dsc_validate_context);
3089                 } else {
3090                         DC_ERROR("Failed to allocate new validate context for DSC change\n");
3091                         update->dsc_config = NULL;
3092                 }
3093         }
3094 }
3095
3096 static bool update_planes_and_stream_state(struct dc *dc,
3097                 struct dc_surface_update *srf_updates, int surface_count,
3098                 struct dc_stream_state *stream,
3099                 struct dc_stream_update *stream_update,
3100                 enum surface_update_type *new_update_type,
3101                 struct dc_state **new_context)
3102 {
3103         struct dc_state *context;
3104         int i, j;
3105         enum surface_update_type update_type;
3106         const struct dc_stream_status *stream_status;
3107         struct dc_context *dc_ctx = dc->ctx;
3108
3109         stream_status = dc_stream_get_status(stream);
3110
3111         if (!stream_status) {
3112                 if (surface_count) /* Only an error condition if surf_count non-zero*/
3113                         ASSERT(false);
3114
3115                 return false; /* Cannot commit surface to stream that is not committed */
3116         }
3117
3118         context = dc->current_state;
3119
3120         update_type = dc_check_update_surfaces_for_stream(
3121                         dc, srf_updates, surface_count, stream_update, stream_status);
3122
3123         /* update current stream with the new updates */
3124         copy_stream_update_to_stream(dc, context, stream, stream_update);
3125
3126         /* do not perform surface update if surface has invalid dimensions
3127          * (all zero) and no scaling_info is provided
3128          */
3129         if (surface_count > 0) {
3130                 for (i = 0; i < surface_count; i++) {
3131                         if ((srf_updates[i].surface->src_rect.width == 0 ||
3132                                  srf_updates[i].surface->src_rect.height == 0 ||
3133                                  srf_updates[i].surface->dst_rect.width == 0 ||
3134                                  srf_updates[i].surface->dst_rect.height == 0) &&
3135                                 (!srf_updates[i].scaling_info ||
3136                                   srf_updates[i].scaling_info->src_rect.width == 0 ||
3137                                   srf_updates[i].scaling_info->src_rect.height == 0 ||
3138                                   srf_updates[i].scaling_info->dst_rect.width == 0 ||
3139                                   srf_updates[i].scaling_info->dst_rect.height == 0)) {
3140                                 DC_ERROR("Invalid src/dst rects in surface update!\n");
3141                                 return false;
3142                         }
3143                 }
3144         }
3145
3146         if (update_type >= update_surface_trace_level)
3147                 update_surface_trace(dc, srf_updates, surface_count);
3148
3149         if (update_type >= UPDATE_TYPE_FULL) {
3150                 struct dc_plane_state *new_planes[MAX_SURFACES] = {0};
3151
3152                 for (i = 0; i < surface_count; i++)
3153                         new_planes[i] = srf_updates[i].surface;
3154
3155                 /* initialize scratch memory for building context */
3156                 context = dc_create_state(dc);
3157                 if (context == NULL) {
3158                         DC_ERROR("Failed to allocate new validate context!\n");
3159                         return false;
3160                 }
3161
3162                 dc_resource_state_copy_construct(
3163                                 dc->current_state, context);
3164
3165                 /* For each full update, remove all existing phantom pipes first.
3166                  * Ensures that we have enough pipes for newly added MPO planes
3167                  */
3168                 if (dc->res_pool->funcs->remove_phantom_pipes)
3169                         dc->res_pool->funcs->remove_phantom_pipes(dc, context, false);
3170
3171                 /*remove old surfaces from context */
3172                 if (!dc_rem_all_planes_for_stream(dc, stream, context)) {
3173
3174                         BREAK_TO_DEBUGGER();
3175                         goto fail;
3176                 }
3177
3178                 /* add surface to context */
3179                 if (!dc_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) {
3180
3181                         BREAK_TO_DEBUGGER();
3182                         goto fail;
3183                 }
3184         }
3185
3186         /* save update parameters into surface */
3187         for (i = 0; i < surface_count; i++) {
3188                 struct dc_plane_state *surface = srf_updates[i].surface;
3189
3190                 copy_surface_update_to_plane(surface, &srf_updates[i]);
3191
3192                 if (update_type >= UPDATE_TYPE_MED) {
3193                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3194                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3195
3196                                 if (pipe_ctx->plane_state != surface)
3197                                         continue;
3198
3199                                 resource_build_scaling_params(pipe_ctx);
3200                         }
3201                 }
3202         }
3203
3204         if (update_type == UPDATE_TYPE_FULL) {
3205                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
3206                         /* For phantom pipes we remove and create a new set of phantom pipes
3207                          * for each full update (because we don't know if we'll need phantom
3208                          * pipes until after the first round of validation). However, if validation
3209                          * fails we need to keep the existing phantom pipes (because we don't update
3210                          * the dc->current_state).
3211                          *
3212                          * The phantom stream/plane refcount is decremented for validation because
3213                          * we assume it'll be removed (the free comes when the dc_state is freed),
3214                          * but if validation fails we have to increment back the refcount so it's
3215                          * consistent.
3216                          */
3217                         if (dc->res_pool->funcs->retain_phantom_pipes)
3218                                 dc->res_pool->funcs->retain_phantom_pipes(dc, dc->current_state);
3219                         BREAK_TO_DEBUGGER();
3220                         goto fail;
3221                 }
3222         }
3223
3224         *new_context = context;
3225         *new_update_type = update_type;
3226
3227         return true;
3228
3229 fail:
3230         dc_release_state(context);
3231
3232         return false;
3233
3234 }
3235
3236 static void commit_planes_do_stream_update(struct dc *dc,
3237                 struct dc_stream_state *stream,
3238                 struct dc_stream_update *stream_update,
3239                 enum surface_update_type update_type,
3240                 struct dc_state *context)
3241 {
3242         int j;
3243
3244         // Stream updates
3245         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3246                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3247
3248                 if (!pipe_ctx->top_pipe &&  !pipe_ctx->prev_odm_pipe && pipe_ctx->stream == stream) {
3249
3250                         if (stream_update->periodic_interrupt && dc->hwss.setup_periodic_interrupt)
3251                                 dc->hwss.setup_periodic_interrupt(dc, pipe_ctx);
3252
3253                         if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
3254                                         stream_update->vrr_infopacket ||
3255                                         stream_update->vsc_infopacket ||
3256                                         stream_update->vsp_infopacket ||
3257                                         stream_update->hfvsif_infopacket ||
3258                                         stream_update->adaptive_sync_infopacket ||
3259                                         stream_update->vtem_infopacket) {
3260                                 resource_build_info_frame(pipe_ctx);
3261                                 dc->hwss.update_info_frame(pipe_ctx);
3262
3263                                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3264                                         dc->link_srv->dp_trace_source_sequence(
3265                                                         pipe_ctx->stream->link,
3266                                                         DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
3267                         }
3268
3269                         if (stream_update->hdr_static_metadata &&
3270                                         stream->use_dynamic_meta &&
3271                                         dc->hwss.set_dmdata_attributes &&
3272                                         pipe_ctx->stream->dmdata_address.quad_part != 0)
3273                                 dc->hwss.set_dmdata_attributes(pipe_ctx);
3274
3275                         if (stream_update->gamut_remap)
3276                                 dc_stream_set_gamut_remap(dc, stream);
3277
3278                         if (stream_update->output_csc_transform)
3279                                 dc_stream_program_csc_matrix(dc, stream);
3280
3281                         if (stream_update->dither_option) {
3282                                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
3283                                 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
3284                                                                         &pipe_ctx->stream->bit_depth_params);
3285                                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(pipe_ctx->stream_res.opp,
3286                                                 &stream->bit_depth_params,
3287                                                 &stream->clamping);
3288                                 while (odm_pipe) {
3289                                         odm_pipe->stream_res.opp->funcs->opp_program_fmt(odm_pipe->stream_res.opp,
3290                                                         &stream->bit_depth_params,
3291                                                         &stream->clamping);
3292                                         odm_pipe = odm_pipe->next_odm_pipe;
3293                                 }
3294                         }
3295
3296
3297                         /* Full fe update*/
3298                         if (update_type == UPDATE_TYPE_FAST)
3299                                 continue;
3300
3301                         if (stream_update->dsc_config)
3302                                 dc->link_srv->update_dsc_config(pipe_ctx);
3303
3304                         if (stream_update->mst_bw_update) {
3305                                 if (stream_update->mst_bw_update->is_increase)
3306                                         dc->link_srv->increase_mst_payload(pipe_ctx,
3307                                                         stream_update->mst_bw_update->mst_stream_bw);
3308                                 else
3309                                         dc->link_srv->reduce_mst_payload(pipe_ctx,
3310                                                         stream_update->mst_bw_update->mst_stream_bw);
3311                         }
3312
3313                         if (stream_update->pending_test_pattern) {
3314                                 dc_link_dp_set_test_pattern(stream->link,
3315                                         stream->test_pattern.type,
3316                                         stream->test_pattern.color_space,
3317                                         stream->test_pattern.p_link_settings,
3318                                         stream->test_pattern.p_custom_pattern,
3319                                         stream->test_pattern.cust_pattern_size);
3320                         }
3321
3322                         if (stream_update->dpms_off) {
3323                                 if (*stream_update->dpms_off) {
3324                                         dc->link_srv->set_dpms_off(pipe_ctx);
3325                                         /* for dpms, keep acquired resources*/
3326                                         if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
3327                                                 pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
3328
3329                                         dc->optimized_required = true;
3330
3331                                 } else {
3332                                         if (get_seamless_boot_stream_count(context) == 0)
3333                                                 dc->hwss.prepare_bandwidth(dc, dc->current_state);
3334                                         dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);
3335                                 }
3336                         } else if (pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change && stream_update->output_color_space
3337                                         && !stream->dpms_off && dc_is_dp_signal(pipe_ctx->stream->signal)) {
3338                                 /*
3339                                  * Workaround for firmware issue in some receivers where they don't pick up
3340                                  * correct output color space unless DP link is disabled/re-enabled
3341                                  */
3342                                 dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);
3343                         }
3344
3345                         if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
3346                                 bool should_program_abm = true;
3347
3348                                 // if otg funcs defined check if blanked before programming
3349                                 if (pipe_ctx->stream_res.tg->funcs->is_blanked)
3350                                         if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg))
3351                                                 should_program_abm = false;
3352
3353                                 if (should_program_abm) {
3354                                         if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) {
3355                                                 dc->hwss.set_abm_immediate_disable(pipe_ctx);
3356                                         } else {
3357                                                 pipe_ctx->stream_res.abm->funcs->set_abm_level(
3358                                                         pipe_ctx->stream_res.abm, stream->abm_level);
3359                                         }
3360                                 }
3361                         }
3362                 }
3363         }
3364 }
3365
3366 static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_state *stream)
3367 {
3368         if ((stream->link->psr_settings.psr_version == DC_PSR_VERSION_SU_1
3369                         || stream->link->psr_settings.psr_version == DC_PSR_VERSION_1)
3370                         && stream->ctx->dce_version >= DCN_VERSION_3_1)
3371                 return true;
3372
3373         return false;
3374 }
3375
3376 void dc_dmub_update_dirty_rect(struct dc *dc,
3377                                int surface_count,
3378                                struct dc_stream_state *stream,
3379                                struct dc_surface_update *srf_updates,
3380                                struct dc_state *context)
3381 {
3382         union dmub_rb_cmd cmd;
3383         struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
3384         unsigned int i, j;
3385         unsigned int panel_inst = 0;
3386
3387         if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
3388                 return;
3389
3390         if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
3391                 return;
3392
3393         memset(&cmd, 0x0, sizeof(cmd));
3394         cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
3395         cmd.update_dirty_rect.header.sub_type = 0;
3396         cmd.update_dirty_rect.header.payload_bytes =
3397                 sizeof(cmd.update_dirty_rect) -
3398                 sizeof(cmd.update_dirty_rect.header);
3399         update_dirty_rect = &cmd.update_dirty_rect.update_dirty_rect_data;
3400         for (i = 0; i < surface_count; i++) {
3401                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3402                 const struct dc_flip_addrs *flip_addr = srf_updates[i].flip_addr;
3403
3404                 if (!srf_updates[i].surface || !flip_addr)
3405                         continue;
3406                 /* Do not send in immediate flip mode */
3407                 if (srf_updates[i].surface->flip_immediate)
3408                         continue;
3409
3410                 update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
3411                 memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
3412                                 sizeof(flip_addr->dirty_rects));
3413                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3414                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3415
3416                         if (pipe_ctx->stream != stream)
3417                                 continue;
3418                         if (pipe_ctx->plane_state != plane_state)
3419                                 continue;
3420
3421                         update_dirty_rect->panel_inst = panel_inst;
3422                         update_dirty_rect->pipe_idx = j;
3423                         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
3424                 }
3425         }
3426 }
3427
3428 static void build_dmub_update_dirty_rect(
3429                 struct dc *dc,
3430                 int surface_count,
3431                 struct dc_stream_state *stream,
3432                 struct dc_surface_update *srf_updates,
3433                 struct dc_state *context,
3434                 struct dc_dmub_cmd dc_dmub_cmd[],
3435                 unsigned int *dmub_cmd_count)
3436 {
3437         union dmub_rb_cmd cmd;
3438         struct dmub_cmd_update_dirty_rect_data *update_dirty_rect;
3439         unsigned int i, j;
3440         unsigned int panel_inst = 0;
3441
3442         if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
3443                 return;
3444
3445         if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
3446                 return;
3447
3448         memset(&cmd, 0x0, sizeof(cmd));
3449         cmd.update_dirty_rect.header.type = DMUB_CMD__UPDATE_DIRTY_RECT;
3450         cmd.update_dirty_rect.header.sub_type = 0;
3451         cmd.update_dirty_rect.header.payload_bytes =
3452                 sizeof(cmd.update_dirty_rect) -
3453                 sizeof(cmd.update_dirty_rect.header);
3454         update_dirty_rect = &cmd.update_dirty_rect.update_dirty_rect_data;
3455         for (i = 0; i < surface_count; i++) {
3456                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3457                 const struct dc_flip_addrs *flip_addr = srf_updates[i].flip_addr;
3458
3459                 if (!srf_updates[i].surface || !flip_addr)
3460                         continue;
3461                 /* Do not send in immediate flip mode */
3462                 if (srf_updates[i].surface->flip_immediate)
3463                         continue;
3464                 update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
3465                 update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
3466                 memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
3467                                 sizeof(flip_addr->dirty_rects));
3468                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3469                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3470
3471                         if (pipe_ctx->stream != stream)
3472                                 continue;
3473                         if (pipe_ctx->plane_state != plane_state)
3474                                 continue;
3475                         update_dirty_rect->panel_inst = panel_inst;
3476                         update_dirty_rect->pipe_idx = j;
3477                         dc_dmub_cmd[*dmub_cmd_count].dmub_cmd = cmd;
3478                         dc_dmub_cmd[*dmub_cmd_count].wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT;
3479                         (*dmub_cmd_count)++;
3480                 }
3481         }
3482 }
3483
3484
3485 /**
3486  * build_dmub_cmd_list() - Build an array of DMCUB commands to be sent to DMCUB
3487  *
3488  * @dc: Current DC state
3489  * @srf_updates: Array of surface updates
3490  * @surface_count: Number of surfaces that have an updated
3491  * @stream: Corresponding stream to be updated in the current flip
3492  * @context: New DC state to be programmed
3493  *
3494  * @dc_dmub_cmd: Array of DMCUB commands to be sent to DMCUB
3495  * @dmub_cmd_count: Count indicating the number of DMCUB commands in dc_dmub_cmd array
3496  *
3497  * This function builds an array of DMCUB commands to be sent to DMCUB. This function is required
3498  * to build an array of commands and have them sent while the OTG lock is acquired.
3499  *
3500  * Return: void
3501  */
3502 static void build_dmub_cmd_list(struct dc *dc,
3503                 struct dc_surface_update *srf_updates,
3504                 int surface_count,
3505                 struct dc_stream_state *stream,
3506                 struct dc_state *context,
3507                 struct dc_dmub_cmd dc_dmub_cmd[],
3508                 unsigned int *dmub_cmd_count)
3509 {
3510         // Initialize cmd count to 0
3511         *dmub_cmd_count = 0;
3512         build_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context, dc_dmub_cmd, dmub_cmd_count);
3513 }
3514
3515 static void commit_planes_for_stream_fast(struct dc *dc,
3516                 struct dc_surface_update *srf_updates,
3517                 int surface_count,
3518                 struct dc_stream_state *stream,
3519                 struct dc_stream_update *stream_update,
3520                 enum surface_update_type update_type,
3521                 struct dc_state *context)
3522 {
3523         int i, j;
3524         struct pipe_ctx *top_pipe_to_program = NULL;
3525         dc_z10_restore(dc);
3526
3527         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3528                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3529
3530                 if (!pipe_ctx->top_pipe &&
3531                         !pipe_ctx->prev_odm_pipe &&
3532                         pipe_ctx->stream &&
3533                         pipe_ctx->stream == stream) {
3534                         top_pipe_to_program = pipe_ctx;
3535                 }
3536         }
3537
3538         if (dc->debug.visual_confirm) {
3539                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3540                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3541
3542                         if (pipe->stream && pipe->plane_state)
3543                                 dc_update_viusal_confirm_color(dc, context, pipe);
3544                 }
3545         }
3546
3547         for (i = 0; i < surface_count; i++) {
3548                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3549                 /*set logical flag for lock/unlock use*/
3550                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3551                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3552
3553                         if (!pipe_ctx->plane_state)
3554                                 continue;
3555                         if (should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3556                                 continue;
3557                         pipe_ctx->plane_state->triplebuffer_flips = false;
3558                         if (update_type == UPDATE_TYPE_FAST &&
3559                             dc->hwss.program_triplebuffer &&
3560                             !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {
3561                                 /*triple buffer for VUpdate  only*/
3562                                 pipe_ctx->plane_state->triplebuffer_flips = true;
3563                         }
3564                 }
3565         }
3566
3567         build_dmub_cmd_list(dc,
3568                         srf_updates,
3569                         surface_count,
3570                         stream,
3571                         context,
3572                         context->dc_dmub_cmd,
3573                         &(context->dmub_cmd_count));
3574         hwss_build_fast_sequence(dc,
3575                         context->dc_dmub_cmd,
3576                         context->dmub_cmd_count,
3577                         context->block_sequence,
3578                         &(context->block_sequence_steps),
3579                         top_pipe_to_program);
3580         hwss_execute_sequence(dc,
3581                         context->block_sequence,
3582                         context->block_sequence_steps);
3583         /* Clear update flags so next flip doesn't have redundant programming
3584          * (if there's no stream update, the update flags are not cleared).
3585          */
3586         if (top_pipe_to_program->plane_state)
3587                 top_pipe_to_program->plane_state->update_flags.raw = 0;
3588         if (top_pipe_to_program->stream)
3589                 top_pipe_to_program->stream->update_flags.raw = 0;
3590 }
3591
3592 static void commit_planes_for_stream(struct dc *dc,
3593                 struct dc_surface_update *srf_updates,
3594                 int surface_count,
3595                 struct dc_stream_state *stream,
3596                 struct dc_stream_update *stream_update,
3597                 enum surface_update_type update_type,
3598                 struct dc_state *context)
3599 {
3600         int i, j;
3601         struct pipe_ctx *top_pipe_to_program = NULL;
3602         bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST);
3603         bool subvp_prev_use = false;
3604         bool subvp_curr_use = false;
3605
3606         // Once we apply the new subvp context to hardware it won't be in the
3607         // dc->current_state anymore, so we have to cache it before we apply
3608         // the new SubVP context
3609         subvp_prev_use = false;
3610
3611
3612         dc_z10_restore(dc);
3613
3614         if (update_type == UPDATE_TYPE_FULL) {
3615                 /* wait for all double-buffer activity to clear on all pipes */
3616                 int pipe_idx;
3617
3618                 for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) {
3619                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
3620
3621                         if (!pipe_ctx->stream)
3622                                 continue;
3623
3624                         if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear)
3625                                 pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg);
3626                 }
3627         }
3628
3629         if (update_type == UPDATE_TYPE_FULL) {
3630                 dc_allow_idle_optimizations(dc, false);
3631
3632                 if (get_seamless_boot_stream_count(context) == 0)
3633                         dc->hwss.prepare_bandwidth(dc, context);
3634
3635                 if (dc->debug.enable_double_buffered_dsc_pg_support)
3636                         dc->hwss.update_dsc_pg(dc, context, false);
3637
3638                 context_clock_trace(dc, context);
3639         }
3640
3641         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3642                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3643
3644                 if (!pipe_ctx->top_pipe &&
3645                         !pipe_ctx->prev_odm_pipe &&
3646                         pipe_ctx->stream &&
3647                         pipe_ctx->stream == stream) {
3648                         top_pipe_to_program = pipe_ctx;
3649                 }
3650         }
3651
3652         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3653                 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3654
3655                 // Check old context for SubVP
3656                 subvp_prev_use |= (old_pipe->stream && old_pipe->stream->mall_stream_config.type == SUBVP_PHANTOM);
3657                 if (subvp_prev_use)
3658                         break;
3659         }
3660
3661         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3662                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3663
3664                 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
3665                         subvp_curr_use = true;
3666                         break;
3667                 }
3668         }
3669
3670         if (dc->debug.visual_confirm)
3671                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3672                         struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
3673
3674                         if (pipe->stream && pipe->plane_state)
3675                                 dc_update_viusal_confirm_color(dc, context, pipe);
3676                 }
3677
3678         if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
3679                 struct pipe_ctx *mpcc_pipe;
3680                 struct pipe_ctx *odm_pipe;
3681
3682                 for (mpcc_pipe = top_pipe_to_program; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
3683                         for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3684                                 odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
3685         }
3686
3687         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
3688                 if (top_pipe_to_program &&
3689                         top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
3690                         if (should_use_dmub_lock(stream->link)) {
3691                                 union dmub_hw_lock_flags hw_locks = { 0 };
3692                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
3693
3694                                 hw_locks.bits.lock_dig = 1;
3695                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
3696
3697                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
3698                                                         true,
3699                                                         &hw_locks,
3700                                                         &inst_flags);
3701                         } else
3702                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
3703                                                 top_pipe_to_program->stream_res.tg);
3704                 }
3705
3706         if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
3707                 if (dc->hwss.subvp_pipe_control_lock)
3708                                 dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, NULL, subvp_prev_use);
3709                 dc->hwss.interdependent_update_lock(dc, context, true);
3710
3711         } else {
3712                 if (dc->hwss.subvp_pipe_control_lock)
3713                         dc->hwss.subvp_pipe_control_lock(dc, context, true, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
3714                 /* Lock the top pipe while updating plane addrs, since freesync requires
3715                  *  plane addr update event triggers to be synchronized.
3716                  *  top_pipe_to_program is expected to never be NULL
3717                  */
3718                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
3719         }
3720
3721         dc_dmub_update_dirty_rect(dc, surface_count, stream, srf_updates, context);
3722
3723         // Stream updates
3724         if (stream_update)
3725                 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
3726
3727         if (surface_count == 0) {
3728                 /*
3729                  * In case of turning off screen, no need to program front end a second time.
3730                  * just return after program blank.
3731                  */
3732                 if (dc->hwss.apply_ctx_for_surface)
3733                         dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
3734                 if (dc->hwss.program_front_end_for_ctx)
3735                         dc->hwss.program_front_end_for_ctx(dc, context);
3736
3737                 if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
3738                         dc->hwss.interdependent_update_lock(dc, context, false);
3739                 } else {
3740                         dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
3741                 }
3742                 dc->hwss.post_unlock_program_front_end(dc, context);
3743
3744                 if (update_type != UPDATE_TYPE_FAST)
3745                         if (dc->hwss.commit_subvp_config)
3746                                 dc->hwss.commit_subvp_config(dc, context);
3747
3748                 /* Since phantom pipe programming is moved to post_unlock_program_front_end,
3749                  * move the SubVP lock to after the phantom pipes have been setup
3750                  */
3751                 if (dc->hwss.subvp_pipe_control_lock)
3752                         dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes,
3753                                                          NULL, subvp_prev_use);
3754                 return;
3755         }
3756
3757         if (update_type != UPDATE_TYPE_FAST) {
3758                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3759                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3760
3761                         if ((dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP ||
3762                                 dc->debug.visual_confirm == VISUAL_CONFIRM_MCLK_SWITCH) &&
3763                                 pipe_ctx->stream && pipe_ctx->plane_state) {
3764                                 /* Only update visual confirm for SUBVP and Mclk switching here.
3765                                  * The bar appears on all pipes, so we need to update the bar on all displays,
3766                                  * so the information doesn't get stale.
3767                                  */
3768                                 dc->hwss.update_visual_confirm_color(dc, pipe_ctx,
3769                                                 pipe_ctx->plane_res.hubp->inst);
3770                         }
3771                 }
3772         }
3773
3774         for (i = 0; i < surface_count; i++) {
3775                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3776                 /*set logical flag for lock/unlock use*/
3777                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3778                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3779                         if (!pipe_ctx->plane_state)
3780                                 continue;
3781                         if (should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3782                                 continue;
3783                         pipe_ctx->plane_state->triplebuffer_flips = false;
3784                         if (update_type == UPDATE_TYPE_FAST &&
3785                                 dc->hwss.program_triplebuffer != NULL &&
3786                                 !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {
3787                                         /*triple buffer for VUpdate  only*/
3788                                         pipe_ctx->plane_state->triplebuffer_flips = true;
3789                         }
3790                 }
3791                 if (update_type == UPDATE_TYPE_FULL) {
3792                         /* force vsync flip when reconfiguring pipes to prevent underflow */
3793                         plane_state->flip_immediate = false;
3794                 }
3795         }
3796
3797         // Update Type FULL, Surface updates
3798         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3799                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3800
3801                 if (!pipe_ctx->top_pipe &&
3802                         !pipe_ctx->prev_odm_pipe &&
3803                         should_update_pipe_for_stream(context, pipe_ctx, stream)) {
3804                         struct dc_stream_status *stream_status = NULL;
3805
3806                         if (!pipe_ctx->plane_state)
3807                                 continue;
3808
3809                         /* Full fe update*/
3810                         if (update_type == UPDATE_TYPE_FAST)
3811                                 continue;
3812
3813                         ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
3814
3815                         if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
3816                                 /*turn off triple buffer for full update*/
3817                                 dc->hwss.program_triplebuffer(
3818                                         dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
3819                         }
3820                         stream_status =
3821                                 stream_get_status(context, pipe_ctx->stream);
3822
3823                         if (dc->hwss.apply_ctx_for_surface)
3824                                 dc->hwss.apply_ctx_for_surface(
3825                                         dc, pipe_ctx->stream, stream_status->plane_count, context);
3826                 }
3827         }
3828         if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
3829                 dc->hwss.program_front_end_for_ctx(dc, context);
3830                 if (dc->debug.validate_dml_output) {
3831                         for (i = 0; i < dc->res_pool->pipe_count; i++) {
3832                                 struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i];
3833                                 if (cur_pipe->stream == NULL)
3834                                         continue;
3835
3836                                 cur_pipe->plane_res.hubp->funcs->validate_dml_output(
3837                                                 cur_pipe->plane_res.hubp, dc->ctx,
3838                                                 &context->res_ctx.pipe_ctx[i].rq_regs,
3839                                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
3840                                                 &context->res_ctx.pipe_ctx[i].ttu_regs);
3841                         }
3842                 }
3843         }
3844
3845         // Update Type FAST, Surface updates
3846         if (update_type == UPDATE_TYPE_FAST) {
3847                 if (dc->hwss.set_flip_control_gsl)
3848                         for (i = 0; i < surface_count; i++) {
3849                                 struct dc_plane_state *plane_state = srf_updates[i].surface;
3850
3851                                 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3852                                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3853
3854                                         if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
3855                                                 continue;
3856
3857                                         if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3858                                                 continue;
3859
3860                                         // GSL has to be used for flip immediate
3861                                         dc->hwss.set_flip_control_gsl(pipe_ctx,
3862                                                         pipe_ctx->plane_state->flip_immediate);
3863                                 }
3864                         }
3865
3866                 /* Perform requested Updates */
3867                 for (i = 0; i < surface_count; i++) {
3868                         struct dc_plane_state *plane_state = srf_updates[i].surface;
3869
3870                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3871                                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3872
3873                                 if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
3874                                         continue;
3875
3876                                 if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
3877                                         continue;
3878
3879                                 /*program triple buffer after lock based on flip type*/
3880                                 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
3881                                         /*only enable triplebuffer for  fast_update*/
3882                                         dc->hwss.program_triplebuffer(
3883                                                 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
3884                                 }
3885                                 if (pipe_ctx->plane_state->update_flags.bits.addr_update)
3886                                         dc->hwss.update_plane_addr(dc, pipe_ctx);
3887                         }
3888                 }
3889         }
3890
3891         if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
3892                 dc->hwss.interdependent_update_lock(dc, context, false);
3893         } else {
3894                 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
3895         }
3896
3897         if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
3898                 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
3899                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
3900                                 top_pipe_to_program->stream_res.tg,
3901                                 CRTC_STATE_VACTIVE);
3902                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
3903                                 top_pipe_to_program->stream_res.tg,
3904                                 CRTC_STATE_VBLANK);
3905                         top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
3906                                 top_pipe_to_program->stream_res.tg,
3907                                 CRTC_STATE_VACTIVE);
3908
3909                         if (should_use_dmub_lock(stream->link)) {
3910                                 union dmub_hw_lock_flags hw_locks = { 0 };
3911                                 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
3912
3913                                 hw_locks.bits.lock_dig = 1;
3914                                 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
3915
3916                                 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
3917                                                         false,
3918                                                         &hw_locks,
3919                                                         &inst_flags);
3920                         } else
3921                                 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
3922                                         top_pipe_to_program->stream_res.tg);
3923                 }
3924
3925         if (subvp_curr_use) {
3926                 /* If enabling subvp or transitioning from subvp->subvp, enable the
3927                  * phantom streams before we program front end for the phantom pipes.
3928                  */
3929                 if (update_type != UPDATE_TYPE_FAST) {
3930                         if (dc->hwss.enable_phantom_streams)
3931                                 dc->hwss.enable_phantom_streams(dc, context);
3932                 }
3933         }
3934
3935         if (update_type != UPDATE_TYPE_FAST)
3936                 dc->hwss.post_unlock_program_front_end(dc, context);
3937
3938         if (subvp_prev_use && !subvp_curr_use) {
3939                 /* If disabling subvp, disable phantom streams after front end
3940                  * programming has completed (we turn on phantom OTG in order
3941                  * to complete the plane disable for phantom pipes).
3942                  */
3943                 dc->hwss.apply_ctx_to_hw(dc, context);
3944         }
3945
3946         if (update_type != UPDATE_TYPE_FAST)
3947                 if (dc->hwss.commit_subvp_config)
3948                         dc->hwss.commit_subvp_config(dc, context);
3949         /* Since phantom pipe programming is moved to post_unlock_program_front_end,
3950          * move the SubVP lock to after the phantom pipes have been setup
3951          */
3952         if (should_lock_all_pipes && dc->hwss.interdependent_update_lock) {
3953                 if (dc->hwss.subvp_pipe_control_lock)
3954                         dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, NULL, subvp_prev_use);
3955         } else {
3956                 if (dc->hwss.subvp_pipe_control_lock)
3957                         dc->hwss.subvp_pipe_control_lock(dc, context, false, should_lock_all_pipes, top_pipe_to_program, subvp_prev_use);
3958         }
3959
3960         // Fire manual trigger only when bottom plane is flipped
3961         for (j = 0; j < dc->res_pool->pipe_count; j++) {
3962                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3963
3964                 if (!pipe_ctx->plane_state)
3965                         continue;
3966
3967                 if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
3968                                 !pipe_ctx->stream || !should_update_pipe_for_stream(context, pipe_ctx, stream) ||
3969                                 !pipe_ctx->plane_state->update_flags.bits.addr_update ||
3970                                 pipe_ctx->plane_state->skip_manual_trigger)
3971                         continue;
3972
3973                 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
3974                         pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
3975         }
3976 }
3977
3978 /**
3979  * could_mpcc_tree_change_for_active_pipes - Check if an OPP associated with MPCC might change
3980  *
3981  * @dc: Used to get the current state status
3982  * @stream: Target stream, which we want to remove the attached planes
3983  * @surface_count: Number of surface update
3984  * @is_plane_addition: [in] Fill out with true if it is a plane addition case
3985  *
3986  * DCN32x and newer support a feature named Dynamic ODM which can conflict with
3987  * the MPO if used simultaneously in some specific configurations (e.g.,
3988  * 4k@144). This function checks if the incoming context requires applying a
3989  * transition state with unnecessary pipe splitting and ODM disabled to
3990  * circumvent our hardware limitations to prevent this edge case. If the OPP
3991  * associated with an MPCC might change due to plane additions, this function
3992  * returns true.
3993  *
3994  * Return:
3995  * Return true if OPP and MPCC might change, otherwise, return false.
3996  */
3997 static bool could_mpcc_tree_change_for_active_pipes(struct dc *dc,
3998                 struct dc_stream_state *stream,
3999                 int surface_count,
4000                 bool *is_plane_addition)
4001 {
4002
4003         struct dc_stream_status *cur_stream_status = stream_get_status(dc->current_state, stream);
4004         bool force_minimal_pipe_splitting = false;
4005         bool subvp_active = false;
4006         uint32_t i;
4007
4008         *is_plane_addition = false;
4009
4010         if (cur_stream_status &&
4011                         dc->current_state->stream_count > 0 &&
4012                         dc->debug.pipe_split_policy != MPC_SPLIT_AVOID) {
4013                 /* determine if minimal transition is required due to MPC*/
4014                 if (surface_count > 0) {
4015                         if (cur_stream_status->plane_count > surface_count) {
4016                                 force_minimal_pipe_splitting = true;
4017                         } else if (cur_stream_status->plane_count < surface_count) {
4018                                 force_minimal_pipe_splitting = true;
4019                                 *is_plane_addition = true;
4020                         }
4021                 }
4022         }
4023
4024         if (cur_stream_status &&
4025                         dc->current_state->stream_count == 1 &&
4026                         dc->debug.enable_single_display_2to1_odm_policy) {
4027                 /* determine if minimal transition is required due to dynamic ODM*/
4028                 if (surface_count > 0) {
4029                         if (cur_stream_status->plane_count > 2 && cur_stream_status->plane_count > surface_count) {
4030                                 force_minimal_pipe_splitting = true;
4031                         } else if (surface_count > 2 && cur_stream_status->plane_count < surface_count) {
4032                                 force_minimal_pipe_splitting = true;
4033                                 *is_plane_addition = true;
4034                         }
4035                 }
4036         }
4037
4038         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4039                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4040
4041                 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE) {
4042                         subvp_active = true;
4043                         break;
4044                 }
4045         }
4046
4047         /* For SubVP when adding or removing planes we need to add a minimal transition
4048          * (even when disabling all planes). Whenever disabling a phantom pipe, we
4049          * must use the minimal transition path to disable the pipe correctly.
4050          *
4051          * We want to use the minimal transition whenever subvp is active, not only if
4052          * a plane is being added / removed from a subvp stream (MPO plane can be added
4053          * to a DRR pipe of SubVP + DRR config, in which case we still want to run through
4054          * a min transition to disable subvp.
4055          */
4056         if (cur_stream_status && subvp_active) {
4057                 /* determine if minimal transition is required due to SubVP*/
4058                 if (cur_stream_status->plane_count > surface_count) {
4059                         force_minimal_pipe_splitting = true;
4060                 } else if (cur_stream_status->plane_count < surface_count) {
4061                         force_minimal_pipe_splitting = true;
4062                         *is_plane_addition = true;
4063                 }
4064         }
4065
4066         return force_minimal_pipe_splitting;
4067 }
4068
4069 /**
4070  * commit_minimal_transition_state - Create a transition pipe split state
4071  *
4072  * @dc: Used to get the current state status
4073  * @transition_base_context: New transition state
4074  *
4075  * In some specific configurations, such as pipe split on multi-display with
4076  * MPO and/or Dynamic ODM, removing a plane may cause unsupported pipe
4077  * programming when moving to new planes. To mitigate those types of problems,
4078  * this function adds a transition state that minimizes pipe usage before
4079  * programming the new configuration. When adding a new plane, the current
4080  * state requires the least pipes, so it is applied without splitting. When
4081  * removing a plane, the new state requires the least pipes, so it is applied
4082  * without splitting.
4083  *
4084  * Return:
4085  * Return false if something is wrong in the transition state.
4086  */
4087 static bool commit_minimal_transition_state(struct dc *dc,
4088                 struct dc_state *transition_base_context)
4089 {
4090         struct dc_state *transition_context = dc_create_state(dc);
4091         enum pipe_split_policy tmp_mpc_policy;
4092         bool temp_dynamic_odm_policy;
4093         bool temp_subvp_policy;
4094         enum dc_status ret = DC_ERROR_UNEXPECTED;
4095         unsigned int i, j;
4096         unsigned int pipe_in_use = 0;
4097         bool subvp_in_use = false;
4098         bool odm_in_use = false;
4099
4100         if (!transition_context)
4101                 return false;
4102         /* Setup:
4103          * Store the current ODM and MPC config in some temp variables to be
4104          * restored after we commit the transition state.
4105          */
4106
4107         /* check current pipes in use*/
4108         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4109                 struct pipe_ctx *pipe = &transition_base_context->res_ctx.pipe_ctx[i];
4110
4111                 if (pipe->plane_state)
4112                         pipe_in_use++;
4113         }
4114
4115         /* If SubVP is enabled and we are adding or removing planes from any main subvp
4116          * pipe, we must use the minimal transition.
4117          */
4118         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4119                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4120
4121                 if (pipe->stream && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) {
4122                         subvp_in_use = true;
4123                         break;
4124                 }
4125         }
4126
4127         /* If ODM is enabled and we are adding or removing planes from any ODM
4128          * pipe, we must use the minimal transition.
4129          */
4130         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4131                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4132
4133                 if (pipe->stream && pipe->next_odm_pipe) {
4134                         odm_in_use = true;
4135                         break;
4136                 }
4137         }
4138
4139         /* When the OS add a new surface if we have been used all of pipes with odm combine
4140          * and mpc split feature, it need use commit_minimal_transition_state to transition safely.
4141          * After OS exit MPO, it will back to use odm and mpc split with all of pipes, we need
4142          * call it again. Otherwise return true to skip.
4143          *
4144          * Reduce the scenarios to use dc_commit_state_no_check in the stage of flip. Especially
4145          * enter/exit MPO when DCN still have enough resources.
4146          */
4147         if (pipe_in_use != dc->res_pool->pipe_count && !subvp_in_use && !odm_in_use) {
4148                 dc_release_state(transition_context);
4149                 return true;
4150         }
4151
4152         if (!dc->config.is_vmin_only_asic) {
4153                 tmp_mpc_policy = dc->debug.pipe_split_policy;
4154                 dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
4155         }
4156
4157         temp_dynamic_odm_policy = dc->debug.enable_single_display_2to1_odm_policy;
4158         dc->debug.enable_single_display_2to1_odm_policy = false;
4159
4160         temp_subvp_policy = dc->debug.force_disable_subvp;
4161         dc->debug.force_disable_subvp = true;
4162
4163         dc_resource_state_copy_construct(transition_base_context, transition_context);
4164
4165         /* commit minimal state */
4166         if (dc->res_pool->funcs->validate_bandwidth(dc, transition_context, false)) {
4167                 for (i = 0; i < transition_context->stream_count; i++) {
4168                         struct dc_stream_status *stream_status = &transition_context->stream_status[i];
4169
4170                         for (j = 0; j < stream_status->plane_count; j++) {
4171                                 struct dc_plane_state *plane_state = stream_status->plane_states[j];
4172
4173                                 /* force vsync flip when reconfiguring pipes to prevent underflow
4174                                  * and corruption
4175                                  */
4176                                 plane_state->flip_immediate = false;
4177                         }
4178                 }
4179
4180                 ret = dc_commit_state_no_check(dc, transition_context);
4181         }
4182
4183         /* always release as dc_commit_state_no_check retains in good case */
4184         dc_release_state(transition_context);
4185
4186         /* TearDown:
4187          * Restore original configuration for ODM and MPO.
4188          */
4189         if (!dc->config.is_vmin_only_asic)
4190                 dc->debug.pipe_split_policy = tmp_mpc_policy;
4191
4192         dc->debug.enable_single_display_2to1_odm_policy = temp_dynamic_odm_policy;
4193         dc->debug.force_disable_subvp = temp_subvp_policy;
4194
4195         if (ret != DC_OK) {
4196                 /* this should never happen */
4197                 BREAK_TO_DEBUGGER();
4198                 return false;
4199         }
4200
4201         /* force full surface update */
4202         for (i = 0; i < dc->current_state->stream_count; i++) {
4203                 for (j = 0; j < dc->current_state->stream_status[i].plane_count; j++) {
4204                         dc->current_state->stream_status[i].plane_states[j]->update_flags.raw = 0xFFFFFFFF;
4205                 }
4206         }
4207
4208         return true;
4209 }
4210
4211 /**
4212  * update_seamless_boot_flags() - Helper function for updating seamless boot flags
4213  *
4214  * @dc: Current DC state
4215  * @context: New DC state to be programmed
4216  * @surface_count: Number of surfaces that have an updated
4217  * @stream: Corresponding stream to be updated in the current flip
4218  *
4219  * Updating seamless boot flags do not need to be part of the commit sequence. This
4220  * helper function will update the seamless boot flags on each flip (if required)
4221  * outside of the HW commit sequence (fast or slow).
4222  *
4223  * Return: void
4224  */
4225 static void update_seamless_boot_flags(struct dc *dc,
4226                 struct dc_state *context,
4227                 int surface_count,
4228                 struct dc_stream_state *stream)
4229 {
4230         if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
4231                 /* Optimize seamless boot flag keeps clocks and watermarks high until
4232                  * first flip. After first flip, optimization is required to lower
4233                  * bandwidth. Important to note that it is expected UEFI will
4234                  * only light up a single display on POST, therefore we only expect
4235                  * one stream with seamless boot flag set.
4236                  */
4237                 if (stream->apply_seamless_boot_optimization) {
4238                         stream->apply_seamless_boot_optimization = false;
4239
4240                         if (get_seamless_boot_stream_count(context) == 0)
4241                                 dc->optimized_required = true;
4242                 }
4243         }
4244 }
4245
4246 static void populate_fast_updates(struct dc_fast_update *fast_update,
4247                 struct dc_surface_update *srf_updates,
4248                 int surface_count,
4249                 struct dc_stream_update *stream_update)
4250 {
4251         int i = 0;
4252
4253         if (stream_update) {
4254                 fast_update[0].out_transfer_func = stream_update->out_transfer_func;
4255                 fast_update[0].output_csc_transform = stream_update->output_csc_transform;
4256         }
4257
4258         for (i = 0; i < surface_count; i++) {
4259                 fast_update[i].flip_addr = srf_updates[i].flip_addr;
4260                 fast_update[i].gamma = srf_updates[i].gamma;
4261                 fast_update[i].gamut_remap_matrix = srf_updates[i].gamut_remap_matrix;
4262                 fast_update[i].input_csc_color_matrix = srf_updates[i].input_csc_color_matrix;
4263                 fast_update[i].coeff_reduction_factor = srf_updates[i].coeff_reduction_factor;
4264         }
4265 }
4266
4267 static bool fast_updates_exist(struct dc_fast_update *fast_update, int surface_count)
4268 {
4269         int i;
4270
4271         if (fast_update[0].out_transfer_func ||
4272                 fast_update[0].output_csc_transform)
4273                 return true;
4274
4275         for (i = 0; i < surface_count; i++) {
4276                 if (fast_update[i].flip_addr ||
4277                                 fast_update[i].gamma ||
4278                                 fast_update[i].gamut_remap_matrix ||
4279                                 fast_update[i].input_csc_color_matrix ||
4280                                 fast_update[i].coeff_reduction_factor)
4281                         return true;
4282         }
4283
4284         return false;
4285 }
4286
4287 static bool full_update_required(struct dc_surface_update *srf_updates,
4288                 int surface_count,
4289                 struct dc_stream_update *stream_update,
4290                 struct dc_stream_state *stream)
4291 {
4292
4293         int i;
4294         struct dc_stream_status *stream_status;
4295
4296         for (i = 0; i < surface_count; i++) {
4297                 if (srf_updates &&
4298                                 (srf_updates[i].plane_info ||
4299                                 srf_updates[i].scaling_info ||
4300                                 (srf_updates[i].hdr_mult.value &&
4301                                 srf_updates[i].hdr_mult.value != srf_updates->surface->hdr_mult.value) ||
4302                                 srf_updates[i].in_transfer_func ||
4303                                 srf_updates[i].func_shaper ||
4304                                 srf_updates[i].lut3d_func ||
4305                                 srf_updates[i].blend_tf))
4306                         return true;
4307         }
4308
4309         if (stream_update &&
4310                         (((stream_update->src.height != 0 && stream_update->src.width != 0) ||
4311                         (stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
4312                         stream_update->integer_scaling_update) ||
4313                         stream_update->hdr_static_metadata ||
4314                         stream_update->abm_level ||
4315                         stream_update->periodic_interrupt ||
4316                         stream_update->vrr_infopacket ||
4317                         stream_update->vsc_infopacket ||
4318                         stream_update->vsp_infopacket ||
4319                         stream_update->hfvsif_infopacket ||
4320                         stream_update->vtem_infopacket ||
4321                         stream_update->adaptive_sync_infopacket ||
4322                         stream_update->dpms_off ||
4323                         stream_update->allow_freesync ||
4324                         stream_update->vrr_active_variable ||
4325                         stream_update->vrr_active_fixed ||
4326                         stream_update->gamut_remap ||
4327                         stream_update->output_color_space ||
4328                         stream_update->dither_option ||
4329                         stream_update->wb_update ||
4330                         stream_update->dsc_config ||
4331                         stream_update->mst_bw_update ||
4332                         stream_update->func_shaper ||
4333                         stream_update->lut3d_func ||
4334                         stream_update->pending_test_pattern ||
4335                         stream_update->crtc_timing_adjust))
4336                 return true;
4337
4338         if (stream) {
4339                 stream_status = dc_stream_get_status(stream);
4340                 if (stream_status == NULL || stream_status->plane_count != surface_count)
4341                         return true;
4342         }
4343
4344         return false;
4345 }
4346
4347 static bool fast_update_only(struct dc_fast_update *fast_update,
4348                 struct dc_surface_update *srf_updates,
4349                 int surface_count,
4350                 struct dc_stream_update *stream_update,
4351                 struct dc_stream_state *stream)
4352 {
4353         return fast_updates_exist(fast_update, surface_count)
4354                         && !full_update_required(srf_updates, surface_count, stream_update, stream);
4355 }
4356
4357 bool dc_update_planes_and_stream(struct dc *dc,
4358                 struct dc_surface_update *srf_updates, int surface_count,
4359                 struct dc_stream_state *stream,
4360                 struct dc_stream_update *stream_update)
4361 {
4362         struct dc_state *context;
4363         enum surface_update_type update_type;
4364         int i;
4365         struct mall_temp_config mall_temp_config;
4366         struct dc_fast_update fast_update[MAX_SURFACES] = {0};
4367
4368         /* In cases where MPO and split or ODM are used transitions can
4369          * cause underflow. Apply stream configuration with minimal pipe
4370          * split first to avoid unsupported transitions for active pipes.
4371          */
4372         bool force_minimal_pipe_splitting;
4373         bool is_plane_addition;
4374
4375         populate_fast_updates(fast_update, srf_updates, surface_count, stream_update);
4376         force_minimal_pipe_splitting = could_mpcc_tree_change_for_active_pipes(
4377                         dc,
4378                         stream,
4379                         surface_count,
4380                         &is_plane_addition);
4381
4382         /* on plane addition, minimal state is the current one */
4383         if (force_minimal_pipe_splitting && is_plane_addition &&
4384                 !commit_minimal_transition_state(dc, dc->current_state))
4385                                 return false;
4386
4387         if (!update_planes_and_stream_state(
4388                         dc,
4389                         srf_updates,
4390                         surface_count,
4391                         stream,
4392                         stream_update,
4393                         &update_type,
4394                         &context))
4395                 return false;
4396
4397         /* on plane removal, minimal state is the new one */
4398         if (force_minimal_pipe_splitting && !is_plane_addition) {
4399                 /* Since all phantom pipes are removed in full validation,
4400                  * we have to save and restore the subvp/mall config when
4401                  * we do a minimal transition since the flags marking the
4402                  * pipe as subvp/phantom will be cleared (dc copy constructor
4403                  * creates a shallow copy).
4404                  */
4405                 if (dc->res_pool->funcs->save_mall_state)
4406                         dc->res_pool->funcs->save_mall_state(dc, context, &mall_temp_config);
4407                 if (!commit_minimal_transition_state(dc, context)) {
4408                         dc_release_state(context);
4409                         return false;
4410                 }
4411                 if (dc->res_pool->funcs->restore_mall_state)
4412                         dc->res_pool->funcs->restore_mall_state(dc, context, &mall_temp_config);
4413
4414                 /* If we do a minimal transition with plane removal and the context
4415                  * has subvp we also have to retain back the phantom stream / planes
4416                  * since the refcount is decremented as part of the min transition
4417                  * (we commit a state with no subvp, so the phantom streams / planes
4418                  * had to be removed).
4419                  */
4420                 if (dc->res_pool->funcs->retain_phantom_pipes)
4421                         dc->res_pool->funcs->retain_phantom_pipes(dc, context);
4422                 update_type = UPDATE_TYPE_FULL;
4423         }
4424
4425         update_seamless_boot_flags(dc, context, surface_count, stream);
4426         if (fast_update_only(fast_update, srf_updates, surface_count, stream_update, stream) &&
4427                         !dc->debug.enable_legacy_fast_update) {
4428                 commit_planes_for_stream_fast(dc,
4429                                 srf_updates,
4430                                 surface_count,
4431                                 stream,
4432                                 stream_update,
4433                                 update_type,
4434                                 context);
4435         } else {
4436                 commit_planes_for_stream(
4437                                 dc,
4438                                 srf_updates,
4439                                 surface_count,
4440                                 stream,
4441                                 stream_update,
4442                                 update_type,
4443                                 context);
4444         }
4445
4446         if (dc->current_state != context) {
4447
4448                 /* Since memory free requires elevated IRQL, an interrupt
4449                  * request is generated by mem free. If this happens
4450                  * between freeing and reassigning the context, our vsync
4451                  * interrupt will call into dc and cause a memory
4452                  * corruption BSOD. Hence, we first reassign the context,
4453                  * then free the old context.
4454                  */
4455
4456                 struct dc_state *old = dc->current_state;
4457
4458                 dc->current_state = context;
4459                 dc_release_state(old);
4460
4461                 // clear any forced full updates
4462                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4463                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4464
4465                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
4466                                 pipe_ctx->plane_state->force_full_update = false;
4467                 }
4468         }
4469         return true;
4470 }
4471
4472 void dc_commit_updates_for_stream(struct dc *dc,
4473                 struct dc_surface_update *srf_updates,
4474                 int surface_count,
4475                 struct dc_stream_state *stream,
4476                 struct dc_stream_update *stream_update,
4477                 struct dc_state *state)
4478 {
4479         const struct dc_stream_status *stream_status;
4480         enum surface_update_type update_type;
4481         struct dc_state *context;
4482         struct dc_context *dc_ctx = dc->ctx;
4483         int i, j;
4484         struct dc_fast_update fast_update[MAX_SURFACES] = {0};
4485
4486         populate_fast_updates(fast_update, srf_updates, surface_count, stream_update);
4487         stream_status = dc_stream_get_status(stream);
4488         context = dc->current_state;
4489
4490         update_type = dc_check_update_surfaces_for_stream(
4491                                 dc, srf_updates, surface_count, stream_update, stream_status);
4492
4493         /* TODO: Since change commit sequence can have a huge impact,
4494          * we decided to only enable it for DCN3x. However, as soon as
4495          * we get more confident about this change we'll need to enable
4496          * the new sequence for all ASICs.
4497          */
4498         if (dc->ctx->dce_version >= DCN_VERSION_3_2) {
4499                 /*
4500                  * Previous frame finished and HW is ready for optimization.
4501                  */
4502                 if (update_type == UPDATE_TYPE_FAST)
4503                         dc_post_update_surfaces_to_stream(dc);
4504
4505                 dc_update_planes_and_stream(dc, srf_updates,
4506                                             surface_count, stream,
4507                                             stream_update);
4508                 return;
4509         }
4510
4511         if (update_type >= update_surface_trace_level)
4512                 update_surface_trace(dc, srf_updates, surface_count);
4513
4514
4515         if (update_type >= UPDATE_TYPE_FULL) {
4516
4517                 /* initialize scratch memory for building context */
4518                 context = dc_create_state(dc);
4519                 if (context == NULL) {
4520                         DC_ERROR("Failed to allocate new validate context!\n");
4521                         return;
4522                 }
4523
4524                 dc_resource_state_copy_construct(state, context);
4525
4526                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4527                         struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
4528                         struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4529
4530                         if (new_pipe->plane_state && new_pipe->plane_state != old_pipe->plane_state)
4531                                 new_pipe->plane_state->force_full_update = true;
4532                 }
4533         } else if (update_type == UPDATE_TYPE_FAST) {
4534                 /*
4535                  * Previous frame finished and HW is ready for optimization.
4536                  */
4537                 dc_post_update_surfaces_to_stream(dc);
4538         }
4539
4540
4541         for (i = 0; i < surface_count; i++) {
4542                 struct dc_plane_state *surface = srf_updates[i].surface;
4543
4544                 copy_surface_update_to_plane(surface, &srf_updates[i]);
4545
4546                 if (update_type >= UPDATE_TYPE_MED) {
4547                         for (j = 0; j < dc->res_pool->pipe_count; j++) {
4548                                 struct pipe_ctx *pipe_ctx =
4549                                         &context->res_ctx.pipe_ctx[j];
4550
4551                                 if (pipe_ctx->plane_state != surface)
4552                                         continue;
4553
4554                                 resource_build_scaling_params(pipe_ctx);
4555                         }
4556                 }
4557         }
4558
4559         copy_stream_update_to_stream(dc, context, stream, stream_update);
4560
4561         if (update_type >= UPDATE_TYPE_FULL) {
4562                 if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
4563                         DC_ERROR("Mode validation failed for stream update!\n");
4564                         dc_release_state(context);
4565                         return;
4566                 }
4567         }
4568
4569         TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);
4570
4571         update_seamless_boot_flags(dc, context, surface_count, stream);
4572         if (fast_update_only(fast_update, srf_updates, surface_count, stream_update, stream) &&
4573                         !dc->debug.enable_legacy_fast_update) {
4574                 commit_planes_for_stream_fast(dc,
4575                                 srf_updates,
4576                                 surface_count,
4577                                 stream,
4578                                 stream_update,
4579                                 update_type,
4580                                 context);
4581         } else {
4582                 commit_planes_for_stream(
4583                                 dc,
4584                                 srf_updates,
4585                                 surface_count,
4586                                 stream,
4587                                 stream_update,
4588                                 update_type,
4589                                 context);
4590         }
4591         /*update current_State*/
4592         if (dc->current_state != context) {
4593
4594                 struct dc_state *old = dc->current_state;
4595
4596                 dc->current_state = context;
4597                 dc_release_state(old);
4598
4599                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
4600                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
4601
4602                         if (pipe_ctx->plane_state && pipe_ctx->stream == stream)
4603                                 pipe_ctx->plane_state->force_full_update = false;
4604                 }
4605         }
4606
4607         /* Legacy optimization path for DCE. */
4608         if (update_type >= UPDATE_TYPE_FULL && dc_ctx->dce_version < DCE_VERSION_MAX) {
4609                 dc_post_update_surfaces_to_stream(dc);
4610                 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce);
4611         }
4612
4613         return;
4614
4615 }
4616
4617 uint8_t dc_get_current_stream_count(struct dc *dc)
4618 {
4619         return dc->current_state->stream_count;
4620 }
4621
4622 struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i)
4623 {
4624         if (i < dc->current_state->stream_count)
4625                 return dc->current_state->streams[i];
4626         return NULL;
4627 }
4628
4629 enum dc_irq_source dc_interrupt_to_irq_source(
4630                 struct dc *dc,
4631                 uint32_t src_id,
4632                 uint32_t ext_id)
4633 {
4634         return dal_irq_service_to_irq_source(dc->res_pool->irqs, src_id, ext_id);
4635 }
4636
4637 /*
4638  * dc_interrupt_set() - Enable/disable an AMD hw interrupt source
4639  */
4640 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable)
4641 {
4642
4643         if (dc == NULL)
4644                 return false;
4645
4646         return dal_irq_service_set(dc->res_pool->irqs, src, enable);
4647 }
4648
4649 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
4650 {
4651         dal_irq_service_ack(dc->res_pool->irqs, src);
4652 }
4653
4654 void dc_power_down_on_boot(struct dc *dc)
4655 {
4656         if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW &&
4657                         dc->hwss.power_down_on_boot)
4658                 dc->hwss.power_down_on_boot(dc);
4659 }
4660
4661 void dc_set_power_state(
4662         struct dc *dc,
4663         enum dc_acpi_cm_power_state power_state)
4664 {
4665         struct kref refcount;
4666         struct display_mode_lib *dml;
4667
4668         if (!dc->current_state)
4669                 return;
4670
4671         switch (power_state) {
4672         case DC_ACPI_CM_POWER_STATE_D0:
4673                 dc_resource_state_construct(dc, dc->current_state);
4674
4675                 dc_z10_restore(dc);
4676
4677                 dc->hwss.init_hw(dc);
4678
4679                 if (dc->hwss.init_sys_ctx != NULL &&
4680                         dc->vm_pa_config.valid) {
4681                         dc->hwss.init_sys_ctx(dc->hwseq, dc, &dc->vm_pa_config);
4682                 }
4683
4684                 break;
4685         default:
4686                 ASSERT(dc->current_state->stream_count == 0);
4687                 /* Zero out the current context so that on resume we start with
4688                  * clean state, and dc hw programming optimizations will not
4689                  * cause any trouble.
4690                  */
4691                 dml = kzalloc(sizeof(struct display_mode_lib),
4692                                 GFP_KERNEL);
4693
4694                 ASSERT(dml);
4695                 if (!dml)
4696                         return;
4697
4698                 /* Preserve refcount */
4699                 refcount = dc->current_state->refcount;
4700                 /* Preserve display mode lib */
4701                 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
4702
4703                 dc_resource_state_destruct(dc->current_state);
4704                 memset(dc->current_state, 0,
4705                                 sizeof(*dc->current_state));
4706
4707                 dc->current_state->refcount = refcount;
4708                 dc->current_state->bw_ctx.dml = *dml;
4709
4710                 kfree(dml);
4711
4712                 break;
4713         }
4714 }
4715
4716 void dc_resume(struct dc *dc)
4717 {
4718         uint32_t i;
4719
4720         for (i = 0; i < dc->link_count; i++)
4721                 dc->link_srv->resume(dc->links[i]);
4722 }
4723
4724 bool dc_is_dmcu_initialized(struct dc *dc)
4725 {
4726         struct dmcu *dmcu = dc->res_pool->dmcu;
4727
4728         if (dmcu)
4729                 return dmcu->funcs->is_dmcu_initialized(dmcu);
4730         return false;
4731 }
4732
4733 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info)
4734 {
4735         info->displayClock                              = (unsigned int)state->bw_ctx.bw.dcn.clk.dispclk_khz;
4736         info->engineClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz;
4737         info->memoryClock                               = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz;
4738         info->maxSupportedDppClock              = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
4739         info->dppClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
4740         info->socClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz;
4741         info->dcfClockDeepSleep                 = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz;
4742         info->fClock                                    = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz;
4743         info->phyClock                                  = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz;
4744 }
4745 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping)
4746 {
4747         if (dc->hwss.set_clock)
4748                 return dc->hwss.set_clock(dc, clock_type, clk_khz, stepping);
4749         return DC_ERROR_UNEXPECTED;
4750 }
4751 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
4752 {
4753         if (dc->hwss.get_clock)
4754                 dc->hwss.get_clock(dc, clock_type, clock_cfg);
4755 }
4756
4757 /* enable/disable eDP PSR without specify stream for eDP */
4758 bool dc_set_psr_allow_active(struct dc *dc, bool enable)
4759 {
4760         int i;
4761         bool allow_active;
4762
4763         for (i = 0; i < dc->current_state->stream_count ; i++) {
4764                 struct dc_link *link;
4765                 struct dc_stream_state *stream = dc->current_state->streams[i];
4766
4767                 link = stream->link;
4768                 if (!link)
4769                         continue;
4770
4771                 if (link->psr_settings.psr_feature_enabled) {
4772                         if (enable && !link->psr_settings.psr_allow_active) {
4773                                 allow_active = true;
4774                                 if (!dc_link_set_psr_allow_active(link, &allow_active, false, false, NULL))
4775                                         return false;
4776                         } else if (!enable && link->psr_settings.psr_allow_active) {
4777                                 allow_active = false;
4778                                 if (!dc_link_set_psr_allow_active(link, &allow_active, true, false, NULL))
4779                                         return false;
4780                         }
4781                 }
4782         }
4783
4784         return true;
4785 }
4786
4787 void dc_allow_idle_optimizations(struct dc *dc, bool allow)
4788 {
4789         if (dc->debug.disable_idle_power_optimizations)
4790                 return;
4791
4792         if (dc->clk_mgr != NULL && dc->clk_mgr->funcs->is_smu_present)
4793                 if (!dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr))
4794                         return;
4795
4796         if (allow == dc->idle_optimizations_allowed)
4797                 return;
4798
4799         if (dc->hwss.apply_idle_power_optimizations && dc->hwss.apply_idle_power_optimizations(dc, allow))
4800                 dc->idle_optimizations_allowed = allow;
4801 }
4802
4803 /* set min and max memory clock to lowest and highest DPM level, respectively */
4804 void dc_unlock_memory_clock_frequency(struct dc *dc)
4805 {
4806         if (dc->clk_mgr->funcs->set_hard_min_memclk)
4807                 dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, false);
4808
4809         if (dc->clk_mgr->funcs->set_hard_max_memclk)
4810                 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
4811 }
4812
4813 /* set min memory clock to the min required for current mode, max to maxDPM */
4814 void dc_lock_memory_clock_frequency(struct dc *dc)
4815 {
4816         if (dc->clk_mgr->funcs->get_memclk_states_from_smu)
4817                 dc->clk_mgr->funcs->get_memclk_states_from_smu(dc->clk_mgr);
4818
4819         if (dc->clk_mgr->funcs->set_hard_min_memclk)
4820                 dc->clk_mgr->funcs->set_hard_min_memclk(dc->clk_mgr, true);
4821
4822         if (dc->clk_mgr->funcs->set_hard_max_memclk)
4823                 dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
4824 }
4825
4826 static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz)
4827 {
4828         struct dc_state *context = dc->current_state;
4829         struct hubp *hubp;
4830         struct pipe_ctx *pipe;
4831         int i;
4832
4833         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4834                 pipe = &context->res_ctx.pipe_ctx[i];
4835
4836                 if (pipe->stream != NULL) {
4837                         dc->hwss.disable_pixel_data(dc, pipe, true);
4838
4839                         // wait for double buffer
4840                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);
4841                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK);
4842                         pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VACTIVE);
4843
4844                         hubp = pipe->plane_res.hubp;
4845                         hubp->funcs->set_blank_regs(hubp, true);
4846                 }
4847         }
4848
4849         dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, memclk_mhz);
4850         dc->clk_mgr->funcs->set_min_memclk(dc->clk_mgr, memclk_mhz);
4851
4852         for (i = 0; i < dc->res_pool->pipe_count; i++) {
4853                 pipe = &context->res_ctx.pipe_ctx[i];
4854
4855                 if (pipe->stream != NULL) {
4856                         dc->hwss.disable_pixel_data(dc, pipe, false);
4857
4858                         hubp = pipe->plane_res.hubp;
4859                         hubp->funcs->set_blank_regs(hubp, false);
4860                 }
4861         }
4862 }
4863
4864
4865 /**
4866  * dc_enable_dcmode_clk_limit() - lower clocks in dc (battery) mode
4867  * @dc: pointer to dc of the dm calling this
4868  * @enable: True = transition to DC mode, false = transition back to AC mode
4869  *
4870  * Some SoCs define additional clock limits when in DC mode, DM should
4871  * invoke this function when the platform undergoes a power source transition
4872  * so DC can apply/unapply the limit. This interface may be disruptive to
4873  * the onscreen content.
4874  *
4875  * Context: Triggered by OS through DM interface, or manually by escape calls.
4876  * Need to hold a dclock when doing so.
4877  *
4878  * Return: none (void function)
4879  *
4880  */
4881 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable)
4882 {
4883         unsigned int softMax = 0, maxDPM = 0, funcMin = 0, i;
4884         bool p_state_change_support;
4885
4886         if (!dc->config.dc_mode_clk_limit_support)
4887                 return;
4888
4889         softMax = dc->clk_mgr->bw_params->dc_mode_softmax_memclk;
4890         for (i = 0; i < dc->clk_mgr->bw_params->clk_table.num_entries; i++) {
4891                 if (dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz > maxDPM)
4892                         maxDPM = dc->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz;
4893         }
4894         funcMin = (dc->clk_mgr->clks.dramclk_khz + 999) / 1000;
4895         p_state_change_support = dc->clk_mgr->clks.p_state_change_support;
4896
4897         if (enable && !dc->clk_mgr->dc_mode_softmax_enabled) {
4898                 if (p_state_change_support) {
4899                         if (funcMin <= softMax)
4900                                 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, softMax);
4901                         // else: No-Op
4902                 } else {
4903                         if (funcMin <= softMax)
4904                                 blank_and_force_memclk(dc, true, softMax);
4905                         // else: No-Op
4906                 }
4907         } else if (!enable && dc->clk_mgr->dc_mode_softmax_enabled) {
4908                 if (p_state_change_support) {
4909                         if (funcMin <= softMax)
4910                                 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, maxDPM);
4911                         // else: No-Op
4912                 } else {
4913                         if (funcMin <= softMax)
4914                                 blank_and_force_memclk(dc, true, maxDPM);
4915                         // else: No-Op
4916                 }
4917         }
4918         dc->clk_mgr->dc_mode_softmax_enabled = enable;
4919 }
4920 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
4921                 struct dc_cursor_attributes *cursor_attr)
4922 {
4923         if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, plane, cursor_attr))
4924                 return true;
4925         return false;
4926 }
4927
4928 /* cleanup on driver unload */
4929 void dc_hardware_release(struct dc *dc)
4930 {
4931         dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(dc);
4932
4933         if (dc->hwss.hardware_release)
4934                 dc->hwss.hardware_release(dc);
4935 }
4936
4937 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc)
4938 {
4939         if (dc->current_state)
4940                 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down = true;
4941 }
4942
4943 /**
4944  * dc_is_dmub_outbox_supported - Check if DMUB firmware support outbox notification
4945  *
4946  * @dc: [in] dc structure
4947  *
4948  * Checks whether DMUB FW supports outbox notifications, if supported DM
4949  * should register outbox interrupt prior to actually enabling interrupts
4950  * via dc_enable_dmub_outbox
4951  *
4952  * Return:
4953  * True if DMUB FW supports outbox notifications, False otherwise
4954  */
4955 bool dc_is_dmub_outbox_supported(struct dc *dc)
4956 {
4957         /* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */
4958         if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
4959             dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
4960             !dc->debug.dpia_debug.bits.disable_dpia)
4961                 return true;
4962
4963         if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1 &&
4964             !dc->debug.dpia_debug.bits.disable_dpia)
4965                 return true;
4966
4967         /* dmub aux needs dmub notifications to be enabled */
4968         return dc->debug.enable_dmub_aux_for_legacy_ddc;
4969 }
4970
4971 /**
4972  * dc_enable_dmub_notifications - Check if dmub fw supports outbox
4973  *
4974  * @dc: [in] dc structure
4975  *
4976  * Calls dc_is_dmub_outbox_supported to check if dmub fw supports outbox
4977  * notifications. All DMs shall switch to dc_is_dmub_outbox_supported.  This
4978  * API shall be removed after switching.
4979  *
4980  * Return:
4981  * True if DMUB FW supports outbox notifications, False otherwise
4982  */
4983 bool dc_enable_dmub_notifications(struct dc *dc)
4984 {
4985         return dc_is_dmub_outbox_supported(dc);
4986 }
4987
4988 /**
4989  * dc_enable_dmub_outbox - Enables DMUB unsolicited notification
4990  *
4991  * @dc: [in] dc structure
4992  *
4993  * Enables DMUB unsolicited notifications to x86 via outbox.
4994  */
4995 void dc_enable_dmub_outbox(struct dc *dc)
4996 {
4997         struct dc_context *dc_ctx = dc->ctx;
4998
4999         dmub_enable_outbox_notification(dc_ctx->dmub_srv);
5000         DC_LOG_DC("%s: dmub outbox notifications enabled\n", __func__);
5001 }
5002
5003 /**
5004  * dc_process_dmub_aux_transfer_async - Submits aux command to dmub via inbox message
5005  *                                      Sets port index appropriately for legacy DDC
5006  * @dc: dc structure
5007  * @link_index: link index
5008  * @payload: aux payload
5009  *
5010  * Returns: True if successful, False if failure
5011  */
5012 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
5013                                 uint32_t link_index,
5014                                 struct aux_payload *payload)
5015 {
5016         uint8_t action;
5017         union dmub_rb_cmd cmd = {0};
5018
5019         ASSERT(payload->length <= 16);
5020
5021         cmd.dp_aux_access.header.type = DMUB_CMD__DP_AUX_ACCESS;
5022         cmd.dp_aux_access.header.payload_bytes = 0;
5023         /* For dpia, ddc_pin is set to NULL */
5024         if (!dc->links[link_index]->ddc->ddc_pin)
5025                 cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_DPIA;
5026         else
5027                 cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC;
5028
5029         cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst;
5030         cmd.dp_aux_access.aux_control.sw_crc_enabled = 0;
5031         cmd.dp_aux_access.aux_control.timeout = 0;
5032         cmd.dp_aux_access.aux_control.dpaux.address = payload->address;
5033         cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux;
5034         cmd.dp_aux_access.aux_control.dpaux.length = payload->length;
5035
5036         /* set aux action */
5037         if (payload->i2c_over_aux) {
5038                 if (payload->write) {
5039                         if (payload->mot)
5040                                 action = DP_AUX_REQ_ACTION_I2C_WRITE_MOT;
5041                         else
5042                                 action = DP_AUX_REQ_ACTION_I2C_WRITE;
5043                 } else {
5044                         if (payload->mot)
5045                                 action = DP_AUX_REQ_ACTION_I2C_READ_MOT;
5046                         else
5047                                 action = DP_AUX_REQ_ACTION_I2C_READ;
5048                         }
5049         } else {
5050                 if (payload->write)
5051                         action = DP_AUX_REQ_ACTION_DPCD_WRITE;
5052                 else
5053                         action = DP_AUX_REQ_ACTION_DPCD_READ;
5054         }
5055
5056         cmd.dp_aux_access.aux_control.dpaux.action = action;
5057
5058         if (payload->length && payload->write) {
5059                 memcpy(cmd.dp_aux_access.aux_control.dpaux.data,
5060                         payload->data,
5061                         payload->length
5062                         );
5063         }
5064
5065         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
5066
5067         return true;
5068 }
5069
5070 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
5071                                             uint8_t dpia_port_index)
5072 {
5073         uint8_t index, link_index = 0xFF;
5074
5075         for (index = 0; index < dc->link_count; index++) {
5076                 /* ddc_hw_inst has dpia port index for dpia links
5077                  * and ddc instance for legacy links
5078                  */
5079                 if (!dc->links[index]->ddc->ddc_pin) {
5080                         if (dc->links[index]->ddc_hw_inst == dpia_port_index) {
5081                                 link_index = index;
5082                                 break;
5083                         }
5084                 }
5085         }
5086         ASSERT(link_index != 0xFF);
5087         return link_index;
5088 }
5089
5090 /**
5091  * dc_process_dmub_set_config_async - Submits set_config command
5092  *
5093  * @dc: [in] dc structure
5094  * @link_index: [in] link_index: link index
5095  * @payload: [in] aux payload
5096  * @notify: [out] set_config immediate reply
5097  *
5098  * Submits set_config command to dmub via inbox message.
5099  *
5100  * Return:
5101  * True if successful, False if failure
5102  */
5103 bool dc_process_dmub_set_config_async(struct dc *dc,
5104                                 uint32_t link_index,
5105                                 struct set_config_cmd_payload *payload,
5106                                 struct dmub_notification *notify)
5107 {
5108         union dmub_rb_cmd cmd = {0};
5109         bool is_cmd_complete = true;
5110
5111         /* prepare SET_CONFIG command */
5112         cmd.set_config_access.header.type = DMUB_CMD__DPIA;
5113         cmd.set_config_access.header.sub_type = DMUB_CMD__DPIA_SET_CONFIG_ACCESS;
5114
5115         cmd.set_config_access.set_config_control.instance = dc->links[link_index]->ddc_hw_inst;
5116         cmd.set_config_access.set_config_control.cmd_pkt.msg_type = payload->msg_type;
5117         cmd.set_config_access.set_config_control.cmd_pkt.msg_data = payload->msg_data;
5118
5119         if (!dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) {
5120                 /* command is not processed by dmub */
5121                 notify->sc_status = SET_CONFIG_UNKNOWN_ERROR;
5122                 return is_cmd_complete;
5123         }
5124
5125         /* command processed by dmub, if ret_status is 1, it is completed instantly */
5126         if (cmd.set_config_access.header.ret_status == 1)
5127                 notify->sc_status = cmd.set_config_access.set_config_control.immed_status;
5128         else
5129                 /* cmd pending, will receive notification via outbox */
5130                 is_cmd_complete = false;
5131
5132         return is_cmd_complete;
5133 }
5134
5135 /**
5136  * dc_process_dmub_set_mst_slots - Submits MST solt allocation
5137  *
5138  * @dc: [in] dc structure
5139  * @link_index: [in] link index
5140  * @mst_alloc_slots: [in] mst slots to be allotted
5141  * @mst_slots_in_use: [out] mst slots in use returned in failure case
5142  *
5143  * Submits mst slot allocation command to dmub via inbox message
5144  *
5145  * Return:
5146  * DC_OK if successful, DC_ERROR if failure
5147  */
5148 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
5149                                 uint32_t link_index,
5150                                 uint8_t mst_alloc_slots,
5151                                 uint8_t *mst_slots_in_use)
5152 {
5153         union dmub_rb_cmd cmd = {0};
5154
5155         /* prepare MST_ALLOC_SLOTS command */
5156         cmd.set_mst_alloc_slots.header.type = DMUB_CMD__DPIA;
5157         cmd.set_mst_alloc_slots.header.sub_type = DMUB_CMD__DPIA_MST_ALLOC_SLOTS;
5158
5159         cmd.set_mst_alloc_slots.mst_slots_control.instance = dc->links[link_index]->ddc_hw_inst;
5160         cmd.set_mst_alloc_slots.mst_slots_control.mst_alloc_slots = mst_alloc_slots;
5161
5162         if (!dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
5163                 /* command is not processed by dmub */
5164                 return DC_ERROR_UNEXPECTED;
5165
5166         /* command processed by dmub, if ret_status is 1 */
5167         if (cmd.set_config_access.header.ret_status != 1)
5168                 /* command processing error */
5169                 return DC_ERROR_UNEXPECTED;
5170
5171         /* command processed and we have a status of 2, mst not enabled in dpia */
5172         if (cmd.set_mst_alloc_slots.mst_slots_control.immed_status == 2)
5173                 return DC_FAIL_UNSUPPORTED_1;
5174
5175         /* previously configured mst alloc and used slots did not match */
5176         if (cmd.set_mst_alloc_slots.mst_slots_control.immed_status == 3) {
5177                 *mst_slots_in_use = cmd.set_mst_alloc_slots.mst_slots_control.mst_slots_in_use;
5178                 return DC_NOT_SUPPORTED;
5179         }
5180
5181         return DC_OK;
5182 }
5183
5184 /**
5185  * dc_process_dmub_dpia_hpd_int_enable - Submits DPIA DPD interruption
5186  *
5187  * @dc: [in] dc structure
5188  * @hpd_int_enable: [in] 1 for hpd int enable, 0 to disable
5189  *
5190  * Submits dpia hpd int enable command to dmub via inbox message
5191  */
5192 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
5193                                 uint32_t hpd_int_enable)
5194 {
5195         union dmub_rb_cmd cmd = {0};
5196
5197         cmd.dpia_hpd_int_enable.header.type = DMUB_CMD__DPIA_HPD_INT_ENABLE;
5198         cmd.dpia_hpd_int_enable.enable = hpd_int_enable;
5199
5200         dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
5201
5202         DC_LOG_DEBUG("%s: hpd_int_enable(%d)\n", __func__, hpd_int_enable);
5203 }
5204
5205 /**
5206  * dc_print_dmub_diagnostic_data - Print DMUB diagnostic data for debugging
5207  *
5208  * @dc: [in] dc structure
5209  *
5210  *
5211  */
5212 void dc_print_dmub_diagnostic_data(const struct dc *dc)
5213 {
5214         dc_dmub_srv_log_diagnostic_data(dc->ctx->dmub_srv);
5215 }
5216
5217 /**
5218  * dc_disable_accelerated_mode - disable accelerated mode
5219  * @dc: dc structure
5220  */
5221 void dc_disable_accelerated_mode(struct dc *dc)
5222 {
5223         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 0);
5224 }
5225
5226
5227 /**
5228  *  dc_notify_vsync_int_state - notifies vsync enable/disable state
5229  *  @dc: dc structure
5230  *  @stream: stream where vsync int state changed
5231  *  @enable: whether vsync is enabled or disabled
5232  *
5233  *  Called when vsync is enabled/disabled Will notify DMUB to start/stop ABM
5234  *  interrupts after steady state is reached.
5235  */
5236 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable)
5237 {
5238         int i;
5239         int edp_num;
5240         struct pipe_ctx *pipe = NULL;
5241         struct dc_link *link = stream->sink->link;
5242         struct dc_link *edp_links[MAX_NUM_EDP];
5243
5244
5245         if (link->psr_settings.psr_feature_enabled)
5246                 return;
5247
5248         /*find primary pipe associated with stream*/
5249         for (i = 0; i < MAX_PIPES; i++) {
5250                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
5251
5252                 if (pipe->stream == stream && pipe->stream_res.tg)
5253                         break;
5254         }
5255
5256         if (i == MAX_PIPES) {
5257                 ASSERT(0);
5258                 return;
5259         }
5260
5261         dc_get_edp_links(dc, edp_links, &edp_num);
5262
5263         /* Determine panel inst */
5264         for (i = 0; i < edp_num; i++) {
5265                 if (edp_links[i] == link)
5266                         break;
5267         }
5268
5269         if (i == edp_num) {
5270                 return;
5271         }
5272
5273         if (pipe->stream_res.abm && pipe->stream_res.abm->funcs->set_abm_pause)
5274                 pipe->stream_res.abm->funcs->set_abm_pause(pipe->stream_res.abm, !enable, i, pipe->stream_res.tg->inst);
5275 }