drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "core_types.h"
  27 #include "clk_mgr_internal.h"
  28 #include "reg_helper.h"
  29 #include <linux/delay.h>
  30
  31 #include "dcn301_smu.h"
  32
  33 #include "vangogh_ip_offset.h"
  34
  35 #include "mp/mp_11_5_0_offset.h"
  36 #include "mp/mp_11_5_0_sh_mask.h"
  37
  38 #define REG(reg_name) \
  39         (MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
  40
  41 #define FN(reg_name, field) \
  42         FD(reg_name##__##field)
  43
  44 #define VBIOSSMC_MSG_GetSmuVersion                0x2
  45 #define VBIOSSMC_MSG_SetDispclkFreq               0x4
  46 #define VBIOSSMC_MSG_SetDprefclkFreq              0x5
  47 #define VBIOSSMC_MSG_SetDppclkFreq                0x6
  48 #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq       0x7
  49 #define VBIOSSMC_MSG_SetMinDeepSleepDcfclk        0x8
  50 //#define VBIOSSMC_MSG_SetPhyclkVoltageByFreq       0xA
  51 #define VBIOSSMC_MSG_GetFclkFrequency             0xA
  52 //#define VBIOSSMC_MSG_SetDisplayCount              0xC
  53 //#define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xD
  54 #define VBIOSSMC_MSG_UpdatePmeRestore                     0xD
  55 #define VBIOSSMC_MSG_SetVbiosDramAddrHigh         0xE   //Used for WM table txfr
  56 #define VBIOSSMC_MSG_SetVbiosDramAddrLow          0xF
  57 #define VBIOSSMC_MSG_TransferTableSmu2Dram        0x10
  58 #define VBIOSSMC_MSG_TransferTableDram2Smu        0x11
  59 #define VBIOSSMC_MSG_SetDisplayIdleOptimizations  0x12
  60
  61 #define VBIOSSMC_Status_BUSY                      0x0
  62 #define VBIOSSMC_Result_OK                        0x1
  63 #define VBIOSSMC_Result_Failed                    0xFF
  64 #define VBIOSSMC_Result_UnknownCmd                0xFE
  65 #define VBIOSSMC_Result_CmdRejectedPrereq         0xFD
  66 #define VBIOSSMC_Result_CmdRejectedBusy           0xFC
  67
  68 /*
  69  * Function to be used instead of REG_WAIT macro because the wait ends when
  70  * the register is NOT EQUAL to zero, and because the translation in msg_if.h
  71  * won't work with REG_WAIT.
  72  */
  73 static uint32_t dcn301_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
  74 {
  75         uint32_t res_val = VBIOSSMC_Status_BUSY;
  76
  77         do {
  78                 res_val = REG_READ(MP1_SMN_C2PMSG_91);
  79                 if (res_val != VBIOSSMC_Status_BUSY)
  80                         break;
  81
  82                 if (delay_us >= 1000)
  83                         msleep(delay_us/1000);
  84                 else if (delay_us > 0)
  85                         udelay(delay_us);
  86         } while (max_retries--);
  87
  88         return res_val;
  89 }
  90
  91 int dcn301_smu_send_msg_with_param(
  92                 struct clk_mgr_internal *clk_mgr,
  93                 unsigned int msg_id, unsigned int param)
  94 {
  95         uint32_t result;
  96
  97         /* First clear response register */
  98         REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
  99
 100         /* Set the parameter register for the SMU message, unit is Mhz */
 101         REG_WRITE(MP1_SMN_C2PMSG_83, param);
 102
 103         /* Trigger the message transaction by writing the message ID */
 104         REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
 105
 106         result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000);
 107
 108         ASSERT(result == VBIOSSMC_Result_OK);
 109
 110         /* Actual dispclk set is returned in the parameter register */
 111         return REG_READ(MP1_SMN_C2PMSG_83);
 112 }
 113
 114 int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
 115 {
 116         return dcn301_smu_send_msg_with_param(
 117                         clk_mgr,
 118                         VBIOSSMC_MSG_GetSmuVersion,
 119                         0);
 120 }
 121
 122
 123 int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
 124 {
 125         int actual_dispclk_set_mhz = -1;
 126
 127         /*  Unit of SMU msg parameter is Mhz */
 128         actual_dispclk_set_mhz = dcn301_smu_send_msg_with_param(
 129                         clk_mgr,
 130                         VBIOSSMC_MSG_SetDispclkFreq,
 131                         requested_dispclk_khz / 1000);
 132
 133         return actual_dispclk_set_mhz * 1000;
 134 }
 135
 136 int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
 137 {
 138         int actual_dprefclk_set_mhz = -1;
 139
 140         actual_dprefclk_set_mhz = dcn301_smu_send_msg_with_param(
 141                         clk_mgr,
 142                         VBIOSSMC_MSG_SetDprefclkFreq,
 143                         clk_mgr->base.dprefclk_khz / 1000);
 144
 145         /* TODO: add code for programing DP DTO, currently this is down by command table */
 146
 147         return actual_dprefclk_set_mhz * 1000;
 148 }
 149
 150 int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
 151 {
 152         int actual_dcfclk_set_mhz = -1;
 153
 154         actual_dcfclk_set_mhz = dcn301_smu_send_msg_with_param(
 155                         clk_mgr,
 156                         VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
 157                         requested_dcfclk_khz / 1000);
 158
 159         return actual_dcfclk_set_mhz * 1000;
 160 }
 161
 162 int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
 163 {
 164         int actual_min_ds_dcfclk_mhz = -1;
 165
 166         actual_min_ds_dcfclk_mhz = dcn301_smu_send_msg_with_param(
 167                         clk_mgr,
 168                         VBIOSSMC_MSG_SetMinDeepSleepDcfclk,
 169                         requested_min_ds_dcfclk_khz / 1000);
 170
 171         return actual_min_ds_dcfclk_mhz * 1000;
 172 }
 173
 174 int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
 175 {
 176         int actual_dppclk_set_mhz = -1;
 177
 178         actual_dppclk_set_mhz = dcn301_smu_send_msg_with_param(
 179                         clk_mgr,
 180                         VBIOSSMC_MSG_SetDppclkFreq,
 181                         requested_dpp_khz / 1000);
 182
 183         return actual_dppclk_set_mhz * 1000;
 184 }
 185
 186 void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)
 187 {
 188         //TODO: Work with smu team to define optimization options.
 189
 190         dcn301_smu_send_msg_with_param(
 191                 clk_mgr,
 192                 VBIOSSMC_MSG_SetDisplayIdleOptimizations,
 193                 idle_info);
 194 }
 195
 196 void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
 197 {
 198         union display_idle_optimization_u idle_info = { 0 };
 199
 200         if (enable) {
 201                 idle_info.idle_info.df_request_disabled = 1;
 202                 idle_info.idle_info.phy_ref_clk_off = 1;
 203         }
 204
 205         dcn301_smu_send_msg_with_param(
 206                         clk_mgr,
 207                         VBIOSSMC_MSG_SetDisplayIdleOptimizations,
 208                         idle_info.data);
 209 }
 210
 211 void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
 212 {
 213         dcn301_smu_send_msg_with_param(
 214                         clk_mgr,
 215                         VBIOSSMC_MSG_UpdatePmeRestore,
 216                         0);
 217 }
 218
 219 void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
 220 {
 221         dcn301_smu_send_msg_with_param(clk_mgr,
 222                         VBIOSSMC_MSG_SetVbiosDramAddrHigh, addr_high);
 223 }
 224
 225 void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
 226 {
 227         dcn301_smu_send_msg_with_param(clk_mgr,
 228                         VBIOSSMC_MSG_SetVbiosDramAddrLow, addr_low);
 229 }
 230
 231 void dcn301_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)
 232 {
 233         dcn301_smu_send_msg_with_param(clk_mgr,
 234                         VBIOSSMC_MSG_TransferTableSmu2Dram, TABLE_DPMCLOCKS);
 235 }
 236
 237 void dcn301_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
 238 {
 239         dcn301_smu_send_msg_with_param(clk_mgr,
 240                         VBIOSSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS);
 241 }