drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dccg.h"
  27 #include "clk_mgr_internal.h"
  28
  29
  30 #include "dcn20/dcn20_clk_mgr.h"
  31 #include "rn_clk_mgr.h"
  32
  33
  34 #include "dce100/dce_clk_mgr.h"
  35 #include "rn_clk_mgr_vbios_smu.h"
  36 #include "reg_helper.h"
  37 #include "core_types.h"
  38 #include "dm_helpers.h"
  39
  40 #include "atomfirmware.h"
  41 #include "clk/clk_10_0_2_offset.h"
  42 #include "clk/clk_10_0_2_sh_mask.h"
  43 #include "renoir_ip_offset.h"
  44
  45 #include "irq/dcn21/irq_service_dcn21.h"
  46
  47 /* Constants */
  48
  49 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
  50 #define SMU_VER_55_51_0 0x373300 /* SMU Version that is able to set DISPCLK below 100MHz */
  51
  52 /* Macros */
  53
  54 #define REG(reg_name) \
  55         (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
  56
  57
  58 /* TODO: evaluate how to lower or disable all dcn clocks in screen off case */
  59 int rn_get_active_display_cnt_wa(
  60                 struct dc *dc,
  61                 struct dc_state *context)
  62 {
  63         int i, display_count;
  64         bool tmds_present = false;
  65
  66         display_count = 0;
  67         for (i = 0; i < context->stream_count; i++) {
  68                 const struct dc_stream_state *stream = context->streams[i];
  69
  70                 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
  71                                 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
  72                                 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
  73                         tmds_present = true;
  74         }
  75
  76         for (i = 0; i < dc->link_count; i++) {
  77                 const struct dc_link *link = dc->links[i];
  78
  79                 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
  80                 if (link->link_enc->funcs->is_dig_enabled(link->link_enc))
  81                         display_count++;
  82         }
  83
  84         /* WA for hang on HDMI after display off back back on*/
  85         if (display_count == 0 && tmds_present)
  86                 display_count = 1;
  87
  88         return display_count;
  89 }
  90
  91 void rn_set_low_power_state(struct clk_mgr *clk_mgr_base)
  92 {
  93         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
  94
  95         rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
  96         /* update power state */
  97         clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
  98 }
  99
 100 static void rn_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
 101                 struct dc_state *context, int ref_dpp_clk, bool safe_to_lower)
 102 {
 103         int i;
 104
 105         clk_mgr->dccg->ref_dppclk = ref_dpp_clk;
 106
 107         for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
 108                 int dpp_inst, dppclk_khz, prev_dppclk_khz;
 109
 110                 /* Loop index may not match dpp->inst if some pipes disabled,
 111                  * so select correct inst from res_pool
 112                  */
 113                 dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst;
 114                 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
 115
 116                 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
 117
 118                 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
 119                         clk_mgr->dccg->funcs->update_dpp_dto(
 120                                                         clk_mgr->dccg, dpp_inst, dppclk_khz);
 121         }
 122 }
 123
 124
 125 void rn_update_clocks(struct clk_mgr *clk_mgr_base,
 126                         struct dc_state *context,
 127                         bool safe_to_lower)
 128 {
 129         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 130         struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
 131         struct dc *dc = clk_mgr_base->ctx->dc;
 132         int display_count;
 133         int irq_src;
 134         bool update_dppclk = false;
 135         bool update_dispclk = false;
 136         bool dpp_clock_lowered = false;
 137         uint32_t hpd_state;
 138
 139         struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
 140
 141         if (dc->work_arounds.skip_clock_update)
 142                 return;
 143
 144         /*
 145          * if it is safe to lower, but we are already in the lower state, we don't have to do anything
 146          * also if safe to lower is false, we just go in the higher state
 147          */
 148         if (safe_to_lower && !dc->debug.disable_48mhz_pwrdwn) {
 149                 /* check that we're not already in lower */
 150                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
 151
 152                         display_count = rn_get_active_display_cnt_wa(dc, context);
 153
 154                         for (irq_src = DC_IRQ_SOURCE_HPD1; irq_src <= DC_IRQ_SOURCE_HPD5; irq_src++) {
 155                                 hpd_state = dal_get_hpd_state_dcn21(dc->res_pool->irqs, irq_src);
 156                                 if (hpd_state)
 157                                         break;
 158                         }
 159
 160                         /* if we can go lower, go lower */
 161                         if (display_count == 0 && !hpd_state) {
 162                                 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
 163                                 /* update power state */
 164                                 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
 165                         }
 166                 }
 167         } else {
 168                 /* check that we're not already in D0 */
 169                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
 170                         rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE);
 171                         /* update power state */
 172                         clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
 173                 }
 174         }
 175
 176         if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
 177                 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
 178                 rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
 179         }
 180
 181         if (should_set_clock(safe_to_lower,
 182                         new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
 183                 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
 184                 rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
 185         }
 186
 187         // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
 188         // Do not adjust dppclk if dppclk is 0 to avoid unexpected result
 189         if (new_clocks->dppclk_khz < 100000 && new_clocks->dppclk_khz > 0)
 190                 new_clocks->dppclk_khz = 100000;
 191
 192         /*
 193          * Temporally ignore thew 0 cases for disp and dpp clks.
 194          * We may have a new feature that requires 0 clks in the future.
 195          */
 196         if (new_clocks->dppclk_khz == 0 || new_clocks->dispclk_khz == 0) {
 197                 new_clocks->dppclk_khz = clk_mgr_base->clks.dppclk_khz;
 198                 new_clocks->dispclk_khz = clk_mgr_base->clks.dispclk_khz;
 199         }
 200
 201         if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
 202                 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
 203                         dpp_clock_lowered = true;
 204                 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
 205                 update_dppclk = true;
 206         }
 207
 208         if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
 209                 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 210                 clk_mgr_base->clks.actual_dispclk_khz = rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
 211
 212                 update_dispclk = true;
 213         }
 214
 215         if (dpp_clock_lowered) {
 216                 // increase per DPP DTO before lowering global dppclk with requested dppclk
 217                 rn_update_clocks_update_dpp_dto(
 218                                 clk_mgr,
 219                                 context,
 220                                 clk_mgr_base->clks.dppclk_khz,
 221                                 safe_to_lower);
 222
 223                 clk_mgr_base->clks.actual_dppclk_khz =
 224                                 rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 225
 226                 //update dpp dto with actual dpp clk.
 227                 rn_update_clocks_update_dpp_dto(
 228                                 clk_mgr,
 229                                 context,
 230                                 clk_mgr_base->clks.actual_dppclk_khz,
 231                                 safe_to_lower);
 232
 233         } else {
 234                 // increase global DPPCLK before lowering per DPP DTO
 235                 if (update_dppclk || update_dispclk)
 236                         clk_mgr_base->clks.actual_dppclk_khz =
 237                                         rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 238
 239                 // always update dtos unless clock is lowered and not safe to lower
 240                 rn_update_clocks_update_dpp_dto(
 241                                 clk_mgr,
 242                                 context,
 243                                 clk_mgr_base->clks.actual_dppclk_khz,
 244                                 safe_to_lower);
 245         }
 246
 247         if (update_dispclk &&
 248                         dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
 249                 /*update dmcu for wait_loop count*/
 250                 dmcu->funcs->set_psr_wait_loop(dmcu,
 251                         clk_mgr_base->clks.dispclk_khz / 1000 / 7);
 252         }
 253 }
 254
 255 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
 256 {
 257         /* get FbMult value */
 258         struct fixed31_32 pll_req;
 259         unsigned int fbmult_frac_val = 0;
 260         unsigned int fbmult_int_val = 0;
 261
 262
 263         /*
 264          * Register value of fbmult is in 8.16 format, we are converting to 31.32
 265          * to leverage the fix point operations available in driver
 266          */
 267
 268         REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
 269         REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
 270
 271         pll_req = dc_fixpt_from_int(fbmult_int_val);
 272
 273         /*
 274          * since fractional part is only 16 bit in register definition but is 32 bit
 275          * in our fix point definiton, need to shift left by 16 to obtain correct value
 276          */
 277         pll_req.value |= fbmult_frac_val << 16;
 278
 279         /* multiply by REFCLK period */
 280         pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
 281
 282         /* integer part is now VCO frequency in kHz */
 283         return dc_fixpt_floor(pll_req);
 284 }
 285
 286 static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base)
 287 {
 288         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 289
 290         internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);
 291         internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL);
 292
 293         internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL);      //dcf deep sleep divider
 294         internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS);
 295
 296         internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);
 297         internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL);
 298
 299         internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);
 300         internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL);
 301
 302         internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);
 303         internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL);
 304 }
 305
 306 /* This function collect raw clk register values */
 307 static void rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
 308                 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
 309 {
 310         struct rn_clk_internal internal = {0};
 311         char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
 312         unsigned int chars_printed = 0;
 313         unsigned int remaining_buffer = log_info->bufSize;
 314
 315         rn_dump_clk_registers_internal(&internal, clk_mgr_base);
 316
 317         regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
 318         regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
 319         regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;
 320         regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
 321         regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
 322         regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
 323
 324         regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
 325         if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
 326                 regs_and_bypass->dppclk_bypass = 0;
 327         regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
 328         if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
 329                 regs_and_bypass->dcfclk_bypass = 0;
 330         regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
 331         if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
 332                 regs_and_bypass->dispclk_bypass = 0;
 333         regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
 334         if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
 335                 regs_and_bypass->dprefclk_bypass = 0;
 336
 337         if (log_info->enabled) {
 338                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
 339                 remaining_buffer -= chars_printed;
 340                 *log_info->sum_chars_printed += chars_printed;
 341                 log_info->pBuf += chars_printed;
 342
 343                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n",
 344                         regs_and_bypass->dcfclk,
 345                         regs_and_bypass->dcf_deep_sleep_divider,
 346                         regs_and_bypass->dcf_deep_sleep_allow,
 347                         bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
 348                 remaining_buffer -= chars_printed;
 349                 *log_info->sum_chars_printed += chars_printed;
 350                 log_info->pBuf += chars_printed;
 351
 352                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n",
 353                         regs_and_bypass->dprefclk,
 354                         bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
 355                 remaining_buffer -= chars_printed;
 356                 *log_info->sum_chars_printed += chars_printed;
 357                 log_info->pBuf += chars_printed;
 358
 359                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
 360                         regs_and_bypass->dispclk,
 361                         bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
 362                 remaining_buffer -= chars_printed;
 363                 *log_info->sum_chars_printed += chars_printed;
 364                 log_info->pBuf += chars_printed;
 365
 366                 //split
 367                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n");
 368                 remaining_buffer -= chars_printed;
 369                 *log_info->sum_chars_printed += chars_printed;
 370                 log_info->pBuf += chars_printed;
 371
 372                 // REGISTER VALUES
 373                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n");
 374                 remaining_buffer -= chars_printed;
 375                 *log_info->sum_chars_printed += chars_printed;
 376                 log_info->pBuf += chars_printed;
 377
 378                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n",
 379                                 internal.CLK1_CLK3_CURRENT_CNT);
 380                 remaining_buffer -= chars_printed;
 381                 *log_info->sum_chars_printed += chars_printed;
 382                 log_info->pBuf += chars_printed;
 383
 384                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
 385                                         internal.CLK1_CLK3_DS_CNTL);
 386                 remaining_buffer -= chars_printed;
 387                 *log_info->sum_chars_printed += chars_printed;
 388                 log_info->pBuf += chars_printed;
 389
 390                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n",
 391                                         internal.CLK1_CLK3_ALLOW_DS);
 392                 remaining_buffer -= chars_printed;
 393                 *log_info->sum_chars_printed += chars_printed;
 394                 log_info->pBuf += chars_printed;
 395
 396                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n",
 397                                         internal.CLK1_CLK2_CURRENT_CNT);
 398                 remaining_buffer -= chars_printed;
 399                 *log_info->sum_chars_printed += chars_printed;
 400                 log_info->pBuf += chars_printed;
 401
 402                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
 403                                         internal.CLK1_CLK0_CURRENT_CNT);
 404                 remaining_buffer -= chars_printed;
 405                 *log_info->sum_chars_printed += chars_printed;
 406                 log_info->pBuf += chars_printed;
 407
 408                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",
 409                                         internal.CLK1_CLK1_CURRENT_CNT);
 410                 remaining_buffer -= chars_printed;
 411                 *log_info->sum_chars_printed += chars_printed;
 412                 log_info->pBuf += chars_printed;
 413
 414                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n",
 415                                         internal.CLK1_CLK3_BYPASS_CNTL);
 416                 remaining_buffer -= chars_printed;
 417                 *log_info->sum_chars_printed += chars_printed;
 418                 log_info->pBuf += chars_printed;
 419
 420                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n",
 421                                         internal.CLK1_CLK2_BYPASS_CNTL);
 422                 remaining_buffer -= chars_printed;
 423                 *log_info->sum_chars_printed += chars_printed;
 424                 log_info->pBuf += chars_printed;
 425
 426                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n",
 427                                         internal.CLK1_CLK0_BYPASS_CNTL);
 428                 remaining_buffer -= chars_printed;
 429                 *log_info->sum_chars_printed += chars_printed;
 430                 log_info->pBuf += chars_printed;
 431
 432                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n",
 433                                         internal.CLK1_CLK1_BYPASS_CNTL);
 434                 remaining_buffer -= chars_printed;
 435                 *log_info->sum_chars_printed += chars_printed;
 436                 log_info->pBuf += chars_printed;
 437         }
 438 }
 439
 440 /* This function produce translated logical clk state values*/
 441 void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
 442 {
 443         struct clk_state_registers_and_bypass sb = { 0 };
 444         struct clk_log_info log_info = { 0 };
 445
 446         rn_dump_clk_registers(&sb, clk_mgr_base, &log_info);
 447
 448         s->dprefclk_khz = sb.dprefclk * 1000;
 449 }
 450
 451 void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
 452 {
 453         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 454
 455         rn_vbios_smu_enable_pme_wa(clk_mgr);
 456 }
 457
 458 void rn_init_clocks(struct clk_mgr *clk_mgr)
 459 {
 460         memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
 461         // Assumption is that boot state always supports pstate
 462         clk_mgr->clks.p_state_change_support = true;
 463         clk_mgr->clks.prev_p_state_change_support = true;
 464         clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
 465 }
 466
 467 static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
 468 {
 469         int i, num_valid_sets;
 470
 471         num_valid_sets = 0;
 472
 473         for (i = 0; i < WM_SET_COUNT; i++) {
 474                 /* skip empty entries, the smu array has no holes*/
 475                 if (!bw_params->wm_table.entries[i].valid)
 476                         continue;
 477
 478                 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
 479                 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;
 480                 /* We will not select WM based on fclk, so leave it as unconstrained */
 481                 ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 482                 ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 483                 /* dcfclk wil be used to select WM*/
 484
 485                 if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) {
 486                         if (i == 0)
 487                                 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 0;
 488                         else {
 489                                 /* add 1 to make it non-overlapping with next lvl */
 490                                 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
 491                         }
 492                         ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
 493
 494                 } else {
 495                         /* unconstrained for memory retraining */
 496                         ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 497                         ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 498
 499                         /* Modify previous watermark range to cover up to max */
 500                         ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 501                 }
 502                 num_valid_sets++;
 503         }
 504
 505         ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
 506         ranges->num_reader_wm_sets = num_valid_sets;
 507
 508         /* modify the min and max to make sure we cover the whole range*/
 509         ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 510         ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 511         ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 512         ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 513
 514         /* This is for writeback only, does not matter currently as no writeback support*/
 515         ranges->num_writer_wm_sets = 1;
 516         ranges->writer_wm_sets[0].wm_inst = WM_A;
 517         ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 518         ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 519         ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 520         ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 521
 522 }
 523
 524 static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 525 {
 526         struct dc_debug_options *debug = &clk_mgr_base->ctx->dc->debug;
 527         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 528         struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu;
 529
 530         if (!debug->disable_pplib_wm_range) {
 531                 build_watermark_ranges(clk_mgr_base->bw_params, &clk_mgr_base->ranges);
 532
 533                 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
 534                 if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)
 535                         pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges);
 536         }
 537
 538 }
 539
 540 static bool rn_are_clock_states_equal(struct dc_clocks *a,
 541                 struct dc_clocks *b)
 542 {
 543         if (a->dispclk_khz != b->dispclk_khz)
 544                 return false;
 545         else if (a->dppclk_khz != b->dppclk_khz)
 546                 return false;
 547         else if (a->dcfclk_khz != b->dcfclk_khz)
 548                 return false;
 549         else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
 550                 return false;
 551
 552         return true;
 553 }
 554
 555
 556 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
 557 static void rn_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)
 558 {
 559         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 560         unsigned int i, max_phyclk_req = 0;
 561
 562         clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
 563
 564         for (i = 0; i < MAX_PIPES * 2; i++) {
 565                 if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
 566                         max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
 567         }
 568
 569         if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
 570                 clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
 571                 rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz);
 572         }
 573 }
 574
 575 static struct clk_mgr_funcs dcn21_funcs = {
 576         .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 577         .update_clocks = rn_update_clocks,
 578         .init_clocks = rn_init_clocks,
 579         .enable_pme_wa = rn_enable_pme_wa,
 580         .are_clock_states_equal = rn_are_clock_states_equal,
 581         .set_low_power_state = rn_set_low_power_state,
 582         .notify_wm_ranges = rn_notify_wm_ranges,
 583         .notify_link_rate_change = rn_notify_link_rate_change,
 584 };
 585
 586 static struct clk_bw_params rn_bw_params = {
 587         .vram_type = Ddr4MemType,
 588         .num_channels = 1,
 589         .clk_table = {
 590                 .entries = {
 591                         {
 592                                 .voltage = 0,
 593                                 .dcfclk_mhz = 400,
 594                                 .fclk_mhz = 400,
 595                                 .memclk_mhz = 800,
 596                                 .socclk_mhz = 0,
 597                         },
 598                         {
 599                                 .voltage = 0,
 600                                 .dcfclk_mhz = 483,
 601                                 .fclk_mhz = 800,
 602                                 .memclk_mhz = 1600,
 603                                 .socclk_mhz = 0,
 604                         },
 605                         {
 606                                 .voltage = 0,
 607                                 .dcfclk_mhz = 602,
 608                                 .fclk_mhz = 1067,
 609                                 .memclk_mhz = 1067,
 610                                 .socclk_mhz = 0,
 611                         },
 612                         {
 613                                 .voltage = 0,
 614                                 .dcfclk_mhz = 738,
 615                                 .fclk_mhz = 1333,
 616                                 .memclk_mhz = 1600,
 617                                 .socclk_mhz = 0,
 618                         },
 619                 },
 620
 621                 .num_entries = 4,
 622         },
 623
 624 };
 625
 626 static struct wm_table ddr4_wm_table_gs = {
 627         .entries = {
 628                 {
 629                         .wm_inst = WM_A,
 630                         .wm_type = WM_TYPE_PSTATE_CHG,
 631                         .pstate_latency_us = 11.72,
 632                         .sr_exit_time_us = 7.09,
 633                         .sr_enter_plus_exit_time_us = 8.14,
 634                         .valid = true,
 635                 },
 636                 {
 637                         .wm_inst = WM_B,
 638                         .wm_type = WM_TYPE_PSTATE_CHG,
 639                         .pstate_latency_us = 11.72,
 640                         .sr_exit_time_us = 10.12,
 641                         .sr_enter_plus_exit_time_us = 11.48,
 642                         .valid = true,
 643                 },
 644                 {
 645                         .wm_inst = WM_C,
 646                         .wm_type = WM_TYPE_PSTATE_CHG,
 647                         .pstate_latency_us = 11.72,
 648                         .sr_exit_time_us = 10.12,
 649                         .sr_enter_plus_exit_time_us = 11.48,
 650                         .valid = true,
 651                 },
 652                 {
 653                         .wm_inst = WM_D,
 654                         .wm_type = WM_TYPE_PSTATE_CHG,
 655                         .pstate_latency_us = 11.72,
 656                         .sr_exit_time_us = 10.12,
 657                         .sr_enter_plus_exit_time_us = 11.48,
 658                         .valid = true,
 659                 },
 660         }
 661 };
 662
 663 static struct wm_table lpddr4_wm_table_gs = {
 664         .entries = {
 665                 {
 666                         .wm_inst = WM_A,
 667                         .wm_type = WM_TYPE_PSTATE_CHG,
 668                         .pstate_latency_us = 11.65333,
 669                         .sr_exit_time_us = 5.32,
 670                         .sr_enter_plus_exit_time_us = 6.38,
 671                         .valid = true,
 672                 },
 673                 {
 674                         .wm_inst = WM_B,
 675                         .wm_type = WM_TYPE_PSTATE_CHG,
 676                         .pstate_latency_us = 11.65333,
 677                         .sr_exit_time_us = 9.82,
 678                         .sr_enter_plus_exit_time_us = 11.196,
 679                         .valid = true,
 680                 },
 681                 {
 682                         .wm_inst = WM_C,
 683                         .wm_type = WM_TYPE_PSTATE_CHG,
 684                         .pstate_latency_us = 11.65333,
 685                         .sr_exit_time_us = 9.89,
 686                         .sr_enter_plus_exit_time_us = 11.24,
 687                         .valid = true,
 688                 },
 689                 {
 690                         .wm_inst = WM_D,
 691                         .wm_type = WM_TYPE_PSTATE_CHG,
 692                         .pstate_latency_us = 11.65333,
 693                         .sr_exit_time_us = 9.748,
 694                         .sr_enter_plus_exit_time_us = 11.102,
 695                         .valid = true,
 696                 },
 697         }
 698 };
 699
 700 static struct wm_table lpddr4_wm_table_with_disabled_ppt = {
 701         .entries = {
 702                 {
 703                         .wm_inst = WM_A,
 704                         .wm_type = WM_TYPE_PSTATE_CHG,
 705                         .pstate_latency_us = 11.65333,
 706                         .sr_exit_time_us = 8.32,
 707                         .sr_enter_plus_exit_time_us = 9.38,
 708                         .valid = true,
 709                 },
 710                 {
 711                         .wm_inst = WM_B,
 712                         .wm_type = WM_TYPE_PSTATE_CHG,
 713                         .pstate_latency_us = 11.65333,
 714                         .sr_exit_time_us = 9.82,
 715                         .sr_enter_plus_exit_time_us = 11.196,
 716                         .valid = true,
 717                 },
 718                 {
 719                         .wm_inst = WM_C,
 720                         .wm_type = WM_TYPE_PSTATE_CHG,
 721                         .pstate_latency_us = 11.65333,
 722                         .sr_exit_time_us = 9.89,
 723                         .sr_enter_plus_exit_time_us = 11.24,
 724                         .valid = true,
 725                 },
 726                 {
 727                         .wm_inst = WM_D,
 728                         .wm_type = WM_TYPE_PSTATE_CHG,
 729                         .pstate_latency_us = 11.65333,
 730                         .sr_exit_time_us = 9.748,
 731                         .sr_enter_plus_exit_time_us = 11.102,
 732                         .valid = true,
 733                 },
 734         }
 735 };
 736
 737 static struct wm_table ddr4_wm_table_rn = {
 738         .entries = {
 739                 {
 740                         .wm_inst = WM_A,
 741                         .wm_type = WM_TYPE_PSTATE_CHG,
 742                         .pstate_latency_us = 11.72,
 743                         .sr_exit_time_us = 11.90,
 744                         .sr_enter_plus_exit_time_us = 12.80,
 745                         .valid = true,
 746                 },
 747                 {
 748                         .wm_inst = WM_B,
 749                         .wm_type = WM_TYPE_PSTATE_CHG,
 750                         .pstate_latency_us = 11.72,
 751                         .sr_exit_time_us = 13.18,
 752                         .sr_enter_plus_exit_time_us = 14.30,
 753                         .valid = true,
 754                 },
 755                 {
 756                         .wm_inst = WM_C,
 757                         .wm_type = WM_TYPE_PSTATE_CHG,
 758                         .pstate_latency_us = 11.72,
 759                         .sr_exit_time_us = 13.18,
 760                         .sr_enter_plus_exit_time_us = 14.30,
 761                         .valid = true,
 762                 },
 763                 {
 764                         .wm_inst = WM_D,
 765                         .wm_type = WM_TYPE_PSTATE_CHG,
 766                         .pstate_latency_us = 11.72,
 767                         .sr_exit_time_us = 13.18,
 768                         .sr_enter_plus_exit_time_us = 14.30,
 769                         .valid = true,
 770                 },
 771         }
 772 };
 773
 774 static struct wm_table ddr4_1R_wm_table_rn = {
 775         .entries = {
 776                 {
 777                         .wm_inst = WM_A,
 778                         .wm_type = WM_TYPE_PSTATE_CHG,
 779                         .pstate_latency_us = 11.72,
 780                         .sr_exit_time_us = 13.90,
 781                         .sr_enter_plus_exit_time_us = 14.80,
 782                         .valid = true,
 783                 },
 784                 {
 785                         .wm_inst = WM_B,
 786                         .wm_type = WM_TYPE_PSTATE_CHG,
 787                         .pstate_latency_us = 11.72,
 788                         .sr_exit_time_us = 13.90,
 789                         .sr_enter_plus_exit_time_us = 14.80,
 790                         .valid = true,
 791                 },
 792                 {
 793                         .wm_inst = WM_C,
 794                         .wm_type = WM_TYPE_PSTATE_CHG,
 795                         .pstate_latency_us = 11.72,
 796                         .sr_exit_time_us = 13.90,
 797                         .sr_enter_plus_exit_time_us = 14.80,
 798                         .valid = true,
 799                 },
 800                 {
 801                         .wm_inst = WM_D,
 802                         .wm_type = WM_TYPE_PSTATE_CHG,
 803                         .pstate_latency_us = 11.72,
 804                         .sr_exit_time_us = 13.90,
 805                         .sr_enter_plus_exit_time_us = 14.80,
 806                         .valid = true,
 807                 },
 808         }
 809 };
 810
 811 static struct wm_table lpddr4_wm_table_rn = {
 812         .entries = {
 813                 {
 814                         .wm_inst = WM_A,
 815                         .wm_type = WM_TYPE_PSTATE_CHG,
 816                         .pstate_latency_us = 11.65333,
 817                         .sr_exit_time_us = 7.32,
 818                         .sr_enter_plus_exit_time_us = 8.38,
 819                         .valid = true,
 820                 },
 821                 {
 822                         .wm_inst = WM_B,
 823                         .wm_type = WM_TYPE_PSTATE_CHG,
 824                         .pstate_latency_us = 11.65333,
 825                         .sr_exit_time_us = 9.82,
 826                         .sr_enter_plus_exit_time_us = 11.196,
 827                         .valid = true,
 828                 },
 829                 {
 830                         .wm_inst = WM_C,
 831                         .wm_type = WM_TYPE_PSTATE_CHG,
 832                         .pstate_latency_us = 11.65333,
 833                         .sr_exit_time_us = 9.89,
 834                         .sr_enter_plus_exit_time_us = 11.24,
 835                         .valid = true,
 836                 },
 837                 {
 838                         .wm_inst = WM_D,
 839                         .wm_type = WM_TYPE_PSTATE_CHG,
 840                         .pstate_latency_us = 11.65333,
 841                         .sr_exit_time_us = 9.748,
 842                         .sr_enter_plus_exit_time_us = 11.102,
 843                         .valid = true,
 844                 },
 845         }
 846 };
 847
 848 static unsigned int find_socclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
 849 {
 850         int i;
 851
 852         for (i = 0; i < PP_SMU_NUM_SOCCLK_DPM_LEVELS; i++) {
 853                 if (clock_table->SocClocks[i].Vol == voltage)
 854                         return clock_table->SocClocks[i].Freq;
 855         }
 856
 857         ASSERT(0);
 858         return 0;
 859 }
 860
 861 static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
 862 {
 863         int i;
 864
 865         for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) {
 866                 if (clock_table->DcfClocks[i].Vol == voltage)
 867                         return clock_table->DcfClocks[i].Freq;
 868         }
 869
 870         ASSERT(0);
 871         return 0;
 872 }
 873
 874 static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info)
 875 {
 876         int i, j = 0;
 877
 878         j = -1;
 879
 880         ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
 881
 882         /* Find lowest DPM, FCLK is filled in reverse order*/
 883
 884         for (i = PP_SMU_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) {
 885                 if (clock_table->FClocks[i].Freq != 0 && clock_table->FClocks[i].Vol != 0) {
 886                         j = i;
 887                         break;
 888                 }
 889         }
 890
 891         if (j == -1) {
 892                 /* clock table is all 0s, just use our own hardcode */
 893                 ASSERT(0);
 894                 return;
 895         }
 896
 897         bw_params->clk_table.num_entries = j + 1;
 898
 899         for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
 900                 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq;
 901                 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq;
 902                 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol;
 903                 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
 904                 bw_params->clk_table.entries[i].socclk_mhz = find_socclk_for_voltage(clock_table,
 905                                                                         bw_params->clk_table.entries[i].voltage);
 906         }
 907
 908         bw_params->vram_type = bios_info->memory_type;
 909         bw_params->num_channels = bios_info->ma_channel_number;
 910
 911         for (i = 0; i < WM_SET_COUNT; i++) {
 912                 bw_params->wm_table.entries[i].wm_inst = i;
 913
 914                 if (i >= bw_params->clk_table.num_entries) {
 915                         bw_params->wm_table.entries[i].valid = false;
 916                         continue;
 917                 }
 918
 919                 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
 920                 bw_params->wm_table.entries[i].valid = true;
 921         }
 922
 923         if (bw_params->vram_type == LpDdr4MemType) {
 924                 /*
 925                  * WM set D will be re-purposed for memory retraining
 926                  */
 927                 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;
 928                 bw_params->wm_table.entries[WM_D].wm_inst = WM_D;
 929                 bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
 930                 bw_params->wm_table.entries[WM_D].valid = true;
 931         }
 932
 933 }
 934
 935 void rn_clk_mgr_construct(
 936                 struct dc_context *ctx,
 937                 struct clk_mgr_internal *clk_mgr,
 938                 struct pp_smu_funcs *pp_smu,
 939                 struct dccg *dccg)
 940 {
 941         struct dc_debug_options *debug = &ctx->dc->debug;
 942         struct dpm_clocks clock_table = { 0 };
 943         enum pp_smu_status status = 0;
 944         int is_green_sardine = 0;
 945
 946 #if defined(CONFIG_DRM_AMD_DC_DCN)
 947         is_green_sardine = ASICREV_IS_GREEN_SARDINE(ctx->asic_id.hw_internal_rev);
 948 #endif
 949
 950         clk_mgr->base.ctx = ctx;
 951         clk_mgr->base.funcs = &dcn21_funcs;
 952
 953         clk_mgr->pp_smu = pp_smu;
 954
 955         clk_mgr->dccg = dccg;
 956         clk_mgr->dfs_bypass_disp_clk = 0;
 957
 958         clk_mgr->dprefclk_ss_percentage = 0;
 959         clk_mgr->dprefclk_ss_divider = 1000;
 960         clk_mgr->ss_on_dprefclk = false;
 961         clk_mgr->dfs_ref_freq_khz = 48000;
 962
 963         clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr);
 964
 965         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
 966                 dcn21_funcs.update_clocks = dcn2_update_clocks_fpga;
 967                 clk_mgr->base.dentist_vco_freq_khz = 3600000;
 968         } else {
 969                 struct clk_log_info log_info = {0};
 970
 971                 clk_mgr->periodic_retraining_disabled = rn_vbios_smu_is_periodic_retraining_disabled(clk_mgr);
 972
 973                 /* SMU Version 55.51.0 and up no longer have an issue
 974                  * that needs to limit minimum dispclk */
 975                 if (clk_mgr->smu_ver >= SMU_VER_55_51_0)
 976                         debug->min_disp_clk_khz = 0;
 977
 978                 /* TODO: Check we get what we expect during bringup */
 979                 clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
 980
 981                 /* in case we don't get a value from the register, use default */
 982                 if (clk_mgr->base.dentist_vco_freq_khz == 0)
 983                         clk_mgr->base.dentist_vco_freq_khz = 3600000;
 984
 985                 if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) {
 986                         if (clk_mgr->periodic_retraining_disabled) {
 987                                 rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt;
 988                         } else {
 989                                 if (is_green_sardine)
 990                                         rn_bw_params.wm_table = lpddr4_wm_table_gs;
 991                                 else
 992                                         rn_bw_params.wm_table = lpddr4_wm_table_rn;
 993                         }
 994                 } else {
 995                         if (is_green_sardine)
 996                                 rn_bw_params.wm_table = ddr4_wm_table_gs;
 997                         else {
 998                                 if (ctx->dc->config.is_single_rank_dimm)
 999                                         rn_bw_params.wm_table = ddr4_1R_wm_table_rn;
1000                                 else
1001                                         rn_bw_params.wm_table = ddr4_wm_table_rn;
1002                         }
1003                 }
1004                 /* Saved clocks configured at boot for debug purposes */
1005                 rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
1006         }
1007
1008         clk_mgr->base.dprefclk_khz = 600000;
1009         dce_clock_read_ss_info(clk_mgr);
1010
1011
1012         clk_mgr->base.bw_params = &rn_bw_params;
1013
1014         if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) {
1015                 status = pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table);
1016
1017                 if (status == PP_SMU_RESULT_OK &&
1018                     ctx->dc_bios && ctx->dc_bios->integrated_info) {
1019                         rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);
1020                         /* treat memory config as single channel if memory is asymmetrics. */
1021                         if (ctx->dc->config.is_asymmetric_memory)
1022                                 clk_mgr->base.bw_params->num_channels = 1;
1023                 }
1024         }
1025
1026         if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) {
1027                 /* enable powerfeatures when displaycount goes to 0 */
1028                 rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
1029         }
1030 }
1031