drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <drm/drm_atomic.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_dp_mst_helper.h>
  29 #include <drm/drm_dp_helper.h>
  30 #include "dm_services.h"
  31 #include "amdgpu.h"
  32 #include "amdgpu_dm.h"
  33 #include "amdgpu_dm_mst_types.h"
  34
  35 #include "dc.h"
  36 #include "dm_helpers.h"
  37
  38 #include "dc_link_ddc.h"
  39
  40 #include "i2caux_interface.h"
  41 #include "dmub_cmd.h"
  42 #if defined(CONFIG_DEBUG_FS)
  43 #include "amdgpu_dm_debugfs.h"
  44 #endif
  45
  46 #if defined(CONFIG_DRM_AMD_DC_DCN)
  47 #include "dc/dcn20/dcn20_resource.h"
  48 #endif
  49
  50 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
  51                                   struct drm_dp_aux_msg *msg)
  52 {
  53         ssize_t result = 0;
  54         struct aux_payload payload;
  55         enum aux_return_code_type operation_result;
  56
  57         if (WARN_ON(msg->size > 16))
  58                 return -E2BIG;
  59
  60         payload.address = msg->address;
  61         payload.data = msg->buffer;
  62         payload.length = msg->size;
  63         payload.reply = &msg->reply;
  64         payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
  65         payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
  66         payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
  67         payload.defer_delay = 0;
  68
  69         result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
  70                                       &operation_result);
  71
  72         if (payload.write && result >= 0)
  73                 result = msg->size;
  74
  75         if (result < 0)
  76                 switch (operation_result) {
  77                 case AUX_RET_SUCCESS:
  78                         break;
  79                 case AUX_RET_ERROR_HPD_DISCON:
  80                 case AUX_RET_ERROR_UNKNOWN:
  81                 case AUX_RET_ERROR_INVALID_OPERATION:
  82                 case AUX_RET_ERROR_PROTOCOL_ERROR:
  83                         result = -EIO;
  84                         break;
  85                 case AUX_RET_ERROR_INVALID_REPLY:
  86                 case AUX_RET_ERROR_ENGINE_ACQUIRE:
  87                         result = -EBUSY;
  88                         break;
  89                 case AUX_RET_ERROR_TIMEOUT:
  90                         result = -ETIMEDOUT;
  91                         break;
  92                 }
  93
  94         return result;
  95 }
  96
  97 static void
  98 dm_dp_mst_connector_destroy(struct drm_connector *connector)
  99 {
 100         struct amdgpu_dm_connector *aconnector =
 101                 to_amdgpu_dm_connector(connector);
 102
 103         if (aconnector->dc_sink) {
 104                 dc_link_remove_remote_sink(aconnector->dc_link,
 105                                            aconnector->dc_sink);
 106                 dc_sink_release(aconnector->dc_sink);
 107         }
 108
 109         kfree(aconnector->edid);
 110
 111         drm_connector_cleanup(connector);
 112         drm_dp_mst_put_port_malloc(aconnector->port);
 113         kfree(aconnector);
 114 }
 115
 116 static int
 117 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
 118 {
 119         struct amdgpu_dm_connector *amdgpu_dm_connector =
 120                 to_amdgpu_dm_connector(connector);
 121         int r;
 122
 123         r = drm_dp_mst_connector_late_register(connector,
 124                                                amdgpu_dm_connector->port);
 125         if (r < 0)
 126                 return r;
 127
 128 #if defined(CONFIG_DEBUG_FS)
 129         connector_debugfs_init(amdgpu_dm_connector);
 130 #endif
 131
 132         return 0;
 133 }
 134
 135 static void
 136 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
 137 {
 138         struct amdgpu_dm_connector *amdgpu_dm_connector =
 139                 to_amdgpu_dm_connector(connector);
 140         struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
 141
 142         drm_dp_mst_connector_early_unregister(connector, port);
 143 }
 144
 145 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
 146         .fill_modes = drm_helper_probe_single_connector_modes,
 147         .destroy = dm_dp_mst_connector_destroy,
 148         .reset = amdgpu_dm_connector_funcs_reset,
 149         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
 150         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 151         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
 152         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
 153         .late_register = amdgpu_dm_mst_connector_late_register,
 154         .early_unregister = amdgpu_dm_mst_connector_early_unregister,
 155 };
 156
 157 #if defined(CONFIG_DRM_AMD_DC_DCN)
 158 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
 159 {
 160         struct dc_sink *dc_sink = aconnector->dc_sink;
 161         struct drm_dp_mst_port *port = aconnector->port;
 162         u8 dsc_caps[16] = { 0 };
 163
 164         aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
 165 #if defined(CONFIG_HP_HOOK_WORKAROUND)
 166         /*
 167          * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
 168          * because it only check the dsc/fec caps of the "port variable" and not the dock
 169          *
 170          * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
 171          *
 172          * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
 173          *
 174          */
 175
 176         if (!aconnector->dsc_aux && !port->parent->port_parent)
 177                 aconnector->dsc_aux = &aconnector->mst_port->dm_dp_aux.aux;
 178 #endif
 179         if (!aconnector->dsc_aux)
 180                 return false;
 181
 182         if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
 183                 return false;
 184
 185         if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
 186                                    dsc_caps, NULL,
 187                                    &dc_sink->dsc_caps.dsc_dec_caps))
 188                 return false;
 189
 190         return true;
 191 }
 192 #endif
 193
 194 static int dm_dp_mst_get_modes(struct drm_connector *connector)
 195 {
 196         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 197         int ret = 0;
 198
 199         if (!aconnector)
 200                 return drm_add_edid_modes(connector, NULL);
 201
 202         if (!aconnector->edid) {
 203                 struct edid *edid;
 204                 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
 205
 206                 if (!edid) {
 207                         drm_connector_update_edid_property(
 208                                 &aconnector->base,
 209                                 NULL);
 210                         return ret;
 211                 }
 212
 213                 aconnector->edid = edid;
 214         }
 215
 216         if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
 217                 dc_sink_release(aconnector->dc_sink);
 218                 aconnector->dc_sink = NULL;
 219         }
 220
 221         if (!aconnector->dc_sink) {
 222                 struct dc_sink *dc_sink;
 223                 struct dc_sink_init_data init_params = {
 224                                 .link = aconnector->dc_link,
 225                                 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
 226                 dc_sink = dc_link_add_remote_sink(
 227                         aconnector->dc_link,
 228                         (uint8_t *)aconnector->edid,
 229                         (aconnector->edid->extensions + 1) * EDID_LENGTH,
 230                         &init_params);
 231
 232                 if (!dc_sink) {
 233                         DRM_ERROR("Unable to add a remote sink\n");
 234                         return 0;
 235                 }
 236
 237                 dc_sink->priv = aconnector;
 238                 /* dc_link_add_remote_sink returns a new reference */
 239                 aconnector->dc_sink = dc_sink;
 240
 241                 if (aconnector->dc_sink) {
 242                         amdgpu_dm_update_freesync_caps(
 243                                         connector, aconnector->edid);
 244
 245 #if defined(CONFIG_DRM_AMD_DC_DCN)
 246                         if (!validate_dsc_caps_on_connector(aconnector))
 247                                 memset(&aconnector->dc_sink->dsc_caps,
 248                                        0, sizeof(aconnector->dc_sink->dsc_caps));
 249 #endif
 250                 }
 251         }
 252
 253         drm_connector_update_edid_property(
 254                                         &aconnector->base, aconnector->edid);
 255
 256         ret = drm_add_edid_modes(connector, aconnector->edid);
 257
 258         return ret;
 259 }
 260
 261 static struct drm_encoder *
 262 dm_mst_atomic_best_encoder(struct drm_connector *connector,
 263                            struct drm_atomic_state *state)
 264 {
 265         struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
 266                                                                                          connector);
 267         struct drm_device *dev = connector->dev;
 268         struct amdgpu_device *adev = drm_to_adev(dev);
 269         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);
 270
 271         return &adev->dm.mst_encoders[acrtc->crtc_id].base;
 272 }
 273
 274 static int
 275 dm_dp_mst_detect(struct drm_connector *connector,
 276                  struct drm_modeset_acquire_ctx *ctx, bool force)
 277 {
 278         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 279         struct amdgpu_dm_connector *master = aconnector->mst_port;
 280
 281         return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
 282                                       aconnector->port);
 283 }
 284
 285 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
 286                                 struct drm_atomic_state *state)
 287 {
 288         struct drm_connector_state *new_conn_state =
 289                         drm_atomic_get_new_connector_state(state, connector);
 290         struct drm_connector_state *old_conn_state =
 291                         drm_atomic_get_old_connector_state(state, connector);
 292         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 293         struct drm_crtc_state *new_crtc_state;
 294         struct drm_dp_mst_topology_mgr *mst_mgr;
 295         struct drm_dp_mst_port *mst_port;
 296
 297         mst_port = aconnector->port;
 298         mst_mgr = &aconnector->mst_port->mst_mgr;
 299
 300         if (!old_conn_state->crtc)
 301                 return 0;
 302
 303         if (new_conn_state->crtc) {
 304                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
 305                 if (!new_crtc_state ||
 306                     !drm_atomic_crtc_needs_modeset(new_crtc_state) ||
 307                     new_crtc_state->enable)
 308                         return 0;
 309                 }
 310
 311         return drm_dp_atomic_release_vcpi_slots(state,
 312                                                 mst_mgr,
 313                                                 mst_port);
 314 }
 315
 316 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
 317         .get_modes = dm_dp_mst_get_modes,
 318         .mode_valid = amdgpu_dm_connector_mode_valid,
 319         .atomic_best_encoder = dm_mst_atomic_best_encoder,
 320         .detect_ctx = dm_dp_mst_detect,
 321         .atomic_check = dm_dp_mst_atomic_check,
 322 };
 323
 324 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
 325 {
 326         drm_encoder_cleanup(encoder);
 327         kfree(encoder);
 328 }
 329
 330 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
 331         .destroy = amdgpu_dm_encoder_destroy,
 332 };
 333
 334 void
 335 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
 336 {
 337         struct drm_device *dev = adev_to_drm(adev);
 338         int i;
 339
 340         for (i = 0; i < adev->dm.display_indexes_num; i++) {
 341                 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
 342                 struct drm_encoder *encoder = &amdgpu_encoder->base;
 343
 344                 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
 345
 346                 drm_encoder_init(
 347                         dev,
 348                         &amdgpu_encoder->base,
 349                         &amdgpu_dm_encoder_funcs,
 350                         DRM_MODE_ENCODER_DPMST,
 351                         NULL);
 352
 353                 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
 354         }
 355 }
 356
 357 static struct drm_connector *
 358 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 359                         struct drm_dp_mst_port *port,
 360                         const char *pathprop)
 361 {
 362         struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
 363         struct drm_device *dev = master->base.dev;
 364         struct amdgpu_device *adev = drm_to_adev(dev);
 365         struct amdgpu_dm_connector *aconnector;
 366         struct drm_connector *connector;
 367         int i;
 368
 369         aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
 370         if (!aconnector)
 371                 return NULL;
 372
 373         connector = &aconnector->base;
 374         aconnector->port = port;
 375         aconnector->mst_port = master;
 376
 377         if (drm_connector_init(
 378                 dev,
 379                 connector,
 380                 &dm_dp_mst_connector_funcs,
 381                 DRM_MODE_CONNECTOR_DisplayPort)) {
 382                 kfree(aconnector);
 383                 return NULL;
 384         }
 385         drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
 386
 387         amdgpu_dm_connector_init_helper(
 388                 &adev->dm,
 389                 aconnector,
 390                 DRM_MODE_CONNECTOR_DisplayPort,
 391                 master->dc_link,
 392                 master->connector_id);
 393
 394         for (i = 0; i < adev->dm.display_indexes_num; i++) {
 395                 drm_connector_attach_encoder(&aconnector->base,
 396                                              &adev->dm.mst_encoders[i].base);
 397         }
 398
 399         connector->max_bpc_property = master->base.max_bpc_property;
 400         if (connector->max_bpc_property)
 401                 drm_connector_attach_max_bpc_property(connector, 8, 16);
 402
 403         connector->vrr_capable_property = master->base.vrr_capable_property;
 404         if (connector->vrr_capable_property)
 405                 drm_connector_attach_vrr_capable_property(connector);
 406
 407         drm_object_attach_property(
 408                 &connector->base,
 409                 dev->mode_config.path_property,
 410                 0);
 411         drm_object_attach_property(
 412                 &connector->base,
 413                 dev->mode_config.tile_property,
 414                 0);
 415
 416         drm_connector_set_path_property(connector, pathprop);
 417
 418         /*
 419          * Initialize connector state before adding the connectror to drm and
 420          * framebuffer lists
 421          */
 422         amdgpu_dm_connector_funcs_reset(connector);
 423
 424         drm_dp_mst_get_port_malloc(port);
 425
 426         return connector;
 427 }
 428
 429 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
 430         .add_connector = dm_dp_add_mst_connector,
 431 };
 432
 433 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 434                                        struct amdgpu_dm_connector *aconnector,
 435                                        int link_index)
 436 {
 437         aconnector->dm_dp_aux.aux.name =
 438                 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
 439                           link_index);
 440         aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
 441         aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
 442
 443         drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
 444         drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
 445                                       &aconnector->base);
 446
 447         if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
 448                 return;
 449
 450         aconnector->mst_mgr.cbs = &dm_mst_cbs;
 451         drm_dp_mst_topology_mgr_init(
 452                 &aconnector->mst_mgr,
 453                 adev_to_drm(dm->adev),
 454                 &aconnector->dm_dp_aux.aux,
 455                 16,
 456                 4,
 457                 aconnector->connector_id);
 458
 459         drm_connector_attach_dp_subconnector_property(&aconnector->base);
 460 }
 461
 462 int dm_mst_get_pbn_divider(struct dc_link *link)
 463 {
 464         if (!link)
 465                 return 0;
 466
 467         return dc_link_bandwidth_kbps(link,
 468                         dc_link_get_link_cap(link)) / (8 * 1000 * 54);
 469 }
 470
 471 #if defined(CONFIG_DRM_AMD_DC_DCN)
 472
 473 struct dsc_mst_fairness_params {
 474         struct dc_crtc_timing *timing;
 475         struct dc_sink *sink;
 476         struct dc_dsc_bw_range bw_range;
 477         bool compression_possible;
 478         struct drm_dp_mst_port *port;
 479         enum dsc_clock_force_state clock_force_enable;
 480         uint32_t num_slices_h;
 481         uint32_t num_slices_v;
 482         uint32_t bpp_overwrite;
 483 };
 484
 485 struct dsc_mst_fairness_vars {
 486         int pbn;
 487         bool dsc_enabled;
 488         int bpp_x16;
 489 };
 490
 491 static int kbps_to_peak_pbn(int kbps)
 492 {
 493         u64 peak_kbps = kbps;
 494
 495         peak_kbps *= 1006;
 496         peak_kbps = div_u64(peak_kbps, 1000);
 497         return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
 498 }
 499
 500 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
 501                 struct dsc_mst_fairness_vars *vars,
 502                 int count)
 503 {
 504         int i;
 505
 506         for (i = 0; i < count; i++) {
 507                 memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
 508                 if (vars[i].dsc_enabled && dc_dsc_compute_config(
 509                                         params[i].sink->ctx->dc->res_pool->dscs[0],
 510                                         &params[i].sink->dsc_caps.dsc_dec_caps,
 511                                         params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
 512                                         0,
 513                                         0,
 514                                         params[i].timing,
 515                                         &params[i].timing->dsc_cfg)) {
 516                         params[i].timing->flags.DSC = 1;
 517
 518                         if (params[i].bpp_overwrite)
 519                                 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
 520                         else
 521                                 params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
 522
 523                         if (params[i].num_slices_h)
 524                                 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
 525
 526                         if (params[i].num_slices_v)
 527                                 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
 528                 } else {
 529                         params[i].timing->flags.DSC = 0;
 530                 }
 531         }
 532 }
 533
 534 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
 535 {
 536         struct dc_dsc_config dsc_config;
 537         u64 kbps;
 538
 539         kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
 540         dc_dsc_compute_config(
 541                         param.sink->ctx->dc->res_pool->dscs[0],
 542                         &param.sink->dsc_caps.dsc_dec_caps,
 543                         param.sink->ctx->dc->debug.dsc_min_slice_height_override,
 544                         0,
 545                         (int) kbps, param.timing, &dsc_config);
 546
 547         return dsc_config.bits_per_pixel;
 548 }
 549
 550 static void increase_dsc_bpp(struct drm_atomic_state *state,
 551                              struct dc_link *dc_link,
 552                              struct dsc_mst_fairness_params *params,
 553                              struct dsc_mst_fairness_vars *vars,
 554                              int count)
 555 {
 556         int i;
 557         bool bpp_increased[MAX_PIPES];
 558         int initial_slack[MAX_PIPES];
 559         int min_initial_slack;
 560         int next_index;
 561         int remaining_to_increase = 0;
 562         int pbn_per_timeslot;
 563         int link_timeslots_used;
 564         int fair_pbn_alloc;
 565
 566         pbn_per_timeslot = dm_mst_get_pbn_divider(dc_link);
 567
 568         for (i = 0; i < count; i++) {
 569                 if (vars[i].dsc_enabled) {
 570                         initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
 571                         bpp_increased[i] = false;
 572                         remaining_to_increase += 1;
 573                 } else {
 574                         initial_slack[i] = 0;
 575                         bpp_increased[i] = true;
 576                 }
 577         }
 578
 579         while (remaining_to_increase) {
 580                 next_index = -1;
 581                 min_initial_slack = -1;
 582                 for (i = 0; i < count; i++) {
 583                         if (!bpp_increased[i]) {
 584                                 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
 585                                         min_initial_slack = initial_slack[i];
 586                                         next_index = i;
 587                                 }
 588                         }
 589                 }
 590
 591                 if (next_index == -1)
 592                         break;
 593
 594                 link_timeslots_used = 0;
 595
 596                 for (i = 0; i < count; i++)
 597                         link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
 598
 599                 fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
 600
 601                 if (initial_slack[next_index] > fair_pbn_alloc) {
 602                         vars[next_index].pbn += fair_pbn_alloc;
 603                         if (drm_dp_atomic_find_vcpi_slots(state,
 604                                                           params[next_index].port->mgr,
 605                                                           params[next_index].port,
 606                                                           vars[next_index].pbn,
 607                                                           pbn_per_timeslot) < 0)
 608                                 return;
 609                         if (!drm_dp_mst_atomic_check(state)) {
 610                                 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
 611                         } else {
 612                                 vars[next_index].pbn -= fair_pbn_alloc;
 613                                 if (drm_dp_atomic_find_vcpi_slots(state,
 614                                                                   params[next_index].port->mgr,
 615                                                                   params[next_index].port,
 616                                                                   vars[next_index].pbn,
 617                                                                   pbn_per_timeslot) < 0)
 618                                         return;
 619                         }
 620                 } else {
 621                         vars[next_index].pbn += initial_slack[next_index];
 622                         if (drm_dp_atomic_find_vcpi_slots(state,
 623                                                           params[next_index].port->mgr,
 624                                                           params[next_index].port,
 625                                                           vars[next_index].pbn,
 626                                                           pbn_per_timeslot) < 0)
 627                                 return;
 628                         if (!drm_dp_mst_atomic_check(state)) {
 629                                 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
 630                         } else {
 631                                 vars[next_index].pbn -= initial_slack[next_index];
 632                                 if (drm_dp_atomic_find_vcpi_slots(state,
 633                                                                   params[next_index].port->mgr,
 634                                                                   params[next_index].port,
 635                                                                   vars[next_index].pbn,
 636                                                                   pbn_per_timeslot) < 0)
 637                                         return;
 638                         }
 639                 }
 640
 641                 bpp_increased[next_index] = true;
 642                 remaining_to_increase--;
 643         }
 644 }
 645
 646 static void try_disable_dsc(struct drm_atomic_state *state,
 647                             struct dc_link *dc_link,
 648                             struct dsc_mst_fairness_params *params,
 649                             struct dsc_mst_fairness_vars *vars,
 650                             int count)
 651 {
 652         int i;
 653         bool tried[MAX_PIPES];
 654         int kbps_increase[MAX_PIPES];
 655         int max_kbps_increase;
 656         int next_index;
 657         int remaining_to_try = 0;
 658
 659         for (i = 0; i < count; i++) {
 660                 if (vars[i].dsc_enabled
 661                                 && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16
 662                                 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
 663                         kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
 664                         tried[i] = false;
 665                         remaining_to_try += 1;
 666                 } else {
 667                         kbps_increase[i] = 0;
 668                         tried[i] = true;
 669                 }
 670         }
 671
 672         while (remaining_to_try) {
 673                 next_index = -1;
 674                 max_kbps_increase = -1;
 675                 for (i = 0; i < count; i++) {
 676                         if (!tried[i]) {
 677                                 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
 678                                         max_kbps_increase = kbps_increase[i];
 679                                         next_index = i;
 680                                 }
 681                         }
 682                 }
 683
 684                 if (next_index == -1)
 685                         break;
 686
 687                 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
 688                 if (drm_dp_atomic_find_vcpi_slots(state,
 689                                                   params[next_index].port->mgr,
 690                                                   params[next_index].port,
 691                                                   vars[next_index].pbn,
 692                                                   dm_mst_get_pbn_divider(dc_link)) < 0)
 693                         return;
 694
 695                 if (!drm_dp_mst_atomic_check(state)) {
 696                         vars[next_index].dsc_enabled = false;
 697                         vars[next_index].bpp_x16 = 0;
 698                 } else {
 699                         vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
 700                         if (drm_dp_atomic_find_vcpi_slots(state,
 701                                                           params[next_index].port->mgr,
 702                                                           params[next_index].port,
 703                                                           vars[next_index].pbn,
 704                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 705                                 return;
 706                 }
 707
 708                 tried[next_index] = true;
 709                 remaining_to_try--;
 710         }
 711 }
 712
 713 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 714                                              struct dc_state *dc_state,
 715                                              struct dc_link *dc_link)
 716 {
 717         int i;
 718         struct dc_stream_state *stream;
 719         struct dsc_mst_fairness_params params[MAX_PIPES];
 720         struct dsc_mst_fairness_vars vars[MAX_PIPES];
 721         struct amdgpu_dm_connector *aconnector;
 722         int count = 0;
 723         bool debugfs_overwrite = false;
 724
 725         memset(params, 0, sizeof(params));
 726
 727         /* Set up params */
 728         for (i = 0; i < dc_state->stream_count; i++) {
 729                 struct dc_dsc_policy dsc_policy = {0};
 730
 731                 stream = dc_state->streams[i];
 732
 733                 if (stream->link != dc_link)
 734                         continue;
 735
 736                 stream->timing.flags.DSC = 0;
 737
 738                 params[count].timing = &stream->timing;
 739                 params[count].sink = stream->sink;
 740                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 741                 params[count].port = aconnector->port;
 742                 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
 743                 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
 744                         debugfs_overwrite = true;
 745                 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
 746                 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
 747                 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
 748                 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
 749                 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy);
 750                 if (!dc_dsc_compute_bandwidth_range(
 751                                 stream->sink->ctx->dc->res_pool->dscs[0],
 752                                 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
 753                                 dsc_policy.min_target_bpp * 16,
 754                                 dsc_policy.max_target_bpp * 16,
 755                                 &stream->sink->dsc_caps.dsc_dec_caps,
 756                                 &stream->timing, &params[count].bw_range))
 757                         params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
 758
 759                 count++;
 760         }
 761         /* Try no compression */
 762         for (i = 0; i < count; i++) {
 763                 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 764                 vars[i].dsc_enabled = false;
 765                 vars[i].bpp_x16 = 0;
 766                 if (drm_dp_atomic_find_vcpi_slots(state,
 767                                                  params[i].port->mgr,
 768                                                  params[i].port,
 769                                                  vars[i].pbn,
 770                                                  dm_mst_get_pbn_divider(dc_link)) < 0)
 771                         return false;
 772         }
 773         if (!drm_dp_mst_atomic_check(state) && !debugfs_overwrite) {
 774                 set_dsc_configs_from_fairness_vars(params, vars, count);
 775                 return true;
 776         }
 777
 778         /* Try max compression */
 779         for (i = 0; i < count; i++) {
 780                 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
 781                         vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
 782                         vars[i].dsc_enabled = true;
 783                         vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
 784                         if (drm_dp_atomic_find_vcpi_slots(state,
 785                                                           params[i].port->mgr,
 786                                                           params[i].port,
 787                                                           vars[i].pbn,
 788                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 789                                 return false;
 790                 } else {
 791                         vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 792                         vars[i].dsc_enabled = false;
 793                         vars[i].bpp_x16 = 0;
 794                         if (drm_dp_atomic_find_vcpi_slots(state,
 795                                                           params[i].port->mgr,
 796                                                           params[i].port,
 797                                                           vars[i].pbn,
 798                                                           dm_mst_get_pbn_divider(dc_link)) < 0)
 799                                 return false;
 800                 }
 801         }
 802         if (drm_dp_mst_atomic_check(state))
 803                 return false;
 804
 805         /* Optimize degree of compression */
 806         increase_dsc_bpp(state, dc_link, params, vars, count);
 807
 808         try_disable_dsc(state, dc_link, params, vars, count);
 809
 810         set_dsc_configs_from_fairness_vars(params, vars, count);
 811
 812         return true;
 813 }
 814
 815 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
 816                                        struct dc_state *dc_state)
 817 {
 818         int i, j;
 819         struct dc_stream_state *stream;
 820         bool computed_streams[MAX_PIPES];
 821         struct amdgpu_dm_connector *aconnector;
 822
 823         for (i = 0; i < dc_state->stream_count; i++)
 824                 computed_streams[i] = false;
 825
 826         for (i = 0; i < dc_state->stream_count; i++) {
 827                 stream = dc_state->streams[i];
 828
 829                 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
 830                         continue;
 831
 832                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 833
 834                 if (!aconnector || !aconnector->dc_sink)
 835                         continue;
 836
 837                 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
 838                         continue;
 839
 840                 if (computed_streams[i])
 841                         continue;
 842
 843                 if (dcn20_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
 844                         return false;
 845
 846                 mutex_lock(&aconnector->mst_mgr.lock);
 847                 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
 848                         mutex_unlock(&aconnector->mst_mgr.lock);
 849                         return false;
 850                 }
 851                 mutex_unlock(&aconnector->mst_mgr.lock);
 852
 853                 for (j = 0; j < dc_state->stream_count; j++) {
 854                         if (dc_state->streams[j]->link == stream->link)
 855                                 computed_streams[j] = true;
 856                 }
 857         }
 858
 859         for (i = 0; i < dc_state->stream_count; i++) {
 860                 stream = dc_state->streams[i];
 861
 862                 if (stream->timing.flags.DSC == 1)
 863                         if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK)
 864                                 return false;
 865         }
 866
 867         return true;
 868 }
 869
 870 #endif