2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <drm/drm_atomic.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_dp_mst_helper.h>
29 #include <drm/drm_dp_helper.h>
30 #include "dm_services.h"
32 #include "amdgpu_dm.h"
33 #include "amdgpu_dm_mst_types.h"
36 #include "dm_helpers.h"
38 #include "dc_link_ddc.h"
40 #include "i2caux_interface.h"
42 #if defined(CONFIG_DEBUG_FS)
43 #include "amdgpu_dm_debugfs.h"
46 #if defined(CONFIG_DRM_AMD_DC_DCN)
47 #include "dc/dcn20/dcn20_resource.h"
50 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
51 struct drm_dp_aux_msg *msg)
54 struct aux_payload payload;
55 enum aux_return_code_type operation_result;
57 if (WARN_ON(msg->size > 16))
60 payload.address = msg->address;
61 payload.data = msg->buffer;
62 payload.length = msg->size;
63 payload.reply = &msg->reply;
64 payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
65 payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
66 payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
67 payload.defer_delay = 0;
69 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
72 if (payload.write && result >= 0)
76 switch (operation_result) {
79 case AUX_RET_ERROR_HPD_DISCON:
80 case AUX_RET_ERROR_UNKNOWN:
81 case AUX_RET_ERROR_INVALID_OPERATION:
82 case AUX_RET_ERROR_PROTOCOL_ERROR:
85 case AUX_RET_ERROR_INVALID_REPLY:
86 case AUX_RET_ERROR_ENGINE_ACQUIRE:
89 case AUX_RET_ERROR_TIMEOUT:
98 dm_dp_mst_connector_destroy(struct drm_connector *connector)
100 struct amdgpu_dm_connector *aconnector =
101 to_amdgpu_dm_connector(connector);
103 if (aconnector->dc_sink) {
104 dc_link_remove_remote_sink(aconnector->dc_link,
105 aconnector->dc_sink);
106 dc_sink_release(aconnector->dc_sink);
109 kfree(aconnector->edid);
111 drm_connector_cleanup(connector);
112 drm_dp_mst_put_port_malloc(aconnector->port);
117 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
119 struct amdgpu_dm_connector *amdgpu_dm_connector =
120 to_amdgpu_dm_connector(connector);
123 r = drm_dp_mst_connector_late_register(connector,
124 amdgpu_dm_connector->port);
128 #if defined(CONFIG_DEBUG_FS)
129 connector_debugfs_init(amdgpu_dm_connector);
136 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
138 struct amdgpu_dm_connector *amdgpu_dm_connector =
139 to_amdgpu_dm_connector(connector);
140 struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
142 drm_dp_mst_connector_early_unregister(connector, port);
145 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
146 .fill_modes = drm_helper_probe_single_connector_modes,
147 .destroy = dm_dp_mst_connector_destroy,
148 .reset = amdgpu_dm_connector_funcs_reset,
149 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
150 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
151 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
152 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
153 .late_register = amdgpu_dm_mst_connector_late_register,
154 .early_unregister = amdgpu_dm_mst_connector_early_unregister,
157 #if defined(CONFIG_DRM_AMD_DC_DCN)
158 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
160 struct dc_sink *dc_sink = aconnector->dc_sink;
161 struct drm_dp_mst_port *port = aconnector->port;
162 u8 dsc_caps[16] = { 0 };
164 aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
165 #if defined(CONFIG_HP_HOOK_WORKAROUND)
167 * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
168 * because it only check the dsc/fec caps of the "port variable" and not the dock
170 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
172 * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
176 if (!aconnector->dsc_aux && !port->parent->port_parent)
177 aconnector->dsc_aux = &aconnector->mst_port->dm_dp_aux.aux;
179 if (!aconnector->dsc_aux)
182 if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
185 if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
187 &dc_sink->dsc_caps.dsc_dec_caps))
194 static int dm_dp_mst_get_modes(struct drm_connector *connector)
196 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
200 return drm_add_edid_modes(connector, NULL);
202 if (!aconnector->edid) {
204 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
207 drm_connector_update_edid_property(
213 aconnector->edid = edid;
216 if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
217 dc_sink_release(aconnector->dc_sink);
218 aconnector->dc_sink = NULL;
221 if (!aconnector->dc_sink) {
222 struct dc_sink *dc_sink;
223 struct dc_sink_init_data init_params = {
224 .link = aconnector->dc_link,
225 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
226 dc_sink = dc_link_add_remote_sink(
228 (uint8_t *)aconnector->edid,
229 (aconnector->edid->extensions + 1) * EDID_LENGTH,
233 DRM_ERROR("Unable to add a remote sink\n");
237 dc_sink->priv = aconnector;
238 /* dc_link_add_remote_sink returns a new reference */
239 aconnector->dc_sink = dc_sink;
241 if (aconnector->dc_sink) {
242 amdgpu_dm_update_freesync_caps(
243 connector, aconnector->edid);
245 #if defined(CONFIG_DRM_AMD_DC_DCN)
246 if (!validate_dsc_caps_on_connector(aconnector))
247 memset(&aconnector->dc_sink->dsc_caps,
248 0, sizeof(aconnector->dc_sink->dsc_caps));
253 drm_connector_update_edid_property(
254 &aconnector->base, aconnector->edid);
256 ret = drm_add_edid_modes(connector, aconnector->edid);
261 static struct drm_encoder *
262 dm_mst_atomic_best_encoder(struct drm_connector *connector,
263 struct drm_atomic_state *state)
265 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
267 struct drm_device *dev = connector->dev;
268 struct amdgpu_device *adev = drm_to_adev(dev);
269 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);
271 return &adev->dm.mst_encoders[acrtc->crtc_id].base;
275 dm_dp_mst_detect(struct drm_connector *connector,
276 struct drm_modeset_acquire_ctx *ctx, bool force)
278 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
279 struct amdgpu_dm_connector *master = aconnector->mst_port;
281 return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
285 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
286 struct drm_atomic_state *state)
288 struct drm_connector_state *new_conn_state =
289 drm_atomic_get_new_connector_state(state, connector);
290 struct drm_connector_state *old_conn_state =
291 drm_atomic_get_old_connector_state(state, connector);
292 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
293 struct drm_crtc_state *new_crtc_state;
294 struct drm_dp_mst_topology_mgr *mst_mgr;
295 struct drm_dp_mst_port *mst_port;
297 mst_port = aconnector->port;
298 mst_mgr = &aconnector->mst_port->mst_mgr;
300 if (!old_conn_state->crtc)
303 if (new_conn_state->crtc) {
304 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
305 if (!new_crtc_state ||
306 !drm_atomic_crtc_needs_modeset(new_crtc_state) ||
307 new_crtc_state->enable)
311 return drm_dp_atomic_release_vcpi_slots(state,
316 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
317 .get_modes = dm_dp_mst_get_modes,
318 .mode_valid = amdgpu_dm_connector_mode_valid,
319 .atomic_best_encoder = dm_mst_atomic_best_encoder,
320 .detect_ctx = dm_dp_mst_detect,
321 .atomic_check = dm_dp_mst_atomic_check,
324 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
326 drm_encoder_cleanup(encoder);
330 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
331 .destroy = amdgpu_dm_encoder_destroy,
335 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
337 struct drm_device *dev = adev_to_drm(adev);
340 for (i = 0; i < adev->dm.display_indexes_num; i++) {
341 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
342 struct drm_encoder *encoder = &amdgpu_encoder->base;
344 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
348 &amdgpu_encoder->base,
349 &amdgpu_dm_encoder_funcs,
350 DRM_MODE_ENCODER_DPMST,
353 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
357 static struct drm_connector *
358 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
359 struct drm_dp_mst_port *port,
360 const char *pathprop)
362 struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
363 struct drm_device *dev = master->base.dev;
364 struct amdgpu_device *adev = drm_to_adev(dev);
365 struct amdgpu_dm_connector *aconnector;
366 struct drm_connector *connector;
369 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
373 connector = &aconnector->base;
374 aconnector->port = port;
375 aconnector->mst_port = master;
377 if (drm_connector_init(
380 &dm_dp_mst_connector_funcs,
381 DRM_MODE_CONNECTOR_DisplayPort)) {
385 drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
387 amdgpu_dm_connector_init_helper(
390 DRM_MODE_CONNECTOR_DisplayPort,
392 master->connector_id);
394 for (i = 0; i < adev->dm.display_indexes_num; i++) {
395 drm_connector_attach_encoder(&aconnector->base,
396 &adev->dm.mst_encoders[i].base);
399 connector->max_bpc_property = master->base.max_bpc_property;
400 if (connector->max_bpc_property)
401 drm_connector_attach_max_bpc_property(connector, 8, 16);
403 connector->vrr_capable_property = master->base.vrr_capable_property;
404 if (connector->vrr_capable_property)
405 drm_connector_attach_vrr_capable_property(connector);
407 drm_object_attach_property(
409 dev->mode_config.path_property,
411 drm_object_attach_property(
413 dev->mode_config.tile_property,
416 drm_connector_set_path_property(connector, pathprop);
419 * Initialize connector state before adding the connectror to drm and
422 amdgpu_dm_connector_funcs_reset(connector);
424 drm_dp_mst_get_port_malloc(port);
429 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
430 .add_connector = dm_dp_add_mst_connector,
433 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
434 struct amdgpu_dm_connector *aconnector,
437 aconnector->dm_dp_aux.aux.name =
438 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
440 aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
441 aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
443 drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
444 drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
447 if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
450 aconnector->mst_mgr.cbs = &dm_mst_cbs;
451 drm_dp_mst_topology_mgr_init(
452 &aconnector->mst_mgr,
453 adev_to_drm(dm->adev),
454 &aconnector->dm_dp_aux.aux,
457 aconnector->connector_id);
459 drm_connector_attach_dp_subconnector_property(&aconnector->base);
462 int dm_mst_get_pbn_divider(struct dc_link *link)
467 return dc_link_bandwidth_kbps(link,
468 dc_link_get_link_cap(link)) / (8 * 1000 * 54);
471 #if defined(CONFIG_DRM_AMD_DC_DCN)
473 struct dsc_mst_fairness_params {
474 struct dc_crtc_timing *timing;
475 struct dc_sink *sink;
476 struct dc_dsc_bw_range bw_range;
477 bool compression_possible;
478 struct drm_dp_mst_port *port;
479 enum dsc_clock_force_state clock_force_enable;
480 uint32_t num_slices_h;
481 uint32_t num_slices_v;
482 uint32_t bpp_overwrite;
485 struct dsc_mst_fairness_vars {
491 static int kbps_to_peak_pbn(int kbps)
493 u64 peak_kbps = kbps;
496 peak_kbps = div_u64(peak_kbps, 1000);
497 return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
500 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
501 struct dsc_mst_fairness_vars *vars,
506 for (i = 0; i < count; i++) {
507 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
508 if (vars[i].dsc_enabled && dc_dsc_compute_config(
509 params[i].sink->ctx->dc->res_pool->dscs[0],
510 ¶ms[i].sink->dsc_caps.dsc_dec_caps,
511 params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
515 ¶ms[i].timing->dsc_cfg)) {
516 params[i].timing->flags.DSC = 1;
518 if (params[i].bpp_overwrite)
519 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
521 params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
523 if (params[i].num_slices_h)
524 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
526 if (params[i].num_slices_v)
527 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
529 params[i].timing->flags.DSC = 0;
534 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
536 struct dc_dsc_config dsc_config;
539 kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
540 dc_dsc_compute_config(
541 param.sink->ctx->dc->res_pool->dscs[0],
542 ¶m.sink->dsc_caps.dsc_dec_caps,
543 param.sink->ctx->dc->debug.dsc_min_slice_height_override,
545 (int) kbps, param.timing, &dsc_config);
547 return dsc_config.bits_per_pixel;
550 static void increase_dsc_bpp(struct drm_atomic_state *state,
551 struct dc_link *dc_link,
552 struct dsc_mst_fairness_params *params,
553 struct dsc_mst_fairness_vars *vars,
557 bool bpp_increased[MAX_PIPES];
558 int initial_slack[MAX_PIPES];
559 int min_initial_slack;
561 int remaining_to_increase = 0;
562 int pbn_per_timeslot;
563 int link_timeslots_used;
566 pbn_per_timeslot = dm_mst_get_pbn_divider(dc_link);
568 for (i = 0; i < count; i++) {
569 if (vars[i].dsc_enabled) {
570 initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn;
571 bpp_increased[i] = false;
572 remaining_to_increase += 1;
574 initial_slack[i] = 0;
575 bpp_increased[i] = true;
579 while (remaining_to_increase) {
581 min_initial_slack = -1;
582 for (i = 0; i < count; i++) {
583 if (!bpp_increased[i]) {
584 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
585 min_initial_slack = initial_slack[i];
591 if (next_index == -1)
594 link_timeslots_used = 0;
596 for (i = 0; i < count; i++)
597 link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot);
599 fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot;
601 if (initial_slack[next_index] > fair_pbn_alloc) {
602 vars[next_index].pbn += fair_pbn_alloc;
603 if (drm_dp_atomic_find_vcpi_slots(state,
604 params[next_index].port->mgr,
605 params[next_index].port,
606 vars[next_index].pbn,
607 pbn_per_timeslot) < 0)
609 if (!drm_dp_mst_atomic_check(state)) {
610 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
612 vars[next_index].pbn -= fair_pbn_alloc;
613 if (drm_dp_atomic_find_vcpi_slots(state,
614 params[next_index].port->mgr,
615 params[next_index].port,
616 vars[next_index].pbn,
617 pbn_per_timeslot) < 0)
621 vars[next_index].pbn += initial_slack[next_index];
622 if (drm_dp_atomic_find_vcpi_slots(state,
623 params[next_index].port->mgr,
624 params[next_index].port,
625 vars[next_index].pbn,
626 pbn_per_timeslot) < 0)
628 if (!drm_dp_mst_atomic_check(state)) {
629 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
631 vars[next_index].pbn -= initial_slack[next_index];
632 if (drm_dp_atomic_find_vcpi_slots(state,
633 params[next_index].port->mgr,
634 params[next_index].port,
635 vars[next_index].pbn,
636 pbn_per_timeslot) < 0)
641 bpp_increased[next_index] = true;
642 remaining_to_increase--;
646 static void try_disable_dsc(struct drm_atomic_state *state,
647 struct dc_link *dc_link,
648 struct dsc_mst_fairness_params *params,
649 struct dsc_mst_fairness_vars *vars,
653 bool tried[MAX_PIPES];
654 int kbps_increase[MAX_PIPES];
655 int max_kbps_increase;
657 int remaining_to_try = 0;
659 for (i = 0; i < count; i++) {
660 if (vars[i].dsc_enabled
661 && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16
662 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
663 kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
665 remaining_to_try += 1;
667 kbps_increase[i] = 0;
672 while (remaining_to_try) {
674 max_kbps_increase = -1;
675 for (i = 0; i < count; i++) {
677 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
678 max_kbps_increase = kbps_increase[i];
684 if (next_index == -1)
687 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
688 if (drm_dp_atomic_find_vcpi_slots(state,
689 params[next_index].port->mgr,
690 params[next_index].port,
691 vars[next_index].pbn,
692 dm_mst_get_pbn_divider(dc_link)) < 0)
695 if (!drm_dp_mst_atomic_check(state)) {
696 vars[next_index].dsc_enabled = false;
697 vars[next_index].bpp_x16 = 0;
699 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
700 if (drm_dp_atomic_find_vcpi_slots(state,
701 params[next_index].port->mgr,
702 params[next_index].port,
703 vars[next_index].pbn,
704 dm_mst_get_pbn_divider(dc_link)) < 0)
708 tried[next_index] = true;
713 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
714 struct dc_state *dc_state,
715 struct dc_link *dc_link)
718 struct dc_stream_state *stream;
719 struct dsc_mst_fairness_params params[MAX_PIPES];
720 struct dsc_mst_fairness_vars vars[MAX_PIPES];
721 struct amdgpu_dm_connector *aconnector;
723 bool debugfs_overwrite = false;
725 memset(params, 0, sizeof(params));
728 for (i = 0; i < dc_state->stream_count; i++) {
729 struct dc_dsc_policy dsc_policy = {0};
731 stream = dc_state->streams[i];
733 if (stream->link != dc_link)
736 stream->timing.flags.DSC = 0;
738 params[count].timing = &stream->timing;
739 params[count].sink = stream->sink;
740 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
741 params[count].port = aconnector->port;
742 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
743 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
744 debugfs_overwrite = true;
745 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
746 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
747 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
748 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
749 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy);
750 if (!dc_dsc_compute_bandwidth_range(
751 stream->sink->ctx->dc->res_pool->dscs[0],
752 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
753 dsc_policy.min_target_bpp * 16,
754 dsc_policy.max_target_bpp * 16,
755 &stream->sink->dsc_caps.dsc_dec_caps,
756 &stream->timing, ¶ms[count].bw_range))
757 params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
761 /* Try no compression */
762 for (i = 0; i < count; i++) {
763 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
764 vars[i].dsc_enabled = false;
766 if (drm_dp_atomic_find_vcpi_slots(state,
770 dm_mst_get_pbn_divider(dc_link)) < 0)
773 if (!drm_dp_mst_atomic_check(state) && !debugfs_overwrite) {
774 set_dsc_configs_from_fairness_vars(params, vars, count);
778 /* Try max compression */
779 for (i = 0; i < count; i++) {
780 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
781 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
782 vars[i].dsc_enabled = true;
783 vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
784 if (drm_dp_atomic_find_vcpi_slots(state,
788 dm_mst_get_pbn_divider(dc_link)) < 0)
791 vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
792 vars[i].dsc_enabled = false;
794 if (drm_dp_atomic_find_vcpi_slots(state,
798 dm_mst_get_pbn_divider(dc_link)) < 0)
802 if (drm_dp_mst_atomic_check(state))
805 /* Optimize degree of compression */
806 increase_dsc_bpp(state, dc_link, params, vars, count);
808 try_disable_dsc(state, dc_link, params, vars, count);
810 set_dsc_configs_from_fairness_vars(params, vars, count);
815 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
816 struct dc_state *dc_state)
819 struct dc_stream_state *stream;
820 bool computed_streams[MAX_PIPES];
821 struct amdgpu_dm_connector *aconnector;
823 for (i = 0; i < dc_state->stream_count; i++)
824 computed_streams[i] = false;
826 for (i = 0; i < dc_state->stream_count; i++) {
827 stream = dc_state->streams[i];
829 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
832 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
834 if (!aconnector || !aconnector->dc_sink)
837 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
840 if (computed_streams[i])
843 if (dcn20_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
846 mutex_lock(&aconnector->mst_mgr.lock);
847 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
848 mutex_unlock(&aconnector->mst_mgr.lock);
851 mutex_unlock(&aconnector->mst_mgr.lock);
853 for (j = 0; j < dc_state->stream_count; j++) {
854 if (dc_state->streams[j]->link == stream->link)
855 computed_streams[j] = true;
859 for (i = 0; i < dc_state->stream_count; i++) {
860 stream = dc_state->streams[i];
862 if (stream->timing.flags.DSC == 1)
863 if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK)