drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <drm/display/drm_dp_helper.h>
  27 #include <drm/display/drm_dp_mst_helper.h>
  28 #include <drm/drm_atomic.h>
  29 #include <drm/drm_atomic_helper.h>
  30 #include "dm_services.h"
  31 #include "amdgpu.h"
  32 #include "amdgpu_dm.h"
  33 #include "amdgpu_dm_mst_types.h"
  34 #include "amdgpu_dm_hdcp.h"
  35
  36 #include "dc.h"
  37 #include "dm_helpers.h"
  38
  39 #include "ddc_service_types.h"
  40 #include "dpcd_defs.h"
  41
  42 #include "dmub_cmd.h"
  43 #if defined(CONFIG_DEBUG_FS)
  44 #include "amdgpu_dm_debugfs.h"
  45 #endif
  46
  47 #include "dc/dcn20/dcn20_resource.h"
  48
  49 #define PEAK_FACTOR_X1000 1006
  50
  51 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
  52                                   struct drm_dp_aux_msg *msg)
  53 {
  54         ssize_t result = 0;
  55         struct aux_payload payload;
  56         enum aux_return_code_type operation_result;
  57         struct amdgpu_device *adev;
  58         struct ddc_service *ddc;
  59
  60         if (WARN_ON(msg->size > 16))
  61                 return -E2BIG;
  62
  63         payload.address = msg->address;
  64         payload.data = msg->buffer;
  65         payload.length = msg->size;
  66         payload.reply = &msg->reply;
  67         payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
  68         payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
  69         payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
  70         payload.write_status_update =
  71                         (msg->request & DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0;
  72         payload.defer_delay = 0;
  73
  74         result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
  75                                       &operation_result);
  76
  77         /*
  78          * w/a on certain intel platform where hpd is unexpected to pull low during
  79          * 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON
  80          * aux transaction is succuess in such case, therefore bypass the error
  81          */
  82         ddc = TO_DM_AUX(aux)->ddc_service;
  83         adev = ddc->ctx->driver_context;
  84         if (adev->dm.aux_hpd_discon_quirk) {
  85                 if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE &&
  86                         operation_result == AUX_RET_ERROR_HPD_DISCON) {
  87                         result = 0;
  88                         operation_result = AUX_RET_SUCCESS;
  89                 }
  90         }
  91
  92         if (payload.write && result >= 0)
  93                 result = msg->size;
  94
  95         if (result < 0)
  96                 switch (operation_result) {
  97                 case AUX_RET_SUCCESS:
  98                         break;
  99                 case AUX_RET_ERROR_HPD_DISCON:
 100                 case AUX_RET_ERROR_UNKNOWN:
 101                 case AUX_RET_ERROR_INVALID_OPERATION:
 102                 case AUX_RET_ERROR_PROTOCOL_ERROR:
 103                         result = -EIO;
 104                         break;
 105                 case AUX_RET_ERROR_INVALID_REPLY:
 106                 case AUX_RET_ERROR_ENGINE_ACQUIRE:
 107                         result = -EBUSY;
 108                         break;
 109                 case AUX_RET_ERROR_TIMEOUT:
 110                         result = -ETIMEDOUT;
 111                         break;
 112                 }
 113
 114         return result;
 115 }
 116
 117 static void
 118 dm_dp_mst_connector_destroy(struct drm_connector *connector)
 119 {
 120         struct amdgpu_dm_connector *aconnector =
 121                 to_amdgpu_dm_connector(connector);
 122
 123         if (aconnector->dc_sink) {
 124                 dc_link_remove_remote_sink(aconnector->dc_link,
 125                                            aconnector->dc_sink);
 126                 dc_sink_release(aconnector->dc_sink);
 127         }
 128
 129         kfree(aconnector->edid);
 130
 131         drm_connector_cleanup(connector);
 132         drm_dp_mst_put_port_malloc(aconnector->mst_output_port);
 133         kfree(aconnector);
 134 }
 135
 136 static int
 137 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
 138 {
 139         struct amdgpu_dm_connector *amdgpu_dm_connector =
 140                 to_amdgpu_dm_connector(connector);
 141         int r;
 142
 143         r = drm_dp_mst_connector_late_register(connector,
 144                                                amdgpu_dm_connector->mst_output_port);
 145         if (r < 0)
 146                 return r;
 147
 148 #if defined(CONFIG_DEBUG_FS)
 149         connector_debugfs_init(amdgpu_dm_connector);
 150 #endif
 151
 152         return 0;
 153 }
 154
 155 static void
 156 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
 157 {
 158         struct amdgpu_dm_connector *aconnector =
 159                 to_amdgpu_dm_connector(connector);
 160         struct drm_dp_mst_port *port = aconnector->mst_output_port;
 161         struct amdgpu_dm_connector *root = aconnector->mst_root;
 162         struct dc_link *dc_link = aconnector->dc_link;
 163         struct dc_sink *dc_sink = aconnector->dc_sink;
 164
 165         drm_dp_mst_connector_early_unregister(connector, port);
 166
 167         /*
 168          * Release dc_sink for connector which its attached port is
 169          * no longer in the mst topology
 170          */
 171         drm_modeset_lock(&root->mst_mgr.base.lock, NULL);
 172         if (dc_sink) {
 173                 if (dc_link->sink_count)
 174                         dc_link_remove_remote_sink(dc_link, dc_sink);
 175
 176                 DC_LOG_MST("DM_MST: remove remote sink 0x%p, %d remaining\n",
 177                         dc_sink, dc_link->sink_count);
 178
 179                 dc_sink_release(dc_sink);
 180                 aconnector->dc_sink = NULL;
 181                 aconnector->edid = NULL;
 182         }
 183
 184         aconnector->mst_status = MST_STATUS_DEFAULT;
 185         drm_modeset_unlock(&root->mst_mgr.base.lock);
 186 }
 187
 188 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
 189         .fill_modes = drm_helper_probe_single_connector_modes,
 190         .destroy = dm_dp_mst_connector_destroy,
 191         .reset = amdgpu_dm_connector_funcs_reset,
 192         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
 193         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 194         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
 195         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
 196         .late_register = amdgpu_dm_mst_connector_late_register,
 197         .early_unregister = amdgpu_dm_mst_connector_early_unregister,
 198 };
 199
 200 bool needs_dsc_aux_workaround(struct dc_link *link)
 201 {
 202         if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
 203             (link->dpcd_caps.dpcd_rev.raw == DPCD_REV_14 || link->dpcd_caps.dpcd_rev.raw == DPCD_REV_12) &&
 204             link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2)
 205                 return true;
 206
 207         return false;
 208 }
 209
 210 static bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_mst_port *port)
 211 {
 212         u8 branch_vendor_data[4] = { 0 }; // Vendor data 0x50C ~ 0x50F
 213
 214         if (drm_dp_dpcd_read(port->mgr->aux, DP_BRANCH_VENDOR_SPECIFIC_START, &branch_vendor_data, 4) == 4) {
 215                 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
 216                                 IS_SYNAPTICS_CASCADED_PANAMERA(link->dpcd_caps.branch_dev_name, branch_vendor_data)) {
 217                         DRM_INFO("Synaptics Cascaded MST hub\n");
 218                         return true;
 219                 }
 220         }
 221
 222         return false;
 223 }
 224
 225 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
 226 {
 227         struct dc_sink *dc_sink = aconnector->dc_sink;
 228         struct drm_dp_mst_port *port = aconnector->mst_output_port;
 229         u8 dsc_caps[16] = { 0 };
 230         u8 dsc_branch_dec_caps_raw[3] = { 0 };  // DSC branch decoder caps 0xA0 ~ 0xA2
 231         u8 *dsc_branch_dec_caps = NULL;
 232
 233         aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
 234
 235         /*
 236          * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
 237          * because it only check the dsc/fec caps of the "port variable" and not the dock
 238          *
 239          * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
 240          *
 241          * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
 242          *
 243          */
 244         if (!aconnector->dsc_aux && !port->parent->port_parent &&
 245             needs_dsc_aux_workaround(aconnector->dc_link))
 246                 aconnector->dsc_aux = &aconnector->mst_root->dm_dp_aux.aux;
 247
 248         /* synaptics cascaded MST hub case */
 249         if (!aconnector->dsc_aux && is_synaptics_cascaded_panamera(aconnector->dc_link, port))
 250                 aconnector->dsc_aux = port->mgr->aux;
 251
 252         if (!aconnector->dsc_aux)
 253                 return false;
 254
 255         if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
 256                 return false;
 257
 258         if (drm_dp_dpcd_read(aconnector->dsc_aux,
 259                         DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3)
 260                 dsc_branch_dec_caps = dsc_branch_dec_caps_raw;
 261
 262         if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
 263                                   dsc_caps, dsc_branch_dec_caps,
 264                                   &dc_sink->dsc_caps.dsc_dec_caps))
 265                 return false;
 266
 267         return true;
 268 }
 269
 270 static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector)
 271 {
 272         union dp_downstream_port_present ds_port_present;
 273
 274         if (!aconnector->dsc_aux)
 275                 return false;
 276
 277         if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DOWNSTREAMPORT_PRESENT, &ds_port_present, 1) < 0) {
 278                 DRM_INFO("Failed to read downstream_port_present 0x05 from DFP of branch device\n");
 279                 return false;
 280         }
 281
 282         aconnector->mst_downstream_port_present = ds_port_present;
 283         DRM_INFO("Downstream port present %d, type %d\n",
 284                         ds_port_present.fields.PORT_PRESENT, ds_port_present.fields.PORT_TYPE);
 285
 286         return true;
 287 }
 288
 289 static int dm_dp_mst_get_modes(struct drm_connector *connector)
 290 {
 291         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 292         int ret = 0;
 293
 294         if (!aconnector)
 295                 return drm_add_edid_modes(connector, NULL);
 296
 297         if (!aconnector->edid) {
 298                 struct edid *edid;
 299
 300                 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_root->mst_mgr, aconnector->mst_output_port);
 301
 302                 if (!edid) {
 303                         amdgpu_dm_set_mst_status(&aconnector->mst_status,
 304                         MST_REMOTE_EDID, false);
 305
 306                         drm_connector_update_edid_property(
 307                                 &aconnector->base,
 308                                 NULL);
 309
 310                         DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name);
 311                         if (!aconnector->dc_sink) {
 312                                 struct dc_sink *dc_sink;
 313                                 struct dc_sink_init_data init_params = {
 314                                         .link = aconnector->dc_link,
 315                                         .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
 316
 317                                 dc_sink = dc_link_add_remote_sink(
 318                                         aconnector->dc_link,
 319                                         NULL,
 320                                         0,
 321                                         &init_params);
 322
 323                                 if (!dc_sink) {
 324                                         DRM_ERROR("Unable to add a remote sink\n");
 325                                         return 0;
 326                                 }
 327
 328                                 DC_LOG_MST("DM_MST: add remote sink 0x%p, %d remaining\n",
 329                                         dc_sink, aconnector->dc_link->sink_count);
 330
 331                                 dc_sink->priv = aconnector;
 332                                 aconnector->dc_sink = dc_sink;
 333                         }
 334
 335                         return ret;
 336                 }
 337
 338                 aconnector->edid = edid;
 339                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 340                         MST_REMOTE_EDID, true);
 341         }
 342
 343         if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
 344                 dc_sink_release(aconnector->dc_sink);
 345                 aconnector->dc_sink = NULL;
 346         }
 347
 348         if (!aconnector->dc_sink) {
 349                 struct dc_sink *dc_sink;
 350                 struct dc_sink_init_data init_params = {
 351                                 .link = aconnector->dc_link,
 352                                 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
 353                 dc_sink = dc_link_add_remote_sink(
 354                         aconnector->dc_link,
 355                         (uint8_t *)aconnector->edid,
 356                         (aconnector->edid->extensions + 1) * EDID_LENGTH,
 357                         &init_params);
 358
 359                 if (!dc_sink) {
 360                         DRM_ERROR("Unable to add a remote sink\n");
 361                         return 0;
 362                 }
 363
 364                 DC_LOG_MST("DM_MST: add remote sink 0x%p, %d remaining\n",
 365                         dc_sink, aconnector->dc_link->sink_count);
 366
 367                 dc_sink->priv = aconnector;
 368                 /* dc_link_add_remote_sink returns a new reference */
 369                 aconnector->dc_sink = dc_sink;
 370
 371                 /* when display is unplugged from mst hub, connctor will be
 372                  * destroyed within dm_dp_mst_connector_destroy. connector
 373                  * hdcp perperties, like type, undesired, desired, enabled,
 374                  * will be lost. So, save hdcp properties into hdcp_work within
 375                  * amdgpu_dm_atomic_commit_tail. if the same display is
 376                  * plugged back with same display index, its hdcp properties
 377                  * will be retrieved from hdcp_work within dm_dp_mst_get_modes
 378                  */
 379                 if (aconnector->dc_sink && connector->state) {
 380                         struct drm_device *dev = connector->dev;
 381                         struct amdgpu_device *adev = drm_to_adev(dev);
 382
 383                         if (adev->dm.hdcp_workqueue) {
 384                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
 385                                 struct hdcp_workqueue *hdcp_w =
 386                                         &hdcp_work[aconnector->dc_link->link_index];
 387
 388                                 connector->state->hdcp_content_type =
 389                                 hdcp_w->hdcp_content_type[connector->index];
 390                                 connector->state->content_protection =
 391                                 hdcp_w->content_protection[connector->index];
 392                         }
 393                 }
 394
 395                 if (aconnector->dc_sink) {
 396                         amdgpu_dm_update_freesync_caps(
 397                                         connector, aconnector->edid);
 398
 399                         if (!validate_dsc_caps_on_connector(aconnector))
 400                                 memset(&aconnector->dc_sink->dsc_caps,
 401                                        0, sizeof(aconnector->dc_sink->dsc_caps));
 402
 403                         if (!retrieve_downstream_port_device(aconnector))
 404                                 memset(&aconnector->mst_downstream_port_present,
 405                                         0, sizeof(aconnector->mst_downstream_port_present));
 406                 }
 407         }
 408
 409         drm_connector_update_edid_property(
 410                                         &aconnector->base, aconnector->edid);
 411
 412         ret = drm_add_edid_modes(connector, aconnector->edid);
 413
 414         return ret;
 415 }
 416
 417 static struct drm_encoder *
 418 dm_mst_atomic_best_encoder(struct drm_connector *connector,
 419                            struct drm_atomic_state *state)
 420 {
 421         struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
 422                                                                                          connector);
 423         struct drm_device *dev = connector->dev;
 424         struct amdgpu_device *adev = drm_to_adev(dev);
 425         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);
 426
 427         return &adev->dm.mst_encoders[acrtc->crtc_id].base;
 428 }
 429
 430 static int
 431 dm_dp_mst_detect(struct drm_connector *connector,
 432                  struct drm_modeset_acquire_ctx *ctx, bool force)
 433 {
 434         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 435         struct amdgpu_dm_connector *master = aconnector->mst_root;
 436         struct drm_dp_mst_port *port = aconnector->mst_output_port;
 437         int connection_status;
 438
 439         if (drm_connector_is_unregistered(connector))
 440                 return connector_status_disconnected;
 441
 442         connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
 443                                                         aconnector->mst_output_port);
 444
 445         if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) {
 446                 uint8_t dpcd_rev;
 447                 int ret;
 448
 449                 ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev);
 450
 451                 if (ret == 1) {
 452                         port->dpcd_rev = dpcd_rev;
 453
 454                         /* Could be DP1.2 DP Rx case*/
 455                         if (!dpcd_rev) {
 456                                 ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev);
 457
 458                                 if (ret == 1)
 459                                         port->dpcd_rev = dpcd_rev;
 460                         }
 461
 462                         if (!dpcd_rev)
 463                                 DRM_DEBUG_KMS("Can't decide DPCD revision number!");
 464                 }
 465
 466                 /*
 467                  * Could be legacy sink, logical port etc on DP1.2.
 468                  * Will get Nack under these cases when issue remote
 469                  * DPCD read.
 470                  */
 471                 if (ret != 1)
 472                         DRM_DEBUG_KMS("Can't access DPCD");
 473         } else if (port->pdt == DP_PEER_DEVICE_NONE) {
 474                 port->dpcd_rev = 0;
 475         }
 476
 477         /*
 478          * Release dc_sink for connector which unplug event is notified by CSN msg
 479          */
 480         if (connection_status == connector_status_disconnected && aconnector->dc_sink) {
 481                 if (aconnector->dc_link->sink_count)
 482                         dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
 483
 484                 DC_LOG_MST("DM_MST: remove remote sink 0x%p, %d remaining\n",
 485                         aconnector->dc_link, aconnector->dc_link->sink_count);
 486
 487                 dc_sink_release(aconnector->dc_sink);
 488                 aconnector->dc_sink = NULL;
 489                 aconnector->edid = NULL;
 490
 491                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 492                         MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD,
 493                         false);
 494         }
 495
 496         return connection_status;
 497 }
 498
 499 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
 500                                   struct drm_atomic_state *state)
 501 {
 502         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 503         struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr;
 504         struct drm_dp_mst_port *mst_port = aconnector->mst_output_port;
 505
 506         return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port);
 507 }
 508
 509 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
 510         .get_modes = dm_dp_mst_get_modes,
 511         .mode_valid = amdgpu_dm_connector_mode_valid,
 512         .atomic_best_encoder = dm_mst_atomic_best_encoder,
 513         .detect_ctx = dm_dp_mst_detect,
 514         .atomic_check = dm_dp_mst_atomic_check,
 515 };
 516
 517 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
 518 {
 519         drm_encoder_cleanup(encoder);
 520 }
 521
 522 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
 523         .destroy = amdgpu_dm_encoder_destroy,
 524 };
 525
 526 void
 527 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
 528 {
 529         struct drm_device *dev = adev_to_drm(adev);
 530         int i;
 531
 532         for (i = 0; i < adev->dm.display_indexes_num; i++) {
 533                 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
 534                 struct drm_encoder *encoder = &amdgpu_encoder->base;
 535
 536                 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
 537
 538                 drm_encoder_init(
 539                         dev,
 540                         &amdgpu_encoder->base,
 541                         &amdgpu_dm_encoder_funcs,
 542                         DRM_MODE_ENCODER_DPMST,
 543                         NULL);
 544
 545                 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
 546         }
 547 }
 548
 549 static struct drm_connector *
 550 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 551                         struct drm_dp_mst_port *port,
 552                         const char *pathprop)
 553 {
 554         struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
 555         struct drm_device *dev = master->base.dev;
 556         struct amdgpu_device *adev = drm_to_adev(dev);
 557         struct amdgpu_dm_connector *aconnector;
 558         struct drm_connector *connector;
 559         int i;
 560
 561         aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
 562         if (!aconnector)
 563                 return NULL;
 564
 565         connector = &aconnector->base;
 566         aconnector->mst_output_port = port;
 567         aconnector->mst_root = master;
 568         amdgpu_dm_set_mst_status(&aconnector->mst_status,
 569                         MST_PROBE, true);
 570
 571         if (drm_connector_init(
 572                 dev,
 573                 connector,
 574                 &dm_dp_mst_connector_funcs,
 575                 DRM_MODE_CONNECTOR_DisplayPort)) {
 576                 kfree(aconnector);
 577                 return NULL;
 578         }
 579         drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
 580
 581         amdgpu_dm_connector_init_helper(
 582                 &adev->dm,
 583                 aconnector,
 584                 DRM_MODE_CONNECTOR_DisplayPort,
 585                 master->dc_link,
 586                 master->connector_id);
 587
 588         for (i = 0; i < adev->dm.display_indexes_num; i++) {
 589                 drm_connector_attach_encoder(&aconnector->base,
 590                                              &adev->dm.mst_encoders[i].base);
 591         }
 592
 593         connector->max_bpc_property = master->base.max_bpc_property;
 594         if (connector->max_bpc_property)
 595                 drm_connector_attach_max_bpc_property(connector, 8, 16);
 596
 597         connector->vrr_capable_property = master->base.vrr_capable_property;
 598         if (connector->vrr_capable_property)
 599                 drm_connector_attach_vrr_capable_property(connector);
 600
 601         drm_object_attach_property(
 602                 &connector->base,
 603                 dev->mode_config.path_property,
 604                 0);
 605         drm_object_attach_property(
 606                 &connector->base,
 607                 dev->mode_config.tile_property,
 608                 0);
 609
 610         drm_connector_set_path_property(connector, pathprop);
 611
 612         /*
 613          * Initialize connector state before adding the connectror to drm and
 614          * framebuffer lists
 615          */
 616         amdgpu_dm_connector_funcs_reset(connector);
 617
 618         drm_dp_mst_get_port_malloc(port);
 619
 620         return connector;
 621 }
 622
 623 void dm_handle_mst_sideband_msg_ready_event(
 624         struct drm_dp_mst_topology_mgr *mgr,
 625         enum mst_msg_ready_type msg_rdy_type)
 626 {
 627         uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
 628         uint8_t dret;
 629         bool new_irq_handled = false;
 630         int dpcd_addr;
 631         uint8_t dpcd_bytes_to_read;
 632         const uint8_t max_process_count = 30;
 633         uint8_t process_count = 0;
 634         u8 retry;
 635         struct amdgpu_dm_connector *aconnector =
 636                         container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
 637
 638
 639         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
 640
 641         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
 642                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
 643                 /* DPCD 0x200 - 0x201 for downstream IRQ */
 644                 dpcd_addr = DP_SINK_COUNT;
 645         } else {
 646                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
 647                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
 648                 dpcd_addr = DP_SINK_COUNT_ESI;
 649         }
 650
 651         mutex_lock(&aconnector->handle_mst_msg_ready);
 652
 653         while (process_count < max_process_count) {
 654                 u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {};
 655
 656                 process_count++;
 657
 658                 dret = drm_dp_dpcd_read(
 659                         &aconnector->dm_dp_aux.aux,
 660                         dpcd_addr,
 661                         esi,
 662                         dpcd_bytes_to_read);
 663
 664                 if (dret != dpcd_bytes_to_read) {
 665                         DRM_DEBUG_KMS("DPCD read and acked number is not as expected!");
 666                         break;
 667                 }
 668
 669                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
 670
 671                 switch (msg_rdy_type) {
 672                 case DOWN_REP_MSG_RDY_EVENT:
 673                         /* Only handle DOWN_REP_MSG_RDY case*/
 674                         esi[1] &= DP_DOWN_REP_MSG_RDY;
 675                         break;
 676                 case UP_REQ_MSG_RDY_EVENT:
 677                         /* Only handle UP_REQ_MSG_RDY case*/
 678                         esi[1] &= DP_UP_REQ_MSG_RDY;
 679                         break;
 680                 default:
 681                         /* Handle both cases*/
 682                         esi[1] &= (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY);
 683                         break;
 684                 }
 685
 686                 if (!esi[1])
 687                         break;
 688
 689                 /* handle MST irq */
 690                 if (aconnector->mst_mgr.mst_state)
 691                         drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr,
 692                                                  esi,
 693                                                  ack,
 694                                                  &new_irq_handled);
 695
 696                 if (new_irq_handled) {
 697                         /* ACK at DPCD to notify down stream */
 698                         for (retry = 0; retry < 3; retry++) {
 699                                 ssize_t wret;
 700
 701                                 wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux,
 702                                                           dpcd_addr + 1,
 703                                                           ack[1]);
 704                                 if (wret == 1)
 705                                         break;
 706                         }
 707
 708                         if (retry == 3) {
 709                                 DRM_ERROR("Failed to ack MST event.\n");
 710                                 break;
 711                         }
 712
 713                         drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr);
 714
 715                         new_irq_handled = false;
 716                 } else {
 717                         break;
 718                 }
 719         }
 720
 721         mutex_unlock(&aconnector->handle_mst_msg_ready);
 722
 723         if (process_count == max_process_count)
 724                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
 725 }
 726
 727 static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr)
 728 {
 729         dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT);
 730 }
 731
 732 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
 733         .add_connector = dm_dp_add_mst_connector,
 734         .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready,
 735 };
 736
 737 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 738                                        struct amdgpu_dm_connector *aconnector,
 739                                        int link_index)
 740 {
 741         struct dc_link_settings max_link_enc_cap = {0};
 742
 743         aconnector->dm_dp_aux.aux.name =
 744                 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
 745                           link_index);
 746         aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
 747         aconnector->dm_dp_aux.aux.drm_dev = dm->ddev;
 748         aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
 749
 750         drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
 751         drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
 752                                       &aconnector->base);
 753
 754         if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
 755                 return;
 756
 757         dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap);
 758         aconnector->mst_mgr.cbs = &dm_mst_cbs;
 759         drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev),
 760                                      &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id);
 761
 762         drm_connector_attach_dp_subconnector_property(&aconnector->base);
 763 }
 764
 765 int dm_mst_get_pbn_divider(struct dc_link *link)
 766 {
 767         if (!link)
 768                 return 0;
 769
 770         return dc_link_bandwidth_kbps(link,
 771                         dc_link_get_link_cap(link)) / (8 * 1000 * 54);
 772 }
 773
 774 struct dsc_mst_fairness_params {
 775         struct dc_crtc_timing *timing;
 776         struct dc_sink *sink;
 777         struct dc_dsc_bw_range bw_range;
 778         bool compression_possible;
 779         struct drm_dp_mst_port *port;
 780         enum dsc_clock_force_state clock_force_enable;
 781         uint32_t num_slices_h;
 782         uint32_t num_slices_v;
 783         uint32_t bpp_overwrite;
 784         struct amdgpu_dm_connector *aconnector;
 785 };
 786
 787 static uint16_t get_fec_overhead_multiplier(struct dc_link *dc_link)
 788 {
 789         u8 link_coding_cap;
 790         uint16_t fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B;
 791
 792         link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(dc_link);
 793         if (link_coding_cap == DP_128b_132b_ENCODING)
 794                 fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B;
 795
 796         return fec_overhead_multiplier_x1000;
 797 }
 798
 799 static int kbps_to_peak_pbn(int kbps, uint16_t fec_overhead_multiplier_x1000)
 800 {
 801         u64 peak_kbps = kbps;
 802
 803         peak_kbps *= 1006;
 804         peak_kbps *= fec_overhead_multiplier_x1000;
 805         peak_kbps = div_u64(peak_kbps, 1000 * 1000);
 806         return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
 807 }
 808
 809 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
 810                 struct dsc_mst_fairness_vars *vars,
 811                 int count,
 812                 int k)
 813 {
 814         struct drm_connector *drm_connector;
 815         int i;
 816         struct dc_dsc_config_options dsc_options = {0};
 817
 818         for (i = 0; i < count; i++) {
 819                 drm_connector = &params[i].aconnector->base;
 820
 821                 dc_dsc_get_default_config_option(params[i].sink->ctx->dc, &dsc_options);
 822                 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16;
 823
 824                 memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
 825                 if (vars[i + k].dsc_enabled && dc_dsc_compute_config(
 826                                         params[i].sink->ctx->dc->res_pool->dscs[0],
 827                                         &params[i].sink->dsc_caps.dsc_dec_caps,
 828                                         &dsc_options,
 829                                         0,
 830                                         params[i].timing,
 831                                         dc_link_get_highest_encoding_format(params[i].aconnector->dc_link),
 832                                         &params[i].timing->dsc_cfg)) {
 833                         params[i].timing->flags.DSC = 1;
 834
 835                         if (params[i].bpp_overwrite)
 836                                 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
 837                         else
 838                                 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;
 839
 840                         if (params[i].num_slices_h)
 841                                 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
 842
 843                         if (params[i].num_slices_v)
 844                                 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
 845                 } else {
 846                         params[i].timing->flags.DSC = 0;
 847                 }
 848                 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn;
 849         }
 850
 851         for (i = 0; i < count; i++) {
 852                 if (params[i].sink) {
 853                         if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
 854                                 params[i].sink->sink_signal != SIGNAL_TYPE_NONE)
 855                                 DRM_DEBUG_DRIVER("%s i=%d dispname=%s\n", __func__, i,
 856                                         params[i].sink->edid_caps.display_name);
 857                 }
 858
 859                 DRM_DEBUG_DRIVER("dsc=%d bits_per_pixel=%d pbn=%d\n",
 860                         params[i].timing->flags.DSC,
 861                         params[i].timing->dsc_cfg.bits_per_pixel,
 862                         vars[i + k].pbn);
 863         }
 864 }
 865
 866 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
 867 {
 868         struct dc_dsc_config dsc_config;
 869         u64 kbps;
 870
 871         struct drm_connector *drm_connector = &param.aconnector->base;
 872         struct dc_dsc_config_options dsc_options = {0};
 873
 874         dc_dsc_get_default_config_option(param.sink->ctx->dc, &dsc_options);
 875         dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16;
 876
 877         kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
 878         dc_dsc_compute_config(
 879                         param.sink->ctx->dc->res_pool->dscs[0],
 880                         &param.sink->dsc_caps.dsc_dec_caps,
 881                         &dsc_options,
 882                         (int) kbps, param.timing,
 883                         dc_link_get_highest_encoding_format(param.aconnector->dc_link),
 884                         &dsc_config);
 885
 886         return dsc_config.bits_per_pixel;
 887 }
 888
 889 static int increase_dsc_bpp(struct drm_atomic_state *state,
 890                             struct drm_dp_mst_topology_state *mst_state,
 891                             struct dc_link *dc_link,
 892                             struct dsc_mst_fairness_params *params,
 893                             struct dsc_mst_fairness_vars *vars,
 894                             int count,
 895                             int k)
 896 {
 897         int i;
 898         bool bpp_increased[MAX_PIPES];
 899         int initial_slack[MAX_PIPES];
 900         int min_initial_slack;
 901         int next_index;
 902         int remaining_to_increase = 0;
 903         int link_timeslots_used;
 904         int fair_pbn_alloc;
 905         int ret = 0;
 906         uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
 907
 908         for (i = 0; i < count; i++) {
 909                 if (vars[i + k].dsc_enabled) {
 910                         initial_slack[i] =
 911                         kbps_to_peak_pbn(params[i].bw_range.max_kbps, fec_overhead_multiplier_x1000) - vars[i + k].pbn;
 912                         bpp_increased[i] = false;
 913                         remaining_to_increase += 1;
 914                 } else {
 915                         initial_slack[i] = 0;
 916                         bpp_increased[i] = true;
 917                 }
 918         }
 919
 920         while (remaining_to_increase) {
 921                 next_index = -1;
 922                 min_initial_slack = -1;
 923                 for (i = 0; i < count; i++) {
 924                         if (!bpp_increased[i]) {
 925                                 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
 926                                         min_initial_slack = initial_slack[i];
 927                                         next_index = i;
 928                                 }
 929                         }
 930                 }
 931
 932                 if (next_index == -1)
 933                         break;
 934
 935                 link_timeslots_used = 0;
 936
 937                 for (i = 0; i < count; i++)
 938                         link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, mst_state->pbn_div);
 939
 940                 fair_pbn_alloc =
 941                         (63 - link_timeslots_used) / remaining_to_increase * mst_state->pbn_div;
 942
 943                 if (initial_slack[next_index] > fair_pbn_alloc) {
 944                         vars[next_index].pbn += fair_pbn_alloc;
 945                         ret = drm_dp_atomic_find_time_slots(state,
 946                                                             params[next_index].port->mgr,
 947                                                             params[next_index].port,
 948                                                             vars[next_index].pbn);
 949                         if (ret < 0)
 950                                 return ret;
 951
 952                         ret = drm_dp_mst_atomic_check(state);
 953                         if (ret == 0) {
 954                                 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
 955                         } else {
 956                                 vars[next_index].pbn -= fair_pbn_alloc;
 957                                 ret = drm_dp_atomic_find_time_slots(state,
 958                                                                     params[next_index].port->mgr,
 959                                                                     params[next_index].port,
 960                                                                     vars[next_index].pbn);
 961                                 if (ret < 0)
 962                                         return ret;
 963                         }
 964                 } else {
 965                         vars[next_index].pbn += initial_slack[next_index];
 966                         ret = drm_dp_atomic_find_time_slots(state,
 967                                                             params[next_index].port->mgr,
 968                                                             params[next_index].port,
 969                                                             vars[next_index].pbn);
 970                         if (ret < 0)
 971                                 return ret;
 972
 973                         ret = drm_dp_mst_atomic_check(state);
 974                         if (ret == 0) {
 975                                 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
 976                         } else {
 977                                 vars[next_index].pbn -= initial_slack[next_index];
 978                                 ret = drm_dp_atomic_find_time_slots(state,
 979                                                                     params[next_index].port->mgr,
 980                                                                     params[next_index].port,
 981                                                                     vars[next_index].pbn);
 982                                 if (ret < 0)
 983                                         return ret;
 984                         }
 985                 }
 986
 987                 bpp_increased[next_index] = true;
 988                 remaining_to_increase--;
 989         }
 990         return 0;
 991 }
 992
 993 static int try_disable_dsc(struct drm_atomic_state *state,
 994                            struct dc_link *dc_link,
 995                            struct dsc_mst_fairness_params *params,
 996                            struct dsc_mst_fairness_vars *vars,
 997                            int count,
 998                            int k)
 999 {
1000         int i;
1001         bool tried[MAX_PIPES];
1002         int kbps_increase[MAX_PIPES];
1003         int max_kbps_increase;
1004         int next_index;
1005         int remaining_to_try = 0;
1006         int ret;
1007         uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
1008
1009         for (i = 0; i < count; i++) {
1010                 if (vars[i + k].dsc_enabled
1011                                 && vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16
1012                                 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
1013                         kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
1014                         tried[i] = false;
1015                         remaining_to_try += 1;
1016                 } else {
1017                         kbps_increase[i] = 0;
1018                         tried[i] = true;
1019                 }
1020         }
1021
1022         while (remaining_to_try) {
1023                 next_index = -1;
1024                 max_kbps_increase = -1;
1025                 for (i = 0; i < count; i++) {
1026                         if (!tried[i]) {
1027                                 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
1028                                         max_kbps_increase = kbps_increase[i];
1029                                         next_index = i;
1030                                 }
1031                         }
1032                 }
1033
1034                 if (next_index == -1)
1035                         break;
1036
1037                 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1038                 ret = drm_dp_atomic_find_time_slots(state,
1039                                                     params[next_index].port->mgr,
1040                                                     params[next_index].port,
1041                                                     vars[next_index].pbn);
1042                 if (ret < 0)
1043                         return ret;
1044
1045                 ret = drm_dp_mst_atomic_check(state);
1046                 if (ret == 0) {
1047                         vars[next_index].dsc_enabled = false;
1048                         vars[next_index].bpp_x16 = 0;
1049                 } else {
1050                         vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps, fec_overhead_multiplier_x1000);
1051                         ret = drm_dp_atomic_find_time_slots(state,
1052                                                             params[next_index].port->mgr,
1053                                                             params[next_index].port,
1054                                                             vars[next_index].pbn);
1055                         if (ret < 0)
1056                                 return ret;
1057                 }
1058
1059                 tried[next_index] = true;
1060                 remaining_to_try--;
1061         }
1062         return 0;
1063 }
1064
1065 static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
1066                                             struct dc_state *dc_state,
1067                                             struct dc_link *dc_link,
1068                                             struct dsc_mst_fairness_vars *vars,
1069                                             struct drm_dp_mst_topology_mgr *mgr,
1070                                             int *link_vars_start_index)
1071 {
1072         struct dc_stream_state *stream;
1073         struct dsc_mst_fairness_params params[MAX_PIPES];
1074         struct amdgpu_dm_connector *aconnector;
1075         struct drm_dp_mst_topology_state *mst_state = drm_atomic_get_mst_topology_state(state, mgr);
1076         int count = 0;
1077         int i, k, ret;
1078         bool debugfs_overwrite = false;
1079         uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link);
1080
1081         memset(params, 0, sizeof(params));
1082
1083         if (IS_ERR(mst_state))
1084                 return PTR_ERR(mst_state);
1085
1086         /* Set up params */
1087         for (i = 0; i < dc_state->stream_count; i++) {
1088                 struct dc_dsc_policy dsc_policy = {0};
1089
1090                 stream = dc_state->streams[i];
1091
1092                 if (stream->link != dc_link)
1093                         continue;
1094
1095                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1096                 if (!aconnector)
1097                         continue;
1098
1099                 if (!aconnector->mst_output_port)
1100                         continue;
1101
1102                 stream->timing.flags.DSC = 0;
1103
1104                 params[count].timing = &stream->timing;
1105                 params[count].sink = stream->sink;
1106                 params[count].aconnector = aconnector;
1107                 params[count].port = aconnector->mst_output_port;
1108                 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
1109                 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
1110                         debugfs_overwrite = true;
1111                 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
1112                 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
1113                 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
1114                 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
1115                 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy);
1116                 if (!dc_dsc_compute_bandwidth_range(
1117                                 stream->sink->ctx->dc->res_pool->dscs[0],
1118                                 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
1119                                 dsc_policy.min_target_bpp * 16,
1120                                 dsc_policy.max_target_bpp * 16,
1121                                 &stream->sink->dsc_caps.dsc_dec_caps,
1122                                 &stream->timing,
1123                                 dc_link_get_highest_encoding_format(dc_link),
1124                                 &params[count].bw_range))
1125                         params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
1126                                         dc_link_get_highest_encoding_format(dc_link));
1127
1128                 count++;
1129         }
1130
1131         if (count == 0) {
1132                 ASSERT(0);
1133                 return 0;
1134         }
1135
1136         /* k is start index of vars for current phy link used by mst hub */
1137         k = *link_vars_start_index;
1138         /* set vars start index for next mst hub phy link */
1139         *link_vars_start_index += count;
1140
1141         /* Try no compression */
1142         for (i = 0; i < count; i++) {
1143                 vars[i + k].aconnector = params[i].aconnector;
1144                 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1145                 vars[i + k].dsc_enabled = false;
1146                 vars[i + k].bpp_x16 = 0;
1147                 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port,
1148                                                     vars[i + k].pbn);
1149                 if (ret < 0)
1150                         return ret;
1151         }
1152         ret = drm_dp_mst_atomic_check(state);
1153         if (ret == 0 && !debugfs_overwrite) {
1154                 set_dsc_configs_from_fairness_vars(params, vars, count, k);
1155                 return 0;
1156         } else if (ret != -ENOSPC) {
1157                 return ret;
1158         }
1159
1160         /* Try max compression */
1161         for (i = 0; i < count; i++) {
1162                 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
1163                         vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps, fec_overhead_multiplier_x1000);
1164                         vars[i + k].dsc_enabled = true;
1165                         vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
1166                         ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
1167                                                             params[i].port, vars[i + k].pbn);
1168                         if (ret < 0)
1169                                 return ret;
1170                 } else {
1171                         vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000);
1172                         vars[i + k].dsc_enabled = false;
1173                         vars[i + k].bpp_x16 = 0;
1174                         ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
1175                                                             params[i].port, vars[i + k].pbn);
1176                         if (ret < 0)
1177                                 return ret;
1178                 }
1179         }
1180         ret = drm_dp_mst_atomic_check(state);
1181         if (ret != 0)
1182                 return ret;
1183
1184         /* Optimize degree of compression */
1185         ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k);
1186         if (ret < 0)
1187                 return ret;
1188
1189         ret = try_disable_dsc(state, dc_link, params, vars, count, k);
1190         if (ret < 0)
1191                 return ret;
1192
1193         set_dsc_configs_from_fairness_vars(params, vars, count, k);
1194
1195         return 0;
1196 }
1197
1198 static bool is_dsc_need_re_compute(
1199         struct drm_atomic_state *state,
1200         struct dc_state *dc_state,
1201         struct dc_link *dc_link)
1202 {
1203         int i, j;
1204         bool is_dsc_need_re_compute = false;
1205         struct amdgpu_dm_connector *stream_on_link[MAX_PIPES];
1206         int new_stream_on_link_num = 0;
1207         struct amdgpu_dm_connector *aconnector;
1208         struct dc_stream_state *stream;
1209         const struct dc *dc = dc_link->dc;
1210
1211         /* only check phy used by dsc mst branch */
1212         if (dc_link->type != dc_connection_mst_branch)
1213                 return false;
1214
1215         if (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
1216                 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
1217                 return false;
1218
1219         for (i = 0; i < MAX_PIPES; i++)
1220                 stream_on_link[i] = NULL;
1221
1222         /* check if there is mode change in new request */
1223         for (i = 0; i < dc_state->stream_count; i++) {
1224                 struct drm_crtc_state *new_crtc_state;
1225                 struct drm_connector_state *new_conn_state;
1226
1227                 stream = dc_state->streams[i];
1228                 if (!stream)
1229                         continue;
1230
1231                 /* check if stream using the same link for mst */
1232                 if (stream->link != dc_link)
1233                         continue;
1234
1235                 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context;
1236                 if (!aconnector)
1237                         continue;
1238
1239                 stream_on_link[new_stream_on_link_num] = aconnector;
1240                 new_stream_on_link_num++;
1241
1242                 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base);
1243                 if (!new_conn_state)
1244                         continue;
1245
1246                 if (IS_ERR(new_conn_state))
1247                         continue;
1248
1249                 if (!new_conn_state->crtc)
1250                         continue;
1251
1252                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
1253                 if (!new_crtc_state)
1254                         continue;
1255
1256                 if (IS_ERR(new_crtc_state))
1257                         continue;
1258
1259                 if (new_crtc_state->enable && new_crtc_state->active) {
1260                         if (new_crtc_state->mode_changed || new_crtc_state->active_changed ||
1261                                 new_crtc_state->connectors_changed)
1262                                 return true;
1263                 }
1264         }
1265
1266         /* check current_state if there stream on link but it is not in
1267          * new request state
1268          */
1269         for (i = 0; i < dc->current_state->stream_count; i++) {
1270                 stream = dc->current_state->streams[i];
1271                 /* only check stream on the mst hub */
1272                 if (stream->link != dc_link)
1273                         continue;
1274
1275                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1276                 if (!aconnector)
1277                         continue;
1278
1279                 for (j = 0; j < new_stream_on_link_num; j++) {
1280                         if (stream_on_link[j]) {
1281                                 if (aconnector == stream_on_link[j])
1282                                         break;
1283                         }
1284                 }
1285
1286                 if (j == new_stream_on_link_num) {
1287                         /* not in new state */
1288                         is_dsc_need_re_compute = true;
1289                         break;
1290                 }
1291         }
1292
1293         return is_dsc_need_re_compute;
1294 }
1295
1296 int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
1297                                       struct dc_state *dc_state,
1298                                       struct dsc_mst_fairness_vars *vars)
1299 {
1300         int i, j;
1301         struct dc_stream_state *stream;
1302         bool computed_streams[MAX_PIPES];
1303         struct amdgpu_dm_connector *aconnector;
1304         struct drm_dp_mst_topology_mgr *mst_mgr;
1305         struct resource_pool *res_pool;
1306         int link_vars_start_index = 0;
1307         int ret = 0;
1308
1309         for (i = 0; i < dc_state->stream_count; i++)
1310                 computed_streams[i] = false;
1311
1312         for (i = 0; i < dc_state->stream_count; i++) {
1313                 stream = dc_state->streams[i];
1314                 res_pool = stream->ctx->dc->res_pool;
1315
1316                 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1317                         continue;
1318
1319                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1320
1321                 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port)
1322                         continue;
1323
1324                 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1325                         continue;
1326
1327                 if (computed_streams[i])
1328                         continue;
1329
1330                 if (res_pool->funcs->remove_stream_from_ctx &&
1331                     res_pool->funcs->remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
1332                         return -EINVAL;
1333
1334                 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1335                         continue;
1336
1337                 mst_mgr = aconnector->mst_output_port->mgr;
1338                 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,
1339                                                        &link_vars_start_index);
1340                 if (ret != 0)
1341                         return ret;
1342
1343                 for (j = 0; j < dc_state->stream_count; j++) {
1344                         if (dc_state->streams[j]->link == stream->link)
1345                                 computed_streams[j] = true;
1346                 }
1347         }
1348
1349         for (i = 0; i < dc_state->stream_count; i++) {
1350                 stream = dc_state->streams[i];
1351
1352                 if (stream->timing.flags.DSC == 1)
1353                         if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK)
1354                                 return -EINVAL;
1355         }
1356
1357         return ret;
1358 }
1359
1360 static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
1361                                                  struct dc_state *dc_state,
1362                                                  struct dsc_mst_fairness_vars *vars)
1363 {
1364         int i, j;
1365         struct dc_stream_state *stream;
1366         bool computed_streams[MAX_PIPES];
1367         struct amdgpu_dm_connector *aconnector;
1368         struct drm_dp_mst_topology_mgr *mst_mgr;
1369         int link_vars_start_index = 0;
1370         int ret = 0;
1371
1372         for (i = 0; i < dc_state->stream_count; i++)
1373                 computed_streams[i] = false;
1374
1375         for (i = 0; i < dc_state->stream_count; i++) {
1376                 stream = dc_state->streams[i];
1377
1378                 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1379                         continue;
1380
1381                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1382
1383                 if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port)
1384                         continue;
1385
1386                 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1387                         continue;
1388
1389                 if (computed_streams[i])
1390                         continue;
1391
1392                 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1393                         continue;
1394
1395                 mst_mgr = aconnector->mst_output_port->mgr;
1396                 ret = compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars, mst_mgr,
1397                                                        &link_vars_start_index);
1398                 if (ret != 0)
1399                         return ret;
1400
1401                 for (j = 0; j < dc_state->stream_count; j++) {
1402                         if (dc_state->streams[j]->link == stream->link)
1403                                 computed_streams[j] = true;
1404                 }
1405         }
1406
1407         return ret;
1408 }
1409
1410 static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state,
1411                                               struct dc_stream_state *stream)
1412 {
1413         int i;
1414         struct drm_crtc *crtc;
1415         struct drm_crtc_state *new_state, *old_state;
1416
1417         for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, i) {
1418                 struct dm_crtc_state *dm_state = to_dm_crtc_state(new_state);
1419
1420                 if (dm_state->stream == stream)
1421                         return i;
1422         }
1423         return -1;
1424 }
1425
1426 static bool is_link_to_dschub(struct dc_link *dc_link)
1427 {
1428         union dpcd_dsc_basic_capabilities *dsc_caps =
1429                         &dc_link->dpcd_caps.dsc_caps.dsc_basic_caps;
1430
1431         /* only check phy used by dsc mst branch */
1432         if (dc_link->type != dc_connection_mst_branch)
1433                 return false;
1434
1435         if (!(dsc_caps->fields.dsc_support.DSC_SUPPORT ||
1436               dsc_caps->fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
1437                 return false;
1438         return true;
1439 }
1440
1441 static bool is_dsc_precompute_needed(struct drm_atomic_state *state)
1442 {
1443         int i;
1444         struct drm_crtc *crtc;
1445         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1446         bool ret = false;
1447
1448         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1449                 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(new_crtc_state);
1450
1451                 if (!amdgpu_dm_find_first_crtc_matching_connector(state, crtc)) {
1452                         ret =  false;
1453                         break;
1454                 }
1455                 if (dm_crtc_state->stream && dm_crtc_state->stream->link)
1456                         if (is_link_to_dschub(dm_crtc_state->stream->link))
1457                                 ret = true;
1458         }
1459         return ret;
1460 }
1461
1462 int pre_validate_dsc(struct drm_atomic_state *state,
1463                      struct dm_atomic_state **dm_state_ptr,
1464                      struct dsc_mst_fairness_vars *vars)
1465 {
1466         int i;
1467         struct dm_atomic_state *dm_state;
1468         struct dc_state *local_dc_state = NULL;
1469         int ret = 0;
1470
1471         if (!is_dsc_precompute_needed(state)) {
1472                 DRM_INFO_ONCE("DSC precompute is not needed.\n");
1473                 return 0;
1474         }
1475         ret = dm_atomic_get_state(state, dm_state_ptr);
1476         if (ret != 0) {
1477                 DRM_INFO_ONCE("dm_atomic_get_state() failed\n");
1478                 return ret;
1479         }
1480         dm_state = *dm_state_ptr;
1481
1482         /*
1483          * create local vailable for dc_state. copy content of streams of dm_state->context
1484          * to local variable. make sure stream pointer of local variable not the same as stream
1485          * from dm_state->context.
1486          */
1487
1488         local_dc_state = kmemdup(dm_state->context, sizeof(struct dc_state), GFP_KERNEL);
1489         if (!local_dc_state)
1490                 return -ENOMEM;
1491
1492         for (i = 0; i < local_dc_state->stream_count; i++) {
1493                 struct dc_stream_state *stream = dm_state->context->streams[i];
1494                 int ind = find_crtc_index_in_state_by_stream(state, stream);
1495
1496                 if (ind >= 0) {
1497                         struct amdgpu_dm_connector *aconnector;
1498                         struct drm_connector_state *drm_new_conn_state;
1499                         struct dm_connector_state *dm_new_conn_state;
1500                         struct dm_crtc_state *dm_old_crtc_state;
1501
1502                         aconnector =
1503                                 amdgpu_dm_find_first_crtc_matching_connector(state,
1504                                                                              state->crtcs[ind].ptr);
1505                         drm_new_conn_state =
1506                                 drm_atomic_get_new_connector_state(state,
1507                                                                    &aconnector->base);
1508                         dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
1509                         dm_old_crtc_state = to_dm_crtc_state(state->crtcs[ind].old_state);
1510
1511                         local_dc_state->streams[i] =
1512                                 create_validate_stream_for_sink(aconnector,
1513                                                                 &state->crtcs[ind].new_state->mode,
1514                                                                 dm_new_conn_state,
1515                                                                 dm_old_crtc_state->stream);
1516                         if (local_dc_state->streams[i] == NULL) {
1517                                 ret = -EINVAL;
1518                                 break;
1519                         }
1520                 }
1521         }
1522
1523         if (ret != 0)
1524                 goto clean_exit;
1525
1526         ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars);
1527         if (ret != 0) {
1528                 DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n");
1529                 ret = -EINVAL;
1530                 goto clean_exit;
1531         }
1532
1533         /*
1534          * compare local_streams -> timing  with dm_state->context,
1535          * if the same set crtc_state->mode-change = 0;
1536          */
1537         for (i = 0; i < local_dc_state->stream_count; i++) {
1538                 struct dc_stream_state *stream = dm_state->context->streams[i];
1539
1540                 if (local_dc_state->streams[i] &&
1541                     dc_is_timing_changed(stream, local_dc_state->streams[i])) {
1542                         DRM_INFO_ONCE("crtc[%d] needs mode_changed\n", i);
1543                 } else {
1544                         int ind = find_crtc_index_in_state_by_stream(state, stream);
1545
1546                         if (ind >= 0)
1547                                 state->crtcs[ind].new_state->mode_changed = 0;
1548                 }
1549         }
1550 clean_exit:
1551         for (i = 0; i < local_dc_state->stream_count; i++) {
1552                 struct dc_stream_state *stream = dm_state->context->streams[i];
1553
1554                 if (local_dc_state->streams[i] != stream)
1555                         dc_stream_release(local_dc_state->streams[i]);
1556         }
1557
1558         kfree(local_dc_state);
1559
1560         return ret;
1561 }
1562
1563 static unsigned int kbps_from_pbn(unsigned int pbn)
1564 {
1565         unsigned int kbps = pbn;
1566
1567         kbps *= (1000000 / PEAK_FACTOR_X1000);
1568         kbps *= 8;
1569         kbps *= 54;
1570         kbps /= 64;
1571
1572         return kbps;
1573 }
1574
1575 static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
1576                                           struct dc_dsc_bw_range *bw_range)
1577 {
1578         struct dc_dsc_policy dsc_policy = {0};
1579
1580         dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy);
1581         dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],
1582                                        stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
1583                                        dsc_policy.min_target_bpp * 16,
1584                                        dsc_policy.max_target_bpp * 16,
1585                                        &stream->sink->dsc_caps.dsc_dec_caps,
1586                                        &stream->timing, dc_link_get_highest_encoding_format(stream->link), bw_range);
1587
1588         return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16;
1589 }
1590
1591 enum dc_status dm_dp_mst_is_port_support_mode(
1592         struct amdgpu_dm_connector *aconnector,
1593         struct dc_stream_state *stream)
1594 {
1595         int bpp, pbn, branch_max_throughput_mps = 0;
1596         struct dc_link_settings cur_link_settings;
1597         unsigned int end_to_end_bw_in_kbps = 0;
1598         unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0;
1599         unsigned int max_compressed_bw_in_kbps = 0;
1600         struct dc_dsc_bw_range bw_range = {0};
1601         struct drm_dp_mst_topology_mgr *mst_mgr;
1602
1603         /*
1604          * check if the mode could be supported if DSC pass-through is supported
1605          * AND check if there enough bandwidth available to support the mode
1606          * with DSC enabled.
1607          */
1608         if (is_dsc_common_config_possible(stream, &bw_range) &&
1609             aconnector->mst_output_port->passthrough_aux) {
1610                 mst_mgr = aconnector->mst_output_port->mgr;
1611                 mutex_lock(&mst_mgr->lock);
1612
1613                 cur_link_settings = stream->link->verified_link_cap;
1614
1615                 upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
1616                                                                &cur_link_settings
1617                                                                );
1618                 down_link_bw_in_kbps = kbps_from_pbn(aconnector->mst_output_port->full_pbn);
1619
1620                 /* pick the bottleneck */
1621                 end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps,
1622                                             down_link_bw_in_kbps);
1623
1624                 mutex_unlock(&mst_mgr->lock);
1625
1626                 /*
1627                  * use the maximum dsc compression bandwidth as the required
1628                  * bandwidth for the mode
1629                  */
1630                 max_compressed_bw_in_kbps = bw_range.min_kbps;
1631
1632                 if (end_to_end_bw_in_kbps < max_compressed_bw_in_kbps) {
1633                         DRM_DEBUG_DRIVER("Mode does not fit into DSC pass-through bandwidth validation\n");
1634                         return DC_FAIL_BANDWIDTH_VALIDATE;
1635                 }
1636         } else {
1637                 /* check if mode could be supported within full_pbn */
1638                 bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
1639                 pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
1640
1641                 if (pbn > aconnector->mst_output_port->full_pbn)
1642                         return DC_FAIL_BANDWIDTH_VALIDATE;
1643         }
1644
1645         /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
1646         switch (stream->timing.pixel_encoding) {
1647         case PIXEL_ENCODING_RGB:
1648         case PIXEL_ENCODING_YCBCR444:
1649                 branch_max_throughput_mps =
1650                         aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps;
1651                 break;
1652         case PIXEL_ENCODING_YCBCR422:
1653         case PIXEL_ENCODING_YCBCR420:
1654                 branch_max_throughput_mps =
1655                         aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps;
1656                 break;
1657         default:
1658                 break;
1659         }
1660
1661         if (branch_max_throughput_mps != 0 &&
1662                 ((stream->timing.pix_clk_100hz / 10) >  branch_max_throughput_mps * 1000))
1663                 return DC_FAIL_BANDWIDTH_VALIDATE;
1664
1665         return DC_OK;
1666 }