drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services_types.h"
  27 #include "dc.h"
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_dm.h"
  31 #include "amdgpu_dm_irq.h"
  32
  33 /**
  34  * DOC: overview
  35  *
  36  * DM provides another layer of IRQ management on top of what the base driver
  37  * already provides. This is something that could be cleaned up, and is a
  38  * future TODO item.
  39  *
  40  * The base driver provides IRQ source registration with DRM, handler
  41  * registration into the base driver's IRQ table, and a handler callback
  42  * amdgpu_irq_handler(), with which DRM calls on interrupts. This generic
  43  * handler looks up the IRQ table, and calls the respective
  44  * &amdgpu_irq_src_funcs.process hookups.
  45  *
  46  * What DM provides on top are two IRQ tables specifically for top-half and
  47  * bottom-half IRQ handling, with the bottom-half implementing workqueues:
  48  *
  49  * - &amdgpu_display_manager.irq_handler_list_high_tab
  50  * - &amdgpu_display_manager.irq_handler_list_low_tab
  51  *
  52  * They override the base driver's IRQ table, and the effect can be seen
  53  * in the hooks that DM provides for &amdgpu_irq_src_funcs.process. They
  54  * are all set to the DM generic handler amdgpu_dm_irq_handler(), which looks up
  55  * DM's IRQ tables. However, in order for base driver to recognize this hook, DM
  56  * still needs to register the IRQ with the base driver. See
  57  * dce110_register_irq_handlers() and dcn10_register_irq_handlers().
  58  *
  59  * To expose DC's hardware interrupt toggle to the base driver, DM implements
  60  * &amdgpu_irq_src_funcs.set hooks. Base driver calls it through
  61  * amdgpu_irq_update() to enable or disable the interrupt.
  62  */
  63
  64 /******************************************************************************
  65  * Private declarations.
  66  *****************************************************************************/
  67
  68 /**
  69  * struct amdgpu_dm_irq_handler_data - Data for DM interrupt handlers.
  70  *
  71  * @list: Linked list entry referencing the next/previous handler
  72  * @handler: Handler function
  73  * @handler_arg: Argument passed to the handler when triggered
  74  * @dm: DM which this handler belongs to
  75  * @irq_source: DC interrupt source that this handler is registered for
  76  */
  77 struct amdgpu_dm_irq_handler_data {
  78         struct list_head list;
  79         interrupt_handler handler;
  80         void *handler_arg;
  81
  82         struct amdgpu_display_manager *dm;
  83         /* DAL irq source which registered for this interrupt. */
  84         enum dc_irq_source irq_source;
  85         struct work_struct work;
  86 };
  87
  88 #define DM_IRQ_TABLE_LOCK(adev, flags) \
  89         spin_lock_irqsave(&adev->dm.irq_handler_list_table_lock, flags)
  90
  91 #define DM_IRQ_TABLE_UNLOCK(adev, flags) \
  92         spin_unlock_irqrestore(&adev->dm.irq_handler_list_table_lock, flags)
  93
  94 /******************************************************************************
  95  * Private functions.
  96  *****************************************************************************/
  97
  98 static void init_handler_common_data(struct amdgpu_dm_irq_handler_data *hcd,
  99                                      void (*ih)(void *),
 100                                      void *args,
 101                                      struct amdgpu_display_manager *dm)
 102 {
 103         hcd->handler = ih;
 104         hcd->handler_arg = args;
 105         hcd->dm = dm;
 106 }
 107
 108 /**
 109  * dm_irq_work_func() - Handle an IRQ outside of the interrupt handler proper.
 110  *
 111  * @work: work struct
 112  */
 113 static void dm_irq_work_func(struct work_struct *work)
 114 {
 115         struct amdgpu_dm_irq_handler_data *handler_data =
 116                 container_of(work, struct amdgpu_dm_irq_handler_data, work);
 117
 118         handler_data->handler(handler_data->handler_arg);
 119
 120         /* Call a DAL subcomponent which registered for interrupt notification
 121          * at INTERRUPT_LOW_IRQ_CONTEXT.
 122          * (The most common use is HPD interrupt) */
 123 }
 124
 125 /*
 126  * Remove a handler and return a pointer to handler list from which the
 127  * handler was removed.
 128  */
 129 static struct list_head *remove_irq_handler(struct amdgpu_device *adev,
 130                                             void *ih,
 131                                             const struct dc_interrupt_params *int_params)
 132 {
 133         struct list_head *hnd_list;
 134         struct list_head *entry, *tmp;
 135         struct amdgpu_dm_irq_handler_data *handler;
 136         unsigned long irq_table_flags;
 137         bool handler_removed = false;
 138         enum dc_irq_source irq_source;
 139
 140         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 141
 142         irq_source = int_params->irq_source;
 143
 144         switch (int_params->int_context) {
 145         case INTERRUPT_HIGH_IRQ_CONTEXT:
 146                 hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
 147                 break;
 148         case INTERRUPT_LOW_IRQ_CONTEXT:
 149         default:
 150                 hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source];
 151                 break;
 152         }
 153
 154         list_for_each_safe(entry, tmp, hnd_list) {
 155
 156                 handler = list_entry(entry, struct amdgpu_dm_irq_handler_data,
 157                                      list);
 158
 159                 if (handler == NULL)
 160                         continue;
 161
 162                 if (ih == handler->handler) {
 163                         /* Found our handler. Remove it from the list. */
 164                         list_del(&handler->list);
 165                         handler_removed = true;
 166                         break;
 167                 }
 168         }
 169
 170         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 171
 172         if (handler_removed == false) {
 173                 /* Not necessarily an error - caller may not
 174                  * know the context. */
 175                 return NULL;
 176         }
 177
 178         kfree(handler);
 179
 180         DRM_DEBUG_KMS(
 181         "DM_IRQ: removed irq handler: %p for: dal_src=%d, irq context=%d\n",
 182                 ih, int_params->irq_source, int_params->int_context);
 183
 184         return hnd_list;
 185 }
 186
 187 static bool
 188 validate_irq_registration_params(struct dc_interrupt_params *int_params,
 189                                  void (*ih)(void *))
 190 {
 191         if (NULL == int_params || NULL == ih) {
 192                 DRM_ERROR("DM_IRQ: invalid input!\n");
 193                 return false;
 194         }
 195
 196         if (int_params->int_context >= INTERRUPT_CONTEXT_NUMBER) {
 197                 DRM_ERROR("DM_IRQ: invalid context: %d!\n",
 198                                 int_params->int_context);
 199                 return false;
 200         }
 201
 202         if (!DAL_VALID_IRQ_SRC_NUM(int_params->irq_source)) {
 203                 DRM_ERROR("DM_IRQ: invalid irq_source: %d!\n",
 204                                 int_params->irq_source);
 205                 return false;
 206         }
 207
 208         return true;
 209 }
 210
 211 static bool validate_irq_unregistration_params(enum dc_irq_source irq_source,
 212                                                irq_handler_idx handler_idx)
 213 {
 214         if (DAL_INVALID_IRQ_HANDLER_IDX == handler_idx) {
 215                 DRM_ERROR("DM_IRQ: invalid handler_idx==NULL!\n");
 216                 return false;
 217         }
 218
 219         if (!DAL_VALID_IRQ_SRC_NUM(irq_source)) {
 220                 DRM_ERROR("DM_IRQ: invalid irq_source:%d!\n", irq_source);
 221                 return false;
 222         }
 223
 224         return true;
 225 }
 226 /******************************************************************************
 227  * Public functions.
 228  *
 229  * Note: caller is responsible for input validation.
 230  *****************************************************************************/
 231
 232 /**
 233  * amdgpu_dm_irq_register_interrupt() - Register a handler within DM.
 234  * @adev: The base driver device containing the DM device.
 235  * @int_params: Interrupt parameters containing the source, and handler context
 236  * @ih: Function pointer to the interrupt handler to register
 237  * @handler_args: Arguments passed to the handler when the interrupt occurs
 238  *
 239  * Register an interrupt handler for the given IRQ source, under the given
 240  * context. The context can either be high or low. High context handlers are
 241  * executed directly within ISR context, while low context is executed within a
 242  * workqueue, thereby allowing operations that sleep.
 243  *
 244  * Registered handlers are called in a FIFO manner, i.e. the most recently
 245  * registered handler will be called first.
 246  *
 247  * Return: Handler data &struct amdgpu_dm_irq_handler_data containing the IRQ
 248  *         source, handler function, and args
 249  */
 250 void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
 251                                        struct dc_interrupt_params *int_params,
 252                                        void (*ih)(void *),
 253                                        void *handler_args)
 254 {
 255         struct list_head *hnd_list;
 256         struct amdgpu_dm_irq_handler_data *handler_data;
 257         unsigned long irq_table_flags;
 258         enum dc_irq_source irq_source;
 259
 260         if (false == validate_irq_registration_params(int_params, ih))
 261                 return DAL_INVALID_IRQ_HANDLER_IDX;
 262
 263         handler_data = kzalloc(sizeof(*handler_data), GFP_KERNEL);
 264         if (!handler_data) {
 265                 DRM_ERROR("DM_IRQ: failed to allocate irq handler!\n");
 266                 return DAL_INVALID_IRQ_HANDLER_IDX;
 267         }
 268
 269         init_handler_common_data(handler_data, ih, handler_args, &adev->dm);
 270
 271         irq_source = int_params->irq_source;
 272
 273         handler_data->irq_source = irq_source;
 274
 275         /* Lock the list, add the handler. */
 276         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 277
 278         switch (int_params->int_context) {
 279         case INTERRUPT_HIGH_IRQ_CONTEXT:
 280                 hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
 281                 break;
 282         case INTERRUPT_LOW_IRQ_CONTEXT:
 283         default:
 284                 hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source];
 285                 INIT_WORK(&handler_data->work, dm_irq_work_func);
 286                 break;
 287         }
 288
 289         list_add_tail(&handler_data->list, hnd_list);
 290
 291         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 292
 293         /* This pointer will be stored by code which requested interrupt
 294          * registration.
 295          * The same pointer will be needed in order to unregister the
 296          * interrupt. */
 297
 298         DRM_DEBUG_KMS(
 299                 "DM_IRQ: added irq handler: %p for: dal_src=%d, irq context=%d\n",
 300                 handler_data,
 301                 irq_source,
 302                 int_params->int_context);
 303
 304         return handler_data;
 305 }
 306
 307 /**
 308  * amdgpu_dm_irq_unregister_interrupt() - Remove a handler from the DM IRQ table
 309  * @adev: The base driver device containing the DM device
 310  * @irq_source: IRQ source to remove the given handler from
 311  * @ih: Function pointer to the interrupt handler to unregister
 312  *
 313  * Go through both low and high context IRQ tables, and find the given handler
 314  * for the given irq source. If found, remove it. Otherwise, do nothing.
 315  */
 316 void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev,
 317                                         enum dc_irq_source irq_source,
 318                                         void *ih)
 319 {
 320         struct list_head *handler_list;
 321         struct dc_interrupt_params int_params;
 322         int i;
 323
 324         if (false == validate_irq_unregistration_params(irq_source, ih))
 325                 return;
 326
 327         memset(&int_params, 0, sizeof(int_params));
 328
 329         int_params.irq_source = irq_source;
 330
 331         for (i = 0; i < INTERRUPT_CONTEXT_NUMBER; i++) {
 332
 333                 int_params.int_context = i;
 334
 335                 handler_list = remove_irq_handler(adev, ih, &int_params);
 336
 337                 if (handler_list != NULL)
 338                         break;
 339         }
 340
 341         if (handler_list == NULL) {
 342                 /* If we got here, it means we searched all irq contexts
 343                  * for this irq source, but the handler was not found. */
 344                 DRM_ERROR(
 345                 "DM_IRQ: failed to find irq handler:%p for irq_source:%d!\n",
 346                         ih, irq_source);
 347         }
 348 }
 349
 350 /**
 351  * amdgpu_dm_irq_init() - Initialize DM IRQ management
 352  * @adev:  The base driver device containing the DM device
 353  *
 354  * Initialize DM's high and low context IRQ tables.
 355  *
 356  * The N by M table contains N IRQ sources, with M
 357  * &struct amdgpu_dm_irq_handler_data hooked together in a linked list. The
 358  * list_heads are initialized here. When an interrupt n is triggered, all m
 359  * handlers are called in sequence, FIFO according to registration order.
 360  *
 361  * The low context table requires special steps to initialize, since handlers
 362  * will be deferred to a workqueue. See &struct irq_list_head.
 363  */
 364 int amdgpu_dm_irq_init(struct amdgpu_device *adev)
 365 {
 366         int src;
 367         struct list_head *lh;
 368
 369         DRM_DEBUG_KMS("DM_IRQ\n");
 370
 371         spin_lock_init(&adev->dm.irq_handler_list_table_lock);
 372
 373         for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
 374                 /* low context handler list init */
 375                 lh = &adev->dm.irq_handler_list_low_tab[src];
 376                 INIT_LIST_HEAD(lh);
 377                 /* high context handler init */
 378                 INIT_LIST_HEAD(&adev->dm.irq_handler_list_high_tab[src]);
 379         }
 380
 381         return 0;
 382 }
 383
 384 /**
 385  * amdgpu_dm_irq_fini() - Tear down DM IRQ management
 386  * @adev: The base driver device containing the DM device
 387  *
 388  * Flush all work within the low context IRQ table.
 389  */
 390 void amdgpu_dm_irq_fini(struct amdgpu_device *adev)
 391 {
 392         int src;
 393         struct list_head *lh;
 394         struct list_head *entry, *tmp;
 395         struct amdgpu_dm_irq_handler_data *handler;
 396         unsigned long irq_table_flags;
 397
 398         DRM_DEBUG_KMS("DM_IRQ: releasing resources.\n");
 399         for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
 400                 DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 401                 /* The handler was removed from the table,
 402                  * it means it is safe to flush all the 'work'
 403                  * (because no code can schedule a new one). */
 404                 lh = &adev->dm.irq_handler_list_low_tab[src];
 405                 DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 406
 407                 if (!list_empty(lh)) {
 408                         list_for_each_safe(entry, tmp, lh) {
 409                                 handler = list_entry(
 410                                         entry,
 411                                         struct amdgpu_dm_irq_handler_data,
 412                                         list);
 413                                 flush_work(&handler->work);
 414                         }
 415                 }
 416         }
 417 }
 418
 419 int amdgpu_dm_irq_suspend(struct amdgpu_device *adev)
 420 {
 421         int src;
 422         struct list_head *hnd_list_h;
 423         struct list_head *hnd_list_l;
 424         unsigned long irq_table_flags;
 425         struct list_head *entry, *tmp;
 426         struct amdgpu_dm_irq_handler_data *handler;
 427
 428         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 429
 430         DRM_DEBUG_KMS("DM_IRQ: suspend\n");
 431
 432         /**
 433          * Disable HW interrupt  for HPD and HPDRX only since FLIP and VBLANK
 434          * will be disabled from manage_dm_interrupts on disable CRTC.
 435          */
 436         for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6RX; src++) {
 437                 hnd_list_l = &adev->dm.irq_handler_list_low_tab[src];
 438                 hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
 439                 if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
 440                         dc_interrupt_set(adev->dm.dc, src, false);
 441
 442                 DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 443
 444                 if (!list_empty(hnd_list_l)) {
 445                         list_for_each_safe (entry, tmp, hnd_list_l) {
 446                                 handler = list_entry(
 447                                         entry,
 448                                         struct amdgpu_dm_irq_handler_data,
 449                                         list);
 450                                 flush_work(&handler->work);
 451                         }
 452                 }
 453                 DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 454         }
 455
 456         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 457         return 0;
 458 }
 459
 460 int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev)
 461 {
 462         int src;
 463         struct list_head *hnd_list_h, *hnd_list_l;
 464         unsigned long irq_table_flags;
 465
 466         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 467
 468         DRM_DEBUG_KMS("DM_IRQ: early resume\n");
 469
 470         /* re-enable short pulse interrupts HW interrupt */
 471         for (src = DC_IRQ_SOURCE_HPD1RX; src <= DC_IRQ_SOURCE_HPD6RX; src++) {
 472                 hnd_list_l = &adev->dm.irq_handler_list_low_tab[src];
 473                 hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
 474                 if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
 475                         dc_interrupt_set(adev->dm.dc, src, true);
 476         }
 477
 478         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 479
 480         return 0;
 481 }
 482
 483 int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev)
 484 {
 485         int src;
 486         struct list_head *hnd_list_h, *hnd_list_l;
 487         unsigned long irq_table_flags;
 488
 489         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 490
 491         DRM_DEBUG_KMS("DM_IRQ: resume\n");
 492
 493         /**
 494          * Renable HW interrupt  for HPD and only since FLIP and VBLANK
 495          * will be enabled from manage_dm_interrupts on enable CRTC.
 496          */
 497         for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6; src++) {
 498                 hnd_list_l = &adev->dm.irq_handler_list_low_tab[src];
 499                 hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
 500                 if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
 501                         dc_interrupt_set(adev->dm.dc, src, true);
 502         }
 503
 504         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 505         return 0;
 506 }
 507
 508 /*
 509  * amdgpu_dm_irq_schedule_work - schedule all work items registered for the
 510  * "irq_source".
 511  */
 512 static void amdgpu_dm_irq_schedule_work(struct amdgpu_device *adev,
 513                                         enum dc_irq_source irq_source)
 514 {
 515         struct  list_head *handler_list = &adev->dm.irq_handler_list_low_tab[irq_source];
 516         struct  amdgpu_dm_irq_handler_data *handler_data;
 517         bool    work_queued = false;
 518
 519         if (list_empty(handler_list))
 520                 return;
 521
 522         list_for_each_entry (handler_data, handler_list, list) {
 523                 if (queue_work(system_highpri_wq, &handler_data->work)) {
 524                         work_queued = true;
 525                         break;
 526                 }
 527         }
 528
 529         if (!work_queued) {
 530                 struct  amdgpu_dm_irq_handler_data *handler_data_add;
 531                 /*get the amdgpu_dm_irq_handler_data of first item pointed by handler_list*/
 532                 handler_data = container_of(handler_list->next, struct amdgpu_dm_irq_handler_data, list);
 533
 534                 /*allocate a new amdgpu_dm_irq_handler_data*/
 535                 handler_data_add = kzalloc(sizeof(*handler_data), GFP_KERNEL);
 536                 if (!handler_data_add) {
 537                         DRM_ERROR("DM_IRQ: failed to allocate irq handler!\n");
 538                         return;
 539                 }
 540
 541                 /*copy new amdgpu_dm_irq_handler_data members from handler_data*/
 542                 handler_data_add->handler       = handler_data->handler;
 543                 handler_data_add->handler_arg   = handler_data->handler_arg;
 544                 handler_data_add->dm            = handler_data->dm;
 545                 handler_data_add->irq_source    = irq_source;
 546
 547                 list_add_tail(&handler_data_add->list, handler_list);
 548
 549                 INIT_WORK(&handler_data_add->work, dm_irq_work_func);
 550
 551                 if (queue_work(system_highpri_wq, &handler_data_add->work))
 552                         DRM_DEBUG("Queued work for handling interrupt from "
 553                                   "display for IRQ source %d\n",
 554                                   irq_source);
 555                 else
 556                         DRM_ERROR("Failed to queue work for handling interrupt "
 557                                   "from display for IRQ source %d\n",
 558                                   irq_source);
 559         }
 560 }
 561
 562 /*
 563  * amdgpu_dm_irq_immediate_work
 564  * Callback high irq work immediately, don't send to work queue
 565  */
 566 static void amdgpu_dm_irq_immediate_work(struct amdgpu_device *adev,
 567                                          enum dc_irq_source irq_source)
 568 {
 569         struct amdgpu_dm_irq_handler_data *handler_data;
 570         unsigned long irq_table_flags;
 571
 572         DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
 573
 574         list_for_each_entry(handler_data,
 575                             &adev->dm.irq_handler_list_high_tab[irq_source],
 576                             list) {
 577                 /* Call a subcomponent which registered for immediate
 578                  * interrupt notification */
 579                 handler_data->handler(handler_data->handler_arg);
 580         }
 581
 582         DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
 583 }
 584
 585 /**
 586  * amdgpu_dm_irq_handler - Generic DM IRQ handler
 587  * @adev: amdgpu base driver device containing the DM device
 588  * @source: Unused
 589  * @entry: Data about the triggered interrupt
 590  *
 591  * Calls all registered high irq work immediately, and schedules work for low
 592  * irq. The DM IRQ table is used to find the corresponding handlers.
 593  */
 594 static int amdgpu_dm_irq_handler(struct amdgpu_device *adev,
 595                                  struct amdgpu_irq_src *source,
 596                                  struct amdgpu_iv_entry *entry)
 597 {
 598
 599         enum dc_irq_source src =
 600                 dc_interrupt_to_irq_source(
 601                         adev->dm.dc,
 602                         entry->src_id,
 603                         entry->src_data[0]);
 604
 605         dc_interrupt_ack(adev->dm.dc, src);
 606
 607         /* Call high irq work immediately */
 608         amdgpu_dm_irq_immediate_work(adev, src);
 609         /*Schedule low_irq work */
 610         amdgpu_dm_irq_schedule_work(adev, src);
 611
 612         return 0;
 613 }
 614
 615 static enum dc_irq_source amdgpu_dm_hpd_to_dal_irq_source(unsigned type)
 616 {
 617         switch (type) {
 618         case AMDGPU_HPD_1:
 619                 return DC_IRQ_SOURCE_HPD1;
 620         case AMDGPU_HPD_2:
 621                 return DC_IRQ_SOURCE_HPD2;
 622         case AMDGPU_HPD_3:
 623                 return DC_IRQ_SOURCE_HPD3;
 624         case AMDGPU_HPD_4:
 625                 return DC_IRQ_SOURCE_HPD4;
 626         case AMDGPU_HPD_5:
 627                 return DC_IRQ_SOURCE_HPD5;
 628         case AMDGPU_HPD_6:
 629                 return DC_IRQ_SOURCE_HPD6;
 630         default:
 631                 return DC_IRQ_SOURCE_INVALID;
 632         }
 633 }
 634
 635 static int amdgpu_dm_set_hpd_irq_state(struct amdgpu_device *adev,
 636                                        struct amdgpu_irq_src *source,
 637                                        unsigned type,
 638                                        enum amdgpu_interrupt_state state)
 639 {
 640         enum dc_irq_source src = amdgpu_dm_hpd_to_dal_irq_source(type);
 641         bool st = (state == AMDGPU_IRQ_STATE_ENABLE);
 642
 643         dc_interrupt_set(adev->dm.dc, src, st);
 644         return 0;
 645 }
 646
 647 static inline int dm_irq_state(struct amdgpu_device *adev,
 648                                struct amdgpu_irq_src *source,
 649                                unsigned crtc_id,
 650                                enum amdgpu_interrupt_state state,
 651                                const enum irq_type dal_irq_type,
 652                                const char *func)
 653 {
 654         bool st;
 655         enum dc_irq_source irq_source;
 656
 657         struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id];
 658
 659         if (!acrtc) {
 660                 DRM_ERROR(
 661                         "%s: crtc is NULL at id :%d\n",
 662                         func,
 663                         crtc_id);
 664                 return 0;
 665         }
 666
 667         if (acrtc->otg_inst == -1)
 668                 return 0;
 669
 670         irq_source = dal_irq_type + acrtc->otg_inst;
 671
 672         st = (state == AMDGPU_IRQ_STATE_ENABLE);
 673
 674         dc_interrupt_set(adev->dm.dc, irq_source, st);
 675         return 0;
 676 }
 677
 678 static int amdgpu_dm_set_pflip_irq_state(struct amdgpu_device *adev,
 679                                          struct amdgpu_irq_src *source,
 680                                          unsigned crtc_id,
 681                                          enum amdgpu_interrupt_state state)
 682 {
 683         return dm_irq_state(
 684                 adev,
 685                 source,
 686                 crtc_id,
 687                 state,
 688                 IRQ_TYPE_PFLIP,
 689                 __func__);
 690 }
 691
 692 static int amdgpu_dm_set_crtc_irq_state(struct amdgpu_device *adev,
 693                                         struct amdgpu_irq_src *source,
 694                                         unsigned crtc_id,
 695                                         enum amdgpu_interrupt_state state)
 696 {
 697         return dm_irq_state(
 698                 adev,
 699                 source,
 700                 crtc_id,
 701                 state,
 702                 IRQ_TYPE_VBLANK,
 703                 __func__);
 704 }
 705
 706 static int amdgpu_dm_set_vline0_irq_state(struct amdgpu_device *adev,
 707                                         struct amdgpu_irq_src *source,
 708                                         unsigned int crtc_id,
 709                                         enum amdgpu_interrupt_state state)
 710 {
 711         return dm_irq_state(
 712                 adev,
 713                 source,
 714                 crtc_id,
 715                 state,
 716                 IRQ_TYPE_VLINE0,
 717                 __func__);
 718 }
 719
 720 static int amdgpu_dm_set_vupdate_irq_state(struct amdgpu_device *adev,
 721                                            struct amdgpu_irq_src *source,
 722                                            unsigned int crtc_id,
 723                                            enum amdgpu_interrupt_state state)
 724 {
 725         return dm_irq_state(
 726                 adev,
 727                 source,
 728                 crtc_id,
 729                 state,
 730                 IRQ_TYPE_VUPDATE,
 731                 __func__);
 732 }
 733
 734 static const struct amdgpu_irq_src_funcs dm_crtc_irq_funcs = {
 735         .set = amdgpu_dm_set_crtc_irq_state,
 736         .process = amdgpu_dm_irq_handler,
 737 };
 738
 739 static const struct amdgpu_irq_src_funcs dm_vline0_irq_funcs = {
 740         .set = amdgpu_dm_set_vline0_irq_state,
 741         .process = amdgpu_dm_irq_handler,
 742 };
 743
 744 static const struct amdgpu_irq_src_funcs dm_vupdate_irq_funcs = {
 745         .set = amdgpu_dm_set_vupdate_irq_state,
 746         .process = amdgpu_dm_irq_handler,
 747 };
 748
 749 static const struct amdgpu_irq_src_funcs dm_pageflip_irq_funcs = {
 750         .set = amdgpu_dm_set_pflip_irq_state,
 751         .process = amdgpu_dm_irq_handler,
 752 };
 753
 754 static const struct amdgpu_irq_src_funcs dm_hpd_irq_funcs = {
 755         .set = amdgpu_dm_set_hpd_irq_state,
 756         .process = amdgpu_dm_irq_handler,
 757 };
 758
 759 void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev)
 760 {
 761
 762         adev->crtc_irq.num_types = adev->mode_info.num_crtc;
 763         adev->crtc_irq.funcs = &dm_crtc_irq_funcs;
 764
 765         adev->vline0_irq.num_types = adev->mode_info.num_crtc;
 766         adev->vline0_irq.funcs = &dm_vline0_irq_funcs;
 767
 768         adev->vupdate_irq.num_types = adev->mode_info.num_crtc;
 769         adev->vupdate_irq.funcs = &dm_vupdate_irq_funcs;
 770
 771         adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
 772         adev->pageflip_irq.funcs = &dm_pageflip_irq_funcs;
 773
 774         adev->hpd_irq.num_types = adev->mode_info.num_hpd;
 775         adev->hpd_irq.funcs = &dm_hpd_irq_funcs;
 776 }
 777
 778 /**
 779  * amdgpu_dm_hpd_init - hpd setup callback.
 780  *
 781  * @adev: amdgpu_device pointer
 782  *
 783  * Setup the hpd pins used by the card (evergreen+).
 784  * Enable the pin, set the polarity, and enable the hpd interrupts.
 785  */
 786 void amdgpu_dm_hpd_init(struct amdgpu_device *adev)
 787 {
 788         struct drm_device *dev = adev_to_drm(adev);
 789         struct drm_connector *connector;
 790         struct drm_connector_list_iter iter;
 791
 792         drm_connector_list_iter_begin(dev, &iter);
 793         drm_for_each_connector_iter(connector, &iter) {
 794                 struct amdgpu_dm_connector *amdgpu_dm_connector =
 795                                 to_amdgpu_dm_connector(connector);
 796
 797                 const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
 798
 799                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
 800                         dc_interrupt_set(adev->dm.dc,
 801                                         dc_link->irq_source_hpd,
 802                                         true);
 803                 }
 804
 805                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
 806                         dc_interrupt_set(adev->dm.dc,
 807                                         dc_link->irq_source_hpd_rx,
 808                                         true);
 809                 }
 810         }
 811         drm_connector_list_iter_end(&iter);
 812 }
 813
 814 /**
 815  * amdgpu_dm_hpd_fini - hpd tear down callback.
 816  *
 817  * @adev: amdgpu_device pointer
 818  *
 819  * Tear down the hpd pins used by the card (evergreen+).
 820  * Disable the hpd interrupts.
 821  */
 822 void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)
 823 {
 824         struct drm_device *dev = adev_to_drm(adev);
 825         struct drm_connector *connector;
 826         struct drm_connector_list_iter iter;
 827
 828         drm_connector_list_iter_begin(dev, &iter);
 829         drm_for_each_connector_iter(connector, &iter) {
 830                 struct amdgpu_dm_connector *amdgpu_dm_connector =
 831                                 to_amdgpu_dm_connector(connector);
 832                 const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
 833
 834                 dc_interrupt_set(adev->dm.dc, dc_link->irq_source_hpd, false);
 835
 836                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
 837                         dc_interrupt_set(adev->dm.dc,
 838                                         dc_link->irq_source_hpd_rx,
 839                                         false);
 840                 }
 841         }
 842         drm_connector_list_iter_end(&iter);
 843 }