drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/uaccess.h>
  27
  28 #include "dc.h"
  29 #include "amdgpu.h"
  30 #include "amdgpu_dm.h"
  31 #include "amdgpu_dm_debugfs.h"
  32 #include "dm_helpers.h"
  33 #include "dmub/dmub_srv.h"
  34 #include "resource.h"
  35 #include "dsc.h"
  36 #include "dc_link_dp.h"
  37 #include "dc/dc_dmub_srv.h"
  38
  39 struct dmub_debugfs_trace_header {
  40         uint32_t entry_count;
  41         uint32_t reserved[3];
  42 };
  43
  44 struct dmub_debugfs_trace_entry {
  45         uint32_t trace_code;
  46         uint32_t tick_count;
  47         uint32_t param0;
  48         uint32_t param1;
  49 };
  50
  51 static inline const char *yesno(bool v)
  52 {
  53         return v ? "yes" : "no";
  54 }
  55
  56 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
  57  *
  58  * Function takes in attributes passed to debugfs write entry
  59  * and writes into param array.
  60  * The user passes max_param_num to identify maximum number of
  61  * parameters that could be parsed.
  62  *
  63  */
  64 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,
  65                                           long *param, const char __user *buf,
  66                                           int max_param_num,
  67                                           uint8_t *param_nums)
  68 {
  69         char *wr_buf_ptr = NULL;
  70         uint32_t wr_buf_count = 0;
  71         int r;
  72         char *sub_str = NULL;
  73         const char delimiter[3] = {' ', '\n', '\0'};
  74         uint8_t param_index = 0;
  75
  76         *param_nums = 0;
  77
  78         wr_buf_ptr = wr_buf;
  79
  80         r = copy_from_user(wr_buf_ptr, buf, wr_buf_size);
  81
  82                 /* r is bytes not be copied */
  83         if (r >= wr_buf_size) {
  84                 DRM_DEBUG_DRIVER("user data not be read\n");
  85                 return -EINVAL;
  86         }
  87
  88         /* check number of parameters. isspace could not differ space and \n */
  89         while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
  90                 /* skip space*/
  91                 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
  92                         wr_buf_ptr++;
  93                         wr_buf_count++;
  94                         }
  95
  96                 if (wr_buf_count == wr_buf_size)
  97                         break;
  98
  99                 /* skip non-space*/
 100                 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
 101                         wr_buf_ptr++;
 102                         wr_buf_count++;
 103                 }
 104
 105                 (*param_nums)++;
 106
 107                 if (wr_buf_count == wr_buf_size)
 108                         break;
 109         }
 110
 111         if (*param_nums > max_param_num)
 112                 *param_nums = max_param_num;
 113
 114         wr_buf_ptr = wr_buf; /* reset buf pointer */
 115         wr_buf_count = 0; /* number of char already checked */
 116
 117         while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
 118                 wr_buf_ptr++;
 119                 wr_buf_count++;
 120         }
 121
 122         while (param_index < *param_nums) {
 123                 /* after strsep, wr_buf_ptr will be moved to after space */
 124                 sub_str = strsep(&wr_buf_ptr, delimiter);
 125
 126                 r = kstrtol(sub_str, 16, &(param[param_index]));
 127
 128                 if (r)
 129                         DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
 130
 131                 param_index++;
 132         }
 133
 134         return 0;
 135 }
 136
 137 /* function description
 138  * get/ set DP configuration: lane_count, link_rate, spread_spectrum
 139  *
 140  * valid lane count value: 1, 2, 4
 141  * valid link rate value:
 142  * 06h = 1.62Gbps per lane
 143  * 0Ah = 2.7Gbps per lane
 144  * 0Ch = 3.24Gbps per lane
 145  * 14h = 5.4Gbps per lane
 146  * 1Eh = 8.1Gbps per lane
 147  *
 148  * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
 149  *
 150  * --- to get dp configuration
 151  *
 152  * cat link_settings
 153  *
 154  * It will list current, verified, reported, preferred dp configuration.
 155  * current -- for current video mode
 156  * verified --- maximum configuration which pass link training
 157  * reported --- DP rx report caps (DPCD register offset 0, 1 2)
 158  * preferred --- user force settings
 159  *
 160  * --- set (or force) dp configuration
 161  *
 162  * echo <lane_count>  <link_rate> > link_settings
 163  *
 164  * for example, to force to  2 lane, 2.7GHz,
 165  * echo 4 0xa > link_settings
 166  *
 167  * spread_spectrum could not be changed dynamically.
 168  *
 169  * in case invalid lane count, link rate are force, no hw programming will be
 170  * done. please check link settings after force operation to see if HW get
 171  * programming.
 172  *
 173  * cat link_settings
 174  *
 175  * check current and preferred settings.
 176  *
 177  */
 178 static ssize_t dp_link_settings_read(struct file *f, char __user *buf,
 179                                  size_t size, loff_t *pos)
 180 {
 181         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 182         struct dc_link *link = connector->dc_link;
 183         char *rd_buf = NULL;
 184         char *rd_buf_ptr = NULL;
 185         const uint32_t rd_buf_size = 100;
 186         uint32_t result = 0;
 187         uint8_t str_len = 0;
 188         int r;
 189
 190         if (*pos & 3 || size & 3)
 191                 return -EINVAL;
 192
 193         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 194         if (!rd_buf)
 195                 return 0;
 196
 197         rd_buf_ptr = rd_buf;
 198
 199         str_len = strlen("Current:  %d  %d  %d  ");
 200         snprintf(rd_buf_ptr, str_len, "Current:  %d  %d  %d  ",
 201                         link->cur_link_settings.lane_count,
 202                         link->cur_link_settings.link_rate,
 203                         link->cur_link_settings.link_spread);
 204         rd_buf_ptr += str_len;
 205
 206         str_len = strlen("Verified:  %d  %d  %d  ");
 207         snprintf(rd_buf_ptr, str_len, "Verified:  %d  %d  %d  ",
 208                         link->verified_link_cap.lane_count,
 209                         link->verified_link_cap.link_rate,
 210                         link->verified_link_cap.link_spread);
 211         rd_buf_ptr += str_len;
 212
 213         str_len = strlen("Reported:  %d  %d  %d  ");
 214         snprintf(rd_buf_ptr, str_len, "Reported:  %d  %d  %d  ",
 215                         link->reported_link_cap.lane_count,
 216                         link->reported_link_cap.link_rate,
 217                         link->reported_link_cap.link_spread);
 218         rd_buf_ptr += str_len;
 219
 220         str_len = strlen("Preferred:  %d  %d  %d  ");
 221         snprintf(rd_buf_ptr, str_len, "Preferred:  %d  %d  %d\n",
 222                         link->preferred_link_setting.lane_count,
 223                         link->preferred_link_setting.link_rate,
 224                         link->preferred_link_setting.link_spread);
 225
 226         while (size) {
 227                 if (*pos >= rd_buf_size)
 228                         break;
 229
 230                 r = put_user(*(rd_buf + result), buf);
 231                 if (r)
 232                         return r; /* r = -EFAULT */
 233
 234                 buf += 1;
 235                 size -= 1;
 236                 *pos += 1;
 237                 result += 1;
 238         }
 239
 240         kfree(rd_buf);
 241         return result;
 242 }
 243
 244 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
 245                                  size_t size, loff_t *pos)
 246 {
 247         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 248         struct dc_link *link = connector->dc_link;
 249         struct dc *dc = (struct dc *)link->dc;
 250         struct dc_link_settings prefer_link_settings;
 251         char *wr_buf = NULL;
 252         const uint32_t wr_buf_size = 40;
 253         /* 0: lane_count; 1: link_rate */
 254         int max_param_num = 2;
 255         uint8_t param_nums = 0;
 256         long param[2];
 257         bool valid_input = false;
 258
 259         if (size == 0)
 260                 return -EINVAL;
 261
 262         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 263         if (!wr_buf)
 264                 return -ENOSPC;
 265
 266         if (parse_write_buffer_into_params(wr_buf, size,
 267                                            (long *)param, buf,
 268                                            max_param_num,
 269                                            &param_nums)) {
 270                 kfree(wr_buf);
 271                 return -EINVAL;
 272         }
 273
 274         if (param_nums <= 0) {
 275                 kfree(wr_buf);
 276                 DRM_DEBUG_DRIVER("user data not be read\n");
 277                 return -EINVAL;
 278         }
 279
 280         switch (param[0]) {
 281         case LANE_COUNT_ONE:
 282         case LANE_COUNT_TWO:
 283         case LANE_COUNT_FOUR:
 284                 valid_input = true;
 285                 break;
 286         default:
 287                 break;
 288         }
 289
 290         switch (param[1]) {
 291         case LINK_RATE_LOW:
 292         case LINK_RATE_HIGH:
 293         case LINK_RATE_RBR2:
 294         case LINK_RATE_HIGH2:
 295         case LINK_RATE_HIGH3:
 296                 valid_input = true;
 297                 break;
 298         default:
 299                 break;
 300         }
 301
 302         if (!valid_input) {
 303                 kfree(wr_buf);
 304                 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
 305                 return size;
 306         }
 307
 308         /* save user force lane_count, link_rate to preferred settings
 309          * spread spectrum will not be changed
 310          */
 311         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
 312         prefer_link_settings.lane_count = param[0];
 313         prefer_link_settings.link_rate = param[1];
 314
 315         dc_link_set_preferred_link_settings(dc, &prefer_link_settings, link);
 316
 317         kfree(wr_buf);
 318         return size;
 319 }
 320
 321 /* function: get current DP PHY settings: voltage swing, pre-emphasis,
 322  * post-cursor2 (defined by VESA DP specification)
 323  *
 324  * valid values
 325  * voltage swing: 0,1,2,3
 326  * pre-emphasis : 0,1,2,3
 327  * post cursor2 : 0,1,2,3
 328  *
 329  *
 330  * how to use this debugfs
 331  *
 332  * debugfs is located at /sys/kernel/debug/dri/0/DP-x
 333  *
 334  * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display
 335  *
 336  * To figure out which DP-x is the display for DP to be check,
 337  * cd DP-x
 338  * ls -ll
 339  * There should be debugfs file, like link_settings, phy_settings.
 340  * cat link_settings
 341  * from lane_count, link_rate to figure which DP-x is for display to be worked
 342  * on
 343  *
 344  * To get current DP PHY settings,
 345  * cat phy_settings
 346  *
 347  * To change DP PHY settings,
 348  * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings
 349  * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to
 350  * 0,
 351  * echo 2 3 0 > phy_settings
 352  *
 353  * To check if change be applied, get current phy settings by
 354  * cat phy_settings
 355  *
 356  * In case invalid values are set by user, like
 357  * echo 1 4 0 > phy_settings
 358  *
 359  * HW will NOT be programmed by these settings.
 360  * cat phy_settings will show the previous valid settings.
 361  */
 362 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,
 363                                  size_t size, loff_t *pos)
 364 {
 365         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 366         struct dc_link *link = connector->dc_link;
 367         char *rd_buf = NULL;
 368         const uint32_t rd_buf_size = 20;
 369         uint32_t result = 0;
 370         int r;
 371
 372         if (*pos & 3 || size & 3)
 373                 return -EINVAL;
 374
 375         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 376         if (!rd_buf)
 377                 return -EINVAL;
 378
 379         snprintf(rd_buf, rd_buf_size, "  %d  %d  %d  ",
 380                         link->cur_lane_setting.VOLTAGE_SWING,
 381                         link->cur_lane_setting.PRE_EMPHASIS,
 382                         link->cur_lane_setting.POST_CURSOR2);
 383
 384         while (size) {
 385                 if (*pos >= rd_buf_size)
 386                         break;
 387
 388                 r = put_user((*(rd_buf + result)), buf);
 389                 if (r)
 390                         return r; /* r = -EFAULT */
 391
 392                 buf += 1;
 393                 size -= 1;
 394                 *pos += 1;
 395                 result += 1;
 396         }
 397
 398         kfree(rd_buf);
 399         return result;
 400 }
 401
 402 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
 403                                  size_t size, loff_t *pos)
 404 {
 405         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 406         struct dc_link *link = connector->dc_link;
 407         struct dc *dc = (struct dc *)link->dc;
 408         char *wr_buf = NULL;
 409         uint32_t wr_buf_size = 40;
 410         long param[3];
 411         bool use_prefer_link_setting;
 412         struct link_training_settings link_lane_settings;
 413         int max_param_num = 3;
 414         uint8_t param_nums = 0;
 415         int r = 0;
 416
 417
 418         if (size == 0)
 419                 return -EINVAL;
 420
 421         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 422         if (!wr_buf)
 423                 return -ENOSPC;
 424
 425         if (parse_write_buffer_into_params(wr_buf, size,
 426                                            (long *)param, buf,
 427                                            max_param_num,
 428                                            &param_nums)) {
 429                 kfree(wr_buf);
 430                 return -EINVAL;
 431         }
 432
 433         if (param_nums <= 0) {
 434                 kfree(wr_buf);
 435                 DRM_DEBUG_DRIVER("user data not be read\n");
 436                 return -EINVAL;
 437         }
 438
 439         if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) ||
 440                         (param[1] > PRE_EMPHASIS_MAX_LEVEL) ||
 441                         (param[2] > POST_CURSOR2_MAX_LEVEL)) {
 442                 kfree(wr_buf);
 443                 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n");
 444                 return size;
 445         }
 446
 447         /* get link settings: lane count, link rate */
 448         use_prefer_link_setting =
 449                 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) &&
 450                 (link->test_pattern_enabled));
 451
 452         memset(&link_lane_settings, 0, sizeof(link_lane_settings));
 453
 454         if (use_prefer_link_setting) {
 455                 link_lane_settings.link_settings.lane_count =
 456                                 link->preferred_link_setting.lane_count;
 457                 link_lane_settings.link_settings.link_rate =
 458                                 link->preferred_link_setting.link_rate;
 459                 link_lane_settings.link_settings.link_spread =
 460                                 link->preferred_link_setting.link_spread;
 461         } else {
 462                 link_lane_settings.link_settings.lane_count =
 463                                 link->cur_link_settings.lane_count;
 464                 link_lane_settings.link_settings.link_rate =
 465                                 link->cur_link_settings.link_rate;
 466                 link_lane_settings.link_settings.link_spread =
 467                                 link->cur_link_settings.link_spread;
 468         }
 469
 470         /* apply phy settings from user */
 471         for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
 472                 link_lane_settings.lane_settings[r].VOLTAGE_SWING =
 473                                 (enum dc_voltage_swing) (param[0]);
 474                 link_lane_settings.lane_settings[r].PRE_EMPHASIS =
 475                                 (enum dc_pre_emphasis) (param[1]);
 476                 link_lane_settings.lane_settings[r].POST_CURSOR2 =
 477                                 (enum dc_post_cursor2) (param[2]);
 478         }
 479
 480         /* program ASIC registers and DPCD registers */
 481         dc_link_set_drive_settings(dc, &link_lane_settings, link);
 482
 483         kfree(wr_buf);
 484         return size;
 485 }
 486
 487 /* function description
 488  *
 489  * set PHY layer or Link layer test pattern
 490  * PHY test pattern is used for PHY SI check.
 491  * Link layer test will not affect PHY SI.
 492  *
 493  * Reset Test Pattern:
 494  * 0 = DP_TEST_PATTERN_VIDEO_MODE
 495  *
 496  * PHY test pattern supported:
 497  * 1 = DP_TEST_PATTERN_D102
 498  * 2 = DP_TEST_PATTERN_SYMBOL_ERROR
 499  * 3 = DP_TEST_PATTERN_PRBS7
 500  * 4 = DP_TEST_PATTERN_80BIT_CUSTOM
 501  * 5 = DP_TEST_PATTERN_CP2520_1
 502  * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
 503  * 7 = DP_TEST_PATTERN_CP2520_3
 504  *
 505  * DP PHY Link Training Patterns
 506  * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1
 507  * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2
 508  * a = DP_TEST_PATTERN_TRAINING_PATTERN3
 509  * b = DP_TEST_PATTERN_TRAINING_PATTERN4
 510  *
 511  * DP Link Layer Test pattern
 512  * c = DP_TEST_PATTERN_COLOR_SQUARES
 513  * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA
 514  * e = DP_TEST_PATTERN_VERTICAL_BARS
 515  * f = DP_TEST_PATTERN_HORIZONTAL_BARS
 516  * 10= DP_TEST_PATTERN_COLOR_RAMP
 517  *
 518  * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x
 519  *
 520  * --- set test pattern
 521  * echo <test pattern #> > test_pattern
 522  *
 523  * If test pattern # is not supported, NO HW programming will be done.
 524  * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
 525  * for the user pattern. input 10 bytes data are separated by space
 526  *
 527  * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern
 528  *
 529  * --- reset test pattern
 530  * echo 0 > test_pattern
 531  *
 532  * --- HPD detection is disabled when set PHY test pattern
 533  *
 534  * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC
 535  * is disable. User could unplug DP display from DP connected and plug scope to
 536  * check test pattern PHY SI.
 537  * If there is need unplug scope and plug DP display back, do steps below:
 538  * echo 0 > phy_test_pattern
 539  * unplug scope
 540  * plug DP display.
 541  *
 542  * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw
 543  * driver could detect "unplug scope" and "plug DP display"
 544  */
 545 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf,
 546                                  size_t size, loff_t *pos)
 547 {
 548         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 549         struct dc_link *link = connector->dc_link;
 550         char *wr_buf = NULL;
 551         uint32_t wr_buf_size = 100;
 552         long param[11] = {0x0};
 553         int max_param_num = 11;
 554         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 555         bool disable_hpd = false;
 556         bool valid_test_pattern = false;
 557         uint8_t param_nums = 0;
 558         /* init with default 80bit custom pattern */
 559         uint8_t custom_pattern[10] = {
 560                         0x1f, 0x7c, 0xf0, 0xc1, 0x07,
 561                         0x1f, 0x7c, 0xf0, 0xc1, 0x07
 562                         };
 563         struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN,
 564                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 565         struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN,
 566                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 567         struct link_training_settings link_training_settings;
 568         int i;
 569
 570         if (size == 0)
 571                 return -EINVAL;
 572
 573         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 574         if (!wr_buf)
 575                 return -ENOSPC;
 576
 577         if (parse_write_buffer_into_params(wr_buf, size,
 578                                            (long *)param, buf,
 579                                            max_param_num,
 580                                            &param_nums)) {
 581                 kfree(wr_buf);
 582                 return -EINVAL;
 583         }
 584
 585         if (param_nums <= 0) {
 586                 kfree(wr_buf);
 587                 DRM_DEBUG_DRIVER("user data not be read\n");
 588                 return -EINVAL;
 589         }
 590
 591
 592         test_pattern = param[0];
 593
 594         switch (test_pattern) {
 595         case DP_TEST_PATTERN_VIDEO_MODE:
 596         case DP_TEST_PATTERN_COLOR_SQUARES:
 597         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
 598         case DP_TEST_PATTERN_VERTICAL_BARS:
 599         case DP_TEST_PATTERN_HORIZONTAL_BARS:
 600         case DP_TEST_PATTERN_COLOR_RAMP:
 601                 valid_test_pattern = true;
 602                 break;
 603
 604         case DP_TEST_PATTERN_D102:
 605         case DP_TEST_PATTERN_SYMBOL_ERROR:
 606         case DP_TEST_PATTERN_PRBS7:
 607         case DP_TEST_PATTERN_80BIT_CUSTOM:
 608         case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
 609         case DP_TEST_PATTERN_TRAINING_PATTERN4:
 610                 disable_hpd = true;
 611                 valid_test_pattern = true;
 612                 break;
 613
 614         default:
 615                 valid_test_pattern = false;
 616                 test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 617                 break;
 618         }
 619
 620         if (!valid_test_pattern) {
 621                 kfree(wr_buf);
 622                 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n");
 623                 return size;
 624         }
 625
 626         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
 627                 for (i = 0; i < 10; i++) {
 628                         if ((uint8_t) param[i + 1] != 0x0)
 629                                 break;
 630                 }
 631
 632                 if (i < 10) {
 633                         /* not use default value */
 634                         for (i = 0; i < 10; i++)
 635                                 custom_pattern[i] = (uint8_t) param[i + 1];
 636                 }
 637         }
 638
 639         /* Usage: set DP physical test pattern using debugfs with normal DP
 640          * panel. Then plug out DP panel and connect a scope to measure
 641          * For normal video mode and test pattern generated from CRCT,
 642          * they are visibile to user. So do not disable HPD.
 643          * Video Mode is also set to clear the test pattern, so enable HPD
 644          * because it might have been disabled after a test pattern was set.
 645          * AUX depends on HPD * sequence dependent, do not move!
 646          */
 647         if (!disable_hpd)
 648                 dc_link_enable_hpd(link);
 649
 650         prefer_link_settings.lane_count = link->verified_link_cap.lane_count;
 651         prefer_link_settings.link_rate = link->verified_link_cap.link_rate;
 652         prefer_link_settings.link_spread = link->verified_link_cap.link_spread;
 653
 654         cur_link_settings.lane_count = link->cur_link_settings.lane_count;
 655         cur_link_settings.link_rate = link->cur_link_settings.link_rate;
 656         cur_link_settings.link_spread = link->cur_link_settings.link_spread;
 657
 658         link_training_settings.link_settings = cur_link_settings;
 659
 660
 661         if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
 662                 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN &&
 663                         prefer_link_settings.link_rate !=  LINK_RATE_UNKNOWN &&
 664                         (prefer_link_settings.lane_count != cur_link_settings.lane_count ||
 665                         prefer_link_settings.link_rate != cur_link_settings.link_rate))
 666                         link_training_settings.link_settings = prefer_link_settings;
 667         }
 668
 669         for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
 670                 link_training_settings.lane_settings[i] = link->cur_lane_setting;
 671
 672         dc_link_set_test_pattern(
 673                 link,
 674                 test_pattern,
 675                 DP_TEST_PATTERN_COLOR_SPACE_RGB,
 676                 &link_training_settings,
 677                 custom_pattern,
 678                 10);
 679
 680         /* Usage: Set DP physical test pattern using AMDDP with normal DP panel
 681          * Then plug out DP panel and connect a scope to measure DP PHY signal.
 682          * Need disable interrupt to avoid SW driver disable DP output. This is
 683          * done after the test pattern is set.
 684          */
 685         if (valid_test_pattern && disable_hpd)
 686                 dc_link_disable_hpd(link);
 687
 688         kfree(wr_buf);
 689
 690         return size;
 691 }
 692
 693 /*
 694  * Returns the DMCUB tracebuffer contents.
 695  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
 696  */
 697 static int dmub_tracebuffer_show(struct seq_file *m, void *data)
 698 {
 699         struct amdgpu_device *adev = m->private;
 700         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 701         struct dmub_debugfs_trace_entry *entries;
 702         uint8_t *tbuf_base;
 703         uint32_t tbuf_size, max_entries, num_entries, i;
 704
 705         if (!fb_info)
 706                 return 0;
 707
 708         tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;
 709         if (!tbuf_base)
 710                 return 0;
 711
 712         tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size;
 713         max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /
 714                       sizeof(struct dmub_debugfs_trace_entry);
 715
 716         num_entries =
 717                 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count;
 718
 719         num_entries = min(num_entries, max_entries);
 720
 721         entries = (struct dmub_debugfs_trace_entry
 722                            *)(tbuf_base +
 723                               sizeof(struct dmub_debugfs_trace_header));
 724
 725         for (i = 0; i < num_entries; ++i) {
 726                 struct dmub_debugfs_trace_entry *entry = &entries[i];
 727
 728                 seq_printf(m,
 729                            "trace_code=%u tick_count=%u param0=%u param1=%u\n",
 730                            entry->trace_code, entry->tick_count, entry->param0,
 731                            entry->param1);
 732         }
 733
 734         return 0;
 735 }
 736
 737 /*
 738  * Returns the DMCUB firmware state contents.
 739  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state
 740  */
 741 static int dmub_fw_state_show(struct seq_file *m, void *data)
 742 {
 743         struct amdgpu_device *adev = m->private;
 744         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 745         uint8_t *state_base;
 746         uint32_t state_size;
 747
 748         if (!fb_info)
 749                 return 0;
 750
 751         state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr;
 752         if (!state_base)
 753                 return 0;
 754
 755         state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size;
 756
 757         return seq_write(m, state_base, state_size);
 758 }
 759
 760 /*
 761  * Returns the current and maximum output bpc for the connector.
 762  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/output_bpc
 763  */
 764 static int output_bpc_show(struct seq_file *m, void *data)
 765 {
 766         struct drm_connector *connector = m->private;
 767         struct drm_device *dev = connector->dev;
 768         struct drm_crtc *crtc = NULL;
 769         struct dm_crtc_state *dm_crtc_state = NULL;
 770         int res = -ENODEV;
 771         unsigned int bpc;
 772
 773         mutex_lock(&dev->mode_config.mutex);
 774         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 775
 776         if (connector->state == NULL)
 777                 goto unlock;
 778
 779         crtc = connector->state->crtc;
 780         if (crtc == NULL)
 781                 goto unlock;
 782
 783         drm_modeset_lock(&crtc->mutex, NULL);
 784         if (crtc->state == NULL)
 785                 goto unlock;
 786
 787         dm_crtc_state = to_dm_crtc_state(crtc->state);
 788         if (dm_crtc_state->stream == NULL)
 789                 goto unlock;
 790
 791         switch (dm_crtc_state->stream->timing.display_color_depth) {
 792         case COLOR_DEPTH_666:
 793                 bpc = 6;
 794                 break;
 795         case COLOR_DEPTH_888:
 796                 bpc = 8;
 797                 break;
 798         case COLOR_DEPTH_101010:
 799                 bpc = 10;
 800                 break;
 801         case COLOR_DEPTH_121212:
 802                 bpc = 12;
 803                 break;
 804         case COLOR_DEPTH_161616:
 805                 bpc = 16;
 806                 break;
 807         default:
 808                 goto unlock;
 809         }
 810
 811         seq_printf(m, "Current: %u\n", bpc);
 812         seq_printf(m, "Maximum: %u\n", connector->display_info.bpc);
 813         res = 0;
 814
 815 unlock:
 816         if (crtc)
 817                 drm_modeset_unlock(&crtc->mutex);
 818
 819         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 820         mutex_unlock(&dev->mode_config.mutex);
 821
 822         return res;
 823 }
 824
 825 #ifdef CONFIG_DRM_AMD_DC_HDCP
 826 /*
 827  * Returns the HDCP capability of the Display (1.4 for now).
 828  *
 829  * NOTE* Not all HDMI displays report their HDCP caps even when they are capable.
 830  * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable.
 831  *
 832  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability
 833  *              or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability
 834  */
 835 static int hdcp_sink_capability_show(struct seq_file *m, void *data)
 836 {
 837         struct drm_connector *connector = m->private;
 838         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 839         bool hdcp_cap, hdcp2_cap;
 840
 841         if (connector->status != connector_status_connected)
 842                 return -ENODEV;
 843
 844         seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id);
 845
 846         hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal);
 847         hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal);
 848
 849
 850         if (hdcp_cap)
 851                 seq_printf(m, "%s ", "HDCP1.4");
 852         if (hdcp2_cap)
 853                 seq_printf(m, "%s ", "HDCP2.2");
 854
 855         if (!hdcp_cap && !hdcp2_cap)
 856                 seq_printf(m, "%s ", "None");
 857
 858         seq_puts(m, "\n");
 859
 860         return 0;
 861 }
 862 #endif
 863 /* function description
 864  *
 865  * generic SDP message access for testing
 866  *
 867  * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x
 868  *
 869  * SDP header
 870  * Hb0 : Secondary-Data Packet ID
 871  * Hb1 : Secondary-Data Packet type
 872  * Hb2 : Secondary-Data-packet-specific header, Byte 0
 873  * Hb3 : Secondary-Data-packet-specific header, Byte 1
 874  *
 875  * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data
 876  */
 877 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf,
 878                                  size_t size, loff_t *pos)
 879 {
 880         int r;
 881         uint8_t data[36];
 882         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 883         struct dm_crtc_state *acrtc_state;
 884         uint32_t write_size = 36;
 885
 886         if (connector->base.status != connector_status_connected)
 887                 return -ENODEV;
 888
 889         if (size == 0)
 890                 return 0;
 891
 892         acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state);
 893
 894         r = copy_from_user(data, buf, write_size);
 895
 896         write_size -= r;
 897
 898         dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size);
 899
 900         return write_size;
 901 }
 902
 903 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf,
 904                                  size_t size, loff_t *pos)
 905 {
 906         int r;
 907         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 908
 909         if (size < sizeof(connector->debugfs_dpcd_address))
 910                 return -EINVAL;
 911
 912         r = copy_from_user(&connector->debugfs_dpcd_address,
 913                         buf, sizeof(connector->debugfs_dpcd_address));
 914
 915         return size - r;
 916 }
 917
 918 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf,
 919                                  size_t size, loff_t *pos)
 920 {
 921         int r;
 922         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 923
 924         if (size < sizeof(connector->debugfs_dpcd_size))
 925                 return -EINVAL;
 926
 927         r = copy_from_user(&connector->debugfs_dpcd_size,
 928                         buf, sizeof(connector->debugfs_dpcd_size));
 929
 930         if (connector->debugfs_dpcd_size > 256)
 931                 connector->debugfs_dpcd_size = 0;
 932
 933         return size - r;
 934 }
 935
 936 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf,
 937                                  size_t size, loff_t *pos)
 938 {
 939         int r;
 940         char *data;
 941         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 942         struct dc_link *link = connector->dc_link;
 943         uint32_t write_size = connector->debugfs_dpcd_size;
 944
 945         if (!write_size || size < write_size)
 946                 return -EINVAL;
 947
 948         data = kzalloc(write_size, GFP_KERNEL);
 949         if (!data)
 950                 return 0;
 951
 952         r = copy_from_user(data, buf, write_size);
 953
 954         dm_helpers_dp_write_dpcd(link->ctx, link,
 955                         connector->debugfs_dpcd_address, data, write_size - r);
 956         kfree(data);
 957         return write_size - r;
 958 }
 959
 960 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf,
 961                                  size_t size, loff_t *pos)
 962 {
 963         int r;
 964         char *data;
 965         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 966         struct dc_link *link = connector->dc_link;
 967         uint32_t read_size = connector->debugfs_dpcd_size;
 968
 969         if (!read_size || size < read_size)
 970                 return 0;
 971
 972         data = kzalloc(read_size, GFP_KERNEL);
 973         if (!data)
 974                 return 0;
 975
 976         dm_helpers_dp_read_dpcd(link->ctx, link,
 977                         connector->debugfs_dpcd_address, data, read_size);
 978
 979         r = copy_to_user(buf, data, read_size);
 980
 981         kfree(data);
 982         return read_size - r;
 983 }
 984
 985 /* function: Read link's DSC & FEC capabilities
 986  *
 987  *
 988  * Access it with the following command (you need to specify
 989  * connector like DP-1):
 990  *
 991  *      cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support
 992  *
 993  */
 994 static int dp_dsc_fec_support_show(struct seq_file *m, void *data)
 995 {
 996         struct drm_connector *connector = m->private;
 997         struct drm_modeset_acquire_ctx ctx;
 998         struct drm_device *dev = connector->dev;
 999         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1000         int ret = 0;
1001         bool try_again = false;
1002         bool is_fec_supported = false;
1003         bool is_dsc_supported = false;
1004         struct dpcd_caps dpcd_caps;
1005
1006         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1007         do {
1008                 try_again = false;
1009                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
1010                 if (ret) {
1011                         if (ret == -EDEADLK) {
1012                                 ret = drm_modeset_backoff(&ctx);
1013                                 if (!ret) {
1014                                         try_again = true;
1015                                         continue;
1016                                 }
1017                         }
1018                         break;
1019                 }
1020                 if (connector->status != connector_status_connected) {
1021                         ret = -ENODEV;
1022                         break;
1023                 }
1024                 dpcd_caps = aconnector->dc_link->dpcd_caps;
1025                 if (aconnector->port) {
1026                         /* aconnector sets dsc_aux during get_modes call
1027                          * if MST connector has it means it can either
1028                          * enable DSC on the sink device or on MST branch
1029                          * its connected to.
1030                          */
1031                         if (aconnector->dsc_aux) {
1032                                 is_fec_supported = true;
1033                                 is_dsc_supported = true;
1034                         }
1035                 } else {
1036                         is_fec_supported = dpcd_caps.fec_cap.raw & 0x1;
1037                         is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1;
1038                 }
1039         } while (try_again);
1040
1041         drm_modeset_drop_locks(&ctx);
1042         drm_modeset_acquire_fini(&ctx);
1043
1044         seq_printf(m, "FEC_Sink_Support: %s\n", yesno(is_fec_supported));
1045         seq_printf(m, "DSC_Sink_Support: %s\n", yesno(is_dsc_supported));
1046
1047         return ret;
1048 }
1049
1050 /* function: Trigger virtual HPD redetection on connector
1051  *
1052  * This function will perform link rediscovery, link disable
1053  * and enable, and dm connector state update.
1054  *
1055  * Retrigger HPD on an existing connector by echoing 1 into
1056  * its respectful "trigger_hotplug" debugfs entry:
1057  *
1058  *      echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1059  *
1060  * This function can perform HPD unplug:
1061  *
1062  *      echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1063  *
1064  */
1065 static ssize_t trigger_hotplug(struct file *f, const char __user *buf,
1066                                                         size_t size, loff_t *pos)
1067 {
1068         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1069         struct drm_connector *connector = &aconnector->base;
1070         struct dc_link *link = NULL;
1071         struct drm_device *dev = connector->dev;
1072         enum dc_connection_type new_connection_type = dc_connection_none;
1073         char *wr_buf = NULL;
1074         uint32_t wr_buf_size = 42;
1075         int max_param_num = 1;
1076         long param[1] = {0};
1077         uint8_t param_nums = 0;
1078
1079         if (!aconnector || !aconnector->dc_link)
1080                 return -EINVAL;
1081
1082         if (size == 0)
1083                 return -EINVAL;
1084
1085         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1086
1087         if (!wr_buf) {
1088                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1089                 return -ENOSPC;
1090         }
1091
1092         if (parse_write_buffer_into_params(wr_buf, size,
1093                                                 (long *)param, buf,
1094                                                 max_param_num,
1095                                                 &param_nums)) {
1096                 kfree(wr_buf);
1097                 return -EINVAL;
1098         }
1099
1100         if (param_nums <= 0) {
1101                 DRM_DEBUG_DRIVER("user data not be read\n");
1102                 kfree(wr_buf);
1103                 return -EINVAL;
1104         }
1105
1106         if (param[0] == 1) {
1107                 mutex_lock(&aconnector->hpd_lock);
1108
1109                 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type) &&
1110                         new_connection_type != dc_connection_none)
1111                         goto unlock;
1112
1113                 if (!dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD))
1114                         goto unlock;
1115
1116                 amdgpu_dm_update_connector_after_detect(aconnector);
1117
1118                 drm_modeset_lock_all(dev);
1119                 dm_restore_drm_connector_state(dev, connector);
1120                 drm_modeset_unlock_all(dev);
1121
1122                 drm_kms_helper_hotplug_event(dev);
1123         } else if (param[0] == 0) {
1124                 if (!aconnector->dc_link)
1125                         goto unlock;
1126
1127                 link = aconnector->dc_link;
1128
1129                 if (link->local_sink) {
1130                         dc_sink_release(link->local_sink);
1131                         link->local_sink = NULL;
1132                 }
1133
1134                 link->dpcd_sink_count = 0;
1135                 link->type = dc_connection_none;
1136                 link->dongle_max_pix_clk = 0;
1137
1138                 amdgpu_dm_update_connector_after_detect(aconnector);
1139
1140                 drm_modeset_lock_all(dev);
1141                 dm_restore_drm_connector_state(dev, connector);
1142                 drm_modeset_unlock_all(dev);
1143
1144                 drm_kms_helper_hotplug_event(dev);
1145         }
1146
1147 unlock:
1148         mutex_unlock(&aconnector->hpd_lock);
1149
1150         kfree(wr_buf);
1151         return size;
1152 }
1153
1154 /* function: read DSC status on the connector
1155  *
1156  * The read function: dp_dsc_clock_en_read
1157  * returns current status of DSC clock on the connector.
1158  * The return is a boolean flag: 1 or 0.
1159  *
1160  * Access it with the following command (you need to specify
1161  * connector like DP-1):
1162  *
1163  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1164  *
1165  * Expected output:
1166  * 1 - means that DSC is currently enabled
1167  * 0 - means that DSC is disabled
1168  */
1169 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
1170                                     size_t size, loff_t *pos)
1171 {
1172         char *rd_buf = NULL;
1173         char *rd_buf_ptr = NULL;
1174         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1175         struct display_stream_compressor *dsc;
1176         struct dcn_dsc_state dsc_state = {0};
1177         const uint32_t rd_buf_size = 10;
1178         struct pipe_ctx *pipe_ctx;
1179         ssize_t result = 0;
1180         int i, r, str_len = 30;
1181
1182         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1183
1184         if (!rd_buf)
1185                 return -ENOMEM;
1186
1187         rd_buf_ptr = rd_buf;
1188
1189         for (i = 0; i < MAX_PIPES; i++) {
1190                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1191                         if (pipe_ctx && pipe_ctx->stream &&
1192                             pipe_ctx->stream->link == aconnector->dc_link)
1193                                 break;
1194         }
1195
1196         if (!pipe_ctx)
1197                 return -ENXIO;
1198
1199         dsc = pipe_ctx->stream_res.dsc;
1200         if (dsc)
1201                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1202
1203         snprintf(rd_buf_ptr, str_len,
1204                 "%d\n",
1205                 dsc_state.dsc_clock_en);
1206         rd_buf_ptr += str_len;
1207
1208         while (size) {
1209                 if (*pos >= rd_buf_size)
1210                         break;
1211
1212                 r = put_user(*(rd_buf + result), buf);
1213                 if (r)
1214                         return r; /* r = -EFAULT */
1215
1216                 buf += 1;
1217                 size -= 1;
1218                 *pos += 1;
1219                 result += 1;
1220         }
1221
1222         kfree(rd_buf);
1223         return result;
1224 }
1225
1226 /* function: write force DSC on the connector
1227  *
1228  * The write function: dp_dsc_clock_en_write
1229  * enables to force DSC on the connector.
1230  * User can write to either force enable or force disable DSC
1231  * on the next modeset or set it to driver default
1232  *
1233  * Accepted inputs:
1234  * 0 - default DSC enablement policy
1235  * 1 - force enable DSC on the connector
1236  * 2 - force disable DSC on the connector (might cause fail in atomic_check)
1237  *
1238  * Writing DSC settings is done with the following command:
1239  * - To force enable DSC (you need to specify
1240  * connector like DP-1):
1241  *
1242  *      echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1243  *
1244  * - To return to default state set the flag to zero and
1245  * let driver deal with DSC automatically
1246  * (you need to specify connector like DP-1):
1247  *
1248  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1249  *
1250  */
1251 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
1252                                      size_t size, loff_t *pos)
1253 {
1254         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1255         struct drm_connector *connector = &aconnector->base;
1256         struct drm_device *dev = connector->dev;
1257         struct drm_crtc *crtc = NULL;
1258         struct dm_crtc_state *dm_crtc_state = NULL;
1259         struct pipe_ctx *pipe_ctx;
1260         int i;
1261         char *wr_buf = NULL;
1262         uint32_t wr_buf_size = 42;
1263         int max_param_num = 1;
1264         long param[1] = {0};
1265         uint8_t param_nums = 0;
1266
1267         if (size == 0)
1268                 return -EINVAL;
1269
1270         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1271
1272         if (!wr_buf) {
1273                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1274                 return -ENOSPC;
1275         }
1276
1277         if (parse_write_buffer_into_params(wr_buf, size,
1278                                             (long *)param, buf,
1279                                             max_param_num,
1280                                             &param_nums)) {
1281                 kfree(wr_buf);
1282                 return -EINVAL;
1283         }
1284
1285         if (param_nums <= 0) {
1286                 DRM_DEBUG_DRIVER("user data not be read\n");
1287                 kfree(wr_buf);
1288                 return -EINVAL;
1289         }
1290
1291         for (i = 0; i < MAX_PIPES; i++) {
1292                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1293                         if (pipe_ctx && pipe_ctx->stream &&
1294                             pipe_ctx->stream->link == aconnector->dc_link)
1295                                 break;
1296         }
1297
1298         if (!pipe_ctx || !pipe_ctx->stream)
1299                 goto done;
1300
1301         // Get CRTC state
1302         mutex_lock(&dev->mode_config.mutex);
1303         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1304
1305         if (connector->state == NULL)
1306                 goto unlock;
1307
1308         crtc = connector->state->crtc;
1309         if (crtc == NULL)
1310                 goto unlock;
1311
1312         drm_modeset_lock(&crtc->mutex, NULL);
1313         if (crtc->state == NULL)
1314                 goto unlock;
1315
1316         dm_crtc_state = to_dm_crtc_state(crtc->state);
1317         if (dm_crtc_state->stream == NULL)
1318                 goto unlock;
1319
1320         if (param[0] == 1)
1321                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE;
1322         else if (param[0] == 2)
1323                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE;
1324         else
1325                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT;
1326
1327         dm_crtc_state->dsc_force_changed = true;
1328
1329 unlock:
1330         if (crtc)
1331                 drm_modeset_unlock(&crtc->mutex);
1332         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1333         mutex_unlock(&dev->mode_config.mutex);
1334
1335 done:
1336         kfree(wr_buf);
1337         return size;
1338 }
1339
1340 /* function: read DSC slice width parameter on the connector
1341  *
1342  * The read function: dp_dsc_slice_width_read
1343  * returns dsc slice width used in the current configuration
1344  * The return is an integer: 0 or other positive number
1345  *
1346  * Access the status with the following command:
1347  *
1348  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1349  *
1350  * 0 - means that DSC is disabled
1351  *
1352  * Any other number more than zero represents the
1353  * slice width currently used by DSC in pixels
1354  *
1355  */
1356 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
1357                                     size_t size, loff_t *pos)
1358 {
1359         char *rd_buf = NULL;
1360         char *rd_buf_ptr = NULL;
1361         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1362         struct display_stream_compressor *dsc;
1363         struct dcn_dsc_state dsc_state = {0};
1364         const uint32_t rd_buf_size = 100;
1365         struct pipe_ctx *pipe_ctx;
1366         ssize_t result = 0;
1367         int i, r, str_len = 30;
1368
1369         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1370
1371         if (!rd_buf)
1372                 return -ENOMEM;
1373
1374         rd_buf_ptr = rd_buf;
1375
1376         for (i = 0; i < MAX_PIPES; i++) {
1377                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1378                         if (pipe_ctx && pipe_ctx->stream &&
1379                             pipe_ctx->stream->link == aconnector->dc_link)
1380                                 break;
1381         }
1382
1383         if (!pipe_ctx)
1384                 return -ENXIO;
1385
1386         dsc = pipe_ctx->stream_res.dsc;
1387         if (dsc)
1388                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1389
1390         snprintf(rd_buf_ptr, str_len,
1391                 "%d\n",
1392                 dsc_state.dsc_slice_width);
1393         rd_buf_ptr += str_len;
1394
1395         while (size) {
1396                 if (*pos >= rd_buf_size)
1397                         break;
1398
1399                 r = put_user(*(rd_buf + result), buf);
1400                 if (r)
1401                         return r; /* r = -EFAULT */
1402
1403                 buf += 1;
1404                 size -= 1;
1405                 *pos += 1;
1406                 result += 1;
1407         }
1408
1409         kfree(rd_buf);
1410         return result;
1411 }
1412
1413 /* function: write DSC slice width parameter
1414  *
1415  * The write function: dp_dsc_slice_width_write
1416  * overwrites automatically generated DSC configuration
1417  * of slice width.
1418  *
1419  * The user has to write the slice width divisible by the
1420  * picture width.
1421  *
1422  * Also the user has to write width in hexidecimal
1423  * rather than in decimal.
1424  *
1425  * Writing DSC settings is done with the following command:
1426  * - To force overwrite slice width: (example sets to 1920 pixels)
1427  *
1428  *      echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1429  *
1430  *  - To stop overwriting and let driver find the optimal size,
1431  * set the width to zero:
1432  *
1433  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1434  *
1435  */
1436 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
1437                                      size_t size, loff_t *pos)
1438 {
1439         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1440         struct pipe_ctx *pipe_ctx;
1441         struct drm_connector *connector = &aconnector->base;
1442         struct drm_device *dev = connector->dev;
1443         struct drm_crtc *crtc = NULL;
1444         struct dm_crtc_state *dm_crtc_state = NULL;
1445         int i;
1446         char *wr_buf = NULL;
1447         uint32_t wr_buf_size = 42;
1448         int max_param_num = 1;
1449         long param[1] = {0};
1450         uint8_t param_nums = 0;
1451
1452         if (size == 0)
1453                 return -EINVAL;
1454
1455         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1456
1457         if (!wr_buf) {
1458                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1459                 return -ENOSPC;
1460         }
1461
1462         if (parse_write_buffer_into_params(wr_buf, size,
1463                                             (long *)param, buf,
1464                                             max_param_num,
1465                                             &param_nums)) {
1466                 kfree(wr_buf);
1467                 return -EINVAL;
1468         }
1469
1470         if (param_nums <= 0) {
1471                 DRM_DEBUG_DRIVER("user data not be read\n");
1472                 kfree(wr_buf);
1473                 return -EINVAL;
1474         }
1475
1476         for (i = 0; i < MAX_PIPES; i++) {
1477                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1478                         if (pipe_ctx && pipe_ctx->stream &&
1479                             pipe_ctx->stream->link == aconnector->dc_link)
1480                                 break;
1481         }
1482
1483         if (!pipe_ctx || !pipe_ctx->stream)
1484                 goto done;
1485
1486         // Safely get CRTC state
1487         mutex_lock(&dev->mode_config.mutex);
1488         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1489
1490         if (connector->state == NULL)
1491                 goto unlock;
1492
1493         crtc = connector->state->crtc;
1494         if (crtc == NULL)
1495                 goto unlock;
1496
1497         drm_modeset_lock(&crtc->mutex, NULL);
1498         if (crtc->state == NULL)
1499                 goto unlock;
1500
1501         dm_crtc_state = to_dm_crtc_state(crtc->state);
1502         if (dm_crtc_state->stream == NULL)
1503                 goto unlock;
1504
1505         if (param[0] > 0)
1506                 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(
1507                                         pipe_ctx->stream->timing.h_addressable,
1508                                         param[0]);
1509         else
1510                 aconnector->dsc_settings.dsc_num_slices_h = 0;
1511
1512         dm_crtc_state->dsc_force_changed = true;
1513
1514 unlock:
1515         if (crtc)
1516                 drm_modeset_unlock(&crtc->mutex);
1517         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1518         mutex_unlock(&dev->mode_config.mutex);
1519
1520 done:
1521         kfree(wr_buf);
1522         return size;
1523 }
1524
1525 /* function: read DSC slice height parameter on the connector
1526  *
1527  * The read function: dp_dsc_slice_height_read
1528  * returns dsc slice height used in the current configuration
1529  * The return is an integer: 0 or other positive number
1530  *
1531  * Access the status with the following command:
1532  *
1533  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1534  *
1535  * 0 - means that DSC is disabled
1536  *
1537  * Any other number more than zero represents the
1538  * slice height currently used by DSC in pixels
1539  *
1540  */
1541 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
1542                                     size_t size, loff_t *pos)
1543 {
1544         char *rd_buf = NULL;
1545         char *rd_buf_ptr = NULL;
1546         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1547         struct display_stream_compressor *dsc;
1548         struct dcn_dsc_state dsc_state = {0};
1549         const uint32_t rd_buf_size = 100;
1550         struct pipe_ctx *pipe_ctx;
1551         ssize_t result = 0;
1552         int i, r, str_len = 30;
1553
1554         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1555
1556         if (!rd_buf)
1557                 return -ENOMEM;
1558
1559         rd_buf_ptr = rd_buf;
1560
1561         for (i = 0; i < MAX_PIPES; i++) {
1562                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1563                         if (pipe_ctx && pipe_ctx->stream &&
1564                             pipe_ctx->stream->link == aconnector->dc_link)
1565                                 break;
1566         }
1567
1568         if (!pipe_ctx)
1569                 return -ENXIO;
1570
1571         dsc = pipe_ctx->stream_res.dsc;
1572         if (dsc)
1573                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1574
1575         snprintf(rd_buf_ptr, str_len,
1576                 "%d\n",
1577                 dsc_state.dsc_slice_height);
1578         rd_buf_ptr += str_len;
1579
1580         while (size) {
1581                 if (*pos >= rd_buf_size)
1582                         break;
1583
1584                 r = put_user(*(rd_buf + result), buf);
1585                 if (r)
1586                         return r; /* r = -EFAULT */
1587
1588                 buf += 1;
1589                 size -= 1;
1590                 *pos += 1;
1591                 result += 1;
1592         }
1593
1594         kfree(rd_buf);
1595         return result;
1596 }
1597
1598 /* function: write DSC slice height parameter
1599  *
1600  * The write function: dp_dsc_slice_height_write
1601  * overwrites automatically generated DSC configuration
1602  * of slice height.
1603  *
1604  * The user has to write the slice height divisible by the
1605  * picture height.
1606  *
1607  * Also the user has to write height in hexidecimal
1608  * rather than in decimal.
1609  *
1610  * Writing DSC settings is done with the following command:
1611  * - To force overwrite slice height (example sets to 128 pixels):
1612  *
1613  *      echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1614  *
1615  *  - To stop overwriting and let driver find the optimal size,
1616  * set the height to zero:
1617  *
1618  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1619  *
1620  */
1621 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
1622                                      size_t size, loff_t *pos)
1623 {
1624         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1625         struct drm_connector *connector = &aconnector->base;
1626         struct drm_device *dev = connector->dev;
1627         struct drm_crtc *crtc = NULL;
1628         struct dm_crtc_state *dm_crtc_state = NULL;
1629         struct pipe_ctx *pipe_ctx;
1630         int i;
1631         char *wr_buf = NULL;
1632         uint32_t wr_buf_size = 42;
1633         int max_param_num = 1;
1634         uint8_t param_nums = 0;
1635         long param[1] = {0};
1636
1637         if (size == 0)
1638                 return -EINVAL;
1639
1640         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1641
1642         if (!wr_buf) {
1643                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1644                 return -ENOSPC;
1645         }
1646
1647         if (parse_write_buffer_into_params(wr_buf, size,
1648                                             (long *)param, buf,
1649                                             max_param_num,
1650                                             &param_nums)) {
1651                 kfree(wr_buf);
1652                 return -EINVAL;
1653         }
1654
1655         if (param_nums <= 0) {
1656                 DRM_DEBUG_DRIVER("user data not be read\n");
1657                 kfree(wr_buf);
1658                 return -EINVAL;
1659         }
1660
1661         for (i = 0; i < MAX_PIPES; i++) {
1662                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1663                         if (pipe_ctx && pipe_ctx->stream &&
1664                             pipe_ctx->stream->link == aconnector->dc_link)
1665                                 break;
1666         }
1667
1668         if (!pipe_ctx || !pipe_ctx->stream)
1669                 goto done;
1670
1671         // Get CRTC state
1672         mutex_lock(&dev->mode_config.mutex);
1673         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1674
1675         if (connector->state == NULL)
1676                 goto unlock;
1677
1678         crtc = connector->state->crtc;
1679         if (crtc == NULL)
1680                 goto unlock;
1681
1682         drm_modeset_lock(&crtc->mutex, NULL);
1683         if (crtc->state == NULL)
1684                 goto unlock;
1685
1686         dm_crtc_state = to_dm_crtc_state(crtc->state);
1687         if (dm_crtc_state->stream == NULL)
1688                 goto unlock;
1689
1690         if (param[0] > 0)
1691                 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(
1692                                         pipe_ctx->stream->timing.v_addressable,
1693                                         param[0]);
1694         else
1695                 aconnector->dsc_settings.dsc_num_slices_v = 0;
1696
1697         dm_crtc_state->dsc_force_changed = true;
1698
1699 unlock:
1700         if (crtc)
1701                 drm_modeset_unlock(&crtc->mutex);
1702         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1703         mutex_unlock(&dev->mode_config.mutex);
1704
1705 done:
1706         kfree(wr_buf);
1707         return size;
1708 }
1709
1710 /* function: read DSC target rate on the connector in bits per pixel
1711  *
1712  * The read function: dp_dsc_bits_per_pixel_read
1713  * returns target rate of compression in bits per pixel
1714  * The return is an integer: 0 or other positive integer
1715  *
1716  * Access it with the following command:
1717  *
1718  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1719  *
1720  *  0 - means that DSC is disabled
1721  */
1722 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
1723                                     size_t size, loff_t *pos)
1724 {
1725         char *rd_buf = NULL;
1726         char *rd_buf_ptr = NULL;
1727         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1728         struct display_stream_compressor *dsc;
1729         struct dcn_dsc_state dsc_state = {0};
1730         const uint32_t rd_buf_size = 100;
1731         struct pipe_ctx *pipe_ctx;
1732         ssize_t result = 0;
1733         int i, r, str_len = 30;
1734
1735         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1736
1737         if (!rd_buf)
1738                 return -ENOMEM;
1739
1740         rd_buf_ptr = rd_buf;
1741
1742         for (i = 0; i < MAX_PIPES; i++) {
1743                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1744                         if (pipe_ctx && pipe_ctx->stream &&
1745                             pipe_ctx->stream->link == aconnector->dc_link)
1746                                 break;
1747         }
1748
1749         if (!pipe_ctx)
1750                 return -ENXIO;
1751
1752         dsc = pipe_ctx->stream_res.dsc;
1753         if (dsc)
1754                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1755
1756         snprintf(rd_buf_ptr, str_len,
1757                 "%d\n",
1758                 dsc_state.dsc_bits_per_pixel);
1759         rd_buf_ptr += str_len;
1760
1761         while (size) {
1762                 if (*pos >= rd_buf_size)
1763                         break;
1764
1765                 r = put_user(*(rd_buf + result), buf);
1766                 if (r)
1767                         return r; /* r = -EFAULT */
1768
1769                 buf += 1;
1770                 size -= 1;
1771                 *pos += 1;
1772                 result += 1;
1773         }
1774
1775         kfree(rd_buf);
1776         return result;
1777 }
1778
1779 /* function: write DSC target rate in bits per pixel
1780  *
1781  * The write function: dp_dsc_bits_per_pixel_write
1782  * overwrites automatically generated DSC configuration
1783  * of DSC target bit rate.
1784  *
1785  * Also the user has to write bpp in hexidecimal
1786  * rather than in decimal.
1787  *
1788  * Writing DSC settings is done with the following command:
1789  * - To force overwrite rate (example sets to 256 bpp x 1/16):
1790  *
1791  *      echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1792  *
1793  *  - To stop overwriting and let driver find the optimal rate,
1794  * set the rate to zero:
1795  *
1796  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1797  *
1798  */
1799 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf,
1800                                      size_t size, loff_t *pos)
1801 {
1802         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1803         struct drm_connector *connector = &aconnector->base;
1804         struct drm_device *dev = connector->dev;
1805         struct drm_crtc *crtc = NULL;
1806         struct dm_crtc_state *dm_crtc_state = NULL;
1807         struct pipe_ctx *pipe_ctx;
1808         int i;
1809         char *wr_buf = NULL;
1810         uint32_t wr_buf_size = 42;
1811         int max_param_num = 1;
1812         uint8_t param_nums = 0;
1813         long param[1] = {0};
1814
1815         if (size == 0)
1816                 return -EINVAL;
1817
1818         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1819
1820         if (!wr_buf) {
1821                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1822                 return -ENOSPC;
1823         }
1824
1825         if (parse_write_buffer_into_params(wr_buf, size,
1826                                             (long *)param, buf,
1827                                             max_param_num,
1828                                             &param_nums)) {
1829                 kfree(wr_buf);
1830                 return -EINVAL;
1831         }
1832
1833         if (param_nums <= 0) {
1834                 DRM_DEBUG_DRIVER("user data not be read\n");
1835                 kfree(wr_buf);
1836                 return -EINVAL;
1837         }
1838
1839         for (i = 0; i < MAX_PIPES; i++) {
1840                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1841                         if (pipe_ctx && pipe_ctx->stream &&
1842                             pipe_ctx->stream->link == aconnector->dc_link)
1843                                 break;
1844         }
1845
1846         if (!pipe_ctx || !pipe_ctx->stream)
1847                 goto done;
1848
1849         // Get CRTC state
1850         mutex_lock(&dev->mode_config.mutex);
1851         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1852
1853         if (connector->state == NULL)
1854                 goto unlock;
1855
1856         crtc = connector->state->crtc;
1857         if (crtc == NULL)
1858                 goto unlock;
1859
1860         drm_modeset_lock(&crtc->mutex, NULL);
1861         if (crtc->state == NULL)
1862                 goto unlock;
1863
1864         dm_crtc_state = to_dm_crtc_state(crtc->state);
1865         if (dm_crtc_state->stream == NULL)
1866                 goto unlock;
1867
1868         aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
1869
1870         dm_crtc_state->dsc_force_changed = true;
1871
1872 unlock:
1873         if (crtc)
1874                 drm_modeset_unlock(&crtc->mutex);
1875         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1876         mutex_unlock(&dev->mode_config.mutex);
1877
1878 done:
1879         kfree(wr_buf);
1880         return size;
1881 }
1882
1883 /* function: read DSC picture width parameter on the connector
1884  *
1885  * The read function: dp_dsc_pic_width_read
1886  * returns dsc picture width used in the current configuration
1887  * It is the same as h_addressable of the current
1888  * display's timing
1889  * The return is an integer: 0 or other positive integer
1890  * If 0 then DSC is disabled.
1891  *
1892  * Access it with the following command:
1893  *
1894  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width
1895  *
1896  * 0 - means that DSC is disabled
1897  */
1898 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
1899                                     size_t size, loff_t *pos)
1900 {
1901         char *rd_buf = NULL;
1902         char *rd_buf_ptr = NULL;
1903         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1904         struct display_stream_compressor *dsc;
1905         struct dcn_dsc_state dsc_state = {0};
1906         const uint32_t rd_buf_size = 100;
1907         struct pipe_ctx *pipe_ctx;
1908         ssize_t result = 0;
1909         int i, r, str_len = 30;
1910
1911         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1912
1913         if (!rd_buf)
1914                 return -ENOMEM;
1915
1916         rd_buf_ptr = rd_buf;
1917
1918         for (i = 0; i < MAX_PIPES; i++) {
1919                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1920                         if (pipe_ctx && pipe_ctx->stream &&
1921                             pipe_ctx->stream->link == aconnector->dc_link)
1922                                 break;
1923         }
1924
1925         if (!pipe_ctx)
1926                 return -ENXIO;
1927
1928         dsc = pipe_ctx->stream_res.dsc;
1929         if (dsc)
1930                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1931
1932         snprintf(rd_buf_ptr, str_len,
1933                 "%d\n",
1934                 dsc_state.dsc_pic_width);
1935         rd_buf_ptr += str_len;
1936
1937         while (size) {
1938                 if (*pos >= rd_buf_size)
1939                         break;
1940
1941                 r = put_user(*(rd_buf + result), buf);
1942                 if (r)
1943                         return r; /* r = -EFAULT */
1944
1945                 buf += 1;
1946                 size -= 1;
1947                 *pos += 1;
1948                 result += 1;
1949         }
1950
1951         kfree(rd_buf);
1952         return result;
1953 }
1954
1955 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
1956                                     size_t size, loff_t *pos)
1957 {
1958         char *rd_buf = NULL;
1959         char *rd_buf_ptr = NULL;
1960         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1961         struct display_stream_compressor *dsc;
1962         struct dcn_dsc_state dsc_state = {0};
1963         const uint32_t rd_buf_size = 100;
1964         struct pipe_ctx *pipe_ctx;
1965         ssize_t result = 0;
1966         int i, r, str_len = 30;
1967
1968         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1969
1970         if (!rd_buf)
1971                 return -ENOMEM;
1972
1973         rd_buf_ptr = rd_buf;
1974
1975         for (i = 0; i < MAX_PIPES; i++) {
1976                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1977                         if (pipe_ctx && pipe_ctx->stream &&
1978                             pipe_ctx->stream->link == aconnector->dc_link)
1979                                 break;
1980         }
1981
1982         if (!pipe_ctx)
1983                 return -ENXIO;
1984
1985         dsc = pipe_ctx->stream_res.dsc;
1986         if (dsc)
1987                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1988
1989         snprintf(rd_buf_ptr, str_len,
1990                 "%d\n",
1991                 dsc_state.dsc_pic_height);
1992         rd_buf_ptr += str_len;
1993
1994         while (size) {
1995                 if (*pos >= rd_buf_size)
1996                         break;
1997
1998                 r = put_user(*(rd_buf + result), buf);
1999                 if (r)
2000                         return r; /* r = -EFAULT */
2001
2002                 buf += 1;
2003                 size -= 1;
2004                 *pos += 1;
2005                 result += 1;
2006         }
2007
2008         kfree(rd_buf);
2009         return result;
2010 }
2011
2012 /* function: read DSC chunk size parameter on the connector
2013  *
2014  * The read function: dp_dsc_chunk_size_read
2015  * returns dsc chunk size set in the current configuration
2016  * The value is calculated automatically by DSC code
2017  * and depends on slice parameters and bpp target rate
2018  * The return is an integer: 0 or other positive integer
2019  * If 0 then DSC is disabled.
2020  *
2021  * Access it with the following command:
2022  *
2023  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size
2024  *
2025  * 0 - means that DSC is disabled
2026  */
2027 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
2028                                     size_t size, loff_t *pos)
2029 {
2030         char *rd_buf = NULL;
2031         char *rd_buf_ptr = NULL;
2032         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2033         struct display_stream_compressor *dsc;
2034         struct dcn_dsc_state dsc_state = {0};
2035         const uint32_t rd_buf_size = 100;
2036         struct pipe_ctx *pipe_ctx;
2037         ssize_t result = 0;
2038         int i, r, str_len = 30;
2039
2040         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2041
2042         if (!rd_buf)
2043                 return -ENOMEM;
2044
2045         rd_buf_ptr = rd_buf;
2046
2047         for (i = 0; i < MAX_PIPES; i++) {
2048                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2049                         if (pipe_ctx && pipe_ctx->stream &&
2050                             pipe_ctx->stream->link == aconnector->dc_link)
2051                                 break;
2052         }
2053
2054         if (!pipe_ctx)
2055                 return -ENXIO;
2056
2057         dsc = pipe_ctx->stream_res.dsc;
2058         if (dsc)
2059                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2060
2061         snprintf(rd_buf_ptr, str_len,
2062                 "%d\n",
2063                 dsc_state.dsc_chunk_size);
2064         rd_buf_ptr += str_len;
2065
2066         while (size) {
2067                 if (*pos >= rd_buf_size)
2068                         break;
2069
2070                 r = put_user(*(rd_buf + result), buf);
2071                 if (r)
2072                         return r; /* r = -EFAULT */
2073
2074                 buf += 1;
2075                 size -= 1;
2076                 *pos += 1;
2077                 result += 1;
2078         }
2079
2080         kfree(rd_buf);
2081         return result;
2082 }
2083
2084 /* function: read DSC slice bpg offset on the connector
2085  *
2086  * The read function: dp_dsc_slice_bpg_offset_read
2087  * returns dsc bpg slice offset set in the current configuration
2088  * The value is calculated automatically by DSC code
2089  * and depends on slice parameters and bpp target rate
2090  * The return is an integer: 0 or other positive integer
2091  * If 0 then DSC is disabled.
2092  *
2093  * Access it with the following command:
2094  *
2095  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset
2096  *
2097  * 0 - means that DSC is disabled
2098  */
2099 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
2100                                     size_t size, loff_t *pos)
2101 {
2102         char *rd_buf = NULL;
2103         char *rd_buf_ptr = NULL;
2104         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2105         struct display_stream_compressor *dsc;
2106         struct dcn_dsc_state dsc_state = {0};
2107         const uint32_t rd_buf_size = 100;
2108         struct pipe_ctx *pipe_ctx;
2109         ssize_t result = 0;
2110         int i, r, str_len = 30;
2111
2112         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2113
2114         if (!rd_buf)
2115                 return -ENOMEM;
2116
2117         rd_buf_ptr = rd_buf;
2118
2119         for (i = 0; i < MAX_PIPES; i++) {
2120                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2121                         if (pipe_ctx && pipe_ctx->stream &&
2122                             pipe_ctx->stream->link == aconnector->dc_link)
2123                                 break;
2124         }
2125
2126         if (!pipe_ctx)
2127                 return -ENXIO;
2128
2129         dsc = pipe_ctx->stream_res.dsc;
2130         if (dsc)
2131                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2132
2133         snprintf(rd_buf_ptr, str_len,
2134                 "%d\n",
2135                 dsc_state.dsc_slice_bpg_offset);
2136         rd_buf_ptr += str_len;
2137
2138         while (size) {
2139                 if (*pos >= rd_buf_size)
2140                         break;
2141
2142                 r = put_user(*(rd_buf + result), buf);
2143                 if (r)
2144                         return r; /* r = -EFAULT */
2145
2146                 buf += 1;
2147                 size -= 1;
2148                 *pos += 1;
2149                 result += 1;
2150         }
2151
2152         kfree(rd_buf);
2153         return result;
2154 }
2155
2156
2157 /*
2158  * function description: Read max_requested_bpc property from the connector
2159  *
2160  * Access it with the following command:
2161  *
2162  *      cat /sys/kernel/debug/dri/0/DP-X/max_bpc
2163  *
2164  */
2165 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf,
2166                 size_t size, loff_t *pos)
2167 {
2168         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2169         struct drm_connector *connector = &aconnector->base;
2170         struct drm_device *dev = connector->dev;
2171         struct dm_connector_state *state;
2172         ssize_t result = 0;
2173         char *rd_buf = NULL;
2174         char *rd_buf_ptr = NULL;
2175         const uint32_t rd_buf_size = 10;
2176         int r;
2177
2178         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2179
2180         if (!rd_buf)
2181                 return -ENOMEM;
2182
2183         mutex_lock(&dev->mode_config.mutex);
2184         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2185
2186         if (connector->state == NULL)
2187                 goto unlock;
2188
2189         state = to_dm_connector_state(connector->state);
2190
2191         rd_buf_ptr = rd_buf;
2192         snprintf(rd_buf_ptr, rd_buf_size,
2193                 "%u\n",
2194                 state->base.max_requested_bpc);
2195
2196         while (size) {
2197                 if (*pos >= rd_buf_size)
2198                         break;
2199
2200                 r = put_user(*(rd_buf + result), buf);
2201                 if (r) {
2202                         result = r; /* r = -EFAULT */
2203                         goto unlock;
2204                 }
2205                 buf += 1;
2206                 size -= 1;
2207                 *pos += 1;
2208                 result += 1;
2209         }
2210 unlock:
2211         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2212         mutex_unlock(&dev->mode_config.mutex);
2213         kfree(rd_buf);
2214         return result;
2215 }
2216
2217
2218 /*
2219  * function description: Set max_requested_bpc property on the connector
2220  *
2221  * This function will not force the input BPC on connector, it will only
2222  * change the max value. This is equivalent to setting max_bpc through
2223  * xrandr.
2224  *
2225  * The BPC value written must be >= 6 and <= 16. Values outside of this
2226  * range will result in errors.
2227  *
2228  * BPC values:
2229  *      0x6 - 6 BPC
2230  *      0x8 - 8 BPC
2231  *      0xa - 10 BPC
2232  *      0xc - 12 BPC
2233  *      0x10 - 16 BPC
2234  *
2235  * Write the max_bpc in the following way:
2236  *
2237  * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc
2238  *
2239  */
2240 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf,
2241                                      size_t size, loff_t *pos)
2242 {
2243         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2244         struct drm_connector *connector = &aconnector->base;
2245         struct dm_connector_state *state;
2246         struct drm_device *dev = connector->dev;
2247         char *wr_buf = NULL;
2248         uint32_t wr_buf_size = 42;
2249         int max_param_num = 1;
2250         long param[1] = {0};
2251         uint8_t param_nums = 0;
2252
2253         if (size == 0)
2254                 return -EINVAL;
2255
2256         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2257
2258         if (!wr_buf) {
2259                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2260                 return -ENOSPC;
2261         }
2262
2263         if (parse_write_buffer_into_params(wr_buf, size,
2264                                            (long *)param, buf,
2265                                            max_param_num,
2266                                            &param_nums)) {
2267                 kfree(wr_buf);
2268                 return -EINVAL;
2269         }
2270
2271         if (param_nums <= 0) {
2272                 DRM_DEBUG_DRIVER("user data not be read\n");
2273                 kfree(wr_buf);
2274                 return -EINVAL;
2275         }
2276
2277         if (param[0] < 6 || param[0] > 16) {
2278                 DRM_DEBUG_DRIVER("bad max_bpc value\n");
2279                 kfree(wr_buf);
2280                 return -EINVAL;
2281         }
2282
2283         mutex_lock(&dev->mode_config.mutex);
2284         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2285
2286         if (connector->state == NULL)
2287                 goto unlock;
2288
2289         state = to_dm_connector_state(connector->state);
2290         state->base.max_requested_bpc = param[0];
2291 unlock:
2292         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2293         mutex_unlock(&dev->mode_config.mutex);
2294
2295         kfree(wr_buf);
2296         return size;
2297 }
2298
2299 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
2300 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
2301 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
2302 DEFINE_SHOW_ATTRIBUTE(output_bpc);
2303 #ifdef CONFIG_DRM_AMD_DC_HDCP
2304 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
2305 #endif
2306
2307 static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
2308         .owner = THIS_MODULE,
2309         .read = dp_dsc_clock_en_read,
2310         .write = dp_dsc_clock_en_write,
2311         .llseek = default_llseek
2312 };
2313
2314 static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
2315         .owner = THIS_MODULE,
2316         .read = dp_dsc_slice_width_read,
2317         .write = dp_dsc_slice_width_write,
2318         .llseek = default_llseek
2319 };
2320
2321 static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
2322         .owner = THIS_MODULE,
2323         .read = dp_dsc_slice_height_read,
2324         .write = dp_dsc_slice_height_write,
2325         .llseek = default_llseek
2326 };
2327
2328 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = {
2329         .owner = THIS_MODULE,
2330         .read = dp_dsc_bits_per_pixel_read,
2331         .write = dp_dsc_bits_per_pixel_write,
2332         .llseek = default_llseek
2333 };
2334
2335 static const struct file_operations dp_dsc_pic_width_debugfs_fops = {
2336         .owner = THIS_MODULE,
2337         .read = dp_dsc_pic_width_read,
2338         .llseek = default_llseek
2339 };
2340
2341 static const struct file_operations dp_dsc_pic_height_debugfs_fops = {
2342         .owner = THIS_MODULE,
2343         .read = dp_dsc_pic_height_read,
2344         .llseek = default_llseek
2345 };
2346
2347 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = {
2348         .owner = THIS_MODULE,
2349         .read = dp_dsc_chunk_size_read,
2350         .llseek = default_llseek
2351 };
2352
2353 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = {
2354         .owner = THIS_MODULE,
2355         .read = dp_dsc_slice_bpg_offset_read,
2356         .llseek = default_llseek
2357 };
2358
2359 static const struct file_operations trigger_hotplug_debugfs_fops = {
2360         .owner = THIS_MODULE,
2361         .write = trigger_hotplug,
2362         .llseek = default_llseek
2363 };
2364
2365 static const struct file_operations dp_link_settings_debugfs_fops = {
2366         .owner = THIS_MODULE,
2367         .read = dp_link_settings_read,
2368         .write = dp_link_settings_write,
2369         .llseek = default_llseek
2370 };
2371
2372 static const struct file_operations dp_phy_settings_debugfs_fop = {
2373         .owner = THIS_MODULE,
2374         .read = dp_phy_settings_read,
2375         .write = dp_phy_settings_write,
2376         .llseek = default_llseek
2377 };
2378
2379 static const struct file_operations dp_phy_test_pattern_fops = {
2380         .owner = THIS_MODULE,
2381         .write = dp_phy_test_pattern_debugfs_write,
2382         .llseek = default_llseek
2383 };
2384
2385 static const struct file_operations sdp_message_fops = {
2386         .owner = THIS_MODULE,
2387         .write = dp_sdp_message_debugfs_write,
2388         .llseek = default_llseek
2389 };
2390
2391 static const struct file_operations dp_dpcd_address_debugfs_fops = {
2392         .owner = THIS_MODULE,
2393         .write = dp_dpcd_address_write,
2394         .llseek = default_llseek
2395 };
2396
2397 static const struct file_operations dp_dpcd_size_debugfs_fops = {
2398         .owner = THIS_MODULE,
2399         .write = dp_dpcd_size_write,
2400         .llseek = default_llseek
2401 };
2402
2403 static const struct file_operations dp_dpcd_data_debugfs_fops = {
2404         .owner = THIS_MODULE,
2405         .read = dp_dpcd_data_read,
2406         .write = dp_dpcd_data_write,
2407         .llseek = default_llseek
2408 };
2409
2410 static const struct file_operations dp_max_bpc_debugfs_fops = {
2411         .owner = THIS_MODULE,
2412         .read = dp_max_bpc_read,
2413         .write = dp_max_bpc_write,
2414         .llseek = default_llseek
2415 };
2416
2417 static const struct {
2418         char *name;
2419         const struct file_operations *fops;
2420 } dp_debugfs_entries[] = {
2421                 {"link_settings", &dp_link_settings_debugfs_fops},
2422                 {"phy_settings", &dp_phy_settings_debugfs_fop},
2423                 {"test_pattern", &dp_phy_test_pattern_fops},
2424 #ifdef CONFIG_DRM_AMD_DC_HDCP
2425                 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
2426 #endif
2427                 {"sdp_message", &sdp_message_fops},
2428                 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops},
2429                 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops},
2430                 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops},
2431                 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops},
2432                 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops},
2433                 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops},
2434                 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops},
2435                 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops},
2436                 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops},
2437                 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
2438                 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
2439                 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
2440                 {"max_bpc", &dp_max_bpc_debugfs_fops}
2441 };
2442
2443 #ifdef CONFIG_DRM_AMD_DC_HDCP
2444 static const struct {
2445         char *name;
2446         const struct file_operations *fops;
2447 } hdmi_debugfs_entries[] = {
2448                 {"hdcp_sink_capability", &hdcp_sink_capability_fops}
2449 };
2450 #endif
2451 /*
2452  * Force YUV420 output if available from the given mode
2453  */
2454 static int force_yuv420_output_set(void *data, u64 val)
2455 {
2456         struct amdgpu_dm_connector *connector = data;
2457
2458         connector->force_yuv420_output = (bool)val;
2459
2460         return 0;
2461 }
2462
2463 /*
2464  * Check if YUV420 is forced when available from the given mode
2465  */
2466 static int force_yuv420_output_get(void *data, u64 *val)
2467 {
2468         struct amdgpu_dm_connector *connector = data;
2469
2470         *val = connector->force_yuv420_output;
2471
2472         return 0;
2473 }
2474
2475 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
2476                          force_yuv420_output_set, "%llu\n");
2477
2478 /*
2479  *  Read PSR state
2480  */
2481 static int psr_get(void *data, u64 *val)
2482 {
2483         struct amdgpu_dm_connector *connector = data;
2484         struct dc_link *link = connector->dc_link;
2485         enum dc_psr_state state = PSR_STATE0;
2486
2487         dc_link_get_psr_state(link, &state);
2488
2489         *val = state;
2490
2491         return 0;
2492 }
2493
2494 /*
2495  * Set dmcub trace event IRQ enable or disable.
2496  * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2497  * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2498  */
2499 static int dmcub_trace_event_state_set(void *data, u64 val)
2500 {
2501         struct amdgpu_device *adev = data;
2502
2503         if (val == 1 || val == 0) {
2504                 dc_dmub_trace_event_control(adev->dm.dc, val);
2505                 adev->dm.dmcub_trace_event_en = (bool)val;
2506         } else
2507                 return 0;
2508
2509         return 0;
2510 }
2511
2512 /*
2513  * The interface doesn't need get function, so it will return the
2514  * value of zero
2515  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2516  */
2517 static int dmcub_trace_event_state_get(void *data, u64 *val)
2518 {
2519         struct amdgpu_device *adev = data;
2520
2521         *val = adev->dm.dmcub_trace_event_en;
2522         return 0;
2523 }
2524
2525 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get,
2526                          dmcub_trace_event_state_set, "%llu\n");
2527
2528 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
2529
2530 static const struct {
2531         char *name;
2532         const struct file_operations *fops;
2533 } connector_debugfs_entries[] = {
2534                 {"force_yuv420_output", &force_yuv420_output_fops},
2535                 {"output_bpc", &output_bpc_fops},
2536                 {"trigger_hotplug", &trigger_hotplug_debugfs_fops}
2537 };
2538
2539 void connector_debugfs_init(struct amdgpu_dm_connector *connector)
2540 {
2541         int i;
2542         struct dentry *dir = connector->base.debugfs_entry;
2543
2544         if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2545             connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
2546                 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
2547                         debugfs_create_file(dp_debugfs_entries[i].name,
2548                                             0644, dir, connector,
2549                                             dp_debugfs_entries[i].fops);
2550                 }
2551         }
2552         if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2553                 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
2554
2555         for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
2556                 debugfs_create_file(connector_debugfs_entries[i].name,
2557                                     0644, dir, connector,
2558                                     connector_debugfs_entries[i].fops);
2559         }
2560
2561         connector->debugfs_dpcd_address = 0;
2562         connector->debugfs_dpcd_size = 0;
2563
2564 #ifdef CONFIG_DRM_AMD_DC_HDCP
2565         if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
2566                 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) {
2567                         debugfs_create_file(hdmi_debugfs_entries[i].name,
2568                                             0644, dir, connector,
2569                                             hdmi_debugfs_entries[i].fops);
2570                 }
2571         }
2572 #endif
2573 }
2574
2575 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
2576 /*
2577  * Set crc window coordinate x start
2578  */
2579 static int crc_win_x_start_set(void *data, u64 val)
2580 {
2581         struct drm_crtc *crtc = data;
2582         struct drm_device *drm_dev = crtc->dev;
2583         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2584
2585         spin_lock_irq(&drm_dev->event_lock);
2586         acrtc->dm_irq_params.crc_window.x_start = (uint16_t) val;
2587         acrtc->dm_irq_params.crc_window.update_win = false;
2588         spin_unlock_irq(&drm_dev->event_lock);
2589
2590         return 0;
2591 }
2592
2593 /*
2594  * Get crc window coordinate x start
2595  */
2596 static int crc_win_x_start_get(void *data, u64 *val)
2597 {
2598         struct drm_crtc *crtc = data;
2599         struct drm_device *drm_dev = crtc->dev;
2600         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2601
2602         spin_lock_irq(&drm_dev->event_lock);
2603         *val = acrtc->dm_irq_params.crc_window.x_start;
2604         spin_unlock_irq(&drm_dev->event_lock);
2605
2606         return 0;
2607 }
2608
2609 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get,
2610                          crc_win_x_start_set, "%llu\n");
2611
2612
2613 /*
2614  * Set crc window coordinate y start
2615  */
2616 static int crc_win_y_start_set(void *data, u64 val)
2617 {
2618         struct drm_crtc *crtc = data;
2619         struct drm_device *drm_dev = crtc->dev;
2620         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2621
2622         spin_lock_irq(&drm_dev->event_lock);
2623         acrtc->dm_irq_params.crc_window.y_start = (uint16_t) val;
2624         acrtc->dm_irq_params.crc_window.update_win = false;
2625         spin_unlock_irq(&drm_dev->event_lock);
2626
2627         return 0;
2628 }
2629
2630 /*
2631  * Get crc window coordinate y start
2632  */
2633 static int crc_win_y_start_get(void *data, u64 *val)
2634 {
2635         struct drm_crtc *crtc = data;
2636         struct drm_device *drm_dev = crtc->dev;
2637         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2638
2639         spin_lock_irq(&drm_dev->event_lock);
2640         *val = acrtc->dm_irq_params.crc_window.y_start;
2641         spin_unlock_irq(&drm_dev->event_lock);
2642
2643         return 0;
2644 }
2645
2646 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get,
2647                          crc_win_y_start_set, "%llu\n");
2648
2649 /*
2650  * Set crc window coordinate x end
2651  */
2652 static int crc_win_x_end_set(void *data, u64 val)
2653 {
2654         struct drm_crtc *crtc = data;
2655         struct drm_device *drm_dev = crtc->dev;
2656         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2657
2658         spin_lock_irq(&drm_dev->event_lock);
2659         acrtc->dm_irq_params.crc_window.x_end = (uint16_t) val;
2660         acrtc->dm_irq_params.crc_window.update_win = false;
2661         spin_unlock_irq(&drm_dev->event_lock);
2662
2663         return 0;
2664 }
2665
2666 /*
2667  * Get crc window coordinate x end
2668  */
2669 static int crc_win_x_end_get(void *data, u64 *val)
2670 {
2671         struct drm_crtc *crtc = data;
2672         struct drm_device *drm_dev = crtc->dev;
2673         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2674
2675         spin_lock_irq(&drm_dev->event_lock);
2676         *val = acrtc->dm_irq_params.crc_window.x_end;
2677         spin_unlock_irq(&drm_dev->event_lock);
2678
2679         return 0;
2680 }
2681
2682 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get,
2683                          crc_win_x_end_set, "%llu\n");
2684
2685 /*
2686  * Set crc window coordinate y end
2687  */
2688 static int crc_win_y_end_set(void *data, u64 val)
2689 {
2690         struct drm_crtc *crtc = data;
2691         struct drm_device *drm_dev = crtc->dev;
2692         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2693
2694         spin_lock_irq(&drm_dev->event_lock);
2695         acrtc->dm_irq_params.crc_window.y_end = (uint16_t) val;
2696         acrtc->dm_irq_params.crc_window.update_win = false;
2697         spin_unlock_irq(&drm_dev->event_lock);
2698
2699         return 0;
2700 }
2701
2702 /*
2703  * Get crc window coordinate y end
2704  */
2705 static int crc_win_y_end_get(void *data, u64 *val)
2706 {
2707         struct drm_crtc *crtc = data;
2708         struct drm_device *drm_dev = crtc->dev;
2709         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2710
2711         spin_lock_irq(&drm_dev->event_lock);
2712         *val = acrtc->dm_irq_params.crc_window.y_end;
2713         spin_unlock_irq(&drm_dev->event_lock);
2714
2715         return 0;
2716 }
2717
2718 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get,
2719                          crc_win_y_end_set, "%llu\n");
2720 /*
2721  * Trigger to commit crc window
2722  */
2723 static int crc_win_update_set(void *data, u64 val)
2724 {
2725         struct drm_crtc *new_crtc = data;
2726         struct drm_crtc *old_crtc = NULL;
2727         struct amdgpu_crtc *new_acrtc, *old_acrtc;
2728         struct amdgpu_device *adev = drm_to_adev(new_crtc->dev);
2729         struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk;
2730
2731         if (val) {
2732                 spin_lock_irq(&adev_to_drm(adev)->event_lock);
2733                 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);
2734                 if (crc_rd_wrk && crc_rd_wrk->crtc) {
2735                         old_crtc = crc_rd_wrk->crtc;
2736                         old_acrtc = to_amdgpu_crtc(old_crtc);
2737                 }
2738                 new_acrtc = to_amdgpu_crtc(new_crtc);
2739
2740                 if (old_crtc && old_crtc != new_crtc) {
2741                         old_acrtc->dm_irq_params.crc_window.activated = false;
2742                         old_acrtc->dm_irq_params.crc_window.update_win = false;
2743                         old_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
2744
2745                         new_acrtc->dm_irq_params.crc_window.activated = true;
2746                         new_acrtc->dm_irq_params.crc_window.update_win = true;
2747                         new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
2748                         crc_rd_wrk->crtc = new_crtc;
2749                 } else {
2750                         new_acrtc->dm_irq_params.crc_window.activated = true;
2751                         new_acrtc->dm_irq_params.crc_window.update_win = true;
2752                         new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
2753                         crc_rd_wrk->crtc = new_crtc;
2754                 }
2755                 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
2756                 spin_unlock_irq(&adev_to_drm(adev)->event_lock);
2757         }
2758
2759         return 0;
2760 }
2761
2762 /*
2763  * Get crc window update flag
2764  */
2765 static int crc_win_update_get(void *data, u64 *val)
2766 {
2767         *val = 0;
2768         return 0;
2769 }
2770
2771 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get,
2772                          crc_win_update_set, "%llu\n");
2773
2774 void crtc_debugfs_init(struct drm_crtc *crtc)
2775 {
2776         struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry);
2777
2778         if (!dir)
2779                 return;
2780
2781         debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc,
2782                                    &crc_win_x_start_fops);
2783         debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc,
2784                                    &crc_win_y_start_fops);
2785         debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc,
2786                                    &crc_win_x_end_fops);
2787         debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc,
2788                                    &crc_win_y_end_fops);
2789         debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc,
2790                                    &crc_win_update_fops);
2791
2792 }
2793 #endif
2794 /*
2795  * Writes DTN log state to the user supplied buffer.
2796  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
2797  */
2798 static ssize_t dtn_log_read(
2799         struct file *f,
2800         char __user *buf,
2801         size_t size,
2802         loff_t *pos)
2803 {
2804         struct amdgpu_device *adev = file_inode(f)->i_private;
2805         struct dc *dc = adev->dm.dc;
2806         struct dc_log_buffer_ctx log_ctx = { 0 };
2807         ssize_t result = 0;
2808
2809         if (!buf || !size)
2810                 return -EINVAL;
2811
2812         if (!dc->hwss.log_hw_state)
2813                 return 0;
2814
2815         dc->hwss.log_hw_state(dc, &log_ctx);
2816
2817         if (*pos < log_ctx.pos) {
2818                 size_t to_copy = log_ctx.pos - *pos;
2819
2820                 to_copy = min(to_copy, size);
2821
2822                 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) {
2823                         *pos += to_copy;
2824                         result = to_copy;
2825                 }
2826         }
2827
2828         kfree(log_ctx.buf);
2829
2830         return result;
2831 }
2832
2833 /*
2834  * Writes DTN log state to dmesg when triggered via a write.
2835  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
2836  */
2837 static ssize_t dtn_log_write(
2838         struct file *f,
2839         const char __user *buf,
2840         size_t size,
2841         loff_t *pos)
2842 {
2843         struct amdgpu_device *adev = file_inode(f)->i_private;
2844         struct dc *dc = adev->dm.dc;
2845
2846         /* Write triggers log output via dmesg. */
2847         if (size == 0)
2848                 return 0;
2849
2850         if (dc->hwss.log_hw_state)
2851                 dc->hwss.log_hw_state(dc, NULL);
2852
2853         return size;
2854 }
2855
2856 /*
2857  * Backlight at this moment.  Read only.
2858  * As written to display, taking ABM and backlight lut into account.
2859  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2860  */
2861 static int current_backlight_show(struct seq_file *m, void *unused)
2862 {
2863         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2864         struct amdgpu_display_manager *dm = &adev->dm;
2865
2866         unsigned int backlight = dc_link_get_backlight_level(dm->backlight_link);
2867
2868         seq_printf(m, "0x%x\n", backlight);
2869         return 0;
2870 }
2871
2872 /*
2873  * Backlight value that is being approached.  Read only.
2874  * As written to display, taking ABM and backlight lut into account.
2875  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2876  */
2877 static int target_backlight_show(struct seq_file *m, void *unused)
2878 {
2879         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2880         struct amdgpu_display_manager *dm = &adev->dm;
2881
2882         unsigned int backlight = dc_link_get_target_backlight_pwm(dm->backlight_link);
2883
2884         seq_printf(m, "0x%x\n", backlight);
2885         return 0;
2886 }
2887
2888 static int mst_topo_show(struct seq_file *m, void *unused)
2889 {
2890         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2891         struct drm_device *dev = adev_to_drm(adev);
2892         struct drm_connector *connector;
2893         struct drm_connector_list_iter conn_iter;
2894         struct amdgpu_dm_connector *aconnector;
2895
2896         drm_connector_list_iter_begin(dev, &conn_iter);
2897         drm_for_each_connector_iter(connector, &conn_iter) {
2898                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
2899                         continue;
2900
2901                 aconnector = to_amdgpu_dm_connector(connector);
2902
2903                 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
2904                 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
2905         }
2906         drm_connector_list_iter_end(&conn_iter);
2907
2908         return 0;
2909 }
2910
2911 /*
2912  * Sets the force_timing_sync debug optino from the given string.
2913  * All connected displays will be force synchronized immediately.
2914  * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
2915  */
2916 static int force_timing_sync_set(void *data, u64 val)
2917 {
2918         struct amdgpu_device *adev = data;
2919
2920         adev->dm.force_timing_sync = (bool)val;
2921
2922         amdgpu_dm_trigger_timing_sync(adev_to_drm(adev));
2923
2924         return 0;
2925 }
2926
2927 /*
2928  * Gets the force_timing_sync debug option value into the given buffer.
2929  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
2930  */
2931 static int force_timing_sync_get(void *data, u64 *val)
2932 {
2933         struct amdgpu_device *adev = data;
2934
2935         *val = adev->dm.force_timing_sync;
2936
2937         return 0;
2938 }
2939
2940 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get,
2941                          force_timing_sync_set, "%llu\n");
2942
2943 /*
2944  * Sets the DC visual confirm debug option from the given string.
2945  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm
2946  */
2947 static int visual_confirm_set(void *data, u64 val)
2948 {
2949         struct amdgpu_device *adev = data;
2950
2951         adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
2952
2953         return 0;
2954 }
2955
2956 /*
2957  * Reads the DC visual confirm debug option value into the given buffer.
2958  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
2959  */
2960 static int visual_confirm_get(void *data, u64 *val)
2961 {
2962         struct amdgpu_device *adev = data;
2963
2964         *val = adev->dm.dc->debug.visual_confirm;
2965
2966         return 0;
2967 }
2968
2969 DEFINE_SHOW_ATTRIBUTE(current_backlight);
2970 DEFINE_SHOW_ATTRIBUTE(target_backlight);
2971 DEFINE_SHOW_ATTRIBUTE(mst_topo);
2972 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
2973                          visual_confirm_set, "%llu\n");
2974
2975 void dtn_debugfs_init(struct amdgpu_device *adev)
2976 {
2977         static const struct file_operations dtn_log_fops = {
2978                 .owner = THIS_MODULE,
2979                 .read = dtn_log_read,
2980                 .write = dtn_log_write,
2981                 .llseek = default_llseek
2982         };
2983
2984         struct drm_minor *minor = adev_to_drm(adev)->primary;
2985         struct dentry *root = minor->debugfs_root;
2986
2987         debugfs_create_file("amdgpu_current_backlight_pwm", 0444,
2988                             root, adev, &current_backlight_fops);
2989         debugfs_create_file("amdgpu_target_backlight_pwm", 0444,
2990                             root, adev, &target_backlight_fops);
2991         debugfs_create_file("amdgpu_mst_topology", 0444, root,
2992                             adev, &mst_topo_fops);
2993         debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
2994                             &dtn_log_fops);
2995
2996         debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
2997                                    &visual_confirm_fops);
2998
2999         debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root,
3000                                    adev, &dmub_tracebuffer_fops);
3001
3002         debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root,
3003                                    adev, &dmub_fw_state_fops);
3004
3005         debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,
3006                                    adev, &force_timing_sync_ops);
3007
3008         debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
3009                                    adev, &dmcub_trace_event_state_fops);
3010 }