drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "link_enc_cfg.h"
  32 #include "dc/inc/core_types.h"
  33 #include "dal_asic_id.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "dc/inc/hw/dmcu.h"
  36 #include "dc/inc/hw/abm.h"
  37 #include "dc/dc_dmub_srv.h"
  38 #include "dc/dc_edid_parser.h"
  39 #include "dc/dc_stat.h"
  40 #include "amdgpu_dm_trace.h"
  41 #include "dpcd_defs.h"
  42 #include "link/protocols/link_dpcd.h"
  43 #include "link_service_types.h"
  44 #include "link/protocols/link_dp_capability.h"
  45 #include "link/protocols/link_ddc.h"
  46
  47 #include "vid.h"
  48 #include "amdgpu.h"
  49 #include "amdgpu_display.h"
  50 #include "amdgpu_ucode.h"
  51 #include "atom.h"
  52 #include "amdgpu_dm.h"
  53 #include "amdgpu_dm_plane.h"
  54 #include "amdgpu_dm_crtc.h"
  55 #include "amdgpu_dm_hdcp.h"
  56 #include <drm/display/drm_hdcp_helper.h>
  57 #include "amdgpu_pm.h"
  58 #include "amdgpu_atombios.h"
  59
  60 #include "amd_shared.h"
  61 #include "amdgpu_dm_irq.h"
  62 #include "dm_helpers.h"
  63 #include "amdgpu_dm_mst_types.h"
  64 #if defined(CONFIG_DEBUG_FS)
  65 #include "amdgpu_dm_debugfs.h"
  66 #endif
  67 #include "amdgpu_dm_psr.h"
  68
  69 #include "ivsrcid/ivsrcid_vislands30.h"
  70
  71 #include <linux/backlight.h>
  72 #include <linux/module.h>
  73 #include <linux/moduleparam.h>
  74 #include <linux/types.h>
  75 #include <linux/pm_runtime.h>
  76 #include <linux/pci.h>
  77 #include <linux/firmware.h>
  78 #include <linux/component.h>
  79 #include <linux/dmi.h>
  80
  81 #include <drm/display/drm_dp_mst_helper.h>
  82 #include <drm/display/drm_hdmi_helper.h>
  83 #include <drm/drm_atomic.h>
  84 #include <drm/drm_atomic_uapi.h>
  85 #include <drm/drm_atomic_helper.h>
  86 #include <drm/drm_blend.h>
  87 #include <drm/drm_fourcc.h>
  88 #include <drm/drm_edid.h>
  89 #include <drm/drm_vblank.h>
  90 #include <drm/drm_audio_component.h>
  91 #include <drm/drm_gem_atomic_helper.h>
  92 #include <drm/drm_plane_helper.h>
  93
  94 #include <acpi/video.h>
  95
  96 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  97
  98 #include "dcn/dcn_1_0_offset.h"
  99 #include "dcn/dcn_1_0_sh_mask.h"
 100 #include "soc15_hw_ip.h"
 101 #include "soc15_common.h"
 102 #include "vega10_ip_offset.h"
 103
 104 #include "gc/gc_11_0_0_offset.h"
 105 #include "gc/gc_11_0_0_sh_mask.h"
 106
 107 #include "modules/inc/mod_freesync.h"
 108 #include "modules/power/power_helpers.h"
 109
 110 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 111 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 112 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 113 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 114 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 115 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 116 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 117 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 118 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 119 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 120 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 121 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 122 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 123 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 124 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 125 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 126 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 127 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 128 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 129 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 130 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 131 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 132
 133 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 134 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 135 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 137
 138 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 139 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 140
 141 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 142 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 143
 144 /* Number of bytes in PSP header for firmware. */
 145 #define PSP_HEADER_BYTES 0x100
 146
 147 /* Number of bytes in PSP footer for firmware. */
 148 #define PSP_FOOTER_BYTES 0x100
 149
 150 /**
 151  * DOC: overview
 152  *
 153  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 154  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 155  * requests into DC requests, and DC responses into DRM responses.
 156  *
 157  * The root control structure is &struct amdgpu_display_manager.
 158  */
 159
 160 /* basic init/fini API */
 161 static int amdgpu_dm_init(struct amdgpu_device *adev);
 162 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 163 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 164
 165 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 166 {
 167         switch (link->dpcd_caps.dongle_type) {
 168         case DISPLAY_DONGLE_NONE:
 169                 return DRM_MODE_SUBCONNECTOR_Native;
 170         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 171                 return DRM_MODE_SUBCONNECTOR_VGA;
 172         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 173         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 174                 return DRM_MODE_SUBCONNECTOR_DVID;
 175         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 176         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 177                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 178         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 179         default:
 180                 return DRM_MODE_SUBCONNECTOR_Unknown;
 181         }
 182 }
 183
 184 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 185 {
 186         struct dc_link *link = aconnector->dc_link;
 187         struct drm_connector *connector = &aconnector->base;
 188         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 189
 190         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 191                 return;
 192
 193         if (aconnector->dc_sink)
 194                 subconnector = get_subconnector_type(link);
 195
 196         drm_object_property_set_value(&connector->base,
 197                         connector->dev->mode_config.dp_subconnector_property,
 198                         subconnector);
 199 }
 200
 201 /*
 202  * initializes drm_device display related structures, based on the information
 203  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 204  * drm_encoder, drm_mode_config
 205  *
 206  * Returns 0 on success
 207  */
 208 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 209 /* removes and deallocates the drm structures, created by the above function */
 210 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 211
 212 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 213                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 214                                     u32 link_index,
 215                                     struct amdgpu_encoder *amdgpu_encoder);
 216 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 217                                   struct amdgpu_encoder *aencoder,
 218                                   uint32_t link_index);
 219
 220 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 221
 222 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 223
 224 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 225                                   struct drm_atomic_state *state);
 226
 227 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 228 static void handle_hpd_rx_irq(void *param);
 229
 230 static bool
 231 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 232                                  struct drm_crtc_state *new_crtc_state);
 233 /*
 234  * dm_vblank_get_counter
 235  *
 236  * @brief
 237  * Get counter for number of vertical blanks
 238  *
 239  * @param
 240  * struct amdgpu_device *adev - [in] desired amdgpu device
 241  * int disp_idx - [in] which CRTC to get the counter from
 242  *
 243  * @return
 244  * Counter for vertical blanks
 245  */
 246 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 247 {
 248         if (crtc >= adev->mode_info.num_crtc)
 249                 return 0;
 250         else {
 251                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 252
 253                 if (acrtc->dm_irq_params.stream == NULL) {
 254                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 255                                   crtc);
 256                         return 0;
 257                 }
 258
 259                 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 260         }
 261 }
 262
 263 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 264                                   u32 *vbl, u32 *position)
 265 {
 266         u32 v_blank_start, v_blank_end, h_position, v_position;
 267
 268         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 269                 return -EINVAL;
 270         else {
 271                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 272
 273                 if (acrtc->dm_irq_params.stream ==  NULL) {
 274                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 275                                   crtc);
 276                         return 0;
 277                 }
 278
 279                 /*
 280                  * TODO rework base driver to use values directly.
 281                  * for now parse it back into reg-format
 282                  */
 283                 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 284                                          &v_blank_start,
 285                                          &v_blank_end,
 286                                          &h_position,
 287                                          &v_position);
 288
 289                 *position = v_position | (h_position << 16);
 290                 *vbl = v_blank_start | (v_blank_end << 16);
 291         }
 292
 293         return 0;
 294 }
 295
 296 static bool dm_is_idle(void *handle)
 297 {
 298         /* XXX todo */
 299         return true;
 300 }
 301
 302 static int dm_wait_for_idle(void *handle)
 303 {
 304         /* XXX todo */
 305         return 0;
 306 }
 307
 308 static bool dm_check_soft_reset(void *handle)
 309 {
 310         return false;
 311 }
 312
 313 static int dm_soft_reset(void *handle)
 314 {
 315         /* XXX todo */
 316         return 0;
 317 }
 318
 319 static struct amdgpu_crtc *
 320 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 321                      int otg_inst)
 322 {
 323         struct drm_device *dev = adev_to_drm(adev);
 324         struct drm_crtc *crtc;
 325         struct amdgpu_crtc *amdgpu_crtc;
 326
 327         if (WARN_ON(otg_inst == -1))
 328                 return adev->mode_info.crtcs[0];
 329
 330         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 331                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 332
 333                 if (amdgpu_crtc->otg_inst == otg_inst)
 334                         return amdgpu_crtc;
 335         }
 336
 337         return NULL;
 338 }
 339
 340 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 341                                               struct dm_crtc_state *new_state)
 342 {
 343         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 344                 return true;
 345         else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
 346                 return true;
 347         else
 348                 return false;
 349 }
 350
 351 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
 352                                         int planes_count)
 353 {
 354         int i, j;
 355
 356         for (i = 0, j = planes_count - 1; i < j; i++, j--)
 357                 swap(array_of_surface_update[i], array_of_surface_update[j]);
 358 }
 359
 360 /**
 361  * update_planes_and_stream_adapter() - Send planes to be updated in DC
 362  *
 363  * DC has a generic way to update planes and stream via
 364  * dc_update_planes_and_stream function; however, DM might need some
 365  * adjustments and preparation before calling it. This function is a wrapper
 366  * for the dc_update_planes_and_stream that does any required configuration
 367  * before passing control to DC.
 368  */
 369 static inline bool update_planes_and_stream_adapter(struct dc *dc,
 370                                                     int update_type,
 371                                                     int planes_count,
 372                                                     struct dc_stream_state *stream,
 373                                                     struct dc_stream_update *stream_update,
 374                                                     struct dc_surface_update *array_of_surface_update)
 375 {
 376         reverse_planes_order(array_of_surface_update, planes_count);
 377
 378         /*
 379          * Previous frame finished and HW is ready for optimization.
 380          */
 381         if (update_type == UPDATE_TYPE_FAST)
 382                 dc_post_update_surfaces_to_stream(dc);
 383
 384         return dc_update_planes_and_stream(dc,
 385                                            array_of_surface_update,
 386                                            planes_count,
 387                                            stream,
 388                                            stream_update);
 389 }
 390
 391 /**
 392  * dm_pflip_high_irq() - Handle pageflip interrupt
 393  * @interrupt_params: ignored
 394  *
 395  * Handles the pageflip interrupt by notifying all interested parties
 396  * that the pageflip has been completed.
 397  */
 398 static void dm_pflip_high_irq(void *interrupt_params)
 399 {
 400         struct amdgpu_crtc *amdgpu_crtc;
 401         struct common_irq_params *irq_params = interrupt_params;
 402         struct amdgpu_device *adev = irq_params->adev;
 403         unsigned long flags;
 404         struct drm_pending_vblank_event *e;
 405         u32 vpos, hpos, v_blank_start, v_blank_end;
 406         bool vrr_active;
 407
 408         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 409
 410         /* IRQ could occur when in initial stage */
 411         /* TODO work and BO cleanup */
 412         if (amdgpu_crtc == NULL) {
 413                 DC_LOG_PFLIP("CRTC is null, returning.\n");
 414                 return;
 415         }
 416
 417         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 418
 419         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 420                 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 421                                                  amdgpu_crtc->pflip_status,
 422                                                  AMDGPU_FLIP_SUBMITTED,
 423                                                  amdgpu_crtc->crtc_id,
 424                                                  amdgpu_crtc);
 425                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 426                 return;
 427         }
 428
 429         /* page flip completed. */
 430         e = amdgpu_crtc->event;
 431         amdgpu_crtc->event = NULL;
 432
 433         WARN_ON(!e);
 434
 435         vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
 436
 437         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 438         if (!vrr_active ||
 439             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 440                                       &v_blank_end, &hpos, &vpos) ||
 441             (vpos < v_blank_start)) {
 442                 /* Update to correct count and vblank timestamp if racing with
 443                  * vblank irq. This also updates to the correct vblank timestamp
 444                  * even in VRR mode, as scanout is past the front-porch atm.
 445                  */
 446                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 447
 448                 /* Wake up userspace by sending the pageflip event with proper
 449                  * count and timestamp of vblank of flip completion.
 450                  */
 451                 if (e) {
 452                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 453
 454                         /* Event sent, so done with vblank for this flip */
 455                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 456                 }
 457         } else if (e) {
 458                 /* VRR active and inside front-porch: vblank count and
 459                  * timestamp for pageflip event will only be up to date after
 460                  * drm_crtc_handle_vblank() has been executed from late vblank
 461                  * irq handler after start of back-porch (vline 0). We queue the
 462                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 463                  * updated timestamp and count, once it runs after us.
 464                  *
 465                  * We need to open-code this instead of using the helper
 466                  * drm_crtc_arm_vblank_event(), as that helper would
 467                  * call drm_crtc_accurate_vblank_count(), which we must
 468                  * not call in VRR mode while we are in front-porch!
 469                  */
 470
 471                 /* sequence will be replaced by real count during send-out. */
 472                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 473                 e->pipe = amdgpu_crtc->crtc_id;
 474
 475                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 476                 e = NULL;
 477         }
 478
 479         /* Keep track of vblank of this flip for flip throttling. We use the
 480          * cooked hw counter, as that one incremented at start of this vblank
 481          * of pageflip completion, so last_flip_vblank is the forbidden count
 482          * for queueing new pageflips if vsync + VRR is enabled.
 483          */
 484         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 485                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 486
 487         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 488         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 489
 490         DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 491                      amdgpu_crtc->crtc_id, amdgpu_crtc,
 492                      vrr_active, (int) !e);
 493 }
 494
 495 static void dm_vupdate_high_irq(void *interrupt_params)
 496 {
 497         struct common_irq_params *irq_params = interrupt_params;
 498         struct amdgpu_device *adev = irq_params->adev;
 499         struct amdgpu_crtc *acrtc;
 500         struct drm_device *drm_dev;
 501         struct drm_vblank_crtc *vblank;
 502         ktime_t frame_duration_ns, previous_timestamp;
 503         unsigned long flags;
 504         int vrr_active;
 505
 506         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 507
 508         if (acrtc) {
 509                 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 510                 drm_dev = acrtc->base.dev;
 511                 vblank = &drm_dev->vblank[acrtc->base.index];
 512                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 513                 frame_duration_ns = vblank->time - previous_timestamp;
 514
 515                 if (frame_duration_ns > 0) {
 516                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 517                                                 frame_duration_ns,
 518                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 519                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 520                 }
 521
 522                 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
 523                               acrtc->crtc_id,
 524                               vrr_active);
 525
 526                 /* Core vblank handling is done here after end of front-porch in
 527                  * vrr mode, as vblank timestamping will give valid results
 528                  * while now done after front-porch. This will also deliver
 529                  * page-flip completion events that have been queued to us
 530                  * if a pageflip happened inside front-porch.
 531                  */
 532                 if (vrr_active) {
 533                         amdgpu_dm_crtc_handle_vblank(acrtc);
 534
 535                         /* BTR processing for pre-DCE12 ASICs */
 536                         if (acrtc->dm_irq_params.stream &&
 537                             adev->family < AMDGPU_FAMILY_AI) {
 538                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 539                                 mod_freesync_handle_v_update(
 540                                     adev->dm.freesync_module,
 541                                     acrtc->dm_irq_params.stream,
 542                                     &acrtc->dm_irq_params.vrr_params);
 543
 544                                 dc_stream_adjust_vmin_vmax(
 545                                     adev->dm.dc,
 546                                     acrtc->dm_irq_params.stream,
 547                                     &acrtc->dm_irq_params.vrr_params.adjust);
 548                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 549                         }
 550                 }
 551         }
 552 }
 553
 554 /**
 555  * dm_crtc_high_irq() - Handles CRTC interrupt
 556  * @interrupt_params: used for determining the CRTC instance
 557  *
 558  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 559  * event handler.
 560  */
 561 static void dm_crtc_high_irq(void *interrupt_params)
 562 {
 563         struct common_irq_params *irq_params = interrupt_params;
 564         struct amdgpu_device *adev = irq_params->adev;
 565         struct amdgpu_crtc *acrtc;
 566         unsigned long flags;
 567         int vrr_active;
 568
 569         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 570         if (!acrtc)
 571                 return;
 572
 573         vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 574
 575         DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 576                       vrr_active, acrtc->dm_irq_params.active_planes);
 577
 578         /**
 579          * Core vblank handling at start of front-porch is only possible
 580          * in non-vrr mode, as only there vblank timestamping will give
 581          * valid results while done in front-porch. Otherwise defer it
 582          * to dm_vupdate_high_irq after end of front-porch.
 583          */
 584         if (!vrr_active)
 585                 amdgpu_dm_crtc_handle_vblank(acrtc);
 586
 587         /**
 588          * Following stuff must happen at start of vblank, for crc
 589          * computation and below-the-range btr support in vrr mode.
 590          */
 591         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 592
 593         /* BTR updates need to happen before VUPDATE on Vega and above. */
 594         if (adev->family < AMDGPU_FAMILY_AI)
 595                 return;
 596
 597         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 598
 599         if (acrtc->dm_irq_params.stream &&
 600             acrtc->dm_irq_params.vrr_params.supported &&
 601             acrtc->dm_irq_params.freesync_config.state ==
 602                     VRR_STATE_ACTIVE_VARIABLE) {
 603                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 604                                              acrtc->dm_irq_params.stream,
 605                                              &acrtc->dm_irq_params.vrr_params);
 606
 607                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 608                                            &acrtc->dm_irq_params.vrr_params.adjust);
 609         }
 610
 611         /*
 612          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 613          * In that case, pageflip completion interrupts won't fire and pageflip
 614          * completion events won't get delivered. Prevent this by sending
 615          * pending pageflip events from here if a flip is still pending.
 616          *
 617          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 618          * avoid race conditions between flip programming and completion,
 619          * which could cause too early flip completion events.
 620          */
 621         if (adev->family >= AMDGPU_FAMILY_RV &&
 622             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 623             acrtc->dm_irq_params.active_planes == 0) {
 624                 if (acrtc->event) {
 625                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 626                         acrtc->event = NULL;
 627                         drm_crtc_vblank_put(&acrtc->base);
 628                 }
 629                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 630         }
 631
 632         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 633 }
 634
 635 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 636 /**
 637  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 638  * DCN generation ASICs
 639  * @interrupt_params: interrupt parameters
 640  *
 641  * Used to set crc window/read out crc value at vertical line 0 position
 642  */
 643 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 644 {
 645         struct common_irq_params *irq_params = interrupt_params;
 646         struct amdgpu_device *adev = irq_params->adev;
 647         struct amdgpu_crtc *acrtc;
 648
 649         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 650
 651         if (!acrtc)
 652                 return;
 653
 654         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 655 }
 656 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 657
 658 /**
 659  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 660  * @adev: amdgpu_device pointer
 661  * @notify: dmub notification structure
 662  *
 663  * Dmub AUX or SET_CONFIG command completion processing callback
 664  * Copies dmub notification to DM which is to be read by AUX command.
 665  * issuing thread and also signals the event to wake up the thread.
 666  */
 667 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 668                                         struct dmub_notification *notify)
 669 {
 670         if (adev->dm.dmub_notify)
 671                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 672         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 673                 complete(&adev->dm.dmub_aux_transfer_done);
 674 }
 675
 676 /**
 677  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 678  * @adev: amdgpu_device pointer
 679  * @notify: dmub notification structure
 680  *
 681  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 682  * ink index and calls helper to do the processing.
 683  */
 684 static void dmub_hpd_callback(struct amdgpu_device *adev,
 685                               struct dmub_notification *notify)
 686 {
 687         struct amdgpu_dm_connector *aconnector;
 688         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 689         struct drm_connector *connector;
 690         struct drm_connector_list_iter iter;
 691         struct dc_link *link;
 692         u8 link_index = 0;
 693         struct drm_device *dev;
 694
 695         if (adev == NULL)
 696                 return;
 697
 698         if (notify == NULL) {
 699                 DRM_ERROR("DMUB HPD callback notification was NULL");
 700                 return;
 701         }
 702
 703         if (notify->link_index > adev->dm.dc->link_count) {
 704                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 705                 return;
 706         }
 707
 708         link_index = notify->link_index;
 709         link = adev->dm.dc->links[link_index];
 710         dev = adev->dm.ddev;
 711
 712         drm_connector_list_iter_begin(dev, &iter);
 713         drm_for_each_connector_iter(connector, &iter) {
 714                 aconnector = to_amdgpu_dm_connector(connector);
 715                 if (link && aconnector->dc_link == link) {
 716                         if (notify->type == DMUB_NOTIFICATION_HPD)
 717                                 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 718                         else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 719                                 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
 720                         else
 721                                 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
 722                                                 notify->type, link_index);
 723
 724                         hpd_aconnector = aconnector;
 725                         break;
 726                 }
 727         }
 728         drm_connector_list_iter_end(&iter);
 729
 730         if (hpd_aconnector) {
 731                 if (notify->type == DMUB_NOTIFICATION_HPD)
 732                         handle_hpd_irq_helper(hpd_aconnector);
 733                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 734                         handle_hpd_rx_irq(hpd_aconnector);
 735         }
 736 }
 737
 738 /**
 739  * register_dmub_notify_callback - Sets callback for DMUB notify
 740  * @adev: amdgpu_device pointer
 741  * @type: Type of dmub notification
 742  * @callback: Dmub interrupt callback function
 743  * @dmub_int_thread_offload: offload indicator
 744  *
 745  * API to register a dmub callback handler for a dmub notification
 746  * Also sets indicator whether callback processing to be offloaded.
 747  * to dmub interrupt handling thread
 748  * Return: true if successfully registered, false if there is existing registration
 749  */
 750 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 751                                           enum dmub_notification_type type,
 752                                           dmub_notify_interrupt_callback_t callback,
 753                                           bool dmub_int_thread_offload)
 754 {
 755         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 756                 adev->dm.dmub_callback[type] = callback;
 757                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 758         } else
 759                 return false;
 760
 761         return true;
 762 }
 763
 764 static void dm_handle_hpd_work(struct work_struct *work)
 765 {
 766         struct dmub_hpd_work *dmub_hpd_wrk;
 767
 768         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 769
 770         if (!dmub_hpd_wrk->dmub_notify) {
 771                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 772                 return;
 773         }
 774
 775         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 776                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 777                 dmub_hpd_wrk->dmub_notify);
 778         }
 779
 780         kfree(dmub_hpd_wrk->dmub_notify);
 781         kfree(dmub_hpd_wrk);
 782
 783 }
 784
 785 #define DMUB_TRACE_MAX_READ 64
 786 /**
 787  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 788  * @interrupt_params: used for determining the Outbox instance
 789  *
 790  * Handles the Outbox Interrupt
 791  * event handler.
 792  */
 793 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 794 {
 795         struct dmub_notification notify;
 796         struct common_irq_params *irq_params = interrupt_params;
 797         struct amdgpu_device *adev = irq_params->adev;
 798         struct amdgpu_display_manager *dm = &adev->dm;
 799         struct dmcub_trace_buf_entry entry = { 0 };
 800         u32 count = 0;
 801         struct dmub_hpd_work *dmub_hpd_wrk;
 802         struct dc_link *plink = NULL;
 803
 804         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 805                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 806
 807                 do {
 808                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 809                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 810                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 811                                 continue;
 812                         }
 813                         if (!dm->dmub_callback[notify.type]) {
 814                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 815                                 continue;
 816                         }
 817                         if (dm->dmub_thread_offload[notify.type] == true) {
 818                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 819                                 if (!dmub_hpd_wrk) {
 820                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 821                                         return;
 822                                 }
 823                                 dmub_hpd_wrk->dmub_notify = kmemdup(&notify, sizeof(struct dmub_notification),
 824                                                                     GFP_ATOMIC);
 825                                 if (!dmub_hpd_wrk->dmub_notify) {
 826                                         kfree(dmub_hpd_wrk);
 827                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 828                                         return;
 829                                 }
 830                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 831                                 dmub_hpd_wrk->adev = adev;
 832                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 833                                         plink = adev->dm.dc->links[notify.link_index];
 834                                         if (plink) {
 835                                                 plink->hpd_status =
 836                                                         notify.hpd_status == DP_HPD_PLUG;
 837                                         }
 838                                 }
 839                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 840                         } else {
 841                                 dm->dmub_callback[notify.type](adev, &notify);
 842                         }
 843                 } while (notify.pending_notification);
 844         }
 845
 846
 847         do {
 848                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 849                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 850                                                         entry.param0, entry.param1);
 851
 852                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 853                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 854                 } else
 855                         break;
 856
 857                 count++;
 858
 859         } while (count <= DMUB_TRACE_MAX_READ);
 860
 861         if (count > DMUB_TRACE_MAX_READ)
 862                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 863 }
 864
 865 static int dm_set_clockgating_state(void *handle,
 866                   enum amd_clockgating_state state)
 867 {
 868         return 0;
 869 }
 870
 871 static int dm_set_powergating_state(void *handle,
 872                   enum amd_powergating_state state)
 873 {
 874         return 0;
 875 }
 876
 877 /* Prototypes of private functions */
 878 static int dm_early_init(void* handle);
 879
 880 /* Allocate memory for FBC compressed data  */
 881 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 882 {
 883         struct drm_device *dev = connector->dev;
 884         struct amdgpu_device *adev = drm_to_adev(dev);
 885         struct dm_compressor_info *compressor = &adev->dm.compressor;
 886         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 887         struct drm_display_mode *mode;
 888         unsigned long max_size = 0;
 889
 890         if (adev->dm.dc->fbc_compressor == NULL)
 891                 return;
 892
 893         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 894                 return;
 895
 896         if (compressor->bo_ptr)
 897                 return;
 898
 899
 900         list_for_each_entry(mode, &connector->modes, head) {
 901                 if (max_size < mode->htotal * mode->vtotal)
 902                         max_size = mode->htotal * mode->vtotal;
 903         }
 904
 905         if (max_size) {
 906                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 907                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 908                             &compressor->gpu_addr, &compressor->cpu_addr);
 909
 910                 if (r)
 911                         DRM_ERROR("DM: Failed to initialize FBC\n");
 912                 else {
 913                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 914                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 915                 }
 916
 917         }
 918
 919 }
 920
 921 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 922                                           int pipe, bool *enabled,
 923                                           unsigned char *buf, int max_bytes)
 924 {
 925         struct drm_device *dev = dev_get_drvdata(kdev);
 926         struct amdgpu_device *adev = drm_to_adev(dev);
 927         struct drm_connector *connector;
 928         struct drm_connector_list_iter conn_iter;
 929         struct amdgpu_dm_connector *aconnector;
 930         int ret = 0;
 931
 932         *enabled = false;
 933
 934         mutex_lock(&adev->dm.audio_lock);
 935
 936         drm_connector_list_iter_begin(dev, &conn_iter);
 937         drm_for_each_connector_iter(connector, &conn_iter) {
 938                 aconnector = to_amdgpu_dm_connector(connector);
 939                 if (aconnector->audio_inst != port)
 940                         continue;
 941
 942                 *enabled = true;
 943                 ret = drm_eld_size(connector->eld);
 944                 memcpy(buf, connector->eld, min(max_bytes, ret));
 945
 946                 break;
 947         }
 948         drm_connector_list_iter_end(&conn_iter);
 949
 950         mutex_unlock(&adev->dm.audio_lock);
 951
 952         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 953
 954         return ret;
 955 }
 956
 957 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 958         .get_eld = amdgpu_dm_audio_component_get_eld,
 959 };
 960
 961 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 962                                        struct device *hda_kdev, void *data)
 963 {
 964         struct drm_device *dev = dev_get_drvdata(kdev);
 965         struct amdgpu_device *adev = drm_to_adev(dev);
 966         struct drm_audio_component *acomp = data;
 967
 968         acomp->ops = &amdgpu_dm_audio_component_ops;
 969         acomp->dev = kdev;
 970         adev->dm.audio_component = acomp;
 971
 972         return 0;
 973 }
 974
 975 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 976                                           struct device *hda_kdev, void *data)
 977 {
 978         struct drm_device *dev = dev_get_drvdata(kdev);
 979         struct amdgpu_device *adev = drm_to_adev(dev);
 980         struct drm_audio_component *acomp = data;
 981
 982         acomp->ops = NULL;
 983         acomp->dev = NULL;
 984         adev->dm.audio_component = NULL;
 985 }
 986
 987 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 988         .bind   = amdgpu_dm_audio_component_bind,
 989         .unbind = amdgpu_dm_audio_component_unbind,
 990 };
 991
 992 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
 993 {
 994         int i, ret;
 995
 996         if (!amdgpu_audio)
 997                 return 0;
 998
 999         adev->mode_info.audio.enabled = true;
1000
1001         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1002
1003         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1004                 adev->mode_info.audio.pin[i].channels = -1;
1005                 adev->mode_info.audio.pin[i].rate = -1;
1006                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1007                 adev->mode_info.audio.pin[i].status_bits = 0;
1008                 adev->mode_info.audio.pin[i].category_code = 0;
1009                 adev->mode_info.audio.pin[i].connected = false;
1010                 adev->mode_info.audio.pin[i].id =
1011                         adev->dm.dc->res_pool->audios[i]->inst;
1012                 adev->mode_info.audio.pin[i].offset = 0;
1013         }
1014
1015         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1016         if (ret < 0)
1017                 return ret;
1018
1019         adev->dm.audio_registered = true;
1020
1021         return 0;
1022 }
1023
1024 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1025 {
1026         if (!amdgpu_audio)
1027                 return;
1028
1029         if (!adev->mode_info.audio.enabled)
1030                 return;
1031
1032         if (adev->dm.audio_registered) {
1033                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1034                 adev->dm.audio_registered = false;
1035         }
1036
1037         /* TODO: Disable audio? */
1038
1039         adev->mode_info.audio.enabled = false;
1040 }
1041
1042 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1043 {
1044         struct drm_audio_component *acomp = adev->dm.audio_component;
1045
1046         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1047                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1048
1049                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1050                                                  pin, -1);
1051         }
1052 }
1053
1054 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1055 {
1056         const struct dmcub_firmware_header_v1_0 *hdr;
1057         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1058         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1059         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1060         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1061         struct abm *abm = adev->dm.dc->res_pool->abm;
1062         struct dmub_srv_hw_params hw_params;
1063         enum dmub_status status;
1064         const unsigned char *fw_inst_const, *fw_bss_data;
1065         u32 i, fw_inst_const_size, fw_bss_data_size;
1066         bool has_hw_support;
1067
1068         if (!dmub_srv)
1069                 /* DMUB isn't supported on the ASIC. */
1070                 return 0;
1071
1072         if (!fb_info) {
1073                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1074                 return -EINVAL;
1075         }
1076
1077         if (!dmub_fw) {
1078                 /* Firmware required for DMUB support. */
1079                 DRM_ERROR("No firmware provided for DMUB.\n");
1080                 return -EINVAL;
1081         }
1082
1083         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1084         if (status != DMUB_STATUS_OK) {
1085                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1086                 return -EINVAL;
1087         }
1088
1089         if (!has_hw_support) {
1090                 DRM_INFO("DMUB unsupported on ASIC\n");
1091                 return 0;
1092         }
1093
1094         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1095         status = dmub_srv_hw_reset(dmub_srv);
1096         if (status != DMUB_STATUS_OK)
1097                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1098
1099         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1100
1101         fw_inst_const = dmub_fw->data +
1102                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1103                         PSP_HEADER_BYTES;
1104
1105         fw_bss_data = dmub_fw->data +
1106                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1107                       le32_to_cpu(hdr->inst_const_bytes);
1108
1109         /* Copy firmware and bios info into FB memory. */
1110         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1111                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1112
1113         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1114
1115         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1116          * amdgpu_ucode_init_single_fw will load dmub firmware
1117          * fw_inst_const part to cw0; otherwise, the firmware back door load
1118          * will be done by dm_dmub_hw_init
1119          */
1120         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1121                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1122                                 fw_inst_const_size);
1123         }
1124
1125         if (fw_bss_data_size)
1126                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1127                        fw_bss_data, fw_bss_data_size);
1128
1129         /* Copy firmware bios info into FB memory. */
1130         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1131                adev->bios_size);
1132
1133         /* Reset regions that need to be reset. */
1134         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1135         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1136
1137         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1138                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1139
1140         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1141                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1142
1143         /* Initialize hardware. */
1144         memset(&hw_params, 0, sizeof(hw_params));
1145         hw_params.fb_base = adev->gmc.fb_start;
1146         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1147
1148         /* backdoor load firmware and trigger dmub running */
1149         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1150                 hw_params.load_inst_const = true;
1151
1152         if (dmcu)
1153                 hw_params.psp_version = dmcu->psp_version;
1154
1155         for (i = 0; i < fb_info->num_fb; ++i)
1156                 hw_params.fb[i] = &fb_info->fb[i];
1157
1158         switch (adev->ip_versions[DCE_HWIP][0]) {
1159         case IP_VERSION(3, 1, 3):
1160         case IP_VERSION(3, 1, 4):
1161                 hw_params.dpia_supported = true;
1162                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1163                 break;
1164         default:
1165                 break;
1166         }
1167
1168         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1169         if (status != DMUB_STATUS_OK) {
1170                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1171                 return -EINVAL;
1172         }
1173
1174         /* Wait for firmware load to finish. */
1175         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1176         if (status != DMUB_STATUS_OK)
1177                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1178
1179         /* Init DMCU and ABM if available. */
1180         if (dmcu && abm) {
1181                 dmcu->funcs->dmcu_init(dmcu);
1182                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1183         }
1184
1185         if (!adev->dm.dc->ctx->dmub_srv)
1186                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1187         if (!adev->dm.dc->ctx->dmub_srv) {
1188                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1189                 return -ENOMEM;
1190         }
1191
1192         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1193                  adev->dm.dmcub_fw_version);
1194
1195         return 0;
1196 }
1197
1198 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1199 {
1200         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1201         enum dmub_status status;
1202         bool init;
1203
1204         if (!dmub_srv) {
1205                 /* DMUB isn't supported on the ASIC. */
1206                 return;
1207         }
1208
1209         status = dmub_srv_is_hw_init(dmub_srv, &init);
1210         if (status != DMUB_STATUS_OK)
1211                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1212
1213         if (status == DMUB_STATUS_OK && init) {
1214                 /* Wait for firmware load to finish. */
1215                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1216                 if (status != DMUB_STATUS_OK)
1217                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1218         } else {
1219                 /* Perform the full hardware initialization. */
1220                 dm_dmub_hw_init(adev);
1221         }
1222 }
1223
1224 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1225 {
1226         u64 pt_base;
1227         u32 logical_addr_low;
1228         u32 logical_addr_high;
1229         u32 agp_base, agp_bot, agp_top;
1230         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1231
1232         memset(pa_config, 0, sizeof(*pa_config));
1233
1234         agp_base = 0;
1235         agp_bot = adev->gmc.agp_start >> 24;
1236         agp_top = adev->gmc.agp_end >> 24;
1237
1238         /* AGP aperture is disabled */
1239         if (agp_bot == agp_top) {
1240                 logical_addr_low = adev->gmc.fb_start >> 18;
1241                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1242                         /*
1243                          * Raven2 has a HW issue that it is unable to use the vram which
1244                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1245                          * workaround that increase system aperture high address (add 1)
1246                          * to get rid of the VM fault and hardware hang.
1247                          */
1248                         logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1249                 else
1250                         logical_addr_high = adev->gmc.fb_end >> 18;
1251         } else {
1252                 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1253                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1254                         /*
1255                          * Raven2 has a HW issue that it is unable to use the vram which
1256                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1257                          * workaround that increase system aperture high address (add 1)
1258                          * to get rid of the VM fault and hardware hang.
1259                          */
1260                         logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1261                 else
1262                         logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1263         }
1264
1265         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1266
1267         page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1268         page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1269         page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1270         page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1271         page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1272         page_table_base.low_part = lower_32_bits(pt_base);
1273
1274         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1275         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1276
1277         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1278         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1279         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1280
1281         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1282         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1283         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1284
1285         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1286         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1287         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1288
1289         pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1290
1291 }
1292
1293 static void force_connector_state(
1294         struct amdgpu_dm_connector *aconnector,
1295         enum drm_connector_force force_state)
1296 {
1297         struct drm_connector *connector = &aconnector->base;
1298
1299         mutex_lock(&connector->dev->mode_config.mutex);
1300         aconnector->base.force = force_state;
1301         mutex_unlock(&connector->dev->mode_config.mutex);
1302
1303         mutex_lock(&aconnector->hpd_lock);
1304         drm_kms_helper_connector_hotplug_event(connector);
1305         mutex_unlock(&aconnector->hpd_lock);
1306 }
1307
1308 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1309 {
1310         struct hpd_rx_irq_offload_work *offload_work;
1311         struct amdgpu_dm_connector *aconnector;
1312         struct dc_link *dc_link;
1313         struct amdgpu_device *adev;
1314         enum dc_connection_type new_connection_type = dc_connection_none;
1315         unsigned long flags;
1316         union test_response test_response;
1317
1318         memset(&test_response, 0, sizeof(test_response));
1319
1320         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1321         aconnector = offload_work->offload_wq->aconnector;
1322
1323         if (!aconnector) {
1324                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1325                 goto skip;
1326         }
1327
1328         adev = drm_to_adev(aconnector->base.dev);
1329         dc_link = aconnector->dc_link;
1330
1331         mutex_lock(&aconnector->hpd_lock);
1332         if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1333                 DRM_ERROR("KMS: Failed to detect connector\n");
1334         mutex_unlock(&aconnector->hpd_lock);
1335
1336         if (new_connection_type == dc_connection_none)
1337                 goto skip;
1338
1339         if (amdgpu_in_reset(adev))
1340                 goto skip;
1341
1342         mutex_lock(&adev->dm.dc_lock);
1343         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1344                 dc_link_dp_handle_automated_test(dc_link);
1345
1346                 if (aconnector->timing_changed) {
1347                         /* force connector disconnect and reconnect */
1348                         force_connector_state(aconnector, DRM_FORCE_OFF);
1349                         msleep(100);
1350                         force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1351                 }
1352
1353                 test_response.bits.ACK = 1;
1354
1355                 core_link_write_dpcd(
1356                 dc_link,
1357                 DP_TEST_RESPONSE,
1358                 &test_response.raw,
1359                 sizeof(test_response));
1360         }
1361         else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1362                         dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1363                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1364                 /* offload_work->data is from handle_hpd_rx_irq->
1365                  * schedule_hpd_rx_offload_work.this is defer handle
1366                  * for hpd short pulse. upon here, link status may be
1367                  * changed, need get latest link status from dpcd
1368                  * registers. if link status is good, skip run link
1369                  * training again.
1370                  */
1371                 union hpd_irq_data irq_data;
1372
1373                 memset(&irq_data, 0, sizeof(irq_data));
1374
1375                 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1376                  * request be added to work queue if link lost at end of dc_link_
1377                  * dp_handle_link_loss
1378                  */
1379                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1380                 offload_work->offload_wq->is_handling_link_loss = false;
1381                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1382
1383                 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1384                         dc_link_check_link_loss_status(dc_link, &irq_data))
1385                         dc_link_dp_handle_link_loss(dc_link);
1386         }
1387         mutex_unlock(&adev->dm.dc_lock);
1388
1389 skip:
1390         kfree(offload_work);
1391
1392 }
1393
1394 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1395 {
1396         int max_caps = dc->caps.max_links;
1397         int i = 0;
1398         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1399
1400         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1401
1402         if (!hpd_rx_offload_wq)
1403                 return NULL;
1404
1405
1406         for (i = 0; i < max_caps; i++) {
1407                 hpd_rx_offload_wq[i].wq =
1408                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1409
1410                 if (hpd_rx_offload_wq[i].wq == NULL) {
1411                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1412                         goto out_err;
1413                 }
1414
1415                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1416         }
1417
1418         return hpd_rx_offload_wq;
1419
1420 out_err:
1421         for (i = 0; i < max_caps; i++) {
1422                 if (hpd_rx_offload_wq[i].wq)
1423                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1424         }
1425         kfree(hpd_rx_offload_wq);
1426         return NULL;
1427 }
1428
1429 struct amdgpu_stutter_quirk {
1430         u16 chip_vendor;
1431         u16 chip_device;
1432         u16 subsys_vendor;
1433         u16 subsys_device;
1434         u8 revision;
1435 };
1436
1437 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1438         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1439         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1440         { 0, 0, 0, 0, 0 },
1441 };
1442
1443 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1444 {
1445         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1446
1447         while (p && p->chip_device != 0) {
1448                 if (pdev->vendor == p->chip_vendor &&
1449                     pdev->device == p->chip_device &&
1450                     pdev->subsystem_vendor == p->subsys_vendor &&
1451                     pdev->subsystem_device == p->subsys_device &&
1452                     pdev->revision == p->revision) {
1453                         return true;
1454                 }
1455                 ++p;
1456         }
1457         return false;
1458 }
1459
1460 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1461         {
1462                 .matches = {
1463                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1464                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1465                 },
1466         },
1467         {
1468                 .matches = {
1469                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1470                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1471                 },
1472         },
1473         {
1474                 .matches = {
1475                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1476                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1477                 },
1478         },
1479         {
1480                 .matches = {
1481                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1482                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1483                 },
1484         },
1485         {
1486                 .matches = {
1487                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1488                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1489                 },
1490         },
1491         {
1492                 .matches = {
1493                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1494                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1495                 },
1496         },
1497         {
1498                 .matches = {
1499                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1500                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1501                 },
1502         },
1503         {
1504                 .matches = {
1505                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1506                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1507                 },
1508         },
1509         {
1510                 .matches = {
1511                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1512                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1513                 },
1514         },
1515         {}
1516         /* TODO: refactor this from a fixed table to a dynamic option */
1517 };
1518
1519 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1520 {
1521         const struct dmi_system_id *dmi_id;
1522
1523         dm->aux_hpd_discon_quirk = false;
1524
1525         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1526         if (dmi_id) {
1527                 dm->aux_hpd_discon_quirk = true;
1528                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1529         }
1530 }
1531
1532 static int amdgpu_dm_init(struct amdgpu_device *adev)
1533 {
1534         struct dc_init_data init_data;
1535         struct dc_callback_init init_params;
1536         int r;
1537
1538         adev->dm.ddev = adev_to_drm(adev);
1539         adev->dm.adev = adev;
1540
1541         /* Zero all the fields */
1542         memset(&init_data, 0, sizeof(init_data));
1543         memset(&init_params, 0, sizeof(init_params));
1544
1545         mutex_init(&adev->dm.dpia_aux_lock);
1546         mutex_init(&adev->dm.dc_lock);
1547         mutex_init(&adev->dm.audio_lock);
1548
1549         if(amdgpu_dm_irq_init(adev)) {
1550                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1551                 goto error;
1552         }
1553
1554         init_data.asic_id.chip_family = adev->family;
1555
1556         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1557         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1558         init_data.asic_id.chip_id = adev->pdev->device;
1559
1560         init_data.asic_id.vram_width = adev->gmc.vram_width;
1561         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1562         init_data.asic_id.atombios_base_address =
1563                 adev->mode_info.atom_context->bios;
1564
1565         init_data.driver = adev;
1566
1567         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1568
1569         if (!adev->dm.cgs_device) {
1570                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1571                 goto error;
1572         }
1573
1574         init_data.cgs_device = adev->dm.cgs_device;
1575
1576         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1577
1578         switch (adev->ip_versions[DCE_HWIP][0]) {
1579         case IP_VERSION(2, 1, 0):
1580                 switch (adev->dm.dmcub_fw_version) {
1581                 case 0: /* development */
1582                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1583                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1584                         init_data.flags.disable_dmcu = false;
1585                         break;
1586                 default:
1587                         init_data.flags.disable_dmcu = true;
1588                 }
1589                 break;
1590         case IP_VERSION(2, 0, 3):
1591                 init_data.flags.disable_dmcu = true;
1592                 break;
1593         default:
1594                 break;
1595         }
1596
1597         switch (adev->asic_type) {
1598         case CHIP_CARRIZO:
1599         case CHIP_STONEY:
1600                 init_data.flags.gpu_vm_support = true;
1601                 break;
1602         default:
1603                 switch (adev->ip_versions[DCE_HWIP][0]) {
1604                 case IP_VERSION(1, 0, 0):
1605                 case IP_VERSION(1, 0, 1):
1606                         /* enable S/G on PCO and RV2 */
1607                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1608                             (adev->apu_flags & AMD_APU_IS_PICASSO))
1609                                 init_data.flags.gpu_vm_support = true;
1610                         break;
1611                 case IP_VERSION(2, 1, 0):
1612                 case IP_VERSION(3, 0, 1):
1613                 case IP_VERSION(3, 1, 2):
1614                 case IP_VERSION(3, 1, 3):
1615                 case IP_VERSION(3, 1, 4):
1616                 case IP_VERSION(3, 1, 5):
1617                 case IP_VERSION(3, 1, 6):
1618                         init_data.flags.gpu_vm_support = true;
1619                         break;
1620                 default:
1621                         break;
1622                 }
1623                 break;
1624         }
1625         if (init_data.flags.gpu_vm_support &&
1626             (amdgpu_sg_display == 0))
1627                 init_data.flags.gpu_vm_support = false;
1628
1629         if (init_data.flags.gpu_vm_support)
1630                 adev->mode_info.gpu_vm_support = true;
1631
1632         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1633                 init_data.flags.fbc_support = true;
1634
1635         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1636                 init_data.flags.multi_mon_pp_mclk_switch = true;
1637
1638         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1639                 init_data.flags.disable_fractional_pwm = true;
1640
1641         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1642                 init_data.flags.edp_no_power_sequencing = true;
1643
1644         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1645                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1646         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1647                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1648
1649         /* Disable SubVP + DRR config by default */
1650         init_data.flags.disable_subvp_drr = true;
1651         if (amdgpu_dc_feature_mask & DC_ENABLE_SUBVP_DRR)
1652                 init_data.flags.disable_subvp_drr = false;
1653
1654         init_data.flags.seamless_boot_edp_requested = false;
1655
1656         if (check_seamless_boot_capability(adev)) {
1657                 init_data.flags.seamless_boot_edp_requested = true;
1658                 init_data.flags.allow_seamless_boot_optimization = true;
1659                 DRM_INFO("Seamless boot condition check passed\n");
1660         }
1661
1662         init_data.flags.enable_mipi_converter_optimization = true;
1663
1664         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1665         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1666
1667         INIT_LIST_HEAD(&adev->dm.da_list);
1668
1669         retrieve_dmi_info(&adev->dm);
1670
1671         /* Display Core create. */
1672         adev->dm.dc = dc_create(&init_data);
1673
1674         if (adev->dm.dc) {
1675                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
1676         } else {
1677                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1678                 goto error;
1679         }
1680
1681         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1682                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1683                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1684         }
1685
1686         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1687                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1688         if (dm_should_disable_stutter(adev->pdev))
1689                 adev->dm.dc->debug.disable_stutter = true;
1690
1691         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1692                 adev->dm.dc->debug.disable_stutter = true;
1693
1694         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1695                 adev->dm.dc->debug.disable_dsc = true;
1696         }
1697
1698         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1699                 adev->dm.dc->debug.disable_clock_gate = true;
1700
1701         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1702                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1703
1704         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1705
1706         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1707         adev->dm.dc->debug.ignore_cable_id = true;
1708
1709         /* TODO: There is a new drm mst change where the freedom of
1710          * vc_next_start_slot update is revoked/moved into drm, instead of in
1711          * driver. This forces us to make sure to get vc_next_start_slot updated
1712          * in drm function each time without considering if mst_state is active
1713          * or not. Otherwise, next time hotplug will give wrong start_slot
1714          * number. We are implementing a temporary solution to even notify drm
1715          * mst deallocation when link is no longer of MST type when uncommitting
1716          * the stream so we will have more time to work on a proper solution.
1717          * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1718          * should notify drm to do a complete "reset" of its states and stop
1719          * calling further drm mst functions when link is no longer of an MST
1720          * type. This could happen when we unplug an MST hubs/displays. When
1721          * uncommit stream comes later after unplug, we should just reset
1722          * hardware states only.
1723          */
1724         adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1725
1726         if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1727                 DRM_INFO("DP-HDMI FRL PCON supported\n");
1728
1729         r = dm_dmub_hw_init(adev);
1730         if (r) {
1731                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1732                 goto error;
1733         }
1734
1735         dc_hardware_init(adev->dm.dc);
1736
1737         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1738         if (!adev->dm.hpd_rx_offload_wq) {
1739                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1740                 goto error;
1741         }
1742
1743         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1744                 struct dc_phy_addr_space_config pa_config;
1745
1746                 mmhub_read_system_context(adev, &pa_config);
1747
1748                 // Call the DC init_memory func
1749                 dc_setup_system_context(adev->dm.dc, &pa_config);
1750         }
1751
1752         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1753         if (!adev->dm.freesync_module) {
1754                 DRM_ERROR(
1755                 "amdgpu: failed to initialize freesync_module.\n");
1756         } else
1757                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1758                                 adev->dm.freesync_module);
1759
1760         amdgpu_dm_init_color_mod();
1761
1762         if (adev->dm.dc->caps.max_links > 0) {
1763                 adev->dm.vblank_control_workqueue =
1764                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1765                 if (!adev->dm.vblank_control_workqueue)
1766                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1767         }
1768
1769         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1770                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1771
1772                 if (!adev->dm.hdcp_workqueue)
1773                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1774                 else
1775                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1776
1777                 dc_init_callbacks(adev->dm.dc, &init_params);
1778         }
1779 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1780         adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1781         if (!adev->dm.secure_display_ctxs) {
1782                 DRM_ERROR("amdgpu: failed to initialize secure_display_ctxs.\n");
1783         }
1784 #endif
1785         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1786                 init_completion(&adev->dm.dmub_aux_transfer_done);
1787                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1788                 if (!adev->dm.dmub_notify) {
1789                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1790                         goto error;
1791                 }
1792
1793                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1794                 if (!adev->dm.delayed_hpd_wq) {
1795                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1796                         goto error;
1797                 }
1798
1799                 amdgpu_dm_outbox_init(adev);
1800                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1801                         dmub_aux_setconfig_callback, false)) {
1802                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1803                         goto error;
1804                 }
1805                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1806                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1807                         goto error;
1808                 }
1809                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1810                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1811                         goto error;
1812                 }
1813         }
1814
1815         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1816          * It is expected that DMUB will resend any pending notifications at this point, for
1817          * example HPD from DPIA.
1818          */
1819         if (dc_is_dmub_outbox_supported(adev->dm.dc))
1820                 dc_enable_dmub_outbox(adev->dm.dc);
1821
1822         if (amdgpu_dm_initialize_drm_device(adev)) {
1823                 DRM_ERROR(
1824                 "amdgpu: failed to initialize sw for display support.\n");
1825                 goto error;
1826         }
1827
1828         /* create fake encoders for MST */
1829         dm_dp_create_fake_mst_encoders(adev);
1830
1831         /* TODO: Add_display_info? */
1832
1833         /* TODO use dynamic cursor width */
1834         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1835         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1836
1837         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1838                 DRM_ERROR(
1839                 "amdgpu: failed to initialize sw for display support.\n");
1840                 goto error;
1841         }
1842
1843
1844         DRM_DEBUG_DRIVER("KMS initialized.\n");
1845
1846         return 0;
1847 error:
1848         amdgpu_dm_fini(adev);
1849
1850         return -EINVAL;
1851 }
1852
1853 static int amdgpu_dm_early_fini(void *handle)
1854 {
1855         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1856
1857         amdgpu_dm_audio_fini(adev);
1858
1859         return 0;
1860 }
1861
1862 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1863 {
1864         int i;
1865
1866         if (adev->dm.vblank_control_workqueue) {
1867                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1868                 adev->dm.vblank_control_workqueue = NULL;
1869         }
1870
1871         amdgpu_dm_destroy_drm_device(&adev->dm);
1872
1873 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1874         if (adev->dm.secure_display_ctxs) {
1875                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1876                         if (adev->dm.secure_display_ctxs[i].crtc) {
1877                                 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1878                                 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1879                         }
1880                 }
1881                 kfree(adev->dm.secure_display_ctxs);
1882                 adev->dm.secure_display_ctxs = NULL;
1883         }
1884 #endif
1885         if (adev->dm.hdcp_workqueue) {
1886                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1887                 adev->dm.hdcp_workqueue = NULL;
1888         }
1889
1890         if (adev->dm.dc)
1891                 dc_deinit_callbacks(adev->dm.dc);
1892
1893         if (adev->dm.dc)
1894                 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1895
1896         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1897                 kfree(adev->dm.dmub_notify);
1898                 adev->dm.dmub_notify = NULL;
1899                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1900                 adev->dm.delayed_hpd_wq = NULL;
1901         }
1902
1903         if (adev->dm.dmub_bo)
1904                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1905                                       &adev->dm.dmub_bo_gpu_addr,
1906                                       &adev->dm.dmub_bo_cpu_addr);
1907
1908         if (adev->dm.hpd_rx_offload_wq) {
1909                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1910                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1911                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1912                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1913                         }
1914                 }
1915
1916                 kfree(adev->dm.hpd_rx_offload_wq);
1917                 adev->dm.hpd_rx_offload_wq = NULL;
1918         }
1919
1920         /* DC Destroy TODO: Replace destroy DAL */
1921         if (adev->dm.dc)
1922                 dc_destroy(&adev->dm.dc);
1923         /*
1924          * TODO: pageflip, vlank interrupt
1925          *
1926          * amdgpu_dm_irq_fini(adev);
1927          */
1928
1929         if (adev->dm.cgs_device) {
1930                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1931                 adev->dm.cgs_device = NULL;
1932         }
1933         if (adev->dm.freesync_module) {
1934                 mod_freesync_destroy(adev->dm.freesync_module);
1935                 adev->dm.freesync_module = NULL;
1936         }
1937
1938         mutex_destroy(&adev->dm.audio_lock);
1939         mutex_destroy(&adev->dm.dc_lock);
1940         mutex_destroy(&adev->dm.dpia_aux_lock);
1941
1942         return;
1943 }
1944
1945 static int load_dmcu_fw(struct amdgpu_device *adev)
1946 {
1947         const char *fw_name_dmcu = NULL;
1948         int r;
1949         const struct dmcu_firmware_header_v1_0 *hdr;
1950
1951         switch(adev->asic_type) {
1952 #if defined(CONFIG_DRM_AMD_DC_SI)
1953         case CHIP_TAHITI:
1954         case CHIP_PITCAIRN:
1955         case CHIP_VERDE:
1956         case CHIP_OLAND:
1957 #endif
1958         case CHIP_BONAIRE:
1959         case CHIP_HAWAII:
1960         case CHIP_KAVERI:
1961         case CHIP_KABINI:
1962         case CHIP_MULLINS:
1963         case CHIP_TONGA:
1964         case CHIP_FIJI:
1965         case CHIP_CARRIZO:
1966         case CHIP_STONEY:
1967         case CHIP_POLARIS11:
1968         case CHIP_POLARIS10:
1969         case CHIP_POLARIS12:
1970         case CHIP_VEGAM:
1971         case CHIP_VEGA10:
1972         case CHIP_VEGA12:
1973         case CHIP_VEGA20:
1974                 return 0;
1975         case CHIP_NAVI12:
1976                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1977                 break;
1978         case CHIP_RAVEN:
1979                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1980                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1981                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1982                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1983                 else
1984                         return 0;
1985                 break;
1986         default:
1987                 switch (adev->ip_versions[DCE_HWIP][0]) {
1988                 case IP_VERSION(2, 0, 2):
1989                 case IP_VERSION(2, 0, 3):
1990                 case IP_VERSION(2, 0, 0):
1991                 case IP_VERSION(2, 1, 0):
1992                 case IP_VERSION(3, 0, 0):
1993                 case IP_VERSION(3, 0, 2):
1994                 case IP_VERSION(3, 0, 3):
1995                 case IP_VERSION(3, 0, 1):
1996                 case IP_VERSION(3, 1, 2):
1997                 case IP_VERSION(3, 1, 3):
1998                 case IP_VERSION(3, 1, 4):
1999                 case IP_VERSION(3, 1, 5):
2000                 case IP_VERSION(3, 1, 6):
2001                 case IP_VERSION(3, 2, 0):
2002                 case IP_VERSION(3, 2, 1):
2003                         return 0;
2004                 default:
2005                         break;
2006                 }
2007                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2008                 return -EINVAL;
2009         }
2010
2011         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2012                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2013                 return 0;
2014         }
2015
2016         r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2017         if (r == -ENODEV) {
2018                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2019                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2020                 adev->dm.fw_dmcu = NULL;
2021                 return 0;
2022         }
2023         if (r) {
2024                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2025                         fw_name_dmcu);
2026                 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2027                 return r;
2028         }
2029
2030         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2031         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2032         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2033         adev->firmware.fw_size +=
2034                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2035
2036         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2037         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2038         adev->firmware.fw_size +=
2039                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2040
2041         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2042
2043         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2044
2045         return 0;
2046 }
2047
2048 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2049 {
2050         struct amdgpu_device *adev = ctx;
2051
2052         return dm_read_reg(adev->dm.dc->ctx, address);
2053 }
2054
2055 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2056                                      uint32_t value)
2057 {
2058         struct amdgpu_device *adev = ctx;
2059
2060         return dm_write_reg(adev->dm.dc->ctx, address, value);
2061 }
2062
2063 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2064 {
2065         struct dmub_srv_create_params create_params;
2066         struct dmub_srv_region_params region_params;
2067         struct dmub_srv_region_info region_info;
2068         struct dmub_srv_fb_params fb_params;
2069         struct dmub_srv_fb_info *fb_info;
2070         struct dmub_srv *dmub_srv;
2071         const struct dmcub_firmware_header_v1_0 *hdr;
2072         enum dmub_asic dmub_asic;
2073         enum dmub_status status;
2074         int r;
2075
2076         switch (adev->ip_versions[DCE_HWIP][0]) {
2077         case IP_VERSION(2, 1, 0):
2078                 dmub_asic = DMUB_ASIC_DCN21;
2079                 break;
2080         case IP_VERSION(3, 0, 0):
2081                 dmub_asic = DMUB_ASIC_DCN30;
2082                 break;
2083         case IP_VERSION(3, 0, 1):
2084                 dmub_asic = DMUB_ASIC_DCN301;
2085                 break;
2086         case IP_VERSION(3, 0, 2):
2087                 dmub_asic = DMUB_ASIC_DCN302;
2088                 break;
2089         case IP_VERSION(3, 0, 3):
2090                 dmub_asic = DMUB_ASIC_DCN303;
2091                 break;
2092         case IP_VERSION(3, 1, 2):
2093         case IP_VERSION(3, 1, 3):
2094                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2095                 break;
2096         case IP_VERSION(3, 1, 4):
2097                 dmub_asic = DMUB_ASIC_DCN314;
2098                 break;
2099         case IP_VERSION(3, 1, 5):
2100                 dmub_asic = DMUB_ASIC_DCN315;
2101                 break;
2102         case IP_VERSION(3, 1, 6):
2103                 dmub_asic = DMUB_ASIC_DCN316;
2104                 break;
2105         case IP_VERSION(3, 2, 0):
2106                 dmub_asic = DMUB_ASIC_DCN32;
2107                 break;
2108         case IP_VERSION(3, 2, 1):
2109                 dmub_asic = DMUB_ASIC_DCN321;
2110                 break;
2111         default:
2112                 /* ASIC doesn't support DMUB. */
2113                 return 0;
2114         }
2115
2116         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2117         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2118
2119         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2120                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2121                         AMDGPU_UCODE_ID_DMCUB;
2122                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2123                         adev->dm.dmub_fw;
2124                 adev->firmware.fw_size +=
2125                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2126
2127                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2128                          adev->dm.dmcub_fw_version);
2129         }
2130
2131
2132         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2133         dmub_srv = adev->dm.dmub_srv;
2134
2135         if (!dmub_srv) {
2136                 DRM_ERROR("Failed to allocate DMUB service!\n");
2137                 return -ENOMEM;
2138         }
2139
2140         memset(&create_params, 0, sizeof(create_params));
2141         create_params.user_ctx = adev;
2142         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2143         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2144         create_params.asic = dmub_asic;
2145
2146         /* Create the DMUB service. */
2147         status = dmub_srv_create(dmub_srv, &create_params);
2148         if (status != DMUB_STATUS_OK) {
2149                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2150                 return -EINVAL;
2151         }
2152
2153         /* Calculate the size of all the regions for the DMUB service. */
2154         memset(&region_params, 0, sizeof(region_params));
2155
2156         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2157                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2158         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2159         region_params.vbios_size = adev->bios_size;
2160         region_params.fw_bss_data = region_params.bss_data_size ?
2161                 adev->dm.dmub_fw->data +
2162                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2163                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2164         region_params.fw_inst_const =
2165                 adev->dm.dmub_fw->data +
2166                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2167                 PSP_HEADER_BYTES;
2168
2169         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2170                                            &region_info);
2171
2172         if (status != DMUB_STATUS_OK) {
2173                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2174                 return -EINVAL;
2175         }
2176
2177         /*
2178          * Allocate a framebuffer based on the total size of all the regions.
2179          * TODO: Move this into GART.
2180          */
2181         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2182                                     AMDGPU_GEM_DOMAIN_VRAM |
2183                                     AMDGPU_GEM_DOMAIN_GTT,
2184                                     &adev->dm.dmub_bo,
2185                                     &adev->dm.dmub_bo_gpu_addr,
2186                                     &adev->dm.dmub_bo_cpu_addr);
2187         if (r)
2188                 return r;
2189
2190         /* Rebase the regions on the framebuffer address. */
2191         memset(&fb_params, 0, sizeof(fb_params));
2192         fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2193         fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2194         fb_params.region_info = &region_info;
2195
2196         adev->dm.dmub_fb_info =
2197                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2198         fb_info = adev->dm.dmub_fb_info;
2199
2200         if (!fb_info) {
2201                 DRM_ERROR(
2202                         "Failed to allocate framebuffer info for DMUB service!\n");
2203                 return -ENOMEM;
2204         }
2205
2206         status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2207         if (status != DMUB_STATUS_OK) {
2208                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2209                 return -EINVAL;
2210         }
2211
2212         return 0;
2213 }
2214
2215 static int dm_sw_init(void *handle)
2216 {
2217         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2218         int r;
2219
2220         r = dm_dmub_sw_init(adev);
2221         if (r)
2222                 return r;
2223
2224         return load_dmcu_fw(adev);
2225 }
2226
2227 static int dm_sw_fini(void *handle)
2228 {
2229         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2230
2231         kfree(adev->dm.dmub_fb_info);
2232         adev->dm.dmub_fb_info = NULL;
2233
2234         if (adev->dm.dmub_srv) {
2235                 dmub_srv_destroy(adev->dm.dmub_srv);
2236                 adev->dm.dmub_srv = NULL;
2237         }
2238
2239         amdgpu_ucode_release(&adev->dm.dmub_fw);
2240         amdgpu_ucode_release(&adev->dm.fw_dmcu);
2241
2242         return 0;
2243 }
2244
2245 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2246 {
2247         struct amdgpu_dm_connector *aconnector;
2248         struct drm_connector *connector;
2249         struct drm_connector_list_iter iter;
2250         int ret = 0;
2251
2252         drm_connector_list_iter_begin(dev, &iter);
2253         drm_for_each_connector_iter(connector, &iter) {
2254                 aconnector = to_amdgpu_dm_connector(connector);
2255                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2256                     aconnector->mst_mgr.aux) {
2257                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2258                                          aconnector,
2259                                          aconnector->base.base.id);
2260
2261                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2262                         if (ret < 0) {
2263                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2264                                 aconnector->dc_link->type =
2265                                         dc_connection_single;
2266                                 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2267                                                                      aconnector->dc_link);
2268                                 break;
2269                         }
2270                 }
2271         }
2272         drm_connector_list_iter_end(&iter);
2273
2274         return ret;
2275 }
2276
2277 static int dm_late_init(void *handle)
2278 {
2279         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2280
2281         struct dmcu_iram_parameters params;
2282         unsigned int linear_lut[16];
2283         int i;
2284         struct dmcu *dmcu = NULL;
2285
2286         dmcu = adev->dm.dc->res_pool->dmcu;
2287
2288         for (i = 0; i < 16; i++)
2289                 linear_lut[i] = 0xFFFF * i / 15;
2290
2291         params.set = 0;
2292         params.backlight_ramping_override = false;
2293         params.backlight_ramping_start = 0xCCCC;
2294         params.backlight_ramping_reduction = 0xCCCCCCCC;
2295         params.backlight_lut_array_size = 16;
2296         params.backlight_lut_array = linear_lut;
2297
2298         /* Min backlight level after ABM reduction,  Don't allow below 1%
2299          * 0xFFFF x 0.01 = 0x28F
2300          */
2301         params.min_abm_backlight = 0x28F;
2302         /* In the case where abm is implemented on dmcub,
2303          * dmcu object will be null.
2304          * ABM 2.4 and up are implemented on dmcub.
2305          */
2306         if (dmcu) {
2307                 if (!dmcu_load_iram(dmcu, params))
2308                         return -EINVAL;
2309         } else if (adev->dm.dc->ctx->dmub_srv) {
2310                 struct dc_link *edp_links[MAX_NUM_EDP];
2311                 int edp_num;
2312
2313                 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2314                 for (i = 0; i < edp_num; i++) {
2315                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2316                                 return -EINVAL;
2317                 }
2318         }
2319
2320         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2321 }
2322
2323 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2324 {
2325         struct amdgpu_dm_connector *aconnector;
2326         struct drm_connector *connector;
2327         struct drm_connector_list_iter iter;
2328         struct drm_dp_mst_topology_mgr *mgr;
2329         int ret;
2330         bool need_hotplug = false;
2331
2332         drm_connector_list_iter_begin(dev, &iter);
2333         drm_for_each_connector_iter(connector, &iter) {
2334                 aconnector = to_amdgpu_dm_connector(connector);
2335                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2336                     aconnector->mst_root)
2337                         continue;
2338
2339                 mgr = &aconnector->mst_mgr;
2340
2341                 if (suspend) {
2342                         drm_dp_mst_topology_mgr_suspend(mgr);
2343                 } else {
2344                         /* if extended timeout is supported in hardware,
2345                          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2346                          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2347                          */
2348                         try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2349                         if (!dp_is_lttpr_present(aconnector->dc_link))
2350                                 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2351
2352                         ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2353                         if (ret < 0) {
2354                                 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2355                                         aconnector->dc_link);
2356                                 need_hotplug = true;
2357                         }
2358                 }
2359         }
2360         drm_connector_list_iter_end(&iter);
2361
2362         if (need_hotplug)
2363                 drm_kms_helper_hotplug_event(dev);
2364 }
2365
2366 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2367 {
2368         int ret = 0;
2369
2370         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2371          * on window driver dc implementation.
2372          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2373          * should be passed to smu during boot up and resume from s3.
2374          * boot up: dc calculate dcn watermark clock settings within dc_create,
2375          * dcn20_resource_construct
2376          * then call pplib functions below to pass the settings to smu:
2377          * smu_set_watermarks_for_clock_ranges
2378          * smu_set_watermarks_table
2379          * navi10_set_watermarks_table
2380          * smu_write_watermarks_table
2381          *
2382          * For Renoir, clock settings of dcn watermark are also fixed values.
2383          * dc has implemented different flow for window driver:
2384          * dc_hardware_init / dc_set_power_state
2385          * dcn10_init_hw
2386          * notify_wm_ranges
2387          * set_wm_ranges
2388          * -- Linux
2389          * smu_set_watermarks_for_clock_ranges
2390          * renoir_set_watermarks_table
2391          * smu_write_watermarks_table
2392          *
2393          * For Linux,
2394          * dc_hardware_init -> amdgpu_dm_init
2395          * dc_set_power_state --> dm_resume
2396          *
2397          * therefore, this function apply to navi10/12/14 but not Renoir
2398          * *
2399          */
2400         switch (adev->ip_versions[DCE_HWIP][0]) {
2401         case IP_VERSION(2, 0, 2):
2402         case IP_VERSION(2, 0, 0):
2403                 break;
2404         default:
2405                 return 0;
2406         }
2407
2408         ret = amdgpu_dpm_write_watermarks_table(adev);
2409         if (ret) {
2410                 DRM_ERROR("Failed to update WMTABLE!\n");
2411                 return ret;
2412         }
2413
2414         return 0;
2415 }
2416
2417 /**
2418  * dm_hw_init() - Initialize DC device
2419  * @handle: The base driver device containing the amdgpu_dm device.
2420  *
2421  * Initialize the &struct amdgpu_display_manager device. This involves calling
2422  * the initializers of each DM component, then populating the struct with them.
2423  *
2424  * Although the function implies hardware initialization, both hardware and
2425  * software are initialized here. Splitting them out to their relevant init
2426  * hooks is a future TODO item.
2427  *
2428  * Some notable things that are initialized here:
2429  *
2430  * - Display Core, both software and hardware
2431  * - DC modules that we need (freesync and color management)
2432  * - DRM software states
2433  * - Interrupt sources and handlers
2434  * - Vblank support
2435  * - Debug FS entries, if enabled
2436  */
2437 static int dm_hw_init(void *handle)
2438 {
2439         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2440         /* Create DAL display manager */
2441         amdgpu_dm_init(adev);
2442         amdgpu_dm_hpd_init(adev);
2443
2444         return 0;
2445 }
2446
2447 /**
2448  * dm_hw_fini() - Teardown DC device
2449  * @handle: The base driver device containing the amdgpu_dm device.
2450  *
2451  * Teardown components within &struct amdgpu_display_manager that require
2452  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2453  * were loaded. Also flush IRQ workqueues and disable them.
2454  */
2455 static int dm_hw_fini(void *handle)
2456 {
2457         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2458
2459         amdgpu_dm_hpd_fini(adev);
2460
2461         amdgpu_dm_irq_fini(adev);
2462         amdgpu_dm_fini(adev);
2463         return 0;
2464 }
2465
2466
2467 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2468                                  struct dc_state *state, bool enable)
2469 {
2470         enum dc_irq_source irq_source;
2471         struct amdgpu_crtc *acrtc;
2472         int rc = -EBUSY;
2473         int i = 0;
2474
2475         for (i = 0; i < state->stream_count; i++) {
2476                 acrtc = get_crtc_by_otg_inst(
2477                                 adev, state->stream_status[i].primary_otg_inst);
2478
2479                 if (acrtc && state->stream_status[i].plane_count != 0) {
2480                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2481                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2482                         DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
2483                                       acrtc->crtc_id, enable ? "en" : "dis", rc);
2484                         if (rc)
2485                                 DRM_WARN("Failed to %s pflip interrupts\n",
2486                                          enable ? "enable" : "disable");
2487
2488                         if (enable) {
2489                                 rc = amdgpu_dm_crtc_enable_vblank(&acrtc->base);
2490                                 if (rc)
2491                                         DRM_WARN("Failed to enable vblank interrupts\n");
2492                         } else {
2493                                 amdgpu_dm_crtc_disable_vblank(&acrtc->base);
2494                         }
2495
2496                 }
2497         }
2498
2499 }
2500
2501 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2502 {
2503         struct dc_state *context = NULL;
2504         enum dc_status res = DC_ERROR_UNEXPECTED;
2505         int i;
2506         struct dc_stream_state *del_streams[MAX_PIPES];
2507         int del_streams_count = 0;
2508
2509         memset(del_streams, 0, sizeof(del_streams));
2510
2511         context = dc_create_state(dc);
2512         if (context == NULL)
2513                 goto context_alloc_fail;
2514
2515         dc_resource_state_copy_construct_current(dc, context);
2516
2517         /* First remove from context all streams */
2518         for (i = 0; i < context->stream_count; i++) {
2519                 struct dc_stream_state *stream = context->streams[i];
2520
2521                 del_streams[del_streams_count++] = stream;
2522         }
2523
2524         /* Remove all planes for removed streams and then remove the streams */
2525         for (i = 0; i < del_streams_count; i++) {
2526                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2527                         res = DC_FAIL_DETACH_SURFACES;
2528                         goto fail;
2529                 }
2530
2531                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2532                 if (res != DC_OK)
2533                         goto fail;
2534         }
2535
2536         res = dc_commit_streams(dc, context->streams, context->stream_count);
2537
2538 fail:
2539         dc_release_state(context);
2540
2541 context_alloc_fail:
2542         return res;
2543 }
2544
2545 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2546 {
2547         int i;
2548
2549         if (dm->hpd_rx_offload_wq) {
2550                 for (i = 0; i < dm->dc->caps.max_links; i++)
2551                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2552         }
2553 }
2554
2555 static int dm_suspend(void *handle)
2556 {
2557         struct amdgpu_device *adev = handle;
2558         struct amdgpu_display_manager *dm = &adev->dm;
2559         int ret = 0;
2560
2561         if (amdgpu_in_reset(adev)) {
2562                 mutex_lock(&dm->dc_lock);
2563
2564                 dc_allow_idle_optimizations(adev->dm.dc, false);
2565
2566                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2567
2568                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2569
2570                 amdgpu_dm_commit_zero_streams(dm->dc);
2571
2572                 amdgpu_dm_irq_suspend(adev);
2573
2574                 hpd_rx_irq_work_suspend(dm);
2575
2576                 return ret;
2577         }
2578
2579         WARN_ON(adev->dm.cached_state);
2580         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2581
2582         s3_handle_mst(adev_to_drm(adev), true);
2583
2584         amdgpu_dm_irq_suspend(adev);
2585
2586         hpd_rx_irq_work_suspend(dm);
2587
2588         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2589
2590         return 0;
2591 }
2592
2593 struct amdgpu_dm_connector *
2594 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2595                                              struct drm_crtc *crtc)
2596 {
2597         u32 i;
2598         struct drm_connector_state *new_con_state;
2599         struct drm_connector *connector;
2600         struct drm_crtc *crtc_from_state;
2601
2602         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2603                 crtc_from_state = new_con_state->crtc;
2604
2605                 if (crtc_from_state == crtc)
2606                         return to_amdgpu_dm_connector(connector);
2607         }
2608
2609         return NULL;
2610 }
2611
2612 static void emulated_link_detect(struct dc_link *link)
2613 {
2614         struct dc_sink_init_data sink_init_data = { 0 };
2615         struct display_sink_capability sink_caps = { 0 };
2616         enum dc_edid_status edid_status;
2617         struct dc_context *dc_ctx = link->ctx;
2618         struct dc_sink *sink = NULL;
2619         struct dc_sink *prev_sink = NULL;
2620
2621         link->type = dc_connection_none;
2622         prev_sink = link->local_sink;
2623
2624         if (prev_sink)
2625                 dc_sink_release(prev_sink);
2626
2627         switch (link->connector_signal) {
2628         case SIGNAL_TYPE_HDMI_TYPE_A: {
2629                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2630                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2631                 break;
2632         }
2633
2634         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2635                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2636                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2637                 break;
2638         }
2639
2640         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2641                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2642                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2643                 break;
2644         }
2645
2646         case SIGNAL_TYPE_LVDS: {
2647                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2648                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2649                 break;
2650         }
2651
2652         case SIGNAL_TYPE_EDP: {
2653                 sink_caps.transaction_type =
2654                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2655                 sink_caps.signal = SIGNAL_TYPE_EDP;
2656                 break;
2657         }
2658
2659         case SIGNAL_TYPE_DISPLAY_PORT: {
2660                 sink_caps.transaction_type =
2661                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2662                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2663                 break;
2664         }
2665
2666         default:
2667                 DC_ERROR("Invalid connector type! signal:%d\n",
2668                         link->connector_signal);
2669                 return;
2670         }
2671
2672         sink_init_data.link = link;
2673         sink_init_data.sink_signal = sink_caps.signal;
2674
2675         sink = dc_sink_create(&sink_init_data);
2676         if (!sink) {
2677                 DC_ERROR("Failed to create sink!\n");
2678                 return;
2679         }
2680
2681         /* dc_sink_create returns a new reference */
2682         link->local_sink = sink;
2683
2684         edid_status = dm_helpers_read_local_edid(
2685                         link->ctx,
2686                         link,
2687                         sink);
2688
2689         if (edid_status != EDID_OK)
2690                 DC_ERROR("Failed to read EDID");
2691
2692 }
2693
2694 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2695                                      struct amdgpu_display_manager *dm)
2696 {
2697         struct {
2698                 struct dc_surface_update surface_updates[MAX_SURFACES];
2699                 struct dc_plane_info plane_infos[MAX_SURFACES];
2700                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2701                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2702                 struct dc_stream_update stream_update;
2703         } * bundle;
2704         int k, m;
2705
2706         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2707
2708         if (!bundle) {
2709                 dm_error("Failed to allocate update bundle\n");
2710                 goto cleanup;
2711         }
2712
2713         for (k = 0; k < dc_state->stream_count; k++) {
2714                 bundle->stream_update.stream = dc_state->streams[k];
2715
2716                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2717                         bundle->surface_updates[m].surface =
2718                                 dc_state->stream_status->plane_states[m];
2719                         bundle->surface_updates[m].surface->force_full_update =
2720                                 true;
2721                 }
2722
2723                 update_planes_and_stream_adapter(dm->dc,
2724                                          UPDATE_TYPE_FULL,
2725                                          dc_state->stream_status->plane_count,
2726                                          dc_state->streams[k],
2727                                          &bundle->stream_update,
2728                                          bundle->surface_updates);
2729         }
2730
2731 cleanup:
2732         kfree(bundle);
2733
2734         return;
2735 }
2736
2737 static int dm_resume(void *handle)
2738 {
2739         struct amdgpu_device *adev = handle;
2740         struct drm_device *ddev = adev_to_drm(adev);
2741         struct amdgpu_display_manager *dm = &adev->dm;
2742         struct amdgpu_dm_connector *aconnector;
2743         struct drm_connector *connector;
2744         struct drm_connector_list_iter iter;
2745         struct drm_crtc *crtc;
2746         struct drm_crtc_state *new_crtc_state;
2747         struct dm_crtc_state *dm_new_crtc_state;
2748         struct drm_plane *plane;
2749         struct drm_plane_state *new_plane_state;
2750         struct dm_plane_state *dm_new_plane_state;
2751         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2752         enum dc_connection_type new_connection_type = dc_connection_none;
2753         struct dc_state *dc_state;
2754         int i, r, j;
2755
2756         if (amdgpu_in_reset(adev)) {
2757                 dc_state = dm->cached_dc_state;
2758
2759                 /*
2760                  * The dc->current_state is backed up into dm->cached_dc_state
2761                  * before we commit 0 streams.
2762                  *
2763                  * DC will clear link encoder assignments on the real state
2764                  * but the changes won't propagate over to the copy we made
2765                  * before the 0 streams commit.
2766                  *
2767                  * DC expects that link encoder assignments are *not* valid
2768                  * when committing a state, so as a workaround we can copy
2769                  * off of the current state.
2770                  *
2771                  * We lose the previous assignments, but we had already
2772                  * commit 0 streams anyway.
2773                  */
2774                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2775
2776                 r = dm_dmub_hw_init(adev);
2777                 if (r)
2778                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2779
2780                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2781                 dc_resume(dm->dc);
2782
2783                 amdgpu_dm_irq_resume_early(adev);
2784
2785                 for (i = 0; i < dc_state->stream_count; i++) {
2786                         dc_state->streams[i]->mode_changed = true;
2787                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2788                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2789                                         = 0xffffffff;
2790                         }
2791                 }
2792
2793                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2794                         amdgpu_dm_outbox_init(adev);
2795                         dc_enable_dmub_outbox(adev->dm.dc);
2796                 }
2797
2798                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2799
2800                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2801
2802                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2803
2804                 dc_release_state(dm->cached_dc_state);
2805                 dm->cached_dc_state = NULL;
2806
2807                 amdgpu_dm_irq_resume_late(adev);
2808
2809                 mutex_unlock(&dm->dc_lock);
2810
2811                 return 0;
2812         }
2813         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2814         dc_release_state(dm_state->context);
2815         dm_state->context = dc_create_state(dm->dc);
2816         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2817         dc_resource_state_construct(dm->dc, dm_state->context);
2818
2819         /* Before powering on DC we need to re-initialize DMUB. */
2820         dm_dmub_hw_resume(adev);
2821
2822         /* Re-enable outbox interrupts for DPIA. */
2823         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2824                 amdgpu_dm_outbox_init(adev);
2825                 dc_enable_dmub_outbox(adev->dm.dc);
2826         }
2827
2828         /* power on hardware */
2829         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2830
2831         /* program HPD filter */
2832         dc_resume(dm->dc);
2833
2834         /*
2835          * early enable HPD Rx IRQ, should be done before set mode as short
2836          * pulse interrupts are used for MST
2837          */
2838         amdgpu_dm_irq_resume_early(adev);
2839
2840         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2841         s3_handle_mst(ddev, false);
2842
2843         /* Do detection*/
2844         drm_connector_list_iter_begin(ddev, &iter);
2845         drm_for_each_connector_iter(connector, &iter) {
2846                 aconnector = to_amdgpu_dm_connector(connector);
2847
2848                 if (!aconnector->dc_link)
2849                         continue;
2850
2851                 /*
2852                  * this is the case when traversing through already created
2853                  * MST connectors, should be skipped
2854                  */
2855                 if (aconnector->dc_link->type == dc_connection_mst_branch)
2856                         continue;
2857
2858                 mutex_lock(&aconnector->hpd_lock);
2859                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2860                         DRM_ERROR("KMS: Failed to detect connector\n");
2861
2862                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2863                         emulated_link_detect(aconnector->dc_link);
2864                 } else {
2865                         mutex_lock(&dm->dc_lock);
2866                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2867                         mutex_unlock(&dm->dc_lock);
2868                 }
2869
2870                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2871                         aconnector->fake_enable = false;
2872
2873                 if (aconnector->dc_sink)
2874                         dc_sink_release(aconnector->dc_sink);
2875                 aconnector->dc_sink = NULL;
2876                 amdgpu_dm_update_connector_after_detect(aconnector);
2877                 mutex_unlock(&aconnector->hpd_lock);
2878         }
2879         drm_connector_list_iter_end(&iter);
2880
2881         /* Force mode set in atomic commit */
2882         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2883                 new_crtc_state->active_changed = true;
2884
2885         /*
2886          * atomic_check is expected to create the dc states. We need to release
2887          * them here, since they were duplicated as part of the suspend
2888          * procedure.
2889          */
2890         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2891                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2892                 if (dm_new_crtc_state->stream) {
2893                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2894                         dc_stream_release(dm_new_crtc_state->stream);
2895                         dm_new_crtc_state->stream = NULL;
2896                 }
2897         }
2898
2899         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2900                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2901                 if (dm_new_plane_state->dc_state) {
2902                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2903                         dc_plane_state_release(dm_new_plane_state->dc_state);
2904                         dm_new_plane_state->dc_state = NULL;
2905                 }
2906         }
2907
2908         drm_atomic_helper_resume(ddev, dm->cached_state);
2909
2910         dm->cached_state = NULL;
2911
2912         amdgpu_dm_irq_resume_late(adev);
2913
2914         amdgpu_dm_smu_write_watermarks_table(adev);
2915
2916         return 0;
2917 }
2918
2919 /**
2920  * DOC: DM Lifecycle
2921  *
2922  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2923  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2924  * the base driver's device list to be initialized and torn down accordingly.
2925  *
2926  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2927  */
2928
2929 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2930         .name = "dm",
2931         .early_init = dm_early_init,
2932         .late_init = dm_late_init,
2933         .sw_init = dm_sw_init,
2934         .sw_fini = dm_sw_fini,
2935         .early_fini = amdgpu_dm_early_fini,
2936         .hw_init = dm_hw_init,
2937         .hw_fini = dm_hw_fini,
2938         .suspend = dm_suspend,
2939         .resume = dm_resume,
2940         .is_idle = dm_is_idle,
2941         .wait_for_idle = dm_wait_for_idle,
2942         .check_soft_reset = dm_check_soft_reset,
2943         .soft_reset = dm_soft_reset,
2944         .set_clockgating_state = dm_set_clockgating_state,
2945         .set_powergating_state = dm_set_powergating_state,
2946 };
2947
2948 const struct amdgpu_ip_block_version dm_ip_block =
2949 {
2950         .type = AMD_IP_BLOCK_TYPE_DCE,
2951         .major = 1,
2952         .minor = 0,
2953         .rev = 0,
2954         .funcs = &amdgpu_dm_funcs,
2955 };
2956
2957
2958 /**
2959  * DOC: atomic
2960  *
2961  * *WIP*
2962  */
2963
2964 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2965         .fb_create = amdgpu_display_user_framebuffer_create,
2966         .get_format_info = amdgpu_dm_plane_get_format_info,
2967         .atomic_check = amdgpu_dm_atomic_check,
2968         .atomic_commit = drm_atomic_helper_commit,
2969 };
2970
2971 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2972         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2973         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2974 };
2975
2976 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2977 {
2978         struct amdgpu_dm_backlight_caps *caps;
2979         struct drm_connector *conn_base;
2980         struct amdgpu_device *adev;
2981         struct drm_luminance_range_info *luminance_range;
2982
2983         if (aconnector->bl_idx == -1 ||
2984             aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
2985                 return;
2986
2987         conn_base = &aconnector->base;
2988         adev = drm_to_adev(conn_base->dev);
2989
2990         caps = &adev->dm.backlight_caps[aconnector->bl_idx];
2991         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2992         caps->aux_support = false;
2993
2994         if (caps->ext_caps->bits.oled == 1 /*||
2995             caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
2996             caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
2997                 caps->aux_support = true;
2998
2999         if (amdgpu_backlight == 0)
3000                 caps->aux_support = false;
3001         else if (amdgpu_backlight == 1)
3002                 caps->aux_support = true;
3003
3004         luminance_range = &conn_base->display_info.luminance_range;
3005
3006         if (luminance_range->max_luminance) {
3007                 caps->aux_min_input_signal = luminance_range->min_luminance;
3008                 caps->aux_max_input_signal = luminance_range->max_luminance;
3009         } else {
3010                 caps->aux_min_input_signal = 0;
3011                 caps->aux_max_input_signal = 512;
3012         }
3013 }
3014
3015 void amdgpu_dm_update_connector_after_detect(
3016                 struct amdgpu_dm_connector *aconnector)
3017 {
3018         struct drm_connector *connector = &aconnector->base;
3019         struct drm_device *dev = connector->dev;
3020         struct dc_sink *sink;
3021
3022         /* MST handled by drm_mst framework */
3023         if (aconnector->mst_mgr.mst_state == true)
3024                 return;
3025
3026         sink = aconnector->dc_link->local_sink;
3027         if (sink)
3028                 dc_sink_retain(sink);
3029
3030         /*
3031          * Edid mgmt connector gets first update only in mode_valid hook and then
3032          * the connector sink is set to either fake or physical sink depends on link status.
3033          * Skip if already done during boot.
3034          */
3035         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3036                         && aconnector->dc_em_sink) {
3037
3038                 /*
3039                  * For S3 resume with headless use eml_sink to fake stream
3040                  * because on resume connector->sink is set to NULL
3041                  */
3042                 mutex_lock(&dev->mode_config.mutex);
3043
3044                 if (sink) {
3045                         if (aconnector->dc_sink) {
3046                                 amdgpu_dm_update_freesync_caps(connector, NULL);
3047                                 /*
3048                                  * retain and release below are used to
3049                                  * bump up refcount for sink because the link doesn't point
3050                                  * to it anymore after disconnect, so on next crtc to connector
3051                                  * reshuffle by UMD we will get into unwanted dc_sink release
3052                                  */
3053                                 dc_sink_release(aconnector->dc_sink);
3054                         }
3055                         aconnector->dc_sink = sink;
3056                         dc_sink_retain(aconnector->dc_sink);
3057                         amdgpu_dm_update_freesync_caps(connector,
3058                                         aconnector->edid);
3059                 } else {
3060                         amdgpu_dm_update_freesync_caps(connector, NULL);
3061                         if (!aconnector->dc_sink) {
3062                                 aconnector->dc_sink = aconnector->dc_em_sink;
3063                                 dc_sink_retain(aconnector->dc_sink);
3064                         }
3065                 }
3066
3067                 mutex_unlock(&dev->mode_config.mutex);
3068
3069                 if (sink)
3070                         dc_sink_release(sink);
3071                 return;
3072         }
3073
3074         /*
3075          * TODO: temporary guard to look for proper fix
3076          * if this sink is MST sink, we should not do anything
3077          */
3078         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3079                 dc_sink_release(sink);
3080                 return;
3081         }
3082
3083         if (aconnector->dc_sink == sink) {
3084                 /*
3085                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
3086                  * Do nothing!!
3087                  */
3088                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3089                                 aconnector->connector_id);
3090                 if (sink)
3091                         dc_sink_release(sink);
3092                 return;
3093         }
3094
3095         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3096                 aconnector->connector_id, aconnector->dc_sink, sink);
3097
3098         mutex_lock(&dev->mode_config.mutex);
3099
3100         /*
3101          * 1. Update status of the drm connector
3102          * 2. Send an event and let userspace tell us what to do
3103          */
3104         if (sink) {
3105                 /*
3106                  * TODO: check if we still need the S3 mode update workaround.
3107                  * If yes, put it here.
3108                  */
3109                 if (aconnector->dc_sink) {
3110                         amdgpu_dm_update_freesync_caps(connector, NULL);
3111                         dc_sink_release(aconnector->dc_sink);
3112                 }
3113
3114                 aconnector->dc_sink = sink;
3115                 dc_sink_retain(aconnector->dc_sink);
3116                 if (sink->dc_edid.length == 0) {
3117                         aconnector->edid = NULL;
3118                         if (aconnector->dc_link->aux_mode) {
3119                                 drm_dp_cec_unset_edid(
3120                                         &aconnector->dm_dp_aux.aux);
3121                         }
3122                 } else {
3123                         aconnector->edid =
3124                                 (struct edid *)sink->dc_edid.raw_edid;
3125
3126                         if (aconnector->dc_link->aux_mode)
3127                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3128                                                     aconnector->edid);
3129                 }
3130
3131                 if (!aconnector->timing_requested) {
3132                         aconnector->timing_requested =
3133                                 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3134                         if (!aconnector->timing_requested)
3135                                 dm_error("failed to create aconnector->requested_timing\n");
3136                 }
3137
3138                 drm_connector_update_edid_property(connector, aconnector->edid);
3139                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3140                 update_connector_ext_caps(aconnector);
3141         } else {
3142                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3143                 amdgpu_dm_update_freesync_caps(connector, NULL);
3144                 drm_connector_update_edid_property(connector, NULL);
3145                 aconnector->num_modes = 0;
3146                 dc_sink_release(aconnector->dc_sink);
3147                 aconnector->dc_sink = NULL;
3148                 aconnector->edid = NULL;
3149                 kfree(aconnector->timing_requested);
3150                 aconnector->timing_requested = NULL;
3151                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3152                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3153                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3154         }
3155
3156         mutex_unlock(&dev->mode_config.mutex);
3157
3158         update_subconnector_property(aconnector);
3159
3160         if (sink)
3161                 dc_sink_release(sink);
3162 }
3163
3164 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3165 {
3166         struct drm_connector *connector = &aconnector->base;
3167         struct drm_device *dev = connector->dev;
3168         enum dc_connection_type new_connection_type = dc_connection_none;
3169         struct amdgpu_device *adev = drm_to_adev(dev);
3170         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3171         bool ret = false;
3172
3173         if (adev->dm.disable_hpd_irq)
3174                 return;
3175
3176         /*
3177          * In case of failure or MST no need to update connector status or notify the OS
3178          * since (for MST case) MST does this in its own context.
3179          */
3180         mutex_lock(&aconnector->hpd_lock);
3181
3182         if (adev->dm.hdcp_workqueue) {
3183                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3184                 dm_con_state->update_hdcp = true;
3185         }
3186         if (aconnector->fake_enable)
3187                 aconnector->fake_enable = false;
3188
3189         aconnector->timing_changed = false;
3190
3191         if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3192                 DRM_ERROR("KMS: Failed to detect connector\n");
3193
3194         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3195                 emulated_link_detect(aconnector->dc_link);
3196
3197                 drm_modeset_lock_all(dev);
3198                 dm_restore_drm_connector_state(dev, connector);
3199                 drm_modeset_unlock_all(dev);
3200
3201                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3202                         drm_kms_helper_connector_hotplug_event(connector);
3203         } else {
3204                 mutex_lock(&adev->dm.dc_lock);
3205                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3206                 mutex_unlock(&adev->dm.dc_lock);
3207                 if (ret) {
3208                         amdgpu_dm_update_connector_after_detect(aconnector);
3209
3210                         drm_modeset_lock_all(dev);
3211                         dm_restore_drm_connector_state(dev, connector);
3212                         drm_modeset_unlock_all(dev);
3213
3214                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3215                                 drm_kms_helper_connector_hotplug_event(connector);
3216                 }
3217         }
3218         mutex_unlock(&aconnector->hpd_lock);
3219
3220 }
3221
3222 static void handle_hpd_irq(void *param)
3223 {
3224         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3225
3226         handle_hpd_irq_helper(aconnector);
3227
3228 }
3229
3230 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
3231 {
3232         u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3233         u8 dret;
3234         bool new_irq_handled = false;
3235         int dpcd_addr;
3236         int dpcd_bytes_to_read;
3237
3238         const int max_process_count = 30;
3239         int process_count = 0;
3240
3241         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3242
3243         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3244                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3245                 /* DPCD 0x200 - 0x201 for downstream IRQ */
3246                 dpcd_addr = DP_SINK_COUNT;
3247         } else {
3248                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3249                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3250                 dpcd_addr = DP_SINK_COUNT_ESI;
3251         }
3252
3253         dret = drm_dp_dpcd_read(
3254                 &aconnector->dm_dp_aux.aux,
3255                 dpcd_addr,
3256                 esi,
3257                 dpcd_bytes_to_read);
3258
3259         while (dret == dpcd_bytes_to_read &&
3260                 process_count < max_process_count) {
3261                 u8 retry;
3262                 dret = 0;
3263
3264                 process_count++;
3265
3266                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3267                 /* handle HPD short pulse irq */
3268                 if (aconnector->mst_mgr.mst_state)
3269                         drm_dp_mst_hpd_irq(
3270                                 &aconnector->mst_mgr,
3271                                 esi,
3272                                 &new_irq_handled);
3273
3274                 if (new_irq_handled) {
3275                         /* ACK at DPCD to notify down stream */
3276                         const int ack_dpcd_bytes_to_write =
3277                                 dpcd_bytes_to_read - 1;
3278
3279                         for (retry = 0; retry < 3; retry++) {
3280                                 u8 wret;
3281
3282                                 wret = drm_dp_dpcd_write(
3283                                         &aconnector->dm_dp_aux.aux,
3284                                         dpcd_addr + 1,
3285                                         &esi[1],
3286                                         ack_dpcd_bytes_to_write);
3287                                 if (wret == ack_dpcd_bytes_to_write)
3288                                         break;
3289                         }
3290
3291                         /* check if there is new irq to be handled */
3292                         dret = drm_dp_dpcd_read(
3293                                 &aconnector->dm_dp_aux.aux,
3294                                 dpcd_addr,
3295                                 esi,
3296                                 dpcd_bytes_to_read);
3297
3298                         new_irq_handled = false;
3299                 } else {
3300                         break;
3301                 }
3302         }
3303
3304         if (process_count == max_process_count)
3305                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
3306 }
3307
3308 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3309                                                         union hpd_irq_data hpd_irq_data)
3310 {
3311         struct hpd_rx_irq_offload_work *offload_work =
3312                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3313
3314         if (!offload_work) {
3315                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3316                 return;
3317         }
3318
3319         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3320         offload_work->data = hpd_irq_data;
3321         offload_work->offload_wq = offload_wq;
3322
3323         queue_work(offload_wq->wq, &offload_work->work);
3324         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3325 }
3326
3327 static void handle_hpd_rx_irq(void *param)
3328 {
3329         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3330         struct drm_connector *connector = &aconnector->base;
3331         struct drm_device *dev = connector->dev;
3332         struct dc_link *dc_link = aconnector->dc_link;
3333         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3334         bool result = false;
3335         enum dc_connection_type new_connection_type = dc_connection_none;
3336         struct amdgpu_device *adev = drm_to_adev(dev);
3337         union hpd_irq_data hpd_irq_data;
3338         bool link_loss = false;
3339         bool has_left_work = false;
3340         int idx = dc_link->link_index;
3341         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3342
3343         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3344
3345         if (adev->dm.disable_hpd_irq)
3346                 return;
3347
3348         /*
3349          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3350          * conflict, after implement i2c helper, this mutex should be
3351          * retired.
3352          */
3353         mutex_lock(&aconnector->hpd_lock);
3354
3355         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3356                                                 &link_loss, true, &has_left_work);
3357
3358         if (!has_left_work)
3359                 goto out;
3360
3361         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3362                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3363                 goto out;
3364         }
3365
3366         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3367                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3368                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3369                         dm_handle_mst_sideband_msg(aconnector);
3370                         goto out;
3371                 }
3372
3373                 if (link_loss) {
3374                         bool skip = false;
3375
3376                         spin_lock(&offload_wq->offload_lock);
3377                         skip = offload_wq->is_handling_link_loss;
3378
3379                         if (!skip)
3380                                 offload_wq->is_handling_link_loss = true;
3381
3382                         spin_unlock(&offload_wq->offload_lock);
3383
3384                         if (!skip)
3385                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3386
3387                         goto out;
3388                 }
3389         }
3390
3391 out:
3392         if (result && !is_mst_root_connector) {
3393                 /* Downstream Port status changed. */
3394                 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3395                         DRM_ERROR("KMS: Failed to detect connector\n");
3396
3397                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3398                         emulated_link_detect(dc_link);
3399
3400                         if (aconnector->fake_enable)
3401                                 aconnector->fake_enable = false;
3402
3403                         amdgpu_dm_update_connector_after_detect(aconnector);
3404
3405
3406                         drm_modeset_lock_all(dev);
3407                         dm_restore_drm_connector_state(dev, connector);
3408                         drm_modeset_unlock_all(dev);
3409
3410                         drm_kms_helper_connector_hotplug_event(connector);
3411                 } else {
3412                         bool ret = false;
3413
3414                         mutex_lock(&adev->dm.dc_lock);
3415                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3416                         mutex_unlock(&adev->dm.dc_lock);
3417
3418                         if (ret) {
3419                                 if (aconnector->fake_enable)
3420                                         aconnector->fake_enable = false;
3421
3422                                 amdgpu_dm_update_connector_after_detect(aconnector);
3423
3424                                 drm_modeset_lock_all(dev);
3425                                 dm_restore_drm_connector_state(dev, connector);
3426                                 drm_modeset_unlock_all(dev);
3427
3428                                 drm_kms_helper_connector_hotplug_event(connector);
3429                         }
3430                 }
3431         }
3432         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3433                 if (adev->dm.hdcp_workqueue)
3434                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3435         }
3436
3437         if (dc_link->type != dc_connection_mst_branch)
3438                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3439
3440         mutex_unlock(&aconnector->hpd_lock);
3441 }
3442
3443 static void register_hpd_handlers(struct amdgpu_device *adev)
3444 {
3445         struct drm_device *dev = adev_to_drm(adev);
3446         struct drm_connector *connector;
3447         struct amdgpu_dm_connector *aconnector;
3448         const struct dc_link *dc_link;
3449         struct dc_interrupt_params int_params = {0};
3450
3451         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3452         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3453
3454         list_for_each_entry(connector,
3455                         &dev->mode_config.connector_list, head) {
3456
3457                 aconnector = to_amdgpu_dm_connector(connector);
3458                 dc_link = aconnector->dc_link;
3459
3460                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3461                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3462                         int_params.irq_source = dc_link->irq_source_hpd;
3463
3464                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3465                                         handle_hpd_irq,
3466                                         (void *) aconnector);
3467                 }
3468
3469                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3470
3471                         /* Also register for DP short pulse (hpd_rx). */
3472                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3473                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3474
3475                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3476                                         handle_hpd_rx_irq,
3477                                         (void *) aconnector);
3478
3479                         if (adev->dm.hpd_rx_offload_wq)
3480                                 adev->dm.hpd_rx_offload_wq[dc_link->link_index].aconnector =
3481                                         aconnector;
3482                 }
3483         }
3484 }
3485
3486 #if defined(CONFIG_DRM_AMD_DC_SI)
3487 /* Register IRQ sources and initialize IRQ callbacks */
3488 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3489 {
3490         struct dc *dc = adev->dm.dc;
3491         struct common_irq_params *c_irq_params;
3492         struct dc_interrupt_params int_params = {0};
3493         int r;
3494         int i;
3495         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3496
3497         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3498         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3499
3500         /*
3501          * Actions of amdgpu_irq_add_id():
3502          * 1. Register a set() function with base driver.
3503          *    Base driver will call set() function to enable/disable an
3504          *    interrupt in DC hardware.
3505          * 2. Register amdgpu_dm_irq_handler().
3506          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3507          *    coming from DC hardware.
3508          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3509          *    for acknowledging and handling. */
3510
3511         /* Use VBLANK interrupt */
3512         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3513                 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3514                 if (r) {
3515                         DRM_ERROR("Failed to add crtc irq id!\n");
3516                         return r;
3517                 }
3518
3519                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3520                 int_params.irq_source =
3521                         dc_interrupt_to_irq_source(dc, i+1 , 0);
3522
3523                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3524
3525                 c_irq_params->adev = adev;
3526                 c_irq_params->irq_src = int_params.irq_source;
3527
3528                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3529                                 dm_crtc_high_irq, c_irq_params);
3530         }
3531
3532         /* Use GRPH_PFLIP interrupt */
3533         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3534                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3535                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3536                 if (r) {
3537                         DRM_ERROR("Failed to add page flip irq id!\n");
3538                         return r;
3539                 }
3540
3541                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3542                 int_params.irq_source =
3543                         dc_interrupt_to_irq_source(dc, i, 0);
3544
3545                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3546
3547                 c_irq_params->adev = adev;
3548                 c_irq_params->irq_src = int_params.irq_source;
3549
3550                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3551                                 dm_pflip_high_irq, c_irq_params);
3552
3553         }
3554
3555         /* HPD */
3556         r = amdgpu_irq_add_id(adev, client_id,
3557                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3558         if (r) {
3559                 DRM_ERROR("Failed to add hpd irq id!\n");
3560                 return r;
3561         }
3562
3563         register_hpd_handlers(adev);
3564
3565         return 0;
3566 }
3567 #endif
3568
3569 /* Register IRQ sources and initialize IRQ callbacks */
3570 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3571 {
3572         struct dc *dc = adev->dm.dc;
3573         struct common_irq_params *c_irq_params;
3574         struct dc_interrupt_params int_params = {0};
3575         int r;
3576         int i;
3577         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3578
3579         if (adev->family >= AMDGPU_FAMILY_AI)
3580                 client_id = SOC15_IH_CLIENTID_DCE;
3581
3582         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3583         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3584
3585         /*
3586          * Actions of amdgpu_irq_add_id():
3587          * 1. Register a set() function with base driver.
3588          *    Base driver will call set() function to enable/disable an
3589          *    interrupt in DC hardware.
3590          * 2. Register amdgpu_dm_irq_handler().
3591          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3592          *    coming from DC hardware.
3593          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3594          *    for acknowledging and handling. */
3595
3596         /* Use VBLANK interrupt */
3597         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3598                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3599                 if (r) {
3600                         DRM_ERROR("Failed to add crtc irq id!\n");
3601                         return r;
3602                 }
3603
3604                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3605                 int_params.irq_source =
3606                         dc_interrupt_to_irq_source(dc, i, 0);
3607
3608                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3609
3610                 c_irq_params->adev = adev;
3611                 c_irq_params->irq_src = int_params.irq_source;
3612
3613                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3614                                 dm_crtc_high_irq, c_irq_params);
3615         }
3616
3617         /* Use VUPDATE interrupt */
3618         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3619                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3620                 if (r) {
3621                         DRM_ERROR("Failed to add vupdate irq id!\n");
3622                         return r;
3623                 }
3624
3625                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3626                 int_params.irq_source =
3627                         dc_interrupt_to_irq_source(dc, i, 0);
3628
3629                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3630
3631                 c_irq_params->adev = adev;
3632                 c_irq_params->irq_src = int_params.irq_source;
3633
3634                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3635                                 dm_vupdate_high_irq, c_irq_params);
3636         }
3637
3638         /* Use GRPH_PFLIP interrupt */
3639         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3640                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3641                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3642                 if (r) {
3643                         DRM_ERROR("Failed to add page flip irq id!\n");
3644                         return r;
3645                 }
3646
3647                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3648                 int_params.irq_source =
3649                         dc_interrupt_to_irq_source(dc, i, 0);
3650
3651                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3652
3653                 c_irq_params->adev = adev;
3654                 c_irq_params->irq_src = int_params.irq_source;
3655
3656                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3657                                 dm_pflip_high_irq, c_irq_params);
3658
3659         }
3660
3661         /* HPD */
3662         r = amdgpu_irq_add_id(adev, client_id,
3663                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3664         if (r) {
3665                 DRM_ERROR("Failed to add hpd irq id!\n");
3666                 return r;
3667         }
3668
3669         register_hpd_handlers(adev);
3670
3671         return 0;
3672 }
3673
3674 /* Register IRQ sources and initialize IRQ callbacks */
3675 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3676 {
3677         struct dc *dc = adev->dm.dc;
3678         struct common_irq_params *c_irq_params;
3679         struct dc_interrupt_params int_params = {0};
3680         int r;
3681         int i;
3682 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3683         static const unsigned int vrtl_int_srcid[] = {
3684                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3685                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3686                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3687                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3688                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3689                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3690         };
3691 #endif
3692
3693         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3694         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3695
3696         /*
3697          * Actions of amdgpu_irq_add_id():
3698          * 1. Register a set() function with base driver.
3699          *    Base driver will call set() function to enable/disable an
3700          *    interrupt in DC hardware.
3701          * 2. Register amdgpu_dm_irq_handler().
3702          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3703          *    coming from DC hardware.
3704          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3705          *    for acknowledging and handling.
3706          */
3707
3708         /* Use VSTARTUP interrupt */
3709         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3710                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3711                         i++) {
3712                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3713
3714                 if (r) {
3715                         DRM_ERROR("Failed to add crtc irq id!\n");
3716                         return r;
3717                 }
3718
3719                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3720                 int_params.irq_source =
3721                         dc_interrupt_to_irq_source(dc, i, 0);
3722
3723                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3724
3725                 c_irq_params->adev = adev;
3726                 c_irq_params->irq_src = int_params.irq_source;
3727
3728                 amdgpu_dm_irq_register_interrupt(
3729                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3730         }
3731
3732         /* Use otg vertical line interrupt */
3733 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3734         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3735                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3736                                 vrtl_int_srcid[i], &adev->vline0_irq);
3737
3738                 if (r) {
3739                         DRM_ERROR("Failed to add vline0 irq id!\n");
3740                         return r;
3741                 }
3742
3743                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3744                 int_params.irq_source =
3745                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3746
3747                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3748                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3749                         break;
3750                 }
3751
3752                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3753                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3754
3755                 c_irq_params->adev = adev;
3756                 c_irq_params->irq_src = int_params.irq_source;
3757
3758                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3759                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3760         }
3761 #endif
3762
3763         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3764          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3765          * to trigger at end of each vblank, regardless of state of the lock,
3766          * matching DCE behaviour.
3767          */
3768         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3769              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3770              i++) {
3771                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3772
3773                 if (r) {
3774                         DRM_ERROR("Failed to add vupdate irq id!\n");
3775                         return r;
3776                 }
3777
3778                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3779                 int_params.irq_source =
3780                         dc_interrupt_to_irq_source(dc, i, 0);
3781
3782                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3783
3784                 c_irq_params->adev = adev;
3785                 c_irq_params->irq_src = int_params.irq_source;
3786
3787                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3788                                 dm_vupdate_high_irq, c_irq_params);
3789         }
3790
3791         /* Use GRPH_PFLIP interrupt */
3792         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3793                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3794                         i++) {
3795                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3796                 if (r) {
3797                         DRM_ERROR("Failed to add page flip irq id!\n");
3798                         return r;
3799                 }
3800
3801                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3802                 int_params.irq_source =
3803                         dc_interrupt_to_irq_source(dc, i, 0);
3804
3805                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3806
3807                 c_irq_params->adev = adev;
3808                 c_irq_params->irq_src = int_params.irq_source;
3809
3810                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3811                                 dm_pflip_high_irq, c_irq_params);
3812
3813         }
3814
3815         /* HPD */
3816         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3817                         &adev->hpd_irq);
3818         if (r) {
3819                 DRM_ERROR("Failed to add hpd irq id!\n");
3820                 return r;
3821         }
3822
3823         register_hpd_handlers(adev);
3824
3825         return 0;
3826 }
3827 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3828 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3829 {
3830         struct dc *dc = adev->dm.dc;
3831         struct common_irq_params *c_irq_params;
3832         struct dc_interrupt_params int_params = {0};
3833         int r, i;
3834
3835         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3836         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3837
3838         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3839                         &adev->dmub_outbox_irq);
3840         if (r) {
3841                 DRM_ERROR("Failed to add outbox irq id!\n");
3842                 return r;
3843         }
3844
3845         if (dc->ctx->dmub_srv) {
3846                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3847                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3848                 int_params.irq_source =
3849                 dc_interrupt_to_irq_source(dc, i, 0);
3850
3851                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3852
3853                 c_irq_params->adev = adev;
3854                 c_irq_params->irq_src = int_params.irq_source;
3855
3856                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3857                                 dm_dmub_outbox1_low_irq, c_irq_params);
3858         }
3859
3860         return 0;
3861 }
3862
3863 /*
3864  * Acquires the lock for the atomic state object and returns
3865  * the new atomic state.
3866  *
3867  * This should only be called during atomic check.
3868  */
3869 int dm_atomic_get_state(struct drm_atomic_state *state,
3870                         struct dm_atomic_state **dm_state)
3871 {
3872         struct drm_device *dev = state->dev;
3873         struct amdgpu_device *adev = drm_to_adev(dev);
3874         struct amdgpu_display_manager *dm = &adev->dm;
3875         struct drm_private_state *priv_state;
3876
3877         if (*dm_state)
3878                 return 0;
3879
3880         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3881         if (IS_ERR(priv_state))
3882                 return PTR_ERR(priv_state);
3883
3884         *dm_state = to_dm_atomic_state(priv_state);
3885
3886         return 0;
3887 }
3888
3889 static struct dm_atomic_state *
3890 dm_atomic_get_new_state(struct drm_atomic_state *state)
3891 {
3892         struct drm_device *dev = state->dev;
3893         struct amdgpu_device *adev = drm_to_adev(dev);
3894         struct amdgpu_display_manager *dm = &adev->dm;
3895         struct drm_private_obj *obj;
3896         struct drm_private_state *new_obj_state;
3897         int i;
3898
3899         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3900                 if (obj->funcs == dm->atomic_obj.funcs)
3901                         return to_dm_atomic_state(new_obj_state);
3902         }
3903
3904         return NULL;
3905 }
3906
3907 static struct drm_private_state *
3908 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3909 {
3910         struct dm_atomic_state *old_state, *new_state;
3911
3912         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3913         if (!new_state)
3914                 return NULL;
3915
3916         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3917
3918         old_state = to_dm_atomic_state(obj->state);
3919
3920         if (old_state && old_state->context)
3921                 new_state->context = dc_copy_state(old_state->context);
3922
3923         if (!new_state->context) {
3924                 kfree(new_state);
3925                 return NULL;
3926         }
3927
3928         return &new_state->base;
3929 }
3930
3931 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3932                                     struct drm_private_state *state)
3933 {
3934         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3935
3936         if (dm_state && dm_state->context)
3937                 dc_release_state(dm_state->context);
3938
3939         kfree(dm_state);
3940 }
3941
3942 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3943         .atomic_duplicate_state = dm_atomic_duplicate_state,
3944         .atomic_destroy_state = dm_atomic_destroy_state,
3945 };
3946
3947 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3948 {
3949         struct dm_atomic_state *state;
3950         int r;
3951
3952         adev->mode_info.mode_config_initialized = true;
3953
3954         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3955         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3956
3957         adev_to_drm(adev)->mode_config.max_width = 16384;
3958         adev_to_drm(adev)->mode_config.max_height = 16384;
3959
3960         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3961         if (adev->asic_type == CHIP_HAWAII)
3962                 /* disable prefer shadow for now due to hibernation issues */
3963                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3964         else
3965                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3966         /* indicates support for immediate flip */
3967         adev_to_drm(adev)->mode_config.async_page_flip = true;
3968
3969         state = kzalloc(sizeof(*state), GFP_KERNEL);
3970         if (!state)
3971                 return -ENOMEM;
3972
3973         state->context = dc_create_state(adev->dm.dc);
3974         if (!state->context) {
3975                 kfree(state);
3976                 return -ENOMEM;
3977         }
3978
3979         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3980
3981         drm_atomic_private_obj_init(adev_to_drm(adev),
3982                                     &adev->dm.atomic_obj,
3983                                     &state->base,
3984                                     &dm_atomic_state_funcs);
3985
3986         r = amdgpu_display_modeset_create_props(adev);
3987         if (r) {
3988                 dc_release_state(state->context);
3989                 kfree(state);
3990                 return r;
3991         }
3992
3993         r = amdgpu_dm_audio_init(adev);
3994         if (r) {
3995                 dc_release_state(state->context);
3996                 kfree(state);
3997                 return r;
3998         }
3999
4000         return 0;
4001 }
4002
4003 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4004 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4005 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4006
4007 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4008                                             int bl_idx)
4009 {
4010 #if defined(CONFIG_ACPI)
4011         struct amdgpu_dm_backlight_caps caps;
4012
4013         memset(&caps, 0, sizeof(caps));
4014
4015         if (dm->backlight_caps[bl_idx].caps_valid)
4016                 return;
4017
4018         amdgpu_acpi_get_backlight_caps(&caps);
4019         if (caps.caps_valid) {
4020                 dm->backlight_caps[bl_idx].caps_valid = true;
4021                 if (caps.aux_support)
4022                         return;
4023                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4024                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4025         } else {
4026                 dm->backlight_caps[bl_idx].min_input_signal =
4027                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4028                 dm->backlight_caps[bl_idx].max_input_signal =
4029                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4030         }
4031 #else
4032         if (dm->backlight_caps[bl_idx].aux_support)
4033                 return;
4034
4035         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4036         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4037 #endif
4038 }
4039
4040 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4041                                 unsigned *min, unsigned *max)
4042 {
4043         if (!caps)
4044                 return 0;
4045
4046         if (caps->aux_support) {
4047                 // Firmware limits are in nits, DC API wants millinits.
4048                 *max = 1000 * caps->aux_max_input_signal;
4049                 *min = 1000 * caps->aux_min_input_signal;
4050         } else {
4051                 // Firmware limits are 8-bit, PWM control is 16-bit.
4052                 *max = 0x101 * caps->max_input_signal;
4053                 *min = 0x101 * caps->min_input_signal;
4054         }
4055         return 1;
4056 }
4057
4058 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4059                                         uint32_t brightness)
4060 {
4061         unsigned min, max;
4062
4063         if (!get_brightness_range(caps, &min, &max))
4064                 return brightness;
4065
4066         // Rescale 0..255 to min..max
4067         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4068                                        AMDGPU_MAX_BL_LEVEL);
4069 }
4070
4071 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4072                                       uint32_t brightness)
4073 {
4074         unsigned min, max;
4075
4076         if (!get_brightness_range(caps, &min, &max))
4077                 return brightness;
4078
4079         if (brightness < min)
4080                 return 0;
4081         // Rescale min..max to 0..255
4082         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4083                                  max - min);
4084 }
4085
4086 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4087                                          int bl_idx,
4088                                          u32 user_brightness)
4089 {
4090         struct amdgpu_dm_backlight_caps caps;
4091         struct dc_link *link;
4092         u32 brightness;
4093         bool rc;
4094
4095         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4096         caps = dm->backlight_caps[bl_idx];
4097
4098         dm->brightness[bl_idx] = user_brightness;
4099         /* update scratch register */
4100         if (bl_idx == 0)
4101                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4102         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4103         link = (struct dc_link *)dm->backlight_link[bl_idx];
4104
4105         /* Change brightness based on AUX property */
4106         if (caps.aux_support) {
4107                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4108                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4109                 if (!rc)
4110                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4111         } else {
4112                 rc = dc_link_set_backlight_level(link, brightness, 0);
4113                 if (!rc)
4114                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4115         }
4116
4117         if (rc)
4118                 dm->actual_brightness[bl_idx] = user_brightness;
4119 }
4120
4121 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4122 {
4123         struct amdgpu_display_manager *dm = bl_get_data(bd);
4124         int i;
4125
4126         for (i = 0; i < dm->num_of_edps; i++) {
4127                 if (bd == dm->backlight_dev[i])
4128                         break;
4129         }
4130         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4131                 i = 0;
4132         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4133
4134         return 0;
4135 }
4136
4137 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4138                                          int bl_idx)
4139 {
4140         struct amdgpu_dm_backlight_caps caps;
4141         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4142
4143         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4144         caps = dm->backlight_caps[bl_idx];
4145
4146         if (caps.aux_support) {
4147                 u32 avg, peak;
4148                 bool rc;
4149
4150                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4151                 if (!rc)
4152                         return dm->brightness[bl_idx];
4153                 return convert_brightness_to_user(&caps, avg);
4154         } else {
4155                 int ret = dc_link_get_backlight_level(link);
4156
4157                 if (ret == DC_ERROR_UNEXPECTED)
4158                         return dm->brightness[bl_idx];
4159                 return convert_brightness_to_user(&caps, ret);
4160         }
4161 }
4162
4163 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4164 {
4165         struct amdgpu_display_manager *dm = bl_get_data(bd);
4166         int i;
4167
4168         for (i = 0; i < dm->num_of_edps; i++) {
4169                 if (bd == dm->backlight_dev[i])
4170                         break;
4171         }
4172         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4173                 i = 0;
4174         return amdgpu_dm_backlight_get_level(dm, i);
4175 }
4176
4177 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4178         .options = BL_CORE_SUSPENDRESUME,
4179         .get_brightness = amdgpu_dm_backlight_get_brightness,
4180         .update_status  = amdgpu_dm_backlight_update_status,
4181 };
4182
4183 static void
4184 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4185 {
4186         struct drm_device *drm = aconnector->base.dev;
4187         struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4188         struct backlight_properties props = { 0 };
4189         char bl_name[16];
4190
4191         if (aconnector->bl_idx == -1)
4192                 return;
4193
4194         if (!acpi_video_backlight_use_native()) {
4195                 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4196                 /* Try registering an ACPI video backlight device instead. */
4197                 acpi_video_register_backlight();
4198                 return;
4199         }
4200
4201         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4202         props.brightness = AMDGPU_MAX_BL_LEVEL;
4203         props.type = BACKLIGHT_RAW;
4204
4205         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4206                  drm->primary->index + aconnector->bl_idx);
4207
4208         dm->backlight_dev[aconnector->bl_idx] =
4209                 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4210                                           &amdgpu_dm_backlight_ops, &props);
4211
4212         if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4213                 DRM_ERROR("DM: Backlight registration failed!\n");
4214                 dm->backlight_dev[aconnector->bl_idx] = NULL;
4215         } else
4216                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4217 }
4218
4219 static int initialize_plane(struct amdgpu_display_manager *dm,
4220                             struct amdgpu_mode_info *mode_info, int plane_id,
4221                             enum drm_plane_type plane_type,
4222                             const struct dc_plane_cap *plane_cap)
4223 {
4224         struct drm_plane *plane;
4225         unsigned long possible_crtcs;
4226         int ret = 0;
4227
4228         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4229         if (!plane) {
4230                 DRM_ERROR("KMS: Failed to allocate plane\n");
4231                 return -ENOMEM;
4232         }
4233         plane->type = plane_type;
4234
4235         /*
4236          * HACK: IGT tests expect that the primary plane for a CRTC
4237          * can only have one possible CRTC. Only expose support for
4238          * any CRTC if they're not going to be used as a primary plane
4239          * for a CRTC - like overlay or underlay planes.
4240          */
4241         possible_crtcs = 1 << plane_id;
4242         if (plane_id >= dm->dc->caps.max_streams)
4243                 possible_crtcs = 0xff;
4244
4245         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4246
4247         if (ret) {
4248                 DRM_ERROR("KMS: Failed to initialize plane\n");
4249                 kfree(plane);
4250                 return ret;
4251         }
4252
4253         if (mode_info)
4254                 mode_info->planes[plane_id] = plane;
4255
4256         return ret;
4257 }
4258
4259
4260 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4261                                    struct amdgpu_dm_connector *aconnector)
4262 {
4263         struct dc_link *link = aconnector->dc_link;
4264         int bl_idx = dm->num_of_edps;
4265
4266         if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4267             link->type == dc_connection_none)
4268                 return;
4269
4270         if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4271                 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4272                 return;
4273         }
4274
4275         aconnector->bl_idx = bl_idx;
4276
4277         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4278         dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4279         dm->backlight_link[bl_idx] = link;
4280         dm->num_of_edps++;
4281
4282         update_connector_ext_caps(aconnector);
4283 }
4284
4285 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4286
4287 /*
4288  * In this architecture, the association
4289  * connector -> encoder -> crtc
4290  * id not really requried. The crtc and connector will hold the
4291  * display_index as an abstraction to use with DAL component
4292  *
4293  * Returns 0 on success
4294  */
4295 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4296 {
4297         struct amdgpu_display_manager *dm = &adev->dm;
4298         s32 i;
4299         struct amdgpu_dm_connector *aconnector = NULL;
4300         struct amdgpu_encoder *aencoder = NULL;
4301         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4302         u32 link_cnt;
4303         s32 primary_planes;
4304         enum dc_connection_type new_connection_type = dc_connection_none;
4305         const struct dc_plane_cap *plane;
4306         bool psr_feature_enabled = false;
4307         int max_overlay = dm->dc->caps.max_slave_planes;
4308
4309         dm->display_indexes_num = dm->dc->caps.max_streams;
4310         /* Update the actual used number of crtc */
4311         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4312
4313         amdgpu_dm_set_irq_funcs(adev);
4314
4315         link_cnt = dm->dc->caps.max_links;
4316         if (amdgpu_dm_mode_config_init(dm->adev)) {
4317                 DRM_ERROR("DM: Failed to initialize mode config\n");
4318                 return -EINVAL;
4319         }
4320
4321         /* There is one primary plane per CRTC */
4322         primary_planes = dm->dc->caps.max_streams;
4323         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4324
4325         /*
4326          * Initialize primary planes, implicit planes for legacy IOCTLS.
4327          * Order is reversed to match iteration order in atomic check.
4328          */
4329         for (i = (primary_planes - 1); i >= 0; i--) {
4330                 plane = &dm->dc->caps.planes[i];
4331
4332                 if (initialize_plane(dm, mode_info, i,
4333                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4334                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4335                         goto fail;
4336                 }
4337         }
4338
4339         /*
4340          * Initialize overlay planes, index starting after primary planes.
4341          * These planes have a higher DRM index than the primary planes since
4342          * they should be considered as having a higher z-order.
4343          * Order is reversed to match iteration order in atomic check.
4344          *
4345          * Only support DCN for now, and only expose one so we don't encourage
4346          * userspace to use up all the pipes.
4347          */
4348         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4349                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4350
4351                 /* Do not create overlay if MPO disabled */
4352                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4353                         break;
4354
4355                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4356                         continue;
4357
4358                 if (!plane->pixel_format_support.argb8888)
4359                         continue;
4360
4361                 if (max_overlay-- == 0)
4362                         break;
4363
4364                 if (initialize_plane(dm, NULL, primary_planes + i,
4365                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4366                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4367                         goto fail;
4368                 }
4369         }
4370
4371         for (i = 0; i < dm->dc->caps.max_streams; i++)
4372                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4373                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4374                         goto fail;
4375                 }
4376
4377         /* Use Outbox interrupt */
4378         switch (adev->ip_versions[DCE_HWIP][0]) {
4379         case IP_VERSION(3, 0, 0):
4380         case IP_VERSION(3, 1, 2):
4381         case IP_VERSION(3, 1, 3):
4382         case IP_VERSION(3, 1, 4):
4383         case IP_VERSION(3, 1, 5):
4384         case IP_VERSION(3, 1, 6):
4385         case IP_VERSION(3, 2, 0):
4386         case IP_VERSION(3, 2, 1):
4387         case IP_VERSION(2, 1, 0):
4388                 if (register_outbox_irq_handlers(dm->adev)) {
4389                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4390                         goto fail;
4391                 }
4392                 break;
4393         default:
4394                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4395                               adev->ip_versions[DCE_HWIP][0]);
4396         }
4397
4398         /* Determine whether to enable PSR support by default. */
4399         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4400                 switch (adev->ip_versions[DCE_HWIP][0]) {
4401                 case IP_VERSION(3, 1, 2):
4402                 case IP_VERSION(3, 1, 3):
4403                 case IP_VERSION(3, 1, 4):
4404                 case IP_VERSION(3, 1, 5):
4405                 case IP_VERSION(3, 1, 6):
4406                 case IP_VERSION(3, 2, 0):
4407                 case IP_VERSION(3, 2, 1):
4408                         psr_feature_enabled = true;
4409                         break;
4410                 default:
4411                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4412                         break;
4413                 }
4414         }
4415
4416         /* loops over all connectors on the board */
4417         for (i = 0; i < link_cnt; i++) {
4418                 struct dc_link *link = NULL;
4419
4420                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4421                         DRM_ERROR(
4422                                 "KMS: Cannot support more than %d display indexes\n",
4423                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4424                         continue;
4425                 }
4426
4427                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4428                 if (!aconnector)
4429                         goto fail;
4430
4431                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4432                 if (!aencoder)
4433                         goto fail;
4434
4435                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4436                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4437                         goto fail;
4438                 }
4439
4440                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4441                         DRM_ERROR("KMS: Failed to initialize connector\n");
4442                         goto fail;
4443                 }
4444
4445                 link = dc_get_link_at_index(dm->dc, i);
4446
4447                 if (!dc_link_detect_connection_type(link, &new_connection_type))
4448                         DRM_ERROR("KMS: Failed to detect connector\n");
4449
4450                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4451                         emulated_link_detect(link);
4452                         amdgpu_dm_update_connector_after_detect(aconnector);
4453                 } else {
4454                         bool ret = false;
4455
4456                         mutex_lock(&dm->dc_lock);
4457                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4458                         mutex_unlock(&dm->dc_lock);
4459
4460                         if (ret) {
4461                                 amdgpu_dm_update_connector_after_detect(aconnector);
4462                                 setup_backlight_device(dm, aconnector);
4463
4464                                 if (psr_feature_enabled)
4465                                         amdgpu_dm_set_psr_caps(link);
4466
4467                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4468                                  * PSR is also supported.
4469                                  */
4470                                 if (link->psr_settings.psr_feature_enabled)
4471                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4472                         }
4473                 }
4474                 amdgpu_set_panel_orientation(&aconnector->base);
4475         }
4476
4477         /* Software is initialized. Now we can register interrupt handlers. */
4478         switch (adev->asic_type) {
4479 #if defined(CONFIG_DRM_AMD_DC_SI)
4480         case CHIP_TAHITI:
4481         case CHIP_PITCAIRN:
4482         case CHIP_VERDE:
4483         case CHIP_OLAND:
4484                 if (dce60_register_irq_handlers(dm->adev)) {
4485                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4486                         goto fail;
4487                 }
4488                 break;
4489 #endif
4490         case CHIP_BONAIRE:
4491         case CHIP_HAWAII:
4492         case CHIP_KAVERI:
4493         case CHIP_KABINI:
4494         case CHIP_MULLINS:
4495         case CHIP_TONGA:
4496         case CHIP_FIJI:
4497         case CHIP_CARRIZO:
4498         case CHIP_STONEY:
4499         case CHIP_POLARIS11:
4500         case CHIP_POLARIS10:
4501         case CHIP_POLARIS12:
4502         case CHIP_VEGAM:
4503         case CHIP_VEGA10:
4504         case CHIP_VEGA12:
4505         case CHIP_VEGA20:
4506                 if (dce110_register_irq_handlers(dm->adev)) {
4507                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4508                         goto fail;
4509                 }
4510                 break;
4511         default:
4512                 switch (adev->ip_versions[DCE_HWIP][0]) {
4513                 case IP_VERSION(1, 0, 0):
4514                 case IP_VERSION(1, 0, 1):
4515                 case IP_VERSION(2, 0, 2):
4516                 case IP_VERSION(2, 0, 3):
4517                 case IP_VERSION(2, 0, 0):
4518                 case IP_VERSION(2, 1, 0):
4519                 case IP_VERSION(3, 0, 0):
4520                 case IP_VERSION(3, 0, 2):
4521                 case IP_VERSION(3, 0, 3):
4522                 case IP_VERSION(3, 0, 1):
4523                 case IP_VERSION(3, 1, 2):
4524                 case IP_VERSION(3, 1, 3):
4525                 case IP_VERSION(3, 1, 4):
4526                 case IP_VERSION(3, 1, 5):
4527                 case IP_VERSION(3, 1, 6):
4528                 case IP_VERSION(3, 2, 0):
4529                 case IP_VERSION(3, 2, 1):
4530                         if (dcn10_register_irq_handlers(dm->adev)) {
4531                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4532                                 goto fail;
4533                         }
4534                         break;
4535                 default:
4536                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4537                                         adev->ip_versions[DCE_HWIP][0]);
4538                         goto fail;
4539                 }
4540                 break;
4541         }
4542
4543         return 0;
4544 fail:
4545         kfree(aencoder);
4546         kfree(aconnector);
4547
4548         return -EINVAL;
4549 }
4550
4551 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4552 {
4553         drm_atomic_private_obj_fini(&dm->atomic_obj);
4554         return;
4555 }
4556
4557 /******************************************************************************
4558  * amdgpu_display_funcs functions
4559  *****************************************************************************/
4560
4561 /*
4562  * dm_bandwidth_update - program display watermarks
4563  *
4564  * @adev: amdgpu_device pointer
4565  *
4566  * Calculate and program the display watermarks and line buffer allocation.
4567  */
4568 static void dm_bandwidth_update(struct amdgpu_device *adev)
4569 {
4570         /* TODO: implement later */
4571 }
4572
4573 static const struct amdgpu_display_funcs dm_display_funcs = {
4574         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4575         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4576         .backlight_set_level = NULL, /* never called for DC */
4577         .backlight_get_level = NULL, /* never called for DC */
4578         .hpd_sense = NULL,/* called unconditionally */
4579         .hpd_set_polarity = NULL, /* called unconditionally */
4580         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4581         .page_flip_get_scanoutpos =
4582                 dm_crtc_get_scanoutpos,/* called unconditionally */
4583         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4584         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4585 };
4586
4587 #if defined(CONFIG_DEBUG_KERNEL_DC)
4588
4589 static ssize_t s3_debug_store(struct device *device,
4590                               struct device_attribute *attr,
4591                               const char *buf,
4592                               size_t count)
4593 {
4594         int ret;
4595         int s3_state;
4596         struct drm_device *drm_dev = dev_get_drvdata(device);
4597         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4598
4599         ret = kstrtoint(buf, 0, &s3_state);
4600
4601         if (ret == 0) {
4602                 if (s3_state) {
4603                         dm_resume(adev);
4604                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4605                 } else
4606                         dm_suspend(adev);
4607         }
4608
4609         return ret == 0 ? count : 0;
4610 }
4611
4612 DEVICE_ATTR_WO(s3_debug);
4613
4614 #endif
4615
4616 static int dm_init_microcode(struct amdgpu_device *adev)
4617 {
4618         char *fw_name_dmub;
4619         int r;
4620
4621         switch (adev->ip_versions[DCE_HWIP][0]) {
4622         case IP_VERSION(2, 1, 0):
4623                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4624                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4625                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4626                 break;
4627         case IP_VERSION(3, 0, 0):
4628                 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4629                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4630                 else
4631                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4632                 break;
4633         case IP_VERSION(3, 0, 1):
4634                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4635                 break;
4636         case IP_VERSION(3, 0, 2):
4637                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4638                 break;
4639         case IP_VERSION(3, 0, 3):
4640                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4641                 break;
4642         case IP_VERSION(3, 1, 2):
4643         case IP_VERSION(3, 1, 3):
4644                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4645                 break;
4646         case IP_VERSION(3, 1, 4):
4647                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4648                 break;
4649         case IP_VERSION(3, 1, 5):
4650                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4651                 break;
4652         case IP_VERSION(3, 1, 6):
4653                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4654                 break;
4655         case IP_VERSION(3, 2, 0):
4656                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4657                 break;
4658         case IP_VERSION(3, 2, 1):
4659                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4660                 break;
4661         default:
4662                 /* ASIC doesn't support DMUB. */
4663                 return 0;
4664         }
4665         r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4666         if (r)
4667                 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4668         return r;
4669 }
4670
4671 static int dm_early_init(void *handle)
4672 {
4673         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4674         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4675         struct atom_context *ctx = mode_info->atom_context;
4676         int index = GetIndexIntoMasterTable(DATA, Object_Header);
4677         u16 data_offset;
4678
4679         /* if there is no object header, skip DM */
4680         if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4681                 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4682                 dev_info(adev->dev, "No object header, skipping DM\n");
4683                 return -ENOENT;
4684         }
4685
4686         switch (adev->asic_type) {
4687 #if defined(CONFIG_DRM_AMD_DC_SI)
4688         case CHIP_TAHITI:
4689         case CHIP_PITCAIRN:
4690         case CHIP_VERDE:
4691                 adev->mode_info.num_crtc = 6;
4692                 adev->mode_info.num_hpd = 6;
4693                 adev->mode_info.num_dig = 6;
4694                 break;
4695         case CHIP_OLAND:
4696                 adev->mode_info.num_crtc = 2;
4697                 adev->mode_info.num_hpd = 2;
4698                 adev->mode_info.num_dig = 2;
4699                 break;
4700 #endif
4701         case CHIP_BONAIRE:
4702         case CHIP_HAWAII:
4703                 adev->mode_info.num_crtc = 6;
4704                 adev->mode_info.num_hpd = 6;
4705                 adev->mode_info.num_dig = 6;
4706                 break;
4707         case CHIP_KAVERI:
4708                 adev->mode_info.num_crtc = 4;
4709                 adev->mode_info.num_hpd = 6;
4710                 adev->mode_info.num_dig = 7;
4711                 break;
4712         case CHIP_KABINI:
4713         case CHIP_MULLINS:
4714                 adev->mode_info.num_crtc = 2;
4715                 adev->mode_info.num_hpd = 6;
4716                 adev->mode_info.num_dig = 6;
4717                 break;
4718         case CHIP_FIJI:
4719         case CHIP_TONGA:
4720                 adev->mode_info.num_crtc = 6;
4721                 adev->mode_info.num_hpd = 6;
4722                 adev->mode_info.num_dig = 7;
4723                 break;
4724         case CHIP_CARRIZO:
4725                 adev->mode_info.num_crtc = 3;
4726                 adev->mode_info.num_hpd = 6;
4727                 adev->mode_info.num_dig = 9;
4728                 break;
4729         case CHIP_STONEY:
4730                 adev->mode_info.num_crtc = 2;
4731                 adev->mode_info.num_hpd = 6;
4732                 adev->mode_info.num_dig = 9;
4733                 break;
4734         case CHIP_POLARIS11:
4735         case CHIP_POLARIS12:
4736                 adev->mode_info.num_crtc = 5;
4737                 adev->mode_info.num_hpd = 5;
4738                 adev->mode_info.num_dig = 5;
4739                 break;
4740         case CHIP_POLARIS10:
4741         case CHIP_VEGAM:
4742                 adev->mode_info.num_crtc = 6;
4743                 adev->mode_info.num_hpd = 6;
4744                 adev->mode_info.num_dig = 6;
4745                 break;
4746         case CHIP_VEGA10:
4747         case CHIP_VEGA12:
4748         case CHIP_VEGA20:
4749                 adev->mode_info.num_crtc = 6;
4750                 adev->mode_info.num_hpd = 6;
4751                 adev->mode_info.num_dig = 6;
4752                 break;
4753         default:
4754
4755                 switch (adev->ip_versions[DCE_HWIP][0]) {
4756                 case IP_VERSION(2, 0, 2):
4757                 case IP_VERSION(3, 0, 0):
4758                         adev->mode_info.num_crtc = 6;
4759                         adev->mode_info.num_hpd = 6;
4760                         adev->mode_info.num_dig = 6;
4761                         break;
4762                 case IP_VERSION(2, 0, 0):
4763                 case IP_VERSION(3, 0, 2):
4764                         adev->mode_info.num_crtc = 5;
4765                         adev->mode_info.num_hpd = 5;
4766                         adev->mode_info.num_dig = 5;
4767                         break;
4768                 case IP_VERSION(2, 0, 3):
4769                 case IP_VERSION(3, 0, 3):
4770                         adev->mode_info.num_crtc = 2;
4771                         adev->mode_info.num_hpd = 2;
4772                         adev->mode_info.num_dig = 2;
4773                         break;
4774                 case IP_VERSION(1, 0, 0):
4775                 case IP_VERSION(1, 0, 1):
4776                 case IP_VERSION(3, 0, 1):
4777                 case IP_VERSION(2, 1, 0):
4778                 case IP_VERSION(3, 1, 2):
4779                 case IP_VERSION(3, 1, 3):
4780                 case IP_VERSION(3, 1, 4):
4781                 case IP_VERSION(3, 1, 5):
4782                 case IP_VERSION(3, 1, 6):
4783                 case IP_VERSION(3, 2, 0):
4784                 case IP_VERSION(3, 2, 1):
4785                         adev->mode_info.num_crtc = 4;
4786                         adev->mode_info.num_hpd = 4;
4787                         adev->mode_info.num_dig = 4;
4788                         break;
4789                 default:
4790                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4791                                         adev->ip_versions[DCE_HWIP][0]);
4792                         return -EINVAL;
4793                 }
4794                 break;
4795         }
4796
4797         if (adev->mode_info.funcs == NULL)
4798                 adev->mode_info.funcs = &dm_display_funcs;
4799
4800         /*
4801          * Note: Do NOT change adev->audio_endpt_rreg and
4802          * adev->audio_endpt_wreg because they are initialised in
4803          * amdgpu_device_init()
4804          */
4805 #if defined(CONFIG_DEBUG_KERNEL_DC)
4806         device_create_file(
4807                 adev_to_drm(adev)->dev,
4808                 &dev_attr_s3_debug);
4809 #endif
4810         adev->dc_enabled = true;
4811
4812         return dm_init_microcode(adev);
4813 }
4814
4815 static bool modereset_required(struct drm_crtc_state *crtc_state)
4816 {
4817         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4818 }
4819
4820 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4821 {
4822         drm_encoder_cleanup(encoder);
4823         kfree(encoder);
4824 }
4825
4826 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4827         .destroy = amdgpu_dm_encoder_destroy,
4828 };
4829
4830 static int
4831 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4832                             const enum surface_pixel_format format,
4833                             enum dc_color_space *color_space)
4834 {
4835         bool full_range;
4836
4837         *color_space = COLOR_SPACE_SRGB;
4838
4839         /* DRM color properties only affect non-RGB formats. */
4840         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4841                 return 0;
4842
4843         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4844
4845         switch (plane_state->color_encoding) {
4846         case DRM_COLOR_YCBCR_BT601:
4847                 if (full_range)
4848                         *color_space = COLOR_SPACE_YCBCR601;
4849                 else
4850                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4851                 break;
4852
4853         case DRM_COLOR_YCBCR_BT709:
4854                 if (full_range)
4855                         *color_space = COLOR_SPACE_YCBCR709;
4856                 else
4857                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4858                 break;
4859
4860         case DRM_COLOR_YCBCR_BT2020:
4861                 if (full_range)
4862                         *color_space = COLOR_SPACE_2020_YCBCR;
4863                 else
4864                         return -EINVAL;
4865                 break;
4866
4867         default:
4868                 return -EINVAL;
4869         }
4870
4871         return 0;
4872 }
4873
4874 static int
4875 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4876                             const struct drm_plane_state *plane_state,
4877                             const u64 tiling_flags,
4878                             struct dc_plane_info *plane_info,
4879                             struct dc_plane_address *address,
4880                             bool tmz_surface,
4881                             bool force_disable_dcc)
4882 {
4883         const struct drm_framebuffer *fb = plane_state->fb;
4884         const struct amdgpu_framebuffer *afb =
4885                 to_amdgpu_framebuffer(plane_state->fb);
4886         int ret;
4887
4888         memset(plane_info, 0, sizeof(*plane_info));
4889
4890         switch (fb->format->format) {
4891         case DRM_FORMAT_C8:
4892                 plane_info->format =
4893                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4894                 break;
4895         case DRM_FORMAT_RGB565:
4896                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4897                 break;
4898         case DRM_FORMAT_XRGB8888:
4899         case DRM_FORMAT_ARGB8888:
4900                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4901                 break;
4902         case DRM_FORMAT_XRGB2101010:
4903         case DRM_FORMAT_ARGB2101010:
4904                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4905                 break;
4906         case DRM_FORMAT_XBGR2101010:
4907         case DRM_FORMAT_ABGR2101010:
4908                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4909                 break;
4910         case DRM_FORMAT_XBGR8888:
4911         case DRM_FORMAT_ABGR8888:
4912                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4913                 break;
4914         case DRM_FORMAT_NV21:
4915                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4916                 break;
4917         case DRM_FORMAT_NV12:
4918                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4919                 break;
4920         case DRM_FORMAT_P010:
4921                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4922                 break;
4923         case DRM_FORMAT_XRGB16161616F:
4924         case DRM_FORMAT_ARGB16161616F:
4925                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4926                 break;
4927         case DRM_FORMAT_XBGR16161616F:
4928         case DRM_FORMAT_ABGR16161616F:
4929                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4930                 break;
4931         case DRM_FORMAT_XRGB16161616:
4932         case DRM_FORMAT_ARGB16161616:
4933                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4934                 break;
4935         case DRM_FORMAT_XBGR16161616:
4936         case DRM_FORMAT_ABGR16161616:
4937                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4938                 break;
4939         default:
4940                 DRM_ERROR(
4941                         "Unsupported screen format %p4cc\n",
4942                         &fb->format->format);
4943                 return -EINVAL;
4944         }
4945
4946         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4947         case DRM_MODE_ROTATE_0:
4948                 plane_info->rotation = ROTATION_ANGLE_0;
4949                 break;
4950         case DRM_MODE_ROTATE_90:
4951                 plane_info->rotation = ROTATION_ANGLE_90;
4952                 break;
4953         case DRM_MODE_ROTATE_180:
4954                 plane_info->rotation = ROTATION_ANGLE_180;
4955                 break;
4956         case DRM_MODE_ROTATE_270:
4957                 plane_info->rotation = ROTATION_ANGLE_270;
4958                 break;
4959         default:
4960                 plane_info->rotation = ROTATION_ANGLE_0;
4961                 break;
4962         }
4963
4964
4965         plane_info->visible = true;
4966         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4967
4968         plane_info->layer_index = plane_state->normalized_zpos;
4969
4970         ret = fill_plane_color_attributes(plane_state, plane_info->format,
4971                                           &plane_info->color_space);
4972         if (ret)
4973                 return ret;
4974
4975         ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
4976                                            plane_info->rotation, tiling_flags,
4977                                            &plane_info->tiling_info,
4978                                            &plane_info->plane_size,
4979                                            &plane_info->dcc, address,
4980                                            tmz_surface, force_disable_dcc);
4981         if (ret)
4982                 return ret;
4983
4984         amdgpu_dm_plane_fill_blending_from_plane_state(
4985                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4986                 &plane_info->global_alpha, &plane_info->global_alpha_value);
4987
4988         return 0;
4989 }
4990
4991 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4992                                     struct dc_plane_state *dc_plane_state,
4993                                     struct drm_plane_state *plane_state,
4994                                     struct drm_crtc_state *crtc_state)
4995 {
4996         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4997         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
4998         struct dc_scaling_info scaling_info;
4999         struct dc_plane_info plane_info;
5000         int ret;
5001         bool force_disable_dcc = false;
5002
5003         ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5004         if (ret)
5005                 return ret;
5006
5007         dc_plane_state->src_rect = scaling_info.src_rect;
5008         dc_plane_state->dst_rect = scaling_info.dst_rect;
5009         dc_plane_state->clip_rect = scaling_info.clip_rect;
5010         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5011
5012         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5013         ret = fill_dc_plane_info_and_addr(adev, plane_state,
5014                                           afb->tiling_flags,
5015                                           &plane_info,
5016                                           &dc_plane_state->address,
5017                                           afb->tmz_surface,
5018                                           force_disable_dcc);
5019         if (ret)
5020                 return ret;
5021
5022         dc_plane_state->format = plane_info.format;
5023         dc_plane_state->color_space = plane_info.color_space;
5024         dc_plane_state->format = plane_info.format;
5025         dc_plane_state->plane_size = plane_info.plane_size;
5026         dc_plane_state->rotation = plane_info.rotation;
5027         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5028         dc_plane_state->stereo_format = plane_info.stereo_format;
5029         dc_plane_state->tiling_info = plane_info.tiling_info;
5030         dc_plane_state->visible = plane_info.visible;
5031         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5032         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5033         dc_plane_state->global_alpha = plane_info.global_alpha;
5034         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5035         dc_plane_state->dcc = plane_info.dcc;
5036         dc_plane_state->layer_index = plane_info.layer_index;
5037         dc_plane_state->flip_int_enabled = true;
5038
5039         /*
5040          * Always set input transfer function, since plane state is refreshed
5041          * every time.
5042          */
5043         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5044         if (ret)
5045                 return ret;
5046
5047         return 0;
5048 }
5049
5050 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5051                                       struct rect *dirty_rect, int32_t x,
5052                                       s32 y, s32 width, s32 height,
5053                                       int *i, bool ffu)
5054 {
5055         if (*i > DC_MAX_DIRTY_RECTS)
5056                 return;
5057
5058         if (*i == DC_MAX_DIRTY_RECTS)
5059                 goto out;
5060
5061         dirty_rect->x = x;
5062         dirty_rect->y = y;
5063         dirty_rect->width = width;
5064         dirty_rect->height = height;
5065
5066         if (ffu)
5067                 drm_dbg(plane->dev,
5068                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5069                         plane->base.id, width, height);
5070         else
5071                 drm_dbg(plane->dev,
5072                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5073                         plane->base.id, x, y, width, height);
5074
5075 out:
5076         (*i)++;
5077 }
5078
5079 /**
5080  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5081  *
5082  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5083  *         remote fb
5084  * @old_plane_state: Old state of @plane
5085  * @new_plane_state: New state of @plane
5086  * @crtc_state: New state of CRTC connected to the @plane
5087  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5088  * @dirty_regions_changed: dirty regions changed
5089  *
5090  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5091  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5092  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5093  * amdgpu_dm's.
5094  *
5095  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5096  * plane with regions that require flushing to the eDP remote buffer. In
5097  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5098  * implicitly provide damage clips without any client support via the plane
5099  * bounds.
5100  */
5101 static void fill_dc_dirty_rects(struct drm_plane *plane,
5102                                 struct drm_plane_state *old_plane_state,
5103                                 struct drm_plane_state *new_plane_state,
5104                                 struct drm_crtc_state *crtc_state,
5105                                 struct dc_flip_addrs *flip_addrs,
5106                                 bool *dirty_regions_changed)
5107 {
5108         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5109         struct rect *dirty_rects = flip_addrs->dirty_rects;
5110         u32 num_clips;
5111         struct drm_mode_rect *clips;
5112         bool bb_changed;
5113         bool fb_changed;
5114         u32 i = 0;
5115         *dirty_regions_changed = false;
5116
5117         /*
5118          * Cursor plane has it's own dirty rect update interface. See
5119          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5120          */
5121         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5122                 return;
5123
5124         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5125         clips = drm_plane_get_damage_clips(new_plane_state);
5126
5127         if (!dm_crtc_state->mpo_requested) {
5128                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5129                         goto ffu;
5130
5131                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5132                         fill_dc_dirty_rect(new_plane_state->plane,
5133                                            &dirty_rects[flip_addrs->dirty_rect_count],
5134                                            clips->x1, clips->y1,
5135                                            clips->x2 - clips->x1, clips->y2 - clips->y1,
5136                                            &flip_addrs->dirty_rect_count,
5137                                            false);
5138                 return;
5139         }
5140
5141         /*
5142          * MPO is requested. Add entire plane bounding box to dirty rects if
5143          * flipped to or damaged.
5144          *
5145          * If plane is moved or resized, also add old bounding box to dirty
5146          * rects.
5147          */
5148         fb_changed = old_plane_state->fb->base.id !=
5149                      new_plane_state->fb->base.id;
5150         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5151                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
5152                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
5153                       old_plane_state->crtc_h != new_plane_state->crtc_h);
5154
5155         drm_dbg(plane->dev,
5156                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5157                 new_plane_state->plane->base.id,
5158                 bb_changed, fb_changed, num_clips);
5159
5160         *dirty_regions_changed = bb_changed;
5161
5162         if (bb_changed) {
5163                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5164                                    new_plane_state->crtc_x,
5165                                    new_plane_state->crtc_y,
5166                                    new_plane_state->crtc_w,
5167                                    new_plane_state->crtc_h, &i, false);
5168
5169                 /* Add old plane bounding-box if plane is moved or resized */
5170                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5171                                    old_plane_state->crtc_x,
5172                                    old_plane_state->crtc_y,
5173                                    old_plane_state->crtc_w,
5174                                    old_plane_state->crtc_h, &i, false);
5175         }
5176
5177         if (num_clips) {
5178                 for (; i < num_clips; clips++)
5179                         fill_dc_dirty_rect(new_plane_state->plane,
5180                                            &dirty_rects[i], clips->x1,
5181                                            clips->y1, clips->x2 - clips->x1,
5182                                            clips->y2 - clips->y1, &i, false);
5183         } else if (fb_changed && !bb_changed) {
5184                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5185                                    new_plane_state->crtc_x,
5186                                    new_plane_state->crtc_y,
5187                                    new_plane_state->crtc_w,
5188                                    new_plane_state->crtc_h, &i, false);
5189         }
5190
5191         if (i > DC_MAX_DIRTY_RECTS)
5192                 goto ffu;
5193
5194         flip_addrs->dirty_rect_count = i;
5195         return;
5196
5197 ffu:
5198         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5199                            dm_crtc_state->base.mode.crtc_hdisplay,
5200                            dm_crtc_state->base.mode.crtc_vdisplay,
5201                            &flip_addrs->dirty_rect_count, true);
5202 }
5203
5204 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5205                                            const struct dm_connector_state *dm_state,
5206                                            struct dc_stream_state *stream)
5207 {
5208         enum amdgpu_rmx_type rmx_type;
5209
5210         struct rect src = { 0 }; /* viewport in composition space*/
5211         struct rect dst = { 0 }; /* stream addressable area */
5212
5213         /* no mode. nothing to be done */
5214         if (!mode)
5215                 return;
5216
5217         /* Full screen scaling by default */
5218         src.width = mode->hdisplay;
5219         src.height = mode->vdisplay;
5220         dst.width = stream->timing.h_addressable;
5221         dst.height = stream->timing.v_addressable;
5222
5223         if (dm_state) {
5224                 rmx_type = dm_state->scaling;
5225                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5226                         if (src.width * dst.height <
5227                                         src.height * dst.width) {
5228                                 /* height needs less upscaling/more downscaling */
5229                                 dst.width = src.width *
5230                                                 dst.height / src.height;
5231                         } else {
5232                                 /* width needs less upscaling/more downscaling */
5233                                 dst.height = src.height *
5234                                                 dst.width / src.width;
5235                         }
5236                 } else if (rmx_type == RMX_CENTER) {
5237                         dst = src;
5238                 }
5239
5240                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5241                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5242
5243                 if (dm_state->underscan_enable) {
5244                         dst.x += dm_state->underscan_hborder / 2;
5245                         dst.y += dm_state->underscan_vborder / 2;
5246                         dst.width -= dm_state->underscan_hborder;
5247                         dst.height -= dm_state->underscan_vborder;
5248                 }
5249         }
5250
5251         stream->src = src;
5252         stream->dst = dst;
5253
5254         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5255                       dst.x, dst.y, dst.width, dst.height);
5256
5257 }
5258
5259 static enum dc_color_depth
5260 convert_color_depth_from_display_info(const struct drm_connector *connector,
5261                                       bool is_y420, int requested_bpc)
5262 {
5263         u8 bpc;
5264
5265         if (is_y420) {
5266                 bpc = 8;
5267
5268                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5269                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5270                         bpc = 16;
5271                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5272                         bpc = 12;
5273                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5274                         bpc = 10;
5275         } else {
5276                 bpc = (uint8_t)connector->display_info.bpc;
5277                 /* Assume 8 bpc by default if no bpc is specified. */
5278                 bpc = bpc ? bpc : 8;
5279         }
5280
5281         if (requested_bpc > 0) {
5282                 /*
5283                  * Cap display bpc based on the user requested value.
5284                  *
5285                  * The value for state->max_bpc may not correctly updated
5286                  * depending on when the connector gets added to the state
5287                  * or if this was called outside of atomic check, so it
5288                  * can't be used directly.
5289                  */
5290                 bpc = min_t(u8, bpc, requested_bpc);
5291
5292                 /* Round down to the nearest even number. */
5293                 bpc = bpc - (bpc & 1);
5294         }
5295
5296         switch (bpc) {
5297         case 0:
5298                 /*
5299                  * Temporary Work around, DRM doesn't parse color depth for
5300                  * EDID revision before 1.4
5301                  * TODO: Fix edid parsing
5302                  */
5303                 return COLOR_DEPTH_888;
5304         case 6:
5305                 return COLOR_DEPTH_666;
5306         case 8:
5307                 return COLOR_DEPTH_888;
5308         case 10:
5309                 return COLOR_DEPTH_101010;
5310         case 12:
5311                 return COLOR_DEPTH_121212;
5312         case 14:
5313                 return COLOR_DEPTH_141414;
5314         case 16:
5315                 return COLOR_DEPTH_161616;
5316         default:
5317                 return COLOR_DEPTH_UNDEFINED;
5318         }
5319 }
5320
5321 static enum dc_aspect_ratio
5322 get_aspect_ratio(const struct drm_display_mode *mode_in)
5323 {
5324         /* 1-1 mapping, since both enums follow the HDMI spec. */
5325         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5326 }
5327
5328 static enum dc_color_space
5329 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5330 {
5331         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5332
5333         switch (dc_crtc_timing->pixel_encoding) {
5334         case PIXEL_ENCODING_YCBCR422:
5335         case PIXEL_ENCODING_YCBCR444:
5336         case PIXEL_ENCODING_YCBCR420:
5337         {
5338                 /*
5339                  * 27030khz is the separation point between HDTV and SDTV
5340                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5341                  * respectively
5342                  */
5343                 if (dc_crtc_timing->pix_clk_100hz > 270300) {
5344                         if (dc_crtc_timing->flags.Y_ONLY)
5345                                 color_space =
5346                                         COLOR_SPACE_YCBCR709_LIMITED;
5347                         else
5348                                 color_space = COLOR_SPACE_YCBCR709;
5349                 } else {
5350                         if (dc_crtc_timing->flags.Y_ONLY)
5351                                 color_space =
5352                                         COLOR_SPACE_YCBCR601_LIMITED;
5353                         else
5354                                 color_space = COLOR_SPACE_YCBCR601;
5355                 }
5356
5357         }
5358         break;
5359         case PIXEL_ENCODING_RGB:
5360                 color_space = COLOR_SPACE_SRGB;
5361                 break;
5362
5363         default:
5364                 WARN_ON(1);
5365                 break;
5366         }
5367
5368         return color_space;
5369 }
5370
5371 static bool adjust_colour_depth_from_display_info(
5372         struct dc_crtc_timing *timing_out,
5373         const struct drm_display_info *info)
5374 {
5375         enum dc_color_depth depth = timing_out->display_color_depth;
5376         int normalized_clk;
5377         do {
5378                 normalized_clk = timing_out->pix_clk_100hz / 10;
5379                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5380                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5381                         normalized_clk /= 2;
5382                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5383                 switch (depth) {
5384                 case COLOR_DEPTH_888:
5385                         break;
5386                 case COLOR_DEPTH_101010:
5387                         normalized_clk = (normalized_clk * 30) / 24;
5388                         break;
5389                 case COLOR_DEPTH_121212:
5390                         normalized_clk = (normalized_clk * 36) / 24;
5391                         break;
5392                 case COLOR_DEPTH_161616:
5393                         normalized_clk = (normalized_clk * 48) / 24;
5394                         break;
5395                 default:
5396                         /* The above depths are the only ones valid for HDMI. */
5397                         return false;
5398                 }
5399                 if (normalized_clk <= info->max_tmds_clock) {
5400                         timing_out->display_color_depth = depth;
5401                         return true;
5402                 }
5403         } while (--depth > COLOR_DEPTH_666);
5404         return false;
5405 }
5406
5407 static void fill_stream_properties_from_drm_display_mode(
5408         struct dc_stream_state *stream,
5409         const struct drm_display_mode *mode_in,
5410         const struct drm_connector *connector,
5411         const struct drm_connector_state *connector_state,
5412         const struct dc_stream_state *old_stream,
5413         int requested_bpc)
5414 {
5415         struct dc_crtc_timing *timing_out = &stream->timing;
5416         const struct drm_display_info *info = &connector->display_info;
5417         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5418         struct hdmi_vendor_infoframe hv_frame;
5419         struct hdmi_avi_infoframe avi_frame;
5420
5421         memset(&hv_frame, 0, sizeof(hv_frame));
5422         memset(&avi_frame, 0, sizeof(avi_frame));
5423
5424         timing_out->h_border_left = 0;
5425         timing_out->h_border_right = 0;
5426         timing_out->v_border_top = 0;
5427         timing_out->v_border_bottom = 0;
5428         /* TODO: un-hardcode */
5429         if (drm_mode_is_420_only(info, mode_in)
5430                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5431                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5432         else if (drm_mode_is_420_also(info, mode_in)
5433                         && aconnector->force_yuv420_output)
5434                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5435         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5436                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5437                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5438         else
5439                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5440
5441         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5442         timing_out->display_color_depth = convert_color_depth_from_display_info(
5443                 connector,
5444                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5445                 requested_bpc);
5446         timing_out->scan_type = SCANNING_TYPE_NODATA;
5447         timing_out->hdmi_vic = 0;
5448
5449         if (old_stream) {
5450                 timing_out->vic = old_stream->timing.vic;
5451                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5452                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5453         } else {
5454                 timing_out->vic = drm_match_cea_mode(mode_in);
5455                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5456                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5457                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5458                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5459         }
5460
5461         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5462                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5463                 timing_out->vic = avi_frame.video_code;
5464                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5465                 timing_out->hdmi_vic = hv_frame.vic;
5466         }
5467
5468         if (is_freesync_video_mode(mode_in, aconnector)) {
5469                 timing_out->h_addressable = mode_in->hdisplay;
5470                 timing_out->h_total = mode_in->htotal;
5471                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5472                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5473                 timing_out->v_total = mode_in->vtotal;
5474                 timing_out->v_addressable = mode_in->vdisplay;
5475                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5476                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5477                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5478         } else {
5479                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5480                 timing_out->h_total = mode_in->crtc_htotal;
5481                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5482                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5483                 timing_out->v_total = mode_in->crtc_vtotal;
5484                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5485                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5486                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5487                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5488         }
5489
5490         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5491
5492         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5493         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5494         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5495                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5496                     drm_mode_is_420_also(info, mode_in) &&
5497                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5498                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5499                         adjust_colour_depth_from_display_info(timing_out, info);
5500                 }
5501         }
5502
5503         stream->output_color_space = get_output_color_space(timing_out);
5504 }
5505
5506 static void fill_audio_info(struct audio_info *audio_info,
5507                             const struct drm_connector *drm_connector,
5508                             const struct dc_sink *dc_sink)
5509 {
5510         int i = 0;
5511         int cea_revision = 0;
5512         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5513
5514         audio_info->manufacture_id = edid_caps->manufacturer_id;
5515         audio_info->product_id = edid_caps->product_id;
5516
5517         cea_revision = drm_connector->display_info.cea_rev;
5518
5519         strscpy(audio_info->display_name,
5520                 edid_caps->display_name,
5521                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5522
5523         if (cea_revision >= 3) {
5524                 audio_info->mode_count = edid_caps->audio_mode_count;
5525
5526                 for (i = 0; i < audio_info->mode_count; ++i) {
5527                         audio_info->modes[i].format_code =
5528                                         (enum audio_format_code)
5529                                         (edid_caps->audio_modes[i].format_code);
5530                         audio_info->modes[i].channel_count =
5531                                         edid_caps->audio_modes[i].channel_count;
5532                         audio_info->modes[i].sample_rates.all =
5533                                         edid_caps->audio_modes[i].sample_rate;
5534                         audio_info->modes[i].sample_size =
5535                                         edid_caps->audio_modes[i].sample_size;
5536                 }
5537         }
5538
5539         audio_info->flags.all = edid_caps->speaker_flags;
5540
5541         /* TODO: We only check for the progressive mode, check for interlace mode too */
5542         if (drm_connector->latency_present[0]) {
5543                 audio_info->video_latency = drm_connector->video_latency[0];
5544                 audio_info->audio_latency = drm_connector->audio_latency[0];
5545         }
5546
5547         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5548
5549 }
5550
5551 static void
5552 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5553                                       struct drm_display_mode *dst_mode)
5554 {
5555         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5556         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5557         dst_mode->crtc_clock = src_mode->crtc_clock;
5558         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5559         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5560         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5561         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5562         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5563         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5564         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5565         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5566         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5567         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5568         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5569 }
5570
5571 static void
5572 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5573                                         const struct drm_display_mode *native_mode,
5574                                         bool scale_enabled)
5575 {
5576         if (scale_enabled) {
5577                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5578         } else if (native_mode->clock == drm_mode->clock &&
5579                         native_mode->htotal == drm_mode->htotal &&
5580                         native_mode->vtotal == drm_mode->vtotal) {
5581                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5582         } else {
5583                 /* no scaling nor amdgpu inserted, no need to patch */
5584         }
5585 }
5586
5587 static struct dc_sink *
5588 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5589 {
5590         struct dc_sink_init_data sink_init_data = { 0 };
5591         struct dc_sink *sink = NULL;
5592         sink_init_data.link = aconnector->dc_link;
5593         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5594
5595         sink = dc_sink_create(&sink_init_data);
5596         if (!sink) {
5597                 DRM_ERROR("Failed to create sink!\n");
5598                 return NULL;
5599         }
5600         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5601
5602         return sink;
5603 }
5604
5605 static void set_multisync_trigger_params(
5606                 struct dc_stream_state *stream)
5607 {
5608         struct dc_stream_state *master = NULL;
5609
5610         if (stream->triggered_crtc_reset.enabled) {
5611                 master = stream->triggered_crtc_reset.event_source;
5612                 stream->triggered_crtc_reset.event =
5613                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5614                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5615                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5616         }
5617 }
5618
5619 static void set_master_stream(struct dc_stream_state *stream_set[],
5620                               int stream_count)
5621 {
5622         int j, highest_rfr = 0, master_stream = 0;
5623
5624         for (j = 0;  j < stream_count; j++) {
5625                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5626                         int refresh_rate = 0;
5627
5628                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5629                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5630                         if (refresh_rate > highest_rfr) {
5631                                 highest_rfr = refresh_rate;
5632                                 master_stream = j;
5633                         }
5634                 }
5635         }
5636         for (j = 0;  j < stream_count; j++) {
5637                 if (stream_set[j])
5638                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5639         }
5640 }
5641
5642 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5643 {
5644         int i = 0;
5645         struct dc_stream_state *stream;
5646
5647         if (context->stream_count < 2)
5648                 return;
5649         for (i = 0; i < context->stream_count ; i++) {
5650                 if (!context->streams[i])
5651                         continue;
5652                 /*
5653                  * TODO: add a function to read AMD VSDB bits and set
5654                  * crtc_sync_master.multi_sync_enabled flag
5655                  * For now it's set to false
5656                  */
5657         }
5658
5659         set_master_stream(context->streams, context->stream_count);
5660
5661         for (i = 0; i < context->stream_count ; i++) {
5662                 stream = context->streams[i];
5663
5664                 if (!stream)
5665                         continue;
5666
5667                 set_multisync_trigger_params(stream);
5668         }
5669 }
5670
5671 /**
5672  * DOC: FreeSync Video
5673  *
5674  * When a userspace application wants to play a video, the content follows a
5675  * standard format definition that usually specifies the FPS for that format.
5676  * The below list illustrates some video format and the expected FPS,
5677  * respectively:
5678  *
5679  * - TV/NTSC (23.976 FPS)
5680  * - Cinema (24 FPS)
5681  * - TV/PAL (25 FPS)
5682  * - TV/NTSC (29.97 FPS)
5683  * - TV/NTSC (30 FPS)
5684  * - Cinema HFR (48 FPS)
5685  * - TV/PAL (50 FPS)
5686  * - Commonly used (60 FPS)
5687  * - Multiples of 24 (48,72,96 FPS)
5688  *
5689  * The list of standards video format is not huge and can be added to the
5690  * connector modeset list beforehand. With that, userspace can leverage
5691  * FreeSync to extends the front porch in order to attain the target refresh
5692  * rate. Such a switch will happen seamlessly, without screen blanking or
5693  * reprogramming of the output in any other way. If the userspace requests a
5694  * modesetting change compatible with FreeSync modes that only differ in the
5695  * refresh rate, DC will skip the full update and avoid blink during the
5696  * transition. For example, the video player can change the modesetting from
5697  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5698  * causing any display blink. This same concept can be applied to a mode
5699  * setting change.
5700  */
5701 static struct drm_display_mode *
5702 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5703                 bool use_probed_modes)
5704 {
5705         struct drm_display_mode *m, *m_pref = NULL;
5706         u16 current_refresh, highest_refresh;
5707         struct list_head *list_head = use_probed_modes ?
5708                 &aconnector->base.probed_modes :
5709                 &aconnector->base.modes;
5710
5711         if (aconnector->freesync_vid_base.clock != 0)
5712                 return &aconnector->freesync_vid_base;
5713
5714         /* Find the preferred mode */
5715         list_for_each_entry (m, list_head, head) {
5716                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5717                         m_pref = m;
5718                         break;
5719                 }
5720         }
5721
5722         if (!m_pref) {
5723                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5724                 m_pref = list_first_entry_or_null(
5725                                 &aconnector->base.modes, struct drm_display_mode, head);
5726                 if (!m_pref) {
5727                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5728                         return NULL;
5729                 }
5730         }
5731
5732         highest_refresh = drm_mode_vrefresh(m_pref);
5733
5734         /*
5735          * Find the mode with highest refresh rate with same resolution.
5736          * For some monitors, preferred mode is not the mode with highest
5737          * supported refresh rate.
5738          */
5739         list_for_each_entry (m, list_head, head) {
5740                 current_refresh  = drm_mode_vrefresh(m);
5741
5742                 if (m->hdisplay == m_pref->hdisplay &&
5743                     m->vdisplay == m_pref->vdisplay &&
5744                     highest_refresh < current_refresh) {
5745                         highest_refresh = current_refresh;
5746                         m_pref = m;
5747                 }
5748         }
5749
5750         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5751         return m_pref;
5752 }
5753
5754 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5755                 struct amdgpu_dm_connector *aconnector)
5756 {
5757         struct drm_display_mode *high_mode;
5758         int timing_diff;
5759
5760         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5761         if (!high_mode || !mode)
5762                 return false;
5763
5764         timing_diff = high_mode->vtotal - mode->vtotal;
5765
5766         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5767             high_mode->hdisplay != mode->hdisplay ||
5768             high_mode->vdisplay != mode->vdisplay ||
5769             high_mode->hsync_start != mode->hsync_start ||
5770             high_mode->hsync_end != mode->hsync_end ||
5771             high_mode->htotal != mode->htotal ||
5772             high_mode->hskew != mode->hskew ||
5773             high_mode->vscan != mode->vscan ||
5774             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5775             high_mode->vsync_end - mode->vsync_end != timing_diff)
5776                 return false;
5777         else
5778                 return true;
5779 }
5780
5781 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5782                             struct dc_sink *sink, struct dc_stream_state *stream,
5783                             struct dsc_dec_dpcd_caps *dsc_caps)
5784 {
5785         stream->timing.flags.DSC = 0;
5786         dsc_caps->is_dsc_supported = false;
5787
5788         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5789             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5790                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5791                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5792                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5793                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5794                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5795                                 dsc_caps);
5796         }
5797 }
5798
5799
5800 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5801                                     struct dc_sink *sink, struct dc_stream_state *stream,
5802                                     struct dsc_dec_dpcd_caps *dsc_caps,
5803                                     uint32_t max_dsc_target_bpp_limit_override)
5804 {
5805         const struct dc_link_settings *verified_link_cap = NULL;
5806         u32 link_bw_in_kbps;
5807         u32 edp_min_bpp_x16, edp_max_bpp_x16;
5808         struct dc *dc = sink->ctx->dc;
5809         struct dc_dsc_bw_range bw_range = {0};
5810         struct dc_dsc_config dsc_cfg = {0};
5811         struct dc_dsc_config_options dsc_options = {0};
5812
5813         dc_dsc_get_default_config_option(dc, &dsc_options);
5814         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5815
5816         verified_link_cap = dc_link_get_link_cap(stream->link);
5817         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5818         edp_min_bpp_x16 = 8 * 16;
5819         edp_max_bpp_x16 = 8 * 16;
5820
5821         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5822                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5823
5824         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5825                 edp_min_bpp_x16 = edp_max_bpp_x16;
5826
5827         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5828                                 dc->debug.dsc_min_slice_height_override,
5829                                 edp_min_bpp_x16, edp_max_bpp_x16,
5830                                 dsc_caps,
5831                                 &stream->timing,
5832                                 &bw_range)) {
5833
5834                 if (bw_range.max_kbps < link_bw_in_kbps) {
5835                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5836                                         dsc_caps,
5837                                         &dsc_options,
5838                                         0,
5839                                         &stream->timing,
5840                                         &dsc_cfg)) {
5841                                 stream->timing.dsc_cfg = dsc_cfg;
5842                                 stream->timing.flags.DSC = 1;
5843                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5844                         }
5845                         return;
5846                 }
5847         }
5848
5849         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5850                                 dsc_caps,
5851                                 &dsc_options,
5852                                 link_bw_in_kbps,
5853                                 &stream->timing,
5854                                 &dsc_cfg)) {
5855                 stream->timing.dsc_cfg = dsc_cfg;
5856                 stream->timing.flags.DSC = 1;
5857         }
5858 }
5859
5860
5861 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5862                                         struct dc_sink *sink, struct dc_stream_state *stream,
5863                                         struct dsc_dec_dpcd_caps *dsc_caps)
5864 {
5865         struct drm_connector *drm_connector = &aconnector->base;
5866         u32 link_bandwidth_kbps;
5867         struct dc *dc = sink->ctx->dc;
5868         u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5869         u32 dsc_max_supported_bw_in_kbps;
5870         u32 max_dsc_target_bpp_limit_override =
5871                 drm_connector->display_info.max_dsc_bpp;
5872         struct dc_dsc_config_options dsc_options = {0};
5873
5874         dc_dsc_get_default_config_option(dc, &dsc_options);
5875         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5876
5877         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5878                                                         dc_link_get_link_cap(aconnector->dc_link));
5879
5880         /* Set DSC policy according to dsc_clock_en */
5881         dc_dsc_policy_set_enable_dsc_when_not_needed(
5882                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5883
5884         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5885             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5886             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5887
5888                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5889
5890         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5891                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5892                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5893                                                 dsc_caps,
5894                                                 &dsc_options,
5895                                                 link_bandwidth_kbps,
5896                                                 &stream->timing,
5897                                                 &stream->timing.dsc_cfg)) {
5898                                 stream->timing.flags.DSC = 1;
5899                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5900                         }
5901                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5902                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5903                         max_supported_bw_in_kbps = link_bandwidth_kbps;
5904                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5905
5906                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5907                                         max_supported_bw_in_kbps > 0 &&
5908                                         dsc_max_supported_bw_in_kbps > 0)
5909                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5910                                                 dsc_caps,
5911                                                 &dsc_options,
5912                                                 dsc_max_supported_bw_in_kbps,
5913                                                 &stream->timing,
5914                                                 &stream->timing.dsc_cfg)) {
5915                                         stream->timing.flags.DSC = 1;
5916                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5917                                                                          __func__, drm_connector->name);
5918                                 }
5919                 }
5920         }
5921
5922         /* Overwrite the stream flag if DSC is enabled through debugfs */
5923         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5924                 stream->timing.flags.DSC = 1;
5925
5926         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5927                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5928
5929         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5930                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5931
5932         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5933                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5934 }
5935
5936 static struct dc_stream_state *
5937 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5938                        const struct drm_display_mode *drm_mode,
5939                        const struct dm_connector_state *dm_state,
5940                        const struct dc_stream_state *old_stream,
5941                        int requested_bpc)
5942 {
5943         struct drm_display_mode *preferred_mode = NULL;
5944         struct drm_connector *drm_connector;
5945         const struct drm_connector_state *con_state =
5946                 dm_state ? &dm_state->base : NULL;
5947         struct dc_stream_state *stream = NULL;
5948         struct drm_display_mode mode;
5949         struct drm_display_mode saved_mode;
5950         struct drm_display_mode *freesync_mode = NULL;
5951         bool native_mode_found = false;
5952         bool recalculate_timing = false;
5953         bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5954         int mode_refresh;
5955         int preferred_refresh = 0;
5956         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
5957         struct dsc_dec_dpcd_caps dsc_caps;
5958
5959         struct dc_sink *sink = NULL;
5960
5961         drm_mode_init(&mode, drm_mode);
5962         memset(&saved_mode, 0, sizeof(saved_mode));
5963
5964         if (aconnector == NULL) {
5965                 DRM_ERROR("aconnector is NULL!\n");
5966                 return stream;
5967         }
5968
5969         drm_connector = &aconnector->base;
5970
5971         if (!aconnector->dc_sink) {
5972                 sink = create_fake_sink(aconnector);
5973                 if (!sink)
5974                         return stream;
5975         } else {
5976                 sink = aconnector->dc_sink;
5977                 dc_sink_retain(sink);
5978         }
5979
5980         stream = dc_create_stream_for_sink(sink);
5981
5982         if (stream == NULL) {
5983                 DRM_ERROR("Failed to create stream for sink!\n");
5984                 goto finish;
5985         }
5986
5987         stream->dm_stream_context = aconnector;
5988
5989         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5990                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5991
5992         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5993                 /* Search for preferred mode */
5994                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
5995                         native_mode_found = true;
5996                         break;
5997                 }
5998         }
5999         if (!native_mode_found)
6000                 preferred_mode = list_first_entry_or_null(
6001                                 &aconnector->base.modes,
6002                                 struct drm_display_mode,
6003                                 head);
6004
6005         mode_refresh = drm_mode_vrefresh(&mode);
6006
6007         if (preferred_mode == NULL) {
6008                 /*
6009                  * This may not be an error, the use case is when we have no
6010                  * usermode calls to reset and set mode upon hotplug. In this
6011                  * case, we call set mode ourselves to restore the previous mode
6012                  * and the modelist may not be filled in in time.
6013                  */
6014                 DRM_DEBUG_DRIVER("No preferred mode found\n");
6015         } else {
6016                 recalculate_timing = amdgpu_freesync_vid_mode &&
6017                                  is_freesync_video_mode(&mode, aconnector);
6018                 if (recalculate_timing) {
6019                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6020                         drm_mode_copy(&saved_mode, &mode);
6021                         drm_mode_copy(&mode, freesync_mode);
6022                 } else {
6023                         decide_crtc_timing_for_drm_display_mode(
6024                                         &mode, preferred_mode, scale);
6025
6026                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
6027                 }
6028         }
6029
6030         if (recalculate_timing)
6031                 drm_mode_set_crtcinfo(&saved_mode, 0);
6032         else if (!dm_state)
6033                 drm_mode_set_crtcinfo(&mode, 0);
6034
6035         /*
6036         * If scaling is enabled and refresh rate didn't change
6037         * we copy the vic and polarities of the old timings
6038         */
6039         if (!scale || mode_refresh != preferred_refresh)
6040                 fill_stream_properties_from_drm_display_mode(
6041                         stream, &mode, &aconnector->base, con_state, NULL,
6042                         requested_bpc);
6043         else
6044                 fill_stream_properties_from_drm_display_mode(
6045                         stream, &mode, &aconnector->base, con_state, old_stream,
6046                         requested_bpc);
6047
6048         if (aconnector->timing_changed) {
6049                 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",
6050                                 __func__,
6051                                 stream->timing.display_color_depth,
6052                                 aconnector->timing_requested->display_color_depth);
6053                 stream->timing = *aconnector->timing_requested;
6054         }
6055
6056         /* SST DSC determination policy */
6057         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6058         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6059                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6060
6061         update_stream_scaling_settings(&mode, dm_state, stream);
6062
6063         fill_audio_info(
6064                 &stream->audio_info,
6065                 drm_connector,
6066                 sink);
6067
6068         update_stream_signal(stream, sink);
6069
6070         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6071                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6072
6073         if (stream->link->psr_settings.psr_feature_enabled) {
6074                 //
6075                 // should decide stream support vsc sdp colorimetry capability
6076                 // before building vsc info packet
6077                 //
6078                 stream->use_vsc_sdp_for_colorimetry = false;
6079                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6080                         stream->use_vsc_sdp_for_colorimetry =
6081                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6082                 } else {
6083                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6084                                 stream->use_vsc_sdp_for_colorimetry = true;
6085                 }
6086                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6087                         tf = TRANSFER_FUNC_GAMMA_22;
6088                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6089                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6090
6091         }
6092 finish:
6093         dc_sink_release(sink);
6094
6095         return stream;
6096 }
6097
6098 static enum drm_connector_status
6099 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6100 {
6101         bool connected;
6102         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6103
6104         /*
6105          * Notes:
6106          * 1. This interface is NOT called in context of HPD irq.
6107          * 2. This interface *is called* in context of user-mode ioctl. Which
6108          * makes it a bad place for *any* MST-related activity.
6109          */
6110
6111         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6112             !aconnector->fake_enable)
6113                 connected = (aconnector->dc_sink != NULL);
6114         else
6115                 connected = (aconnector->base.force == DRM_FORCE_ON ||
6116                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6117
6118         update_subconnector_property(aconnector);
6119
6120         return (connected ? connector_status_connected :
6121                         connector_status_disconnected);
6122 }
6123
6124 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6125                                             struct drm_connector_state *connector_state,
6126                                             struct drm_property *property,
6127                                             uint64_t val)
6128 {
6129         struct drm_device *dev = connector->dev;
6130         struct amdgpu_device *adev = drm_to_adev(dev);
6131         struct dm_connector_state *dm_old_state =
6132                 to_dm_connector_state(connector->state);
6133         struct dm_connector_state *dm_new_state =
6134                 to_dm_connector_state(connector_state);
6135
6136         int ret = -EINVAL;
6137
6138         if (property == dev->mode_config.scaling_mode_property) {
6139                 enum amdgpu_rmx_type rmx_type;
6140
6141                 switch (val) {
6142                 case DRM_MODE_SCALE_CENTER:
6143                         rmx_type = RMX_CENTER;
6144                         break;
6145                 case DRM_MODE_SCALE_ASPECT:
6146                         rmx_type = RMX_ASPECT;
6147                         break;
6148                 case DRM_MODE_SCALE_FULLSCREEN:
6149                         rmx_type = RMX_FULL;
6150                         break;
6151                 case DRM_MODE_SCALE_NONE:
6152                 default:
6153                         rmx_type = RMX_OFF;
6154                         break;
6155                 }
6156
6157                 if (dm_old_state->scaling == rmx_type)
6158                         return 0;
6159
6160                 dm_new_state->scaling = rmx_type;
6161                 ret = 0;
6162         } else if (property == adev->mode_info.underscan_hborder_property) {
6163                 dm_new_state->underscan_hborder = val;
6164                 ret = 0;
6165         } else if (property == adev->mode_info.underscan_vborder_property) {
6166                 dm_new_state->underscan_vborder = val;
6167                 ret = 0;
6168         } else if (property == adev->mode_info.underscan_property) {
6169                 dm_new_state->underscan_enable = val;
6170                 ret = 0;
6171         } else if (property == adev->mode_info.abm_level_property) {
6172                 dm_new_state->abm_level = val;
6173                 ret = 0;
6174         }
6175
6176         return ret;
6177 }
6178
6179 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6180                                             const struct drm_connector_state *state,
6181                                             struct drm_property *property,
6182                                             uint64_t *val)
6183 {
6184         struct drm_device *dev = connector->dev;
6185         struct amdgpu_device *adev = drm_to_adev(dev);
6186         struct dm_connector_state *dm_state =
6187                 to_dm_connector_state(state);
6188         int ret = -EINVAL;
6189
6190         if (property == dev->mode_config.scaling_mode_property) {
6191                 switch (dm_state->scaling) {
6192                 case RMX_CENTER:
6193                         *val = DRM_MODE_SCALE_CENTER;
6194                         break;
6195                 case RMX_ASPECT:
6196                         *val = DRM_MODE_SCALE_ASPECT;
6197                         break;
6198                 case RMX_FULL:
6199                         *val = DRM_MODE_SCALE_FULLSCREEN;
6200                         break;
6201                 case RMX_OFF:
6202                 default:
6203                         *val = DRM_MODE_SCALE_NONE;
6204                         break;
6205                 }
6206                 ret = 0;
6207         } else if (property == adev->mode_info.underscan_hborder_property) {
6208                 *val = dm_state->underscan_hborder;
6209                 ret = 0;
6210         } else if (property == adev->mode_info.underscan_vborder_property) {
6211                 *val = dm_state->underscan_vborder;
6212                 ret = 0;
6213         } else if (property == adev->mode_info.underscan_property) {
6214                 *val = dm_state->underscan_enable;
6215                 ret = 0;
6216         } else if (property == adev->mode_info.abm_level_property) {
6217                 *val = dm_state->abm_level;
6218                 ret = 0;
6219         }
6220
6221         return ret;
6222 }
6223
6224 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6225 {
6226         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6227
6228         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6229 }
6230
6231 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6232 {
6233         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6234         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6235         struct amdgpu_display_manager *dm = &adev->dm;
6236
6237         /*
6238          * Call only if mst_mgr was initialized before since it's not done
6239          * for all connector types.
6240          */
6241         if (aconnector->mst_mgr.dev)
6242                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6243
6244         if (aconnector->bl_idx != -1) {
6245                 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6246                 dm->backlight_dev[aconnector->bl_idx] = NULL;
6247         }
6248
6249         if (aconnector->dc_em_sink)
6250                 dc_sink_release(aconnector->dc_em_sink);
6251         aconnector->dc_em_sink = NULL;
6252         if (aconnector->dc_sink)
6253                 dc_sink_release(aconnector->dc_sink);
6254         aconnector->dc_sink = NULL;
6255
6256         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6257         drm_connector_unregister(connector);
6258         drm_connector_cleanup(connector);
6259         if (aconnector->i2c) {
6260                 i2c_del_adapter(&aconnector->i2c->base);
6261                 kfree(aconnector->i2c);
6262         }
6263         kfree(aconnector->dm_dp_aux.aux.name);
6264
6265         kfree(connector);
6266 }
6267
6268 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6269 {
6270         struct dm_connector_state *state =
6271                 to_dm_connector_state(connector->state);
6272
6273         if (connector->state)
6274                 __drm_atomic_helper_connector_destroy_state(connector->state);
6275
6276         kfree(state);
6277
6278         state = kzalloc(sizeof(*state), GFP_KERNEL);
6279
6280         if (state) {
6281                 state->scaling = RMX_OFF;
6282                 state->underscan_enable = false;
6283                 state->underscan_hborder = 0;
6284                 state->underscan_vborder = 0;
6285                 state->base.max_requested_bpc = 8;
6286                 state->vcpi_slots = 0;
6287                 state->pbn = 0;
6288
6289                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6290                         state->abm_level = amdgpu_dm_abm_level;
6291
6292                 __drm_atomic_helper_connector_reset(connector, &state->base);
6293         }
6294 }
6295
6296 struct drm_connector_state *
6297 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6298 {
6299         struct dm_connector_state *state =
6300                 to_dm_connector_state(connector->state);
6301
6302         struct dm_connector_state *new_state =
6303                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6304
6305         if (!new_state)
6306                 return NULL;
6307
6308         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6309
6310         new_state->freesync_capable = state->freesync_capable;
6311         new_state->abm_level = state->abm_level;
6312         new_state->scaling = state->scaling;
6313         new_state->underscan_enable = state->underscan_enable;
6314         new_state->underscan_hborder = state->underscan_hborder;
6315         new_state->underscan_vborder = state->underscan_vborder;
6316         new_state->vcpi_slots = state->vcpi_slots;
6317         new_state->pbn = state->pbn;
6318         return &new_state->base;
6319 }
6320
6321 static int
6322 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6323 {
6324         struct amdgpu_dm_connector *amdgpu_dm_connector =
6325                 to_amdgpu_dm_connector(connector);
6326         int r;
6327
6328         amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6329
6330         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6331             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6332                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6333                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6334                 if (r)
6335                         return r;
6336         }
6337
6338 #if defined(CONFIG_DEBUG_FS)
6339         connector_debugfs_init(amdgpu_dm_connector);
6340 #endif
6341
6342         return 0;
6343 }
6344
6345 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6346         .reset = amdgpu_dm_connector_funcs_reset,
6347         .detect = amdgpu_dm_connector_detect,
6348         .fill_modes = drm_helper_probe_single_connector_modes,
6349         .destroy = amdgpu_dm_connector_destroy,
6350         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6351         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6352         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6353         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6354         .late_register = amdgpu_dm_connector_late_register,
6355         .early_unregister = amdgpu_dm_connector_unregister
6356 };
6357
6358 static int get_modes(struct drm_connector *connector)
6359 {
6360         return amdgpu_dm_connector_get_modes(connector);
6361 }
6362
6363 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6364 {
6365         struct dc_sink_init_data init_params = {
6366                         .link = aconnector->dc_link,
6367                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6368         };
6369         struct edid *edid;
6370
6371         if (!aconnector->base.edid_blob_ptr) {
6372                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6373                                 aconnector->base.name);
6374
6375                 aconnector->base.force = DRM_FORCE_OFF;
6376                 return;
6377         }
6378
6379         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6380
6381         aconnector->edid = edid;
6382
6383         aconnector->dc_em_sink = dc_link_add_remote_sink(
6384                 aconnector->dc_link,
6385                 (uint8_t *)edid,
6386                 (edid->extensions + 1) * EDID_LENGTH,
6387                 &init_params);
6388
6389         if (aconnector->base.force == DRM_FORCE_ON) {
6390                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6391                 aconnector->dc_link->local_sink :
6392                 aconnector->dc_em_sink;
6393                 dc_sink_retain(aconnector->dc_sink);
6394         }
6395 }
6396
6397 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6398 {
6399         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6400
6401         /*
6402          * In case of headless boot with force on for DP managed connector
6403          * Those settings have to be != 0 to get initial modeset
6404          */
6405         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6406                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6407                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6408         }
6409
6410         create_eml_sink(aconnector);
6411 }
6412
6413 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6414                                                 struct dc_stream_state *stream)
6415 {
6416         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6417         struct dc_plane_state *dc_plane_state = NULL;
6418         struct dc_state *dc_state = NULL;
6419
6420         if (!stream)
6421                 goto cleanup;
6422
6423         dc_plane_state = dc_create_plane_state(dc);
6424         if (!dc_plane_state)
6425                 goto cleanup;
6426
6427         dc_state = dc_create_state(dc);
6428         if (!dc_state)
6429                 goto cleanup;
6430
6431         /* populate stream to plane */
6432         dc_plane_state->src_rect.height  = stream->src.height;
6433         dc_plane_state->src_rect.width   = stream->src.width;
6434         dc_plane_state->dst_rect.height  = stream->src.height;
6435         dc_plane_state->dst_rect.width   = stream->src.width;
6436         dc_plane_state->clip_rect.height = stream->src.height;
6437         dc_plane_state->clip_rect.width  = stream->src.width;
6438         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6439         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6440         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6441         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6442         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6443         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6444         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6445         dc_plane_state->rotation = ROTATION_ANGLE_0;
6446         dc_plane_state->is_tiling_rotated = false;
6447         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6448
6449         dc_result = dc_validate_stream(dc, stream);
6450         if (dc_result == DC_OK)
6451                 dc_result = dc_validate_plane(dc, dc_plane_state);
6452
6453         if (dc_result == DC_OK)
6454                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6455
6456         if (dc_result == DC_OK && !dc_add_plane_to_context(
6457                                                 dc,
6458                                                 stream,
6459                                                 dc_plane_state,
6460                                                 dc_state))
6461                 dc_result = DC_FAIL_ATTACH_SURFACES;
6462
6463         if (dc_result == DC_OK)
6464                 dc_result = dc_validate_global_state(dc, dc_state, true);
6465
6466 cleanup:
6467         if (dc_state)
6468                 dc_release_state(dc_state);
6469
6470         if (dc_plane_state)
6471                 dc_plane_state_release(dc_plane_state);
6472
6473         return dc_result;
6474 }
6475
6476 struct dc_stream_state *
6477 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6478                                 const struct drm_display_mode *drm_mode,
6479                                 const struct dm_connector_state *dm_state,
6480                                 const struct dc_stream_state *old_stream)
6481 {
6482         struct drm_connector *connector = &aconnector->base;
6483         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6484         struct dc_stream_state *stream;
6485         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6486         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6487         enum dc_status dc_result = DC_OK;
6488
6489         do {
6490                 stream = create_stream_for_sink(aconnector, drm_mode,
6491                                                 dm_state, old_stream,
6492                                                 requested_bpc);
6493                 if (stream == NULL) {
6494                         DRM_ERROR("Failed to create stream for sink!\n");
6495                         break;
6496                 }
6497
6498                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6499                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6500                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6501
6502                 if (dc_result == DC_OK)
6503                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6504
6505                 if (dc_result != DC_OK) {
6506                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6507                                       drm_mode->hdisplay,
6508                                       drm_mode->vdisplay,
6509                                       drm_mode->clock,
6510                                       dc_result,
6511                                       dc_status_to_str(dc_result));
6512
6513                         dc_stream_release(stream);
6514                         stream = NULL;
6515                         requested_bpc -= 2; /* lower bpc to retry validation */
6516                 }
6517
6518         } while (stream == NULL && requested_bpc >= 6);
6519
6520         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6521                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6522
6523                 aconnector->force_yuv420_output = true;
6524                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6525                                                 dm_state, old_stream);
6526                 aconnector->force_yuv420_output = false;
6527         }
6528
6529         return stream;
6530 }
6531
6532 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6533                                    struct drm_display_mode *mode)
6534 {
6535         int result = MODE_ERROR;
6536         struct dc_sink *dc_sink;
6537         /* TODO: Unhardcode stream count */
6538         struct dc_stream_state *stream;
6539         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6540
6541         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6542                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6543                 return result;
6544
6545         /*
6546          * Only run this the first time mode_valid is called to initilialize
6547          * EDID mgmt
6548          */
6549         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6550                 !aconnector->dc_em_sink)
6551                 handle_edid_mgmt(aconnector);
6552
6553         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6554
6555         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6556                                 aconnector->base.force != DRM_FORCE_ON) {
6557                 DRM_ERROR("dc_sink is NULL!\n");
6558                 goto fail;
6559         }
6560
6561         stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6562         if (stream) {
6563                 dc_stream_release(stream);
6564                 result = MODE_OK;
6565         }
6566
6567 fail:
6568         /* TODO: error handling*/
6569         return result;
6570 }
6571
6572 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6573                                 struct dc_info_packet *out)
6574 {
6575         struct hdmi_drm_infoframe frame;
6576         unsigned char buf[30]; /* 26 + 4 */
6577         ssize_t len;
6578         int ret, i;
6579
6580         memset(out, 0, sizeof(*out));
6581
6582         if (!state->hdr_output_metadata)
6583                 return 0;
6584
6585         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6586         if (ret)
6587                 return ret;
6588
6589         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6590         if (len < 0)
6591                 return (int)len;
6592
6593         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6594         if (len != 30)
6595                 return -EINVAL;
6596
6597         /* Prepare the infopacket for DC. */
6598         switch (state->connector->connector_type) {
6599         case DRM_MODE_CONNECTOR_HDMIA:
6600                 out->hb0 = 0x87; /* type */
6601                 out->hb1 = 0x01; /* version */
6602                 out->hb2 = 0x1A; /* length */
6603                 out->sb[0] = buf[3]; /* checksum */
6604                 i = 1;
6605                 break;
6606
6607         case DRM_MODE_CONNECTOR_DisplayPort:
6608         case DRM_MODE_CONNECTOR_eDP:
6609                 out->hb0 = 0x00; /* sdp id, zero */
6610                 out->hb1 = 0x87; /* type */
6611                 out->hb2 = 0x1D; /* payload len - 1 */
6612                 out->hb3 = (0x13 << 2); /* sdp version */
6613                 out->sb[0] = 0x01; /* version */
6614                 out->sb[1] = 0x1A; /* length */
6615                 i = 2;
6616                 break;
6617
6618         default:
6619                 return -EINVAL;
6620         }
6621
6622         memcpy(&out->sb[i], &buf[4], 26);
6623         out->valid = true;
6624
6625         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6626                        sizeof(out->sb), false);
6627
6628         return 0;
6629 }
6630
6631 static int
6632 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6633                                  struct drm_atomic_state *state)
6634 {
6635         struct drm_connector_state *new_con_state =
6636                 drm_atomic_get_new_connector_state(state, conn);
6637         struct drm_connector_state *old_con_state =
6638                 drm_atomic_get_old_connector_state(state, conn);
6639         struct drm_crtc *crtc = new_con_state->crtc;
6640         struct drm_crtc_state *new_crtc_state;
6641         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6642         int ret;
6643
6644         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6645
6646         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6647                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6648                 if (ret < 0)
6649                         return ret;
6650         }
6651
6652         if (!crtc)
6653                 return 0;
6654
6655         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6656                 struct dc_info_packet hdr_infopacket;
6657
6658                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6659                 if (ret)
6660                         return ret;
6661
6662                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6663                 if (IS_ERR(new_crtc_state))
6664                         return PTR_ERR(new_crtc_state);
6665
6666                 /*
6667                  * DC considers the stream backends changed if the
6668                  * static metadata changes. Forcing the modeset also
6669                  * gives a simple way for userspace to switch from
6670                  * 8bpc to 10bpc when setting the metadata to enter
6671                  * or exit HDR.
6672                  *
6673                  * Changing the static metadata after it's been
6674                  * set is permissible, however. So only force a
6675                  * modeset if we're entering or exiting HDR.
6676                  */
6677                 new_crtc_state->mode_changed =
6678                         !old_con_state->hdr_output_metadata ||
6679                         !new_con_state->hdr_output_metadata;
6680         }
6681
6682         return 0;
6683 }
6684
6685 static const struct drm_connector_helper_funcs
6686 amdgpu_dm_connector_helper_funcs = {
6687         /*
6688          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6689          * modes will be filtered by drm_mode_validate_size(), and those modes
6690          * are missing after user start lightdm. So we need to renew modes list.
6691          * in get_modes call back, not just return the modes count
6692          */
6693         .get_modes = get_modes,
6694         .mode_valid = amdgpu_dm_connector_mode_valid,
6695         .atomic_check = amdgpu_dm_connector_atomic_check,
6696 };
6697
6698 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6699 {
6700
6701 }
6702
6703 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6704 {
6705         switch (display_color_depth) {
6706         case COLOR_DEPTH_666:
6707                 return 6;
6708         case COLOR_DEPTH_888:
6709                 return 8;
6710         case COLOR_DEPTH_101010:
6711                 return 10;
6712         case COLOR_DEPTH_121212:
6713                 return 12;
6714         case COLOR_DEPTH_141414:
6715                 return 14;
6716         case COLOR_DEPTH_161616:
6717                 return 16;
6718         default:
6719                 break;
6720         }
6721         return 0;
6722 }
6723
6724 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6725                                           struct drm_crtc_state *crtc_state,
6726                                           struct drm_connector_state *conn_state)
6727 {
6728         struct drm_atomic_state *state = crtc_state->state;
6729         struct drm_connector *connector = conn_state->connector;
6730         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6731         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6732         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6733         struct drm_dp_mst_topology_mgr *mst_mgr;
6734         struct drm_dp_mst_port *mst_port;
6735         struct drm_dp_mst_topology_state *mst_state;
6736         enum dc_color_depth color_depth;
6737         int clock, bpp = 0;
6738         bool is_y420 = false;
6739
6740         if (!aconnector->mst_output_port || !aconnector->dc_sink)
6741                 return 0;
6742
6743         mst_port = aconnector->mst_output_port;
6744         mst_mgr = &aconnector->mst_root->mst_mgr;
6745
6746         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6747                 return 0;
6748
6749         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6750         if (IS_ERR(mst_state))
6751                 return PTR_ERR(mst_state);
6752
6753         if (!mst_state->pbn_div)
6754                 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6755
6756         if (!state->duplicated) {
6757                 int max_bpc = conn_state->max_requested_bpc;
6758                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6759                           aconnector->force_yuv420_output;
6760                 color_depth = convert_color_depth_from_display_info(connector,
6761                                                                     is_y420,
6762                                                                     max_bpc);
6763                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6764                 clock = adjusted_mode->clock;
6765                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6766         }
6767
6768         dm_new_connector_state->vcpi_slots =
6769                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6770                                               dm_new_connector_state->pbn);
6771         if (dm_new_connector_state->vcpi_slots < 0) {
6772                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6773                 return dm_new_connector_state->vcpi_slots;
6774         }
6775         return 0;
6776 }
6777
6778 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6779         .disable = dm_encoder_helper_disable,
6780         .atomic_check = dm_encoder_helper_atomic_check
6781 };
6782
6783 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6784                                             struct dc_state *dc_state,
6785                                             struct dsc_mst_fairness_vars *vars)
6786 {
6787         struct dc_stream_state *stream = NULL;
6788         struct drm_connector *connector;
6789         struct drm_connector_state *new_con_state;
6790         struct amdgpu_dm_connector *aconnector;
6791         struct dm_connector_state *dm_conn_state;
6792         int i, j, ret;
6793         int vcpi, pbn_div, pbn, slot_num = 0;
6794
6795         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6796
6797                 aconnector = to_amdgpu_dm_connector(connector);
6798
6799                 if (!aconnector->mst_output_port)
6800                         continue;
6801
6802                 if (!new_con_state || !new_con_state->crtc)
6803                         continue;
6804
6805                 dm_conn_state = to_dm_connector_state(new_con_state);
6806
6807                 for (j = 0; j < dc_state->stream_count; j++) {
6808                         stream = dc_state->streams[j];
6809                         if (!stream)
6810                                 continue;
6811
6812                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6813                                 break;
6814
6815                         stream = NULL;
6816                 }
6817
6818                 if (!stream)
6819                         continue;
6820
6821                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6822                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6823                 for (j = 0; j < dc_state->stream_count; j++) {
6824                         if (vars[j].aconnector == aconnector) {
6825                                 pbn = vars[j].pbn;
6826                                 break;
6827                         }
6828                 }
6829
6830                 if (j == dc_state->stream_count)
6831                         continue;
6832
6833                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6834
6835                 if (stream->timing.flags.DSC != 1) {
6836                         dm_conn_state->pbn = pbn;
6837                         dm_conn_state->vcpi_slots = slot_num;
6838
6839                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6840                                                            dm_conn_state->pbn, false);
6841                         if (ret < 0)
6842                                 return ret;
6843
6844                         continue;
6845                 }
6846
6847                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
6848                 if (vcpi < 0)
6849                         return vcpi;
6850
6851                 dm_conn_state->pbn = pbn;
6852                 dm_conn_state->vcpi_slots = vcpi;
6853         }
6854         return 0;
6855 }
6856
6857 static int to_drm_connector_type(enum signal_type st)
6858 {
6859         switch (st) {
6860         case SIGNAL_TYPE_HDMI_TYPE_A:
6861                 return DRM_MODE_CONNECTOR_HDMIA;
6862         case SIGNAL_TYPE_EDP:
6863                 return DRM_MODE_CONNECTOR_eDP;
6864         case SIGNAL_TYPE_LVDS:
6865                 return DRM_MODE_CONNECTOR_LVDS;
6866         case SIGNAL_TYPE_RGB:
6867                 return DRM_MODE_CONNECTOR_VGA;
6868         case SIGNAL_TYPE_DISPLAY_PORT:
6869         case SIGNAL_TYPE_DISPLAY_PORT_MST:
6870                 return DRM_MODE_CONNECTOR_DisplayPort;
6871         case SIGNAL_TYPE_DVI_DUAL_LINK:
6872         case SIGNAL_TYPE_DVI_SINGLE_LINK:
6873                 return DRM_MODE_CONNECTOR_DVID;
6874         case SIGNAL_TYPE_VIRTUAL:
6875                 return DRM_MODE_CONNECTOR_VIRTUAL;
6876
6877         default:
6878                 return DRM_MODE_CONNECTOR_Unknown;
6879         }
6880 }
6881
6882 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6883 {
6884         struct drm_encoder *encoder;
6885
6886         /* There is only one encoder per connector */
6887         drm_connector_for_each_possible_encoder(connector, encoder)
6888                 return encoder;
6889
6890         return NULL;
6891 }
6892
6893 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6894 {
6895         struct drm_encoder *encoder;
6896         struct amdgpu_encoder *amdgpu_encoder;
6897
6898         encoder = amdgpu_dm_connector_to_encoder(connector);
6899
6900         if (encoder == NULL)
6901                 return;
6902
6903         amdgpu_encoder = to_amdgpu_encoder(encoder);
6904
6905         amdgpu_encoder->native_mode.clock = 0;
6906
6907         if (!list_empty(&connector->probed_modes)) {
6908                 struct drm_display_mode *preferred_mode = NULL;
6909
6910                 list_for_each_entry(preferred_mode,
6911                                     &connector->probed_modes,
6912                                     head) {
6913                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6914                                 amdgpu_encoder->native_mode = *preferred_mode;
6915
6916                         break;
6917                 }
6918
6919         }
6920 }
6921
6922 static struct drm_display_mode *
6923 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6924                              char *name,
6925                              int hdisplay, int vdisplay)
6926 {
6927         struct drm_device *dev = encoder->dev;
6928         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6929         struct drm_display_mode *mode = NULL;
6930         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6931
6932         mode = drm_mode_duplicate(dev, native_mode);
6933
6934         if (mode == NULL)
6935                 return NULL;
6936
6937         mode->hdisplay = hdisplay;
6938         mode->vdisplay = vdisplay;
6939         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6940         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6941
6942         return mode;
6943
6944 }
6945
6946 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6947                                                  struct drm_connector *connector)
6948 {
6949         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6950         struct drm_display_mode *mode = NULL;
6951         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6952         struct amdgpu_dm_connector *amdgpu_dm_connector =
6953                                 to_amdgpu_dm_connector(connector);
6954         int i;
6955         int n;
6956         struct mode_size {
6957                 char name[DRM_DISPLAY_MODE_LEN];
6958                 int w;
6959                 int h;
6960         } common_modes[] = {
6961                 {  "640x480",  640,  480},
6962                 {  "800x600",  800,  600},
6963                 { "1024x768", 1024,  768},
6964                 { "1280x720", 1280,  720},
6965                 { "1280x800", 1280,  800},
6966                 {"1280x1024", 1280, 1024},
6967                 { "1440x900", 1440,  900},
6968                 {"1680x1050", 1680, 1050},
6969                 {"1600x1200", 1600, 1200},
6970                 {"1920x1080", 1920, 1080},
6971                 {"1920x1200", 1920, 1200}
6972         };
6973
6974         n = ARRAY_SIZE(common_modes);
6975
6976         for (i = 0; i < n; i++) {
6977                 struct drm_display_mode *curmode = NULL;
6978                 bool mode_existed = false;
6979
6980                 if (common_modes[i].w > native_mode->hdisplay ||
6981                     common_modes[i].h > native_mode->vdisplay ||
6982                    (common_modes[i].w == native_mode->hdisplay &&
6983                     common_modes[i].h == native_mode->vdisplay))
6984                         continue;
6985
6986                 list_for_each_entry(curmode, &connector->probed_modes, head) {
6987                         if (common_modes[i].w == curmode->hdisplay &&
6988                             common_modes[i].h == curmode->vdisplay) {
6989                                 mode_existed = true;
6990                                 break;
6991                         }
6992                 }
6993
6994                 if (mode_existed)
6995                         continue;
6996
6997                 mode = amdgpu_dm_create_common_mode(encoder,
6998                                 common_modes[i].name, common_modes[i].w,
6999                                 common_modes[i].h);
7000                 if (!mode)
7001                         continue;
7002
7003                 drm_mode_probed_add(connector, mode);
7004                 amdgpu_dm_connector->num_modes++;
7005         }
7006 }
7007
7008 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7009 {
7010         struct drm_encoder *encoder;
7011         struct amdgpu_encoder *amdgpu_encoder;
7012         const struct drm_display_mode *native_mode;
7013
7014         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7015             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7016                 return;
7017
7018         mutex_lock(&connector->dev->mode_config.mutex);
7019         amdgpu_dm_connector_get_modes(connector);
7020         mutex_unlock(&connector->dev->mode_config.mutex);
7021
7022         encoder = amdgpu_dm_connector_to_encoder(connector);
7023         if (!encoder)
7024                 return;
7025
7026         amdgpu_encoder = to_amdgpu_encoder(encoder);
7027
7028         native_mode = &amdgpu_encoder->native_mode;
7029         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7030                 return;
7031
7032         drm_connector_set_panel_orientation_with_quirk(connector,
7033                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7034                                                        native_mode->hdisplay,
7035                                                        native_mode->vdisplay);
7036 }
7037
7038 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7039                                               struct edid *edid)
7040 {
7041         struct amdgpu_dm_connector *amdgpu_dm_connector =
7042                         to_amdgpu_dm_connector(connector);
7043
7044         if (edid) {
7045                 /* empty probed_modes */
7046                 INIT_LIST_HEAD(&connector->probed_modes);
7047                 amdgpu_dm_connector->num_modes =
7048                                 drm_add_edid_modes(connector, edid);
7049
7050                 /* sorting the probed modes before calling function
7051                  * amdgpu_dm_get_native_mode() since EDID can have
7052                  * more than one preferred mode. The modes that are
7053                  * later in the probed mode list could be of higher
7054                  * and preferred resolution. For example, 3840x2160
7055                  * resolution in base EDID preferred timing and 4096x2160
7056                  * preferred resolution in DID extension block later.
7057                  */
7058                 drm_mode_sort(&connector->probed_modes);
7059                 amdgpu_dm_get_native_mode(connector);
7060
7061                 /* Freesync capabilities are reset by calling
7062                  * drm_add_edid_modes() and need to be
7063                  * restored here.
7064                  */
7065                 amdgpu_dm_update_freesync_caps(connector, edid);
7066         } else {
7067                 amdgpu_dm_connector->num_modes = 0;
7068         }
7069 }
7070
7071 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7072                               struct drm_display_mode *mode)
7073 {
7074         struct drm_display_mode *m;
7075
7076         list_for_each_entry (m, &aconnector->base.probed_modes, head) {
7077                 if (drm_mode_equal(m, mode))
7078                         return true;
7079         }
7080
7081         return false;
7082 }
7083
7084 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7085 {
7086         const struct drm_display_mode *m;
7087         struct drm_display_mode *new_mode;
7088         uint i;
7089         u32 new_modes_count = 0;
7090
7091         /* Standard FPS values
7092          *
7093          * 23.976       - TV/NTSC
7094          * 24           - Cinema
7095          * 25           - TV/PAL
7096          * 29.97        - TV/NTSC
7097          * 30           - TV/NTSC
7098          * 48           - Cinema HFR
7099          * 50           - TV/PAL
7100          * 60           - Commonly used
7101          * 48,72,96,120 - Multiples of 24
7102          */
7103         static const u32 common_rates[] = {
7104                 23976, 24000, 25000, 29970, 30000,
7105                 48000, 50000, 60000, 72000, 96000, 120000
7106         };
7107
7108         /*
7109          * Find mode with highest refresh rate with the same resolution
7110          * as the preferred mode. Some monitors report a preferred mode
7111          * with lower resolution than the highest refresh rate supported.
7112          */
7113
7114         m = get_highest_refresh_rate_mode(aconnector, true);
7115         if (!m)
7116                 return 0;
7117
7118         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7119                 u64 target_vtotal, target_vtotal_diff;
7120                 u64 num, den;
7121
7122                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7123                         continue;
7124
7125                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7126                     common_rates[i] > aconnector->max_vfreq * 1000)
7127                         continue;
7128
7129                 num = (unsigned long long)m->clock * 1000 * 1000;
7130                 den = common_rates[i] * (unsigned long long)m->htotal;
7131                 target_vtotal = div_u64(num, den);
7132                 target_vtotal_diff = target_vtotal - m->vtotal;
7133
7134                 /* Check for illegal modes */
7135                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7136                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7137                     m->vtotal + target_vtotal_diff < m->vsync_end)
7138                         continue;
7139
7140                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7141                 if (!new_mode)
7142                         goto out;
7143
7144                 new_mode->vtotal += (u16)target_vtotal_diff;
7145                 new_mode->vsync_start += (u16)target_vtotal_diff;
7146                 new_mode->vsync_end += (u16)target_vtotal_diff;
7147                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7148                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7149
7150                 if (!is_duplicate_mode(aconnector, new_mode)) {
7151                         drm_mode_probed_add(&aconnector->base, new_mode);
7152                         new_modes_count += 1;
7153                 } else
7154                         drm_mode_destroy(aconnector->base.dev, new_mode);
7155         }
7156  out:
7157         return new_modes_count;
7158 }
7159
7160 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7161                                                    struct edid *edid)
7162 {
7163         struct amdgpu_dm_connector *amdgpu_dm_connector =
7164                 to_amdgpu_dm_connector(connector);
7165
7166         if (!(amdgpu_freesync_vid_mode && edid))
7167                 return;
7168
7169         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7170                 amdgpu_dm_connector->num_modes +=
7171                         add_fs_modes(amdgpu_dm_connector);
7172 }
7173
7174 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7175 {
7176         struct amdgpu_dm_connector *amdgpu_dm_connector =
7177                         to_amdgpu_dm_connector(connector);
7178         struct drm_encoder *encoder;
7179         struct edid *edid = amdgpu_dm_connector->edid;
7180         struct dc_link_settings *verified_link_cap =
7181                         &amdgpu_dm_connector->dc_link->verified_link_cap;
7182         const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7183
7184         encoder = amdgpu_dm_connector_to_encoder(connector);
7185
7186         if (!drm_edid_is_valid(edid)) {
7187                 amdgpu_dm_connector->num_modes =
7188                                 drm_add_modes_noedid(connector, 640, 480);
7189                 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7190                         amdgpu_dm_connector->num_modes +=
7191                                 drm_add_modes_noedid(connector, 1920, 1080);
7192         } else {
7193                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7194                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7195                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7196         }
7197         amdgpu_dm_fbc_init(connector);
7198
7199         return amdgpu_dm_connector->num_modes;
7200 }
7201
7202 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7203                                      struct amdgpu_dm_connector *aconnector,
7204                                      int connector_type,
7205                                      struct dc_link *link,
7206                                      int link_index)
7207 {
7208         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7209
7210         /*
7211          * Some of the properties below require access to state, like bpc.
7212          * Allocate some default initial connector state with our reset helper.
7213          */
7214         if (aconnector->base.funcs->reset)
7215                 aconnector->base.funcs->reset(&aconnector->base);
7216
7217         aconnector->connector_id = link_index;
7218         aconnector->bl_idx = -1;
7219         aconnector->dc_link = link;
7220         aconnector->base.interlace_allowed = false;
7221         aconnector->base.doublescan_allowed = false;
7222         aconnector->base.stereo_allowed = false;
7223         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7224         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7225         aconnector->audio_inst = -1;
7226         aconnector->pack_sdp_v1_3 = false;
7227         aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7228         memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7229         mutex_init(&aconnector->hpd_lock);
7230
7231         /*
7232          * configure support HPD hot plug connector_>polled default value is 0
7233          * which means HPD hot plug not supported
7234          */
7235         switch (connector_type) {
7236         case DRM_MODE_CONNECTOR_HDMIA:
7237                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7238                 aconnector->base.ycbcr_420_allowed =
7239                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7240                 break;
7241         case DRM_MODE_CONNECTOR_DisplayPort:
7242                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7243                 link->link_enc = link_enc_cfg_get_link_enc(link);
7244                 ASSERT(link->link_enc);
7245                 if (link->link_enc)
7246                         aconnector->base.ycbcr_420_allowed =
7247                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7248                 break;
7249         case DRM_MODE_CONNECTOR_DVID:
7250                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7251                 break;
7252         default:
7253                 break;
7254         }
7255
7256         drm_object_attach_property(&aconnector->base.base,
7257                                 dm->ddev->mode_config.scaling_mode_property,
7258                                 DRM_MODE_SCALE_NONE);
7259
7260         drm_object_attach_property(&aconnector->base.base,
7261                                 adev->mode_info.underscan_property,
7262                                 UNDERSCAN_OFF);
7263         drm_object_attach_property(&aconnector->base.base,
7264                                 adev->mode_info.underscan_hborder_property,
7265                                 0);
7266         drm_object_attach_property(&aconnector->base.base,
7267                                 adev->mode_info.underscan_vborder_property,
7268                                 0);
7269
7270         if (!aconnector->mst_root)
7271                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7272
7273         aconnector->base.state->max_bpc = 16;
7274         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7275
7276         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7277             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7278                 drm_object_attach_property(&aconnector->base.base,
7279                                 adev->mode_info.abm_level_property, 0);
7280         }
7281
7282         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7283             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7284             connector_type == DRM_MODE_CONNECTOR_eDP) {
7285                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7286
7287                 if (!aconnector->mst_root)
7288                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7289
7290                 if (adev->dm.hdcp_workqueue)
7291                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7292         }
7293 }
7294
7295 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7296                               struct i2c_msg *msgs, int num)
7297 {
7298         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7299         struct ddc_service *ddc_service = i2c->ddc_service;
7300         struct i2c_command cmd;
7301         int i;
7302         int result = -EIO;
7303
7304         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7305
7306         if (!cmd.payloads)
7307                 return result;
7308
7309         cmd.number_of_payloads = num;
7310         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7311         cmd.speed = 100;
7312
7313         for (i = 0; i < num; i++) {
7314                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7315                 cmd.payloads[i].address = msgs[i].addr;
7316                 cmd.payloads[i].length = msgs[i].len;
7317                 cmd.payloads[i].data = msgs[i].buf;
7318         }
7319
7320         if (dc_submit_i2c(
7321                         ddc_service->ctx->dc,
7322                         ddc_service->link->link_index,
7323                         &cmd))
7324                 result = num;
7325
7326         kfree(cmd.payloads);
7327         return result;
7328 }
7329
7330 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7331 {
7332         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7333 }
7334
7335 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7336         .master_xfer = amdgpu_dm_i2c_xfer,
7337         .functionality = amdgpu_dm_i2c_func,
7338 };
7339
7340 static struct amdgpu_i2c_adapter *
7341 create_i2c(struct ddc_service *ddc_service,
7342            int link_index,
7343            int *res)
7344 {
7345         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7346         struct amdgpu_i2c_adapter *i2c;
7347
7348         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7349         if (!i2c)
7350                 return NULL;
7351         i2c->base.owner = THIS_MODULE;
7352         i2c->base.class = I2C_CLASS_DDC;
7353         i2c->base.dev.parent = &adev->pdev->dev;
7354         i2c->base.algo = &amdgpu_dm_i2c_algo;
7355         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7356         i2c_set_adapdata(&i2c->base, i2c);
7357         i2c->ddc_service = ddc_service;
7358
7359         return i2c;
7360 }
7361
7362
7363 /*
7364  * Note: this function assumes that dc_link_detect() was called for the
7365  * dc_link which will be represented by this aconnector.
7366  */
7367 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7368                                     struct amdgpu_dm_connector *aconnector,
7369                                     u32 link_index,
7370                                     struct amdgpu_encoder *aencoder)
7371 {
7372         int res = 0;
7373         int connector_type;
7374         struct dc *dc = dm->dc;
7375         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7376         struct amdgpu_i2c_adapter *i2c;
7377
7378         link->priv = aconnector;
7379
7380         DRM_DEBUG_DRIVER("%s()\n", __func__);
7381
7382         i2c = create_i2c(link->ddc, link->link_index, &res);
7383         if (!i2c) {
7384                 DRM_ERROR("Failed to create i2c adapter data\n");
7385                 return -ENOMEM;
7386         }
7387
7388         aconnector->i2c = i2c;
7389         res = i2c_add_adapter(&i2c->base);
7390
7391         if (res) {
7392                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7393                 goto out_free;
7394         }
7395
7396         connector_type = to_drm_connector_type(link->connector_signal);
7397
7398         res = drm_connector_init_with_ddc(
7399                         dm->ddev,
7400                         &aconnector->base,
7401                         &amdgpu_dm_connector_funcs,
7402                         connector_type,
7403                         &i2c->base);
7404
7405         if (res) {
7406                 DRM_ERROR("connector_init failed\n");
7407                 aconnector->connector_id = -1;
7408                 goto out_free;
7409         }
7410
7411         drm_connector_helper_add(
7412                         &aconnector->base,
7413                         &amdgpu_dm_connector_helper_funcs);
7414
7415         amdgpu_dm_connector_init_helper(
7416                 dm,
7417                 aconnector,
7418                 connector_type,
7419                 link,
7420                 link_index);
7421
7422         drm_connector_attach_encoder(
7423                 &aconnector->base, &aencoder->base);
7424
7425         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7426                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7427                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7428
7429 out_free:
7430         if (res) {
7431                 kfree(i2c);
7432                 aconnector->i2c = NULL;
7433         }
7434         return res;
7435 }
7436
7437 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7438 {
7439         switch (adev->mode_info.num_crtc) {
7440         case 1:
7441                 return 0x1;
7442         case 2:
7443                 return 0x3;
7444         case 3:
7445                 return 0x7;
7446         case 4:
7447                 return 0xf;
7448         case 5:
7449                 return 0x1f;
7450         case 6:
7451         default:
7452                 return 0x3f;
7453         }
7454 }
7455
7456 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7457                                   struct amdgpu_encoder *aencoder,
7458                                   uint32_t link_index)
7459 {
7460         struct amdgpu_device *adev = drm_to_adev(dev);
7461
7462         int res = drm_encoder_init(dev,
7463                                    &aencoder->base,
7464                                    &amdgpu_dm_encoder_funcs,
7465                                    DRM_MODE_ENCODER_TMDS,
7466                                    NULL);
7467
7468         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7469
7470         if (!res)
7471                 aencoder->encoder_id = link_index;
7472         else
7473                 aencoder->encoder_id = -1;
7474
7475         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7476
7477         return res;
7478 }
7479
7480 static void manage_dm_interrupts(struct amdgpu_device *adev,
7481                                  struct amdgpu_crtc *acrtc,
7482                                  bool enable)
7483 {
7484         /*
7485          * We have no guarantee that the frontend index maps to the same
7486          * backend index - some even map to more than one.
7487          *
7488          * TODO: Use a different interrupt or check DC itself for the mapping.
7489          */
7490         int irq_type =
7491                 amdgpu_display_crtc_idx_to_irq_type(
7492                         adev,
7493                         acrtc->crtc_id);
7494
7495         if (enable) {
7496                 drm_crtc_vblank_on(&acrtc->base);
7497                 amdgpu_irq_get(
7498                         adev,
7499                         &adev->pageflip_irq,
7500                         irq_type);
7501 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7502                 amdgpu_irq_get(
7503                         adev,
7504                         &adev->vline0_irq,
7505                         irq_type);
7506 #endif
7507         } else {
7508 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7509                 amdgpu_irq_put(
7510                         adev,
7511                         &adev->vline0_irq,
7512                         irq_type);
7513 #endif
7514                 amdgpu_irq_put(
7515                         adev,
7516                         &adev->pageflip_irq,
7517                         irq_type);
7518                 drm_crtc_vblank_off(&acrtc->base);
7519         }
7520 }
7521
7522 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7523                                       struct amdgpu_crtc *acrtc)
7524 {
7525         int irq_type =
7526                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7527
7528         /**
7529          * This reads the current state for the IRQ and force reapplies
7530          * the setting to hardware.
7531          */
7532         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7533 }
7534
7535 static bool
7536 is_scaling_state_different(const struct dm_connector_state *dm_state,
7537                            const struct dm_connector_state *old_dm_state)
7538 {
7539         if (dm_state->scaling != old_dm_state->scaling)
7540                 return true;
7541         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7542                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7543                         return true;
7544         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7545                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7546                         return true;
7547         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7548                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7549                 return true;
7550         return false;
7551 }
7552
7553 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7554                                             struct drm_crtc_state *old_crtc_state,
7555                                             struct drm_connector_state *new_conn_state,
7556                                             struct drm_connector_state *old_conn_state,
7557                                             const struct drm_connector *connector,
7558                                             struct hdcp_workqueue *hdcp_w)
7559 {
7560         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7561         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7562
7563         pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7564                 connector->index, connector->status, connector->dpms);
7565         pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7566                 old_conn_state->content_protection, new_conn_state->content_protection);
7567
7568         if (old_crtc_state)
7569                 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7570                 old_crtc_state->enable,
7571                 old_crtc_state->active,
7572                 old_crtc_state->mode_changed,
7573                 old_crtc_state->active_changed,
7574                 old_crtc_state->connectors_changed);
7575
7576         if (new_crtc_state)
7577                 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7578                 new_crtc_state->enable,
7579                 new_crtc_state->active,
7580                 new_crtc_state->mode_changed,
7581                 new_crtc_state->active_changed,
7582                 new_crtc_state->connectors_changed);
7583
7584         /* hdcp content type change */
7585         if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7586             new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7587                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7588                 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7589                 return true;
7590         }
7591
7592         /* CP is being re enabled, ignore this */
7593         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7594             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7595                 if (new_crtc_state && new_crtc_state->mode_changed) {
7596                         new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7597                         pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7598                         return true;
7599                 }
7600                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7601                 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7602                 return false;
7603         }
7604
7605         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7606          *
7607          * Handles:     UNDESIRED -> ENABLED
7608          */
7609         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7610             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7611                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7612
7613         /* Stream removed and re-enabled
7614          *
7615          * Can sometimes overlap with the HPD case,
7616          * thus set update_hdcp to false to avoid
7617          * setting HDCP multiple times.
7618          *
7619          * Handles:     DESIRED -> DESIRED (Special case)
7620          */
7621         if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7622                 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7623                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7624                 dm_con_state->update_hdcp = false;
7625                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7626                         __func__);
7627                 return true;
7628         }
7629
7630         /* Hot-plug, headless s3, dpms
7631          *
7632          * Only start HDCP if the display is connected/enabled.
7633          * update_hdcp flag will be set to false until the next
7634          * HPD comes in.
7635          *
7636          * Handles:     DESIRED -> DESIRED (Special case)
7637          */
7638         if (dm_con_state->update_hdcp &&
7639         new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7640         connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7641                 dm_con_state->update_hdcp = false;
7642                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7643                         __func__);
7644                 return true;
7645         }
7646
7647         if (old_conn_state->content_protection == new_conn_state->content_protection) {
7648                 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7649                         if (new_crtc_state && new_crtc_state->mode_changed) {
7650                                 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7651                                         __func__);
7652                                 return true;
7653                         }
7654                         pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7655                                 __func__);
7656                         return false;
7657                 }
7658
7659                 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7660                 return false;
7661         }
7662
7663         if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7664                 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7665                         __func__);
7666                 return true;
7667         }
7668
7669         pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7670         return false;
7671 }
7672
7673 static void remove_stream(struct amdgpu_device *adev,
7674                           struct amdgpu_crtc *acrtc,
7675                           struct dc_stream_state *stream)
7676 {
7677         /* this is the update mode case */
7678
7679         acrtc->otg_inst = -1;
7680         acrtc->enabled = false;
7681 }
7682
7683 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7684 {
7685
7686         assert_spin_locked(&acrtc->base.dev->event_lock);
7687         WARN_ON(acrtc->event);
7688
7689         acrtc->event = acrtc->base.state->event;
7690
7691         /* Set the flip status */
7692         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7693
7694         /* Mark this event as consumed */
7695         acrtc->base.state->event = NULL;
7696
7697         DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7698                      acrtc->crtc_id);
7699 }
7700
7701 static void update_freesync_state_on_stream(
7702         struct amdgpu_display_manager *dm,
7703         struct dm_crtc_state *new_crtc_state,
7704         struct dc_stream_state *new_stream,
7705         struct dc_plane_state *surface,
7706         u32 flip_timestamp_in_us)
7707 {
7708         struct mod_vrr_params vrr_params;
7709         struct dc_info_packet vrr_infopacket = {0};
7710         struct amdgpu_device *adev = dm->adev;
7711         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7712         unsigned long flags;
7713         bool pack_sdp_v1_3 = false;
7714         struct amdgpu_dm_connector *aconn;
7715         enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7716
7717         if (!new_stream)
7718                 return;
7719
7720         /*
7721          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7722          * For now it's sufficient to just guard against these conditions.
7723          */
7724
7725         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7726                 return;
7727
7728         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7729         vrr_params = acrtc->dm_irq_params.vrr_params;
7730
7731         if (surface) {
7732                 mod_freesync_handle_preflip(
7733                         dm->freesync_module,
7734                         surface,
7735                         new_stream,
7736                         flip_timestamp_in_us,
7737                         &vrr_params);
7738
7739                 if (adev->family < AMDGPU_FAMILY_AI &&
7740                     amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7741                         mod_freesync_handle_v_update(dm->freesync_module,
7742                                                      new_stream, &vrr_params);
7743
7744                         /* Need to call this before the frame ends. */
7745                         dc_stream_adjust_vmin_vmax(dm->dc,
7746                                                    new_crtc_state->stream,
7747                                                    &vrr_params.adjust);
7748                 }
7749         }
7750
7751         aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7752
7753         if (aconn && aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
7754                 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7755
7756                 if (aconn->vsdb_info.amd_vsdb_version == 1)
7757                         packet_type = PACKET_TYPE_FS_V1;
7758                 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7759                         packet_type = PACKET_TYPE_FS_V2;
7760                 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7761                         packet_type = PACKET_TYPE_FS_V3;
7762
7763                 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7764                                         &new_stream->adaptive_sync_infopacket);
7765         }
7766
7767         mod_freesync_build_vrr_infopacket(
7768                 dm->freesync_module,
7769                 new_stream,
7770                 &vrr_params,
7771                 packet_type,
7772                 TRANSFER_FUNC_UNKNOWN,
7773                 &vrr_infopacket,
7774                 pack_sdp_v1_3);
7775
7776         new_crtc_state->freesync_vrr_info_changed |=
7777                 (memcmp(&new_crtc_state->vrr_infopacket,
7778                         &vrr_infopacket,
7779                         sizeof(vrr_infopacket)) != 0);
7780
7781         acrtc->dm_irq_params.vrr_params = vrr_params;
7782         new_crtc_state->vrr_infopacket = vrr_infopacket;
7783
7784         new_stream->vrr_infopacket = vrr_infopacket;
7785         new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7786
7787         if (new_crtc_state->freesync_vrr_info_changed)
7788                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7789                               new_crtc_state->base.crtc->base.id,
7790                               (int)new_crtc_state->base.vrr_enabled,
7791                               (int)vrr_params.state);
7792
7793         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7794 }
7795
7796 static void update_stream_irq_parameters(
7797         struct amdgpu_display_manager *dm,
7798         struct dm_crtc_state *new_crtc_state)
7799 {
7800         struct dc_stream_state *new_stream = new_crtc_state->stream;
7801         struct mod_vrr_params vrr_params;
7802         struct mod_freesync_config config = new_crtc_state->freesync_config;
7803         struct amdgpu_device *adev = dm->adev;
7804         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7805         unsigned long flags;
7806
7807         if (!new_stream)
7808                 return;
7809
7810         /*
7811          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7812          * For now it's sufficient to just guard against these conditions.
7813          */
7814         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7815                 return;
7816
7817         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7818         vrr_params = acrtc->dm_irq_params.vrr_params;
7819
7820         if (new_crtc_state->vrr_supported &&
7821             config.min_refresh_in_uhz &&
7822             config.max_refresh_in_uhz) {
7823                 /*
7824                  * if freesync compatible mode was set, config.state will be set
7825                  * in atomic check
7826                  */
7827                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7828                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7829                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7830                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7831                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7832                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7833                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7834                 } else {
7835                         config.state = new_crtc_state->base.vrr_enabled ?
7836                                                      VRR_STATE_ACTIVE_VARIABLE :
7837                                                      VRR_STATE_INACTIVE;
7838                 }
7839         } else {
7840                 config.state = VRR_STATE_UNSUPPORTED;
7841         }
7842
7843         mod_freesync_build_vrr_params(dm->freesync_module,
7844                                       new_stream,
7845                                       &config, &vrr_params);
7846
7847         new_crtc_state->freesync_config = config;
7848         /* Copy state for access from DM IRQ handler */
7849         acrtc->dm_irq_params.freesync_config = config;
7850         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7851         acrtc->dm_irq_params.vrr_params = vrr_params;
7852         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7853 }
7854
7855 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7856                                             struct dm_crtc_state *new_state)
7857 {
7858         bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
7859         bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
7860
7861         if (!old_vrr_active && new_vrr_active) {
7862                 /* Transition VRR inactive -> active:
7863                  * While VRR is active, we must not disable vblank irq, as a
7864                  * reenable after disable would compute bogus vblank/pflip
7865                  * timestamps if it likely happened inside display front-porch.
7866                  *
7867                  * We also need vupdate irq for the actual core vblank handling
7868                  * at end of vblank.
7869                  */
7870                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
7871                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
7872                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7873                                  __func__, new_state->base.crtc->base.id);
7874         } else if (old_vrr_active && !new_vrr_active) {
7875                 /* Transition VRR active -> inactive:
7876                  * Allow vblank irq disable again for fixed refresh rate.
7877                  */
7878                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
7879                 drm_crtc_vblank_put(new_state->base.crtc);
7880                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7881                                  __func__, new_state->base.crtc->base.id);
7882         }
7883 }
7884
7885 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7886 {
7887         struct drm_plane *plane;
7888         struct drm_plane_state *old_plane_state;
7889         int i;
7890
7891         /*
7892          * TODO: Make this per-stream so we don't issue redundant updates for
7893          * commits with multiple streams.
7894          */
7895         for_each_old_plane_in_state(state, plane, old_plane_state, i)
7896                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7897                         amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
7898 }
7899
7900 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
7901 {
7902         struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
7903
7904         return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
7905 }
7906
7907 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7908                                     struct dc_state *dc_state,
7909                                     struct drm_device *dev,
7910                                     struct amdgpu_display_manager *dm,
7911                                     struct drm_crtc *pcrtc,
7912                                     bool wait_for_vblank)
7913 {
7914         u32 i;
7915         u64 timestamp_ns = ktime_get_ns();
7916         struct drm_plane *plane;
7917         struct drm_plane_state *old_plane_state, *new_plane_state;
7918         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
7919         struct drm_crtc_state *new_pcrtc_state =
7920                         drm_atomic_get_new_crtc_state(state, pcrtc);
7921         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
7922         struct dm_crtc_state *dm_old_crtc_state =
7923                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
7924         int planes_count = 0, vpos, hpos;
7925         unsigned long flags;
7926         u32 target_vblank, last_flip_vblank;
7927         bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
7928         bool cursor_update = false;
7929         bool pflip_present = false;
7930         bool dirty_rects_changed = false;
7931         struct {
7932                 struct dc_surface_update surface_updates[MAX_SURFACES];
7933                 struct dc_plane_info plane_infos[MAX_SURFACES];
7934                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
7935                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7936                 struct dc_stream_update stream_update;
7937         } *bundle;
7938
7939         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7940
7941         if (!bundle) {
7942                 dm_error("Failed to allocate update bundle\n");
7943                 goto cleanup;
7944         }
7945
7946         /*
7947          * Disable the cursor first if we're disabling all the planes.
7948          * It'll remain on the screen after the planes are re-enabled
7949          * if we don't.
7950          */
7951         if (acrtc_state->active_planes == 0)
7952                 amdgpu_dm_commit_cursors(state);
7953
7954         /* update planes when needed */
7955         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7956                 struct drm_crtc *crtc = new_plane_state->crtc;
7957                 struct drm_crtc_state *new_crtc_state;
7958                 struct drm_framebuffer *fb = new_plane_state->fb;
7959                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
7960                 bool plane_needs_flip;
7961                 struct dc_plane_state *dc_plane;
7962                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
7963
7964                 /* Cursor plane is handled after stream updates */
7965                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
7966                         if ((fb && crtc == pcrtc) ||
7967                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
7968                                 cursor_update = true;
7969
7970                         continue;
7971                 }
7972
7973                 if (!fb || !crtc || pcrtc != crtc)
7974                         continue;
7975
7976                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
7977                 if (!new_crtc_state->active)
7978                         continue;
7979
7980                 dc_plane = dm_new_plane_state->dc_state;
7981                 if (!dc_plane)
7982                         continue;
7983
7984                 bundle->surface_updates[planes_count].surface = dc_plane;
7985                 if (new_pcrtc_state->color_mgmt_changed) {
7986                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
7987                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
7988                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
7989                 }
7990
7991                 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
7992                                      &bundle->scaling_infos[planes_count]);
7993
7994                 bundle->surface_updates[planes_count].scaling_info =
7995                         &bundle->scaling_infos[planes_count];
7996
7997                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
7998
7999                 pflip_present = pflip_present || plane_needs_flip;
8000
8001                 if (!plane_needs_flip) {
8002                         planes_count += 1;
8003                         continue;
8004                 }
8005
8006                 fill_dc_plane_info_and_addr(
8007                         dm->adev, new_plane_state,
8008                         afb->tiling_flags,
8009                         &bundle->plane_infos[planes_count],
8010                         &bundle->flip_addrs[planes_count].address,
8011                         afb->tmz_surface, false);
8012
8013                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8014                                  new_plane_state->plane->index,
8015                                  bundle->plane_infos[planes_count].dcc.enable);
8016
8017                 bundle->surface_updates[planes_count].plane_info =
8018                         &bundle->plane_infos[planes_count];
8019
8020                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8021                         fill_dc_dirty_rects(plane, old_plane_state,
8022                                             new_plane_state, new_crtc_state,
8023                                             &bundle->flip_addrs[planes_count],
8024                                             &dirty_rects_changed);
8025
8026                         /*
8027                          * If the dirty regions changed, PSR-SU need to be disabled temporarily
8028                          * and enabled it again after dirty regions are stable to avoid video glitch.
8029                          * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8030                          * during the PSR-SU was disabled.
8031                          */
8032                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8033                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8034 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8035                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8036 #endif
8037                             dirty_rects_changed) {
8038                                 mutex_lock(&dm->dc_lock);
8039                                 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8040                                 timestamp_ns;
8041                                 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8042                                         amdgpu_dm_psr_disable(acrtc_state->stream);
8043                                 mutex_unlock(&dm->dc_lock);
8044                         }
8045                 }
8046
8047                 /*
8048                  * Only allow immediate flips for fast updates that don't
8049                  * change memory domain, FB pitch, DCC state, rotation or
8050                  * mirroring.
8051                  */
8052                 bundle->flip_addrs[planes_count].flip_immediate =
8053                         crtc->state->async_flip &&
8054                         acrtc_state->update_type == UPDATE_TYPE_FAST &&
8055                         get_mem_type(old_plane_state->fb) == get_mem_type(fb);
8056
8057                 timestamp_ns = ktime_get_ns();
8058                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8059                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8060                 bundle->surface_updates[planes_count].surface = dc_plane;
8061
8062                 if (!bundle->surface_updates[planes_count].surface) {
8063                         DRM_ERROR("No surface for CRTC: id=%d\n",
8064                                         acrtc_attach->crtc_id);
8065                         continue;
8066                 }
8067
8068                 if (plane == pcrtc->primary)
8069                         update_freesync_state_on_stream(
8070                                 dm,
8071                                 acrtc_state,
8072                                 acrtc_state->stream,
8073                                 dc_plane,
8074                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8075
8076                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8077                                  __func__,
8078                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8079                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8080
8081                 planes_count += 1;
8082
8083         }
8084
8085         if (pflip_present) {
8086                 if (!vrr_active) {
8087                         /* Use old throttling in non-vrr fixed refresh rate mode
8088                          * to keep flip scheduling based on target vblank counts
8089                          * working in a backwards compatible way, e.g., for
8090                          * clients using the GLX_OML_sync_control extension or
8091                          * DRI3/Present extension with defined target_msc.
8092                          */
8093                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8094                 }
8095                 else {
8096                         /* For variable refresh rate mode only:
8097                          * Get vblank of last completed flip to avoid > 1 vrr
8098                          * flips per video frame by use of throttling, but allow
8099                          * flip programming anywhere in the possibly large
8100                          * variable vrr vblank interval for fine-grained flip
8101                          * timing control and more opportunity to avoid stutter
8102                          * on late submission of flips.
8103                          */
8104                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8105                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8106                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8107                 }
8108
8109                 target_vblank = last_flip_vblank + wait_for_vblank;
8110
8111                 /*
8112                  * Wait until we're out of the vertical blank period before the one
8113                  * targeted by the flip
8114                  */
8115                 while ((acrtc_attach->enabled &&
8116                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8117                                                             0, &vpos, &hpos, NULL,
8118                                                             NULL, &pcrtc->hwmode)
8119                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8120                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8121                         (int)(target_vblank -
8122                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8123                         usleep_range(1000, 1100);
8124                 }
8125
8126                 /**
8127                  * Prepare the flip event for the pageflip interrupt to handle.
8128                  *
8129                  * This only works in the case where we've already turned on the
8130                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8131                  * from 0 -> n planes we have to skip a hardware generated event
8132                  * and rely on sending it from software.
8133                  */
8134                 if (acrtc_attach->base.state->event &&
8135                     acrtc_state->active_planes > 0) {
8136                         drm_crtc_vblank_get(pcrtc);
8137
8138                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8139
8140                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8141                         prepare_flip_isr(acrtc_attach);
8142
8143                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8144                 }
8145
8146                 if (acrtc_state->stream) {
8147                         if (acrtc_state->freesync_vrr_info_changed)
8148                                 bundle->stream_update.vrr_infopacket =
8149                                         &acrtc_state->stream->vrr_infopacket;
8150                 }
8151         } else if (cursor_update && acrtc_state->active_planes > 0 &&
8152                    acrtc_attach->base.state->event) {
8153                 drm_crtc_vblank_get(pcrtc);
8154
8155                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8156
8157                 acrtc_attach->event = acrtc_attach->base.state->event;
8158                 acrtc_attach->base.state->event = NULL;
8159
8160                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8161         }
8162
8163         /* Update the planes if changed or disable if we don't have any. */
8164         if ((planes_count || acrtc_state->active_planes == 0) &&
8165                 acrtc_state->stream) {
8166                 /*
8167                  * If PSR or idle optimizations are enabled then flush out
8168                  * any pending work before hardware programming.
8169                  */
8170                 if (dm->vblank_control_workqueue)
8171                         flush_workqueue(dm->vblank_control_workqueue);
8172
8173                 bundle->stream_update.stream = acrtc_state->stream;
8174                 if (new_pcrtc_state->mode_changed) {
8175                         bundle->stream_update.src = acrtc_state->stream->src;
8176                         bundle->stream_update.dst = acrtc_state->stream->dst;
8177                 }
8178
8179                 if (new_pcrtc_state->color_mgmt_changed) {
8180                         /*
8181                          * TODO: This isn't fully correct since we've actually
8182                          * already modified the stream in place.
8183                          */
8184                         bundle->stream_update.gamut_remap =
8185                                 &acrtc_state->stream->gamut_remap_matrix;
8186                         bundle->stream_update.output_csc_transform =
8187                                 &acrtc_state->stream->csc_color_matrix;
8188                         bundle->stream_update.out_transfer_func =
8189                                 acrtc_state->stream->out_transfer_func;
8190                 }
8191
8192                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8193                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8194                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8195
8196                 /*
8197                  * If FreeSync state on the stream has changed then we need to
8198                  * re-adjust the min/max bounds now that DC doesn't handle this
8199                  * as part of commit.
8200                  */
8201                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8202                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8203                         dc_stream_adjust_vmin_vmax(
8204                                 dm->dc, acrtc_state->stream,
8205                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8206                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8207                 }
8208                 mutex_lock(&dm->dc_lock);
8209                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8210                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8211                         amdgpu_dm_psr_disable(acrtc_state->stream);
8212
8213                 update_planes_and_stream_adapter(dm->dc,
8214                                          acrtc_state->update_type,
8215                                          planes_count,
8216                                          acrtc_state->stream,
8217                                          &bundle->stream_update,
8218                                          bundle->surface_updates);
8219
8220                 /**
8221                  * Enable or disable the interrupts on the backend.
8222                  *
8223                  * Most pipes are put into power gating when unused.
8224                  *
8225                  * When power gating is enabled on a pipe we lose the
8226                  * interrupt enablement state when power gating is disabled.
8227                  *
8228                  * So we need to update the IRQ control state in hardware
8229                  * whenever the pipe turns on (since it could be previously
8230                  * power gated) or off (since some pipes can't be power gated
8231                  * on some ASICs).
8232                  */
8233                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8234                         dm_update_pflip_irq_state(drm_to_adev(dev),
8235                                                   acrtc_attach);
8236
8237                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8238                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8239                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8240                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8241
8242                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8243                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8244                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8245                         struct amdgpu_dm_connector *aconn =
8246                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8247
8248                         if (aconn->psr_skip_count > 0)
8249                                 aconn->psr_skip_count--;
8250
8251                         /* Allow PSR when skip count is 0. */
8252                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8253
8254                         /*
8255                          * If sink supports PSR SU, there is no need to rely on
8256                          * a vblank event disable request to enable PSR. PSR SU
8257                          * can be enabled immediately once OS demonstrates an
8258                          * adequate number of fast atomic commits to notify KMD
8259                          * of update events. See `vblank_control_worker()`.
8260                          */
8261                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8262                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8263 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8264                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8265 #endif
8266                             !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8267                             (timestamp_ns -
8268                             acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8269                             500000000)
8270                                 amdgpu_dm_psr_enable(acrtc_state->stream);
8271                 } else {
8272                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
8273                 }
8274
8275                 mutex_unlock(&dm->dc_lock);
8276         }
8277
8278         /*
8279          * Update cursor state *after* programming all the planes.
8280          * This avoids redundant programming in the case where we're going
8281          * to be disabling a single plane - those pipes are being disabled.
8282          */
8283         if (acrtc_state->active_planes)
8284                 amdgpu_dm_commit_cursors(state);
8285
8286 cleanup:
8287         kfree(bundle);
8288 }
8289
8290 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8291                                    struct drm_atomic_state *state)
8292 {
8293         struct amdgpu_device *adev = drm_to_adev(dev);
8294         struct amdgpu_dm_connector *aconnector;
8295         struct drm_connector *connector;
8296         struct drm_connector_state *old_con_state, *new_con_state;
8297         struct drm_crtc_state *new_crtc_state;
8298         struct dm_crtc_state *new_dm_crtc_state;
8299         const struct dc_stream_status *status;
8300         int i, inst;
8301
8302         /* Notify device removals. */
8303         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8304                 if (old_con_state->crtc != new_con_state->crtc) {
8305                         /* CRTC changes require notification. */
8306                         goto notify;
8307                 }
8308
8309                 if (!new_con_state->crtc)
8310                         continue;
8311
8312                 new_crtc_state = drm_atomic_get_new_crtc_state(
8313                         state, new_con_state->crtc);
8314
8315                 if (!new_crtc_state)
8316                         continue;
8317
8318                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8319                         continue;
8320
8321 notify:
8322                 aconnector = to_amdgpu_dm_connector(connector);
8323
8324                 mutex_lock(&adev->dm.audio_lock);
8325                 inst = aconnector->audio_inst;
8326                 aconnector->audio_inst = -1;
8327                 mutex_unlock(&adev->dm.audio_lock);
8328
8329                 amdgpu_dm_audio_eld_notify(adev, inst);
8330         }
8331
8332         /* Notify audio device additions. */
8333         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8334                 if (!new_con_state->crtc)
8335                         continue;
8336
8337                 new_crtc_state = drm_atomic_get_new_crtc_state(
8338                         state, new_con_state->crtc);
8339
8340                 if (!new_crtc_state)
8341                         continue;
8342
8343                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8344                         continue;
8345
8346                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8347                 if (!new_dm_crtc_state->stream)
8348                         continue;
8349
8350                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8351                 if (!status)
8352                         continue;
8353
8354                 aconnector = to_amdgpu_dm_connector(connector);
8355
8356                 mutex_lock(&adev->dm.audio_lock);
8357                 inst = status->audio_inst;
8358                 aconnector->audio_inst = inst;
8359                 mutex_unlock(&adev->dm.audio_lock);
8360
8361                 amdgpu_dm_audio_eld_notify(adev, inst);
8362         }
8363 }
8364
8365 /*
8366  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8367  * @crtc_state: the DRM CRTC state
8368  * @stream_state: the DC stream state.
8369  *
8370  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8371  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8372  */
8373 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8374                                                 struct dc_stream_state *stream_state)
8375 {
8376         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8377 }
8378
8379 /**
8380  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8381  * @state: The atomic state to commit
8382  *
8383  * This will tell DC to commit the constructed DC state from atomic_check,
8384  * programming the hardware. Any failures here implies a hardware failure, since
8385  * atomic check should have filtered anything non-kosher.
8386  */
8387 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8388 {
8389         struct drm_device *dev = state->dev;
8390         struct amdgpu_device *adev = drm_to_adev(dev);
8391         struct amdgpu_display_manager *dm = &adev->dm;
8392         struct dm_atomic_state *dm_state;
8393         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8394         u32 i, j;
8395         struct drm_crtc *crtc;
8396         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8397         unsigned long flags;
8398         bool wait_for_vblank = true;
8399         struct drm_connector *connector;
8400         struct drm_connector_state *old_con_state, *new_con_state;
8401         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8402         int crtc_disable_count = 0;
8403         bool mode_set_reset_required = false;
8404         int r;
8405
8406         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8407
8408         r = drm_atomic_helper_wait_for_fences(dev, state, false);
8409         if (unlikely(r))
8410                 DRM_ERROR("Waiting for fences timed out!");
8411
8412         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8413         drm_dp_mst_atomic_wait_for_dependencies(state);
8414
8415         dm_state = dm_atomic_get_new_state(state);
8416         if (dm_state && dm_state->context) {
8417                 dc_state = dm_state->context;
8418         } else {
8419                 /* No state changes, retain current state. */
8420                 dc_state_temp = dc_create_state(dm->dc);
8421                 ASSERT(dc_state_temp);
8422                 dc_state = dc_state_temp;
8423                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8424         }
8425
8426         for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8427                                        new_crtc_state, i) {
8428                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8429
8430                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8431
8432                 if (old_crtc_state->active &&
8433                     (!new_crtc_state->active ||
8434                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8435                         manage_dm_interrupts(adev, acrtc, false);
8436                         dc_stream_release(dm_old_crtc_state->stream);
8437                 }
8438         }
8439
8440         drm_atomic_helper_calc_timestamping_constants(state);
8441
8442         /* update changed items */
8443         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8444                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8445
8446                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8447                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8448
8449                 drm_dbg_state(state->dev,
8450                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8451                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8452                         "connectors_changed:%d\n",
8453                         acrtc->crtc_id,
8454                         new_crtc_state->enable,
8455                         new_crtc_state->active,
8456                         new_crtc_state->planes_changed,
8457                         new_crtc_state->mode_changed,
8458                         new_crtc_state->active_changed,
8459                         new_crtc_state->connectors_changed);
8460
8461                 /* Disable cursor if disabling crtc */
8462                 if (old_crtc_state->active && !new_crtc_state->active) {
8463                         struct dc_cursor_position position;
8464
8465                         memset(&position, 0, sizeof(position));
8466                         mutex_lock(&dm->dc_lock);
8467                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8468                         mutex_unlock(&dm->dc_lock);
8469                 }
8470
8471                 /* Copy all transient state flags into dc state */
8472                 if (dm_new_crtc_state->stream) {
8473                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8474                                                             dm_new_crtc_state->stream);
8475                 }
8476
8477                 /* handles headless hotplug case, updating new_state and
8478                  * aconnector as needed
8479                  */
8480
8481                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8482
8483                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8484
8485                         if (!dm_new_crtc_state->stream) {
8486                                 /*
8487                                  * this could happen because of issues with
8488                                  * userspace notifications delivery.
8489                                  * In this case userspace tries to set mode on
8490                                  * display which is disconnected in fact.
8491                                  * dc_sink is NULL in this case on aconnector.
8492                                  * We expect reset mode will come soon.
8493                                  *
8494                                  * This can also happen when unplug is done
8495                                  * during resume sequence ended
8496                                  *
8497                                  * In this case, we want to pretend we still
8498                                  * have a sink to keep the pipe running so that
8499                                  * hw state is consistent with the sw state
8500                                  */
8501                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8502                                                 __func__, acrtc->base.base.id);
8503                                 continue;
8504                         }
8505
8506                         if (dm_old_crtc_state->stream)
8507                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8508
8509                         pm_runtime_get_noresume(dev->dev);
8510
8511                         acrtc->enabled = true;
8512                         acrtc->hw_mode = new_crtc_state->mode;
8513                         crtc->hwmode = new_crtc_state->mode;
8514                         mode_set_reset_required = true;
8515                 } else if (modereset_required(new_crtc_state)) {
8516                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8517                         /* i.e. reset mode */
8518                         if (dm_old_crtc_state->stream)
8519                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8520
8521                         mode_set_reset_required = true;
8522                 }
8523         } /* for_each_crtc_in_state() */
8524
8525         if (dc_state) {
8526                 /* if there mode set or reset, disable eDP PSR */
8527                 if (mode_set_reset_required) {
8528                         if (dm->vblank_control_workqueue)
8529                                 flush_workqueue(dm->vblank_control_workqueue);
8530
8531                         amdgpu_dm_psr_disable_all(dm);
8532                 }
8533
8534                 dm_enable_per_frame_crtc_master_sync(dc_state);
8535                 mutex_lock(&dm->dc_lock);
8536                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8537
8538                 /* Allow idle optimization when vblank count is 0 for display off */
8539                 if (dm->active_vblank_irq_count == 0)
8540                         dc_allow_idle_optimizations(dm->dc, true);
8541                 mutex_unlock(&dm->dc_lock);
8542         }
8543
8544         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8545                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8546
8547                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8548
8549                 if (dm_new_crtc_state->stream != NULL) {
8550                         const struct dc_stream_status *status =
8551                                         dc_stream_get_status(dm_new_crtc_state->stream);
8552
8553                         if (!status)
8554                                 status = dc_stream_get_status_from_state(dc_state,
8555                                                                          dm_new_crtc_state->stream);
8556                         if (!status)
8557                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8558                         else
8559                                 acrtc->otg_inst = status->primary_otg_inst;
8560                 }
8561         }
8562         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8563                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8564                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8565                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8566
8567                 if (!adev->dm.hdcp_workqueue)
8568                         continue;
8569
8570                 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8571
8572                 if (!connector)
8573                         continue;
8574
8575                 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8576                         connector->index, connector->status, connector->dpms);
8577                 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8578                         old_con_state->content_protection, new_con_state->content_protection);
8579
8580                 if (aconnector->dc_sink) {
8581                         if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8582                                 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8583                                 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8584                                 aconnector->dc_sink->edid_caps.display_name);
8585                         }
8586                 }
8587
8588                 new_crtc_state = NULL;
8589                 old_crtc_state = NULL;
8590
8591                 if (acrtc) {
8592                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8593                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8594                 }
8595
8596                 if (old_crtc_state)
8597                         pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8598                         old_crtc_state->enable,
8599                         old_crtc_state->active,
8600                         old_crtc_state->mode_changed,
8601                         old_crtc_state->active_changed,
8602                         old_crtc_state->connectors_changed);
8603
8604                 if (new_crtc_state)
8605                         pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8606                         new_crtc_state->enable,
8607                         new_crtc_state->active,
8608                         new_crtc_state->mode_changed,
8609                         new_crtc_state->active_changed,
8610                         new_crtc_state->connectors_changed);
8611         }
8612
8613         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8614                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8615                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8616                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8617
8618                 if (!adev->dm.hdcp_workqueue)
8619                         continue;
8620
8621                 new_crtc_state = NULL;
8622                 old_crtc_state = NULL;
8623
8624                 if (acrtc) {
8625                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8626                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8627                 }
8628
8629                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8630
8631                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8632                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8633                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8634                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8635                         dm_new_con_state->update_hdcp = true;
8636                         continue;
8637                 }
8638
8639                 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8640                                                                                         old_con_state, connector, adev->dm.hdcp_workqueue)) {
8641                         /* when display is unplugged from mst hub, connctor will
8642                          * be destroyed within dm_dp_mst_connector_destroy. connector
8643                          * hdcp perperties, like type, undesired, desired, enabled,
8644                          * will be lost. So, save hdcp properties into hdcp_work within
8645                          * amdgpu_dm_atomic_commit_tail. if the same display is
8646                          * plugged back with same display index, its hdcp properties
8647                          * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8648                          */
8649
8650                         bool enable_encryption = false;
8651
8652                         if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8653                                 enable_encryption = true;
8654
8655                         if (aconnector->dc_link && aconnector->dc_sink &&
8656                                 aconnector->dc_link->type == dc_connection_mst_branch) {
8657                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8658                                 struct hdcp_workqueue *hdcp_w =
8659                                         &hdcp_work[aconnector->dc_link->link_index];
8660
8661                                 hdcp_w->hdcp_content_type[connector->index] =
8662                                         new_con_state->hdcp_content_type;
8663                                 hdcp_w->content_protection[connector->index] =
8664                                         new_con_state->content_protection;
8665                         }
8666
8667                         if (new_crtc_state && new_crtc_state->mode_changed &&
8668                                 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8669                                 enable_encryption = true;
8670
8671                         DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8672
8673                         hdcp_update_display(
8674                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8675                                 new_con_state->hdcp_content_type, enable_encryption);
8676                 }
8677         }
8678
8679         /* Handle connector state changes */
8680         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8681                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8682                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8683                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8684                 struct dc_surface_update dummy_updates[MAX_SURFACES];
8685                 struct dc_stream_update stream_update;
8686                 struct dc_info_packet hdr_packet;
8687                 struct dc_stream_status *status = NULL;
8688                 bool abm_changed, hdr_changed, scaling_changed;
8689
8690                 memset(&dummy_updates, 0, sizeof(dummy_updates));
8691                 memset(&stream_update, 0, sizeof(stream_update));
8692
8693                 if (acrtc) {
8694                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8695                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8696                 }
8697
8698                 /* Skip any modesets/resets */
8699                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8700                         continue;
8701
8702                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8703                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8704
8705                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8706                                                              dm_old_con_state);
8707
8708                 abm_changed = dm_new_crtc_state->abm_level !=
8709                               dm_old_crtc_state->abm_level;
8710
8711                 hdr_changed =
8712                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8713
8714                 if (!scaling_changed && !abm_changed && !hdr_changed)
8715                         continue;
8716
8717                 stream_update.stream = dm_new_crtc_state->stream;
8718                 if (scaling_changed) {
8719                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8720                                         dm_new_con_state, dm_new_crtc_state->stream);
8721
8722                         stream_update.src = dm_new_crtc_state->stream->src;
8723                         stream_update.dst = dm_new_crtc_state->stream->dst;
8724                 }
8725
8726                 if (abm_changed) {
8727                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8728
8729                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8730                 }
8731
8732                 if (hdr_changed) {
8733                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8734                         stream_update.hdr_static_metadata = &hdr_packet;
8735                 }
8736
8737                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8738
8739                 if (WARN_ON(!status))
8740                         continue;
8741
8742                 WARN_ON(!status->plane_count);
8743
8744                 /*
8745                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8746                  * Here we create an empty update on each plane.
8747                  * To fix this, DC should permit updating only stream properties.
8748                  */
8749                 for (j = 0; j < status->plane_count; j++)
8750                         dummy_updates[j].surface = status->plane_states[0];
8751
8752
8753                 mutex_lock(&dm->dc_lock);
8754                 dc_update_planes_and_stream(dm->dc,
8755                                             dummy_updates,
8756                                             status->plane_count,
8757                                             dm_new_crtc_state->stream,
8758                                             &stream_update);
8759                 mutex_unlock(&dm->dc_lock);
8760         }
8761
8762         /**
8763          * Enable interrupts for CRTCs that are newly enabled or went through
8764          * a modeset. It was intentionally deferred until after the front end
8765          * state was modified to wait until the OTG was on and so the IRQ
8766          * handlers didn't access stale or invalid state.
8767          */
8768         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8769                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8770 #ifdef CONFIG_DEBUG_FS
8771                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8772 #endif
8773                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8774                 if (old_crtc_state->active && !new_crtc_state->active)
8775                         crtc_disable_count++;
8776
8777                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8778                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8779
8780                 /* For freesync config update on crtc state and params for irq */
8781                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8782
8783 #ifdef CONFIG_DEBUG_FS
8784                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8785                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8786                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8787 #endif
8788
8789                 if (new_crtc_state->active &&
8790                     (!old_crtc_state->active ||
8791                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8792                         dc_stream_retain(dm_new_crtc_state->stream);
8793                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8794                         manage_dm_interrupts(adev, acrtc, true);
8795                 }
8796                 /* Handle vrr on->off / off->on transitions */
8797                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8798
8799 #ifdef CONFIG_DEBUG_FS
8800                 if (new_crtc_state->active &&
8801                     (!old_crtc_state->active ||
8802                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8803                         /**
8804                          * Frontend may have changed so reapply the CRC capture
8805                          * settings for the stream.
8806                          */
8807                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8808 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8809                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8810                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8811                                         acrtc->dm_irq_params.window_param.update_win = true;
8812
8813                                         /**
8814                                          * It takes 2 frames for HW to stably generate CRC when
8815                                          * resuming from suspend, so we set skip_frame_cnt 2.
8816                                          */
8817                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8818                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8819                                 }
8820 #endif
8821                                 if (amdgpu_dm_crtc_configure_crc_source(
8822                                         crtc, dm_new_crtc_state, cur_crc_src))
8823                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
8824                         }
8825                 }
8826 #endif
8827         }
8828
8829         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8830                 if (new_crtc_state->async_flip)
8831                         wait_for_vblank = false;
8832
8833         /* update planes when needed per crtc*/
8834         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8835                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8836
8837                 if (dm_new_crtc_state->stream)
8838                         amdgpu_dm_commit_planes(state, dc_state, dev,
8839                                                 dm, crtc, wait_for_vblank);
8840         }
8841
8842         /* Update audio instances for each connector. */
8843         amdgpu_dm_commit_audio(dev, state);
8844
8845         /* restore the backlight level */
8846         for (i = 0; i < dm->num_of_edps; i++) {
8847                 if (dm->backlight_dev[i] &&
8848                     (dm->actual_brightness[i] != dm->brightness[i]))
8849                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8850         }
8851
8852         /*
8853          * send vblank event on all events not handled in flip and
8854          * mark consumed event for drm_atomic_helper_commit_hw_done
8855          */
8856         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8857         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8858
8859                 if (new_crtc_state->event)
8860                         drm_send_event_locked(dev, &new_crtc_state->event->base);
8861
8862                 new_crtc_state->event = NULL;
8863         }
8864         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8865
8866         /* Signal HW programming completion */
8867         drm_atomic_helper_commit_hw_done(state);
8868
8869         if (wait_for_vblank)
8870                 drm_atomic_helper_wait_for_flip_done(dev, state);
8871
8872         drm_atomic_helper_cleanup_planes(dev, state);
8873
8874         /* return the stolen vga memory back to VRAM */
8875         if (!adev->mman.keep_stolen_vga_memory)
8876                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8877         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8878
8879         /*
8880          * Finally, drop a runtime PM reference for each newly disabled CRTC,
8881          * so we can put the GPU into runtime suspend if we're not driving any
8882          * displays anymore
8883          */
8884         for (i = 0; i < crtc_disable_count; i++)
8885                 pm_runtime_put_autosuspend(dev->dev);
8886         pm_runtime_mark_last_busy(dev->dev);
8887
8888         if (dc_state_temp)
8889                 dc_release_state(dc_state_temp);
8890 }
8891
8892 static int dm_force_atomic_commit(struct drm_connector *connector)
8893 {
8894         int ret = 0;
8895         struct drm_device *ddev = connector->dev;
8896         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8897         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8898         struct drm_plane *plane = disconnected_acrtc->base.primary;
8899         struct drm_connector_state *conn_state;
8900         struct drm_crtc_state *crtc_state;
8901         struct drm_plane_state *plane_state;
8902
8903         if (!state)
8904                 return -ENOMEM;
8905
8906         state->acquire_ctx = ddev->mode_config.acquire_ctx;
8907
8908         /* Construct an atomic state to restore previous display setting */
8909
8910         /*
8911          * Attach connectors to drm_atomic_state
8912          */
8913         conn_state = drm_atomic_get_connector_state(state, connector);
8914
8915         ret = PTR_ERR_OR_ZERO(conn_state);
8916         if (ret)
8917                 goto out;
8918
8919         /* Attach crtc to drm_atomic_state*/
8920         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8921
8922         ret = PTR_ERR_OR_ZERO(crtc_state);
8923         if (ret)
8924                 goto out;
8925
8926         /* force a restore */
8927         crtc_state->mode_changed = true;
8928
8929         /* Attach plane to drm_atomic_state */
8930         plane_state = drm_atomic_get_plane_state(state, plane);
8931
8932         ret = PTR_ERR_OR_ZERO(plane_state);
8933         if (ret)
8934                 goto out;
8935
8936         /* Call commit internally with the state we just constructed */
8937         ret = drm_atomic_commit(state);
8938
8939 out:
8940         drm_atomic_state_put(state);
8941         if (ret)
8942                 DRM_ERROR("Restoring old state failed with %i\n", ret);
8943
8944         return ret;
8945 }
8946
8947 /*
8948  * This function handles all cases when set mode does not come upon hotplug.
8949  * This includes when a display is unplugged then plugged back into the
8950  * same port and when running without usermode desktop manager supprot
8951  */
8952 void dm_restore_drm_connector_state(struct drm_device *dev,
8953                                     struct drm_connector *connector)
8954 {
8955         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8956         struct amdgpu_crtc *disconnected_acrtc;
8957         struct dm_crtc_state *acrtc_state;
8958
8959         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8960                 return;
8961
8962         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8963         if (!disconnected_acrtc)
8964                 return;
8965
8966         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8967         if (!acrtc_state->stream)
8968                 return;
8969
8970         /*
8971          * If the previous sink is not released and different from the current,
8972          * we deduce we are in a state where we can not rely on usermode call
8973          * to turn on the display, so we do it here
8974          */
8975         if (acrtc_state->stream->sink != aconnector->dc_sink)
8976                 dm_force_atomic_commit(&aconnector->base);
8977 }
8978
8979 /*
8980  * Grabs all modesetting locks to serialize against any blocking commits,
8981  * Waits for completion of all non blocking commits.
8982  */
8983 static int do_aquire_global_lock(struct drm_device *dev,
8984                                  struct drm_atomic_state *state)
8985 {
8986         struct drm_crtc *crtc;
8987         struct drm_crtc_commit *commit;
8988         long ret;
8989
8990         /*
8991          * Adding all modeset locks to aquire_ctx will
8992          * ensure that when the framework release it the
8993          * extra locks we are locking here will get released to
8994          */
8995         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
8996         if (ret)
8997                 return ret;
8998
8999         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9000                 spin_lock(&crtc->commit_lock);
9001                 commit = list_first_entry_or_null(&crtc->commit_list,
9002                                 struct drm_crtc_commit, commit_entry);
9003                 if (commit)
9004                         drm_crtc_commit_get(commit);
9005                 spin_unlock(&crtc->commit_lock);
9006
9007                 if (!commit)
9008                         continue;
9009
9010                 /*
9011                  * Make sure all pending HW programming completed and
9012                  * page flips done
9013                  */
9014                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9015
9016                 if (ret > 0)
9017                         ret = wait_for_completion_interruptible_timeout(
9018                                         &commit->flip_done, 10*HZ);
9019
9020                 if (ret == 0)
9021                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
9022                                   "timed out\n", crtc->base.id, crtc->name);
9023
9024                 drm_crtc_commit_put(commit);
9025         }
9026
9027         return ret < 0 ? ret : 0;
9028 }
9029
9030 static void get_freesync_config_for_crtc(
9031         struct dm_crtc_state *new_crtc_state,
9032         struct dm_connector_state *new_con_state)
9033 {
9034         struct mod_freesync_config config = {0};
9035         struct amdgpu_dm_connector *aconnector =
9036                         to_amdgpu_dm_connector(new_con_state->base.connector);
9037         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9038         int vrefresh = drm_mode_vrefresh(mode);
9039         bool fs_vid_mode = false;
9040
9041         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9042                                         vrefresh >= aconnector->min_vfreq &&
9043                                         vrefresh <= aconnector->max_vfreq;
9044
9045         if (new_crtc_state->vrr_supported) {
9046                 new_crtc_state->stream->ignore_msa_timing_param = true;
9047                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9048
9049                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9050                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9051                 config.vsif_supported = true;
9052                 config.btr = true;
9053
9054                 if (fs_vid_mode) {
9055                         config.state = VRR_STATE_ACTIVE_FIXED;
9056                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9057                         goto out;
9058                 } else if (new_crtc_state->base.vrr_enabled) {
9059                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9060                 } else {
9061                         config.state = VRR_STATE_INACTIVE;
9062                 }
9063         }
9064 out:
9065         new_crtc_state->freesync_config = config;
9066 }
9067
9068 static void reset_freesync_config_for_crtc(
9069         struct dm_crtc_state *new_crtc_state)
9070 {
9071         new_crtc_state->vrr_supported = false;
9072
9073         memset(&new_crtc_state->vrr_infopacket, 0,
9074                sizeof(new_crtc_state->vrr_infopacket));
9075 }
9076
9077 static bool
9078 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9079                                  struct drm_crtc_state *new_crtc_state)
9080 {
9081         const struct drm_display_mode *old_mode, *new_mode;
9082
9083         if (!old_crtc_state || !new_crtc_state)
9084                 return false;
9085
9086         old_mode = &old_crtc_state->mode;
9087         new_mode = &new_crtc_state->mode;
9088
9089         if (old_mode->clock       == new_mode->clock &&
9090             old_mode->hdisplay    == new_mode->hdisplay &&
9091             old_mode->vdisplay    == new_mode->vdisplay &&
9092             old_mode->htotal      == new_mode->htotal &&
9093             old_mode->vtotal      != new_mode->vtotal &&
9094             old_mode->hsync_start == new_mode->hsync_start &&
9095             old_mode->vsync_start != new_mode->vsync_start &&
9096             old_mode->hsync_end   == new_mode->hsync_end &&
9097             old_mode->vsync_end   != new_mode->vsync_end &&
9098             old_mode->hskew       == new_mode->hskew &&
9099             old_mode->vscan       == new_mode->vscan &&
9100             (old_mode->vsync_end - old_mode->vsync_start) ==
9101             (new_mode->vsync_end - new_mode->vsync_start))
9102                 return true;
9103
9104         return false;
9105 }
9106
9107 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
9108         u64 num, den, res;
9109         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9110
9111         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9112
9113         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9114         den = (unsigned long long)new_crtc_state->mode.htotal *
9115               (unsigned long long)new_crtc_state->mode.vtotal;
9116
9117         res = div_u64(num, den);
9118         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9119 }
9120
9121 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9122                          struct drm_atomic_state *state,
9123                          struct drm_crtc *crtc,
9124                          struct drm_crtc_state *old_crtc_state,
9125                          struct drm_crtc_state *new_crtc_state,
9126                          bool enable,
9127                          bool *lock_and_validation_needed)
9128 {
9129         struct dm_atomic_state *dm_state = NULL;
9130         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9131         struct dc_stream_state *new_stream;
9132         int ret = 0;
9133
9134         /*
9135          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9136          * update changed items
9137          */
9138         struct amdgpu_crtc *acrtc = NULL;
9139         struct amdgpu_dm_connector *aconnector = NULL;
9140         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9141         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9142
9143         new_stream = NULL;
9144
9145         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9146         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9147         acrtc = to_amdgpu_crtc(crtc);
9148         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9149
9150         /* TODO This hack should go away */
9151         if (aconnector && enable) {
9152                 /* Make sure fake sink is created in plug-in scenario */
9153                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9154                                                             &aconnector->base);
9155                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9156                                                             &aconnector->base);
9157
9158                 if (IS_ERR(drm_new_conn_state)) {
9159                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9160                         goto fail;
9161                 }
9162
9163                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9164                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9165
9166                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9167                         goto skip_modeset;
9168
9169                 new_stream = create_validate_stream_for_sink(aconnector,
9170                                                              &new_crtc_state->mode,
9171                                                              dm_new_conn_state,
9172                                                              dm_old_crtc_state->stream);
9173
9174                 /*
9175                  * we can have no stream on ACTION_SET if a display
9176                  * was disconnected during S3, in this case it is not an
9177                  * error, the OS will be updated after detection, and
9178                  * will do the right thing on next atomic commit
9179                  */
9180
9181                 if (!new_stream) {
9182                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9183                                         __func__, acrtc->base.base.id);
9184                         ret = -ENOMEM;
9185                         goto fail;
9186                 }
9187
9188                 /*
9189                  * TODO: Check VSDB bits to decide whether this should
9190                  * be enabled or not.
9191                  */
9192                 new_stream->triggered_crtc_reset.enabled =
9193                         dm->force_timing_sync;
9194
9195                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9196
9197                 ret = fill_hdr_info_packet(drm_new_conn_state,
9198                                            &new_stream->hdr_static_metadata);
9199                 if (ret)
9200                         goto fail;
9201
9202                 /*
9203                  * If we already removed the old stream from the context
9204                  * (and set the new stream to NULL) then we can't reuse
9205                  * the old stream even if the stream and scaling are unchanged.
9206                  * We'll hit the BUG_ON and black screen.
9207                  *
9208                  * TODO: Refactor this function to allow this check to work
9209                  * in all conditions.
9210                  */
9211                 if (amdgpu_freesync_vid_mode &&
9212                     dm_new_crtc_state->stream &&
9213                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9214                         goto skip_modeset;
9215
9216                 if (dm_new_crtc_state->stream &&
9217                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9218                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9219                         new_crtc_state->mode_changed = false;
9220                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9221                                          new_crtc_state->mode_changed);
9222                 }
9223         }
9224
9225         /* mode_changed flag may get updated above, need to check again */
9226         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9227                 goto skip_modeset;
9228
9229         drm_dbg_state(state->dev,
9230                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
9231                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
9232                 "connectors_changed:%d\n",
9233                 acrtc->crtc_id,
9234                 new_crtc_state->enable,
9235                 new_crtc_state->active,
9236                 new_crtc_state->planes_changed,
9237                 new_crtc_state->mode_changed,
9238                 new_crtc_state->active_changed,
9239                 new_crtc_state->connectors_changed);
9240
9241         /* Remove stream for any changed/disabled CRTC */
9242         if (!enable) {
9243
9244                 if (!dm_old_crtc_state->stream)
9245                         goto skip_modeset;
9246
9247                 /* Unset freesync video if it was active before */
9248                 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9249                         dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9250                         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9251                 }
9252
9253                 /* Now check if we should set freesync video mode */
9254                 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
9255                     is_timing_unchanged_for_freesync(new_crtc_state,
9256                                                      old_crtc_state)) {
9257                         new_crtc_state->mode_changed = false;
9258                         DRM_DEBUG_DRIVER(
9259                                 "Mode change not required for front porch change, "
9260                                 "setting mode_changed to %d",
9261                                 new_crtc_state->mode_changed);
9262
9263                         set_freesync_fixed_config(dm_new_crtc_state);
9264
9265                         goto skip_modeset;
9266                 } else if (amdgpu_freesync_vid_mode && aconnector &&
9267                            is_freesync_video_mode(&new_crtc_state->mode,
9268                                                   aconnector)) {
9269                         struct drm_display_mode *high_mode;
9270
9271                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
9272                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
9273                                 set_freesync_fixed_config(dm_new_crtc_state);
9274                         }
9275                 }
9276
9277                 ret = dm_atomic_get_state(state, &dm_state);
9278                 if (ret)
9279                         goto fail;
9280
9281                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9282                                 crtc->base.id);
9283
9284                 /* i.e. reset mode */
9285                 if (dc_remove_stream_from_ctx(
9286                                 dm->dc,
9287                                 dm_state->context,
9288                                 dm_old_crtc_state->stream) != DC_OK) {
9289                         ret = -EINVAL;
9290                         goto fail;
9291                 }
9292
9293                 dc_stream_release(dm_old_crtc_state->stream);
9294                 dm_new_crtc_state->stream = NULL;
9295
9296                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9297
9298                 *lock_and_validation_needed = true;
9299
9300         } else {/* Add stream for any updated/enabled CRTC */
9301                 /*
9302                  * Quick fix to prevent NULL pointer on new_stream when
9303                  * added MST connectors not found in existing crtc_state in the chained mode
9304                  * TODO: need to dig out the root cause of that
9305                  */
9306                 if (!aconnector)
9307                         goto skip_modeset;
9308
9309                 if (modereset_required(new_crtc_state))
9310                         goto skip_modeset;
9311
9312                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9313                                      dm_old_crtc_state->stream)) {
9314
9315                         WARN_ON(dm_new_crtc_state->stream);
9316
9317                         ret = dm_atomic_get_state(state, &dm_state);
9318                         if (ret)
9319                                 goto fail;
9320
9321                         dm_new_crtc_state->stream = new_stream;
9322
9323                         dc_stream_retain(new_stream);
9324
9325                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9326                                          crtc->base.id);
9327
9328                         if (dc_add_stream_to_ctx(
9329                                         dm->dc,
9330                                         dm_state->context,
9331                                         dm_new_crtc_state->stream) != DC_OK) {
9332                                 ret = -EINVAL;
9333                                 goto fail;
9334                         }
9335
9336                         *lock_and_validation_needed = true;
9337                 }
9338         }
9339
9340 skip_modeset:
9341         /* Release extra reference */
9342         if (new_stream)
9343                 dc_stream_release(new_stream);
9344
9345         /*
9346          * We want to do dc stream updates that do not require a
9347          * full modeset below.
9348          */
9349         if (!(enable && aconnector && new_crtc_state->active))
9350                 return 0;
9351         /*
9352          * Given above conditions, the dc state cannot be NULL because:
9353          * 1. We're in the process of enabling CRTCs (just been added
9354          *    to the dc context, or already is on the context)
9355          * 2. Has a valid connector attached, and
9356          * 3. Is currently active and enabled.
9357          * => The dc stream state currently exists.
9358          */
9359         BUG_ON(dm_new_crtc_state->stream == NULL);
9360
9361         /* Scaling or underscan settings */
9362         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9363                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
9364                 update_stream_scaling_settings(
9365                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9366
9367         /* ABM settings */
9368         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9369
9370         /*
9371          * Color management settings. We also update color properties
9372          * when a modeset is needed, to ensure it gets reprogrammed.
9373          */
9374         if (dm_new_crtc_state->base.color_mgmt_changed ||
9375             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9376                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9377                 if (ret)
9378                         goto fail;
9379         }
9380
9381         /* Update Freesync settings. */
9382         get_freesync_config_for_crtc(dm_new_crtc_state,
9383                                      dm_new_conn_state);
9384
9385         return ret;
9386
9387 fail:
9388         if (new_stream)
9389                 dc_stream_release(new_stream);
9390         return ret;
9391 }
9392
9393 static bool should_reset_plane(struct drm_atomic_state *state,
9394                                struct drm_plane *plane,
9395                                struct drm_plane_state *old_plane_state,
9396                                struct drm_plane_state *new_plane_state)
9397 {
9398         struct drm_plane *other;
9399         struct drm_plane_state *old_other_state, *new_other_state;
9400         struct drm_crtc_state *new_crtc_state;
9401         int i;
9402
9403         /*
9404          * TODO: Remove this hack once the checks below are sufficient
9405          * enough to determine when we need to reset all the planes on
9406          * the stream.
9407          */
9408         if (state->allow_modeset)
9409                 return true;
9410
9411         /* Exit early if we know that we're adding or removing the plane. */
9412         if (old_plane_state->crtc != new_plane_state->crtc)
9413                 return true;
9414
9415         /* old crtc == new_crtc == NULL, plane not in context. */
9416         if (!new_plane_state->crtc)
9417                 return false;
9418
9419         new_crtc_state =
9420                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9421
9422         if (!new_crtc_state)
9423                 return true;
9424
9425         /* CRTC Degamma changes currently require us to recreate planes. */
9426         if (new_crtc_state->color_mgmt_changed)
9427                 return true;
9428
9429         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9430                 return true;
9431
9432         /*
9433          * If there are any new primary or overlay planes being added or
9434          * removed then the z-order can potentially change. To ensure
9435          * correct z-order and pipe acquisition the current DC architecture
9436          * requires us to remove and recreate all existing planes.
9437          *
9438          * TODO: Come up with a more elegant solution for this.
9439          */
9440         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9441                 struct amdgpu_framebuffer *old_afb, *new_afb;
9442                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9443                         continue;
9444
9445                 if (old_other_state->crtc != new_plane_state->crtc &&
9446                     new_other_state->crtc != new_plane_state->crtc)
9447                         continue;
9448
9449                 if (old_other_state->crtc != new_other_state->crtc)
9450                         return true;
9451
9452                 /* Src/dst size and scaling updates. */
9453                 if (old_other_state->src_w != new_other_state->src_w ||
9454                     old_other_state->src_h != new_other_state->src_h ||
9455                     old_other_state->crtc_w != new_other_state->crtc_w ||
9456                     old_other_state->crtc_h != new_other_state->crtc_h)
9457                         return true;
9458
9459                 /* Rotation / mirroring updates. */
9460                 if (old_other_state->rotation != new_other_state->rotation)
9461                         return true;
9462
9463                 /* Blending updates. */
9464                 if (old_other_state->pixel_blend_mode !=
9465                     new_other_state->pixel_blend_mode)
9466                         return true;
9467
9468                 /* Alpha updates. */
9469                 if (old_other_state->alpha != new_other_state->alpha)
9470                         return true;
9471
9472                 /* Colorspace changes. */
9473                 if (old_other_state->color_range != new_other_state->color_range ||
9474                     old_other_state->color_encoding != new_other_state->color_encoding)
9475                         return true;
9476
9477                 /* Framebuffer checks fall at the end. */
9478                 if (!old_other_state->fb || !new_other_state->fb)
9479                         continue;
9480
9481                 /* Pixel format changes can require bandwidth updates. */
9482                 if (old_other_state->fb->format != new_other_state->fb->format)
9483                         return true;
9484
9485                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9486                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9487
9488                 /* Tiling and DCC changes also require bandwidth updates. */
9489                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9490                     old_afb->base.modifier != new_afb->base.modifier)
9491                         return true;
9492         }
9493
9494         return false;
9495 }
9496
9497 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9498                               struct drm_plane_state *new_plane_state,
9499                               struct drm_framebuffer *fb)
9500 {
9501         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9502         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9503         unsigned int pitch;
9504         bool linear;
9505
9506         if (fb->width > new_acrtc->max_cursor_width ||
9507             fb->height > new_acrtc->max_cursor_height) {
9508                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9509                                  new_plane_state->fb->width,
9510                                  new_plane_state->fb->height);
9511                 return -EINVAL;
9512         }
9513         if (new_plane_state->src_w != fb->width << 16 ||
9514             new_plane_state->src_h != fb->height << 16) {
9515                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9516                 return -EINVAL;
9517         }
9518
9519         /* Pitch in pixels */
9520         pitch = fb->pitches[0] / fb->format->cpp[0];
9521
9522         if (fb->width != pitch) {
9523                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9524                                  fb->width, pitch);
9525                 return -EINVAL;
9526         }
9527
9528         switch (pitch) {
9529         case 64:
9530         case 128:
9531         case 256:
9532                 /* FB pitch is supported by cursor plane */
9533                 break;
9534         default:
9535                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9536                 return -EINVAL;
9537         }
9538
9539         /* Core DRM takes care of checking FB modifiers, so we only need to
9540          * check tiling flags when the FB doesn't have a modifier. */
9541         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9542                 if (adev->family < AMDGPU_FAMILY_AI) {
9543                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9544                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9545                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9546                 } else {
9547                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9548                 }
9549                 if (!linear) {
9550                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9551                         return -EINVAL;
9552                 }
9553         }
9554
9555         return 0;
9556 }
9557
9558 static int dm_update_plane_state(struct dc *dc,
9559                                  struct drm_atomic_state *state,
9560                                  struct drm_plane *plane,
9561                                  struct drm_plane_state *old_plane_state,
9562                                  struct drm_plane_state *new_plane_state,
9563                                  bool enable,
9564                                  bool *lock_and_validation_needed,
9565                                  bool *is_top_most_overlay)
9566 {
9567
9568         struct dm_atomic_state *dm_state = NULL;
9569         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9570         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9571         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9572         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9573         struct amdgpu_crtc *new_acrtc;
9574         bool needs_reset;
9575         int ret = 0;
9576
9577
9578         new_plane_crtc = new_plane_state->crtc;
9579         old_plane_crtc = old_plane_state->crtc;
9580         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9581         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9582
9583         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9584                 if (!enable || !new_plane_crtc ||
9585                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9586                         return 0;
9587
9588                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9589
9590                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9591                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9592                         return -EINVAL;
9593                 }
9594
9595                 if (new_plane_state->fb) {
9596                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9597                                                  new_plane_state->fb);
9598                         if (ret)
9599                                 return ret;
9600                 }
9601
9602                 return 0;
9603         }
9604
9605         needs_reset = should_reset_plane(state, plane, old_plane_state,
9606                                          new_plane_state);
9607
9608         /* Remove any changed/removed planes */
9609         if (!enable) {
9610                 if (!needs_reset)
9611                         return 0;
9612
9613                 if (!old_plane_crtc)
9614                         return 0;
9615
9616                 old_crtc_state = drm_atomic_get_old_crtc_state(
9617                                 state, old_plane_crtc);
9618                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9619
9620                 if (!dm_old_crtc_state->stream)
9621                         return 0;
9622
9623                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9624                                 plane->base.id, old_plane_crtc->base.id);
9625
9626                 ret = dm_atomic_get_state(state, &dm_state);
9627                 if (ret)
9628                         return ret;
9629
9630                 if (!dc_remove_plane_from_context(
9631                                 dc,
9632                                 dm_old_crtc_state->stream,
9633                                 dm_old_plane_state->dc_state,
9634                                 dm_state->context)) {
9635
9636                         return -EINVAL;
9637                 }
9638
9639                 if (dm_old_plane_state->dc_state)
9640                         dc_plane_state_release(dm_old_plane_state->dc_state);
9641
9642                 dm_new_plane_state->dc_state = NULL;
9643
9644                 *lock_and_validation_needed = true;
9645
9646         } else { /* Add new planes */
9647                 struct dc_plane_state *dc_new_plane_state;
9648
9649                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9650                         return 0;
9651
9652                 if (!new_plane_crtc)
9653                         return 0;
9654
9655                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9656                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9657
9658                 if (!dm_new_crtc_state->stream)
9659                         return 0;
9660
9661                 if (!needs_reset)
9662                         return 0;
9663
9664                 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9665                 if (ret)
9666                         return ret;
9667
9668                 WARN_ON(dm_new_plane_state->dc_state);
9669
9670                 dc_new_plane_state = dc_create_plane_state(dc);
9671                 if (!dc_new_plane_state)
9672                         return -ENOMEM;
9673
9674                 /* Block top most plane from being a video plane */
9675                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9676                         if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9677                                 return -EINVAL;
9678                         else
9679                                 *is_top_most_overlay = false;
9680                 }
9681
9682                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9683                                  plane->base.id, new_plane_crtc->base.id);
9684
9685                 ret = fill_dc_plane_attributes(
9686                         drm_to_adev(new_plane_crtc->dev),
9687                         dc_new_plane_state,
9688                         new_plane_state,
9689                         new_crtc_state);
9690                 if (ret) {
9691                         dc_plane_state_release(dc_new_plane_state);
9692                         return ret;
9693                 }
9694
9695                 ret = dm_atomic_get_state(state, &dm_state);
9696                 if (ret) {
9697                         dc_plane_state_release(dc_new_plane_state);
9698                         return ret;
9699                 }
9700
9701                 /*
9702                  * Any atomic check errors that occur after this will
9703                  * not need a release. The plane state will be attached
9704                  * to the stream, and therefore part of the atomic
9705                  * state. It'll be released when the atomic state is
9706                  * cleaned.
9707                  */
9708                 if (!dc_add_plane_to_context(
9709                                 dc,
9710                                 dm_new_crtc_state->stream,
9711                                 dc_new_plane_state,
9712                                 dm_state->context)) {
9713
9714                         dc_plane_state_release(dc_new_plane_state);
9715                         return -EINVAL;
9716                 }
9717
9718                 dm_new_plane_state->dc_state = dc_new_plane_state;
9719
9720                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9721
9722                 /* Tell DC to do a full surface update every time there
9723                  * is a plane change. Inefficient, but works for now.
9724                  */
9725                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9726
9727                 *lock_and_validation_needed = true;
9728         }
9729
9730
9731         return ret;
9732 }
9733
9734 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9735                                        int *src_w, int *src_h)
9736 {
9737         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9738         case DRM_MODE_ROTATE_90:
9739         case DRM_MODE_ROTATE_270:
9740                 *src_w = plane_state->src_h >> 16;
9741                 *src_h = plane_state->src_w >> 16;
9742                 break;
9743         case DRM_MODE_ROTATE_0:
9744         case DRM_MODE_ROTATE_180:
9745         default:
9746                 *src_w = plane_state->src_w >> 16;
9747                 *src_h = plane_state->src_h >> 16;
9748                 break;
9749         }
9750 }
9751
9752 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9753                                 struct drm_crtc *crtc,
9754                                 struct drm_crtc_state *new_crtc_state)
9755 {
9756         struct drm_plane *cursor = crtc->cursor, *underlying;
9757         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9758         int i;
9759         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9760         int cursor_src_w, cursor_src_h;
9761         int underlying_src_w, underlying_src_h;
9762
9763         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9764          * cursor per pipe but it's going to inherit the scaling and
9765          * positioning from the underlying pipe. Check the cursor plane's
9766          * blending properties match the underlying planes'. */
9767
9768         new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9769         if (!new_cursor_state || !new_cursor_state->fb) {
9770                 return 0;
9771         }
9772
9773         dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9774         cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9775         cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9776
9777         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9778                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9779                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9780                         continue;
9781
9782                 /* Ignore disabled planes */
9783                 if (!new_underlying_state->fb)
9784                         continue;
9785
9786                 dm_get_oriented_plane_size(new_underlying_state,
9787                                            &underlying_src_w, &underlying_src_h);
9788                 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9789                 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9790
9791                 if (cursor_scale_w != underlying_scale_w ||
9792                     cursor_scale_h != underlying_scale_h) {
9793                         drm_dbg_atomic(crtc->dev,
9794                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9795                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9796                         return -EINVAL;
9797                 }
9798
9799                 /* If this plane covers the whole CRTC, no need to check planes underneath */
9800                 if (new_underlying_state->crtc_x <= 0 &&
9801                     new_underlying_state->crtc_y <= 0 &&
9802                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9803                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9804                         break;
9805         }
9806
9807         return 0;
9808 }
9809
9810 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9811 {
9812         struct drm_connector *connector;
9813         struct drm_connector_state *conn_state, *old_conn_state;
9814         struct amdgpu_dm_connector *aconnector = NULL;
9815         int i;
9816         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9817                 if (!conn_state->crtc)
9818                         conn_state = old_conn_state;
9819
9820                 if (conn_state->crtc != crtc)
9821                         continue;
9822
9823                 aconnector = to_amdgpu_dm_connector(connector);
9824                 if (!aconnector->mst_output_port || !aconnector->mst_root)
9825                         aconnector = NULL;
9826                 else
9827                         break;
9828         }
9829
9830         if (!aconnector)
9831                 return 0;
9832
9833         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
9834 }
9835
9836 /**
9837  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9838  *
9839  * @dev: The DRM device
9840  * @state: The atomic state to commit
9841  *
9842  * Validate that the given atomic state is programmable by DC into hardware.
9843  * This involves constructing a &struct dc_state reflecting the new hardware
9844  * state we wish to commit, then querying DC to see if it is programmable. It's
9845  * important not to modify the existing DC state. Otherwise, atomic_check
9846  * may unexpectedly commit hardware changes.
9847  *
9848  * When validating the DC state, it's important that the right locks are
9849  * acquired. For full updates case which removes/adds/updates streams on one
9850  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9851  * that any such full update commit will wait for completion of any outstanding
9852  * flip using DRMs synchronization events.
9853  *
9854  * Note that DM adds the affected connectors for all CRTCs in state, when that
9855  * might not seem necessary. This is because DC stream creation requires the
9856  * DC sink, which is tied to the DRM connector state. Cleaning this up should
9857  * be possible but non-trivial - a possible TODO item.
9858  *
9859  * Return: -Error code if validation failed.
9860  */
9861 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9862                                   struct drm_atomic_state *state)
9863 {
9864         struct amdgpu_device *adev = drm_to_adev(dev);
9865         struct dm_atomic_state *dm_state = NULL;
9866         struct dc *dc = adev->dm.dc;
9867         struct drm_connector *connector;
9868         struct drm_connector_state *old_con_state, *new_con_state;
9869         struct drm_crtc *crtc;
9870         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9871         struct drm_plane *plane;
9872         struct drm_plane_state *old_plane_state, *new_plane_state;
9873         enum dc_status status;
9874         int ret, i;
9875         bool lock_and_validation_needed = false;
9876         bool is_top_most_overlay = true;
9877         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9878         struct drm_dp_mst_topology_mgr *mgr;
9879         struct drm_dp_mst_topology_state *mst_state;
9880         struct dsc_mst_fairness_vars vars[MAX_PIPES];
9881
9882         trace_amdgpu_dm_atomic_check_begin(state);
9883
9884         ret = drm_atomic_helper_check_modeset(dev, state);
9885         if (ret) {
9886                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9887                 goto fail;
9888         }
9889
9890         /* Check connector changes */
9891         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9892                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9893                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9894
9895                 /* Skip connectors that are disabled or part of modeset already. */
9896                 if (!new_con_state->crtc)
9897                         continue;
9898
9899                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9900                 if (IS_ERR(new_crtc_state)) {
9901                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
9902                         ret = PTR_ERR(new_crtc_state);
9903                         goto fail;
9904                 }
9905
9906                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
9907                     dm_old_con_state->scaling != dm_new_con_state->scaling)
9908                         new_crtc_state->connectors_changed = true;
9909         }
9910
9911         if (dc_resource_is_dsc_encoding_supported(dc)) {
9912                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9913                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9914                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
9915                                 if (ret) {
9916                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
9917                                         goto fail;
9918                                 }
9919                         }
9920                 }
9921         }
9922         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9923                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9924
9925                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
9926                     !new_crtc_state->color_mgmt_changed &&
9927                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9928                         dm_old_crtc_state->dsc_force_changed == false)
9929                         continue;
9930
9931                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
9932                 if (ret) {
9933                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
9934                         goto fail;
9935                 }
9936
9937                 if (!new_crtc_state->enable)
9938                         continue;
9939
9940                 ret = drm_atomic_add_affected_connectors(state, crtc);
9941                 if (ret) {
9942                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
9943                         goto fail;
9944                 }
9945
9946                 ret = drm_atomic_add_affected_planes(state, crtc);
9947                 if (ret) {
9948                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
9949                         goto fail;
9950                 }
9951
9952                 if (dm_old_crtc_state->dsc_force_changed)
9953                         new_crtc_state->mode_changed = true;
9954         }
9955
9956         /*
9957          * Add all primary and overlay planes on the CRTC to the state
9958          * whenever a plane is enabled to maintain correct z-ordering
9959          * and to enable fast surface updates.
9960          */
9961         drm_for_each_crtc(crtc, dev) {
9962                 bool modified = false;
9963
9964                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9965                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9966                                 continue;
9967
9968                         if (new_plane_state->crtc == crtc ||
9969                             old_plane_state->crtc == crtc) {
9970                                 modified = true;
9971                                 break;
9972                         }
9973                 }
9974
9975                 if (!modified)
9976                         continue;
9977
9978                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9979                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9980                                 continue;
9981
9982                         new_plane_state =
9983                                 drm_atomic_get_plane_state(state, plane);
9984
9985                         if (IS_ERR(new_plane_state)) {
9986                                 ret = PTR_ERR(new_plane_state);
9987                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
9988                                 goto fail;
9989                         }
9990                 }
9991         }
9992
9993         /*
9994          * DC consults the zpos (layer_index in DC terminology) to determine the
9995          * hw plane on which to enable the hw cursor (see
9996          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
9997          * atomic state, so call drm helper to normalize zpos.
9998          */
9999         ret = drm_atomic_normalize_zpos(dev, state);
10000         if (ret) {
10001                 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10002                 goto fail;
10003         }
10004
10005         /* Remove exiting planes if they are modified */
10006         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10007                 ret = dm_update_plane_state(dc, state, plane,
10008                                             old_plane_state,
10009                                             new_plane_state,
10010                                             false,
10011                                             &lock_and_validation_needed,
10012                                             &is_top_most_overlay);
10013                 if (ret) {
10014                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10015                         goto fail;
10016                 }
10017         }
10018
10019         /* Disable all crtcs which require disable */
10020         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10021                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10022                                            old_crtc_state,
10023                                            new_crtc_state,
10024                                            false,
10025                                            &lock_and_validation_needed);
10026                 if (ret) {
10027                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10028                         goto fail;
10029                 }
10030         }
10031
10032         /* Enable all crtcs which require enable */
10033         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10034                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10035                                            old_crtc_state,
10036                                            new_crtc_state,
10037                                            true,
10038                                            &lock_and_validation_needed);
10039                 if (ret) {
10040                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10041                         goto fail;
10042                 }
10043         }
10044
10045         /* Add new/modified planes */
10046         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10047                 ret = dm_update_plane_state(dc, state, plane,
10048                                             old_plane_state,
10049                                             new_plane_state,
10050                                             true,
10051                                             &lock_and_validation_needed,
10052                                             &is_top_most_overlay);
10053                 if (ret) {
10054                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10055                         goto fail;
10056                 }
10057         }
10058
10059         if (dc_resource_is_dsc_encoding_supported(dc)) {
10060                 ret = pre_validate_dsc(state, &dm_state, vars);
10061                 if (ret != 0)
10062                         goto fail;
10063         }
10064
10065         /* Run this here since we want to validate the streams we created */
10066         ret = drm_atomic_helper_check_planes(dev, state);
10067         if (ret) {
10068                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10069                 goto fail;
10070         }
10071
10072         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10073                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10074                 if (dm_new_crtc_state->mpo_requested)
10075                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10076         }
10077
10078         /* Check cursor planes scaling */
10079         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10080                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10081                 if (ret) {
10082                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10083                         goto fail;
10084                 }
10085         }
10086
10087         if (state->legacy_cursor_update) {
10088                 /*
10089                  * This is a fast cursor update coming from the plane update
10090                  * helper, check if it can be done asynchronously for better
10091                  * performance.
10092                  */
10093                 state->async_update =
10094                         !drm_atomic_helper_async_check(dev, state);
10095
10096                 /*
10097                  * Skip the remaining global validation if this is an async
10098                  * update. Cursor updates can be done without affecting
10099                  * state or bandwidth calcs and this avoids the performance
10100                  * penalty of locking the private state object and
10101                  * allocating a new dc_state.
10102                  */
10103                 if (state->async_update)
10104                         return 0;
10105         }
10106
10107         /* Check scaling and underscan changes*/
10108         /* TODO Removed scaling changes validation due to inability to commit
10109          * new stream into context w\o causing full reset. Need to
10110          * decide how to handle.
10111          */
10112         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10113                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10114                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10115                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10116
10117                 /* Skip any modesets/resets */
10118                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10119                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10120                         continue;
10121
10122                 /* Skip any thing not scale or underscan changes */
10123                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10124                         continue;
10125
10126                 lock_and_validation_needed = true;
10127         }
10128
10129         /* set the slot info for each mst_state based on the link encoding format */
10130         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10131                 struct amdgpu_dm_connector *aconnector;
10132                 struct drm_connector *connector;
10133                 struct drm_connector_list_iter iter;
10134                 u8 link_coding_cap;
10135
10136                 drm_connector_list_iter_begin(dev, &iter);
10137                 drm_for_each_connector_iter(connector, &iter) {
10138                         if (connector->index == mst_state->mgr->conn_base_id) {
10139                                 aconnector = to_amdgpu_dm_connector(connector);
10140                                 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10141                                 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10142
10143                                 break;
10144                         }
10145                 }
10146                 drm_connector_list_iter_end(&iter);
10147         }
10148
10149         /**
10150          * Streams and planes are reset when there are changes that affect
10151          * bandwidth. Anything that affects bandwidth needs to go through
10152          * DC global validation to ensure that the configuration can be applied
10153          * to hardware.
10154          *
10155          * We have to currently stall out here in atomic_check for outstanding
10156          * commits to finish in this case because our IRQ handlers reference
10157          * DRM state directly - we can end up disabling interrupts too early
10158          * if we don't.
10159          *
10160          * TODO: Remove this stall and drop DM state private objects.
10161          */
10162         if (lock_and_validation_needed) {
10163                 ret = dm_atomic_get_state(state, &dm_state);
10164                 if (ret) {
10165                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10166                         goto fail;
10167                 }
10168
10169                 ret = do_aquire_global_lock(dev, state);
10170                 if (ret) {
10171                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10172                         goto fail;
10173                 }
10174
10175                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10176                 if (ret) {
10177                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10178                         ret = -EINVAL;
10179                         goto fail;
10180                 }
10181
10182                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10183                 if (ret) {
10184                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10185                         goto fail;
10186                 }
10187
10188                 /*
10189                  * Perform validation of MST topology in the state:
10190                  * We need to perform MST atomic check before calling
10191                  * dc_validate_global_state(), or there is a chance
10192                  * to get stuck in an infinite loop and hang eventually.
10193                  */
10194                 ret = drm_dp_mst_atomic_check(state);
10195                 if (ret) {
10196                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10197                         goto fail;
10198                 }
10199                 status = dc_validate_global_state(dc, dm_state->context, true);
10200                 if (status != DC_OK) {
10201                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10202                                        dc_status_to_str(status), status);
10203                         ret = -EINVAL;
10204                         goto fail;
10205                 }
10206         } else {
10207                 /*
10208                  * The commit is a fast update. Fast updates shouldn't change
10209                  * the DC context, affect global validation, and can have their
10210                  * commit work done in parallel with other commits not touching
10211                  * the same resource. If we have a new DC context as part of
10212                  * the DM atomic state from validation we need to free it and
10213                  * retain the existing one instead.
10214                  *
10215                  * Furthermore, since the DM atomic state only contains the DC
10216                  * context and can safely be annulled, we can free the state
10217                  * and clear the associated private object now to free
10218                  * some memory and avoid a possible use-after-free later.
10219                  */
10220
10221                 for (i = 0; i < state->num_private_objs; i++) {
10222                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10223
10224                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10225                                 int j = state->num_private_objs-1;
10226
10227                                 dm_atomic_destroy_state(obj,
10228                                                 state->private_objs[i].state);
10229
10230                                 /* If i is not at the end of the array then the
10231                                  * last element needs to be moved to where i was
10232                                  * before the array can safely be truncated.
10233                                  */
10234                                 if (i != j)
10235                                         state->private_objs[i] =
10236                                                 state->private_objs[j];
10237
10238                                 state->private_objs[j].ptr = NULL;
10239                                 state->private_objs[j].state = NULL;
10240                                 state->private_objs[j].old_state = NULL;
10241                                 state->private_objs[j].new_state = NULL;
10242
10243                                 state->num_private_objs = j;
10244                                 break;
10245                         }
10246                 }
10247         }
10248
10249         /* Store the overall update type for use later in atomic check. */
10250         for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
10251                 struct dm_crtc_state *dm_new_crtc_state =
10252                         to_dm_crtc_state(new_crtc_state);
10253
10254                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10255                                                          UPDATE_TYPE_FULL :
10256                                                          UPDATE_TYPE_FAST;
10257         }
10258
10259         /* Must be success */
10260         WARN_ON(ret);
10261
10262         trace_amdgpu_dm_atomic_check_finish(state, ret);
10263
10264         return ret;
10265
10266 fail:
10267         if (ret == -EDEADLK)
10268                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10269         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10270                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10271         else
10272                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
10273
10274         trace_amdgpu_dm_atomic_check_finish(state, ret);
10275
10276         return ret;
10277 }
10278
10279 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10280                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10281 {
10282         u8 dpcd_data;
10283         bool capable = false;
10284
10285         if (amdgpu_dm_connector->dc_link &&
10286                 dm_helpers_dp_read_dpcd(
10287                                 NULL,
10288                                 amdgpu_dm_connector->dc_link,
10289                                 DP_DOWN_STREAM_PORT_COUNT,
10290                                 &dpcd_data,
10291                                 sizeof(dpcd_data))) {
10292                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10293         }
10294
10295         return capable;
10296 }
10297
10298 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10299                 unsigned int offset,
10300                 unsigned int total_length,
10301                 u8 *data,
10302                 unsigned int length,
10303                 struct amdgpu_hdmi_vsdb_info *vsdb)
10304 {
10305         bool res;
10306         union dmub_rb_cmd cmd;
10307         struct dmub_cmd_send_edid_cea *input;
10308         struct dmub_cmd_edid_cea_output *output;
10309
10310         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10311                 return false;
10312
10313         memset(&cmd, 0, sizeof(cmd));
10314
10315         input = &cmd.edid_cea.data.input;
10316
10317         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10318         cmd.edid_cea.header.sub_type = 0;
10319         cmd.edid_cea.header.payload_bytes =
10320                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10321         input->offset = offset;
10322         input->length = length;
10323         input->cea_total_length = total_length;
10324         memcpy(input->payload, data, length);
10325
10326         res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
10327         if (!res) {
10328                 DRM_ERROR("EDID CEA parser failed\n");
10329                 return false;
10330         }
10331
10332         output = &cmd.edid_cea.data.output;
10333
10334         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10335                 if (!output->ack.success) {
10336                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
10337                                         output->ack.offset);
10338                 }
10339         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10340                 if (!output->amd_vsdb.vsdb_found)
10341                         return false;
10342
10343                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10344                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10345                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10346                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10347         } else {
10348                 DRM_WARN("Unknown EDID CEA parser results\n");
10349                 return false;
10350         }
10351
10352         return true;
10353 }
10354
10355 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10356                 u8 *edid_ext, int len,
10357                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10358 {
10359         int i;
10360
10361         /* send extension block to DMCU for parsing */
10362         for (i = 0; i < len; i += 8) {
10363                 bool res;
10364                 int offset;
10365
10366                 /* send 8 bytes a time */
10367                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10368                         return false;
10369
10370                 if (i+8 == len) {
10371                         /* EDID block sent completed, expect result */
10372                         int version, min_rate, max_rate;
10373
10374                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10375                         if (res) {
10376                                 /* amd vsdb found */
10377                                 vsdb_info->freesync_supported = 1;
10378                                 vsdb_info->amd_vsdb_version = version;
10379                                 vsdb_info->min_refresh_rate_hz = min_rate;
10380                                 vsdb_info->max_refresh_rate_hz = max_rate;
10381                                 return true;
10382                         }
10383                         /* not amd vsdb */
10384                         return false;
10385                 }
10386
10387                 /* check for ack*/
10388                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10389                 if (!res)
10390                         return false;
10391         }
10392
10393         return false;
10394 }
10395
10396 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10397                 u8 *edid_ext, int len,
10398                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10399 {
10400         int i;
10401
10402         /* send extension block to DMCU for parsing */
10403         for (i = 0; i < len; i += 8) {
10404                 /* send 8 bytes a time */
10405                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10406                         return false;
10407         }
10408
10409         return vsdb_info->freesync_supported;
10410 }
10411
10412 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10413                 u8 *edid_ext, int len,
10414                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10415 {
10416         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10417         bool ret;
10418
10419         mutex_lock(&adev->dm.dc_lock);
10420         if (adev->dm.dmub_srv)
10421                 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10422         else
10423                 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10424         mutex_unlock(&adev->dm.dc_lock);
10425         return ret;
10426 }
10427
10428 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10429                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10430 {
10431         u8 *edid_ext = NULL;
10432         int i;
10433         bool valid_vsdb_found = false;
10434
10435         /*----- drm_find_cea_extension() -----*/
10436         /* No EDID or EDID extensions */
10437         if (edid == NULL || edid->extensions == 0)
10438                 return -ENODEV;
10439
10440         /* Find CEA extension */
10441         for (i = 0; i < edid->extensions; i++) {
10442                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10443                 if (edid_ext[0] == CEA_EXT)
10444                         break;
10445         }
10446
10447         if (i == edid->extensions)
10448                 return -ENODEV;
10449
10450         /*----- cea_db_offsets() -----*/
10451         if (edid_ext[0] != CEA_EXT)
10452                 return -ENODEV;
10453
10454         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10455
10456         return valid_vsdb_found ? i : -ENODEV;
10457 }
10458
10459 /**
10460  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10461  *
10462  * @connector: Connector to query.
10463  * @edid: EDID from monitor
10464  *
10465  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10466  * track of some of the display information in the internal data struct used by
10467  * amdgpu_dm. This function checks which type of connector we need to set the
10468  * FreeSync parameters.
10469  */
10470 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10471                                     struct edid *edid)
10472 {
10473         int i = 0;
10474         struct detailed_timing *timing;
10475         struct detailed_non_pixel *data;
10476         struct detailed_data_monitor_range *range;
10477         struct amdgpu_dm_connector *amdgpu_dm_connector =
10478                         to_amdgpu_dm_connector(connector);
10479         struct dm_connector_state *dm_con_state = NULL;
10480         struct dc_sink *sink;
10481
10482         struct drm_device *dev = connector->dev;
10483         struct amdgpu_device *adev = drm_to_adev(dev);
10484         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10485         bool freesync_capable = false;
10486         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10487
10488         if (!connector->state) {
10489                 DRM_ERROR("%s - Connector has no state", __func__);
10490                 goto update;
10491         }
10492
10493         sink = amdgpu_dm_connector->dc_sink ?
10494                 amdgpu_dm_connector->dc_sink :
10495                 amdgpu_dm_connector->dc_em_sink;
10496
10497         if (!edid || !sink) {
10498                 dm_con_state = to_dm_connector_state(connector->state);
10499
10500                 amdgpu_dm_connector->min_vfreq = 0;
10501                 amdgpu_dm_connector->max_vfreq = 0;
10502                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10503                 connector->display_info.monitor_range.min_vfreq = 0;
10504                 connector->display_info.monitor_range.max_vfreq = 0;
10505                 freesync_capable = false;
10506
10507                 goto update;
10508         }
10509
10510         dm_con_state = to_dm_connector_state(connector->state);
10511
10512         if (!adev->dm.freesync_module)
10513                 goto update;
10514
10515         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10516                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10517                 bool edid_check_required = false;
10518
10519                 if (edid) {
10520                         edid_check_required = is_dp_capable_without_timing_msa(
10521                                                 adev->dm.dc,
10522                                                 amdgpu_dm_connector);
10523                 }
10524
10525                 if (edid_check_required == true && (edid->version > 1 ||
10526                    (edid->version == 1 && edid->revision > 1))) {
10527                         for (i = 0; i < 4; i++) {
10528
10529                                 timing  = &edid->detailed_timings[i];
10530                                 data    = &timing->data.other_data;
10531                                 range   = &data->data.range;
10532                                 /*
10533                                  * Check if monitor has continuous frequency mode
10534                                  */
10535                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10536                                         continue;
10537                                 /*
10538                                  * Check for flag range limits only. If flag == 1 then
10539                                  * no additional timing information provided.
10540                                  * Default GTF, GTF Secondary curve and CVT are not
10541                                  * supported
10542                                  */
10543                                 if (range->flags != 1)
10544                                         continue;
10545
10546                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10547                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10548                                 amdgpu_dm_connector->pixel_clock_mhz =
10549                                         range->pixel_clock_mhz * 10;
10550
10551                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10552                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10553
10554                                 break;
10555                         }
10556
10557                         if (amdgpu_dm_connector->max_vfreq -
10558                             amdgpu_dm_connector->min_vfreq > 10) {
10559
10560                                 freesync_capable = true;
10561                         }
10562                 }
10563         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10564                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10565                 if (i >= 0 && vsdb_info.freesync_supported) {
10566                         timing  = &edid->detailed_timings[i];
10567                         data    = &timing->data.other_data;
10568
10569                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10570                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10571                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10572                                 freesync_capable = true;
10573
10574                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10575                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10576                 }
10577         }
10578
10579         as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10580
10581         if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10582                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10583                 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10584
10585                         amdgpu_dm_connector->pack_sdp_v1_3 = true;
10586                         amdgpu_dm_connector->as_type = as_type;
10587                         amdgpu_dm_connector->vsdb_info = vsdb_info;
10588
10589                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10590                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10591                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10592                                 freesync_capable = true;
10593
10594                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10595                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10596                 }
10597         }
10598
10599 update:
10600         if (dm_con_state)
10601                 dm_con_state->freesync_capable = freesync_capable;
10602
10603         if (connector->vrr_capable_property)
10604                 drm_connector_set_vrr_capable_property(connector,
10605                                                        freesync_capable);
10606 }
10607
10608 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10609 {
10610         struct amdgpu_device *adev = drm_to_adev(dev);
10611         struct dc *dc = adev->dm.dc;
10612         int i;
10613
10614         mutex_lock(&adev->dm.dc_lock);
10615         if (dc->current_state) {
10616                 for (i = 0; i < dc->current_state->stream_count; ++i)
10617                         dc->current_state->streams[i]
10618                                 ->triggered_crtc_reset.enabled =
10619                                 adev->dm.force_timing_sync;
10620
10621                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10622                 dc_trigger_sync(dc, dc->current_state);
10623         }
10624         mutex_unlock(&adev->dm.dc_lock);
10625 }
10626
10627 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10628                        u32 value, const char *func_name)
10629 {
10630 #ifdef DM_CHECK_ADDR_0
10631         if (address == 0) {
10632                 DC_ERR("invalid register write. address = 0");
10633                 return;
10634         }
10635 #endif
10636         cgs_write_register(ctx->cgs_device, address, value);
10637         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10638 }
10639
10640 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10641                           const char *func_name)
10642 {
10643         u32 value;
10644 #ifdef DM_CHECK_ADDR_0
10645         if (address == 0) {
10646                 DC_ERR("invalid register read; address = 0\n");
10647                 return 0;
10648         }
10649 #endif
10650
10651         if (ctx->dmub_srv &&
10652             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10653             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10654                 ASSERT(false);
10655                 return 0;
10656         }
10657
10658         value = cgs_read_register(ctx->cgs_device, address);
10659
10660         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10661
10662         return value;
10663 }
10664
10665 int amdgpu_dm_process_dmub_aux_transfer_sync(
10666                 struct dc_context *ctx,
10667                 unsigned int link_index,
10668                 struct aux_payload *payload,
10669                 enum aux_return_code_type *operation_result)
10670 {
10671         struct amdgpu_device *adev = ctx->driver_context;
10672         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10673         int ret = -1;
10674
10675         mutex_lock(&adev->dm.dpia_aux_lock);
10676         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10677                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10678                 goto out;
10679         }
10680
10681         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10682                 DRM_ERROR("wait_for_completion_timeout timeout!");
10683                 *operation_result = AUX_RET_ERROR_TIMEOUT;
10684                 goto out;
10685         }
10686
10687         if (p_notify->result != AUX_RET_SUCCESS) {
10688                 /*
10689                  * Transient states before tunneling is enabled could
10690                  * lead to this error. We can ignore this for now.
10691                  */
10692                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10693                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10694                                         payload->address, payload->length,
10695                                         p_notify->result);
10696                 }
10697                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10698                 goto out;
10699         }
10700
10701
10702         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10703         if (!payload->write && p_notify->aux_reply.length &&
10704                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10705
10706                 if (payload->length != p_notify->aux_reply.length) {
10707                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10708                                 p_notify->aux_reply.length,
10709                                         payload->address, payload->length);
10710                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10711                         goto out;
10712                 }
10713
10714                 memcpy(payload->data, p_notify->aux_reply.data,
10715                                 p_notify->aux_reply.length);
10716         }
10717
10718         /* success */
10719         ret = p_notify->aux_reply.length;
10720         *operation_result = p_notify->result;
10721 out:
10722         reinit_completion(&adev->dm.dmub_aux_transfer_done);
10723         mutex_unlock(&adev->dm.dpia_aux_lock);
10724         return ret;
10725 }
10726
10727 int amdgpu_dm_process_dmub_set_config_sync(
10728                 struct dc_context *ctx,
10729                 unsigned int link_index,
10730                 struct set_config_cmd_payload *payload,
10731                 enum set_config_status *operation_result)
10732 {
10733         struct amdgpu_device *adev = ctx->driver_context;
10734         bool is_cmd_complete;
10735         int ret;
10736
10737         mutex_lock(&adev->dm.dpia_aux_lock);
10738         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10739                         link_index, payload, adev->dm.dmub_notify);
10740
10741         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10742                 ret = 0;
10743                 *operation_result = adev->dm.dmub_notify->sc_status;
10744         } else {
10745                 DRM_ERROR("wait_for_completion_timeout timeout!");
10746                 ret = -1;
10747                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10748         }
10749
10750         if (!is_cmd_complete)
10751                 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10752         mutex_unlock(&adev->dm.dpia_aux_lock);
10753         return ret;
10754 }
10755
10756 /*
10757  * Check whether seamless boot is supported.
10758  *
10759  * So far we only support seamless boot on CHIP_VANGOGH.
10760  * If everything goes well, we may consider expanding
10761  * seamless boot to other ASICs.
10762  */
10763 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10764 {
10765         switch (adev->ip_versions[DCE_HWIP][0]) {
10766         case IP_VERSION(3, 0, 1):
10767                 if (!adev->mman.keep_stolen_vga_memory)
10768                         return true;
10769                 break;
10770         default:
10771                 break;
10772         }
10773
10774         return false;
10775 }