drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "link_enc_cfg.h"
  32 #include "dc/inc/core_types.h"
  33 #include "dal_asic_id.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "dc/inc/hw/dmcu.h"
  36 #include "dc/inc/hw/abm.h"
  37 #include "dc/dc_dmub_srv.h"
  38 #include "dc/dc_edid_parser.h"
  39 #include "dc/dc_stat.h"
  40 #include "amdgpu_dm_trace.h"
  41 #include "dpcd_defs.h"
  42 #include "link/protocols/link_dpcd.h"
  43 #include "link_service_types.h"
  44 #include "link/protocols/link_dp_capability.h"
  45 #include "link/protocols/link_ddc.h"
  46
  47 #include "vid.h"
  48 #include "amdgpu.h"
  49 #include "amdgpu_display.h"
  50 #include "amdgpu_ucode.h"
  51 #include "atom.h"
  52 #include "amdgpu_dm.h"
  53 #include "amdgpu_dm_plane.h"
  54 #include "amdgpu_dm_crtc.h"
  55 #include "amdgpu_dm_hdcp.h"
  56 #include <drm/display/drm_hdcp_helper.h>
  57 #include "amdgpu_pm.h"
  58 #include "amdgpu_atombios.h"
  59
  60 #include "amd_shared.h"
  61 #include "amdgpu_dm_irq.h"
  62 #include "dm_helpers.h"
  63 #include "amdgpu_dm_mst_types.h"
  64 #if defined(CONFIG_DEBUG_FS)
  65 #include "amdgpu_dm_debugfs.h"
  66 #endif
  67 #include "amdgpu_dm_psr.h"
  68
  69 #include "ivsrcid/ivsrcid_vislands30.h"
  70
  71 #include <linux/backlight.h>
  72 #include <linux/module.h>
  73 #include <linux/moduleparam.h>
  74 #include <linux/types.h>
  75 #include <linux/pm_runtime.h>
  76 #include <linux/pci.h>
  77 #include <linux/firmware.h>
  78 #include <linux/component.h>
  79 #include <linux/dmi.h>
  80
  81 #include <drm/display/drm_dp_mst_helper.h>
  82 #include <drm/display/drm_hdmi_helper.h>
  83 #include <drm/drm_atomic.h>
  84 #include <drm/drm_atomic_uapi.h>
  85 #include <drm/drm_atomic_helper.h>
  86 #include <drm/drm_blend.h>
  87 #include <drm/drm_fourcc.h>
  88 #include <drm/drm_edid.h>
  89 #include <drm/drm_vblank.h>
  90 #include <drm/drm_audio_component.h>
  91 #include <drm/drm_gem_atomic_helper.h>
  92 #include <drm/drm_plane_helper.h>
  93
  94 #include <acpi/video.h>
  95
  96 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  97
  98 #include "dcn/dcn_1_0_offset.h"
  99 #include "dcn/dcn_1_0_sh_mask.h"
 100 #include "soc15_hw_ip.h"
 101 #include "soc15_common.h"
 102 #include "vega10_ip_offset.h"
 103
 104 #include "gc/gc_11_0_0_offset.h"
 105 #include "gc/gc_11_0_0_sh_mask.h"
 106
 107 #include "modules/inc/mod_freesync.h"
 108 #include "modules/power/power_helpers.h"
 109
 110 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 111 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 112 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 113 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 114 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 115 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 116 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 117 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 118 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 119 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 120 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 121 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 122 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 123 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 124 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 125 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 126 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 127 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 128 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 129 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 130 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 131 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 132
 133 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 134 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 135 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 137
 138 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 139 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 140
 141 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 142 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 143
 144 /* Number of bytes in PSP header for firmware. */
 145 #define PSP_HEADER_BYTES 0x100
 146
 147 /* Number of bytes in PSP footer for firmware. */
 148 #define PSP_FOOTER_BYTES 0x100
 149
 150 /**
 151  * DOC: overview
 152  *
 153  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 154  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 155  * requests into DC requests, and DC responses into DRM responses.
 156  *
 157  * The root control structure is &struct amdgpu_display_manager.
 158  */
 159
 160 /* basic init/fini API */
 161 static int amdgpu_dm_init(struct amdgpu_device *adev);
 162 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 163 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 164
 165 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 166 {
 167         switch (link->dpcd_caps.dongle_type) {
 168         case DISPLAY_DONGLE_NONE:
 169                 return DRM_MODE_SUBCONNECTOR_Native;
 170         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 171                 return DRM_MODE_SUBCONNECTOR_VGA;
 172         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 173         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 174                 return DRM_MODE_SUBCONNECTOR_DVID;
 175         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 176         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 177                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 178         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 179         default:
 180                 return DRM_MODE_SUBCONNECTOR_Unknown;
 181         }
 182 }
 183
 184 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 185 {
 186         struct dc_link *link = aconnector->dc_link;
 187         struct drm_connector *connector = &aconnector->base;
 188         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 189
 190         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 191                 return;
 192
 193         if (aconnector->dc_sink)
 194                 subconnector = get_subconnector_type(link);
 195
 196         drm_object_property_set_value(&connector->base,
 197                         connector->dev->mode_config.dp_subconnector_property,
 198                         subconnector);
 199 }
 200
 201 /*
 202  * initializes drm_device display related structures, based on the information
 203  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 204  * drm_encoder, drm_mode_config
 205  *
 206  * Returns 0 on success
 207  */
 208 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 209 /* removes and deallocates the drm structures, created by the above function */
 210 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 211
 212 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 213                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 214                                     u32 link_index,
 215                                     struct amdgpu_encoder *amdgpu_encoder);
 216 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 217                                   struct amdgpu_encoder *aencoder,
 218                                   uint32_t link_index);
 219
 220 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 221
 222 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 223
 224 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 225                                   struct drm_atomic_state *state);
 226
 227 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 228 static void handle_hpd_rx_irq(void *param);
 229
 230 static bool
 231 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 232                                  struct drm_crtc_state *new_crtc_state);
 233 /*
 234  * dm_vblank_get_counter
 235  *
 236  * @brief
 237  * Get counter for number of vertical blanks
 238  *
 239  * @param
 240  * struct amdgpu_device *adev - [in] desired amdgpu device
 241  * int disp_idx - [in] which CRTC to get the counter from
 242  *
 243  * @return
 244  * Counter for vertical blanks
 245  */
 246 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 247 {
 248         if (crtc >= adev->mode_info.num_crtc)
 249                 return 0;
 250         else {
 251                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 252
 253                 if (acrtc->dm_irq_params.stream == NULL) {
 254                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 255                                   crtc);
 256                         return 0;
 257                 }
 258
 259                 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 260         }
 261 }
 262
 263 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 264                                   u32 *vbl, u32 *position)
 265 {
 266         u32 v_blank_start, v_blank_end, h_position, v_position;
 267
 268         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 269                 return -EINVAL;
 270         else {
 271                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 272
 273                 if (acrtc->dm_irq_params.stream ==  NULL) {
 274                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 275                                   crtc);
 276                         return 0;
 277                 }
 278
 279                 /*
 280                  * TODO rework base driver to use values directly.
 281                  * for now parse it back into reg-format
 282                  */
 283                 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 284                                          &v_blank_start,
 285                                          &v_blank_end,
 286                                          &h_position,
 287                                          &v_position);
 288
 289                 *position = v_position | (h_position << 16);
 290                 *vbl = v_blank_start | (v_blank_end << 16);
 291         }
 292
 293         return 0;
 294 }
 295
 296 static bool dm_is_idle(void *handle)
 297 {
 298         /* XXX todo */
 299         return true;
 300 }
 301
 302 static int dm_wait_for_idle(void *handle)
 303 {
 304         /* XXX todo */
 305         return 0;
 306 }
 307
 308 static bool dm_check_soft_reset(void *handle)
 309 {
 310         return false;
 311 }
 312
 313 static int dm_soft_reset(void *handle)
 314 {
 315         /* XXX todo */
 316         return 0;
 317 }
 318
 319 static struct amdgpu_crtc *
 320 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 321                      int otg_inst)
 322 {
 323         struct drm_device *dev = adev_to_drm(adev);
 324         struct drm_crtc *crtc;
 325         struct amdgpu_crtc *amdgpu_crtc;
 326
 327         if (WARN_ON(otg_inst == -1))
 328                 return adev->mode_info.crtcs[0];
 329
 330         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 331                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 332
 333                 if (amdgpu_crtc->otg_inst == otg_inst)
 334                         return amdgpu_crtc;
 335         }
 336
 337         return NULL;
 338 }
 339
 340 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 341                                               struct dm_crtc_state *new_state)
 342 {
 343         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 344                 return true;
 345         else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
 346                 return true;
 347         else
 348                 return false;
 349 }
 350
 351 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
 352                                         int planes_count)
 353 {
 354         int i, j;
 355
 356         for (i = 0, j = planes_count - 1; i < j; i++, j--)
 357                 swap(array_of_surface_update[i], array_of_surface_update[j]);
 358 }
 359
 360 /**
 361  * update_planes_and_stream_adapter() - Send planes to be updated in DC
 362  *
 363  * DC has a generic way to update planes and stream via
 364  * dc_update_planes_and_stream function; however, DM might need some
 365  * adjustments and preparation before calling it. This function is a wrapper
 366  * for the dc_update_planes_and_stream that does any required configuration
 367  * before passing control to DC.
 368  */
 369 static inline bool update_planes_and_stream_adapter(struct dc *dc,
 370                                                     int update_type,
 371                                                     int planes_count,
 372                                                     struct dc_stream_state *stream,
 373                                                     struct dc_stream_update *stream_update,
 374                                                     struct dc_surface_update *array_of_surface_update)
 375 {
 376         reverse_planes_order(array_of_surface_update, planes_count);
 377
 378         /*
 379          * Previous frame finished and HW is ready for optimization.
 380          */
 381         if (update_type == UPDATE_TYPE_FAST)
 382                 dc_post_update_surfaces_to_stream(dc);
 383
 384         return dc_update_planes_and_stream(dc,
 385                                            array_of_surface_update,
 386                                            planes_count,
 387                                            stream,
 388                                            stream_update);
 389 }
 390
 391 /**
 392  * dm_pflip_high_irq() - Handle pageflip interrupt
 393  * @interrupt_params: ignored
 394  *
 395  * Handles the pageflip interrupt by notifying all interested parties
 396  * that the pageflip has been completed.
 397  */
 398 static void dm_pflip_high_irq(void *interrupt_params)
 399 {
 400         struct amdgpu_crtc *amdgpu_crtc;
 401         struct common_irq_params *irq_params = interrupt_params;
 402         struct amdgpu_device *adev = irq_params->adev;
 403         unsigned long flags;
 404         struct drm_pending_vblank_event *e;
 405         u32 vpos, hpos, v_blank_start, v_blank_end;
 406         bool vrr_active;
 407
 408         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 409
 410         /* IRQ could occur when in initial stage */
 411         /* TODO work and BO cleanup */
 412         if (amdgpu_crtc == NULL) {
 413                 DC_LOG_PFLIP("CRTC is null, returning.\n");
 414                 return;
 415         }
 416
 417         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 418
 419         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 420                 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 421                                                  amdgpu_crtc->pflip_status,
 422                                                  AMDGPU_FLIP_SUBMITTED,
 423                                                  amdgpu_crtc->crtc_id,
 424                                                  amdgpu_crtc);
 425                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 426                 return;
 427         }
 428
 429         /* page flip completed. */
 430         e = amdgpu_crtc->event;
 431         amdgpu_crtc->event = NULL;
 432
 433         WARN_ON(!e);
 434
 435         vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
 436
 437         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 438         if (!vrr_active ||
 439             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 440                                       &v_blank_end, &hpos, &vpos) ||
 441             (vpos < v_blank_start)) {
 442                 /* Update to correct count and vblank timestamp if racing with
 443                  * vblank irq. This also updates to the correct vblank timestamp
 444                  * even in VRR mode, as scanout is past the front-porch atm.
 445                  */
 446                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 447
 448                 /* Wake up userspace by sending the pageflip event with proper
 449                  * count and timestamp of vblank of flip completion.
 450                  */
 451                 if (e) {
 452                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 453
 454                         /* Event sent, so done with vblank for this flip */
 455                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 456                 }
 457         } else if (e) {
 458                 /* VRR active and inside front-porch: vblank count and
 459                  * timestamp for pageflip event will only be up to date after
 460                  * drm_crtc_handle_vblank() has been executed from late vblank
 461                  * irq handler after start of back-porch (vline 0). We queue the
 462                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 463                  * updated timestamp and count, once it runs after us.
 464                  *
 465                  * We need to open-code this instead of using the helper
 466                  * drm_crtc_arm_vblank_event(), as that helper would
 467                  * call drm_crtc_accurate_vblank_count(), which we must
 468                  * not call in VRR mode while we are in front-porch!
 469                  */
 470
 471                 /* sequence will be replaced by real count during send-out. */
 472                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 473                 e->pipe = amdgpu_crtc->crtc_id;
 474
 475                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 476                 e = NULL;
 477         }
 478
 479         /* Keep track of vblank of this flip for flip throttling. We use the
 480          * cooked hw counter, as that one incremented at start of this vblank
 481          * of pageflip completion, so last_flip_vblank is the forbidden count
 482          * for queueing new pageflips if vsync + VRR is enabled.
 483          */
 484         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 485                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 486
 487         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 488         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 489
 490         DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 491                      amdgpu_crtc->crtc_id, amdgpu_crtc,
 492                      vrr_active, (int) !e);
 493 }
 494
 495 static void dm_vupdate_high_irq(void *interrupt_params)
 496 {
 497         struct common_irq_params *irq_params = interrupt_params;
 498         struct amdgpu_device *adev = irq_params->adev;
 499         struct amdgpu_crtc *acrtc;
 500         struct drm_device *drm_dev;
 501         struct drm_vblank_crtc *vblank;
 502         ktime_t frame_duration_ns, previous_timestamp;
 503         unsigned long flags;
 504         int vrr_active;
 505
 506         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 507
 508         if (acrtc) {
 509                 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 510                 drm_dev = acrtc->base.dev;
 511                 vblank = &drm_dev->vblank[acrtc->base.index];
 512                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 513                 frame_duration_ns = vblank->time - previous_timestamp;
 514
 515                 if (frame_duration_ns > 0) {
 516                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 517                                                 frame_duration_ns,
 518                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 519                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 520                 }
 521
 522                 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
 523                               acrtc->crtc_id,
 524                               vrr_active);
 525
 526                 /* Core vblank handling is done here after end of front-porch in
 527                  * vrr mode, as vblank timestamping will give valid results
 528                  * while now done after front-porch. This will also deliver
 529                  * page-flip completion events that have been queued to us
 530                  * if a pageflip happened inside front-porch.
 531                  */
 532                 if (vrr_active) {
 533                         amdgpu_dm_crtc_handle_vblank(acrtc);
 534
 535                         /* BTR processing for pre-DCE12 ASICs */
 536                         if (acrtc->dm_irq_params.stream &&
 537                             adev->family < AMDGPU_FAMILY_AI) {
 538                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 539                                 mod_freesync_handle_v_update(
 540                                     adev->dm.freesync_module,
 541                                     acrtc->dm_irq_params.stream,
 542                                     &acrtc->dm_irq_params.vrr_params);
 543
 544                                 dc_stream_adjust_vmin_vmax(
 545                                     adev->dm.dc,
 546                                     acrtc->dm_irq_params.stream,
 547                                     &acrtc->dm_irq_params.vrr_params.adjust);
 548                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 549                         }
 550                 }
 551         }
 552 }
 553
 554 /**
 555  * dm_crtc_high_irq() - Handles CRTC interrupt
 556  * @interrupt_params: used for determining the CRTC instance
 557  *
 558  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 559  * event handler.
 560  */
 561 static void dm_crtc_high_irq(void *interrupt_params)
 562 {
 563         struct common_irq_params *irq_params = interrupt_params;
 564         struct amdgpu_device *adev = irq_params->adev;
 565         struct amdgpu_crtc *acrtc;
 566         unsigned long flags;
 567         int vrr_active;
 568
 569         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 570         if (!acrtc)
 571                 return;
 572
 573         vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 574
 575         DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 576                       vrr_active, acrtc->dm_irq_params.active_planes);
 577
 578         /**
 579          * Core vblank handling at start of front-porch is only possible
 580          * in non-vrr mode, as only there vblank timestamping will give
 581          * valid results while done in front-porch. Otherwise defer it
 582          * to dm_vupdate_high_irq after end of front-porch.
 583          */
 584         if (!vrr_active)
 585                 amdgpu_dm_crtc_handle_vblank(acrtc);
 586
 587         /**
 588          * Following stuff must happen at start of vblank, for crc
 589          * computation and below-the-range btr support in vrr mode.
 590          */
 591         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 592
 593         /* BTR updates need to happen before VUPDATE on Vega and above. */
 594         if (adev->family < AMDGPU_FAMILY_AI)
 595                 return;
 596
 597         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 598
 599         if (acrtc->dm_irq_params.stream &&
 600             acrtc->dm_irq_params.vrr_params.supported &&
 601             acrtc->dm_irq_params.freesync_config.state ==
 602                     VRR_STATE_ACTIVE_VARIABLE) {
 603                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 604                                              acrtc->dm_irq_params.stream,
 605                                              &acrtc->dm_irq_params.vrr_params);
 606
 607                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 608                                            &acrtc->dm_irq_params.vrr_params.adjust);
 609         }
 610
 611         /*
 612          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 613          * In that case, pageflip completion interrupts won't fire and pageflip
 614          * completion events won't get delivered. Prevent this by sending
 615          * pending pageflip events from here if a flip is still pending.
 616          *
 617          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 618          * avoid race conditions between flip programming and completion,
 619          * which could cause too early flip completion events.
 620          */
 621         if (adev->family >= AMDGPU_FAMILY_RV &&
 622             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 623             acrtc->dm_irq_params.active_planes == 0) {
 624                 if (acrtc->event) {
 625                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 626                         acrtc->event = NULL;
 627                         drm_crtc_vblank_put(&acrtc->base);
 628                 }
 629                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 630         }
 631
 632         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 633 }
 634
 635 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 636 /**
 637  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 638  * DCN generation ASICs
 639  * @interrupt_params: interrupt parameters
 640  *
 641  * Used to set crc window/read out crc value at vertical line 0 position
 642  */
 643 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 644 {
 645         struct common_irq_params *irq_params = interrupt_params;
 646         struct amdgpu_device *adev = irq_params->adev;
 647         struct amdgpu_crtc *acrtc;
 648
 649         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 650
 651         if (!acrtc)
 652                 return;
 653
 654         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 655 }
 656 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 657
 658 /**
 659  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 660  * @adev: amdgpu_device pointer
 661  * @notify: dmub notification structure
 662  *
 663  * Dmub AUX or SET_CONFIG command completion processing callback
 664  * Copies dmub notification to DM which is to be read by AUX command.
 665  * issuing thread and also signals the event to wake up the thread.
 666  */
 667 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 668                                         struct dmub_notification *notify)
 669 {
 670         if (adev->dm.dmub_notify)
 671                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 672         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 673                 complete(&adev->dm.dmub_aux_transfer_done);
 674 }
 675
 676 /**
 677  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 678  * @adev: amdgpu_device pointer
 679  * @notify: dmub notification structure
 680  *
 681  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 682  * ink index and calls helper to do the processing.
 683  */
 684 static void dmub_hpd_callback(struct amdgpu_device *adev,
 685                               struct dmub_notification *notify)
 686 {
 687         struct amdgpu_dm_connector *aconnector;
 688         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 689         struct drm_connector *connector;
 690         struct drm_connector_list_iter iter;
 691         struct dc_link *link;
 692         u8 link_index = 0;
 693         struct drm_device *dev;
 694
 695         if (adev == NULL)
 696                 return;
 697
 698         if (notify == NULL) {
 699                 DRM_ERROR("DMUB HPD callback notification was NULL");
 700                 return;
 701         }
 702
 703         if (notify->link_index > adev->dm.dc->link_count) {
 704                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 705                 return;
 706         }
 707
 708         link_index = notify->link_index;
 709         link = adev->dm.dc->links[link_index];
 710         dev = adev->dm.ddev;
 711
 712         drm_connector_list_iter_begin(dev, &iter);
 713         drm_for_each_connector_iter(connector, &iter) {
 714                 aconnector = to_amdgpu_dm_connector(connector);
 715                 if (link && aconnector->dc_link == link) {
 716                         if (notify->type == DMUB_NOTIFICATION_HPD)
 717                                 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 718                         else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 719                                 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
 720                         else
 721                                 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
 722                                                 notify->type, link_index);
 723
 724                         hpd_aconnector = aconnector;
 725                         break;
 726                 }
 727         }
 728         drm_connector_list_iter_end(&iter);
 729
 730         if (hpd_aconnector) {
 731                 if (notify->type == DMUB_NOTIFICATION_HPD)
 732                         handle_hpd_irq_helper(hpd_aconnector);
 733                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 734                         handle_hpd_rx_irq(hpd_aconnector);
 735         }
 736 }
 737
 738 /**
 739  * register_dmub_notify_callback - Sets callback for DMUB notify
 740  * @adev: amdgpu_device pointer
 741  * @type: Type of dmub notification
 742  * @callback: Dmub interrupt callback function
 743  * @dmub_int_thread_offload: offload indicator
 744  *
 745  * API to register a dmub callback handler for a dmub notification
 746  * Also sets indicator whether callback processing to be offloaded.
 747  * to dmub interrupt handling thread
 748  * Return: true if successfully registered, false if there is existing registration
 749  */
 750 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 751                                           enum dmub_notification_type type,
 752                                           dmub_notify_interrupt_callback_t callback,
 753                                           bool dmub_int_thread_offload)
 754 {
 755         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 756                 adev->dm.dmub_callback[type] = callback;
 757                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 758         } else
 759                 return false;
 760
 761         return true;
 762 }
 763
 764 static void dm_handle_hpd_work(struct work_struct *work)
 765 {
 766         struct dmub_hpd_work *dmub_hpd_wrk;
 767
 768         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 769
 770         if (!dmub_hpd_wrk->dmub_notify) {
 771                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 772                 return;
 773         }
 774
 775         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 776                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 777                 dmub_hpd_wrk->dmub_notify);
 778         }
 779
 780         kfree(dmub_hpd_wrk->dmub_notify);
 781         kfree(dmub_hpd_wrk);
 782
 783 }
 784
 785 #define DMUB_TRACE_MAX_READ 64
 786 /**
 787  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 788  * @interrupt_params: used for determining the Outbox instance
 789  *
 790  * Handles the Outbox Interrupt
 791  * event handler.
 792  */
 793 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 794 {
 795         struct dmub_notification notify;
 796         struct common_irq_params *irq_params = interrupt_params;
 797         struct amdgpu_device *adev = irq_params->adev;
 798         struct amdgpu_display_manager *dm = &adev->dm;
 799         struct dmcub_trace_buf_entry entry = { 0 };
 800         u32 count = 0;
 801         struct dmub_hpd_work *dmub_hpd_wrk;
 802         struct dc_link *plink = NULL;
 803
 804         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 805                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 806
 807                 do {
 808                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 809                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 810                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 811                                 continue;
 812                         }
 813                         if (!dm->dmub_callback[notify.type]) {
 814                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 815                                 continue;
 816                         }
 817                         if (dm->dmub_thread_offload[notify.type] == true) {
 818                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 819                                 if (!dmub_hpd_wrk) {
 820                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 821                                         return;
 822                                 }
 823                                 dmub_hpd_wrk->dmub_notify = kmemdup(&notify, sizeof(struct dmub_notification),
 824                                                                     GFP_ATOMIC);
 825                                 if (!dmub_hpd_wrk->dmub_notify) {
 826                                         kfree(dmub_hpd_wrk);
 827                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 828                                         return;
 829                                 }
 830                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 831                                 dmub_hpd_wrk->adev = adev;
 832                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 833                                         plink = adev->dm.dc->links[notify.link_index];
 834                                         if (plink) {
 835                                                 plink->hpd_status =
 836                                                         notify.hpd_status == DP_HPD_PLUG;
 837                                         }
 838                                 }
 839                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 840                         } else {
 841                                 dm->dmub_callback[notify.type](adev, &notify);
 842                         }
 843                 } while (notify.pending_notification);
 844         }
 845
 846
 847         do {
 848                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 849                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 850                                                         entry.param0, entry.param1);
 851
 852                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 853                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 854                 } else
 855                         break;
 856
 857                 count++;
 858
 859         } while (count <= DMUB_TRACE_MAX_READ);
 860
 861         if (count > DMUB_TRACE_MAX_READ)
 862                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 863 }
 864
 865 static int dm_set_clockgating_state(void *handle,
 866                   enum amd_clockgating_state state)
 867 {
 868         return 0;
 869 }
 870
 871 static int dm_set_powergating_state(void *handle,
 872                   enum amd_powergating_state state)
 873 {
 874         return 0;
 875 }
 876
 877 /* Prototypes of private functions */
 878 static int dm_early_init(void* handle);
 879
 880 /* Allocate memory for FBC compressed data  */
 881 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 882 {
 883         struct drm_device *dev = connector->dev;
 884         struct amdgpu_device *adev = drm_to_adev(dev);
 885         struct dm_compressor_info *compressor = &adev->dm.compressor;
 886         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 887         struct drm_display_mode *mode;
 888         unsigned long max_size = 0;
 889
 890         if (adev->dm.dc->fbc_compressor == NULL)
 891                 return;
 892
 893         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 894                 return;
 895
 896         if (compressor->bo_ptr)
 897                 return;
 898
 899
 900         list_for_each_entry(mode, &connector->modes, head) {
 901                 if (max_size < mode->htotal * mode->vtotal)
 902                         max_size = mode->htotal * mode->vtotal;
 903         }
 904
 905         if (max_size) {
 906                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 907                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 908                             &compressor->gpu_addr, &compressor->cpu_addr);
 909
 910                 if (r)
 911                         DRM_ERROR("DM: Failed to initialize FBC\n");
 912                 else {
 913                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 914                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 915                 }
 916
 917         }
 918
 919 }
 920
 921 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 922                                           int pipe, bool *enabled,
 923                                           unsigned char *buf, int max_bytes)
 924 {
 925         struct drm_device *dev = dev_get_drvdata(kdev);
 926         struct amdgpu_device *adev = drm_to_adev(dev);
 927         struct drm_connector *connector;
 928         struct drm_connector_list_iter conn_iter;
 929         struct amdgpu_dm_connector *aconnector;
 930         int ret = 0;
 931
 932         *enabled = false;
 933
 934         mutex_lock(&adev->dm.audio_lock);
 935
 936         drm_connector_list_iter_begin(dev, &conn_iter);
 937         drm_for_each_connector_iter(connector, &conn_iter) {
 938                 aconnector = to_amdgpu_dm_connector(connector);
 939                 if (aconnector->audio_inst != port)
 940                         continue;
 941
 942                 *enabled = true;
 943                 ret = drm_eld_size(connector->eld);
 944                 memcpy(buf, connector->eld, min(max_bytes, ret));
 945
 946                 break;
 947         }
 948         drm_connector_list_iter_end(&conn_iter);
 949
 950         mutex_unlock(&adev->dm.audio_lock);
 951
 952         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 953
 954         return ret;
 955 }
 956
 957 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 958         .get_eld = amdgpu_dm_audio_component_get_eld,
 959 };
 960
 961 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 962                                        struct device *hda_kdev, void *data)
 963 {
 964         struct drm_device *dev = dev_get_drvdata(kdev);
 965         struct amdgpu_device *adev = drm_to_adev(dev);
 966         struct drm_audio_component *acomp = data;
 967
 968         acomp->ops = &amdgpu_dm_audio_component_ops;
 969         acomp->dev = kdev;
 970         adev->dm.audio_component = acomp;
 971
 972         return 0;
 973 }
 974
 975 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 976                                           struct device *hda_kdev, void *data)
 977 {
 978         struct drm_device *dev = dev_get_drvdata(kdev);
 979         struct amdgpu_device *adev = drm_to_adev(dev);
 980         struct drm_audio_component *acomp = data;
 981
 982         acomp->ops = NULL;
 983         acomp->dev = NULL;
 984         adev->dm.audio_component = NULL;
 985 }
 986
 987 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 988         .bind   = amdgpu_dm_audio_component_bind,
 989         .unbind = amdgpu_dm_audio_component_unbind,
 990 };
 991
 992 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
 993 {
 994         int i, ret;
 995
 996         if (!amdgpu_audio)
 997                 return 0;
 998
 999         adev->mode_info.audio.enabled = true;
1000
1001         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1002
1003         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1004                 adev->mode_info.audio.pin[i].channels = -1;
1005                 adev->mode_info.audio.pin[i].rate = -1;
1006                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1007                 adev->mode_info.audio.pin[i].status_bits = 0;
1008                 adev->mode_info.audio.pin[i].category_code = 0;
1009                 adev->mode_info.audio.pin[i].connected = false;
1010                 adev->mode_info.audio.pin[i].id =
1011                         adev->dm.dc->res_pool->audios[i]->inst;
1012                 adev->mode_info.audio.pin[i].offset = 0;
1013         }
1014
1015         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1016         if (ret < 0)
1017                 return ret;
1018
1019         adev->dm.audio_registered = true;
1020
1021         return 0;
1022 }
1023
1024 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1025 {
1026         if (!amdgpu_audio)
1027                 return;
1028
1029         if (!adev->mode_info.audio.enabled)
1030                 return;
1031
1032         if (adev->dm.audio_registered) {
1033                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1034                 adev->dm.audio_registered = false;
1035         }
1036
1037         /* TODO: Disable audio? */
1038
1039         adev->mode_info.audio.enabled = false;
1040 }
1041
1042 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1043 {
1044         struct drm_audio_component *acomp = adev->dm.audio_component;
1045
1046         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1047                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1048
1049                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1050                                                  pin, -1);
1051         }
1052 }
1053
1054 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1055 {
1056         const struct dmcub_firmware_header_v1_0 *hdr;
1057         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1058         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1059         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1060         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1061         struct abm *abm = adev->dm.dc->res_pool->abm;
1062         struct dmub_srv_hw_params hw_params;
1063         enum dmub_status status;
1064         const unsigned char *fw_inst_const, *fw_bss_data;
1065         u32 i, fw_inst_const_size, fw_bss_data_size;
1066         bool has_hw_support;
1067
1068         if (!dmub_srv)
1069                 /* DMUB isn't supported on the ASIC. */
1070                 return 0;
1071
1072         if (!fb_info) {
1073                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1074                 return -EINVAL;
1075         }
1076
1077         if (!dmub_fw) {
1078                 /* Firmware required for DMUB support. */
1079                 DRM_ERROR("No firmware provided for DMUB.\n");
1080                 return -EINVAL;
1081         }
1082
1083         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1084         if (status != DMUB_STATUS_OK) {
1085                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1086                 return -EINVAL;
1087         }
1088
1089         if (!has_hw_support) {
1090                 DRM_INFO("DMUB unsupported on ASIC\n");
1091                 return 0;
1092         }
1093
1094         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1095         status = dmub_srv_hw_reset(dmub_srv);
1096         if (status != DMUB_STATUS_OK)
1097                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1098
1099         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1100
1101         fw_inst_const = dmub_fw->data +
1102                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1103                         PSP_HEADER_BYTES;
1104
1105         fw_bss_data = dmub_fw->data +
1106                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1107                       le32_to_cpu(hdr->inst_const_bytes);
1108
1109         /* Copy firmware and bios info into FB memory. */
1110         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1111                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1112
1113         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1114
1115         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1116          * amdgpu_ucode_init_single_fw will load dmub firmware
1117          * fw_inst_const part to cw0; otherwise, the firmware back door load
1118          * will be done by dm_dmub_hw_init
1119          */
1120         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1121                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1122                                 fw_inst_const_size);
1123         }
1124
1125         if (fw_bss_data_size)
1126                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1127                        fw_bss_data, fw_bss_data_size);
1128
1129         /* Copy firmware bios info into FB memory. */
1130         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1131                adev->bios_size);
1132
1133         /* Reset regions that need to be reset. */
1134         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1135         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1136
1137         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1138                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1139
1140         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1141                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1142
1143         /* Initialize hardware. */
1144         memset(&hw_params, 0, sizeof(hw_params));
1145         hw_params.fb_base = adev->gmc.fb_start;
1146         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1147
1148         /* backdoor load firmware and trigger dmub running */
1149         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1150                 hw_params.load_inst_const = true;
1151
1152         if (dmcu)
1153                 hw_params.psp_version = dmcu->psp_version;
1154
1155         for (i = 0; i < fb_info->num_fb; ++i)
1156                 hw_params.fb[i] = &fb_info->fb[i];
1157
1158         switch (adev->ip_versions[DCE_HWIP][0]) {
1159         case IP_VERSION(3, 1, 3):
1160         case IP_VERSION(3, 1, 4):
1161                 hw_params.dpia_supported = true;
1162                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1163                 break;
1164         default:
1165                 break;
1166         }
1167
1168         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1169         if (status != DMUB_STATUS_OK) {
1170                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1171                 return -EINVAL;
1172         }
1173
1174         /* Wait for firmware load to finish. */
1175         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1176         if (status != DMUB_STATUS_OK)
1177                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1178
1179         /* Init DMCU and ABM if available. */
1180         if (dmcu && abm) {
1181                 dmcu->funcs->dmcu_init(dmcu);
1182                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1183         }
1184
1185         if (!adev->dm.dc->ctx->dmub_srv)
1186                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1187         if (!adev->dm.dc->ctx->dmub_srv) {
1188                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1189                 return -ENOMEM;
1190         }
1191
1192         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1193                  adev->dm.dmcub_fw_version);
1194
1195         return 0;
1196 }
1197
1198 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1199 {
1200         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1201         enum dmub_status status;
1202         bool init;
1203
1204         if (!dmub_srv) {
1205                 /* DMUB isn't supported on the ASIC. */
1206                 return;
1207         }
1208
1209         status = dmub_srv_is_hw_init(dmub_srv, &init);
1210         if (status != DMUB_STATUS_OK)
1211                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1212
1213         if (status == DMUB_STATUS_OK && init) {
1214                 /* Wait for firmware load to finish. */
1215                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1216                 if (status != DMUB_STATUS_OK)
1217                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1218         } else {
1219                 /* Perform the full hardware initialization. */
1220                 dm_dmub_hw_init(adev);
1221         }
1222 }
1223
1224 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1225 {
1226         u64 pt_base;
1227         u32 logical_addr_low;
1228         u32 logical_addr_high;
1229         u32 agp_base, agp_bot, agp_top;
1230         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1231
1232         memset(pa_config, 0, sizeof(*pa_config));
1233
1234         agp_base = 0;
1235         agp_bot = adev->gmc.agp_start >> 24;
1236         agp_top = adev->gmc.agp_end >> 24;
1237
1238         /* AGP aperture is disabled */
1239         if (agp_bot == agp_top) {
1240                 logical_addr_low = adev->gmc.fb_start >> 18;
1241                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1242                         /*
1243                          * Raven2 has a HW issue that it is unable to use the vram which
1244                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1245                          * workaround that increase system aperture high address (add 1)
1246                          * to get rid of the VM fault and hardware hang.
1247                          */
1248                         logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1249                 else
1250                         logical_addr_high = adev->gmc.fb_end >> 18;
1251         } else {
1252                 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1253                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1254                         /*
1255                          * Raven2 has a HW issue that it is unable to use the vram which
1256                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1257                          * workaround that increase system aperture high address (add 1)
1258                          * to get rid of the VM fault and hardware hang.
1259                          */
1260                         logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1261                 else
1262                         logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1263         }
1264
1265         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1266
1267         page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1268         page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1269         page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1270         page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1271         page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1272         page_table_base.low_part = lower_32_bits(pt_base);
1273
1274         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1275         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1276
1277         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1278         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1279         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1280
1281         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1282         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1283         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1284
1285         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1286         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1287         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1288
1289         pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1290
1291 }
1292
1293 static void force_connector_state(
1294         struct amdgpu_dm_connector *aconnector,
1295         enum drm_connector_force force_state)
1296 {
1297         struct drm_connector *connector = &aconnector->base;
1298
1299         mutex_lock(&connector->dev->mode_config.mutex);
1300         aconnector->base.force = force_state;
1301         mutex_unlock(&connector->dev->mode_config.mutex);
1302
1303         mutex_lock(&aconnector->hpd_lock);
1304         drm_kms_helper_connector_hotplug_event(connector);
1305         mutex_unlock(&aconnector->hpd_lock);
1306 }
1307
1308 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1309 {
1310         struct hpd_rx_irq_offload_work *offload_work;
1311         struct amdgpu_dm_connector *aconnector;
1312         struct dc_link *dc_link;
1313         struct amdgpu_device *adev;
1314         enum dc_connection_type new_connection_type = dc_connection_none;
1315         unsigned long flags;
1316         union test_response test_response;
1317
1318         memset(&test_response, 0, sizeof(test_response));
1319
1320         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1321         aconnector = offload_work->offload_wq->aconnector;
1322
1323         if (!aconnector) {
1324                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1325                 goto skip;
1326         }
1327
1328         adev = drm_to_adev(aconnector->base.dev);
1329         dc_link = aconnector->dc_link;
1330
1331         mutex_lock(&aconnector->hpd_lock);
1332         if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1333                 DRM_ERROR("KMS: Failed to detect connector\n");
1334         mutex_unlock(&aconnector->hpd_lock);
1335
1336         if (new_connection_type == dc_connection_none)
1337                 goto skip;
1338
1339         if (amdgpu_in_reset(adev))
1340                 goto skip;
1341
1342         mutex_lock(&adev->dm.dc_lock);
1343         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1344                 dc_link_dp_handle_automated_test(dc_link);
1345
1346                 if (aconnector->timing_changed) {
1347                         /* force connector disconnect and reconnect */
1348                         force_connector_state(aconnector, DRM_FORCE_OFF);
1349                         msleep(100);
1350                         force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1351                 }
1352
1353                 test_response.bits.ACK = 1;
1354
1355                 core_link_write_dpcd(
1356                 dc_link,
1357                 DP_TEST_RESPONSE,
1358                 &test_response.raw,
1359                 sizeof(test_response));
1360         }
1361         else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1362                         dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1363                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1364                 /* offload_work->data is from handle_hpd_rx_irq->
1365                  * schedule_hpd_rx_offload_work.this is defer handle
1366                  * for hpd short pulse. upon here, link status may be
1367                  * changed, need get latest link status from dpcd
1368                  * registers. if link status is good, skip run link
1369                  * training again.
1370                  */
1371                 union hpd_irq_data irq_data;
1372
1373                 memset(&irq_data, 0, sizeof(irq_data));
1374
1375                 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1376                  * request be added to work queue if link lost at end of dc_link_
1377                  * dp_handle_link_loss
1378                  */
1379                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1380                 offload_work->offload_wq->is_handling_link_loss = false;
1381                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1382
1383                 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1384                         dc_link_check_link_loss_status(dc_link, &irq_data))
1385                         dc_link_dp_handle_link_loss(dc_link);
1386         }
1387         mutex_unlock(&adev->dm.dc_lock);
1388
1389 skip:
1390         kfree(offload_work);
1391
1392 }
1393
1394 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1395 {
1396         int max_caps = dc->caps.max_links;
1397         int i = 0;
1398         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1399
1400         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1401
1402         if (!hpd_rx_offload_wq)
1403                 return NULL;
1404
1405
1406         for (i = 0; i < max_caps; i++) {
1407                 hpd_rx_offload_wq[i].wq =
1408                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1409
1410                 if (hpd_rx_offload_wq[i].wq == NULL) {
1411                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1412                         goto out_err;
1413                 }
1414
1415                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1416         }
1417
1418         return hpd_rx_offload_wq;
1419
1420 out_err:
1421         for (i = 0; i < max_caps; i++) {
1422                 if (hpd_rx_offload_wq[i].wq)
1423                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1424         }
1425         kfree(hpd_rx_offload_wq);
1426         return NULL;
1427 }
1428
1429 struct amdgpu_stutter_quirk {
1430         u16 chip_vendor;
1431         u16 chip_device;
1432         u16 subsys_vendor;
1433         u16 subsys_device;
1434         u8 revision;
1435 };
1436
1437 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1438         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1439         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1440         { 0, 0, 0, 0, 0 },
1441 };
1442
1443 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1444 {
1445         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1446
1447         while (p && p->chip_device != 0) {
1448                 if (pdev->vendor == p->chip_vendor &&
1449                     pdev->device == p->chip_device &&
1450                     pdev->subsystem_vendor == p->subsys_vendor &&
1451                     pdev->subsystem_device == p->subsys_device &&
1452                     pdev->revision == p->revision) {
1453                         return true;
1454                 }
1455                 ++p;
1456         }
1457         return false;
1458 }
1459
1460 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1461         {
1462                 .matches = {
1463                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1464                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1465                 },
1466         },
1467         {
1468                 .matches = {
1469                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1470                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1471                 },
1472         },
1473         {
1474                 .matches = {
1475                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1476                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1477                 },
1478         },
1479         {
1480                 .matches = {
1481                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1482                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1483                 },
1484         },
1485         {
1486                 .matches = {
1487                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1488                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1489                 },
1490         },
1491         {
1492                 .matches = {
1493                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1494                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1495                 },
1496         },
1497         {
1498                 .matches = {
1499                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1500                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1501                 },
1502         },
1503         {
1504                 .matches = {
1505                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1506                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1507                 },
1508         },
1509         {
1510                 .matches = {
1511                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1512                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1513                 },
1514         },
1515         {}
1516         /* TODO: refactor this from a fixed table to a dynamic option */
1517 };
1518
1519 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1520 {
1521         const struct dmi_system_id *dmi_id;
1522
1523         dm->aux_hpd_discon_quirk = false;
1524
1525         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1526         if (dmi_id) {
1527                 dm->aux_hpd_discon_quirk = true;
1528                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1529         }
1530 }
1531
1532 static int amdgpu_dm_init(struct amdgpu_device *adev)
1533 {
1534         struct dc_init_data init_data;
1535         struct dc_callback_init init_params;
1536         int r;
1537
1538         adev->dm.ddev = adev_to_drm(adev);
1539         adev->dm.adev = adev;
1540
1541         /* Zero all the fields */
1542         memset(&init_data, 0, sizeof(init_data));
1543         memset(&init_params, 0, sizeof(init_params));
1544
1545         mutex_init(&adev->dm.dpia_aux_lock);
1546         mutex_init(&adev->dm.dc_lock);
1547         mutex_init(&adev->dm.audio_lock);
1548
1549         if(amdgpu_dm_irq_init(adev)) {
1550                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1551                 goto error;
1552         }
1553
1554         init_data.asic_id.chip_family = adev->family;
1555
1556         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1557         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1558         init_data.asic_id.chip_id = adev->pdev->device;
1559
1560         init_data.asic_id.vram_width = adev->gmc.vram_width;
1561         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1562         init_data.asic_id.atombios_base_address =
1563                 adev->mode_info.atom_context->bios;
1564
1565         init_data.driver = adev;
1566
1567         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1568
1569         if (!adev->dm.cgs_device) {
1570                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1571                 goto error;
1572         }
1573
1574         init_data.cgs_device = adev->dm.cgs_device;
1575
1576         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1577
1578         switch (adev->ip_versions[DCE_HWIP][0]) {
1579         case IP_VERSION(2, 1, 0):
1580                 switch (adev->dm.dmcub_fw_version) {
1581                 case 0: /* development */
1582                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1583                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1584                         init_data.flags.disable_dmcu = false;
1585                         break;
1586                 default:
1587                         init_data.flags.disable_dmcu = true;
1588                 }
1589                 break;
1590         case IP_VERSION(2, 0, 3):
1591                 init_data.flags.disable_dmcu = true;
1592                 break;
1593         default:
1594                 break;
1595         }
1596
1597         switch (adev->asic_type) {
1598         case CHIP_CARRIZO:
1599         case CHIP_STONEY:
1600                 init_data.flags.gpu_vm_support = true;
1601                 break;
1602         default:
1603                 switch (adev->ip_versions[DCE_HWIP][0]) {
1604                 case IP_VERSION(1, 0, 0):
1605                 case IP_VERSION(1, 0, 1):
1606                         /* enable S/G on PCO and RV2 */
1607                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1608                             (adev->apu_flags & AMD_APU_IS_PICASSO))
1609                                 init_data.flags.gpu_vm_support = true;
1610                         break;
1611                 case IP_VERSION(2, 1, 0):
1612                 case IP_VERSION(3, 0, 1):
1613                 case IP_VERSION(3, 1, 2):
1614                 case IP_VERSION(3, 1, 3):
1615                 case IP_VERSION(3, 1, 4):
1616                 case IP_VERSION(3, 1, 5):
1617                 case IP_VERSION(3, 1, 6):
1618                         init_data.flags.gpu_vm_support = true;
1619                         break;
1620                 default:
1621                         break;
1622                 }
1623                 break;
1624         }
1625         if (init_data.flags.gpu_vm_support &&
1626             (amdgpu_sg_display == 0))
1627                 init_data.flags.gpu_vm_support = false;
1628
1629         if (init_data.flags.gpu_vm_support)
1630                 adev->mode_info.gpu_vm_support = true;
1631
1632         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1633                 init_data.flags.fbc_support = true;
1634
1635         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1636                 init_data.flags.multi_mon_pp_mclk_switch = true;
1637
1638         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1639                 init_data.flags.disable_fractional_pwm = true;
1640
1641         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1642                 init_data.flags.edp_no_power_sequencing = true;
1643
1644         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1645                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1646         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1647                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1648
1649         /* Disable SubVP + DRR config by default */
1650         init_data.flags.disable_subvp_drr = true;
1651         if (amdgpu_dc_feature_mask & DC_ENABLE_SUBVP_DRR)
1652                 init_data.flags.disable_subvp_drr = false;
1653
1654         init_data.flags.seamless_boot_edp_requested = false;
1655
1656         if (check_seamless_boot_capability(adev)) {
1657                 init_data.flags.seamless_boot_edp_requested = true;
1658                 init_data.flags.allow_seamless_boot_optimization = true;
1659                 DRM_INFO("Seamless boot condition check passed\n");
1660         }
1661
1662         init_data.flags.enable_mipi_converter_optimization = true;
1663
1664         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1665         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1666
1667         INIT_LIST_HEAD(&adev->dm.da_list);
1668
1669         retrieve_dmi_info(&adev->dm);
1670
1671         /* Display Core create. */
1672         adev->dm.dc = dc_create(&init_data);
1673
1674         if (adev->dm.dc) {
1675                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
1676         } else {
1677                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1678                 goto error;
1679         }
1680
1681         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1682                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1683                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1684         }
1685
1686         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1687                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1688         if (dm_should_disable_stutter(adev->pdev))
1689                 adev->dm.dc->debug.disable_stutter = true;
1690
1691         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1692                 adev->dm.dc->debug.disable_stutter = true;
1693
1694         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1695                 adev->dm.dc->debug.disable_dsc = true;
1696         }
1697
1698         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1699                 adev->dm.dc->debug.disable_clock_gate = true;
1700
1701         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1702                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1703
1704         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1705
1706         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1707         adev->dm.dc->debug.ignore_cable_id = true;
1708
1709         /* TODO: There is a new drm mst change where the freedom of
1710          * vc_next_start_slot update is revoked/moved into drm, instead of in
1711          * driver. This forces us to make sure to get vc_next_start_slot updated
1712          * in drm function each time without considering if mst_state is active
1713          * or not. Otherwise, next time hotplug will give wrong start_slot
1714          * number. We are implementing a temporary solution to even notify drm
1715          * mst deallocation when link is no longer of MST type when uncommitting
1716          * the stream so we will have more time to work on a proper solution.
1717          * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1718          * should notify drm to do a complete "reset" of its states and stop
1719          * calling further drm mst functions when link is no longer of an MST
1720          * type. This could happen when we unplug an MST hubs/displays. When
1721          * uncommit stream comes later after unplug, we should just reset
1722          * hardware states only.
1723          */
1724         adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1725
1726         if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1727                 DRM_INFO("DP-HDMI FRL PCON supported\n");
1728
1729         r = dm_dmub_hw_init(adev);
1730         if (r) {
1731                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1732                 goto error;
1733         }
1734
1735         dc_hardware_init(adev->dm.dc);
1736
1737         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1738         if (!adev->dm.hpd_rx_offload_wq) {
1739                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1740                 goto error;
1741         }
1742
1743         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1744                 struct dc_phy_addr_space_config pa_config;
1745
1746                 mmhub_read_system_context(adev, &pa_config);
1747
1748                 // Call the DC init_memory func
1749                 dc_setup_system_context(adev->dm.dc, &pa_config);
1750         }
1751
1752         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1753         if (!adev->dm.freesync_module) {
1754                 DRM_ERROR(
1755                 "amdgpu: failed to initialize freesync_module.\n");
1756         } else
1757                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1758                                 adev->dm.freesync_module);
1759
1760         amdgpu_dm_init_color_mod();
1761
1762         if (adev->dm.dc->caps.max_links > 0) {
1763                 adev->dm.vblank_control_workqueue =
1764                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1765                 if (!adev->dm.vblank_control_workqueue)
1766                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1767         }
1768
1769         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1770                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1771
1772                 if (!adev->dm.hdcp_workqueue)
1773                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1774                 else
1775                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1776
1777                 dc_init_callbacks(adev->dm.dc, &init_params);
1778         }
1779 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1780         adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1781         if (!adev->dm.secure_display_ctxs) {
1782                 DRM_ERROR("amdgpu: failed to initialize secure_display_ctxs.\n");
1783         }
1784 #endif
1785         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1786                 init_completion(&adev->dm.dmub_aux_transfer_done);
1787                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1788                 if (!adev->dm.dmub_notify) {
1789                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1790                         goto error;
1791                 }
1792
1793                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1794                 if (!adev->dm.delayed_hpd_wq) {
1795                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1796                         goto error;
1797                 }
1798
1799                 amdgpu_dm_outbox_init(adev);
1800                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1801                         dmub_aux_setconfig_callback, false)) {
1802                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1803                         goto error;
1804                 }
1805                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1806                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1807                         goto error;
1808                 }
1809                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1810                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1811                         goto error;
1812                 }
1813         }
1814
1815         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1816          * It is expected that DMUB will resend any pending notifications at this point, for
1817          * example HPD from DPIA.
1818          */
1819         if (dc_is_dmub_outbox_supported(adev->dm.dc))
1820                 dc_enable_dmub_outbox(adev->dm.dc);
1821
1822         if (amdgpu_dm_initialize_drm_device(adev)) {
1823                 DRM_ERROR(
1824                 "amdgpu: failed to initialize sw for display support.\n");
1825                 goto error;
1826         }
1827
1828         /* create fake encoders for MST */
1829         dm_dp_create_fake_mst_encoders(adev);
1830
1831         /* TODO: Add_display_info? */
1832
1833         /* TODO use dynamic cursor width */
1834         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1835         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1836
1837         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1838                 DRM_ERROR(
1839                 "amdgpu: failed to initialize sw for display support.\n");
1840                 goto error;
1841         }
1842
1843
1844         DRM_DEBUG_DRIVER("KMS initialized.\n");
1845
1846         return 0;
1847 error:
1848         amdgpu_dm_fini(adev);
1849
1850         return -EINVAL;
1851 }
1852
1853 static int amdgpu_dm_early_fini(void *handle)
1854 {
1855         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1856
1857         amdgpu_dm_audio_fini(adev);
1858
1859         return 0;
1860 }
1861
1862 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1863 {
1864         int i;
1865
1866         if (adev->dm.vblank_control_workqueue) {
1867                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1868                 adev->dm.vblank_control_workqueue = NULL;
1869         }
1870
1871         amdgpu_dm_destroy_drm_device(&adev->dm);
1872
1873 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1874         if (adev->dm.secure_display_ctxs) {
1875                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1876                         if (adev->dm.secure_display_ctxs[i].crtc) {
1877                                 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1878                                 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1879                         }
1880                 }
1881                 kfree(adev->dm.secure_display_ctxs);
1882                 adev->dm.secure_display_ctxs = NULL;
1883         }
1884 #endif
1885         if (adev->dm.hdcp_workqueue) {
1886                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1887                 adev->dm.hdcp_workqueue = NULL;
1888         }
1889
1890         if (adev->dm.dc)
1891                 dc_deinit_callbacks(adev->dm.dc);
1892
1893         if (adev->dm.dc)
1894                 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1895
1896         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1897                 kfree(adev->dm.dmub_notify);
1898                 adev->dm.dmub_notify = NULL;
1899                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1900                 adev->dm.delayed_hpd_wq = NULL;
1901         }
1902
1903         if (adev->dm.dmub_bo)
1904                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1905                                       &adev->dm.dmub_bo_gpu_addr,
1906                                       &adev->dm.dmub_bo_cpu_addr);
1907
1908         if (adev->dm.hpd_rx_offload_wq) {
1909                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1910                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1911                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1912                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1913                         }
1914                 }
1915
1916                 kfree(adev->dm.hpd_rx_offload_wq);
1917                 adev->dm.hpd_rx_offload_wq = NULL;
1918         }
1919
1920         /* DC Destroy TODO: Replace destroy DAL */
1921         if (adev->dm.dc)
1922                 dc_destroy(&adev->dm.dc);
1923         /*
1924          * TODO: pageflip, vlank interrupt
1925          *
1926          * amdgpu_dm_irq_fini(adev);
1927          */
1928
1929         if (adev->dm.cgs_device) {
1930                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1931                 adev->dm.cgs_device = NULL;
1932         }
1933         if (adev->dm.freesync_module) {
1934                 mod_freesync_destroy(adev->dm.freesync_module);
1935                 adev->dm.freesync_module = NULL;
1936         }
1937
1938         mutex_destroy(&adev->dm.audio_lock);
1939         mutex_destroy(&adev->dm.dc_lock);
1940         mutex_destroy(&adev->dm.dpia_aux_lock);
1941
1942         return;
1943 }
1944
1945 static int load_dmcu_fw(struct amdgpu_device *adev)
1946 {
1947         const char *fw_name_dmcu = NULL;
1948         int r;
1949         const struct dmcu_firmware_header_v1_0 *hdr;
1950
1951         switch(adev->asic_type) {
1952 #if defined(CONFIG_DRM_AMD_DC_SI)
1953         case CHIP_TAHITI:
1954         case CHIP_PITCAIRN:
1955         case CHIP_VERDE:
1956         case CHIP_OLAND:
1957 #endif
1958         case CHIP_BONAIRE:
1959         case CHIP_HAWAII:
1960         case CHIP_KAVERI:
1961         case CHIP_KABINI:
1962         case CHIP_MULLINS:
1963         case CHIP_TONGA:
1964         case CHIP_FIJI:
1965         case CHIP_CARRIZO:
1966         case CHIP_STONEY:
1967         case CHIP_POLARIS11:
1968         case CHIP_POLARIS10:
1969         case CHIP_POLARIS12:
1970         case CHIP_VEGAM:
1971         case CHIP_VEGA10:
1972         case CHIP_VEGA12:
1973         case CHIP_VEGA20:
1974                 return 0;
1975         case CHIP_NAVI12:
1976                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1977                 break;
1978         case CHIP_RAVEN:
1979                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1980                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1981                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1982                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1983                 else
1984                         return 0;
1985                 break;
1986         default:
1987                 switch (adev->ip_versions[DCE_HWIP][0]) {
1988                 case IP_VERSION(2, 0, 2):
1989                 case IP_VERSION(2, 0, 3):
1990                 case IP_VERSION(2, 0, 0):
1991                 case IP_VERSION(2, 1, 0):
1992                 case IP_VERSION(3, 0, 0):
1993                 case IP_VERSION(3, 0, 2):
1994                 case IP_VERSION(3, 0, 3):
1995                 case IP_VERSION(3, 0, 1):
1996                 case IP_VERSION(3, 1, 2):
1997                 case IP_VERSION(3, 1, 3):
1998                 case IP_VERSION(3, 1, 4):
1999                 case IP_VERSION(3, 1, 5):
2000                 case IP_VERSION(3, 1, 6):
2001                 case IP_VERSION(3, 2, 0):
2002                 case IP_VERSION(3, 2, 1):
2003                         return 0;
2004                 default:
2005                         break;
2006                 }
2007                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2008                 return -EINVAL;
2009         }
2010
2011         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2012                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2013                 return 0;
2014         }
2015
2016         r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2017         if (r == -ENODEV) {
2018                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2019                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2020                 adev->dm.fw_dmcu = NULL;
2021                 return 0;
2022         }
2023         if (r) {
2024                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2025                         fw_name_dmcu);
2026                 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2027                 return r;
2028         }
2029
2030         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2031         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2032         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2033         adev->firmware.fw_size +=
2034                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2035
2036         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2037         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2038         adev->firmware.fw_size +=
2039                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2040
2041         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2042
2043         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2044
2045         return 0;
2046 }
2047
2048 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2049 {
2050         struct amdgpu_device *adev = ctx;
2051
2052         return dm_read_reg(adev->dm.dc->ctx, address);
2053 }
2054
2055 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2056                                      uint32_t value)
2057 {
2058         struct amdgpu_device *adev = ctx;
2059
2060         return dm_write_reg(adev->dm.dc->ctx, address, value);
2061 }
2062
2063 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2064 {
2065         struct dmub_srv_create_params create_params;
2066         struct dmub_srv_region_params region_params;
2067         struct dmub_srv_region_info region_info;
2068         struct dmub_srv_fb_params fb_params;
2069         struct dmub_srv_fb_info *fb_info;
2070         struct dmub_srv *dmub_srv;
2071         const struct dmcub_firmware_header_v1_0 *hdr;
2072         enum dmub_asic dmub_asic;
2073         enum dmub_status status;
2074         int r;
2075
2076         switch (adev->ip_versions[DCE_HWIP][0]) {
2077         case IP_VERSION(2, 1, 0):
2078                 dmub_asic = DMUB_ASIC_DCN21;
2079                 break;
2080         case IP_VERSION(3, 0, 0):
2081                 dmub_asic = DMUB_ASIC_DCN30;
2082                 break;
2083         case IP_VERSION(3, 0, 1):
2084                 dmub_asic = DMUB_ASIC_DCN301;
2085                 break;
2086         case IP_VERSION(3, 0, 2):
2087                 dmub_asic = DMUB_ASIC_DCN302;
2088                 break;
2089         case IP_VERSION(3, 0, 3):
2090                 dmub_asic = DMUB_ASIC_DCN303;
2091                 break;
2092         case IP_VERSION(3, 1, 2):
2093         case IP_VERSION(3, 1, 3):
2094                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2095                 break;
2096         case IP_VERSION(3, 1, 4):
2097                 dmub_asic = DMUB_ASIC_DCN314;
2098                 break;
2099         case IP_VERSION(3, 1, 5):
2100                 dmub_asic = DMUB_ASIC_DCN315;
2101                 break;
2102         case IP_VERSION(3, 1, 6):
2103                 dmub_asic = DMUB_ASIC_DCN316;
2104                 break;
2105         case IP_VERSION(3, 2, 0):
2106                 dmub_asic = DMUB_ASIC_DCN32;
2107                 break;
2108         case IP_VERSION(3, 2, 1):
2109                 dmub_asic = DMUB_ASIC_DCN321;
2110                 break;
2111         default:
2112                 /* ASIC doesn't support DMUB. */
2113                 return 0;
2114         }
2115
2116         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2117         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2118
2119         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2120                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2121                         AMDGPU_UCODE_ID_DMCUB;
2122                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2123                         adev->dm.dmub_fw;
2124                 adev->firmware.fw_size +=
2125                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2126
2127                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2128                          adev->dm.dmcub_fw_version);
2129         }
2130
2131
2132         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2133         dmub_srv = adev->dm.dmub_srv;
2134
2135         if (!dmub_srv) {
2136                 DRM_ERROR("Failed to allocate DMUB service!\n");
2137                 return -ENOMEM;
2138         }
2139
2140         memset(&create_params, 0, sizeof(create_params));
2141         create_params.user_ctx = adev;
2142         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2143         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2144         create_params.asic = dmub_asic;
2145
2146         /* Create the DMUB service. */
2147         status = dmub_srv_create(dmub_srv, &create_params);
2148         if (status != DMUB_STATUS_OK) {
2149                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2150                 return -EINVAL;
2151         }
2152
2153         /* Calculate the size of all the regions for the DMUB service. */
2154         memset(&region_params, 0, sizeof(region_params));
2155
2156         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2157                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2158         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2159         region_params.vbios_size = adev->bios_size;
2160         region_params.fw_bss_data = region_params.bss_data_size ?
2161                 adev->dm.dmub_fw->data +
2162                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2163                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2164         region_params.fw_inst_const =
2165                 adev->dm.dmub_fw->data +
2166                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2167                 PSP_HEADER_BYTES;
2168
2169         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2170                                            &region_info);
2171
2172         if (status != DMUB_STATUS_OK) {
2173                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2174                 return -EINVAL;
2175         }
2176
2177         /*
2178          * Allocate a framebuffer based on the total size of all the regions.
2179          * TODO: Move this into GART.
2180          */
2181         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2182                                     AMDGPU_GEM_DOMAIN_VRAM |
2183                                     AMDGPU_GEM_DOMAIN_GTT,
2184                                     &adev->dm.dmub_bo,
2185                                     &adev->dm.dmub_bo_gpu_addr,
2186                                     &adev->dm.dmub_bo_cpu_addr);
2187         if (r)
2188                 return r;
2189
2190         /* Rebase the regions on the framebuffer address. */
2191         memset(&fb_params, 0, sizeof(fb_params));
2192         fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2193         fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2194         fb_params.region_info = &region_info;
2195
2196         adev->dm.dmub_fb_info =
2197                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2198         fb_info = adev->dm.dmub_fb_info;
2199
2200         if (!fb_info) {
2201                 DRM_ERROR(
2202                         "Failed to allocate framebuffer info for DMUB service!\n");
2203                 return -ENOMEM;
2204         }
2205
2206         status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2207         if (status != DMUB_STATUS_OK) {
2208                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2209                 return -EINVAL;
2210         }
2211
2212         return 0;
2213 }
2214
2215 static int dm_sw_init(void *handle)
2216 {
2217         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2218         int r;
2219
2220         r = dm_dmub_sw_init(adev);
2221         if (r)
2222                 return r;
2223
2224         return load_dmcu_fw(adev);
2225 }
2226
2227 static int dm_sw_fini(void *handle)
2228 {
2229         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2230
2231         kfree(adev->dm.dmub_fb_info);
2232         adev->dm.dmub_fb_info = NULL;
2233
2234         if (adev->dm.dmub_srv) {
2235                 dmub_srv_destroy(adev->dm.dmub_srv);
2236                 adev->dm.dmub_srv = NULL;
2237         }
2238
2239         amdgpu_ucode_release(&adev->dm.dmub_fw);
2240         amdgpu_ucode_release(&adev->dm.fw_dmcu);
2241
2242         return 0;
2243 }
2244
2245 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2246 {
2247         struct amdgpu_dm_connector *aconnector;
2248         struct drm_connector *connector;
2249         struct drm_connector_list_iter iter;
2250         int ret = 0;
2251
2252         drm_connector_list_iter_begin(dev, &iter);
2253         drm_for_each_connector_iter(connector, &iter) {
2254                 aconnector = to_amdgpu_dm_connector(connector);
2255                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2256                     aconnector->mst_mgr.aux) {
2257                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2258                                          aconnector,
2259                                          aconnector->base.base.id);
2260
2261                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2262                         if (ret < 0) {
2263                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2264                                 aconnector->dc_link->type =
2265                                         dc_connection_single;
2266                                 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2267                                                                      aconnector->dc_link);
2268                                 break;
2269                         }
2270                 }
2271         }
2272         drm_connector_list_iter_end(&iter);
2273
2274         return ret;
2275 }
2276
2277 static int dm_late_init(void *handle)
2278 {
2279         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2280
2281         struct dmcu_iram_parameters params;
2282         unsigned int linear_lut[16];
2283         int i;
2284         struct dmcu *dmcu = NULL;
2285
2286         dmcu = adev->dm.dc->res_pool->dmcu;
2287
2288         for (i = 0; i < 16; i++)
2289                 linear_lut[i] = 0xFFFF * i / 15;
2290
2291         params.set = 0;
2292         params.backlight_ramping_override = false;
2293         params.backlight_ramping_start = 0xCCCC;
2294         params.backlight_ramping_reduction = 0xCCCCCCCC;
2295         params.backlight_lut_array_size = 16;
2296         params.backlight_lut_array = linear_lut;
2297
2298         /* Min backlight level after ABM reduction,  Don't allow below 1%
2299          * 0xFFFF x 0.01 = 0x28F
2300          */
2301         params.min_abm_backlight = 0x28F;
2302         /* In the case where abm is implemented on dmcub,
2303          * dmcu object will be null.
2304          * ABM 2.4 and up are implemented on dmcub.
2305          */
2306         if (dmcu) {
2307                 if (!dmcu_load_iram(dmcu, params))
2308                         return -EINVAL;
2309         } else if (adev->dm.dc->ctx->dmub_srv) {
2310                 struct dc_link *edp_links[MAX_NUM_EDP];
2311                 int edp_num;
2312
2313                 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2314                 for (i = 0; i < edp_num; i++) {
2315                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2316                                 return -EINVAL;
2317                 }
2318         }
2319
2320         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2321 }
2322
2323 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2324 {
2325         struct amdgpu_dm_connector *aconnector;
2326         struct drm_connector *connector;
2327         struct drm_connector_list_iter iter;
2328         struct drm_dp_mst_topology_mgr *mgr;
2329         int ret;
2330         bool need_hotplug = false;
2331
2332         drm_connector_list_iter_begin(dev, &iter);
2333         drm_for_each_connector_iter(connector, &iter) {
2334                 aconnector = to_amdgpu_dm_connector(connector);
2335                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2336                     aconnector->mst_root)
2337                         continue;
2338
2339                 mgr = &aconnector->mst_mgr;
2340
2341                 if (suspend) {
2342                         drm_dp_mst_topology_mgr_suspend(mgr);
2343                 } else {
2344                         /* if extended timeout is supported in hardware,
2345                          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2346                          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2347                          */
2348                         try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2349                         if (!dp_is_lttpr_present(aconnector->dc_link))
2350                                 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2351
2352                         ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2353                         if (ret < 0) {
2354                                 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2355                                         aconnector->dc_link);
2356                                 need_hotplug = true;
2357                         }
2358                 }
2359         }
2360         drm_connector_list_iter_end(&iter);
2361
2362         if (need_hotplug)
2363                 drm_kms_helper_hotplug_event(dev);
2364 }
2365
2366 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2367 {
2368         int ret = 0;
2369
2370         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2371          * on window driver dc implementation.
2372          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2373          * should be passed to smu during boot up and resume from s3.
2374          * boot up: dc calculate dcn watermark clock settings within dc_create,
2375          * dcn20_resource_construct
2376          * then call pplib functions below to pass the settings to smu:
2377          * smu_set_watermarks_for_clock_ranges
2378          * smu_set_watermarks_table
2379          * navi10_set_watermarks_table
2380          * smu_write_watermarks_table
2381          *
2382          * For Renoir, clock settings of dcn watermark are also fixed values.
2383          * dc has implemented different flow for window driver:
2384          * dc_hardware_init / dc_set_power_state
2385          * dcn10_init_hw
2386          * notify_wm_ranges
2387          * set_wm_ranges
2388          * -- Linux
2389          * smu_set_watermarks_for_clock_ranges
2390          * renoir_set_watermarks_table
2391          * smu_write_watermarks_table
2392          *
2393          * For Linux,
2394          * dc_hardware_init -> amdgpu_dm_init
2395          * dc_set_power_state --> dm_resume
2396          *
2397          * therefore, this function apply to navi10/12/14 but not Renoir
2398          * *
2399          */
2400         switch (adev->ip_versions[DCE_HWIP][0]) {
2401         case IP_VERSION(2, 0, 2):
2402         case IP_VERSION(2, 0, 0):
2403                 break;
2404         default:
2405                 return 0;
2406         }
2407
2408         ret = amdgpu_dpm_write_watermarks_table(adev);
2409         if (ret) {
2410                 DRM_ERROR("Failed to update WMTABLE!\n");
2411                 return ret;
2412         }
2413
2414         return 0;
2415 }
2416
2417 /**
2418  * dm_hw_init() - Initialize DC device
2419  * @handle: The base driver device containing the amdgpu_dm device.
2420  *
2421  * Initialize the &struct amdgpu_display_manager device. This involves calling
2422  * the initializers of each DM component, then populating the struct with them.
2423  *
2424  * Although the function implies hardware initialization, both hardware and
2425  * software are initialized here. Splitting them out to their relevant init
2426  * hooks is a future TODO item.
2427  *
2428  * Some notable things that are initialized here:
2429  *
2430  * - Display Core, both software and hardware
2431  * - DC modules that we need (freesync and color management)
2432  * - DRM software states
2433  * - Interrupt sources and handlers
2434  * - Vblank support
2435  * - Debug FS entries, if enabled
2436  */
2437 static int dm_hw_init(void *handle)
2438 {
2439         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2440         /* Create DAL display manager */
2441         amdgpu_dm_init(adev);
2442         amdgpu_dm_hpd_init(adev);
2443
2444         return 0;
2445 }
2446
2447 /**
2448  * dm_hw_fini() - Teardown DC device
2449  * @handle: The base driver device containing the amdgpu_dm device.
2450  *
2451  * Teardown components within &struct amdgpu_display_manager that require
2452  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2453  * were loaded. Also flush IRQ workqueues and disable them.
2454  */
2455 static int dm_hw_fini(void *handle)
2456 {
2457         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2458
2459         amdgpu_dm_hpd_fini(adev);
2460
2461         amdgpu_dm_irq_fini(adev);
2462         amdgpu_dm_fini(adev);
2463         return 0;
2464 }
2465
2466
2467 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2468                                  struct dc_state *state, bool enable)
2469 {
2470         enum dc_irq_source irq_source;
2471         struct amdgpu_crtc *acrtc;
2472         int rc = -EBUSY;
2473         int i = 0;
2474
2475         for (i = 0; i < state->stream_count; i++) {
2476                 acrtc = get_crtc_by_otg_inst(
2477                                 adev, state->stream_status[i].primary_otg_inst);
2478
2479                 if (acrtc && state->stream_status[i].plane_count != 0) {
2480                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2481                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2482                         DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
2483                                       acrtc->crtc_id, enable ? "en" : "dis", rc);
2484                         if (rc)
2485                                 DRM_WARN("Failed to %s pflip interrupts\n",
2486                                          enable ? "enable" : "disable");
2487
2488                         if (enable) {
2489                                 rc = amdgpu_dm_crtc_enable_vblank(&acrtc->base);
2490                                 if (rc)
2491                                         DRM_WARN("Failed to enable vblank interrupts\n");
2492                         } else {
2493                                 amdgpu_dm_crtc_disable_vblank(&acrtc->base);
2494                         }
2495
2496                 }
2497         }
2498
2499 }
2500
2501 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2502 {
2503         struct dc_state *context = NULL;
2504         enum dc_status res = DC_ERROR_UNEXPECTED;
2505         int i;
2506         struct dc_stream_state *del_streams[MAX_PIPES];
2507         int del_streams_count = 0;
2508
2509         memset(del_streams, 0, sizeof(del_streams));
2510
2511         context = dc_create_state(dc);
2512         if (context == NULL)
2513                 goto context_alloc_fail;
2514
2515         dc_resource_state_copy_construct_current(dc, context);
2516
2517         /* First remove from context all streams */
2518         for (i = 0; i < context->stream_count; i++) {
2519                 struct dc_stream_state *stream = context->streams[i];
2520
2521                 del_streams[del_streams_count++] = stream;
2522         }
2523
2524         /* Remove all planes for removed streams and then remove the streams */
2525         for (i = 0; i < del_streams_count; i++) {
2526                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2527                         res = DC_FAIL_DETACH_SURFACES;
2528                         goto fail;
2529                 }
2530
2531                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2532                 if (res != DC_OK)
2533                         goto fail;
2534         }
2535
2536         res = dc_commit_streams(dc, context->streams, context->stream_count);
2537
2538 fail:
2539         dc_release_state(context);
2540
2541 context_alloc_fail:
2542         return res;
2543 }
2544
2545 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2546 {
2547         int i;
2548
2549         if (dm->hpd_rx_offload_wq) {
2550                 for (i = 0; i < dm->dc->caps.max_links; i++)
2551                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2552         }
2553 }
2554
2555 static int dm_suspend(void *handle)
2556 {
2557         struct amdgpu_device *adev = handle;
2558         struct amdgpu_display_manager *dm = &adev->dm;
2559         int ret = 0;
2560
2561         if (amdgpu_in_reset(adev)) {
2562                 mutex_lock(&dm->dc_lock);
2563
2564                 dc_allow_idle_optimizations(adev->dm.dc, false);
2565
2566                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2567
2568                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2569
2570                 amdgpu_dm_commit_zero_streams(dm->dc);
2571
2572                 amdgpu_dm_irq_suspend(adev);
2573
2574                 hpd_rx_irq_work_suspend(dm);
2575
2576                 return ret;
2577         }
2578
2579         WARN_ON(adev->dm.cached_state);
2580         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2581
2582         s3_handle_mst(adev_to_drm(adev), true);
2583
2584         amdgpu_dm_irq_suspend(adev);
2585
2586         hpd_rx_irq_work_suspend(dm);
2587
2588         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2589
2590         return 0;
2591 }
2592
2593 struct amdgpu_dm_connector *
2594 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2595                                              struct drm_crtc *crtc)
2596 {
2597         u32 i;
2598         struct drm_connector_state *new_con_state;
2599         struct drm_connector *connector;
2600         struct drm_crtc *crtc_from_state;
2601
2602         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2603                 crtc_from_state = new_con_state->crtc;
2604
2605                 if (crtc_from_state == crtc)
2606                         return to_amdgpu_dm_connector(connector);
2607         }
2608
2609         return NULL;
2610 }
2611
2612 static void emulated_link_detect(struct dc_link *link)
2613 {
2614         struct dc_sink_init_data sink_init_data = { 0 };
2615         struct display_sink_capability sink_caps = { 0 };
2616         enum dc_edid_status edid_status;
2617         struct dc_context *dc_ctx = link->ctx;
2618         struct dc_sink *sink = NULL;
2619         struct dc_sink *prev_sink = NULL;
2620
2621         link->type = dc_connection_none;
2622         prev_sink = link->local_sink;
2623
2624         if (prev_sink)
2625                 dc_sink_release(prev_sink);
2626
2627         switch (link->connector_signal) {
2628         case SIGNAL_TYPE_HDMI_TYPE_A: {
2629                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2630                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2631                 break;
2632         }
2633
2634         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2635                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2636                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2637                 break;
2638         }
2639
2640         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2641                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2642                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2643                 break;
2644         }
2645
2646         case SIGNAL_TYPE_LVDS: {
2647                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2648                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2649                 break;
2650         }
2651
2652         case SIGNAL_TYPE_EDP: {
2653                 sink_caps.transaction_type =
2654                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2655                 sink_caps.signal = SIGNAL_TYPE_EDP;
2656                 break;
2657         }
2658
2659         case SIGNAL_TYPE_DISPLAY_PORT: {
2660                 sink_caps.transaction_type =
2661                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2662                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2663                 break;
2664         }
2665
2666         default:
2667                 DC_ERROR("Invalid connector type! signal:%d\n",
2668                         link->connector_signal);
2669                 return;
2670         }
2671
2672         sink_init_data.link = link;
2673         sink_init_data.sink_signal = sink_caps.signal;
2674
2675         sink = dc_sink_create(&sink_init_data);
2676         if (!sink) {
2677                 DC_ERROR("Failed to create sink!\n");
2678                 return;
2679         }
2680
2681         /* dc_sink_create returns a new reference */
2682         link->local_sink = sink;
2683
2684         edid_status = dm_helpers_read_local_edid(
2685                         link->ctx,
2686                         link,
2687                         sink);
2688
2689         if (edid_status != EDID_OK)
2690                 DC_ERROR("Failed to read EDID");
2691
2692 }
2693
2694 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2695                                      struct amdgpu_display_manager *dm)
2696 {
2697         struct {
2698                 struct dc_surface_update surface_updates[MAX_SURFACES];
2699                 struct dc_plane_info plane_infos[MAX_SURFACES];
2700                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2701                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2702                 struct dc_stream_update stream_update;
2703         } * bundle;
2704         int k, m;
2705
2706         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2707
2708         if (!bundle) {
2709                 dm_error("Failed to allocate update bundle\n");
2710                 goto cleanup;
2711         }
2712
2713         for (k = 0; k < dc_state->stream_count; k++) {
2714                 bundle->stream_update.stream = dc_state->streams[k];
2715
2716                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2717                         bundle->surface_updates[m].surface =
2718                                 dc_state->stream_status->plane_states[m];
2719                         bundle->surface_updates[m].surface->force_full_update =
2720                                 true;
2721                 }
2722
2723                 update_planes_and_stream_adapter(dm->dc,
2724                                          UPDATE_TYPE_FULL,
2725                                          dc_state->stream_status->plane_count,
2726                                          dc_state->streams[k],
2727                                          &bundle->stream_update,
2728                                          bundle->surface_updates);
2729         }
2730
2731 cleanup:
2732         kfree(bundle);
2733
2734         return;
2735 }
2736
2737 static int dm_resume(void *handle)
2738 {
2739         struct amdgpu_device *adev = handle;
2740         struct drm_device *ddev = adev_to_drm(adev);
2741         struct amdgpu_display_manager *dm = &adev->dm;
2742         struct amdgpu_dm_connector *aconnector;
2743         struct drm_connector *connector;
2744         struct drm_connector_list_iter iter;
2745         struct drm_crtc *crtc;
2746         struct drm_crtc_state *new_crtc_state;
2747         struct dm_crtc_state *dm_new_crtc_state;
2748         struct drm_plane *plane;
2749         struct drm_plane_state *new_plane_state;
2750         struct dm_plane_state *dm_new_plane_state;
2751         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2752         enum dc_connection_type new_connection_type = dc_connection_none;
2753         struct dc_state *dc_state;
2754         int i, r, j;
2755
2756         if (amdgpu_in_reset(adev)) {
2757                 dc_state = dm->cached_dc_state;
2758
2759                 /*
2760                  * The dc->current_state is backed up into dm->cached_dc_state
2761                  * before we commit 0 streams.
2762                  *
2763                  * DC will clear link encoder assignments on the real state
2764                  * but the changes won't propagate over to the copy we made
2765                  * before the 0 streams commit.
2766                  *
2767                  * DC expects that link encoder assignments are *not* valid
2768                  * when committing a state, so as a workaround we can copy
2769                  * off of the current state.
2770                  *
2771                  * We lose the previous assignments, but we had already
2772                  * commit 0 streams anyway.
2773                  */
2774                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2775
2776                 r = dm_dmub_hw_init(adev);
2777                 if (r)
2778                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2779
2780                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2781                 dc_resume(dm->dc);
2782
2783                 amdgpu_dm_irq_resume_early(adev);
2784
2785                 for (i = 0; i < dc_state->stream_count; i++) {
2786                         dc_state->streams[i]->mode_changed = true;
2787                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2788                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2789                                         = 0xffffffff;
2790                         }
2791                 }
2792
2793                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2794                         amdgpu_dm_outbox_init(adev);
2795                         dc_enable_dmub_outbox(adev->dm.dc);
2796                 }
2797
2798                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2799
2800                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2801
2802                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2803
2804                 dc_release_state(dm->cached_dc_state);
2805                 dm->cached_dc_state = NULL;
2806
2807                 amdgpu_dm_irq_resume_late(adev);
2808
2809                 mutex_unlock(&dm->dc_lock);
2810
2811                 return 0;
2812         }
2813         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2814         dc_release_state(dm_state->context);
2815         dm_state->context = dc_create_state(dm->dc);
2816         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2817         dc_resource_state_construct(dm->dc, dm_state->context);
2818
2819         /* Before powering on DC we need to re-initialize DMUB. */
2820         dm_dmub_hw_resume(adev);
2821
2822         /* Re-enable outbox interrupts for DPIA. */
2823         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2824                 amdgpu_dm_outbox_init(adev);
2825                 dc_enable_dmub_outbox(adev->dm.dc);
2826         }
2827
2828         /* power on hardware */
2829         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2830
2831         /* program HPD filter */
2832         dc_resume(dm->dc);
2833
2834         /*
2835          * early enable HPD Rx IRQ, should be done before set mode as short
2836          * pulse interrupts are used for MST
2837          */
2838         amdgpu_dm_irq_resume_early(adev);
2839
2840         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2841         s3_handle_mst(ddev, false);
2842
2843         /* Do detection*/
2844         drm_connector_list_iter_begin(ddev, &iter);
2845         drm_for_each_connector_iter(connector, &iter) {
2846                 aconnector = to_amdgpu_dm_connector(connector);
2847
2848                 if (!aconnector->dc_link)
2849                         continue;
2850
2851                 /*
2852                  * this is the case when traversing through already created
2853                  * MST connectors, should be skipped
2854                  */
2855                 if (aconnector->dc_link->type == dc_connection_mst_branch)
2856                         continue;
2857
2858                 mutex_lock(&aconnector->hpd_lock);
2859                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2860                         DRM_ERROR("KMS: Failed to detect connector\n");
2861
2862                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2863                         emulated_link_detect(aconnector->dc_link);
2864                 } else {
2865                         mutex_lock(&dm->dc_lock);
2866                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2867                         mutex_unlock(&dm->dc_lock);
2868                 }
2869
2870                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2871                         aconnector->fake_enable = false;
2872
2873                 if (aconnector->dc_sink)
2874                         dc_sink_release(aconnector->dc_sink);
2875                 aconnector->dc_sink = NULL;
2876                 amdgpu_dm_update_connector_after_detect(aconnector);
2877                 mutex_unlock(&aconnector->hpd_lock);
2878         }
2879         drm_connector_list_iter_end(&iter);
2880
2881         /* Force mode set in atomic commit */
2882         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2883                 new_crtc_state->active_changed = true;
2884
2885         /*
2886          * atomic_check is expected to create the dc states. We need to release
2887          * them here, since they were duplicated as part of the suspend
2888          * procedure.
2889          */
2890         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2891                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2892                 if (dm_new_crtc_state->stream) {
2893                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2894                         dc_stream_release(dm_new_crtc_state->stream);
2895                         dm_new_crtc_state->stream = NULL;
2896                 }
2897         }
2898
2899         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2900                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2901                 if (dm_new_plane_state->dc_state) {
2902                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2903                         dc_plane_state_release(dm_new_plane_state->dc_state);
2904                         dm_new_plane_state->dc_state = NULL;
2905                 }
2906         }
2907
2908         drm_atomic_helper_resume(ddev, dm->cached_state);
2909
2910         dm->cached_state = NULL;
2911
2912         amdgpu_dm_irq_resume_late(adev);
2913
2914         amdgpu_dm_smu_write_watermarks_table(adev);
2915
2916         return 0;
2917 }
2918
2919 /**
2920  * DOC: DM Lifecycle
2921  *
2922  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2923  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2924  * the base driver's device list to be initialized and torn down accordingly.
2925  *
2926  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2927  */
2928
2929 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2930         .name = "dm",
2931         .early_init = dm_early_init,
2932         .late_init = dm_late_init,
2933         .sw_init = dm_sw_init,
2934         .sw_fini = dm_sw_fini,
2935         .early_fini = amdgpu_dm_early_fini,
2936         .hw_init = dm_hw_init,
2937         .hw_fini = dm_hw_fini,
2938         .suspend = dm_suspend,
2939         .resume = dm_resume,
2940         .is_idle = dm_is_idle,
2941         .wait_for_idle = dm_wait_for_idle,
2942         .check_soft_reset = dm_check_soft_reset,
2943         .soft_reset = dm_soft_reset,
2944         .set_clockgating_state = dm_set_clockgating_state,
2945         .set_powergating_state = dm_set_powergating_state,
2946 };
2947
2948 const struct amdgpu_ip_block_version dm_ip_block =
2949 {
2950         .type = AMD_IP_BLOCK_TYPE_DCE,
2951         .major = 1,
2952         .minor = 0,
2953         .rev = 0,
2954         .funcs = &amdgpu_dm_funcs,
2955 };
2956
2957
2958 /**
2959  * DOC: atomic
2960  *
2961  * *WIP*
2962  */
2963
2964 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2965         .fb_create = amdgpu_display_user_framebuffer_create,
2966         .get_format_info = amdgpu_dm_plane_get_format_info,
2967         .atomic_check = amdgpu_dm_atomic_check,
2968         .atomic_commit = drm_atomic_helper_commit,
2969 };
2970
2971 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2972         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2973         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2974 };
2975
2976 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2977 {
2978         struct amdgpu_dm_backlight_caps *caps;
2979         struct drm_connector *conn_base;
2980         struct amdgpu_device *adev;
2981         struct drm_luminance_range_info *luminance_range;
2982
2983         if (aconnector->bl_idx == -1 ||
2984             aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
2985                 return;
2986
2987         conn_base = &aconnector->base;
2988         adev = drm_to_adev(conn_base->dev);
2989
2990         caps = &adev->dm.backlight_caps[aconnector->bl_idx];
2991         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2992         caps->aux_support = false;
2993
2994         if (caps->ext_caps->bits.oled == 1 /*||
2995             caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
2996             caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
2997                 caps->aux_support = true;
2998
2999         if (amdgpu_backlight == 0)
3000                 caps->aux_support = false;
3001         else if (amdgpu_backlight == 1)
3002                 caps->aux_support = true;
3003
3004         luminance_range = &conn_base->display_info.luminance_range;
3005
3006         if (luminance_range->max_luminance) {
3007                 caps->aux_min_input_signal = luminance_range->min_luminance;
3008                 caps->aux_max_input_signal = luminance_range->max_luminance;
3009         } else {
3010                 caps->aux_min_input_signal = 0;
3011                 caps->aux_max_input_signal = 512;
3012         }
3013 }
3014
3015 void amdgpu_dm_update_connector_after_detect(
3016                 struct amdgpu_dm_connector *aconnector)
3017 {
3018         struct drm_connector *connector = &aconnector->base;
3019         struct drm_device *dev = connector->dev;
3020         struct dc_sink *sink;
3021
3022         /* MST handled by drm_mst framework */
3023         if (aconnector->mst_mgr.mst_state == true)
3024                 return;
3025
3026         sink = aconnector->dc_link->local_sink;
3027         if (sink)
3028                 dc_sink_retain(sink);
3029
3030         /*
3031          * Edid mgmt connector gets first update only in mode_valid hook and then
3032          * the connector sink is set to either fake or physical sink depends on link status.
3033          * Skip if already done during boot.
3034          */
3035         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3036                         && aconnector->dc_em_sink) {
3037
3038                 /*
3039                  * For S3 resume with headless use eml_sink to fake stream
3040                  * because on resume connector->sink is set to NULL
3041                  */
3042                 mutex_lock(&dev->mode_config.mutex);
3043
3044                 if (sink) {
3045                         if (aconnector->dc_sink) {
3046                                 amdgpu_dm_update_freesync_caps(connector, NULL);
3047                                 /*
3048                                  * retain and release below are used to
3049                                  * bump up refcount for sink because the link doesn't point
3050                                  * to it anymore after disconnect, so on next crtc to connector
3051                                  * reshuffle by UMD we will get into unwanted dc_sink release
3052                                  */
3053                                 dc_sink_release(aconnector->dc_sink);
3054                         }
3055                         aconnector->dc_sink = sink;
3056                         dc_sink_retain(aconnector->dc_sink);
3057                         amdgpu_dm_update_freesync_caps(connector,
3058                                         aconnector->edid);
3059                 } else {
3060                         amdgpu_dm_update_freesync_caps(connector, NULL);
3061                         if (!aconnector->dc_sink) {
3062                                 aconnector->dc_sink = aconnector->dc_em_sink;
3063                                 dc_sink_retain(aconnector->dc_sink);
3064                         }
3065                 }
3066
3067                 mutex_unlock(&dev->mode_config.mutex);
3068
3069                 if (sink)
3070                         dc_sink_release(sink);
3071                 return;
3072         }
3073
3074         /*
3075          * TODO: temporary guard to look for proper fix
3076          * if this sink is MST sink, we should not do anything
3077          */
3078         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3079                 dc_sink_release(sink);
3080                 return;
3081         }
3082
3083         if (aconnector->dc_sink == sink) {
3084                 /*
3085                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
3086                  * Do nothing!!
3087                  */
3088                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3089                                 aconnector->connector_id);
3090                 if (sink)
3091                         dc_sink_release(sink);
3092                 return;
3093         }
3094
3095         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3096                 aconnector->connector_id, aconnector->dc_sink, sink);
3097
3098         mutex_lock(&dev->mode_config.mutex);
3099
3100         /*
3101          * 1. Update status of the drm connector
3102          * 2. Send an event and let userspace tell us what to do
3103          */
3104         if (sink) {
3105                 /*
3106                  * TODO: check if we still need the S3 mode update workaround.
3107                  * If yes, put it here.
3108                  */
3109                 if (aconnector->dc_sink) {
3110                         amdgpu_dm_update_freesync_caps(connector, NULL);
3111                         dc_sink_release(aconnector->dc_sink);
3112                 }
3113
3114                 aconnector->dc_sink = sink;
3115                 dc_sink_retain(aconnector->dc_sink);
3116                 if (sink->dc_edid.length == 0) {
3117                         aconnector->edid = NULL;
3118                         if (aconnector->dc_link->aux_mode) {
3119                                 drm_dp_cec_unset_edid(
3120                                         &aconnector->dm_dp_aux.aux);
3121                         }
3122                 } else {
3123                         aconnector->edid =
3124                                 (struct edid *)sink->dc_edid.raw_edid;
3125
3126                         if (aconnector->dc_link->aux_mode)
3127                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3128                                                     aconnector->edid);
3129                 }
3130
3131                 aconnector->timing_requested = kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3132                 if (!aconnector->timing_requested)
3133                         dm_error("%s: failed to create aconnector->requested_timing\n", __func__);
3134
3135                 drm_connector_update_edid_property(connector, aconnector->edid);
3136                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3137                 update_connector_ext_caps(aconnector);
3138         } else {
3139                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3140                 amdgpu_dm_update_freesync_caps(connector, NULL);
3141                 drm_connector_update_edid_property(connector, NULL);
3142                 aconnector->num_modes = 0;
3143                 dc_sink_release(aconnector->dc_sink);
3144                 aconnector->dc_sink = NULL;
3145                 aconnector->edid = NULL;
3146                 kfree(aconnector->timing_requested);
3147                 aconnector->timing_requested = NULL;
3148                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3149                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3150                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3151         }
3152
3153         mutex_unlock(&dev->mode_config.mutex);
3154
3155         update_subconnector_property(aconnector);
3156
3157         if (sink)
3158                 dc_sink_release(sink);
3159 }
3160
3161 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3162 {
3163         struct drm_connector *connector = &aconnector->base;
3164         struct drm_device *dev = connector->dev;
3165         enum dc_connection_type new_connection_type = dc_connection_none;
3166         struct amdgpu_device *adev = drm_to_adev(dev);
3167         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3168         bool ret = false;
3169
3170         if (adev->dm.disable_hpd_irq)
3171                 return;
3172
3173         /*
3174          * In case of failure or MST no need to update connector status or notify the OS
3175          * since (for MST case) MST does this in its own context.
3176          */
3177         mutex_lock(&aconnector->hpd_lock);
3178
3179         if (adev->dm.hdcp_workqueue) {
3180                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3181                 dm_con_state->update_hdcp = true;
3182         }
3183         if (aconnector->fake_enable)
3184                 aconnector->fake_enable = false;
3185
3186         aconnector->timing_changed = false;
3187
3188         if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3189                 DRM_ERROR("KMS: Failed to detect connector\n");
3190
3191         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3192                 emulated_link_detect(aconnector->dc_link);
3193
3194                 drm_modeset_lock_all(dev);
3195                 dm_restore_drm_connector_state(dev, connector);
3196                 drm_modeset_unlock_all(dev);
3197
3198                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3199                         drm_kms_helper_connector_hotplug_event(connector);
3200         } else {
3201                 mutex_lock(&adev->dm.dc_lock);
3202                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3203                 mutex_unlock(&adev->dm.dc_lock);
3204                 if (ret) {
3205                         amdgpu_dm_update_connector_after_detect(aconnector);
3206
3207                         drm_modeset_lock_all(dev);
3208                         dm_restore_drm_connector_state(dev, connector);
3209                         drm_modeset_unlock_all(dev);
3210
3211                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3212                                 drm_kms_helper_connector_hotplug_event(connector);
3213                 }
3214         }
3215         mutex_unlock(&aconnector->hpd_lock);
3216
3217 }
3218
3219 static void handle_hpd_irq(void *param)
3220 {
3221         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3222
3223         handle_hpd_irq_helper(aconnector);
3224
3225 }
3226
3227 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
3228 {
3229         u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3230         u8 dret;
3231         bool new_irq_handled = false;
3232         int dpcd_addr;
3233         int dpcd_bytes_to_read;
3234
3235         const int max_process_count = 30;
3236         int process_count = 0;
3237
3238         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3239
3240         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3241                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3242                 /* DPCD 0x200 - 0x201 for downstream IRQ */
3243                 dpcd_addr = DP_SINK_COUNT;
3244         } else {
3245                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3246                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3247                 dpcd_addr = DP_SINK_COUNT_ESI;
3248         }
3249
3250         dret = drm_dp_dpcd_read(
3251                 &aconnector->dm_dp_aux.aux,
3252                 dpcd_addr,
3253                 esi,
3254                 dpcd_bytes_to_read);
3255
3256         while (dret == dpcd_bytes_to_read &&
3257                 process_count < max_process_count) {
3258                 u8 retry;
3259                 dret = 0;
3260
3261                 process_count++;
3262
3263                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3264                 /* handle HPD short pulse irq */
3265                 if (aconnector->mst_mgr.mst_state)
3266                         drm_dp_mst_hpd_irq(
3267                                 &aconnector->mst_mgr,
3268                                 esi,
3269                                 &new_irq_handled);
3270
3271                 if (new_irq_handled) {
3272                         /* ACK at DPCD to notify down stream */
3273                         const int ack_dpcd_bytes_to_write =
3274                                 dpcd_bytes_to_read - 1;
3275
3276                         for (retry = 0; retry < 3; retry++) {
3277                                 u8 wret;
3278
3279                                 wret = drm_dp_dpcd_write(
3280                                         &aconnector->dm_dp_aux.aux,
3281                                         dpcd_addr + 1,
3282                                         &esi[1],
3283                                         ack_dpcd_bytes_to_write);
3284                                 if (wret == ack_dpcd_bytes_to_write)
3285                                         break;
3286                         }
3287
3288                         /* check if there is new irq to be handled */
3289                         dret = drm_dp_dpcd_read(
3290                                 &aconnector->dm_dp_aux.aux,
3291                                 dpcd_addr,
3292                                 esi,
3293                                 dpcd_bytes_to_read);
3294
3295                         new_irq_handled = false;
3296                 } else {
3297                         break;
3298                 }
3299         }
3300
3301         if (process_count == max_process_count)
3302                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
3303 }
3304
3305 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3306                                                         union hpd_irq_data hpd_irq_data)
3307 {
3308         struct hpd_rx_irq_offload_work *offload_work =
3309                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3310
3311         if (!offload_work) {
3312                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3313                 return;
3314         }
3315
3316         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3317         offload_work->data = hpd_irq_data;
3318         offload_work->offload_wq = offload_wq;
3319
3320         queue_work(offload_wq->wq, &offload_work->work);
3321         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3322 }
3323
3324 static void handle_hpd_rx_irq(void *param)
3325 {
3326         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3327         struct drm_connector *connector = &aconnector->base;
3328         struct drm_device *dev = connector->dev;
3329         struct dc_link *dc_link = aconnector->dc_link;
3330         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3331         bool result = false;
3332         enum dc_connection_type new_connection_type = dc_connection_none;
3333         struct amdgpu_device *adev = drm_to_adev(dev);
3334         union hpd_irq_data hpd_irq_data;
3335         bool link_loss = false;
3336         bool has_left_work = false;
3337         int idx = dc_link->link_index;
3338         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3339
3340         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3341
3342         if (adev->dm.disable_hpd_irq)
3343                 return;
3344
3345         /*
3346          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3347          * conflict, after implement i2c helper, this mutex should be
3348          * retired.
3349          */
3350         mutex_lock(&aconnector->hpd_lock);
3351
3352         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3353                                                 &link_loss, true, &has_left_work);
3354
3355         if (!has_left_work)
3356                 goto out;
3357
3358         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3359                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3360                 goto out;
3361         }
3362
3363         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3364                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3365                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3366                         dm_handle_mst_sideband_msg(aconnector);
3367                         goto out;
3368                 }
3369
3370                 if (link_loss) {
3371                         bool skip = false;
3372
3373                         spin_lock(&offload_wq->offload_lock);
3374                         skip = offload_wq->is_handling_link_loss;
3375
3376                         if (!skip)
3377                                 offload_wq->is_handling_link_loss = true;
3378
3379                         spin_unlock(&offload_wq->offload_lock);
3380
3381                         if (!skip)
3382                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3383
3384                         goto out;
3385                 }
3386         }
3387
3388 out:
3389         if (result && !is_mst_root_connector) {
3390                 /* Downstream Port status changed. */
3391                 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3392                         DRM_ERROR("KMS: Failed to detect connector\n");
3393
3394                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3395                         emulated_link_detect(dc_link);
3396
3397                         if (aconnector->fake_enable)
3398                                 aconnector->fake_enable = false;
3399
3400                         amdgpu_dm_update_connector_after_detect(aconnector);
3401
3402
3403                         drm_modeset_lock_all(dev);
3404                         dm_restore_drm_connector_state(dev, connector);
3405                         drm_modeset_unlock_all(dev);
3406
3407                         drm_kms_helper_connector_hotplug_event(connector);
3408                 } else {
3409                         bool ret = false;
3410
3411                         mutex_lock(&adev->dm.dc_lock);
3412                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3413                         mutex_unlock(&adev->dm.dc_lock);
3414
3415                         if (ret) {
3416                                 if (aconnector->fake_enable)
3417                                         aconnector->fake_enable = false;
3418
3419                                 amdgpu_dm_update_connector_after_detect(aconnector);
3420
3421                                 drm_modeset_lock_all(dev);
3422                                 dm_restore_drm_connector_state(dev, connector);
3423                                 drm_modeset_unlock_all(dev);
3424
3425                                 drm_kms_helper_connector_hotplug_event(connector);
3426                         }
3427                 }
3428         }
3429         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3430                 if (adev->dm.hdcp_workqueue)
3431                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3432         }
3433
3434         if (dc_link->type != dc_connection_mst_branch)
3435                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3436
3437         mutex_unlock(&aconnector->hpd_lock);
3438 }
3439
3440 static void register_hpd_handlers(struct amdgpu_device *adev)
3441 {
3442         struct drm_device *dev = adev_to_drm(adev);
3443         struct drm_connector *connector;
3444         struct amdgpu_dm_connector *aconnector;
3445         const struct dc_link *dc_link;
3446         struct dc_interrupt_params int_params = {0};
3447
3448         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3449         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3450
3451         list_for_each_entry(connector,
3452                         &dev->mode_config.connector_list, head) {
3453
3454                 aconnector = to_amdgpu_dm_connector(connector);
3455                 dc_link = aconnector->dc_link;
3456
3457                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3458                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3459                         int_params.irq_source = dc_link->irq_source_hpd;
3460
3461                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3462                                         handle_hpd_irq,
3463                                         (void *) aconnector);
3464                 }
3465
3466                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3467
3468                         /* Also register for DP short pulse (hpd_rx). */
3469                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3470                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3471
3472                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3473                                         handle_hpd_rx_irq,
3474                                         (void *) aconnector);
3475
3476                         if (adev->dm.hpd_rx_offload_wq)
3477                                 adev->dm.hpd_rx_offload_wq[dc_link->link_index].aconnector =
3478                                         aconnector;
3479                 }
3480         }
3481 }
3482
3483 #if defined(CONFIG_DRM_AMD_DC_SI)
3484 /* Register IRQ sources and initialize IRQ callbacks */
3485 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3486 {
3487         struct dc *dc = adev->dm.dc;
3488         struct common_irq_params *c_irq_params;
3489         struct dc_interrupt_params int_params = {0};
3490         int r;
3491         int i;
3492         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3493
3494         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3495         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3496
3497         /*
3498          * Actions of amdgpu_irq_add_id():
3499          * 1. Register a set() function with base driver.
3500          *    Base driver will call set() function to enable/disable an
3501          *    interrupt in DC hardware.
3502          * 2. Register amdgpu_dm_irq_handler().
3503          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3504          *    coming from DC hardware.
3505          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3506          *    for acknowledging and handling. */
3507
3508         /* Use VBLANK interrupt */
3509         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3510                 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3511                 if (r) {
3512                         DRM_ERROR("Failed to add crtc irq id!\n");
3513                         return r;
3514                 }
3515
3516                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3517                 int_params.irq_source =
3518                         dc_interrupt_to_irq_source(dc, i+1 , 0);
3519
3520                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3521
3522                 c_irq_params->adev = adev;
3523                 c_irq_params->irq_src = int_params.irq_source;
3524
3525                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3526                                 dm_crtc_high_irq, c_irq_params);
3527         }
3528
3529         /* Use GRPH_PFLIP interrupt */
3530         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3531                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3532                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3533                 if (r) {
3534                         DRM_ERROR("Failed to add page flip irq id!\n");
3535                         return r;
3536                 }
3537
3538                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3539                 int_params.irq_source =
3540                         dc_interrupt_to_irq_source(dc, i, 0);
3541
3542                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3543
3544                 c_irq_params->adev = adev;
3545                 c_irq_params->irq_src = int_params.irq_source;
3546
3547                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3548                                 dm_pflip_high_irq, c_irq_params);
3549
3550         }
3551
3552         /* HPD */
3553         r = amdgpu_irq_add_id(adev, client_id,
3554                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3555         if (r) {
3556                 DRM_ERROR("Failed to add hpd irq id!\n");
3557                 return r;
3558         }
3559
3560         register_hpd_handlers(adev);
3561
3562         return 0;
3563 }
3564 #endif
3565
3566 /* Register IRQ sources and initialize IRQ callbacks */
3567 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3568 {
3569         struct dc *dc = adev->dm.dc;
3570         struct common_irq_params *c_irq_params;
3571         struct dc_interrupt_params int_params = {0};
3572         int r;
3573         int i;
3574         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3575
3576         if (adev->family >= AMDGPU_FAMILY_AI)
3577                 client_id = SOC15_IH_CLIENTID_DCE;
3578
3579         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3580         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3581
3582         /*
3583          * Actions of amdgpu_irq_add_id():
3584          * 1. Register a set() function with base driver.
3585          *    Base driver will call set() function to enable/disable an
3586          *    interrupt in DC hardware.
3587          * 2. Register amdgpu_dm_irq_handler().
3588          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3589          *    coming from DC hardware.
3590          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3591          *    for acknowledging and handling. */
3592
3593         /* Use VBLANK interrupt */
3594         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3595                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3596                 if (r) {
3597                         DRM_ERROR("Failed to add crtc irq id!\n");
3598                         return r;
3599                 }
3600
3601                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3602                 int_params.irq_source =
3603                         dc_interrupt_to_irq_source(dc, i, 0);
3604
3605                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3606
3607                 c_irq_params->adev = adev;
3608                 c_irq_params->irq_src = int_params.irq_source;
3609
3610                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3611                                 dm_crtc_high_irq, c_irq_params);
3612         }
3613
3614         /* Use VUPDATE interrupt */
3615         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3616                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3617                 if (r) {
3618                         DRM_ERROR("Failed to add vupdate irq id!\n");
3619                         return r;
3620                 }
3621
3622                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3623                 int_params.irq_source =
3624                         dc_interrupt_to_irq_source(dc, i, 0);
3625
3626                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3627
3628                 c_irq_params->adev = adev;
3629                 c_irq_params->irq_src = int_params.irq_source;
3630
3631                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3632                                 dm_vupdate_high_irq, c_irq_params);
3633         }
3634
3635         /* Use GRPH_PFLIP interrupt */
3636         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3637                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3638                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3639                 if (r) {
3640                         DRM_ERROR("Failed to add page flip irq id!\n");
3641                         return r;
3642                 }
3643
3644                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3645                 int_params.irq_source =
3646                         dc_interrupt_to_irq_source(dc, i, 0);
3647
3648                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3649
3650                 c_irq_params->adev = adev;
3651                 c_irq_params->irq_src = int_params.irq_source;
3652
3653                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3654                                 dm_pflip_high_irq, c_irq_params);
3655
3656         }
3657
3658         /* HPD */
3659         r = amdgpu_irq_add_id(adev, client_id,
3660                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3661         if (r) {
3662                 DRM_ERROR("Failed to add hpd irq id!\n");
3663                 return r;
3664         }
3665
3666         register_hpd_handlers(adev);
3667
3668         return 0;
3669 }
3670
3671 /* Register IRQ sources and initialize IRQ callbacks */
3672 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3673 {
3674         struct dc *dc = adev->dm.dc;
3675         struct common_irq_params *c_irq_params;
3676         struct dc_interrupt_params int_params = {0};
3677         int r;
3678         int i;
3679 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3680         static const unsigned int vrtl_int_srcid[] = {
3681                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3682                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3683                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3684                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3685                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3686                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3687         };
3688 #endif
3689
3690         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3691         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3692
3693         /*
3694          * Actions of amdgpu_irq_add_id():
3695          * 1. Register a set() function with base driver.
3696          *    Base driver will call set() function to enable/disable an
3697          *    interrupt in DC hardware.
3698          * 2. Register amdgpu_dm_irq_handler().
3699          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3700          *    coming from DC hardware.
3701          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3702          *    for acknowledging and handling.
3703          */
3704
3705         /* Use VSTARTUP interrupt */
3706         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3707                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3708                         i++) {
3709                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3710
3711                 if (r) {
3712                         DRM_ERROR("Failed to add crtc irq id!\n");
3713                         return r;
3714                 }
3715
3716                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3717                 int_params.irq_source =
3718                         dc_interrupt_to_irq_source(dc, i, 0);
3719
3720                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3721
3722                 c_irq_params->adev = adev;
3723                 c_irq_params->irq_src = int_params.irq_source;
3724
3725                 amdgpu_dm_irq_register_interrupt(
3726                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3727         }
3728
3729         /* Use otg vertical line interrupt */
3730 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3731         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3732                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3733                                 vrtl_int_srcid[i], &adev->vline0_irq);
3734
3735                 if (r) {
3736                         DRM_ERROR("Failed to add vline0 irq id!\n");
3737                         return r;
3738                 }
3739
3740                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3741                 int_params.irq_source =
3742                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3743
3744                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3745                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3746                         break;
3747                 }
3748
3749                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3750                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3751
3752                 c_irq_params->adev = adev;
3753                 c_irq_params->irq_src = int_params.irq_source;
3754
3755                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3756                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3757         }
3758 #endif
3759
3760         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3761          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3762          * to trigger at end of each vblank, regardless of state of the lock,
3763          * matching DCE behaviour.
3764          */
3765         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3766              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3767              i++) {
3768                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3769
3770                 if (r) {
3771                         DRM_ERROR("Failed to add vupdate irq id!\n");
3772                         return r;
3773                 }
3774
3775                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3776                 int_params.irq_source =
3777                         dc_interrupt_to_irq_source(dc, i, 0);
3778
3779                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3780
3781                 c_irq_params->adev = adev;
3782                 c_irq_params->irq_src = int_params.irq_source;
3783
3784                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3785                                 dm_vupdate_high_irq, c_irq_params);
3786         }
3787
3788         /* Use GRPH_PFLIP interrupt */
3789         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3790                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3791                         i++) {
3792                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3793                 if (r) {
3794                         DRM_ERROR("Failed to add page flip irq id!\n");
3795                         return r;
3796                 }
3797
3798                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3799                 int_params.irq_source =
3800                         dc_interrupt_to_irq_source(dc, i, 0);
3801
3802                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3803
3804                 c_irq_params->adev = adev;
3805                 c_irq_params->irq_src = int_params.irq_source;
3806
3807                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3808                                 dm_pflip_high_irq, c_irq_params);
3809
3810         }
3811
3812         /* HPD */
3813         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3814                         &adev->hpd_irq);
3815         if (r) {
3816                 DRM_ERROR("Failed to add hpd irq id!\n");
3817                 return r;
3818         }
3819
3820         register_hpd_handlers(adev);
3821
3822         return 0;
3823 }
3824 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3825 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3826 {
3827         struct dc *dc = adev->dm.dc;
3828         struct common_irq_params *c_irq_params;
3829         struct dc_interrupt_params int_params = {0};
3830         int r, i;
3831
3832         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3833         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3834
3835         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3836                         &adev->dmub_outbox_irq);
3837         if (r) {
3838                 DRM_ERROR("Failed to add outbox irq id!\n");
3839                 return r;
3840         }
3841
3842         if (dc->ctx->dmub_srv) {
3843                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3844                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3845                 int_params.irq_source =
3846                 dc_interrupt_to_irq_source(dc, i, 0);
3847
3848                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3849
3850                 c_irq_params->adev = adev;
3851                 c_irq_params->irq_src = int_params.irq_source;
3852
3853                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3854                                 dm_dmub_outbox1_low_irq, c_irq_params);
3855         }
3856
3857         return 0;
3858 }
3859
3860 /*
3861  * Acquires the lock for the atomic state object and returns
3862  * the new atomic state.
3863  *
3864  * This should only be called during atomic check.
3865  */
3866 int dm_atomic_get_state(struct drm_atomic_state *state,
3867                         struct dm_atomic_state **dm_state)
3868 {
3869         struct drm_device *dev = state->dev;
3870         struct amdgpu_device *adev = drm_to_adev(dev);
3871         struct amdgpu_display_manager *dm = &adev->dm;
3872         struct drm_private_state *priv_state;
3873
3874         if (*dm_state)
3875                 return 0;
3876
3877         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3878         if (IS_ERR(priv_state))
3879                 return PTR_ERR(priv_state);
3880
3881         *dm_state = to_dm_atomic_state(priv_state);
3882
3883         return 0;
3884 }
3885
3886 static struct dm_atomic_state *
3887 dm_atomic_get_new_state(struct drm_atomic_state *state)
3888 {
3889         struct drm_device *dev = state->dev;
3890         struct amdgpu_device *adev = drm_to_adev(dev);
3891         struct amdgpu_display_manager *dm = &adev->dm;
3892         struct drm_private_obj *obj;
3893         struct drm_private_state *new_obj_state;
3894         int i;
3895
3896         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3897                 if (obj->funcs == dm->atomic_obj.funcs)
3898                         return to_dm_atomic_state(new_obj_state);
3899         }
3900
3901         return NULL;
3902 }
3903
3904 static struct drm_private_state *
3905 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3906 {
3907         struct dm_atomic_state *old_state, *new_state;
3908
3909         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3910         if (!new_state)
3911                 return NULL;
3912
3913         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3914
3915         old_state = to_dm_atomic_state(obj->state);
3916
3917         if (old_state && old_state->context)
3918                 new_state->context = dc_copy_state(old_state->context);
3919
3920         if (!new_state->context) {
3921                 kfree(new_state);
3922                 return NULL;
3923         }
3924
3925         return &new_state->base;
3926 }
3927
3928 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3929                                     struct drm_private_state *state)
3930 {
3931         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3932
3933         if (dm_state && dm_state->context)
3934                 dc_release_state(dm_state->context);
3935
3936         kfree(dm_state);
3937 }
3938
3939 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3940         .atomic_duplicate_state = dm_atomic_duplicate_state,
3941         .atomic_destroy_state = dm_atomic_destroy_state,
3942 };
3943
3944 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3945 {
3946         struct dm_atomic_state *state;
3947         int r;
3948
3949         adev->mode_info.mode_config_initialized = true;
3950
3951         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3952         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3953
3954         adev_to_drm(adev)->mode_config.max_width = 16384;
3955         adev_to_drm(adev)->mode_config.max_height = 16384;
3956
3957         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3958         if (adev->asic_type == CHIP_HAWAII)
3959                 /* disable prefer shadow for now due to hibernation issues */
3960                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3961         else
3962                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3963         /* indicates support for immediate flip */
3964         adev_to_drm(adev)->mode_config.async_page_flip = true;
3965
3966         state = kzalloc(sizeof(*state), GFP_KERNEL);
3967         if (!state)
3968                 return -ENOMEM;
3969
3970         state->context = dc_create_state(adev->dm.dc);
3971         if (!state->context) {
3972                 kfree(state);
3973                 return -ENOMEM;
3974         }
3975
3976         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3977
3978         drm_atomic_private_obj_init(adev_to_drm(adev),
3979                                     &adev->dm.atomic_obj,
3980                                     &state->base,
3981                                     &dm_atomic_state_funcs);
3982
3983         r = amdgpu_display_modeset_create_props(adev);
3984         if (r) {
3985                 dc_release_state(state->context);
3986                 kfree(state);
3987                 return r;
3988         }
3989
3990         r = amdgpu_dm_audio_init(adev);
3991         if (r) {
3992                 dc_release_state(state->context);
3993                 kfree(state);
3994                 return r;
3995         }
3996
3997         return 0;
3998 }
3999
4000 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4001 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4002 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4003
4004 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4005                                             int bl_idx)
4006 {
4007 #if defined(CONFIG_ACPI)
4008         struct amdgpu_dm_backlight_caps caps;
4009
4010         memset(&caps, 0, sizeof(caps));
4011
4012         if (dm->backlight_caps[bl_idx].caps_valid)
4013                 return;
4014
4015         amdgpu_acpi_get_backlight_caps(&caps);
4016         if (caps.caps_valid) {
4017                 dm->backlight_caps[bl_idx].caps_valid = true;
4018                 if (caps.aux_support)
4019                         return;
4020                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4021                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4022         } else {
4023                 dm->backlight_caps[bl_idx].min_input_signal =
4024                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4025                 dm->backlight_caps[bl_idx].max_input_signal =
4026                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4027         }
4028 #else
4029         if (dm->backlight_caps[bl_idx].aux_support)
4030                 return;
4031
4032         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4033         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4034 #endif
4035 }
4036
4037 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4038                                 unsigned *min, unsigned *max)
4039 {
4040         if (!caps)
4041                 return 0;
4042
4043         if (caps->aux_support) {
4044                 // Firmware limits are in nits, DC API wants millinits.
4045                 *max = 1000 * caps->aux_max_input_signal;
4046                 *min = 1000 * caps->aux_min_input_signal;
4047         } else {
4048                 // Firmware limits are 8-bit, PWM control is 16-bit.
4049                 *max = 0x101 * caps->max_input_signal;
4050                 *min = 0x101 * caps->min_input_signal;
4051         }
4052         return 1;
4053 }
4054
4055 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4056                                         uint32_t brightness)
4057 {
4058         unsigned min, max;
4059
4060         if (!get_brightness_range(caps, &min, &max))
4061                 return brightness;
4062
4063         // Rescale 0..255 to min..max
4064         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4065                                        AMDGPU_MAX_BL_LEVEL);
4066 }
4067
4068 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4069                                       uint32_t brightness)
4070 {
4071         unsigned min, max;
4072
4073         if (!get_brightness_range(caps, &min, &max))
4074                 return brightness;
4075
4076         if (brightness < min)
4077                 return 0;
4078         // Rescale min..max to 0..255
4079         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4080                                  max - min);
4081 }
4082
4083 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4084                                          int bl_idx,
4085                                          u32 user_brightness)
4086 {
4087         struct amdgpu_dm_backlight_caps caps;
4088         struct dc_link *link;
4089         u32 brightness;
4090         bool rc;
4091
4092         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4093         caps = dm->backlight_caps[bl_idx];
4094
4095         dm->brightness[bl_idx] = user_brightness;
4096         /* update scratch register */
4097         if (bl_idx == 0)
4098                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4099         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4100         link = (struct dc_link *)dm->backlight_link[bl_idx];
4101
4102         /* Change brightness based on AUX property */
4103         if (caps.aux_support) {
4104                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4105                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4106                 if (!rc)
4107                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4108         } else {
4109                 rc = dc_link_set_backlight_level(link, brightness, 0);
4110                 if (!rc)
4111                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4112         }
4113
4114         if (rc)
4115                 dm->actual_brightness[bl_idx] = user_brightness;
4116 }
4117
4118 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4119 {
4120         struct amdgpu_display_manager *dm = bl_get_data(bd);
4121         int i;
4122
4123         for (i = 0; i < dm->num_of_edps; i++) {
4124                 if (bd == dm->backlight_dev[i])
4125                         break;
4126         }
4127         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4128                 i = 0;
4129         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4130
4131         return 0;
4132 }
4133
4134 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4135                                          int bl_idx)
4136 {
4137         struct amdgpu_dm_backlight_caps caps;
4138         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4139
4140         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4141         caps = dm->backlight_caps[bl_idx];
4142
4143         if (caps.aux_support) {
4144                 u32 avg, peak;
4145                 bool rc;
4146
4147                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4148                 if (!rc)
4149                         return dm->brightness[bl_idx];
4150                 return convert_brightness_to_user(&caps, avg);
4151         } else {
4152                 int ret = dc_link_get_backlight_level(link);
4153
4154                 if (ret == DC_ERROR_UNEXPECTED)
4155                         return dm->brightness[bl_idx];
4156                 return convert_brightness_to_user(&caps, ret);
4157         }
4158 }
4159
4160 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4161 {
4162         struct amdgpu_display_manager *dm = bl_get_data(bd);
4163         int i;
4164
4165         for (i = 0; i < dm->num_of_edps; i++) {
4166                 if (bd == dm->backlight_dev[i])
4167                         break;
4168         }
4169         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4170                 i = 0;
4171         return amdgpu_dm_backlight_get_level(dm, i);
4172 }
4173
4174 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4175         .options = BL_CORE_SUSPENDRESUME,
4176         .get_brightness = amdgpu_dm_backlight_get_brightness,
4177         .update_status  = amdgpu_dm_backlight_update_status,
4178 };
4179
4180 static void
4181 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4182 {
4183         struct drm_device *drm = aconnector->base.dev;
4184         struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4185         struct backlight_properties props = { 0 };
4186         char bl_name[16];
4187
4188         if (aconnector->bl_idx == -1)
4189                 return;
4190
4191         if (!acpi_video_backlight_use_native()) {
4192                 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4193                 /* Try registering an ACPI video backlight device instead. */
4194                 acpi_video_register_backlight();
4195                 return;
4196         }
4197
4198         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4199         props.brightness = AMDGPU_MAX_BL_LEVEL;
4200         props.type = BACKLIGHT_RAW;
4201
4202         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4203                  drm->primary->index + aconnector->bl_idx);
4204
4205         dm->backlight_dev[aconnector->bl_idx] =
4206                 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4207                                           &amdgpu_dm_backlight_ops, &props);
4208
4209         if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4210                 DRM_ERROR("DM: Backlight registration failed!\n");
4211                 dm->backlight_dev[aconnector->bl_idx] = NULL;
4212         } else
4213                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4214 }
4215
4216 static int initialize_plane(struct amdgpu_display_manager *dm,
4217                             struct amdgpu_mode_info *mode_info, int plane_id,
4218                             enum drm_plane_type plane_type,
4219                             const struct dc_plane_cap *plane_cap)
4220 {
4221         struct drm_plane *plane;
4222         unsigned long possible_crtcs;
4223         int ret = 0;
4224
4225         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4226         if (!plane) {
4227                 DRM_ERROR("KMS: Failed to allocate plane\n");
4228                 return -ENOMEM;
4229         }
4230         plane->type = plane_type;
4231
4232         /*
4233          * HACK: IGT tests expect that the primary plane for a CRTC
4234          * can only have one possible CRTC. Only expose support for
4235          * any CRTC if they're not going to be used as a primary plane
4236          * for a CRTC - like overlay or underlay planes.
4237          */
4238         possible_crtcs = 1 << plane_id;
4239         if (plane_id >= dm->dc->caps.max_streams)
4240                 possible_crtcs = 0xff;
4241
4242         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4243
4244         if (ret) {
4245                 DRM_ERROR("KMS: Failed to initialize plane\n");
4246                 kfree(plane);
4247                 return ret;
4248         }
4249
4250         if (mode_info)
4251                 mode_info->planes[plane_id] = plane;
4252
4253         return ret;
4254 }
4255
4256
4257 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4258                                    struct amdgpu_dm_connector *aconnector)
4259 {
4260         struct dc_link *link = aconnector->dc_link;
4261         int bl_idx = dm->num_of_edps;
4262
4263         if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4264             link->type == dc_connection_none)
4265                 return;
4266
4267         if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4268                 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4269                 return;
4270         }
4271
4272         aconnector->bl_idx = bl_idx;
4273
4274         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4275         dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4276         dm->backlight_link[bl_idx] = link;
4277         dm->num_of_edps++;
4278
4279         update_connector_ext_caps(aconnector);
4280 }
4281
4282 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4283
4284 /*
4285  * In this architecture, the association
4286  * connector -> encoder -> crtc
4287  * id not really requried. The crtc and connector will hold the
4288  * display_index as an abstraction to use with DAL component
4289  *
4290  * Returns 0 on success
4291  */
4292 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4293 {
4294         struct amdgpu_display_manager *dm = &adev->dm;
4295         s32 i;
4296         struct amdgpu_dm_connector *aconnector = NULL;
4297         struct amdgpu_encoder *aencoder = NULL;
4298         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4299         u32 link_cnt;
4300         s32 primary_planes;
4301         enum dc_connection_type new_connection_type = dc_connection_none;
4302         const struct dc_plane_cap *plane;
4303         bool psr_feature_enabled = false;
4304         int max_overlay = dm->dc->caps.max_slave_planes;
4305
4306         dm->display_indexes_num = dm->dc->caps.max_streams;
4307         /* Update the actual used number of crtc */
4308         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4309
4310         amdgpu_dm_set_irq_funcs(adev);
4311
4312         link_cnt = dm->dc->caps.max_links;
4313         if (amdgpu_dm_mode_config_init(dm->adev)) {
4314                 DRM_ERROR("DM: Failed to initialize mode config\n");
4315                 return -EINVAL;
4316         }
4317
4318         /* There is one primary plane per CRTC */
4319         primary_planes = dm->dc->caps.max_streams;
4320         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4321
4322         /*
4323          * Initialize primary planes, implicit planes for legacy IOCTLS.
4324          * Order is reversed to match iteration order in atomic check.
4325          */
4326         for (i = (primary_planes - 1); i >= 0; i--) {
4327                 plane = &dm->dc->caps.planes[i];
4328
4329                 if (initialize_plane(dm, mode_info, i,
4330                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4331                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4332                         goto fail;
4333                 }
4334         }
4335
4336         /*
4337          * Initialize overlay planes, index starting after primary planes.
4338          * These planes have a higher DRM index than the primary planes since
4339          * they should be considered as having a higher z-order.
4340          * Order is reversed to match iteration order in atomic check.
4341          *
4342          * Only support DCN for now, and only expose one so we don't encourage
4343          * userspace to use up all the pipes.
4344          */
4345         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4346                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4347
4348                 /* Do not create overlay if MPO disabled */
4349                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4350                         break;
4351
4352                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4353                         continue;
4354
4355                 if (!plane->pixel_format_support.argb8888)
4356                         continue;
4357
4358                 if (max_overlay-- == 0)
4359                         break;
4360
4361                 if (initialize_plane(dm, NULL, primary_planes + i,
4362                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4363                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4364                         goto fail;
4365                 }
4366         }
4367
4368         for (i = 0; i < dm->dc->caps.max_streams; i++)
4369                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4370                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4371                         goto fail;
4372                 }
4373
4374         /* Use Outbox interrupt */
4375         switch (adev->ip_versions[DCE_HWIP][0]) {
4376         case IP_VERSION(3, 0, 0):
4377         case IP_VERSION(3, 1, 2):
4378         case IP_VERSION(3, 1, 3):
4379         case IP_VERSION(3, 1, 4):
4380         case IP_VERSION(3, 1, 5):
4381         case IP_VERSION(3, 1, 6):
4382         case IP_VERSION(3, 2, 0):
4383         case IP_VERSION(3, 2, 1):
4384         case IP_VERSION(2, 1, 0):
4385                 if (register_outbox_irq_handlers(dm->adev)) {
4386                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4387                         goto fail;
4388                 }
4389                 break;
4390         default:
4391                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4392                               adev->ip_versions[DCE_HWIP][0]);
4393         }
4394
4395         /* Determine whether to enable PSR support by default. */
4396         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4397                 switch (adev->ip_versions[DCE_HWIP][0]) {
4398                 case IP_VERSION(3, 1, 2):
4399                 case IP_VERSION(3, 1, 3):
4400                 case IP_VERSION(3, 1, 4):
4401                 case IP_VERSION(3, 1, 5):
4402                 case IP_VERSION(3, 1, 6):
4403                 case IP_VERSION(3, 2, 0):
4404                 case IP_VERSION(3, 2, 1):
4405                         psr_feature_enabled = true;
4406                         break;
4407                 default:
4408                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4409                         break;
4410                 }
4411         }
4412
4413         /* loops over all connectors on the board */
4414         for (i = 0; i < link_cnt; i++) {
4415                 struct dc_link *link = NULL;
4416
4417                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4418                         DRM_ERROR(
4419                                 "KMS: Cannot support more than %d display indexes\n",
4420                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4421                         continue;
4422                 }
4423
4424                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4425                 if (!aconnector)
4426                         goto fail;
4427
4428                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4429                 if (!aencoder)
4430                         goto fail;
4431
4432                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4433                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4434                         goto fail;
4435                 }
4436
4437                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4438                         DRM_ERROR("KMS: Failed to initialize connector\n");
4439                         goto fail;
4440                 }
4441
4442                 link = dc_get_link_at_index(dm->dc, i);
4443
4444                 if (!dc_link_detect_connection_type(link, &new_connection_type))
4445                         DRM_ERROR("KMS: Failed to detect connector\n");
4446
4447                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4448                         emulated_link_detect(link);
4449                         amdgpu_dm_update_connector_after_detect(aconnector);
4450                 } else {
4451                         bool ret = false;
4452
4453                         mutex_lock(&dm->dc_lock);
4454                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4455                         mutex_unlock(&dm->dc_lock);
4456
4457                         if (ret) {
4458                                 amdgpu_dm_update_connector_after_detect(aconnector);
4459                                 setup_backlight_device(dm, aconnector);
4460
4461                                 if (psr_feature_enabled)
4462                                         amdgpu_dm_set_psr_caps(link);
4463
4464                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4465                                  * PSR is also supported.
4466                                  */
4467                                 if (link->psr_settings.psr_feature_enabled)
4468                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4469                         }
4470                 }
4471                 amdgpu_set_panel_orientation(&aconnector->base);
4472         }
4473
4474         /* Software is initialized. Now we can register interrupt handlers. */
4475         switch (adev->asic_type) {
4476 #if defined(CONFIG_DRM_AMD_DC_SI)
4477         case CHIP_TAHITI:
4478         case CHIP_PITCAIRN:
4479         case CHIP_VERDE:
4480         case CHIP_OLAND:
4481                 if (dce60_register_irq_handlers(dm->adev)) {
4482                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4483                         goto fail;
4484                 }
4485                 break;
4486 #endif
4487         case CHIP_BONAIRE:
4488         case CHIP_HAWAII:
4489         case CHIP_KAVERI:
4490         case CHIP_KABINI:
4491         case CHIP_MULLINS:
4492         case CHIP_TONGA:
4493         case CHIP_FIJI:
4494         case CHIP_CARRIZO:
4495         case CHIP_STONEY:
4496         case CHIP_POLARIS11:
4497         case CHIP_POLARIS10:
4498         case CHIP_POLARIS12:
4499         case CHIP_VEGAM:
4500         case CHIP_VEGA10:
4501         case CHIP_VEGA12:
4502         case CHIP_VEGA20:
4503                 if (dce110_register_irq_handlers(dm->adev)) {
4504                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4505                         goto fail;
4506                 }
4507                 break;
4508         default:
4509                 switch (adev->ip_versions[DCE_HWIP][0]) {
4510                 case IP_VERSION(1, 0, 0):
4511                 case IP_VERSION(1, 0, 1):
4512                 case IP_VERSION(2, 0, 2):
4513                 case IP_VERSION(2, 0, 3):
4514                 case IP_VERSION(2, 0, 0):
4515                 case IP_VERSION(2, 1, 0):
4516                 case IP_VERSION(3, 0, 0):
4517                 case IP_VERSION(3, 0, 2):
4518                 case IP_VERSION(3, 0, 3):
4519                 case IP_VERSION(3, 0, 1):
4520                 case IP_VERSION(3, 1, 2):
4521                 case IP_VERSION(3, 1, 3):
4522                 case IP_VERSION(3, 1, 4):
4523                 case IP_VERSION(3, 1, 5):
4524                 case IP_VERSION(3, 1, 6):
4525                 case IP_VERSION(3, 2, 0):
4526                 case IP_VERSION(3, 2, 1):
4527                         if (dcn10_register_irq_handlers(dm->adev)) {
4528                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4529                                 goto fail;
4530                         }
4531                         break;
4532                 default:
4533                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4534                                         adev->ip_versions[DCE_HWIP][0]);
4535                         goto fail;
4536                 }
4537                 break;
4538         }
4539
4540         return 0;
4541 fail:
4542         kfree(aencoder);
4543         kfree(aconnector);
4544
4545         return -EINVAL;
4546 }
4547
4548 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4549 {
4550         drm_atomic_private_obj_fini(&dm->atomic_obj);
4551         return;
4552 }
4553
4554 /******************************************************************************
4555  * amdgpu_display_funcs functions
4556  *****************************************************************************/
4557
4558 /*
4559  * dm_bandwidth_update - program display watermarks
4560  *
4561  * @adev: amdgpu_device pointer
4562  *
4563  * Calculate and program the display watermarks and line buffer allocation.
4564  */
4565 static void dm_bandwidth_update(struct amdgpu_device *adev)
4566 {
4567         /* TODO: implement later */
4568 }
4569
4570 static const struct amdgpu_display_funcs dm_display_funcs = {
4571         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4572         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4573         .backlight_set_level = NULL, /* never called for DC */
4574         .backlight_get_level = NULL, /* never called for DC */
4575         .hpd_sense = NULL,/* called unconditionally */
4576         .hpd_set_polarity = NULL, /* called unconditionally */
4577         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4578         .page_flip_get_scanoutpos =
4579                 dm_crtc_get_scanoutpos,/* called unconditionally */
4580         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4581         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4582 };
4583
4584 #if defined(CONFIG_DEBUG_KERNEL_DC)
4585
4586 static ssize_t s3_debug_store(struct device *device,
4587                               struct device_attribute *attr,
4588                               const char *buf,
4589                               size_t count)
4590 {
4591         int ret;
4592         int s3_state;
4593         struct drm_device *drm_dev = dev_get_drvdata(device);
4594         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4595
4596         ret = kstrtoint(buf, 0, &s3_state);
4597
4598         if (ret == 0) {
4599                 if (s3_state) {
4600                         dm_resume(adev);
4601                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4602                 } else
4603                         dm_suspend(adev);
4604         }
4605
4606         return ret == 0 ? count : 0;
4607 }
4608
4609 DEVICE_ATTR_WO(s3_debug);
4610
4611 #endif
4612
4613 static int dm_init_microcode(struct amdgpu_device *adev)
4614 {
4615         char *fw_name_dmub;
4616         int r;
4617
4618         switch (adev->ip_versions[DCE_HWIP][0]) {
4619         case IP_VERSION(2, 1, 0):
4620                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4621                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4622                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4623                 break;
4624         case IP_VERSION(3, 0, 0):
4625                 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4626                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4627                 else
4628                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4629                 break;
4630         case IP_VERSION(3, 0, 1):
4631                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4632                 break;
4633         case IP_VERSION(3, 0, 2):
4634                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4635                 break;
4636         case IP_VERSION(3, 0, 3):
4637                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4638                 break;
4639         case IP_VERSION(3, 1, 2):
4640         case IP_VERSION(3, 1, 3):
4641                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4642                 break;
4643         case IP_VERSION(3, 1, 4):
4644                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4645                 break;
4646         case IP_VERSION(3, 1, 5):
4647                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4648                 break;
4649         case IP_VERSION(3, 1, 6):
4650                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4651                 break;
4652         case IP_VERSION(3, 2, 0):
4653                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4654                 break;
4655         case IP_VERSION(3, 2, 1):
4656                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4657                 break;
4658         default:
4659                 /* ASIC doesn't support DMUB. */
4660                 return 0;
4661         }
4662         r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4663         if (r)
4664                 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4665         return r;
4666 }
4667
4668 static int dm_early_init(void *handle)
4669 {
4670         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4671         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4672         struct atom_context *ctx = mode_info->atom_context;
4673         int index = GetIndexIntoMasterTable(DATA, Object_Header);
4674         u16 data_offset;
4675
4676         /* if there is no object header, skip DM */
4677         if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4678                 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4679                 dev_info(adev->dev, "No object header, skipping DM\n");
4680                 return -ENOENT;
4681         }
4682
4683         switch (adev->asic_type) {
4684 #if defined(CONFIG_DRM_AMD_DC_SI)
4685         case CHIP_TAHITI:
4686         case CHIP_PITCAIRN:
4687         case CHIP_VERDE:
4688                 adev->mode_info.num_crtc = 6;
4689                 adev->mode_info.num_hpd = 6;
4690                 adev->mode_info.num_dig = 6;
4691                 break;
4692         case CHIP_OLAND:
4693                 adev->mode_info.num_crtc = 2;
4694                 adev->mode_info.num_hpd = 2;
4695                 adev->mode_info.num_dig = 2;
4696                 break;
4697 #endif
4698         case CHIP_BONAIRE:
4699         case CHIP_HAWAII:
4700                 adev->mode_info.num_crtc = 6;
4701                 adev->mode_info.num_hpd = 6;
4702                 adev->mode_info.num_dig = 6;
4703                 break;
4704         case CHIP_KAVERI:
4705                 adev->mode_info.num_crtc = 4;
4706                 adev->mode_info.num_hpd = 6;
4707                 adev->mode_info.num_dig = 7;
4708                 break;
4709         case CHIP_KABINI:
4710         case CHIP_MULLINS:
4711                 adev->mode_info.num_crtc = 2;
4712                 adev->mode_info.num_hpd = 6;
4713                 adev->mode_info.num_dig = 6;
4714                 break;
4715         case CHIP_FIJI:
4716         case CHIP_TONGA:
4717                 adev->mode_info.num_crtc = 6;
4718                 adev->mode_info.num_hpd = 6;
4719                 adev->mode_info.num_dig = 7;
4720                 break;
4721         case CHIP_CARRIZO:
4722                 adev->mode_info.num_crtc = 3;
4723                 adev->mode_info.num_hpd = 6;
4724                 adev->mode_info.num_dig = 9;
4725                 break;
4726         case CHIP_STONEY:
4727                 adev->mode_info.num_crtc = 2;
4728                 adev->mode_info.num_hpd = 6;
4729                 adev->mode_info.num_dig = 9;
4730                 break;
4731         case CHIP_POLARIS11:
4732         case CHIP_POLARIS12:
4733                 adev->mode_info.num_crtc = 5;
4734                 adev->mode_info.num_hpd = 5;
4735                 adev->mode_info.num_dig = 5;
4736                 break;
4737         case CHIP_POLARIS10:
4738         case CHIP_VEGAM:
4739                 adev->mode_info.num_crtc = 6;
4740                 adev->mode_info.num_hpd = 6;
4741                 adev->mode_info.num_dig = 6;
4742                 break;
4743         case CHIP_VEGA10:
4744         case CHIP_VEGA12:
4745         case CHIP_VEGA20:
4746                 adev->mode_info.num_crtc = 6;
4747                 adev->mode_info.num_hpd = 6;
4748                 adev->mode_info.num_dig = 6;
4749                 break;
4750         default:
4751
4752                 switch (adev->ip_versions[DCE_HWIP][0]) {
4753                 case IP_VERSION(2, 0, 2):
4754                 case IP_VERSION(3, 0, 0):
4755                         adev->mode_info.num_crtc = 6;
4756                         adev->mode_info.num_hpd = 6;
4757                         adev->mode_info.num_dig = 6;
4758                         break;
4759                 case IP_VERSION(2, 0, 0):
4760                 case IP_VERSION(3, 0, 2):
4761                         adev->mode_info.num_crtc = 5;
4762                         adev->mode_info.num_hpd = 5;
4763                         adev->mode_info.num_dig = 5;
4764                         break;
4765                 case IP_VERSION(2, 0, 3):
4766                 case IP_VERSION(3, 0, 3):
4767                         adev->mode_info.num_crtc = 2;
4768                         adev->mode_info.num_hpd = 2;
4769                         adev->mode_info.num_dig = 2;
4770                         break;
4771                 case IP_VERSION(1, 0, 0):
4772                 case IP_VERSION(1, 0, 1):
4773                 case IP_VERSION(3, 0, 1):
4774                 case IP_VERSION(2, 1, 0):
4775                 case IP_VERSION(3, 1, 2):
4776                 case IP_VERSION(3, 1, 3):
4777                 case IP_VERSION(3, 1, 4):
4778                 case IP_VERSION(3, 1, 5):
4779                 case IP_VERSION(3, 1, 6):
4780                 case IP_VERSION(3, 2, 0):
4781                 case IP_VERSION(3, 2, 1):
4782                         adev->mode_info.num_crtc = 4;
4783                         adev->mode_info.num_hpd = 4;
4784                         adev->mode_info.num_dig = 4;
4785                         break;
4786                 default:
4787                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4788                                         adev->ip_versions[DCE_HWIP][0]);
4789                         return -EINVAL;
4790                 }
4791                 break;
4792         }
4793
4794         if (adev->mode_info.funcs == NULL)
4795                 adev->mode_info.funcs = &dm_display_funcs;
4796
4797         /*
4798          * Note: Do NOT change adev->audio_endpt_rreg and
4799          * adev->audio_endpt_wreg because they are initialised in
4800          * amdgpu_device_init()
4801          */
4802 #if defined(CONFIG_DEBUG_KERNEL_DC)
4803         device_create_file(
4804                 adev_to_drm(adev)->dev,
4805                 &dev_attr_s3_debug);
4806 #endif
4807         adev->dc_enabled = true;
4808
4809         return dm_init_microcode(adev);
4810 }
4811
4812 static bool modereset_required(struct drm_crtc_state *crtc_state)
4813 {
4814         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4815 }
4816
4817 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4818 {
4819         drm_encoder_cleanup(encoder);
4820         kfree(encoder);
4821 }
4822
4823 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4824         .destroy = amdgpu_dm_encoder_destroy,
4825 };
4826
4827 static int
4828 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4829                             const enum surface_pixel_format format,
4830                             enum dc_color_space *color_space)
4831 {
4832         bool full_range;
4833
4834         *color_space = COLOR_SPACE_SRGB;
4835
4836         /* DRM color properties only affect non-RGB formats. */
4837         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4838                 return 0;
4839
4840         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4841
4842         switch (plane_state->color_encoding) {
4843         case DRM_COLOR_YCBCR_BT601:
4844                 if (full_range)
4845                         *color_space = COLOR_SPACE_YCBCR601;
4846                 else
4847                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4848                 break;
4849
4850         case DRM_COLOR_YCBCR_BT709:
4851                 if (full_range)
4852                         *color_space = COLOR_SPACE_YCBCR709;
4853                 else
4854                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4855                 break;
4856
4857         case DRM_COLOR_YCBCR_BT2020:
4858                 if (full_range)
4859                         *color_space = COLOR_SPACE_2020_YCBCR;
4860                 else
4861                         return -EINVAL;
4862                 break;
4863
4864         default:
4865                 return -EINVAL;
4866         }
4867
4868         return 0;
4869 }
4870
4871 static int
4872 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4873                             const struct drm_plane_state *plane_state,
4874                             const u64 tiling_flags,
4875                             struct dc_plane_info *plane_info,
4876                             struct dc_plane_address *address,
4877                             bool tmz_surface,
4878                             bool force_disable_dcc)
4879 {
4880         const struct drm_framebuffer *fb = plane_state->fb;
4881         const struct amdgpu_framebuffer *afb =
4882                 to_amdgpu_framebuffer(plane_state->fb);
4883         int ret;
4884
4885         memset(plane_info, 0, sizeof(*plane_info));
4886
4887         switch (fb->format->format) {
4888         case DRM_FORMAT_C8:
4889                 plane_info->format =
4890                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4891                 break;
4892         case DRM_FORMAT_RGB565:
4893                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4894                 break;
4895         case DRM_FORMAT_XRGB8888:
4896         case DRM_FORMAT_ARGB8888:
4897                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4898                 break;
4899         case DRM_FORMAT_XRGB2101010:
4900         case DRM_FORMAT_ARGB2101010:
4901                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4902                 break;
4903         case DRM_FORMAT_XBGR2101010:
4904         case DRM_FORMAT_ABGR2101010:
4905                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4906                 break;
4907         case DRM_FORMAT_XBGR8888:
4908         case DRM_FORMAT_ABGR8888:
4909                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4910                 break;
4911         case DRM_FORMAT_NV21:
4912                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4913                 break;
4914         case DRM_FORMAT_NV12:
4915                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4916                 break;
4917         case DRM_FORMAT_P010:
4918                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4919                 break;
4920         case DRM_FORMAT_XRGB16161616F:
4921         case DRM_FORMAT_ARGB16161616F:
4922                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4923                 break;
4924         case DRM_FORMAT_XBGR16161616F:
4925         case DRM_FORMAT_ABGR16161616F:
4926                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4927                 break;
4928         case DRM_FORMAT_XRGB16161616:
4929         case DRM_FORMAT_ARGB16161616:
4930                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4931                 break;
4932         case DRM_FORMAT_XBGR16161616:
4933         case DRM_FORMAT_ABGR16161616:
4934                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4935                 break;
4936         default:
4937                 DRM_ERROR(
4938                         "Unsupported screen format %p4cc\n",
4939                         &fb->format->format);
4940                 return -EINVAL;
4941         }
4942
4943         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4944         case DRM_MODE_ROTATE_0:
4945                 plane_info->rotation = ROTATION_ANGLE_0;
4946                 break;
4947         case DRM_MODE_ROTATE_90:
4948                 plane_info->rotation = ROTATION_ANGLE_90;
4949                 break;
4950         case DRM_MODE_ROTATE_180:
4951                 plane_info->rotation = ROTATION_ANGLE_180;
4952                 break;
4953         case DRM_MODE_ROTATE_270:
4954                 plane_info->rotation = ROTATION_ANGLE_270;
4955                 break;
4956         default:
4957                 plane_info->rotation = ROTATION_ANGLE_0;
4958                 break;
4959         }
4960
4961
4962         plane_info->visible = true;
4963         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4964
4965         plane_info->layer_index = plane_state->normalized_zpos;
4966
4967         ret = fill_plane_color_attributes(plane_state, plane_info->format,
4968                                           &plane_info->color_space);
4969         if (ret)
4970                 return ret;
4971
4972         ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
4973                                            plane_info->rotation, tiling_flags,
4974                                            &plane_info->tiling_info,
4975                                            &plane_info->plane_size,
4976                                            &plane_info->dcc, address,
4977                                            tmz_surface, force_disable_dcc);
4978         if (ret)
4979                 return ret;
4980
4981         amdgpu_dm_plane_fill_blending_from_plane_state(
4982                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4983                 &plane_info->global_alpha, &plane_info->global_alpha_value);
4984
4985         return 0;
4986 }
4987
4988 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4989                                     struct dc_plane_state *dc_plane_state,
4990                                     struct drm_plane_state *plane_state,
4991                                     struct drm_crtc_state *crtc_state)
4992 {
4993         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4994         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
4995         struct dc_scaling_info scaling_info;
4996         struct dc_plane_info plane_info;
4997         int ret;
4998         bool force_disable_dcc = false;
4999
5000         ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5001         if (ret)
5002                 return ret;
5003
5004         dc_plane_state->src_rect = scaling_info.src_rect;
5005         dc_plane_state->dst_rect = scaling_info.dst_rect;
5006         dc_plane_state->clip_rect = scaling_info.clip_rect;
5007         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5008
5009         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5010         ret = fill_dc_plane_info_and_addr(adev, plane_state,
5011                                           afb->tiling_flags,
5012                                           &plane_info,
5013                                           &dc_plane_state->address,
5014                                           afb->tmz_surface,
5015                                           force_disable_dcc);
5016         if (ret)
5017                 return ret;
5018
5019         dc_plane_state->format = plane_info.format;
5020         dc_plane_state->color_space = plane_info.color_space;
5021         dc_plane_state->format = plane_info.format;
5022         dc_plane_state->plane_size = plane_info.plane_size;
5023         dc_plane_state->rotation = plane_info.rotation;
5024         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5025         dc_plane_state->stereo_format = plane_info.stereo_format;
5026         dc_plane_state->tiling_info = plane_info.tiling_info;
5027         dc_plane_state->visible = plane_info.visible;
5028         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5029         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5030         dc_plane_state->global_alpha = plane_info.global_alpha;
5031         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5032         dc_plane_state->dcc = plane_info.dcc;
5033         dc_plane_state->layer_index = plane_info.layer_index;
5034         dc_plane_state->flip_int_enabled = true;
5035
5036         /*
5037          * Always set input transfer function, since plane state is refreshed
5038          * every time.
5039          */
5040         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5041         if (ret)
5042                 return ret;
5043
5044         return 0;
5045 }
5046
5047 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5048                                       struct rect *dirty_rect, int32_t x,
5049                                       s32 y, s32 width, s32 height,
5050                                       int *i, bool ffu)
5051 {
5052         if (*i > DC_MAX_DIRTY_RECTS)
5053                 return;
5054
5055         if (*i == DC_MAX_DIRTY_RECTS)
5056                 goto out;
5057
5058         dirty_rect->x = x;
5059         dirty_rect->y = y;
5060         dirty_rect->width = width;
5061         dirty_rect->height = height;
5062
5063         if (ffu)
5064                 drm_dbg(plane->dev,
5065                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5066                         plane->base.id, width, height);
5067         else
5068                 drm_dbg(plane->dev,
5069                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5070                         plane->base.id, x, y, width, height);
5071
5072 out:
5073         (*i)++;
5074 }
5075
5076 /**
5077  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5078  *
5079  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5080  *         remote fb
5081  * @old_plane_state: Old state of @plane
5082  * @new_plane_state: New state of @plane
5083  * @crtc_state: New state of CRTC connected to the @plane
5084  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5085  * @dirty_regions_changed: dirty regions changed
5086  *
5087  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5088  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5089  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5090  * amdgpu_dm's.
5091  *
5092  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5093  * plane with regions that require flushing to the eDP remote buffer. In
5094  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5095  * implicitly provide damage clips without any client support via the plane
5096  * bounds.
5097  */
5098 static void fill_dc_dirty_rects(struct drm_plane *plane,
5099                                 struct drm_plane_state *old_plane_state,
5100                                 struct drm_plane_state *new_plane_state,
5101                                 struct drm_crtc_state *crtc_state,
5102                                 struct dc_flip_addrs *flip_addrs,
5103                                 bool *dirty_regions_changed)
5104 {
5105         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5106         struct rect *dirty_rects = flip_addrs->dirty_rects;
5107         u32 num_clips;
5108         struct drm_mode_rect *clips;
5109         bool bb_changed;
5110         bool fb_changed;
5111         u32 i = 0;
5112         *dirty_regions_changed = false;
5113
5114         /*
5115          * Cursor plane has it's own dirty rect update interface. See
5116          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5117          */
5118         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5119                 return;
5120
5121         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5122         clips = drm_plane_get_damage_clips(new_plane_state);
5123
5124         if (!dm_crtc_state->mpo_requested) {
5125                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5126                         goto ffu;
5127
5128                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5129                         fill_dc_dirty_rect(new_plane_state->plane,
5130                                            &dirty_rects[flip_addrs->dirty_rect_count],
5131                                            clips->x1, clips->y1,
5132                                            clips->x2 - clips->x1, clips->y2 - clips->y1,
5133                                            &flip_addrs->dirty_rect_count,
5134                                            false);
5135                 return;
5136         }
5137
5138         /*
5139          * MPO is requested. Add entire plane bounding box to dirty rects if
5140          * flipped to or damaged.
5141          *
5142          * If plane is moved or resized, also add old bounding box to dirty
5143          * rects.
5144          */
5145         fb_changed = old_plane_state->fb->base.id !=
5146                      new_plane_state->fb->base.id;
5147         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5148                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
5149                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
5150                       old_plane_state->crtc_h != new_plane_state->crtc_h);
5151
5152         drm_dbg(plane->dev,
5153                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5154                 new_plane_state->plane->base.id,
5155                 bb_changed, fb_changed, num_clips);
5156
5157         *dirty_regions_changed = bb_changed;
5158
5159         if (bb_changed) {
5160                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5161                                    new_plane_state->crtc_x,
5162                                    new_plane_state->crtc_y,
5163                                    new_plane_state->crtc_w,
5164                                    new_plane_state->crtc_h, &i, false);
5165
5166                 /* Add old plane bounding-box if plane is moved or resized */
5167                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5168                                    old_plane_state->crtc_x,
5169                                    old_plane_state->crtc_y,
5170                                    old_plane_state->crtc_w,
5171                                    old_plane_state->crtc_h, &i, false);
5172         }
5173
5174         if (num_clips) {
5175                 for (; i < num_clips; clips++)
5176                         fill_dc_dirty_rect(new_plane_state->plane,
5177                                            &dirty_rects[i], clips->x1,
5178                                            clips->y1, clips->x2 - clips->x1,
5179                                            clips->y2 - clips->y1, &i, false);
5180         } else if (fb_changed && !bb_changed) {
5181                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5182                                    new_plane_state->crtc_x,
5183                                    new_plane_state->crtc_y,
5184                                    new_plane_state->crtc_w,
5185                                    new_plane_state->crtc_h, &i, false);
5186         }
5187
5188         if (i > DC_MAX_DIRTY_RECTS)
5189                 goto ffu;
5190
5191         flip_addrs->dirty_rect_count = i;
5192         return;
5193
5194 ffu:
5195         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5196                            dm_crtc_state->base.mode.crtc_hdisplay,
5197                            dm_crtc_state->base.mode.crtc_vdisplay,
5198                            &flip_addrs->dirty_rect_count, true);
5199 }
5200
5201 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5202                                            const struct dm_connector_state *dm_state,
5203                                            struct dc_stream_state *stream)
5204 {
5205         enum amdgpu_rmx_type rmx_type;
5206
5207         struct rect src = { 0 }; /* viewport in composition space*/
5208         struct rect dst = { 0 }; /* stream addressable area */
5209
5210         /* no mode. nothing to be done */
5211         if (!mode)
5212                 return;
5213
5214         /* Full screen scaling by default */
5215         src.width = mode->hdisplay;
5216         src.height = mode->vdisplay;
5217         dst.width = stream->timing.h_addressable;
5218         dst.height = stream->timing.v_addressable;
5219
5220         if (dm_state) {
5221                 rmx_type = dm_state->scaling;
5222                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5223                         if (src.width * dst.height <
5224                                         src.height * dst.width) {
5225                                 /* height needs less upscaling/more downscaling */
5226                                 dst.width = src.width *
5227                                                 dst.height / src.height;
5228                         } else {
5229                                 /* width needs less upscaling/more downscaling */
5230                                 dst.height = src.height *
5231                                                 dst.width / src.width;
5232                         }
5233                 } else if (rmx_type == RMX_CENTER) {
5234                         dst = src;
5235                 }
5236
5237                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5238                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5239
5240                 if (dm_state->underscan_enable) {
5241                         dst.x += dm_state->underscan_hborder / 2;
5242                         dst.y += dm_state->underscan_vborder / 2;
5243                         dst.width -= dm_state->underscan_hborder;
5244                         dst.height -= dm_state->underscan_vborder;
5245                 }
5246         }
5247
5248         stream->src = src;
5249         stream->dst = dst;
5250
5251         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5252                       dst.x, dst.y, dst.width, dst.height);
5253
5254 }
5255
5256 static enum dc_color_depth
5257 convert_color_depth_from_display_info(const struct drm_connector *connector,
5258                                       bool is_y420, int requested_bpc)
5259 {
5260         u8 bpc;
5261
5262         if (is_y420) {
5263                 bpc = 8;
5264
5265                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5266                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5267                         bpc = 16;
5268                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5269                         bpc = 12;
5270                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5271                         bpc = 10;
5272         } else {
5273                 bpc = (uint8_t)connector->display_info.bpc;
5274                 /* Assume 8 bpc by default if no bpc is specified. */
5275                 bpc = bpc ? bpc : 8;
5276         }
5277
5278         if (requested_bpc > 0) {
5279                 /*
5280                  * Cap display bpc based on the user requested value.
5281                  *
5282                  * The value for state->max_bpc may not correctly updated
5283                  * depending on when the connector gets added to the state
5284                  * or if this was called outside of atomic check, so it
5285                  * can't be used directly.
5286                  */
5287                 bpc = min_t(u8, bpc, requested_bpc);
5288
5289                 /* Round down to the nearest even number. */
5290                 bpc = bpc - (bpc & 1);
5291         }
5292
5293         switch (bpc) {
5294         case 0:
5295                 /*
5296                  * Temporary Work around, DRM doesn't parse color depth for
5297                  * EDID revision before 1.4
5298                  * TODO: Fix edid parsing
5299                  */
5300                 return COLOR_DEPTH_888;
5301         case 6:
5302                 return COLOR_DEPTH_666;
5303         case 8:
5304                 return COLOR_DEPTH_888;
5305         case 10:
5306                 return COLOR_DEPTH_101010;
5307         case 12:
5308                 return COLOR_DEPTH_121212;
5309         case 14:
5310                 return COLOR_DEPTH_141414;
5311         case 16:
5312                 return COLOR_DEPTH_161616;
5313         default:
5314                 return COLOR_DEPTH_UNDEFINED;
5315         }
5316 }
5317
5318 static enum dc_aspect_ratio
5319 get_aspect_ratio(const struct drm_display_mode *mode_in)
5320 {
5321         /* 1-1 mapping, since both enums follow the HDMI spec. */
5322         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5323 }
5324
5325 static enum dc_color_space
5326 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5327 {
5328         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5329
5330         switch (dc_crtc_timing->pixel_encoding) {
5331         case PIXEL_ENCODING_YCBCR422:
5332         case PIXEL_ENCODING_YCBCR444:
5333         case PIXEL_ENCODING_YCBCR420:
5334         {
5335                 /*
5336                  * 27030khz is the separation point between HDTV and SDTV
5337                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5338                  * respectively
5339                  */
5340                 if (dc_crtc_timing->pix_clk_100hz > 270300) {
5341                         if (dc_crtc_timing->flags.Y_ONLY)
5342                                 color_space =
5343                                         COLOR_SPACE_YCBCR709_LIMITED;
5344                         else
5345                                 color_space = COLOR_SPACE_YCBCR709;
5346                 } else {
5347                         if (dc_crtc_timing->flags.Y_ONLY)
5348                                 color_space =
5349                                         COLOR_SPACE_YCBCR601_LIMITED;
5350                         else
5351                                 color_space = COLOR_SPACE_YCBCR601;
5352                 }
5353
5354         }
5355         break;
5356         case PIXEL_ENCODING_RGB:
5357                 color_space = COLOR_SPACE_SRGB;
5358                 break;
5359
5360         default:
5361                 WARN_ON(1);
5362                 break;
5363         }
5364
5365         return color_space;
5366 }
5367
5368 static bool adjust_colour_depth_from_display_info(
5369         struct dc_crtc_timing *timing_out,
5370         const struct drm_display_info *info)
5371 {
5372         enum dc_color_depth depth = timing_out->display_color_depth;
5373         int normalized_clk;
5374         do {
5375                 normalized_clk = timing_out->pix_clk_100hz / 10;
5376                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5377                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5378                         normalized_clk /= 2;
5379                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5380                 switch (depth) {
5381                 case COLOR_DEPTH_888:
5382                         break;
5383                 case COLOR_DEPTH_101010:
5384                         normalized_clk = (normalized_clk * 30) / 24;
5385                         break;
5386                 case COLOR_DEPTH_121212:
5387                         normalized_clk = (normalized_clk * 36) / 24;
5388                         break;
5389                 case COLOR_DEPTH_161616:
5390                         normalized_clk = (normalized_clk * 48) / 24;
5391                         break;
5392                 default:
5393                         /* The above depths are the only ones valid for HDMI. */
5394                         return false;
5395                 }
5396                 if (normalized_clk <= info->max_tmds_clock) {
5397                         timing_out->display_color_depth = depth;
5398                         return true;
5399                 }
5400         } while (--depth > COLOR_DEPTH_666);
5401         return false;
5402 }
5403
5404 static void fill_stream_properties_from_drm_display_mode(
5405         struct dc_stream_state *stream,
5406         const struct drm_display_mode *mode_in,
5407         const struct drm_connector *connector,
5408         const struct drm_connector_state *connector_state,
5409         const struct dc_stream_state *old_stream,
5410         int requested_bpc)
5411 {
5412         struct dc_crtc_timing *timing_out = &stream->timing;
5413         const struct drm_display_info *info = &connector->display_info;
5414         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5415         struct hdmi_vendor_infoframe hv_frame;
5416         struct hdmi_avi_infoframe avi_frame;
5417
5418         memset(&hv_frame, 0, sizeof(hv_frame));
5419         memset(&avi_frame, 0, sizeof(avi_frame));
5420
5421         timing_out->h_border_left = 0;
5422         timing_out->h_border_right = 0;
5423         timing_out->v_border_top = 0;
5424         timing_out->v_border_bottom = 0;
5425         /* TODO: un-hardcode */
5426         if (drm_mode_is_420_only(info, mode_in)
5427                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5428                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5429         else if (drm_mode_is_420_also(info, mode_in)
5430                         && aconnector->force_yuv420_output)
5431                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5432         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5433                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5434                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5435         else
5436                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5437
5438         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5439         timing_out->display_color_depth = convert_color_depth_from_display_info(
5440                 connector,
5441                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5442                 requested_bpc);
5443         timing_out->scan_type = SCANNING_TYPE_NODATA;
5444         timing_out->hdmi_vic = 0;
5445
5446         if (old_stream) {
5447                 timing_out->vic = old_stream->timing.vic;
5448                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5449                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5450         } else {
5451                 timing_out->vic = drm_match_cea_mode(mode_in);
5452                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5453                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5454                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5455                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5456         }
5457
5458         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5459                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5460                 timing_out->vic = avi_frame.video_code;
5461                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5462                 timing_out->hdmi_vic = hv_frame.vic;
5463         }
5464
5465         if (is_freesync_video_mode(mode_in, aconnector)) {
5466                 timing_out->h_addressable = mode_in->hdisplay;
5467                 timing_out->h_total = mode_in->htotal;
5468                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5469                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5470                 timing_out->v_total = mode_in->vtotal;
5471                 timing_out->v_addressable = mode_in->vdisplay;
5472                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5473                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5474                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5475         } else {
5476                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5477                 timing_out->h_total = mode_in->crtc_htotal;
5478                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5479                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5480                 timing_out->v_total = mode_in->crtc_vtotal;
5481                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5482                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5483                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5484                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5485         }
5486
5487         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5488
5489         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5490         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5491         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5492                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5493                     drm_mode_is_420_also(info, mode_in) &&
5494                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5495                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5496                         adjust_colour_depth_from_display_info(timing_out, info);
5497                 }
5498         }
5499
5500         stream->output_color_space = get_output_color_space(timing_out);
5501 }
5502
5503 static void fill_audio_info(struct audio_info *audio_info,
5504                             const struct drm_connector *drm_connector,
5505                             const struct dc_sink *dc_sink)
5506 {
5507         int i = 0;
5508         int cea_revision = 0;
5509         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5510
5511         audio_info->manufacture_id = edid_caps->manufacturer_id;
5512         audio_info->product_id = edid_caps->product_id;
5513
5514         cea_revision = drm_connector->display_info.cea_rev;
5515
5516         strscpy(audio_info->display_name,
5517                 edid_caps->display_name,
5518                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5519
5520         if (cea_revision >= 3) {
5521                 audio_info->mode_count = edid_caps->audio_mode_count;
5522
5523                 for (i = 0; i < audio_info->mode_count; ++i) {
5524                         audio_info->modes[i].format_code =
5525                                         (enum audio_format_code)
5526                                         (edid_caps->audio_modes[i].format_code);
5527                         audio_info->modes[i].channel_count =
5528                                         edid_caps->audio_modes[i].channel_count;
5529                         audio_info->modes[i].sample_rates.all =
5530                                         edid_caps->audio_modes[i].sample_rate;
5531                         audio_info->modes[i].sample_size =
5532                                         edid_caps->audio_modes[i].sample_size;
5533                 }
5534         }
5535
5536         audio_info->flags.all = edid_caps->speaker_flags;
5537
5538         /* TODO: We only check for the progressive mode, check for interlace mode too */
5539         if (drm_connector->latency_present[0]) {
5540                 audio_info->video_latency = drm_connector->video_latency[0];
5541                 audio_info->audio_latency = drm_connector->audio_latency[0];
5542         }
5543
5544         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5545
5546 }
5547
5548 static void
5549 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5550                                       struct drm_display_mode *dst_mode)
5551 {
5552         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5553         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5554         dst_mode->crtc_clock = src_mode->crtc_clock;
5555         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5556         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5557         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5558         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5559         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5560         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5561         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5562         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5563         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5564         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5565         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5566 }
5567
5568 static void
5569 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5570                                         const struct drm_display_mode *native_mode,
5571                                         bool scale_enabled)
5572 {
5573         if (scale_enabled) {
5574                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5575         } else if (native_mode->clock == drm_mode->clock &&
5576                         native_mode->htotal == drm_mode->htotal &&
5577                         native_mode->vtotal == drm_mode->vtotal) {
5578                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5579         } else {
5580                 /* no scaling nor amdgpu inserted, no need to patch */
5581         }
5582 }
5583
5584 static struct dc_sink *
5585 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5586 {
5587         struct dc_sink_init_data sink_init_data = { 0 };
5588         struct dc_sink *sink = NULL;
5589         sink_init_data.link = aconnector->dc_link;
5590         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5591
5592         sink = dc_sink_create(&sink_init_data);
5593         if (!sink) {
5594                 DRM_ERROR("Failed to create sink!\n");
5595                 return NULL;
5596         }
5597         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5598
5599         return sink;
5600 }
5601
5602 static void set_multisync_trigger_params(
5603                 struct dc_stream_state *stream)
5604 {
5605         struct dc_stream_state *master = NULL;
5606
5607         if (stream->triggered_crtc_reset.enabled) {
5608                 master = stream->triggered_crtc_reset.event_source;
5609                 stream->triggered_crtc_reset.event =
5610                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5611                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5612                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5613         }
5614 }
5615
5616 static void set_master_stream(struct dc_stream_state *stream_set[],
5617                               int stream_count)
5618 {
5619         int j, highest_rfr = 0, master_stream = 0;
5620
5621         for (j = 0;  j < stream_count; j++) {
5622                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5623                         int refresh_rate = 0;
5624
5625                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5626                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5627                         if (refresh_rate > highest_rfr) {
5628                                 highest_rfr = refresh_rate;
5629                                 master_stream = j;
5630                         }
5631                 }
5632         }
5633         for (j = 0;  j < stream_count; j++) {
5634                 if (stream_set[j])
5635                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5636         }
5637 }
5638
5639 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5640 {
5641         int i = 0;
5642         struct dc_stream_state *stream;
5643
5644         if (context->stream_count < 2)
5645                 return;
5646         for (i = 0; i < context->stream_count ; i++) {
5647                 if (!context->streams[i])
5648                         continue;
5649                 /*
5650                  * TODO: add a function to read AMD VSDB bits and set
5651                  * crtc_sync_master.multi_sync_enabled flag
5652                  * For now it's set to false
5653                  */
5654         }
5655
5656         set_master_stream(context->streams, context->stream_count);
5657
5658         for (i = 0; i < context->stream_count ; i++) {
5659                 stream = context->streams[i];
5660
5661                 if (!stream)
5662                         continue;
5663
5664                 set_multisync_trigger_params(stream);
5665         }
5666 }
5667
5668 /**
5669  * DOC: FreeSync Video
5670  *
5671  * When a userspace application wants to play a video, the content follows a
5672  * standard format definition that usually specifies the FPS for that format.
5673  * The below list illustrates some video format and the expected FPS,
5674  * respectively:
5675  *
5676  * - TV/NTSC (23.976 FPS)
5677  * - Cinema (24 FPS)
5678  * - TV/PAL (25 FPS)
5679  * - TV/NTSC (29.97 FPS)
5680  * - TV/NTSC (30 FPS)
5681  * - Cinema HFR (48 FPS)
5682  * - TV/PAL (50 FPS)
5683  * - Commonly used (60 FPS)
5684  * - Multiples of 24 (48,72,96 FPS)
5685  *
5686  * The list of standards video format is not huge and can be added to the
5687  * connector modeset list beforehand. With that, userspace can leverage
5688  * FreeSync to extends the front porch in order to attain the target refresh
5689  * rate. Such a switch will happen seamlessly, without screen blanking or
5690  * reprogramming of the output in any other way. If the userspace requests a
5691  * modesetting change compatible with FreeSync modes that only differ in the
5692  * refresh rate, DC will skip the full update and avoid blink during the
5693  * transition. For example, the video player can change the modesetting from
5694  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5695  * causing any display blink. This same concept can be applied to a mode
5696  * setting change.
5697  */
5698 static struct drm_display_mode *
5699 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5700                 bool use_probed_modes)
5701 {
5702         struct drm_display_mode *m, *m_pref = NULL;
5703         u16 current_refresh, highest_refresh;
5704         struct list_head *list_head = use_probed_modes ?
5705                 &aconnector->base.probed_modes :
5706                 &aconnector->base.modes;
5707
5708         if (aconnector->freesync_vid_base.clock != 0)
5709                 return &aconnector->freesync_vid_base;
5710
5711         /* Find the preferred mode */
5712         list_for_each_entry (m, list_head, head) {
5713                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5714                         m_pref = m;
5715                         break;
5716                 }
5717         }
5718
5719         if (!m_pref) {
5720                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5721                 m_pref = list_first_entry_or_null(
5722                                 &aconnector->base.modes, struct drm_display_mode, head);
5723                 if (!m_pref) {
5724                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5725                         return NULL;
5726                 }
5727         }
5728
5729         highest_refresh = drm_mode_vrefresh(m_pref);
5730
5731         /*
5732          * Find the mode with highest refresh rate with same resolution.
5733          * For some monitors, preferred mode is not the mode with highest
5734          * supported refresh rate.
5735          */
5736         list_for_each_entry (m, list_head, head) {
5737                 current_refresh  = drm_mode_vrefresh(m);
5738
5739                 if (m->hdisplay == m_pref->hdisplay &&
5740                     m->vdisplay == m_pref->vdisplay &&
5741                     highest_refresh < current_refresh) {
5742                         highest_refresh = current_refresh;
5743                         m_pref = m;
5744                 }
5745         }
5746
5747         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5748         return m_pref;
5749 }
5750
5751 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5752                 struct amdgpu_dm_connector *aconnector)
5753 {
5754         struct drm_display_mode *high_mode;
5755         int timing_diff;
5756
5757         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5758         if (!high_mode || !mode)
5759                 return false;
5760
5761         timing_diff = high_mode->vtotal - mode->vtotal;
5762
5763         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5764             high_mode->hdisplay != mode->hdisplay ||
5765             high_mode->vdisplay != mode->vdisplay ||
5766             high_mode->hsync_start != mode->hsync_start ||
5767             high_mode->hsync_end != mode->hsync_end ||
5768             high_mode->htotal != mode->htotal ||
5769             high_mode->hskew != mode->hskew ||
5770             high_mode->vscan != mode->vscan ||
5771             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5772             high_mode->vsync_end - mode->vsync_end != timing_diff)
5773                 return false;
5774         else
5775                 return true;
5776 }
5777
5778 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5779                             struct dc_sink *sink, struct dc_stream_state *stream,
5780                             struct dsc_dec_dpcd_caps *dsc_caps)
5781 {
5782         stream->timing.flags.DSC = 0;
5783         dsc_caps->is_dsc_supported = false;
5784
5785         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5786             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5787                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5788                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5789                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5790                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5791                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5792                                 dsc_caps);
5793         }
5794 }
5795
5796
5797 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5798                                     struct dc_sink *sink, struct dc_stream_state *stream,
5799                                     struct dsc_dec_dpcd_caps *dsc_caps,
5800                                     uint32_t max_dsc_target_bpp_limit_override)
5801 {
5802         const struct dc_link_settings *verified_link_cap = NULL;
5803         u32 link_bw_in_kbps;
5804         u32 edp_min_bpp_x16, edp_max_bpp_x16;
5805         struct dc *dc = sink->ctx->dc;
5806         struct dc_dsc_bw_range bw_range = {0};
5807         struct dc_dsc_config dsc_cfg = {0};
5808         struct dc_dsc_config_options dsc_options = {0};
5809
5810         dc_dsc_get_default_config_option(dc, &dsc_options);
5811         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5812
5813         verified_link_cap = dc_link_get_link_cap(stream->link);
5814         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5815         edp_min_bpp_x16 = 8 * 16;
5816         edp_max_bpp_x16 = 8 * 16;
5817
5818         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5819                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5820
5821         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5822                 edp_min_bpp_x16 = edp_max_bpp_x16;
5823
5824         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5825                                 dc->debug.dsc_min_slice_height_override,
5826                                 edp_min_bpp_x16, edp_max_bpp_x16,
5827                                 dsc_caps,
5828                                 &stream->timing,
5829                                 &bw_range)) {
5830
5831                 if (bw_range.max_kbps < link_bw_in_kbps) {
5832                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5833                                         dsc_caps,
5834                                         &dsc_options,
5835                                         0,
5836                                         &stream->timing,
5837                                         &dsc_cfg)) {
5838                                 stream->timing.dsc_cfg = dsc_cfg;
5839                                 stream->timing.flags.DSC = 1;
5840                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5841                         }
5842                         return;
5843                 }
5844         }
5845
5846         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5847                                 dsc_caps,
5848                                 &dsc_options,
5849                                 link_bw_in_kbps,
5850                                 &stream->timing,
5851                                 &dsc_cfg)) {
5852                 stream->timing.dsc_cfg = dsc_cfg;
5853                 stream->timing.flags.DSC = 1;
5854         }
5855 }
5856
5857
5858 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5859                                         struct dc_sink *sink, struct dc_stream_state *stream,
5860                                         struct dsc_dec_dpcd_caps *dsc_caps)
5861 {
5862         struct drm_connector *drm_connector = &aconnector->base;
5863         u32 link_bandwidth_kbps;
5864         struct dc *dc = sink->ctx->dc;
5865         u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5866         u32 dsc_max_supported_bw_in_kbps;
5867         u32 max_dsc_target_bpp_limit_override =
5868                 drm_connector->display_info.max_dsc_bpp;
5869         struct dc_dsc_config_options dsc_options = {0};
5870
5871         dc_dsc_get_default_config_option(dc, &dsc_options);
5872         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5873
5874         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5875                                                         dc_link_get_link_cap(aconnector->dc_link));
5876
5877         /* Set DSC policy according to dsc_clock_en */
5878         dc_dsc_policy_set_enable_dsc_when_not_needed(
5879                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5880
5881         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5882             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5883             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5884
5885                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5886
5887         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5888                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5889                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5890                                                 dsc_caps,
5891                                                 &dsc_options,
5892                                                 link_bandwidth_kbps,
5893                                                 &stream->timing,
5894                                                 &stream->timing.dsc_cfg)) {
5895                                 stream->timing.flags.DSC = 1;
5896                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5897                         }
5898                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5899                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5900                         max_supported_bw_in_kbps = link_bandwidth_kbps;
5901                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5902
5903                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5904                                         max_supported_bw_in_kbps > 0 &&
5905                                         dsc_max_supported_bw_in_kbps > 0)
5906                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5907                                                 dsc_caps,
5908                                                 &dsc_options,
5909                                                 dsc_max_supported_bw_in_kbps,
5910                                                 &stream->timing,
5911                                                 &stream->timing.dsc_cfg)) {
5912                                         stream->timing.flags.DSC = 1;
5913                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5914                                                                          __func__, drm_connector->name);
5915                                 }
5916                 }
5917         }
5918
5919         /* Overwrite the stream flag if DSC is enabled through debugfs */
5920         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5921                 stream->timing.flags.DSC = 1;
5922
5923         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5924                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5925
5926         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5927                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5928
5929         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5930                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5931 }
5932
5933 static struct dc_stream_state *
5934 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5935                        const struct drm_display_mode *drm_mode,
5936                        const struct dm_connector_state *dm_state,
5937                        const struct dc_stream_state *old_stream,
5938                        int requested_bpc)
5939 {
5940         struct drm_display_mode *preferred_mode = NULL;
5941         struct drm_connector *drm_connector;
5942         const struct drm_connector_state *con_state =
5943                 dm_state ? &dm_state->base : NULL;
5944         struct dc_stream_state *stream = NULL;
5945         struct drm_display_mode mode;
5946         struct drm_display_mode saved_mode;
5947         struct drm_display_mode *freesync_mode = NULL;
5948         bool native_mode_found = false;
5949         bool recalculate_timing = false;
5950         bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5951         int mode_refresh;
5952         int preferred_refresh = 0;
5953         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
5954         struct dsc_dec_dpcd_caps dsc_caps;
5955
5956         struct dc_sink *sink = NULL;
5957
5958         drm_mode_init(&mode, drm_mode);
5959         memset(&saved_mode, 0, sizeof(saved_mode));
5960
5961         if (aconnector == NULL) {
5962                 DRM_ERROR("aconnector is NULL!\n");
5963                 return stream;
5964         }
5965
5966         drm_connector = &aconnector->base;
5967
5968         if (!aconnector->dc_sink) {
5969                 sink = create_fake_sink(aconnector);
5970                 if (!sink)
5971                         return stream;
5972         } else {
5973                 sink = aconnector->dc_sink;
5974                 dc_sink_retain(sink);
5975         }
5976
5977         stream = dc_create_stream_for_sink(sink);
5978
5979         if (stream == NULL) {
5980                 DRM_ERROR("Failed to create stream for sink!\n");
5981                 goto finish;
5982         }
5983
5984         stream->dm_stream_context = aconnector;
5985
5986         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5987                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5988
5989         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5990                 /* Search for preferred mode */
5991                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
5992                         native_mode_found = true;
5993                         break;
5994                 }
5995         }
5996         if (!native_mode_found)
5997                 preferred_mode = list_first_entry_or_null(
5998                                 &aconnector->base.modes,
5999                                 struct drm_display_mode,
6000                                 head);
6001
6002         mode_refresh = drm_mode_vrefresh(&mode);
6003
6004         if (preferred_mode == NULL) {
6005                 /*
6006                  * This may not be an error, the use case is when we have no
6007                  * usermode calls to reset and set mode upon hotplug. In this
6008                  * case, we call set mode ourselves to restore the previous mode
6009                  * and the modelist may not be filled in in time.
6010                  */
6011                 DRM_DEBUG_DRIVER("No preferred mode found\n");
6012         } else {
6013                 recalculate_timing = amdgpu_freesync_vid_mode &&
6014                                  is_freesync_video_mode(&mode, aconnector);
6015                 if (recalculate_timing) {
6016                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6017                         drm_mode_copy(&saved_mode, &mode);
6018                         drm_mode_copy(&mode, freesync_mode);
6019                 } else {
6020                         decide_crtc_timing_for_drm_display_mode(
6021                                         &mode, preferred_mode, scale);
6022
6023                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
6024                 }
6025         }
6026
6027         if (recalculate_timing)
6028                 drm_mode_set_crtcinfo(&saved_mode, 0);
6029         else if (!dm_state)
6030                 drm_mode_set_crtcinfo(&mode, 0);
6031
6032         /*
6033         * If scaling is enabled and refresh rate didn't change
6034         * we copy the vic and polarities of the old timings
6035         */
6036         if (!scale || mode_refresh != preferred_refresh)
6037                 fill_stream_properties_from_drm_display_mode(
6038                         stream, &mode, &aconnector->base, con_state, NULL,
6039                         requested_bpc);
6040         else
6041                 fill_stream_properties_from_drm_display_mode(
6042                         stream, &mode, &aconnector->base, con_state, old_stream,
6043                         requested_bpc);
6044
6045         if (aconnector->timing_changed) {
6046                 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",
6047                                 __func__,
6048                                 stream->timing.display_color_depth,
6049                                 aconnector->timing_requested->display_color_depth);
6050                 stream->timing = *aconnector->timing_requested;
6051         }
6052
6053         /* SST DSC determination policy */
6054         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6055         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6056                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6057
6058         update_stream_scaling_settings(&mode, dm_state, stream);
6059
6060         fill_audio_info(
6061                 &stream->audio_info,
6062                 drm_connector,
6063                 sink);
6064
6065         update_stream_signal(stream, sink);
6066
6067         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6068                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6069
6070         if (stream->link->psr_settings.psr_feature_enabled) {
6071                 //
6072                 // should decide stream support vsc sdp colorimetry capability
6073                 // before building vsc info packet
6074                 //
6075                 stream->use_vsc_sdp_for_colorimetry = false;
6076                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6077                         stream->use_vsc_sdp_for_colorimetry =
6078                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6079                 } else {
6080                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6081                                 stream->use_vsc_sdp_for_colorimetry = true;
6082                 }
6083                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6084                         tf = TRANSFER_FUNC_GAMMA_22;
6085                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6086                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6087
6088         }
6089 finish:
6090         dc_sink_release(sink);
6091
6092         return stream;
6093 }
6094
6095 static enum drm_connector_status
6096 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6097 {
6098         bool connected;
6099         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6100
6101         /*
6102          * Notes:
6103          * 1. This interface is NOT called in context of HPD irq.
6104          * 2. This interface *is called* in context of user-mode ioctl. Which
6105          * makes it a bad place for *any* MST-related activity.
6106          */
6107
6108         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6109             !aconnector->fake_enable)
6110                 connected = (aconnector->dc_sink != NULL);
6111         else
6112                 connected = (aconnector->base.force == DRM_FORCE_ON ||
6113                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6114
6115         update_subconnector_property(aconnector);
6116
6117         return (connected ? connector_status_connected :
6118                         connector_status_disconnected);
6119 }
6120
6121 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6122                                             struct drm_connector_state *connector_state,
6123                                             struct drm_property *property,
6124                                             uint64_t val)
6125 {
6126         struct drm_device *dev = connector->dev;
6127         struct amdgpu_device *adev = drm_to_adev(dev);
6128         struct dm_connector_state *dm_old_state =
6129                 to_dm_connector_state(connector->state);
6130         struct dm_connector_state *dm_new_state =
6131                 to_dm_connector_state(connector_state);
6132
6133         int ret = -EINVAL;
6134
6135         if (property == dev->mode_config.scaling_mode_property) {
6136                 enum amdgpu_rmx_type rmx_type;
6137
6138                 switch (val) {
6139                 case DRM_MODE_SCALE_CENTER:
6140                         rmx_type = RMX_CENTER;
6141                         break;
6142                 case DRM_MODE_SCALE_ASPECT:
6143                         rmx_type = RMX_ASPECT;
6144                         break;
6145                 case DRM_MODE_SCALE_FULLSCREEN:
6146                         rmx_type = RMX_FULL;
6147                         break;
6148                 case DRM_MODE_SCALE_NONE:
6149                 default:
6150                         rmx_type = RMX_OFF;
6151                         break;
6152                 }
6153
6154                 if (dm_old_state->scaling == rmx_type)
6155                         return 0;
6156
6157                 dm_new_state->scaling = rmx_type;
6158                 ret = 0;
6159         } else if (property == adev->mode_info.underscan_hborder_property) {
6160                 dm_new_state->underscan_hborder = val;
6161                 ret = 0;
6162         } else if (property == adev->mode_info.underscan_vborder_property) {
6163                 dm_new_state->underscan_vborder = val;
6164                 ret = 0;
6165         } else if (property == adev->mode_info.underscan_property) {
6166                 dm_new_state->underscan_enable = val;
6167                 ret = 0;
6168         } else if (property == adev->mode_info.abm_level_property) {
6169                 dm_new_state->abm_level = val;
6170                 ret = 0;
6171         }
6172
6173         return ret;
6174 }
6175
6176 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6177                                             const struct drm_connector_state *state,
6178                                             struct drm_property *property,
6179                                             uint64_t *val)
6180 {
6181         struct drm_device *dev = connector->dev;
6182         struct amdgpu_device *adev = drm_to_adev(dev);
6183         struct dm_connector_state *dm_state =
6184                 to_dm_connector_state(state);
6185         int ret = -EINVAL;
6186
6187         if (property == dev->mode_config.scaling_mode_property) {
6188                 switch (dm_state->scaling) {
6189                 case RMX_CENTER:
6190                         *val = DRM_MODE_SCALE_CENTER;
6191                         break;
6192                 case RMX_ASPECT:
6193                         *val = DRM_MODE_SCALE_ASPECT;
6194                         break;
6195                 case RMX_FULL:
6196                         *val = DRM_MODE_SCALE_FULLSCREEN;
6197                         break;
6198                 case RMX_OFF:
6199                 default:
6200                         *val = DRM_MODE_SCALE_NONE;
6201                         break;
6202                 }
6203                 ret = 0;
6204         } else if (property == adev->mode_info.underscan_hborder_property) {
6205                 *val = dm_state->underscan_hborder;
6206                 ret = 0;
6207         } else if (property == adev->mode_info.underscan_vborder_property) {
6208                 *val = dm_state->underscan_vborder;
6209                 ret = 0;
6210         } else if (property == adev->mode_info.underscan_property) {
6211                 *val = dm_state->underscan_enable;
6212                 ret = 0;
6213         } else if (property == adev->mode_info.abm_level_property) {
6214                 *val = dm_state->abm_level;
6215                 ret = 0;
6216         }
6217
6218         return ret;
6219 }
6220
6221 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6222 {
6223         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6224
6225         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6226 }
6227
6228 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6229 {
6230         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6231         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6232         struct amdgpu_display_manager *dm = &adev->dm;
6233
6234         /*
6235          * Call only if mst_mgr was initialized before since it's not done
6236          * for all connector types.
6237          */
6238         if (aconnector->mst_mgr.dev)
6239                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6240
6241         if (aconnector->bl_idx != -1) {
6242                 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6243                 dm->backlight_dev[aconnector->bl_idx] = NULL;
6244         }
6245
6246         if (aconnector->dc_em_sink)
6247                 dc_sink_release(aconnector->dc_em_sink);
6248         aconnector->dc_em_sink = NULL;
6249         if (aconnector->dc_sink)
6250                 dc_sink_release(aconnector->dc_sink);
6251         aconnector->dc_sink = NULL;
6252
6253         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6254         drm_connector_unregister(connector);
6255         drm_connector_cleanup(connector);
6256         if (aconnector->i2c) {
6257                 i2c_del_adapter(&aconnector->i2c->base);
6258                 kfree(aconnector->i2c);
6259         }
6260         kfree(aconnector->dm_dp_aux.aux.name);
6261
6262         kfree(connector);
6263 }
6264
6265 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6266 {
6267         struct dm_connector_state *state =
6268                 to_dm_connector_state(connector->state);
6269
6270         if (connector->state)
6271                 __drm_atomic_helper_connector_destroy_state(connector->state);
6272
6273         kfree(state);
6274
6275         state = kzalloc(sizeof(*state), GFP_KERNEL);
6276
6277         if (state) {
6278                 state->scaling = RMX_OFF;
6279                 state->underscan_enable = false;
6280                 state->underscan_hborder = 0;
6281                 state->underscan_vborder = 0;
6282                 state->base.max_requested_bpc = 8;
6283                 state->vcpi_slots = 0;
6284                 state->pbn = 0;
6285
6286                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6287                         state->abm_level = amdgpu_dm_abm_level;
6288
6289                 __drm_atomic_helper_connector_reset(connector, &state->base);
6290         }
6291 }
6292
6293 struct drm_connector_state *
6294 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6295 {
6296         struct dm_connector_state *state =
6297                 to_dm_connector_state(connector->state);
6298
6299         struct dm_connector_state *new_state =
6300                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6301
6302         if (!new_state)
6303                 return NULL;
6304
6305         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6306
6307         new_state->freesync_capable = state->freesync_capable;
6308         new_state->abm_level = state->abm_level;
6309         new_state->scaling = state->scaling;
6310         new_state->underscan_enable = state->underscan_enable;
6311         new_state->underscan_hborder = state->underscan_hborder;
6312         new_state->underscan_vborder = state->underscan_vborder;
6313         new_state->vcpi_slots = state->vcpi_slots;
6314         new_state->pbn = state->pbn;
6315         return &new_state->base;
6316 }
6317
6318 static int
6319 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6320 {
6321         struct amdgpu_dm_connector *amdgpu_dm_connector =
6322                 to_amdgpu_dm_connector(connector);
6323         int r;
6324
6325         amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6326
6327         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6328             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6329                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6330                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6331                 if (r)
6332                         return r;
6333         }
6334
6335 #if defined(CONFIG_DEBUG_FS)
6336         connector_debugfs_init(amdgpu_dm_connector);
6337 #endif
6338
6339         return 0;
6340 }
6341
6342 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6343         .reset = amdgpu_dm_connector_funcs_reset,
6344         .detect = amdgpu_dm_connector_detect,
6345         .fill_modes = drm_helper_probe_single_connector_modes,
6346         .destroy = amdgpu_dm_connector_destroy,
6347         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6348         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6349         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6350         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6351         .late_register = amdgpu_dm_connector_late_register,
6352         .early_unregister = amdgpu_dm_connector_unregister
6353 };
6354
6355 static int get_modes(struct drm_connector *connector)
6356 {
6357         return amdgpu_dm_connector_get_modes(connector);
6358 }
6359
6360 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6361 {
6362         struct dc_sink_init_data init_params = {
6363                         .link = aconnector->dc_link,
6364                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6365         };
6366         struct edid *edid;
6367
6368         if (!aconnector->base.edid_blob_ptr) {
6369                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6370                                 aconnector->base.name);
6371
6372                 aconnector->base.force = DRM_FORCE_OFF;
6373                 return;
6374         }
6375
6376         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6377
6378         aconnector->edid = edid;
6379
6380         aconnector->dc_em_sink = dc_link_add_remote_sink(
6381                 aconnector->dc_link,
6382                 (uint8_t *)edid,
6383                 (edid->extensions + 1) * EDID_LENGTH,
6384                 &init_params);
6385
6386         if (aconnector->base.force == DRM_FORCE_ON) {
6387                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6388                 aconnector->dc_link->local_sink :
6389                 aconnector->dc_em_sink;
6390                 dc_sink_retain(aconnector->dc_sink);
6391         }
6392 }
6393
6394 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6395 {
6396         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6397
6398         /*
6399          * In case of headless boot with force on for DP managed connector
6400          * Those settings have to be != 0 to get initial modeset
6401          */
6402         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6403                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6404                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6405         }
6406
6407         create_eml_sink(aconnector);
6408 }
6409
6410 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6411                                                 struct dc_stream_state *stream)
6412 {
6413         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6414         struct dc_plane_state *dc_plane_state = NULL;
6415         struct dc_state *dc_state = NULL;
6416
6417         if (!stream)
6418                 goto cleanup;
6419
6420         dc_plane_state = dc_create_plane_state(dc);
6421         if (!dc_plane_state)
6422                 goto cleanup;
6423
6424         dc_state = dc_create_state(dc);
6425         if (!dc_state)
6426                 goto cleanup;
6427
6428         /* populate stream to plane */
6429         dc_plane_state->src_rect.height  = stream->src.height;
6430         dc_plane_state->src_rect.width   = stream->src.width;
6431         dc_plane_state->dst_rect.height  = stream->src.height;
6432         dc_plane_state->dst_rect.width   = stream->src.width;
6433         dc_plane_state->clip_rect.height = stream->src.height;
6434         dc_plane_state->clip_rect.width  = stream->src.width;
6435         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6436         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6437         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6438         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6439         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6440         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6441         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6442         dc_plane_state->rotation = ROTATION_ANGLE_0;
6443         dc_plane_state->is_tiling_rotated = false;
6444         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6445
6446         dc_result = dc_validate_stream(dc, stream);
6447         if (dc_result == DC_OK)
6448                 dc_result = dc_validate_plane(dc, dc_plane_state);
6449
6450         if (dc_result == DC_OK)
6451                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6452
6453         if (dc_result == DC_OK && !dc_add_plane_to_context(
6454                                                 dc,
6455                                                 stream,
6456                                                 dc_plane_state,
6457                                                 dc_state))
6458                 dc_result = DC_FAIL_ATTACH_SURFACES;
6459
6460         if (dc_result == DC_OK)
6461                 dc_result = dc_validate_global_state(dc, dc_state, true);
6462
6463 cleanup:
6464         if (dc_state)
6465                 dc_release_state(dc_state);
6466
6467         if (dc_plane_state)
6468                 dc_plane_state_release(dc_plane_state);
6469
6470         return dc_result;
6471 }
6472
6473 struct dc_stream_state *
6474 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6475                                 const struct drm_display_mode *drm_mode,
6476                                 const struct dm_connector_state *dm_state,
6477                                 const struct dc_stream_state *old_stream)
6478 {
6479         struct drm_connector *connector = &aconnector->base;
6480         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6481         struct dc_stream_state *stream;
6482         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6483         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6484         enum dc_status dc_result = DC_OK;
6485
6486         do {
6487                 stream = create_stream_for_sink(aconnector, drm_mode,
6488                                                 dm_state, old_stream,
6489                                                 requested_bpc);
6490                 if (stream == NULL) {
6491                         DRM_ERROR("Failed to create stream for sink!\n");
6492                         break;
6493                 }
6494
6495                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6496                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6497                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6498
6499                 if (dc_result == DC_OK)
6500                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6501
6502                 if (dc_result != DC_OK) {
6503                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6504                                       drm_mode->hdisplay,
6505                                       drm_mode->vdisplay,
6506                                       drm_mode->clock,
6507                                       dc_result,
6508                                       dc_status_to_str(dc_result));
6509
6510                         dc_stream_release(stream);
6511                         stream = NULL;
6512                         requested_bpc -= 2; /* lower bpc to retry validation */
6513                 }
6514
6515         } while (stream == NULL && requested_bpc >= 6);
6516
6517         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6518                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6519
6520                 aconnector->force_yuv420_output = true;
6521                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6522                                                 dm_state, old_stream);
6523                 aconnector->force_yuv420_output = false;
6524         }
6525
6526         return stream;
6527 }
6528
6529 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6530                                    struct drm_display_mode *mode)
6531 {
6532         int result = MODE_ERROR;
6533         struct dc_sink *dc_sink;
6534         /* TODO: Unhardcode stream count */
6535         struct dc_stream_state *stream;
6536         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6537
6538         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6539                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6540                 return result;
6541
6542         /*
6543          * Only run this the first time mode_valid is called to initilialize
6544          * EDID mgmt
6545          */
6546         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6547                 !aconnector->dc_em_sink)
6548                 handle_edid_mgmt(aconnector);
6549
6550         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6551
6552         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6553                                 aconnector->base.force != DRM_FORCE_ON) {
6554                 DRM_ERROR("dc_sink is NULL!\n");
6555                 goto fail;
6556         }
6557
6558         stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6559         if (stream) {
6560                 dc_stream_release(stream);
6561                 result = MODE_OK;
6562         }
6563
6564 fail:
6565         /* TODO: error handling*/
6566         return result;
6567 }
6568
6569 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6570                                 struct dc_info_packet *out)
6571 {
6572         struct hdmi_drm_infoframe frame;
6573         unsigned char buf[30]; /* 26 + 4 */
6574         ssize_t len;
6575         int ret, i;
6576
6577         memset(out, 0, sizeof(*out));
6578
6579         if (!state->hdr_output_metadata)
6580                 return 0;
6581
6582         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6583         if (ret)
6584                 return ret;
6585
6586         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6587         if (len < 0)
6588                 return (int)len;
6589
6590         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6591         if (len != 30)
6592                 return -EINVAL;
6593
6594         /* Prepare the infopacket for DC. */
6595         switch (state->connector->connector_type) {
6596         case DRM_MODE_CONNECTOR_HDMIA:
6597                 out->hb0 = 0x87; /* type */
6598                 out->hb1 = 0x01; /* version */
6599                 out->hb2 = 0x1A; /* length */
6600                 out->sb[0] = buf[3]; /* checksum */
6601                 i = 1;
6602                 break;
6603
6604         case DRM_MODE_CONNECTOR_DisplayPort:
6605         case DRM_MODE_CONNECTOR_eDP:
6606                 out->hb0 = 0x00; /* sdp id, zero */
6607                 out->hb1 = 0x87; /* type */
6608                 out->hb2 = 0x1D; /* payload len - 1 */
6609                 out->hb3 = (0x13 << 2); /* sdp version */
6610                 out->sb[0] = 0x01; /* version */
6611                 out->sb[1] = 0x1A; /* length */
6612                 i = 2;
6613                 break;
6614
6615         default:
6616                 return -EINVAL;
6617         }
6618
6619         memcpy(&out->sb[i], &buf[4], 26);
6620         out->valid = true;
6621
6622         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6623                        sizeof(out->sb), false);
6624
6625         return 0;
6626 }
6627
6628 static int
6629 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6630                                  struct drm_atomic_state *state)
6631 {
6632         struct drm_connector_state *new_con_state =
6633                 drm_atomic_get_new_connector_state(state, conn);
6634         struct drm_connector_state *old_con_state =
6635                 drm_atomic_get_old_connector_state(state, conn);
6636         struct drm_crtc *crtc = new_con_state->crtc;
6637         struct drm_crtc_state *new_crtc_state;
6638         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6639         int ret;
6640
6641         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6642
6643         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6644                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6645                 if (ret < 0)
6646                         return ret;
6647         }
6648
6649         if (!crtc)
6650                 return 0;
6651
6652         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6653                 struct dc_info_packet hdr_infopacket;
6654
6655                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6656                 if (ret)
6657                         return ret;
6658
6659                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6660                 if (IS_ERR(new_crtc_state))
6661                         return PTR_ERR(new_crtc_state);
6662
6663                 /*
6664                  * DC considers the stream backends changed if the
6665                  * static metadata changes. Forcing the modeset also
6666                  * gives a simple way for userspace to switch from
6667                  * 8bpc to 10bpc when setting the metadata to enter
6668                  * or exit HDR.
6669                  *
6670                  * Changing the static metadata after it's been
6671                  * set is permissible, however. So only force a
6672                  * modeset if we're entering or exiting HDR.
6673                  */
6674                 new_crtc_state->mode_changed =
6675                         !old_con_state->hdr_output_metadata ||
6676                         !new_con_state->hdr_output_metadata;
6677         }
6678
6679         return 0;
6680 }
6681
6682 static const struct drm_connector_helper_funcs
6683 amdgpu_dm_connector_helper_funcs = {
6684         /*
6685          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6686          * modes will be filtered by drm_mode_validate_size(), and those modes
6687          * are missing after user start lightdm. So we need to renew modes list.
6688          * in get_modes call back, not just return the modes count
6689          */
6690         .get_modes = get_modes,
6691         .mode_valid = amdgpu_dm_connector_mode_valid,
6692         .atomic_check = amdgpu_dm_connector_atomic_check,
6693 };
6694
6695 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6696 {
6697
6698 }
6699
6700 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6701 {
6702         switch (display_color_depth) {
6703         case COLOR_DEPTH_666:
6704                 return 6;
6705         case COLOR_DEPTH_888:
6706                 return 8;
6707         case COLOR_DEPTH_101010:
6708                 return 10;
6709         case COLOR_DEPTH_121212:
6710                 return 12;
6711         case COLOR_DEPTH_141414:
6712                 return 14;
6713         case COLOR_DEPTH_161616:
6714                 return 16;
6715         default:
6716                 break;
6717         }
6718         return 0;
6719 }
6720
6721 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6722                                           struct drm_crtc_state *crtc_state,
6723                                           struct drm_connector_state *conn_state)
6724 {
6725         struct drm_atomic_state *state = crtc_state->state;
6726         struct drm_connector *connector = conn_state->connector;
6727         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6728         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6729         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6730         struct drm_dp_mst_topology_mgr *mst_mgr;
6731         struct drm_dp_mst_port *mst_port;
6732         struct drm_dp_mst_topology_state *mst_state;
6733         enum dc_color_depth color_depth;
6734         int clock, bpp = 0;
6735         bool is_y420 = false;
6736
6737         if (!aconnector->mst_output_port || !aconnector->dc_sink)
6738                 return 0;
6739
6740         mst_port = aconnector->mst_output_port;
6741         mst_mgr = &aconnector->mst_root->mst_mgr;
6742
6743         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6744                 return 0;
6745
6746         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6747         if (IS_ERR(mst_state))
6748                 return PTR_ERR(mst_state);
6749
6750         if (!mst_state->pbn_div)
6751                 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6752
6753         if (!state->duplicated) {
6754                 int max_bpc = conn_state->max_requested_bpc;
6755                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6756                           aconnector->force_yuv420_output;
6757                 color_depth = convert_color_depth_from_display_info(connector,
6758                                                                     is_y420,
6759                                                                     max_bpc);
6760                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6761                 clock = adjusted_mode->clock;
6762                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6763         }
6764
6765         dm_new_connector_state->vcpi_slots =
6766                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6767                                               dm_new_connector_state->pbn);
6768         if (dm_new_connector_state->vcpi_slots < 0) {
6769                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6770                 return dm_new_connector_state->vcpi_slots;
6771         }
6772         return 0;
6773 }
6774
6775 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6776         .disable = dm_encoder_helper_disable,
6777         .atomic_check = dm_encoder_helper_atomic_check
6778 };
6779
6780 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6781                                             struct dc_state *dc_state,
6782                                             struct dsc_mst_fairness_vars *vars)
6783 {
6784         struct dc_stream_state *stream = NULL;
6785         struct drm_connector *connector;
6786         struct drm_connector_state *new_con_state;
6787         struct amdgpu_dm_connector *aconnector;
6788         struct dm_connector_state *dm_conn_state;
6789         int i, j, ret;
6790         int vcpi, pbn_div, pbn, slot_num = 0;
6791
6792         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6793
6794                 aconnector = to_amdgpu_dm_connector(connector);
6795
6796                 if (!aconnector->mst_output_port)
6797                         continue;
6798
6799                 if (!new_con_state || !new_con_state->crtc)
6800                         continue;
6801
6802                 dm_conn_state = to_dm_connector_state(new_con_state);
6803
6804                 for (j = 0; j < dc_state->stream_count; j++) {
6805                         stream = dc_state->streams[j];
6806                         if (!stream)
6807                                 continue;
6808
6809                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6810                                 break;
6811
6812                         stream = NULL;
6813                 }
6814
6815                 if (!stream)
6816                         continue;
6817
6818                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6819                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6820                 for (j = 0; j < dc_state->stream_count; j++) {
6821                         if (vars[j].aconnector == aconnector) {
6822                                 pbn = vars[j].pbn;
6823                                 break;
6824                         }
6825                 }
6826
6827                 if (j == dc_state->stream_count)
6828                         continue;
6829
6830                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6831
6832                 if (stream->timing.flags.DSC != 1) {
6833                         dm_conn_state->pbn = pbn;
6834                         dm_conn_state->vcpi_slots = slot_num;
6835
6836                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6837                                                            dm_conn_state->pbn, false);
6838                         if (ret < 0)
6839                                 return ret;
6840
6841                         continue;
6842                 }
6843
6844                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
6845                 if (vcpi < 0)
6846                         return vcpi;
6847
6848                 dm_conn_state->pbn = pbn;
6849                 dm_conn_state->vcpi_slots = vcpi;
6850         }
6851         return 0;
6852 }
6853
6854 static int to_drm_connector_type(enum signal_type st)
6855 {
6856         switch (st) {
6857         case SIGNAL_TYPE_HDMI_TYPE_A:
6858                 return DRM_MODE_CONNECTOR_HDMIA;
6859         case SIGNAL_TYPE_EDP:
6860                 return DRM_MODE_CONNECTOR_eDP;
6861         case SIGNAL_TYPE_LVDS:
6862                 return DRM_MODE_CONNECTOR_LVDS;
6863         case SIGNAL_TYPE_RGB:
6864                 return DRM_MODE_CONNECTOR_VGA;
6865         case SIGNAL_TYPE_DISPLAY_PORT:
6866         case SIGNAL_TYPE_DISPLAY_PORT_MST:
6867                 return DRM_MODE_CONNECTOR_DisplayPort;
6868         case SIGNAL_TYPE_DVI_DUAL_LINK:
6869         case SIGNAL_TYPE_DVI_SINGLE_LINK:
6870                 return DRM_MODE_CONNECTOR_DVID;
6871         case SIGNAL_TYPE_VIRTUAL:
6872                 return DRM_MODE_CONNECTOR_VIRTUAL;
6873
6874         default:
6875                 return DRM_MODE_CONNECTOR_Unknown;
6876         }
6877 }
6878
6879 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6880 {
6881         struct drm_encoder *encoder;
6882
6883         /* There is only one encoder per connector */
6884         drm_connector_for_each_possible_encoder(connector, encoder)
6885                 return encoder;
6886
6887         return NULL;
6888 }
6889
6890 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6891 {
6892         struct drm_encoder *encoder;
6893         struct amdgpu_encoder *amdgpu_encoder;
6894
6895         encoder = amdgpu_dm_connector_to_encoder(connector);
6896
6897         if (encoder == NULL)
6898                 return;
6899
6900         amdgpu_encoder = to_amdgpu_encoder(encoder);
6901
6902         amdgpu_encoder->native_mode.clock = 0;
6903
6904         if (!list_empty(&connector->probed_modes)) {
6905                 struct drm_display_mode *preferred_mode = NULL;
6906
6907                 list_for_each_entry(preferred_mode,
6908                                     &connector->probed_modes,
6909                                     head) {
6910                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6911                                 amdgpu_encoder->native_mode = *preferred_mode;
6912
6913                         break;
6914                 }
6915
6916         }
6917 }
6918
6919 static struct drm_display_mode *
6920 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6921                              char *name,
6922                              int hdisplay, int vdisplay)
6923 {
6924         struct drm_device *dev = encoder->dev;
6925         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6926         struct drm_display_mode *mode = NULL;
6927         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6928
6929         mode = drm_mode_duplicate(dev, native_mode);
6930
6931         if (mode == NULL)
6932                 return NULL;
6933
6934         mode->hdisplay = hdisplay;
6935         mode->vdisplay = vdisplay;
6936         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6937         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6938
6939         return mode;
6940
6941 }
6942
6943 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6944                                                  struct drm_connector *connector)
6945 {
6946         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6947         struct drm_display_mode *mode = NULL;
6948         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6949         struct amdgpu_dm_connector *amdgpu_dm_connector =
6950                                 to_amdgpu_dm_connector(connector);
6951         int i;
6952         int n;
6953         struct mode_size {
6954                 char name[DRM_DISPLAY_MODE_LEN];
6955                 int w;
6956                 int h;
6957         } common_modes[] = {
6958                 {  "640x480",  640,  480},
6959                 {  "800x600",  800,  600},
6960                 { "1024x768", 1024,  768},
6961                 { "1280x720", 1280,  720},
6962                 { "1280x800", 1280,  800},
6963                 {"1280x1024", 1280, 1024},
6964                 { "1440x900", 1440,  900},
6965                 {"1680x1050", 1680, 1050},
6966                 {"1600x1200", 1600, 1200},
6967                 {"1920x1080", 1920, 1080},
6968                 {"1920x1200", 1920, 1200}
6969         };
6970
6971         n = ARRAY_SIZE(common_modes);
6972
6973         for (i = 0; i < n; i++) {
6974                 struct drm_display_mode *curmode = NULL;
6975                 bool mode_existed = false;
6976
6977                 if (common_modes[i].w > native_mode->hdisplay ||
6978                     common_modes[i].h > native_mode->vdisplay ||
6979                    (common_modes[i].w == native_mode->hdisplay &&
6980                     common_modes[i].h == native_mode->vdisplay))
6981                         continue;
6982
6983                 list_for_each_entry(curmode, &connector->probed_modes, head) {
6984                         if (common_modes[i].w == curmode->hdisplay &&
6985                             common_modes[i].h == curmode->vdisplay) {
6986                                 mode_existed = true;
6987                                 break;
6988                         }
6989                 }
6990
6991                 if (mode_existed)
6992                         continue;
6993
6994                 mode = amdgpu_dm_create_common_mode(encoder,
6995                                 common_modes[i].name, common_modes[i].w,
6996                                 common_modes[i].h);
6997                 if (!mode)
6998                         continue;
6999
7000                 drm_mode_probed_add(connector, mode);
7001                 amdgpu_dm_connector->num_modes++;
7002         }
7003 }
7004
7005 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7006 {
7007         struct drm_encoder *encoder;
7008         struct amdgpu_encoder *amdgpu_encoder;
7009         const struct drm_display_mode *native_mode;
7010
7011         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7012             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7013                 return;
7014
7015         mutex_lock(&connector->dev->mode_config.mutex);
7016         amdgpu_dm_connector_get_modes(connector);
7017         mutex_unlock(&connector->dev->mode_config.mutex);
7018
7019         encoder = amdgpu_dm_connector_to_encoder(connector);
7020         if (!encoder)
7021                 return;
7022
7023         amdgpu_encoder = to_amdgpu_encoder(encoder);
7024
7025         native_mode = &amdgpu_encoder->native_mode;
7026         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7027                 return;
7028
7029         drm_connector_set_panel_orientation_with_quirk(connector,
7030                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7031                                                        native_mode->hdisplay,
7032                                                        native_mode->vdisplay);
7033 }
7034
7035 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7036                                               struct edid *edid)
7037 {
7038         struct amdgpu_dm_connector *amdgpu_dm_connector =
7039                         to_amdgpu_dm_connector(connector);
7040
7041         if (edid) {
7042                 /* empty probed_modes */
7043                 INIT_LIST_HEAD(&connector->probed_modes);
7044                 amdgpu_dm_connector->num_modes =
7045                                 drm_add_edid_modes(connector, edid);
7046
7047                 /* sorting the probed modes before calling function
7048                  * amdgpu_dm_get_native_mode() since EDID can have
7049                  * more than one preferred mode. The modes that are
7050                  * later in the probed mode list could be of higher
7051                  * and preferred resolution. For example, 3840x2160
7052                  * resolution in base EDID preferred timing and 4096x2160
7053                  * preferred resolution in DID extension block later.
7054                  */
7055                 drm_mode_sort(&connector->probed_modes);
7056                 amdgpu_dm_get_native_mode(connector);
7057
7058                 /* Freesync capabilities are reset by calling
7059                  * drm_add_edid_modes() and need to be
7060                  * restored here.
7061                  */
7062                 amdgpu_dm_update_freesync_caps(connector, edid);
7063         } else {
7064                 amdgpu_dm_connector->num_modes = 0;
7065         }
7066 }
7067
7068 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7069                               struct drm_display_mode *mode)
7070 {
7071         struct drm_display_mode *m;
7072
7073         list_for_each_entry (m, &aconnector->base.probed_modes, head) {
7074                 if (drm_mode_equal(m, mode))
7075                         return true;
7076         }
7077
7078         return false;
7079 }
7080
7081 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7082 {
7083         const struct drm_display_mode *m;
7084         struct drm_display_mode *new_mode;
7085         uint i;
7086         u32 new_modes_count = 0;
7087
7088         /* Standard FPS values
7089          *
7090          * 23.976       - TV/NTSC
7091          * 24           - Cinema
7092          * 25           - TV/PAL
7093          * 29.97        - TV/NTSC
7094          * 30           - TV/NTSC
7095          * 48           - Cinema HFR
7096          * 50           - TV/PAL
7097          * 60           - Commonly used
7098          * 48,72,96,120 - Multiples of 24
7099          */
7100         static const u32 common_rates[] = {
7101                 23976, 24000, 25000, 29970, 30000,
7102                 48000, 50000, 60000, 72000, 96000, 120000
7103         };
7104
7105         /*
7106          * Find mode with highest refresh rate with the same resolution
7107          * as the preferred mode. Some monitors report a preferred mode
7108          * with lower resolution than the highest refresh rate supported.
7109          */
7110
7111         m = get_highest_refresh_rate_mode(aconnector, true);
7112         if (!m)
7113                 return 0;
7114
7115         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7116                 u64 target_vtotal, target_vtotal_diff;
7117                 u64 num, den;
7118
7119                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7120                         continue;
7121
7122                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7123                     common_rates[i] > aconnector->max_vfreq * 1000)
7124                         continue;
7125
7126                 num = (unsigned long long)m->clock * 1000 * 1000;
7127                 den = common_rates[i] * (unsigned long long)m->htotal;
7128                 target_vtotal = div_u64(num, den);
7129                 target_vtotal_diff = target_vtotal - m->vtotal;
7130
7131                 /* Check for illegal modes */
7132                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7133                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7134                     m->vtotal + target_vtotal_diff < m->vsync_end)
7135                         continue;
7136
7137                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7138                 if (!new_mode)
7139                         goto out;
7140
7141                 new_mode->vtotal += (u16)target_vtotal_diff;
7142                 new_mode->vsync_start += (u16)target_vtotal_diff;
7143                 new_mode->vsync_end += (u16)target_vtotal_diff;
7144                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7145                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7146
7147                 if (!is_duplicate_mode(aconnector, new_mode)) {
7148                         drm_mode_probed_add(&aconnector->base, new_mode);
7149                         new_modes_count += 1;
7150                 } else
7151                         drm_mode_destroy(aconnector->base.dev, new_mode);
7152         }
7153  out:
7154         return new_modes_count;
7155 }
7156
7157 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7158                                                    struct edid *edid)
7159 {
7160         struct amdgpu_dm_connector *amdgpu_dm_connector =
7161                 to_amdgpu_dm_connector(connector);
7162
7163         if (!(amdgpu_freesync_vid_mode && edid))
7164                 return;
7165
7166         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7167                 amdgpu_dm_connector->num_modes +=
7168                         add_fs_modes(amdgpu_dm_connector);
7169 }
7170
7171 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7172 {
7173         struct amdgpu_dm_connector *amdgpu_dm_connector =
7174                         to_amdgpu_dm_connector(connector);
7175         struct drm_encoder *encoder;
7176         struct edid *edid = amdgpu_dm_connector->edid;
7177         struct dc_link_settings *verified_link_cap =
7178                         &amdgpu_dm_connector->dc_link->verified_link_cap;
7179         const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7180
7181         encoder = amdgpu_dm_connector_to_encoder(connector);
7182
7183         if (!drm_edid_is_valid(edid)) {
7184                 amdgpu_dm_connector->num_modes =
7185                                 drm_add_modes_noedid(connector, 640, 480);
7186                 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7187                         amdgpu_dm_connector->num_modes +=
7188                                 drm_add_modes_noedid(connector, 1920, 1080);
7189         } else {
7190                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7191                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7192                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7193         }
7194         amdgpu_dm_fbc_init(connector);
7195
7196         return amdgpu_dm_connector->num_modes;
7197 }
7198
7199 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7200                                      struct amdgpu_dm_connector *aconnector,
7201                                      int connector_type,
7202                                      struct dc_link *link,
7203                                      int link_index)
7204 {
7205         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7206
7207         /*
7208          * Some of the properties below require access to state, like bpc.
7209          * Allocate some default initial connector state with our reset helper.
7210          */
7211         if (aconnector->base.funcs->reset)
7212                 aconnector->base.funcs->reset(&aconnector->base);
7213
7214         aconnector->connector_id = link_index;
7215         aconnector->bl_idx = -1;
7216         aconnector->dc_link = link;
7217         aconnector->base.interlace_allowed = false;
7218         aconnector->base.doublescan_allowed = false;
7219         aconnector->base.stereo_allowed = false;
7220         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7221         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7222         aconnector->audio_inst = -1;
7223         aconnector->pack_sdp_v1_3 = false;
7224         aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7225         memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7226         mutex_init(&aconnector->hpd_lock);
7227
7228         /*
7229          * configure support HPD hot plug connector_>polled default value is 0
7230          * which means HPD hot plug not supported
7231          */
7232         switch (connector_type) {
7233         case DRM_MODE_CONNECTOR_HDMIA:
7234                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7235                 aconnector->base.ycbcr_420_allowed =
7236                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7237                 break;
7238         case DRM_MODE_CONNECTOR_DisplayPort:
7239                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7240                 link->link_enc = link_enc_cfg_get_link_enc(link);
7241                 ASSERT(link->link_enc);
7242                 if (link->link_enc)
7243                         aconnector->base.ycbcr_420_allowed =
7244                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7245                 break;
7246         case DRM_MODE_CONNECTOR_DVID:
7247                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7248                 break;
7249         default:
7250                 break;
7251         }
7252
7253         drm_object_attach_property(&aconnector->base.base,
7254                                 dm->ddev->mode_config.scaling_mode_property,
7255                                 DRM_MODE_SCALE_NONE);
7256
7257         drm_object_attach_property(&aconnector->base.base,
7258                                 adev->mode_info.underscan_property,
7259                                 UNDERSCAN_OFF);
7260         drm_object_attach_property(&aconnector->base.base,
7261                                 adev->mode_info.underscan_hborder_property,
7262                                 0);
7263         drm_object_attach_property(&aconnector->base.base,
7264                                 adev->mode_info.underscan_vborder_property,
7265                                 0);
7266
7267         if (!aconnector->mst_root)
7268                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7269
7270         aconnector->base.state->max_bpc = 16;
7271         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7272
7273         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7274             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7275                 drm_object_attach_property(&aconnector->base.base,
7276                                 adev->mode_info.abm_level_property, 0);
7277         }
7278
7279         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7280             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7281             connector_type == DRM_MODE_CONNECTOR_eDP) {
7282                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7283
7284                 if (!aconnector->mst_root)
7285                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7286
7287                 if (adev->dm.hdcp_workqueue)
7288                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7289         }
7290 }
7291
7292 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7293                               struct i2c_msg *msgs, int num)
7294 {
7295         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7296         struct ddc_service *ddc_service = i2c->ddc_service;
7297         struct i2c_command cmd;
7298         int i;
7299         int result = -EIO;
7300
7301         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7302
7303         if (!cmd.payloads)
7304                 return result;
7305
7306         cmd.number_of_payloads = num;
7307         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7308         cmd.speed = 100;
7309
7310         for (i = 0; i < num; i++) {
7311                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7312                 cmd.payloads[i].address = msgs[i].addr;
7313                 cmd.payloads[i].length = msgs[i].len;
7314                 cmd.payloads[i].data = msgs[i].buf;
7315         }
7316
7317         if (dc_submit_i2c(
7318                         ddc_service->ctx->dc,
7319                         ddc_service->link->link_index,
7320                         &cmd))
7321                 result = num;
7322
7323         kfree(cmd.payloads);
7324         return result;
7325 }
7326
7327 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7328 {
7329         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7330 }
7331
7332 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7333         .master_xfer = amdgpu_dm_i2c_xfer,
7334         .functionality = amdgpu_dm_i2c_func,
7335 };
7336
7337 static struct amdgpu_i2c_adapter *
7338 create_i2c(struct ddc_service *ddc_service,
7339            int link_index,
7340            int *res)
7341 {
7342         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7343         struct amdgpu_i2c_adapter *i2c;
7344
7345         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7346         if (!i2c)
7347                 return NULL;
7348         i2c->base.owner = THIS_MODULE;
7349         i2c->base.class = I2C_CLASS_DDC;
7350         i2c->base.dev.parent = &adev->pdev->dev;
7351         i2c->base.algo = &amdgpu_dm_i2c_algo;
7352         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7353         i2c_set_adapdata(&i2c->base, i2c);
7354         i2c->ddc_service = ddc_service;
7355
7356         return i2c;
7357 }
7358
7359
7360 /*
7361  * Note: this function assumes that dc_link_detect() was called for the
7362  * dc_link which will be represented by this aconnector.
7363  */
7364 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7365                                     struct amdgpu_dm_connector *aconnector,
7366                                     u32 link_index,
7367                                     struct amdgpu_encoder *aencoder)
7368 {
7369         int res = 0;
7370         int connector_type;
7371         struct dc *dc = dm->dc;
7372         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7373         struct amdgpu_i2c_adapter *i2c;
7374
7375         link->priv = aconnector;
7376
7377         DRM_DEBUG_DRIVER("%s()\n", __func__);
7378
7379         i2c = create_i2c(link->ddc, link->link_index, &res);
7380         if (!i2c) {
7381                 DRM_ERROR("Failed to create i2c adapter data\n");
7382                 return -ENOMEM;
7383         }
7384
7385         aconnector->i2c = i2c;
7386         res = i2c_add_adapter(&i2c->base);
7387
7388         if (res) {
7389                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7390                 goto out_free;
7391         }
7392
7393         connector_type = to_drm_connector_type(link->connector_signal);
7394
7395         res = drm_connector_init_with_ddc(
7396                         dm->ddev,
7397                         &aconnector->base,
7398                         &amdgpu_dm_connector_funcs,
7399                         connector_type,
7400                         &i2c->base);
7401
7402         if (res) {
7403                 DRM_ERROR("connector_init failed\n");
7404                 aconnector->connector_id = -1;
7405                 goto out_free;
7406         }
7407
7408         drm_connector_helper_add(
7409                         &aconnector->base,
7410                         &amdgpu_dm_connector_helper_funcs);
7411
7412         amdgpu_dm_connector_init_helper(
7413                 dm,
7414                 aconnector,
7415                 connector_type,
7416                 link,
7417                 link_index);
7418
7419         drm_connector_attach_encoder(
7420                 &aconnector->base, &aencoder->base);
7421
7422         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7423                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7424                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7425
7426 out_free:
7427         if (res) {
7428                 kfree(i2c);
7429                 aconnector->i2c = NULL;
7430         }
7431         return res;
7432 }
7433
7434 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7435 {
7436         switch (adev->mode_info.num_crtc) {
7437         case 1:
7438                 return 0x1;
7439         case 2:
7440                 return 0x3;
7441         case 3:
7442                 return 0x7;
7443         case 4:
7444                 return 0xf;
7445         case 5:
7446                 return 0x1f;
7447         case 6:
7448         default:
7449                 return 0x3f;
7450         }
7451 }
7452
7453 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7454                                   struct amdgpu_encoder *aencoder,
7455                                   uint32_t link_index)
7456 {
7457         struct amdgpu_device *adev = drm_to_adev(dev);
7458
7459         int res = drm_encoder_init(dev,
7460                                    &aencoder->base,
7461                                    &amdgpu_dm_encoder_funcs,
7462                                    DRM_MODE_ENCODER_TMDS,
7463                                    NULL);
7464
7465         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7466
7467         if (!res)
7468                 aencoder->encoder_id = link_index;
7469         else
7470                 aencoder->encoder_id = -1;
7471
7472         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7473
7474         return res;
7475 }
7476
7477 static void manage_dm_interrupts(struct amdgpu_device *adev,
7478                                  struct amdgpu_crtc *acrtc,
7479                                  bool enable)
7480 {
7481         /*
7482          * We have no guarantee that the frontend index maps to the same
7483          * backend index - some even map to more than one.
7484          *
7485          * TODO: Use a different interrupt or check DC itself for the mapping.
7486          */
7487         int irq_type =
7488                 amdgpu_display_crtc_idx_to_irq_type(
7489                         adev,
7490                         acrtc->crtc_id);
7491
7492         if (enable) {
7493                 drm_crtc_vblank_on(&acrtc->base);
7494                 amdgpu_irq_get(
7495                         adev,
7496                         &adev->pageflip_irq,
7497                         irq_type);
7498 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7499                 amdgpu_irq_get(
7500                         adev,
7501                         &adev->vline0_irq,
7502                         irq_type);
7503 #endif
7504         } else {
7505 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7506                 amdgpu_irq_put(
7507                         adev,
7508                         &adev->vline0_irq,
7509                         irq_type);
7510 #endif
7511                 amdgpu_irq_put(
7512                         adev,
7513                         &adev->pageflip_irq,
7514                         irq_type);
7515                 drm_crtc_vblank_off(&acrtc->base);
7516         }
7517 }
7518
7519 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7520                                       struct amdgpu_crtc *acrtc)
7521 {
7522         int irq_type =
7523                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7524
7525         /**
7526          * This reads the current state for the IRQ and force reapplies
7527          * the setting to hardware.
7528          */
7529         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7530 }
7531
7532 static bool
7533 is_scaling_state_different(const struct dm_connector_state *dm_state,
7534                            const struct dm_connector_state *old_dm_state)
7535 {
7536         if (dm_state->scaling != old_dm_state->scaling)
7537                 return true;
7538         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7539                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7540                         return true;
7541         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7542                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7543                         return true;
7544         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7545                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7546                 return true;
7547         return false;
7548 }
7549
7550 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7551                                             struct drm_crtc_state *old_crtc_state,
7552                                             struct drm_connector_state *new_conn_state,
7553                                             struct drm_connector_state *old_conn_state,
7554                                             const struct drm_connector *connector,
7555                                             struct hdcp_workqueue *hdcp_w)
7556 {
7557         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7558         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7559
7560         pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7561                 connector->index, connector->status, connector->dpms);
7562         pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7563                 old_conn_state->content_protection, new_conn_state->content_protection);
7564
7565         if (old_crtc_state)
7566                 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7567                 old_crtc_state->enable,
7568                 old_crtc_state->active,
7569                 old_crtc_state->mode_changed,
7570                 old_crtc_state->active_changed,
7571                 old_crtc_state->connectors_changed);
7572
7573         if (new_crtc_state)
7574                 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7575                 new_crtc_state->enable,
7576                 new_crtc_state->active,
7577                 new_crtc_state->mode_changed,
7578                 new_crtc_state->active_changed,
7579                 new_crtc_state->connectors_changed);
7580
7581         /* hdcp content type change */
7582         if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7583             new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7584                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7585                 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7586                 return true;
7587         }
7588
7589         /* CP is being re enabled, ignore this */
7590         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7591             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7592                 if (new_crtc_state && new_crtc_state->mode_changed) {
7593                         new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7594                         pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7595                         return true;
7596                 }
7597                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7598                 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7599                 return false;
7600         }
7601
7602         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7603          *
7604          * Handles:     UNDESIRED -> ENABLED
7605          */
7606         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7607             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7608                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7609
7610         /* Stream removed and re-enabled
7611          *
7612          * Can sometimes overlap with the HPD case,
7613          * thus set update_hdcp to false to avoid
7614          * setting HDCP multiple times.
7615          *
7616          * Handles:     DESIRED -> DESIRED (Special case)
7617          */
7618         if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7619                 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7620                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7621                 dm_con_state->update_hdcp = false;
7622                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7623                         __func__);
7624                 return true;
7625         }
7626
7627         /* Hot-plug, headless s3, dpms
7628          *
7629          * Only start HDCP if the display is connected/enabled.
7630          * update_hdcp flag will be set to false until the next
7631          * HPD comes in.
7632          *
7633          * Handles:     DESIRED -> DESIRED (Special case)
7634          */
7635         if (dm_con_state->update_hdcp &&
7636         new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7637         connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7638                 dm_con_state->update_hdcp = false;
7639                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7640                         __func__);
7641                 return true;
7642         }
7643
7644         if (old_conn_state->content_protection == new_conn_state->content_protection) {
7645                 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7646                         if (new_crtc_state && new_crtc_state->mode_changed) {
7647                                 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7648                                         __func__);
7649                                 return true;
7650                         }
7651                         pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7652                                 __func__);
7653                         return false;
7654                 }
7655
7656                 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7657                 return false;
7658         }
7659
7660         if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7661                 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7662                         __func__);
7663                 return true;
7664         }
7665
7666         pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7667         return false;
7668 }
7669
7670 static void remove_stream(struct amdgpu_device *adev,
7671                           struct amdgpu_crtc *acrtc,
7672                           struct dc_stream_state *stream)
7673 {
7674         /* this is the update mode case */
7675
7676         acrtc->otg_inst = -1;
7677         acrtc->enabled = false;
7678 }
7679
7680 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7681 {
7682
7683         assert_spin_locked(&acrtc->base.dev->event_lock);
7684         WARN_ON(acrtc->event);
7685
7686         acrtc->event = acrtc->base.state->event;
7687
7688         /* Set the flip status */
7689         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7690
7691         /* Mark this event as consumed */
7692         acrtc->base.state->event = NULL;
7693
7694         DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7695                      acrtc->crtc_id);
7696 }
7697
7698 static void update_freesync_state_on_stream(
7699         struct amdgpu_display_manager *dm,
7700         struct dm_crtc_state *new_crtc_state,
7701         struct dc_stream_state *new_stream,
7702         struct dc_plane_state *surface,
7703         u32 flip_timestamp_in_us)
7704 {
7705         struct mod_vrr_params vrr_params;
7706         struct dc_info_packet vrr_infopacket = {0};
7707         struct amdgpu_device *adev = dm->adev;
7708         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7709         unsigned long flags;
7710         bool pack_sdp_v1_3 = false;
7711         struct amdgpu_dm_connector *aconn;
7712         enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7713
7714         if (!new_stream)
7715                 return;
7716
7717         /*
7718          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7719          * For now it's sufficient to just guard against these conditions.
7720          */
7721
7722         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7723                 return;
7724
7725         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7726         vrr_params = acrtc->dm_irq_params.vrr_params;
7727
7728         if (surface) {
7729                 mod_freesync_handle_preflip(
7730                         dm->freesync_module,
7731                         surface,
7732                         new_stream,
7733                         flip_timestamp_in_us,
7734                         &vrr_params);
7735
7736                 if (adev->family < AMDGPU_FAMILY_AI &&
7737                     amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7738                         mod_freesync_handle_v_update(dm->freesync_module,
7739                                                      new_stream, &vrr_params);
7740
7741                         /* Need to call this before the frame ends. */
7742                         dc_stream_adjust_vmin_vmax(dm->dc,
7743                                                    new_crtc_state->stream,
7744                                                    &vrr_params.adjust);
7745                 }
7746         }
7747
7748         aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7749
7750         if (aconn && aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
7751                 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7752
7753                 if (aconn->vsdb_info.amd_vsdb_version == 1)
7754                         packet_type = PACKET_TYPE_FS_V1;
7755                 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7756                         packet_type = PACKET_TYPE_FS_V2;
7757                 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7758                         packet_type = PACKET_TYPE_FS_V3;
7759
7760                 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7761                                         &new_stream->adaptive_sync_infopacket);
7762         }
7763
7764         mod_freesync_build_vrr_infopacket(
7765                 dm->freesync_module,
7766                 new_stream,
7767                 &vrr_params,
7768                 packet_type,
7769                 TRANSFER_FUNC_UNKNOWN,
7770                 &vrr_infopacket,
7771                 pack_sdp_v1_3);
7772
7773         new_crtc_state->freesync_vrr_info_changed |=
7774                 (memcmp(&new_crtc_state->vrr_infopacket,
7775                         &vrr_infopacket,
7776                         sizeof(vrr_infopacket)) != 0);
7777
7778         acrtc->dm_irq_params.vrr_params = vrr_params;
7779         new_crtc_state->vrr_infopacket = vrr_infopacket;
7780
7781         new_stream->vrr_infopacket = vrr_infopacket;
7782         new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7783
7784         if (new_crtc_state->freesync_vrr_info_changed)
7785                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7786                               new_crtc_state->base.crtc->base.id,
7787                               (int)new_crtc_state->base.vrr_enabled,
7788                               (int)vrr_params.state);
7789
7790         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7791 }
7792
7793 static void update_stream_irq_parameters(
7794         struct amdgpu_display_manager *dm,
7795         struct dm_crtc_state *new_crtc_state)
7796 {
7797         struct dc_stream_state *new_stream = new_crtc_state->stream;
7798         struct mod_vrr_params vrr_params;
7799         struct mod_freesync_config config = new_crtc_state->freesync_config;
7800         struct amdgpu_device *adev = dm->adev;
7801         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7802         unsigned long flags;
7803
7804         if (!new_stream)
7805                 return;
7806
7807         /*
7808          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7809          * For now it's sufficient to just guard against these conditions.
7810          */
7811         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7812                 return;
7813
7814         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7815         vrr_params = acrtc->dm_irq_params.vrr_params;
7816
7817         if (new_crtc_state->vrr_supported &&
7818             config.min_refresh_in_uhz &&
7819             config.max_refresh_in_uhz) {
7820                 /*
7821                  * if freesync compatible mode was set, config.state will be set
7822                  * in atomic check
7823                  */
7824                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7825                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7826                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7827                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7828                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7829                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7830                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7831                 } else {
7832                         config.state = new_crtc_state->base.vrr_enabled ?
7833                                                      VRR_STATE_ACTIVE_VARIABLE :
7834                                                      VRR_STATE_INACTIVE;
7835                 }
7836         } else {
7837                 config.state = VRR_STATE_UNSUPPORTED;
7838         }
7839
7840         mod_freesync_build_vrr_params(dm->freesync_module,
7841                                       new_stream,
7842                                       &config, &vrr_params);
7843
7844         new_crtc_state->freesync_config = config;
7845         /* Copy state for access from DM IRQ handler */
7846         acrtc->dm_irq_params.freesync_config = config;
7847         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7848         acrtc->dm_irq_params.vrr_params = vrr_params;
7849         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7850 }
7851
7852 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7853                                             struct dm_crtc_state *new_state)
7854 {
7855         bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
7856         bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
7857
7858         if (!old_vrr_active && new_vrr_active) {
7859                 /* Transition VRR inactive -> active:
7860                  * While VRR is active, we must not disable vblank irq, as a
7861                  * reenable after disable would compute bogus vblank/pflip
7862                  * timestamps if it likely happened inside display front-porch.
7863                  *
7864                  * We also need vupdate irq for the actual core vblank handling
7865                  * at end of vblank.
7866                  */
7867                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
7868                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
7869                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7870                                  __func__, new_state->base.crtc->base.id);
7871         } else if (old_vrr_active && !new_vrr_active) {
7872                 /* Transition VRR active -> inactive:
7873                  * Allow vblank irq disable again for fixed refresh rate.
7874                  */
7875                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
7876                 drm_crtc_vblank_put(new_state->base.crtc);
7877                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7878                                  __func__, new_state->base.crtc->base.id);
7879         }
7880 }
7881
7882 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7883 {
7884         struct drm_plane *plane;
7885         struct drm_plane_state *old_plane_state;
7886         int i;
7887
7888         /*
7889          * TODO: Make this per-stream so we don't issue redundant updates for
7890          * commits with multiple streams.
7891          */
7892         for_each_old_plane_in_state(state, plane, old_plane_state, i)
7893                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7894                         amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
7895 }
7896
7897 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7898                                     struct dc_state *dc_state,
7899                                     struct drm_device *dev,
7900                                     struct amdgpu_display_manager *dm,
7901                                     struct drm_crtc *pcrtc,
7902                                     bool wait_for_vblank)
7903 {
7904         u32 i;
7905         u64 timestamp_ns = ktime_get_ns();
7906         struct drm_plane *plane;
7907         struct drm_plane_state *old_plane_state, *new_plane_state;
7908         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
7909         struct drm_crtc_state *new_pcrtc_state =
7910                         drm_atomic_get_new_crtc_state(state, pcrtc);
7911         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
7912         struct dm_crtc_state *dm_old_crtc_state =
7913                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
7914         int planes_count = 0, vpos, hpos;
7915         unsigned long flags;
7916         u32 target_vblank, last_flip_vblank;
7917         bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
7918         bool cursor_update = false;
7919         bool pflip_present = false;
7920         bool dirty_rects_changed = false;
7921         struct {
7922                 struct dc_surface_update surface_updates[MAX_SURFACES];
7923                 struct dc_plane_info plane_infos[MAX_SURFACES];
7924                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
7925                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7926                 struct dc_stream_update stream_update;
7927         } *bundle;
7928
7929         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7930
7931         if (!bundle) {
7932                 dm_error("Failed to allocate update bundle\n");
7933                 goto cleanup;
7934         }
7935
7936         /*
7937          * Disable the cursor first if we're disabling all the planes.
7938          * It'll remain on the screen after the planes are re-enabled
7939          * if we don't.
7940          */
7941         if (acrtc_state->active_planes == 0)
7942                 amdgpu_dm_commit_cursors(state);
7943
7944         /* update planes when needed */
7945         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7946                 struct drm_crtc *crtc = new_plane_state->crtc;
7947                 struct drm_crtc_state *new_crtc_state;
7948                 struct drm_framebuffer *fb = new_plane_state->fb;
7949                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
7950                 bool plane_needs_flip;
7951                 struct dc_plane_state *dc_plane;
7952                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
7953
7954                 /* Cursor plane is handled after stream updates */
7955                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
7956                         if ((fb && crtc == pcrtc) ||
7957                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
7958                                 cursor_update = true;
7959
7960                         continue;
7961                 }
7962
7963                 if (!fb || !crtc || pcrtc != crtc)
7964                         continue;
7965
7966                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
7967                 if (!new_crtc_state->active)
7968                         continue;
7969
7970                 dc_plane = dm_new_plane_state->dc_state;
7971
7972                 bundle->surface_updates[planes_count].surface = dc_plane;
7973                 if (new_pcrtc_state->color_mgmt_changed) {
7974                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
7975                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
7976                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
7977                 }
7978
7979                 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
7980                                      &bundle->scaling_infos[planes_count]);
7981
7982                 bundle->surface_updates[planes_count].scaling_info =
7983                         &bundle->scaling_infos[planes_count];
7984
7985                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
7986
7987                 pflip_present = pflip_present || plane_needs_flip;
7988
7989                 if (!plane_needs_flip) {
7990                         planes_count += 1;
7991                         continue;
7992                 }
7993
7994                 fill_dc_plane_info_and_addr(
7995                         dm->adev, new_plane_state,
7996                         afb->tiling_flags,
7997                         &bundle->plane_infos[planes_count],
7998                         &bundle->flip_addrs[planes_count].address,
7999                         afb->tmz_surface, false);
8000
8001                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8002                                  new_plane_state->plane->index,
8003                                  bundle->plane_infos[planes_count].dcc.enable);
8004
8005                 bundle->surface_updates[planes_count].plane_info =
8006                         &bundle->plane_infos[planes_count];
8007
8008                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8009                         fill_dc_dirty_rects(plane, old_plane_state,
8010                                             new_plane_state, new_crtc_state,
8011                                             &bundle->flip_addrs[planes_count],
8012                                             &dirty_rects_changed);
8013
8014                         /*
8015                          * If the dirty regions changed, PSR-SU need to be disabled temporarily
8016                          * and enabled it again after dirty regions are stable to avoid video glitch.
8017                          * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8018                          * during the PSR-SU was disabled.
8019                          */
8020                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8021                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8022 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8023                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8024 #endif
8025                             dirty_rects_changed) {
8026                                 mutex_lock(&dm->dc_lock);
8027                                 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8028                                 timestamp_ns;
8029                                 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8030                                         amdgpu_dm_psr_disable(acrtc_state->stream);
8031                                 mutex_unlock(&dm->dc_lock);
8032                         }
8033                 }
8034
8035                 /*
8036                  * Only allow immediate flips for fast updates that don't
8037                  * change FB pitch, DCC state, rotation or mirroing.
8038                  */
8039                 bundle->flip_addrs[planes_count].flip_immediate =
8040                         crtc->state->async_flip &&
8041                         acrtc_state->update_type == UPDATE_TYPE_FAST;
8042
8043                 timestamp_ns = ktime_get_ns();
8044                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8045                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8046                 bundle->surface_updates[planes_count].surface = dc_plane;
8047
8048                 if (!bundle->surface_updates[planes_count].surface) {
8049                         DRM_ERROR("No surface for CRTC: id=%d\n",
8050                                         acrtc_attach->crtc_id);
8051                         continue;
8052                 }
8053
8054                 if (plane == pcrtc->primary)
8055                         update_freesync_state_on_stream(
8056                                 dm,
8057                                 acrtc_state,
8058                                 acrtc_state->stream,
8059                                 dc_plane,
8060                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8061
8062                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8063                                  __func__,
8064                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8065                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8066
8067                 planes_count += 1;
8068
8069         }
8070
8071         if (pflip_present) {
8072                 if (!vrr_active) {
8073                         /* Use old throttling in non-vrr fixed refresh rate mode
8074                          * to keep flip scheduling based on target vblank counts
8075                          * working in a backwards compatible way, e.g., for
8076                          * clients using the GLX_OML_sync_control extension or
8077                          * DRI3/Present extension with defined target_msc.
8078                          */
8079                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8080                 }
8081                 else {
8082                         /* For variable refresh rate mode only:
8083                          * Get vblank of last completed flip to avoid > 1 vrr
8084                          * flips per video frame by use of throttling, but allow
8085                          * flip programming anywhere in the possibly large
8086                          * variable vrr vblank interval for fine-grained flip
8087                          * timing control and more opportunity to avoid stutter
8088                          * on late submission of flips.
8089                          */
8090                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8091                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8092                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8093                 }
8094
8095                 target_vblank = last_flip_vblank + wait_for_vblank;
8096
8097                 /*
8098                  * Wait until we're out of the vertical blank period before the one
8099                  * targeted by the flip
8100                  */
8101                 while ((acrtc_attach->enabled &&
8102                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8103                                                             0, &vpos, &hpos, NULL,
8104                                                             NULL, &pcrtc->hwmode)
8105                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8106                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8107                         (int)(target_vblank -
8108                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8109                         usleep_range(1000, 1100);
8110                 }
8111
8112                 /**
8113                  * Prepare the flip event for the pageflip interrupt to handle.
8114                  *
8115                  * This only works in the case where we've already turned on the
8116                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8117                  * from 0 -> n planes we have to skip a hardware generated event
8118                  * and rely on sending it from software.
8119                  */
8120                 if (acrtc_attach->base.state->event &&
8121                     acrtc_state->active_planes > 0) {
8122                         drm_crtc_vblank_get(pcrtc);
8123
8124                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8125
8126                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8127                         prepare_flip_isr(acrtc_attach);
8128
8129                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8130                 }
8131
8132                 if (acrtc_state->stream) {
8133                         if (acrtc_state->freesync_vrr_info_changed)
8134                                 bundle->stream_update.vrr_infopacket =
8135                                         &acrtc_state->stream->vrr_infopacket;
8136                 }
8137         } else if (cursor_update && acrtc_state->active_planes > 0 &&
8138                    acrtc_attach->base.state->event) {
8139                 drm_crtc_vblank_get(pcrtc);
8140
8141                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8142
8143                 acrtc_attach->event = acrtc_attach->base.state->event;
8144                 acrtc_attach->base.state->event = NULL;
8145
8146                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8147         }
8148
8149         /* Update the planes if changed or disable if we don't have any. */
8150         if ((planes_count || acrtc_state->active_planes == 0) &&
8151                 acrtc_state->stream) {
8152                 /*
8153                  * If PSR or idle optimizations are enabled then flush out
8154                  * any pending work before hardware programming.
8155                  */
8156                 if (dm->vblank_control_workqueue)
8157                         flush_workqueue(dm->vblank_control_workqueue);
8158
8159                 bundle->stream_update.stream = acrtc_state->stream;
8160                 if (new_pcrtc_state->mode_changed) {
8161                         bundle->stream_update.src = acrtc_state->stream->src;
8162                         bundle->stream_update.dst = acrtc_state->stream->dst;
8163                 }
8164
8165                 if (new_pcrtc_state->color_mgmt_changed) {
8166                         /*
8167                          * TODO: This isn't fully correct since we've actually
8168                          * already modified the stream in place.
8169                          */
8170                         bundle->stream_update.gamut_remap =
8171                                 &acrtc_state->stream->gamut_remap_matrix;
8172                         bundle->stream_update.output_csc_transform =
8173                                 &acrtc_state->stream->csc_color_matrix;
8174                         bundle->stream_update.out_transfer_func =
8175                                 acrtc_state->stream->out_transfer_func;
8176                 }
8177
8178                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8179                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8180                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8181
8182                 /*
8183                  * If FreeSync state on the stream has changed then we need to
8184                  * re-adjust the min/max bounds now that DC doesn't handle this
8185                  * as part of commit.
8186                  */
8187                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8188                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8189                         dc_stream_adjust_vmin_vmax(
8190                                 dm->dc, acrtc_state->stream,
8191                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8192                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8193                 }
8194                 mutex_lock(&dm->dc_lock);
8195                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8196                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8197                         amdgpu_dm_psr_disable(acrtc_state->stream);
8198
8199                 update_planes_and_stream_adapter(dm->dc,
8200                                          acrtc_state->update_type,
8201                                          planes_count,
8202                                          acrtc_state->stream,
8203                                          &bundle->stream_update,
8204                                          bundle->surface_updates);
8205
8206                 /**
8207                  * Enable or disable the interrupts on the backend.
8208                  *
8209                  * Most pipes are put into power gating when unused.
8210                  *
8211                  * When power gating is enabled on a pipe we lose the
8212                  * interrupt enablement state when power gating is disabled.
8213                  *
8214                  * So we need to update the IRQ control state in hardware
8215                  * whenever the pipe turns on (since it could be previously
8216                  * power gated) or off (since some pipes can't be power gated
8217                  * on some ASICs).
8218                  */
8219                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8220                         dm_update_pflip_irq_state(drm_to_adev(dev),
8221                                                   acrtc_attach);
8222
8223                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8224                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8225                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8226                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8227
8228                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8229                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8230                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8231                         struct amdgpu_dm_connector *aconn =
8232                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8233
8234                         if (aconn->psr_skip_count > 0)
8235                                 aconn->psr_skip_count--;
8236
8237                         /* Allow PSR when skip count is 0. */
8238                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8239
8240                         /*
8241                          * If sink supports PSR SU, there is no need to rely on
8242                          * a vblank event disable request to enable PSR. PSR SU
8243                          * can be enabled immediately once OS demonstrates an
8244                          * adequate number of fast atomic commits to notify KMD
8245                          * of update events. See `vblank_control_worker()`.
8246                          */
8247                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8248                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8249 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8250                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8251 #endif
8252                             !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8253                             (timestamp_ns -
8254                             acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8255                             500000000)
8256                                 amdgpu_dm_psr_enable(acrtc_state->stream);
8257                 } else {
8258                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
8259                 }
8260
8261                 mutex_unlock(&dm->dc_lock);
8262         }
8263
8264         /*
8265          * Update cursor state *after* programming all the planes.
8266          * This avoids redundant programming in the case where we're going
8267          * to be disabling a single plane - those pipes are being disabled.
8268          */
8269         if (acrtc_state->active_planes)
8270                 amdgpu_dm_commit_cursors(state);
8271
8272 cleanup:
8273         kfree(bundle);
8274 }
8275
8276 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8277                                    struct drm_atomic_state *state)
8278 {
8279         struct amdgpu_device *adev = drm_to_adev(dev);
8280         struct amdgpu_dm_connector *aconnector;
8281         struct drm_connector *connector;
8282         struct drm_connector_state *old_con_state, *new_con_state;
8283         struct drm_crtc_state *new_crtc_state;
8284         struct dm_crtc_state *new_dm_crtc_state;
8285         const struct dc_stream_status *status;
8286         int i, inst;
8287
8288         /* Notify device removals. */
8289         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8290                 if (old_con_state->crtc != new_con_state->crtc) {
8291                         /* CRTC changes require notification. */
8292                         goto notify;
8293                 }
8294
8295                 if (!new_con_state->crtc)
8296                         continue;
8297
8298                 new_crtc_state = drm_atomic_get_new_crtc_state(
8299                         state, new_con_state->crtc);
8300
8301                 if (!new_crtc_state)
8302                         continue;
8303
8304                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8305                         continue;
8306
8307 notify:
8308                 aconnector = to_amdgpu_dm_connector(connector);
8309
8310                 mutex_lock(&adev->dm.audio_lock);
8311                 inst = aconnector->audio_inst;
8312                 aconnector->audio_inst = -1;
8313                 mutex_unlock(&adev->dm.audio_lock);
8314
8315                 amdgpu_dm_audio_eld_notify(adev, inst);
8316         }
8317
8318         /* Notify audio device additions. */
8319         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8320                 if (!new_con_state->crtc)
8321                         continue;
8322
8323                 new_crtc_state = drm_atomic_get_new_crtc_state(
8324                         state, new_con_state->crtc);
8325
8326                 if (!new_crtc_state)
8327                         continue;
8328
8329                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8330                         continue;
8331
8332                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8333                 if (!new_dm_crtc_state->stream)
8334                         continue;
8335
8336                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8337                 if (!status)
8338                         continue;
8339
8340                 aconnector = to_amdgpu_dm_connector(connector);
8341
8342                 mutex_lock(&adev->dm.audio_lock);
8343                 inst = status->audio_inst;
8344                 aconnector->audio_inst = inst;
8345                 mutex_unlock(&adev->dm.audio_lock);
8346
8347                 amdgpu_dm_audio_eld_notify(adev, inst);
8348         }
8349 }
8350
8351 /*
8352  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8353  * @crtc_state: the DRM CRTC state
8354  * @stream_state: the DC stream state.
8355  *
8356  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8357  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8358  */
8359 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8360                                                 struct dc_stream_state *stream_state)
8361 {
8362         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8363 }
8364
8365 /**
8366  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8367  * @state: The atomic state to commit
8368  *
8369  * This will tell DC to commit the constructed DC state from atomic_check,
8370  * programming the hardware. Any failures here implies a hardware failure, since
8371  * atomic check should have filtered anything non-kosher.
8372  */
8373 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8374 {
8375         struct drm_device *dev = state->dev;
8376         struct amdgpu_device *adev = drm_to_adev(dev);
8377         struct amdgpu_display_manager *dm = &adev->dm;
8378         struct dm_atomic_state *dm_state;
8379         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8380         u32 i, j;
8381         struct drm_crtc *crtc;
8382         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8383         unsigned long flags;
8384         bool wait_for_vblank = true;
8385         struct drm_connector *connector;
8386         struct drm_connector_state *old_con_state, *new_con_state;
8387         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8388         int crtc_disable_count = 0;
8389         bool mode_set_reset_required = false;
8390         int r;
8391
8392         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8393
8394         r = drm_atomic_helper_wait_for_fences(dev, state, false);
8395         if (unlikely(r))
8396                 DRM_ERROR("Waiting for fences timed out!");
8397
8398         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8399         drm_dp_mst_atomic_wait_for_dependencies(state);
8400
8401         dm_state = dm_atomic_get_new_state(state);
8402         if (dm_state && dm_state->context) {
8403                 dc_state = dm_state->context;
8404         } else {
8405                 /* No state changes, retain current state. */
8406                 dc_state_temp = dc_create_state(dm->dc);
8407                 ASSERT(dc_state_temp);
8408                 dc_state = dc_state_temp;
8409                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8410         }
8411
8412         for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8413                                        new_crtc_state, i) {
8414                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8415
8416                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8417
8418                 if (old_crtc_state->active &&
8419                     (!new_crtc_state->active ||
8420                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8421                         manage_dm_interrupts(adev, acrtc, false);
8422                         dc_stream_release(dm_old_crtc_state->stream);
8423                 }
8424         }
8425
8426         drm_atomic_helper_calc_timestamping_constants(state);
8427
8428         /* update changed items */
8429         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8430                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8431
8432                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8433                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8434
8435                 drm_dbg_state(state->dev,
8436                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8437                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8438                         "connectors_changed:%d\n",
8439                         acrtc->crtc_id,
8440                         new_crtc_state->enable,
8441                         new_crtc_state->active,
8442                         new_crtc_state->planes_changed,
8443                         new_crtc_state->mode_changed,
8444                         new_crtc_state->active_changed,
8445                         new_crtc_state->connectors_changed);
8446
8447                 /* Disable cursor if disabling crtc */
8448                 if (old_crtc_state->active && !new_crtc_state->active) {
8449                         struct dc_cursor_position position;
8450
8451                         memset(&position, 0, sizeof(position));
8452                         mutex_lock(&dm->dc_lock);
8453                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8454                         mutex_unlock(&dm->dc_lock);
8455                 }
8456
8457                 /* Copy all transient state flags into dc state */
8458                 if (dm_new_crtc_state->stream) {
8459                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8460                                                             dm_new_crtc_state->stream);
8461                 }
8462
8463                 /* handles headless hotplug case, updating new_state and
8464                  * aconnector as needed
8465                  */
8466
8467                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8468
8469                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8470
8471                         if (!dm_new_crtc_state->stream) {
8472                                 /*
8473                                  * this could happen because of issues with
8474                                  * userspace notifications delivery.
8475                                  * In this case userspace tries to set mode on
8476                                  * display which is disconnected in fact.
8477                                  * dc_sink is NULL in this case on aconnector.
8478                                  * We expect reset mode will come soon.
8479                                  *
8480                                  * This can also happen when unplug is done
8481                                  * during resume sequence ended
8482                                  *
8483                                  * In this case, we want to pretend we still
8484                                  * have a sink to keep the pipe running so that
8485                                  * hw state is consistent with the sw state
8486                                  */
8487                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8488                                                 __func__, acrtc->base.base.id);
8489                                 continue;
8490                         }
8491
8492                         if (dm_old_crtc_state->stream)
8493                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8494
8495                         pm_runtime_get_noresume(dev->dev);
8496
8497                         acrtc->enabled = true;
8498                         acrtc->hw_mode = new_crtc_state->mode;
8499                         crtc->hwmode = new_crtc_state->mode;
8500                         mode_set_reset_required = true;
8501                 } else if (modereset_required(new_crtc_state)) {
8502                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8503                         /* i.e. reset mode */
8504                         if (dm_old_crtc_state->stream)
8505                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8506
8507                         mode_set_reset_required = true;
8508                 }
8509         } /* for_each_crtc_in_state() */
8510
8511         if (dc_state) {
8512                 /* if there mode set or reset, disable eDP PSR */
8513                 if (mode_set_reset_required) {
8514                         if (dm->vblank_control_workqueue)
8515                                 flush_workqueue(dm->vblank_control_workqueue);
8516
8517                         amdgpu_dm_psr_disable_all(dm);
8518                 }
8519
8520                 dm_enable_per_frame_crtc_master_sync(dc_state);
8521                 mutex_lock(&dm->dc_lock);
8522                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8523
8524                 /* Allow idle optimization when vblank count is 0 for display off */
8525                 if (dm->active_vblank_irq_count == 0)
8526                         dc_allow_idle_optimizations(dm->dc, true);
8527                 mutex_unlock(&dm->dc_lock);
8528         }
8529
8530         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8531                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8532
8533                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8534
8535                 if (dm_new_crtc_state->stream != NULL) {
8536                         const struct dc_stream_status *status =
8537                                         dc_stream_get_status(dm_new_crtc_state->stream);
8538
8539                         if (!status)
8540                                 status = dc_stream_get_status_from_state(dc_state,
8541                                                                          dm_new_crtc_state->stream);
8542                         if (!status)
8543                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8544                         else
8545                                 acrtc->otg_inst = status->primary_otg_inst;
8546                 }
8547         }
8548         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8549                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8550                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8551                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8552
8553                 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8554
8555                 if (!connector)
8556                         continue;
8557
8558                 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8559                         connector->index, connector->status, connector->dpms);
8560                 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8561                         old_con_state->content_protection, new_con_state->content_protection);
8562
8563                 if (aconnector->dc_sink) {
8564                         if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8565                                 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8566                                 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8567                                 aconnector->dc_sink->edid_caps.display_name);
8568                         }
8569                 }
8570
8571                 new_crtc_state = NULL;
8572                 old_crtc_state = NULL;
8573
8574                 if (acrtc) {
8575                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8576                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8577                 }
8578
8579                 if (old_crtc_state)
8580                         pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8581                         old_crtc_state->enable,
8582                         old_crtc_state->active,
8583                         old_crtc_state->mode_changed,
8584                         old_crtc_state->active_changed,
8585                         old_crtc_state->connectors_changed);
8586
8587                 if (new_crtc_state)
8588                         pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8589                         new_crtc_state->enable,
8590                         new_crtc_state->active,
8591                         new_crtc_state->mode_changed,
8592                         new_crtc_state->active_changed,
8593                         new_crtc_state->connectors_changed);
8594         }
8595
8596         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8597                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8598                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8599                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8600
8601                 new_crtc_state = NULL;
8602                 old_crtc_state = NULL;
8603
8604                 if (acrtc) {
8605                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8606                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8607                 }
8608
8609                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8610
8611                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8612                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8613                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8614                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8615                         dm_new_con_state->update_hdcp = true;
8616                         continue;
8617                 }
8618
8619                 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8620                                                                                         old_con_state, connector, adev->dm.hdcp_workqueue)) {
8621                         /* when display is unplugged from mst hub, connctor will
8622                          * be destroyed within dm_dp_mst_connector_destroy. connector
8623                          * hdcp perperties, like type, undesired, desired, enabled,
8624                          * will be lost. So, save hdcp properties into hdcp_work within
8625                          * amdgpu_dm_atomic_commit_tail. if the same display is
8626                          * plugged back with same display index, its hdcp properties
8627                          * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8628                          */
8629
8630                         bool enable_encryption = false;
8631
8632                         if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8633                                 enable_encryption = true;
8634
8635                         if (aconnector->dc_link && aconnector->dc_sink &&
8636                                 aconnector->dc_link->type == dc_connection_mst_branch) {
8637                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8638                                 struct hdcp_workqueue *hdcp_w =
8639                                         &hdcp_work[aconnector->dc_link->link_index];
8640
8641                                 hdcp_w->hdcp_content_type[connector->index] =
8642                                         new_con_state->hdcp_content_type;
8643                                 hdcp_w->content_protection[connector->index] =
8644                                         new_con_state->content_protection;
8645                         }
8646
8647                         if (new_crtc_state && new_crtc_state->mode_changed &&
8648                                 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8649                                 enable_encryption = true;
8650
8651                         DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8652
8653                         hdcp_update_display(
8654                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8655                                 new_con_state->hdcp_content_type, enable_encryption);
8656                 }
8657         }
8658
8659         /* Handle connector state changes */
8660         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8661                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8662                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8663                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8664                 struct dc_surface_update dummy_updates[MAX_SURFACES];
8665                 struct dc_stream_update stream_update;
8666                 struct dc_info_packet hdr_packet;
8667                 struct dc_stream_status *status = NULL;
8668                 bool abm_changed, hdr_changed, scaling_changed;
8669
8670                 memset(&dummy_updates, 0, sizeof(dummy_updates));
8671                 memset(&stream_update, 0, sizeof(stream_update));
8672
8673                 if (acrtc) {
8674                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8675                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8676                 }
8677
8678                 /* Skip any modesets/resets */
8679                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8680                         continue;
8681
8682                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8683                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8684
8685                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8686                                                              dm_old_con_state);
8687
8688                 abm_changed = dm_new_crtc_state->abm_level !=
8689                               dm_old_crtc_state->abm_level;
8690
8691                 hdr_changed =
8692                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8693
8694                 if (!scaling_changed && !abm_changed && !hdr_changed)
8695                         continue;
8696
8697                 stream_update.stream = dm_new_crtc_state->stream;
8698                 if (scaling_changed) {
8699                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8700                                         dm_new_con_state, dm_new_crtc_state->stream);
8701
8702                         stream_update.src = dm_new_crtc_state->stream->src;
8703                         stream_update.dst = dm_new_crtc_state->stream->dst;
8704                 }
8705
8706                 if (abm_changed) {
8707                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8708
8709                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8710                 }
8711
8712                 if (hdr_changed) {
8713                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8714                         stream_update.hdr_static_metadata = &hdr_packet;
8715                 }
8716
8717                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8718
8719                 if (WARN_ON(!status))
8720                         continue;
8721
8722                 WARN_ON(!status->plane_count);
8723
8724                 /*
8725                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8726                  * Here we create an empty update on each plane.
8727                  * To fix this, DC should permit updating only stream properties.
8728                  */
8729                 for (j = 0; j < status->plane_count; j++)
8730                         dummy_updates[j].surface = status->plane_states[0];
8731
8732
8733                 mutex_lock(&dm->dc_lock);
8734                 dc_update_planes_and_stream(dm->dc,
8735                                             dummy_updates,
8736                                             status->plane_count,
8737                                             dm_new_crtc_state->stream,
8738                                             &stream_update);
8739                 mutex_unlock(&dm->dc_lock);
8740         }
8741
8742         /**
8743          * Enable interrupts for CRTCs that are newly enabled or went through
8744          * a modeset. It was intentionally deferred until after the front end
8745          * state was modified to wait until the OTG was on and so the IRQ
8746          * handlers didn't access stale or invalid state.
8747          */
8748         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8749                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8750 #ifdef CONFIG_DEBUG_FS
8751                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8752 #endif
8753                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8754                 if (old_crtc_state->active && !new_crtc_state->active)
8755                         crtc_disable_count++;
8756
8757                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8758                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8759
8760                 /* For freesync config update on crtc state and params for irq */
8761                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8762
8763 #ifdef CONFIG_DEBUG_FS
8764                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8765                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8766                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8767 #endif
8768
8769                 if (new_crtc_state->active &&
8770                     (!old_crtc_state->active ||
8771                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8772                         dc_stream_retain(dm_new_crtc_state->stream);
8773                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8774                         manage_dm_interrupts(adev, acrtc, true);
8775                 }
8776                 /* Handle vrr on->off / off->on transitions */
8777                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8778
8779 #ifdef CONFIG_DEBUG_FS
8780                 if (new_crtc_state->active &&
8781                     (!old_crtc_state->active ||
8782                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8783                         /**
8784                          * Frontend may have changed so reapply the CRC capture
8785                          * settings for the stream.
8786                          */
8787                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8788 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8789                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8790                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8791                                         acrtc->dm_irq_params.window_param.update_win = true;
8792
8793                                         /**
8794                                          * It takes 2 frames for HW to stably generate CRC when
8795                                          * resuming from suspend, so we set skip_frame_cnt 2.
8796                                          */
8797                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8798                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8799                                 }
8800 #endif
8801                                 if (amdgpu_dm_crtc_configure_crc_source(
8802                                         crtc, dm_new_crtc_state, cur_crc_src))
8803                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
8804                         }
8805                 }
8806 #endif
8807         }
8808
8809         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8810                 if (new_crtc_state->async_flip)
8811                         wait_for_vblank = false;
8812
8813         /* update planes when needed per crtc*/
8814         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8815                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8816
8817                 if (dm_new_crtc_state->stream)
8818                         amdgpu_dm_commit_planes(state, dc_state, dev,
8819                                                 dm, crtc, wait_for_vblank);
8820         }
8821
8822         /* Update audio instances for each connector. */
8823         amdgpu_dm_commit_audio(dev, state);
8824
8825         /* restore the backlight level */
8826         for (i = 0; i < dm->num_of_edps; i++) {
8827                 if (dm->backlight_dev[i] &&
8828                     (dm->actual_brightness[i] != dm->brightness[i]))
8829                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8830         }
8831
8832         /*
8833          * send vblank event on all events not handled in flip and
8834          * mark consumed event for drm_atomic_helper_commit_hw_done
8835          */
8836         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8837         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8838
8839                 if (new_crtc_state->event)
8840                         drm_send_event_locked(dev, &new_crtc_state->event->base);
8841
8842                 new_crtc_state->event = NULL;
8843         }
8844         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8845
8846         /* Signal HW programming completion */
8847         drm_atomic_helper_commit_hw_done(state);
8848
8849         if (wait_for_vblank)
8850                 drm_atomic_helper_wait_for_flip_done(dev, state);
8851
8852         drm_atomic_helper_cleanup_planes(dev, state);
8853
8854         /* return the stolen vga memory back to VRAM */
8855         if (!adev->mman.keep_stolen_vga_memory)
8856                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8857         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8858
8859         /*
8860          * Finally, drop a runtime PM reference for each newly disabled CRTC,
8861          * so we can put the GPU into runtime suspend if we're not driving any
8862          * displays anymore
8863          */
8864         for (i = 0; i < crtc_disable_count; i++)
8865                 pm_runtime_put_autosuspend(dev->dev);
8866         pm_runtime_mark_last_busy(dev->dev);
8867
8868         if (dc_state_temp)
8869                 dc_release_state(dc_state_temp);
8870 }
8871
8872 static int dm_force_atomic_commit(struct drm_connector *connector)
8873 {
8874         int ret = 0;
8875         struct drm_device *ddev = connector->dev;
8876         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8877         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8878         struct drm_plane *plane = disconnected_acrtc->base.primary;
8879         struct drm_connector_state *conn_state;
8880         struct drm_crtc_state *crtc_state;
8881         struct drm_plane_state *plane_state;
8882
8883         if (!state)
8884                 return -ENOMEM;
8885
8886         state->acquire_ctx = ddev->mode_config.acquire_ctx;
8887
8888         /* Construct an atomic state to restore previous display setting */
8889
8890         /*
8891          * Attach connectors to drm_atomic_state
8892          */
8893         conn_state = drm_atomic_get_connector_state(state, connector);
8894
8895         ret = PTR_ERR_OR_ZERO(conn_state);
8896         if (ret)
8897                 goto out;
8898
8899         /* Attach crtc to drm_atomic_state*/
8900         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8901
8902         ret = PTR_ERR_OR_ZERO(crtc_state);
8903         if (ret)
8904                 goto out;
8905
8906         /* force a restore */
8907         crtc_state->mode_changed = true;
8908
8909         /* Attach plane to drm_atomic_state */
8910         plane_state = drm_atomic_get_plane_state(state, plane);
8911
8912         ret = PTR_ERR_OR_ZERO(plane_state);
8913         if (ret)
8914                 goto out;
8915
8916         /* Call commit internally with the state we just constructed */
8917         ret = drm_atomic_commit(state);
8918
8919 out:
8920         drm_atomic_state_put(state);
8921         if (ret)
8922                 DRM_ERROR("Restoring old state failed with %i\n", ret);
8923
8924         return ret;
8925 }
8926
8927 /*
8928  * This function handles all cases when set mode does not come upon hotplug.
8929  * This includes when a display is unplugged then plugged back into the
8930  * same port and when running without usermode desktop manager supprot
8931  */
8932 void dm_restore_drm_connector_state(struct drm_device *dev,
8933                                     struct drm_connector *connector)
8934 {
8935         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8936         struct amdgpu_crtc *disconnected_acrtc;
8937         struct dm_crtc_state *acrtc_state;
8938
8939         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8940                 return;
8941
8942         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8943         if (!disconnected_acrtc)
8944                 return;
8945
8946         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8947         if (!acrtc_state->stream)
8948                 return;
8949
8950         /*
8951          * If the previous sink is not released and different from the current,
8952          * we deduce we are in a state where we can not rely on usermode call
8953          * to turn on the display, so we do it here
8954          */
8955         if (acrtc_state->stream->sink != aconnector->dc_sink)
8956                 dm_force_atomic_commit(&aconnector->base);
8957 }
8958
8959 /*
8960  * Grabs all modesetting locks to serialize against any blocking commits,
8961  * Waits for completion of all non blocking commits.
8962  */
8963 static int do_aquire_global_lock(struct drm_device *dev,
8964                                  struct drm_atomic_state *state)
8965 {
8966         struct drm_crtc *crtc;
8967         struct drm_crtc_commit *commit;
8968         long ret;
8969
8970         /*
8971          * Adding all modeset locks to aquire_ctx will
8972          * ensure that when the framework release it the
8973          * extra locks we are locking here will get released to
8974          */
8975         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
8976         if (ret)
8977                 return ret;
8978
8979         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8980                 spin_lock(&crtc->commit_lock);
8981                 commit = list_first_entry_or_null(&crtc->commit_list,
8982                                 struct drm_crtc_commit, commit_entry);
8983                 if (commit)
8984                         drm_crtc_commit_get(commit);
8985                 spin_unlock(&crtc->commit_lock);
8986
8987                 if (!commit)
8988                         continue;
8989
8990                 /*
8991                  * Make sure all pending HW programming completed and
8992                  * page flips done
8993                  */
8994                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
8995
8996                 if (ret > 0)
8997                         ret = wait_for_completion_interruptible_timeout(
8998                                         &commit->flip_done, 10*HZ);
8999
9000                 if (ret == 0)
9001                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
9002                                   "timed out\n", crtc->base.id, crtc->name);
9003
9004                 drm_crtc_commit_put(commit);
9005         }
9006
9007         return ret < 0 ? ret : 0;
9008 }
9009
9010 static void get_freesync_config_for_crtc(
9011         struct dm_crtc_state *new_crtc_state,
9012         struct dm_connector_state *new_con_state)
9013 {
9014         struct mod_freesync_config config = {0};
9015         struct amdgpu_dm_connector *aconnector =
9016                         to_amdgpu_dm_connector(new_con_state->base.connector);
9017         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9018         int vrefresh = drm_mode_vrefresh(mode);
9019         bool fs_vid_mode = false;
9020
9021         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9022                                         vrefresh >= aconnector->min_vfreq &&
9023                                         vrefresh <= aconnector->max_vfreq;
9024
9025         if (new_crtc_state->vrr_supported) {
9026                 new_crtc_state->stream->ignore_msa_timing_param = true;
9027                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9028
9029                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9030                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9031                 config.vsif_supported = true;
9032                 config.btr = true;
9033
9034                 if (fs_vid_mode) {
9035                         config.state = VRR_STATE_ACTIVE_FIXED;
9036                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9037                         goto out;
9038                 } else if (new_crtc_state->base.vrr_enabled) {
9039                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9040                 } else {
9041                         config.state = VRR_STATE_INACTIVE;
9042                 }
9043         }
9044 out:
9045         new_crtc_state->freesync_config = config;
9046 }
9047
9048 static void reset_freesync_config_for_crtc(
9049         struct dm_crtc_state *new_crtc_state)
9050 {
9051         new_crtc_state->vrr_supported = false;
9052
9053         memset(&new_crtc_state->vrr_infopacket, 0,
9054                sizeof(new_crtc_state->vrr_infopacket));
9055 }
9056
9057 static bool
9058 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9059                                  struct drm_crtc_state *new_crtc_state)
9060 {
9061         const struct drm_display_mode *old_mode, *new_mode;
9062
9063         if (!old_crtc_state || !new_crtc_state)
9064                 return false;
9065
9066         old_mode = &old_crtc_state->mode;
9067         new_mode = &new_crtc_state->mode;
9068
9069         if (old_mode->clock       == new_mode->clock &&
9070             old_mode->hdisplay    == new_mode->hdisplay &&
9071             old_mode->vdisplay    == new_mode->vdisplay &&
9072             old_mode->htotal      == new_mode->htotal &&
9073             old_mode->vtotal      != new_mode->vtotal &&
9074             old_mode->hsync_start == new_mode->hsync_start &&
9075             old_mode->vsync_start != new_mode->vsync_start &&
9076             old_mode->hsync_end   == new_mode->hsync_end &&
9077             old_mode->vsync_end   != new_mode->vsync_end &&
9078             old_mode->hskew       == new_mode->hskew &&
9079             old_mode->vscan       == new_mode->vscan &&
9080             (old_mode->vsync_end - old_mode->vsync_start) ==
9081             (new_mode->vsync_end - new_mode->vsync_start))
9082                 return true;
9083
9084         return false;
9085 }
9086
9087 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
9088         u64 num, den, res;
9089         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9090
9091         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9092
9093         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9094         den = (unsigned long long)new_crtc_state->mode.htotal *
9095               (unsigned long long)new_crtc_state->mode.vtotal;
9096
9097         res = div_u64(num, den);
9098         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9099 }
9100
9101 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9102                          struct drm_atomic_state *state,
9103                          struct drm_crtc *crtc,
9104                          struct drm_crtc_state *old_crtc_state,
9105                          struct drm_crtc_state *new_crtc_state,
9106                          bool enable,
9107                          bool *lock_and_validation_needed)
9108 {
9109         struct dm_atomic_state *dm_state = NULL;
9110         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9111         struct dc_stream_state *new_stream;
9112         int ret = 0;
9113
9114         /*
9115          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9116          * update changed items
9117          */
9118         struct amdgpu_crtc *acrtc = NULL;
9119         struct amdgpu_dm_connector *aconnector = NULL;
9120         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9121         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9122
9123         new_stream = NULL;
9124
9125         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9126         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9127         acrtc = to_amdgpu_crtc(crtc);
9128         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9129
9130         /* TODO This hack should go away */
9131         if (aconnector && enable) {
9132                 /* Make sure fake sink is created in plug-in scenario */
9133                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9134                                                             &aconnector->base);
9135                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9136                                                             &aconnector->base);
9137
9138                 if (IS_ERR(drm_new_conn_state)) {
9139                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9140                         goto fail;
9141                 }
9142
9143                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9144                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9145
9146                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9147                         goto skip_modeset;
9148
9149                 new_stream = create_validate_stream_for_sink(aconnector,
9150                                                              &new_crtc_state->mode,
9151                                                              dm_new_conn_state,
9152                                                              dm_old_crtc_state->stream);
9153
9154                 /*
9155                  * we can have no stream on ACTION_SET if a display
9156                  * was disconnected during S3, in this case it is not an
9157                  * error, the OS will be updated after detection, and
9158                  * will do the right thing on next atomic commit
9159                  */
9160
9161                 if (!new_stream) {
9162                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9163                                         __func__, acrtc->base.base.id);
9164                         ret = -ENOMEM;
9165                         goto fail;
9166                 }
9167
9168                 /*
9169                  * TODO: Check VSDB bits to decide whether this should
9170                  * be enabled or not.
9171                  */
9172                 new_stream->triggered_crtc_reset.enabled =
9173                         dm->force_timing_sync;
9174
9175                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9176
9177                 ret = fill_hdr_info_packet(drm_new_conn_state,
9178                                            &new_stream->hdr_static_metadata);
9179                 if (ret)
9180                         goto fail;
9181
9182                 /*
9183                  * If we already removed the old stream from the context
9184                  * (and set the new stream to NULL) then we can't reuse
9185                  * the old stream even if the stream and scaling are unchanged.
9186                  * We'll hit the BUG_ON and black screen.
9187                  *
9188                  * TODO: Refactor this function to allow this check to work
9189                  * in all conditions.
9190                  */
9191                 if (amdgpu_freesync_vid_mode &&
9192                     dm_new_crtc_state->stream &&
9193                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9194                         goto skip_modeset;
9195
9196                 if (dm_new_crtc_state->stream &&
9197                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9198                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9199                         new_crtc_state->mode_changed = false;
9200                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9201                                          new_crtc_state->mode_changed);
9202                 }
9203         }
9204
9205         /* mode_changed flag may get updated above, need to check again */
9206         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9207                 goto skip_modeset;
9208
9209         drm_dbg_state(state->dev,
9210                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
9211                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
9212                 "connectors_changed:%d\n",
9213                 acrtc->crtc_id,
9214                 new_crtc_state->enable,
9215                 new_crtc_state->active,
9216                 new_crtc_state->planes_changed,
9217                 new_crtc_state->mode_changed,
9218                 new_crtc_state->active_changed,
9219                 new_crtc_state->connectors_changed);
9220
9221         /* Remove stream for any changed/disabled CRTC */
9222         if (!enable) {
9223
9224                 if (!dm_old_crtc_state->stream)
9225                         goto skip_modeset;
9226
9227                 /* Unset freesync video if it was active before */
9228                 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9229                         dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9230                         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9231                 }
9232
9233                 /* Now check if we should set freesync video mode */
9234                 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
9235                     is_timing_unchanged_for_freesync(new_crtc_state,
9236                                                      old_crtc_state)) {
9237                         new_crtc_state->mode_changed = false;
9238                         DRM_DEBUG_DRIVER(
9239                                 "Mode change not required for front porch change, "
9240                                 "setting mode_changed to %d",
9241                                 new_crtc_state->mode_changed);
9242
9243                         set_freesync_fixed_config(dm_new_crtc_state);
9244
9245                         goto skip_modeset;
9246                 } else if (amdgpu_freesync_vid_mode && aconnector &&
9247                            is_freesync_video_mode(&new_crtc_state->mode,
9248                                                   aconnector)) {
9249                         struct drm_display_mode *high_mode;
9250
9251                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
9252                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
9253                                 set_freesync_fixed_config(dm_new_crtc_state);
9254                         }
9255                 }
9256
9257                 ret = dm_atomic_get_state(state, &dm_state);
9258                 if (ret)
9259                         goto fail;
9260
9261                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9262                                 crtc->base.id);
9263
9264                 /* i.e. reset mode */
9265                 if (dc_remove_stream_from_ctx(
9266                                 dm->dc,
9267                                 dm_state->context,
9268                                 dm_old_crtc_state->stream) != DC_OK) {
9269                         ret = -EINVAL;
9270                         goto fail;
9271                 }
9272
9273                 dc_stream_release(dm_old_crtc_state->stream);
9274                 dm_new_crtc_state->stream = NULL;
9275
9276                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9277
9278                 *lock_and_validation_needed = true;
9279
9280         } else {/* Add stream for any updated/enabled CRTC */
9281                 /*
9282                  * Quick fix to prevent NULL pointer on new_stream when
9283                  * added MST connectors not found in existing crtc_state in the chained mode
9284                  * TODO: need to dig out the root cause of that
9285                  */
9286                 if (!aconnector)
9287                         goto skip_modeset;
9288
9289                 if (modereset_required(new_crtc_state))
9290                         goto skip_modeset;
9291
9292                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9293                                      dm_old_crtc_state->stream)) {
9294
9295                         WARN_ON(dm_new_crtc_state->stream);
9296
9297                         ret = dm_atomic_get_state(state, &dm_state);
9298                         if (ret)
9299                                 goto fail;
9300
9301                         dm_new_crtc_state->stream = new_stream;
9302
9303                         dc_stream_retain(new_stream);
9304
9305                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9306                                          crtc->base.id);
9307
9308                         if (dc_add_stream_to_ctx(
9309                                         dm->dc,
9310                                         dm_state->context,
9311                                         dm_new_crtc_state->stream) != DC_OK) {
9312                                 ret = -EINVAL;
9313                                 goto fail;
9314                         }
9315
9316                         *lock_and_validation_needed = true;
9317                 }
9318         }
9319
9320 skip_modeset:
9321         /* Release extra reference */
9322         if (new_stream)
9323                 dc_stream_release(new_stream);
9324
9325         /*
9326          * We want to do dc stream updates that do not require a
9327          * full modeset below.
9328          */
9329         if (!(enable && aconnector && new_crtc_state->active))
9330                 return 0;
9331         /*
9332          * Given above conditions, the dc state cannot be NULL because:
9333          * 1. We're in the process of enabling CRTCs (just been added
9334          *    to the dc context, or already is on the context)
9335          * 2. Has a valid connector attached, and
9336          * 3. Is currently active and enabled.
9337          * => The dc stream state currently exists.
9338          */
9339         BUG_ON(dm_new_crtc_state->stream == NULL);
9340
9341         /* Scaling or underscan settings */
9342         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9343                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
9344                 update_stream_scaling_settings(
9345                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9346
9347         /* ABM settings */
9348         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9349
9350         /*
9351          * Color management settings. We also update color properties
9352          * when a modeset is needed, to ensure it gets reprogrammed.
9353          */
9354         if (dm_new_crtc_state->base.color_mgmt_changed ||
9355             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9356                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9357                 if (ret)
9358                         goto fail;
9359         }
9360
9361         /* Update Freesync settings. */
9362         get_freesync_config_for_crtc(dm_new_crtc_state,
9363                                      dm_new_conn_state);
9364
9365         return ret;
9366
9367 fail:
9368         if (new_stream)
9369                 dc_stream_release(new_stream);
9370         return ret;
9371 }
9372
9373 static bool should_reset_plane(struct drm_atomic_state *state,
9374                                struct drm_plane *plane,
9375                                struct drm_plane_state *old_plane_state,
9376                                struct drm_plane_state *new_plane_state)
9377 {
9378         struct drm_plane *other;
9379         struct drm_plane_state *old_other_state, *new_other_state;
9380         struct drm_crtc_state *new_crtc_state;
9381         int i;
9382
9383         /*
9384          * TODO: Remove this hack once the checks below are sufficient
9385          * enough to determine when we need to reset all the planes on
9386          * the stream.
9387          */
9388         if (state->allow_modeset)
9389                 return true;
9390
9391         /* Exit early if we know that we're adding or removing the plane. */
9392         if (old_plane_state->crtc != new_plane_state->crtc)
9393                 return true;
9394
9395         /* old crtc == new_crtc == NULL, plane not in context. */
9396         if (!new_plane_state->crtc)
9397                 return false;
9398
9399         new_crtc_state =
9400                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9401
9402         if (!new_crtc_state)
9403                 return true;
9404
9405         /* CRTC Degamma changes currently require us to recreate planes. */
9406         if (new_crtc_state->color_mgmt_changed)
9407                 return true;
9408
9409         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9410                 return true;
9411
9412         /*
9413          * If there are any new primary or overlay planes being added or
9414          * removed then the z-order can potentially change. To ensure
9415          * correct z-order and pipe acquisition the current DC architecture
9416          * requires us to remove and recreate all existing planes.
9417          *
9418          * TODO: Come up with a more elegant solution for this.
9419          */
9420         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9421                 struct amdgpu_framebuffer *old_afb, *new_afb;
9422                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9423                         continue;
9424
9425                 if (old_other_state->crtc != new_plane_state->crtc &&
9426                     new_other_state->crtc != new_plane_state->crtc)
9427                         continue;
9428
9429                 if (old_other_state->crtc != new_other_state->crtc)
9430                         return true;
9431
9432                 /* Src/dst size and scaling updates. */
9433                 if (old_other_state->src_w != new_other_state->src_w ||
9434                     old_other_state->src_h != new_other_state->src_h ||
9435                     old_other_state->crtc_w != new_other_state->crtc_w ||
9436                     old_other_state->crtc_h != new_other_state->crtc_h)
9437                         return true;
9438
9439                 /* Rotation / mirroring updates. */
9440                 if (old_other_state->rotation != new_other_state->rotation)
9441                         return true;
9442
9443                 /* Blending updates. */
9444                 if (old_other_state->pixel_blend_mode !=
9445                     new_other_state->pixel_blend_mode)
9446                         return true;
9447
9448                 /* Alpha updates. */
9449                 if (old_other_state->alpha != new_other_state->alpha)
9450                         return true;
9451
9452                 /* Colorspace changes. */
9453                 if (old_other_state->color_range != new_other_state->color_range ||
9454                     old_other_state->color_encoding != new_other_state->color_encoding)
9455                         return true;
9456
9457                 /* Framebuffer checks fall at the end. */
9458                 if (!old_other_state->fb || !new_other_state->fb)
9459                         continue;
9460
9461                 /* Pixel format changes can require bandwidth updates. */
9462                 if (old_other_state->fb->format != new_other_state->fb->format)
9463                         return true;
9464
9465                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9466                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9467
9468                 /* Tiling and DCC changes also require bandwidth updates. */
9469                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9470                     old_afb->base.modifier != new_afb->base.modifier)
9471                         return true;
9472         }
9473
9474         return false;
9475 }
9476
9477 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9478                               struct drm_plane_state *new_plane_state,
9479                               struct drm_framebuffer *fb)
9480 {
9481         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9482         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9483         unsigned int pitch;
9484         bool linear;
9485
9486         if (fb->width > new_acrtc->max_cursor_width ||
9487             fb->height > new_acrtc->max_cursor_height) {
9488                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9489                                  new_plane_state->fb->width,
9490                                  new_plane_state->fb->height);
9491                 return -EINVAL;
9492         }
9493         if (new_plane_state->src_w != fb->width << 16 ||
9494             new_plane_state->src_h != fb->height << 16) {
9495                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9496                 return -EINVAL;
9497         }
9498
9499         /* Pitch in pixels */
9500         pitch = fb->pitches[0] / fb->format->cpp[0];
9501
9502         if (fb->width != pitch) {
9503                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9504                                  fb->width, pitch);
9505                 return -EINVAL;
9506         }
9507
9508         switch (pitch) {
9509         case 64:
9510         case 128:
9511         case 256:
9512                 /* FB pitch is supported by cursor plane */
9513                 break;
9514         default:
9515                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9516                 return -EINVAL;
9517         }
9518
9519         /* Core DRM takes care of checking FB modifiers, so we only need to
9520          * check tiling flags when the FB doesn't have a modifier. */
9521         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9522                 if (adev->family < AMDGPU_FAMILY_AI) {
9523                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9524                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9525                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9526                 } else {
9527                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9528                 }
9529                 if (!linear) {
9530                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9531                         return -EINVAL;
9532                 }
9533         }
9534
9535         return 0;
9536 }
9537
9538 static int dm_update_plane_state(struct dc *dc,
9539                                  struct drm_atomic_state *state,
9540                                  struct drm_plane *plane,
9541                                  struct drm_plane_state *old_plane_state,
9542                                  struct drm_plane_state *new_plane_state,
9543                                  bool enable,
9544                                  bool *lock_and_validation_needed,
9545                                  bool *is_top_most_overlay)
9546 {
9547
9548         struct dm_atomic_state *dm_state = NULL;
9549         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9550         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9551         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9552         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9553         struct amdgpu_crtc *new_acrtc;
9554         bool needs_reset;
9555         int ret = 0;
9556
9557
9558         new_plane_crtc = new_plane_state->crtc;
9559         old_plane_crtc = old_plane_state->crtc;
9560         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9561         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9562
9563         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9564                 if (!enable || !new_plane_crtc ||
9565                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9566                         return 0;
9567
9568                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9569
9570                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9571                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9572                         return -EINVAL;
9573                 }
9574
9575                 if (new_plane_state->fb) {
9576                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9577                                                  new_plane_state->fb);
9578                         if (ret)
9579                                 return ret;
9580                 }
9581
9582                 return 0;
9583         }
9584
9585         needs_reset = should_reset_plane(state, plane, old_plane_state,
9586                                          new_plane_state);
9587
9588         /* Remove any changed/removed planes */
9589         if (!enable) {
9590                 if (!needs_reset)
9591                         return 0;
9592
9593                 if (!old_plane_crtc)
9594                         return 0;
9595
9596                 old_crtc_state = drm_atomic_get_old_crtc_state(
9597                                 state, old_plane_crtc);
9598                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9599
9600                 if (!dm_old_crtc_state->stream)
9601                         return 0;
9602
9603                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9604                                 plane->base.id, old_plane_crtc->base.id);
9605
9606                 ret = dm_atomic_get_state(state, &dm_state);
9607                 if (ret)
9608                         return ret;
9609
9610                 if (!dc_remove_plane_from_context(
9611                                 dc,
9612                                 dm_old_crtc_state->stream,
9613                                 dm_old_plane_state->dc_state,
9614                                 dm_state->context)) {
9615
9616                         return -EINVAL;
9617                 }
9618
9619
9620                 dc_plane_state_release(dm_old_plane_state->dc_state);
9621                 dm_new_plane_state->dc_state = NULL;
9622
9623                 *lock_and_validation_needed = true;
9624
9625         } else { /* Add new planes */
9626                 struct dc_plane_state *dc_new_plane_state;
9627
9628                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9629                         return 0;
9630
9631                 if (!new_plane_crtc)
9632                         return 0;
9633
9634                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9635                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9636
9637                 if (!dm_new_crtc_state->stream)
9638                         return 0;
9639
9640                 if (!needs_reset)
9641                         return 0;
9642
9643                 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9644                 if (ret)
9645                         return ret;
9646
9647                 WARN_ON(dm_new_plane_state->dc_state);
9648
9649                 dc_new_plane_state = dc_create_plane_state(dc);
9650                 if (!dc_new_plane_state)
9651                         return -ENOMEM;
9652
9653                 /* Block top most plane from being a video plane */
9654                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9655                         if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9656                                 return -EINVAL;
9657                         else
9658                                 *is_top_most_overlay = false;
9659                 }
9660
9661                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9662                                  plane->base.id, new_plane_crtc->base.id);
9663
9664                 ret = fill_dc_plane_attributes(
9665                         drm_to_adev(new_plane_crtc->dev),
9666                         dc_new_plane_state,
9667                         new_plane_state,
9668                         new_crtc_state);
9669                 if (ret) {
9670                         dc_plane_state_release(dc_new_plane_state);
9671                         return ret;
9672                 }
9673
9674                 ret = dm_atomic_get_state(state, &dm_state);
9675                 if (ret) {
9676                         dc_plane_state_release(dc_new_plane_state);
9677                         return ret;
9678                 }
9679
9680                 /*
9681                  * Any atomic check errors that occur after this will
9682                  * not need a release. The plane state will be attached
9683                  * to the stream, and therefore part of the atomic
9684                  * state. It'll be released when the atomic state is
9685                  * cleaned.
9686                  */
9687                 if (!dc_add_plane_to_context(
9688                                 dc,
9689                                 dm_new_crtc_state->stream,
9690                                 dc_new_plane_state,
9691                                 dm_state->context)) {
9692
9693                         dc_plane_state_release(dc_new_plane_state);
9694                         return -EINVAL;
9695                 }
9696
9697                 dm_new_plane_state->dc_state = dc_new_plane_state;
9698
9699                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9700
9701                 /* Tell DC to do a full surface update every time there
9702                  * is a plane change. Inefficient, but works for now.
9703                  */
9704                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9705
9706                 *lock_and_validation_needed = true;
9707         }
9708
9709
9710         return ret;
9711 }
9712
9713 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9714                                        int *src_w, int *src_h)
9715 {
9716         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9717         case DRM_MODE_ROTATE_90:
9718         case DRM_MODE_ROTATE_270:
9719                 *src_w = plane_state->src_h >> 16;
9720                 *src_h = plane_state->src_w >> 16;
9721                 break;
9722         case DRM_MODE_ROTATE_0:
9723         case DRM_MODE_ROTATE_180:
9724         default:
9725                 *src_w = plane_state->src_w >> 16;
9726                 *src_h = plane_state->src_h >> 16;
9727                 break;
9728         }
9729 }
9730
9731 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9732                                 struct drm_crtc *crtc,
9733                                 struct drm_crtc_state *new_crtc_state)
9734 {
9735         struct drm_plane *cursor = crtc->cursor, *underlying;
9736         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9737         int i;
9738         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9739         int cursor_src_w, cursor_src_h;
9740         int underlying_src_w, underlying_src_h;
9741
9742         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9743          * cursor per pipe but it's going to inherit the scaling and
9744          * positioning from the underlying pipe. Check the cursor plane's
9745          * blending properties match the underlying planes'. */
9746
9747         new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9748         if (!new_cursor_state || !new_cursor_state->fb) {
9749                 return 0;
9750         }
9751
9752         dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9753         cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9754         cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9755
9756         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9757                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9758                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9759                         continue;
9760
9761                 /* Ignore disabled planes */
9762                 if (!new_underlying_state->fb)
9763                         continue;
9764
9765                 dm_get_oriented_plane_size(new_underlying_state,
9766                                            &underlying_src_w, &underlying_src_h);
9767                 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9768                 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9769
9770                 if (cursor_scale_w != underlying_scale_w ||
9771                     cursor_scale_h != underlying_scale_h) {
9772                         drm_dbg_atomic(crtc->dev,
9773                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9774                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9775                         return -EINVAL;
9776                 }
9777
9778                 /* If this plane covers the whole CRTC, no need to check planes underneath */
9779                 if (new_underlying_state->crtc_x <= 0 &&
9780                     new_underlying_state->crtc_y <= 0 &&
9781                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9782                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9783                         break;
9784         }
9785
9786         return 0;
9787 }
9788
9789 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9790 {
9791         struct drm_connector *connector;
9792         struct drm_connector_state *conn_state, *old_conn_state;
9793         struct amdgpu_dm_connector *aconnector = NULL;
9794         int i;
9795         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9796                 if (!conn_state->crtc)
9797                         conn_state = old_conn_state;
9798
9799                 if (conn_state->crtc != crtc)
9800                         continue;
9801
9802                 aconnector = to_amdgpu_dm_connector(connector);
9803                 if (!aconnector->mst_output_port || !aconnector->mst_root)
9804                         aconnector = NULL;
9805                 else
9806                         break;
9807         }
9808
9809         if (!aconnector)
9810                 return 0;
9811
9812         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
9813 }
9814
9815 /**
9816  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9817  *
9818  * @dev: The DRM device
9819  * @state: The atomic state to commit
9820  *
9821  * Validate that the given atomic state is programmable by DC into hardware.
9822  * This involves constructing a &struct dc_state reflecting the new hardware
9823  * state we wish to commit, then querying DC to see if it is programmable. It's
9824  * important not to modify the existing DC state. Otherwise, atomic_check
9825  * may unexpectedly commit hardware changes.
9826  *
9827  * When validating the DC state, it's important that the right locks are
9828  * acquired. For full updates case which removes/adds/updates streams on one
9829  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9830  * that any such full update commit will wait for completion of any outstanding
9831  * flip using DRMs synchronization events.
9832  *
9833  * Note that DM adds the affected connectors for all CRTCs in state, when that
9834  * might not seem necessary. This is because DC stream creation requires the
9835  * DC sink, which is tied to the DRM connector state. Cleaning this up should
9836  * be possible but non-trivial - a possible TODO item.
9837  *
9838  * Return: -Error code if validation failed.
9839  */
9840 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9841                                   struct drm_atomic_state *state)
9842 {
9843         struct amdgpu_device *adev = drm_to_adev(dev);
9844         struct dm_atomic_state *dm_state = NULL;
9845         struct dc *dc = adev->dm.dc;
9846         struct drm_connector *connector;
9847         struct drm_connector_state *old_con_state, *new_con_state;
9848         struct drm_crtc *crtc;
9849         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9850         struct drm_plane *plane;
9851         struct drm_plane_state *old_plane_state, *new_plane_state;
9852         enum dc_status status;
9853         int ret, i;
9854         bool lock_and_validation_needed = false;
9855         bool is_top_most_overlay = true;
9856         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9857         struct drm_dp_mst_topology_mgr *mgr;
9858         struct drm_dp_mst_topology_state *mst_state;
9859         struct dsc_mst_fairness_vars vars[MAX_PIPES];
9860
9861         trace_amdgpu_dm_atomic_check_begin(state);
9862
9863         ret = drm_atomic_helper_check_modeset(dev, state);
9864         if (ret) {
9865                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9866                 goto fail;
9867         }
9868
9869         /* Check connector changes */
9870         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9871                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9872                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9873
9874                 /* Skip connectors that are disabled or part of modeset already. */
9875                 if (!new_con_state->crtc)
9876                         continue;
9877
9878                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9879                 if (IS_ERR(new_crtc_state)) {
9880                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
9881                         ret = PTR_ERR(new_crtc_state);
9882                         goto fail;
9883                 }
9884
9885                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
9886                     dm_old_con_state->scaling != dm_new_con_state->scaling)
9887                         new_crtc_state->connectors_changed = true;
9888         }
9889
9890         if (dc_resource_is_dsc_encoding_supported(dc)) {
9891                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9892                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9893                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
9894                                 if (ret) {
9895                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
9896                                         goto fail;
9897                                 }
9898                         }
9899                 }
9900         }
9901         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9902                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9903
9904                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
9905                     !new_crtc_state->color_mgmt_changed &&
9906                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9907                         dm_old_crtc_state->dsc_force_changed == false)
9908                         continue;
9909
9910                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
9911                 if (ret) {
9912                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
9913                         goto fail;
9914                 }
9915
9916                 if (!new_crtc_state->enable)
9917                         continue;
9918
9919                 ret = drm_atomic_add_affected_connectors(state, crtc);
9920                 if (ret) {
9921                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
9922                         goto fail;
9923                 }
9924
9925                 ret = drm_atomic_add_affected_planes(state, crtc);
9926                 if (ret) {
9927                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
9928                         goto fail;
9929                 }
9930
9931                 if (dm_old_crtc_state->dsc_force_changed)
9932                         new_crtc_state->mode_changed = true;
9933         }
9934
9935         /*
9936          * Add all primary and overlay planes on the CRTC to the state
9937          * whenever a plane is enabled to maintain correct z-ordering
9938          * and to enable fast surface updates.
9939          */
9940         drm_for_each_crtc(crtc, dev) {
9941                 bool modified = false;
9942
9943                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9944                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9945                                 continue;
9946
9947                         if (new_plane_state->crtc == crtc ||
9948                             old_plane_state->crtc == crtc) {
9949                                 modified = true;
9950                                 break;
9951                         }
9952                 }
9953
9954                 if (!modified)
9955                         continue;
9956
9957                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9958                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9959                                 continue;
9960
9961                         new_plane_state =
9962                                 drm_atomic_get_plane_state(state, plane);
9963
9964                         if (IS_ERR(new_plane_state)) {
9965                                 ret = PTR_ERR(new_plane_state);
9966                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
9967                                 goto fail;
9968                         }
9969                 }
9970         }
9971
9972         /*
9973          * DC consults the zpos (layer_index in DC terminology) to determine the
9974          * hw plane on which to enable the hw cursor (see
9975          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
9976          * atomic state, so call drm helper to normalize zpos.
9977          */
9978         ret = drm_atomic_normalize_zpos(dev, state);
9979         if (ret) {
9980                 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
9981                 goto fail;
9982         }
9983
9984         /* Remove exiting planes if they are modified */
9985         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9986                 ret = dm_update_plane_state(dc, state, plane,
9987                                             old_plane_state,
9988                                             new_plane_state,
9989                                             false,
9990                                             &lock_and_validation_needed,
9991                                             &is_top_most_overlay);
9992                 if (ret) {
9993                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
9994                         goto fail;
9995                 }
9996         }
9997
9998         /* Disable all crtcs which require disable */
9999         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10000                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10001                                            old_crtc_state,
10002                                            new_crtc_state,
10003                                            false,
10004                                            &lock_and_validation_needed);
10005                 if (ret) {
10006                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10007                         goto fail;
10008                 }
10009         }
10010
10011         /* Enable all crtcs which require enable */
10012         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10013                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10014                                            old_crtc_state,
10015                                            new_crtc_state,
10016                                            true,
10017                                            &lock_and_validation_needed);
10018                 if (ret) {
10019                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10020                         goto fail;
10021                 }
10022         }
10023
10024         /* Add new/modified planes */
10025         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10026                 ret = dm_update_plane_state(dc, state, plane,
10027                                             old_plane_state,
10028                                             new_plane_state,
10029                                             true,
10030                                             &lock_and_validation_needed,
10031                                             &is_top_most_overlay);
10032                 if (ret) {
10033                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10034                         goto fail;
10035                 }
10036         }
10037
10038         if (dc_resource_is_dsc_encoding_supported(dc)) {
10039                 ret = pre_validate_dsc(state, &dm_state, vars);
10040                 if (ret != 0)
10041                         goto fail;
10042         }
10043
10044         /* Run this here since we want to validate the streams we created */
10045         ret = drm_atomic_helper_check_planes(dev, state);
10046         if (ret) {
10047                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10048                 goto fail;
10049         }
10050
10051         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10052                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10053                 if (dm_new_crtc_state->mpo_requested)
10054                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10055         }
10056
10057         /* Check cursor planes scaling */
10058         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10059                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10060                 if (ret) {
10061                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10062                         goto fail;
10063                 }
10064         }
10065
10066         if (state->legacy_cursor_update) {
10067                 /*
10068                  * This is a fast cursor update coming from the plane update
10069                  * helper, check if it can be done asynchronously for better
10070                  * performance.
10071                  */
10072                 state->async_update =
10073                         !drm_atomic_helper_async_check(dev, state);
10074
10075                 /*
10076                  * Skip the remaining global validation if this is an async
10077                  * update. Cursor updates can be done without affecting
10078                  * state or bandwidth calcs and this avoids the performance
10079                  * penalty of locking the private state object and
10080                  * allocating a new dc_state.
10081                  */
10082                 if (state->async_update)
10083                         return 0;
10084         }
10085
10086         /* Check scaling and underscan changes*/
10087         /* TODO Removed scaling changes validation due to inability to commit
10088          * new stream into context w\o causing full reset. Need to
10089          * decide how to handle.
10090          */
10091         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10092                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10093                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10094                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10095
10096                 /* Skip any modesets/resets */
10097                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10098                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10099                         continue;
10100
10101                 /* Skip any thing not scale or underscan changes */
10102                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10103                         continue;
10104
10105                 lock_and_validation_needed = true;
10106         }
10107
10108         /* set the slot info for each mst_state based on the link encoding format */
10109         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10110                 struct amdgpu_dm_connector *aconnector;
10111                 struct drm_connector *connector;
10112                 struct drm_connector_list_iter iter;
10113                 u8 link_coding_cap;
10114
10115                 drm_connector_list_iter_begin(dev, &iter);
10116                 drm_for_each_connector_iter(connector, &iter) {
10117                         if (connector->index == mst_state->mgr->conn_base_id) {
10118                                 aconnector = to_amdgpu_dm_connector(connector);
10119                                 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10120                                 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10121
10122                                 break;
10123                         }
10124                 }
10125                 drm_connector_list_iter_end(&iter);
10126         }
10127
10128         /**
10129          * Streams and planes are reset when there are changes that affect
10130          * bandwidth. Anything that affects bandwidth needs to go through
10131          * DC global validation to ensure that the configuration can be applied
10132          * to hardware.
10133          *
10134          * We have to currently stall out here in atomic_check for outstanding
10135          * commits to finish in this case because our IRQ handlers reference
10136          * DRM state directly - we can end up disabling interrupts too early
10137          * if we don't.
10138          *
10139          * TODO: Remove this stall and drop DM state private objects.
10140          */
10141         if (lock_and_validation_needed) {
10142                 ret = dm_atomic_get_state(state, &dm_state);
10143                 if (ret) {
10144                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10145                         goto fail;
10146                 }
10147
10148                 ret = do_aquire_global_lock(dev, state);
10149                 if (ret) {
10150                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10151                         goto fail;
10152                 }
10153
10154                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10155                 if (ret) {
10156                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10157                         goto fail;
10158                 }
10159
10160                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10161                 if (ret) {
10162                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10163                         goto fail;
10164                 }
10165
10166                 /*
10167                  * Perform validation of MST topology in the state:
10168                  * We need to perform MST atomic check before calling
10169                  * dc_validate_global_state(), or there is a chance
10170                  * to get stuck in an infinite loop and hang eventually.
10171                  */
10172                 ret = drm_dp_mst_atomic_check(state);
10173                 if (ret) {
10174                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10175                         goto fail;
10176                 }
10177                 status = dc_validate_global_state(dc, dm_state->context, true);
10178                 if (status != DC_OK) {
10179                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10180                                        dc_status_to_str(status), status);
10181                         ret = -EINVAL;
10182                         goto fail;
10183                 }
10184         } else {
10185                 /*
10186                  * The commit is a fast update. Fast updates shouldn't change
10187                  * the DC context, affect global validation, and can have their
10188                  * commit work done in parallel with other commits not touching
10189                  * the same resource. If we have a new DC context as part of
10190                  * the DM atomic state from validation we need to free it and
10191                  * retain the existing one instead.
10192                  *
10193                  * Furthermore, since the DM atomic state only contains the DC
10194                  * context and can safely be annulled, we can free the state
10195                  * and clear the associated private object now to free
10196                  * some memory and avoid a possible use-after-free later.
10197                  */
10198
10199                 for (i = 0; i < state->num_private_objs; i++) {
10200                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10201
10202                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10203                                 int j = state->num_private_objs-1;
10204
10205                                 dm_atomic_destroy_state(obj,
10206                                                 state->private_objs[i].state);
10207
10208                                 /* If i is not at the end of the array then the
10209                                  * last element needs to be moved to where i was
10210                                  * before the array can safely be truncated.
10211                                  */
10212                                 if (i != j)
10213                                         state->private_objs[i] =
10214                                                 state->private_objs[j];
10215
10216                                 state->private_objs[j].ptr = NULL;
10217                                 state->private_objs[j].state = NULL;
10218                                 state->private_objs[j].old_state = NULL;
10219                                 state->private_objs[j].new_state = NULL;
10220
10221                                 state->num_private_objs = j;
10222                                 break;
10223                         }
10224                 }
10225         }
10226
10227         /* Store the overall update type for use later in atomic check. */
10228         for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
10229                 struct dm_crtc_state *dm_new_crtc_state =
10230                         to_dm_crtc_state(new_crtc_state);
10231
10232                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10233                                                          UPDATE_TYPE_FULL :
10234                                                          UPDATE_TYPE_FAST;
10235         }
10236
10237         /* Must be success */
10238         WARN_ON(ret);
10239
10240         trace_amdgpu_dm_atomic_check_finish(state, ret);
10241
10242         return ret;
10243
10244 fail:
10245         if (ret == -EDEADLK)
10246                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10247         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10248                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10249         else
10250                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
10251
10252         trace_amdgpu_dm_atomic_check_finish(state, ret);
10253
10254         return ret;
10255 }
10256
10257 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10258                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10259 {
10260         u8 dpcd_data;
10261         bool capable = false;
10262
10263         if (amdgpu_dm_connector->dc_link &&
10264                 dm_helpers_dp_read_dpcd(
10265                                 NULL,
10266                                 amdgpu_dm_connector->dc_link,
10267                                 DP_DOWN_STREAM_PORT_COUNT,
10268                                 &dpcd_data,
10269                                 sizeof(dpcd_data))) {
10270                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10271         }
10272
10273         return capable;
10274 }
10275
10276 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10277                 unsigned int offset,
10278                 unsigned int total_length,
10279                 u8 *data,
10280                 unsigned int length,
10281                 struct amdgpu_hdmi_vsdb_info *vsdb)
10282 {
10283         bool res;
10284         union dmub_rb_cmd cmd;
10285         struct dmub_cmd_send_edid_cea *input;
10286         struct dmub_cmd_edid_cea_output *output;
10287
10288         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10289                 return false;
10290
10291         memset(&cmd, 0, sizeof(cmd));
10292
10293         input = &cmd.edid_cea.data.input;
10294
10295         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10296         cmd.edid_cea.header.sub_type = 0;
10297         cmd.edid_cea.header.payload_bytes =
10298                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10299         input->offset = offset;
10300         input->length = length;
10301         input->cea_total_length = total_length;
10302         memcpy(input->payload, data, length);
10303
10304         res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
10305         if (!res) {
10306                 DRM_ERROR("EDID CEA parser failed\n");
10307                 return false;
10308         }
10309
10310         output = &cmd.edid_cea.data.output;
10311
10312         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10313                 if (!output->ack.success) {
10314                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
10315                                         output->ack.offset);
10316                 }
10317         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10318                 if (!output->amd_vsdb.vsdb_found)
10319                         return false;
10320
10321                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10322                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10323                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10324                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10325         } else {
10326                 DRM_WARN("Unknown EDID CEA parser results\n");
10327                 return false;
10328         }
10329
10330         return true;
10331 }
10332
10333 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10334                 u8 *edid_ext, int len,
10335                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10336 {
10337         int i;
10338
10339         /* send extension block to DMCU for parsing */
10340         for (i = 0; i < len; i += 8) {
10341                 bool res;
10342                 int offset;
10343
10344                 /* send 8 bytes a time */
10345                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10346                         return false;
10347
10348                 if (i+8 == len) {
10349                         /* EDID block sent completed, expect result */
10350                         int version, min_rate, max_rate;
10351
10352                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10353                         if (res) {
10354                                 /* amd vsdb found */
10355                                 vsdb_info->freesync_supported = 1;
10356                                 vsdb_info->amd_vsdb_version = version;
10357                                 vsdb_info->min_refresh_rate_hz = min_rate;
10358                                 vsdb_info->max_refresh_rate_hz = max_rate;
10359                                 return true;
10360                         }
10361                         /* not amd vsdb */
10362                         return false;
10363                 }
10364
10365                 /* check for ack*/
10366                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10367                 if (!res)
10368                         return false;
10369         }
10370
10371         return false;
10372 }
10373
10374 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10375                 u8 *edid_ext, int len,
10376                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10377 {
10378         int i;
10379
10380         /* send extension block to DMCU for parsing */
10381         for (i = 0; i < len; i += 8) {
10382                 /* send 8 bytes a time */
10383                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10384                         return false;
10385         }
10386
10387         return vsdb_info->freesync_supported;
10388 }
10389
10390 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10391                 u8 *edid_ext, int len,
10392                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10393 {
10394         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10395         bool ret;
10396
10397         mutex_lock(&adev->dm.dc_lock);
10398         if (adev->dm.dmub_srv)
10399                 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10400         else
10401                 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10402         mutex_unlock(&adev->dm.dc_lock);
10403         return ret;
10404 }
10405
10406 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10407                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10408 {
10409         u8 *edid_ext = NULL;
10410         int i;
10411         bool valid_vsdb_found = false;
10412
10413         /*----- drm_find_cea_extension() -----*/
10414         /* No EDID or EDID extensions */
10415         if (edid == NULL || edid->extensions == 0)
10416                 return -ENODEV;
10417
10418         /* Find CEA extension */
10419         for (i = 0; i < edid->extensions; i++) {
10420                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10421                 if (edid_ext[0] == CEA_EXT)
10422                         break;
10423         }
10424
10425         if (i == edid->extensions)
10426                 return -ENODEV;
10427
10428         /*----- cea_db_offsets() -----*/
10429         if (edid_ext[0] != CEA_EXT)
10430                 return -ENODEV;
10431
10432         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10433
10434         return valid_vsdb_found ? i : -ENODEV;
10435 }
10436
10437 /**
10438  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10439  *
10440  * @connector: Connector to query.
10441  * @edid: EDID from monitor
10442  *
10443  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10444  * track of some of the display information in the internal data struct used by
10445  * amdgpu_dm. This function checks which type of connector we need to set the
10446  * FreeSync parameters.
10447  */
10448 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10449                                     struct edid *edid)
10450 {
10451         int i = 0;
10452         struct detailed_timing *timing;
10453         struct detailed_non_pixel *data;
10454         struct detailed_data_monitor_range *range;
10455         struct amdgpu_dm_connector *amdgpu_dm_connector =
10456                         to_amdgpu_dm_connector(connector);
10457         struct dm_connector_state *dm_con_state = NULL;
10458         struct dc_sink *sink;
10459
10460         struct drm_device *dev = connector->dev;
10461         struct amdgpu_device *adev = drm_to_adev(dev);
10462         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10463         bool freesync_capable = false;
10464         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10465
10466         if (!connector->state) {
10467                 DRM_ERROR("%s - Connector has no state", __func__);
10468                 goto update;
10469         }
10470
10471         sink = amdgpu_dm_connector->dc_sink ?
10472                 amdgpu_dm_connector->dc_sink :
10473                 amdgpu_dm_connector->dc_em_sink;
10474
10475         if (!edid || !sink) {
10476                 dm_con_state = to_dm_connector_state(connector->state);
10477
10478                 amdgpu_dm_connector->min_vfreq = 0;
10479                 amdgpu_dm_connector->max_vfreq = 0;
10480                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10481                 connector->display_info.monitor_range.min_vfreq = 0;
10482                 connector->display_info.monitor_range.max_vfreq = 0;
10483                 freesync_capable = false;
10484
10485                 goto update;
10486         }
10487
10488         dm_con_state = to_dm_connector_state(connector->state);
10489
10490         if (!adev->dm.freesync_module)
10491                 goto update;
10492
10493         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10494                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10495                 bool edid_check_required = false;
10496
10497                 if (edid) {
10498                         edid_check_required = is_dp_capable_without_timing_msa(
10499                                                 adev->dm.dc,
10500                                                 amdgpu_dm_connector);
10501                 }
10502
10503                 if (edid_check_required == true && (edid->version > 1 ||
10504                    (edid->version == 1 && edid->revision > 1))) {
10505                         for (i = 0; i < 4; i++) {
10506
10507                                 timing  = &edid->detailed_timings[i];
10508                                 data    = &timing->data.other_data;
10509                                 range   = &data->data.range;
10510                                 /*
10511                                  * Check if monitor has continuous frequency mode
10512                                  */
10513                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10514                                         continue;
10515                                 /*
10516                                  * Check for flag range limits only. If flag == 1 then
10517                                  * no additional timing information provided.
10518                                  * Default GTF, GTF Secondary curve and CVT are not
10519                                  * supported
10520                                  */
10521                                 if (range->flags != 1)
10522                                         continue;
10523
10524                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10525                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10526                                 amdgpu_dm_connector->pixel_clock_mhz =
10527                                         range->pixel_clock_mhz * 10;
10528
10529                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10530                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10531
10532                                 break;
10533                         }
10534
10535                         if (amdgpu_dm_connector->max_vfreq -
10536                             amdgpu_dm_connector->min_vfreq > 10) {
10537
10538                                 freesync_capable = true;
10539                         }
10540                 }
10541         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10542                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10543                 if (i >= 0 && vsdb_info.freesync_supported) {
10544                         timing  = &edid->detailed_timings[i];
10545                         data    = &timing->data.other_data;
10546
10547                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10548                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10549                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10550                                 freesync_capable = true;
10551
10552                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10553                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10554                 }
10555         }
10556
10557         as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10558
10559         if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10560                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10561                 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10562
10563                         amdgpu_dm_connector->pack_sdp_v1_3 = true;
10564                         amdgpu_dm_connector->as_type = as_type;
10565                         amdgpu_dm_connector->vsdb_info = vsdb_info;
10566
10567                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10568                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10569                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10570                                 freesync_capable = true;
10571
10572                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10573                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10574                 }
10575         }
10576
10577 update:
10578         if (dm_con_state)
10579                 dm_con_state->freesync_capable = freesync_capable;
10580
10581         if (connector->vrr_capable_property)
10582                 drm_connector_set_vrr_capable_property(connector,
10583                                                        freesync_capable);
10584 }
10585
10586 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10587 {
10588         struct amdgpu_device *adev = drm_to_adev(dev);
10589         struct dc *dc = adev->dm.dc;
10590         int i;
10591
10592         mutex_lock(&adev->dm.dc_lock);
10593         if (dc->current_state) {
10594                 for (i = 0; i < dc->current_state->stream_count; ++i)
10595                         dc->current_state->streams[i]
10596                                 ->triggered_crtc_reset.enabled =
10597                                 adev->dm.force_timing_sync;
10598
10599                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10600                 dc_trigger_sync(dc, dc->current_state);
10601         }
10602         mutex_unlock(&adev->dm.dc_lock);
10603 }
10604
10605 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10606                        u32 value, const char *func_name)
10607 {
10608 #ifdef DM_CHECK_ADDR_0
10609         if (address == 0) {
10610                 DC_ERR("invalid register write. address = 0");
10611                 return;
10612         }
10613 #endif
10614         cgs_write_register(ctx->cgs_device, address, value);
10615         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10616 }
10617
10618 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10619                           const char *func_name)
10620 {
10621         u32 value;
10622 #ifdef DM_CHECK_ADDR_0
10623         if (address == 0) {
10624                 DC_ERR("invalid register read; address = 0\n");
10625                 return 0;
10626         }
10627 #endif
10628
10629         if (ctx->dmub_srv &&
10630             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10631             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10632                 ASSERT(false);
10633                 return 0;
10634         }
10635
10636         value = cgs_read_register(ctx->cgs_device, address);
10637
10638         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10639
10640         return value;
10641 }
10642
10643 int amdgpu_dm_process_dmub_aux_transfer_sync(
10644                 struct dc_context *ctx,
10645                 unsigned int link_index,
10646                 struct aux_payload *payload,
10647                 enum aux_return_code_type *operation_result)
10648 {
10649         struct amdgpu_device *adev = ctx->driver_context;
10650         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10651         int ret = -1;
10652
10653         mutex_lock(&adev->dm.dpia_aux_lock);
10654         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10655                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10656                 goto out;
10657         }
10658
10659         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10660                 DRM_ERROR("wait_for_completion_timeout timeout!");
10661                 *operation_result = AUX_RET_ERROR_TIMEOUT;
10662                 goto out;
10663         }
10664
10665         if (p_notify->result != AUX_RET_SUCCESS) {
10666                 /*
10667                  * Transient states before tunneling is enabled could
10668                  * lead to this error. We can ignore this for now.
10669                  */
10670                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10671                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10672                                         payload->address, payload->length,
10673                                         p_notify->result);
10674                 }
10675                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10676                 goto out;
10677         }
10678
10679
10680         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10681         if (!payload->write && p_notify->aux_reply.length &&
10682                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10683
10684                 if (payload->length != p_notify->aux_reply.length) {
10685                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10686                                 p_notify->aux_reply.length,
10687                                         payload->address, payload->length);
10688                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10689                         goto out;
10690                 }
10691
10692                 memcpy(payload->data, p_notify->aux_reply.data,
10693                                 p_notify->aux_reply.length);
10694         }
10695
10696         /* success */
10697         ret = p_notify->aux_reply.length;
10698         *operation_result = p_notify->result;
10699 out:
10700         reinit_completion(&adev->dm.dmub_aux_transfer_done);
10701         mutex_unlock(&adev->dm.dpia_aux_lock);
10702         return ret;
10703 }
10704
10705 int amdgpu_dm_process_dmub_set_config_sync(
10706                 struct dc_context *ctx,
10707                 unsigned int link_index,
10708                 struct set_config_cmd_payload *payload,
10709                 enum set_config_status *operation_result)
10710 {
10711         struct amdgpu_device *adev = ctx->driver_context;
10712         bool is_cmd_complete;
10713         int ret;
10714
10715         mutex_lock(&adev->dm.dpia_aux_lock);
10716         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10717                         link_index, payload, adev->dm.dmub_notify);
10718
10719         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10720                 ret = 0;
10721                 *operation_result = adev->dm.dmub_notify->sc_status;
10722         } else {
10723                 DRM_ERROR("wait_for_completion_timeout timeout!");
10724                 ret = -1;
10725                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10726         }
10727
10728         if (!is_cmd_complete)
10729                 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10730         mutex_unlock(&adev->dm.dpia_aux_lock);
10731         return ret;
10732 }
10733
10734 /*
10735  * Check whether seamless boot is supported.
10736  *
10737  * So far we only support seamless boot on CHIP_VANGOGH.
10738  * If everything goes well, we may consider expanding
10739  * seamless boot to other ASICs.
10740  */
10741 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10742 {
10743         switch (adev->ip_versions[DCE_HWIP][0]) {
10744         case IP_VERSION(3, 0, 1):
10745                 if (!adev->mman.keep_stolen_vga_memory)
10746                         return true;
10747                 break;
10748         default:
10749                 break;
10750         }
10751
10752         return false;
10753 }