drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "link_enc_cfg.h"
  32 #include "dc/inc/core_types.h"
  33 #include "dal_asic_id.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "dc/inc/hw/dmcu.h"
  36 #include "dc/inc/hw/abm.h"
  37 #include "dc/dc_dmub_srv.h"
  38 #include "dc/dc_edid_parser.h"
  39 #include "dc/dc_stat.h"
  40 #include "amdgpu_dm_trace.h"
  41 #include "dpcd_defs.h"
  42 #include "link/protocols/link_dpcd.h"
  43 #include "link_service_types.h"
  44 #include "link/protocols/link_dp_capability.h"
  45 #include "link/protocols/link_ddc.h"
  46
  47 #include "vid.h"
  48 #include "amdgpu.h"
  49 #include "amdgpu_display.h"
  50 #include "amdgpu_ucode.h"
  51 #include "atom.h"
  52 #include "amdgpu_dm.h"
  53 #include "amdgpu_dm_plane.h"
  54 #include "amdgpu_dm_crtc.h"
  55 #include "amdgpu_dm_hdcp.h"
  56 #include <drm/display/drm_hdcp_helper.h>
  57 #include "amdgpu_pm.h"
  58 #include "amdgpu_atombios.h"
  59
  60 #include "amd_shared.h"
  61 #include "amdgpu_dm_irq.h"
  62 #include "dm_helpers.h"
  63 #include "amdgpu_dm_mst_types.h"
  64 #if defined(CONFIG_DEBUG_FS)
  65 #include "amdgpu_dm_debugfs.h"
  66 #endif
  67 #include "amdgpu_dm_psr.h"
  68 #include "amdgpu_dm_replay.h"
  69
  70 #include "ivsrcid/ivsrcid_vislands30.h"
  71
  72 #include <linux/backlight.h>
  73 #include <linux/module.h>
  74 #include <linux/moduleparam.h>
  75 #include <linux/types.h>
  76 #include <linux/pm_runtime.h>
  77 #include <linux/pci.h>
  78 #include <linux/firmware.h>
  79 #include <linux/component.h>
  80 #include <linux/dmi.h>
  81
  82 #include <drm/display/drm_dp_mst_helper.h>
  83 #include <drm/display/drm_hdmi_helper.h>
  84 #include <drm/drm_atomic.h>
  85 #include <drm/drm_atomic_uapi.h>
  86 #include <drm/drm_atomic_helper.h>
  87 #include <drm/drm_blend.h>
  88 #include <drm/drm_fourcc.h>
  89 #include <drm/drm_edid.h>
  90 #include <drm/drm_vblank.h>
  91 #include <drm/drm_audio_component.h>
  92 #include <drm/drm_gem_atomic_helper.h>
  93 #include <drm/drm_plane_helper.h>
  94
  95 #include <acpi/video.h>
  96
  97 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  98
  99 #include "dcn/dcn_1_0_offset.h"
 100 #include "dcn/dcn_1_0_sh_mask.h"
 101 #include "soc15_hw_ip.h"
 102 #include "soc15_common.h"
 103 #include "vega10_ip_offset.h"
 104
 105 #include "gc/gc_11_0_0_offset.h"
 106 #include "gc/gc_11_0_0_sh_mask.h"
 107
 108 #include "modules/inc/mod_freesync.h"
 109 #include "modules/power/power_helpers.h"
 110
 111 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 112 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 113 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 114 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 115 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 116 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 117 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 118 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 119 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 120 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 121 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 122 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 123 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 124 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 125 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 126 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 127 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 128 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 129 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 130 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 131 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 132 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 133
 134 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 135 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 136 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 137 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 138
 139 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 140 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 141
 142 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 143 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 144
 145 #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin"
 146 MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB);
 147
 148 /* Number of bytes in PSP header for firmware. */
 149 #define PSP_HEADER_BYTES 0x100
 150
 151 /* Number of bytes in PSP footer for firmware. */
 152 #define PSP_FOOTER_BYTES 0x100
 153
 154 /**
 155  * DOC: overview
 156  *
 157  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 158  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 159  * requests into DC requests, and DC responses into DRM responses.
 160  *
 161  * The root control structure is &struct amdgpu_display_manager.
 162  */
 163
 164 /* basic init/fini API */
 165 static int amdgpu_dm_init(struct amdgpu_device *adev);
 166 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 167 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 168
 169 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 170 {
 171         switch (link->dpcd_caps.dongle_type) {
 172         case DISPLAY_DONGLE_NONE:
 173                 return DRM_MODE_SUBCONNECTOR_Native;
 174         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 175                 return DRM_MODE_SUBCONNECTOR_VGA;
 176         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 177         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 178                 return DRM_MODE_SUBCONNECTOR_DVID;
 179         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 180         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 181                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 182         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 183         default:
 184                 return DRM_MODE_SUBCONNECTOR_Unknown;
 185         }
 186 }
 187
 188 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 189 {
 190         struct dc_link *link = aconnector->dc_link;
 191         struct drm_connector *connector = &aconnector->base;
 192         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 193
 194         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 195                 return;
 196
 197         if (aconnector->dc_sink)
 198                 subconnector = get_subconnector_type(link);
 199
 200         drm_object_property_set_value(&connector->base,
 201                         connector->dev->mode_config.dp_subconnector_property,
 202                         subconnector);
 203 }
 204
 205 /*
 206  * initializes drm_device display related structures, based on the information
 207  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 208  * drm_encoder, drm_mode_config
 209  *
 210  * Returns 0 on success
 211  */
 212 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 213 /* removes and deallocates the drm structures, created by the above function */
 214 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 215
 216 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 217                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 218                                     u32 link_index,
 219                                     struct amdgpu_encoder *amdgpu_encoder);
 220 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 221                                   struct amdgpu_encoder *aencoder,
 222                                   uint32_t link_index);
 223
 224 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 225
 226 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 227
 228 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 229                                   struct drm_atomic_state *state);
 230
 231 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 232 static void handle_hpd_rx_irq(void *param);
 233
 234 static bool
 235 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 236                                  struct drm_crtc_state *new_crtc_state);
 237 /*
 238  * dm_vblank_get_counter
 239  *
 240  * @brief
 241  * Get counter for number of vertical blanks
 242  *
 243  * @param
 244  * struct amdgpu_device *adev - [in] desired amdgpu device
 245  * int disp_idx - [in] which CRTC to get the counter from
 246  *
 247  * @return
 248  * Counter for vertical blanks
 249  */
 250 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 251 {
 252         struct amdgpu_crtc *acrtc = NULL;
 253
 254         if (crtc >= adev->mode_info.num_crtc)
 255                 return 0;
 256
 257         acrtc = adev->mode_info.crtcs[crtc];
 258
 259         if (!acrtc->dm_irq_params.stream) {
 260                 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 261                           crtc);
 262                 return 0;
 263         }
 264
 265         return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 266 }
 267
 268 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 269                                   u32 *vbl, u32 *position)
 270 {
 271         u32 v_blank_start, v_blank_end, h_position, v_position;
 272         struct amdgpu_crtc *acrtc = NULL;
 273
 274         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 275                 return -EINVAL;
 276
 277         acrtc = adev->mode_info.crtcs[crtc];
 278
 279         if (!acrtc->dm_irq_params.stream) {
 280                 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 281                           crtc);
 282                 return 0;
 283         }
 284
 285         /*
 286          * TODO rework base driver to use values directly.
 287          * for now parse it back into reg-format
 288          */
 289         dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 290                                  &v_blank_start,
 291                                  &v_blank_end,
 292                                  &h_position,
 293                                  &v_position);
 294
 295         *position = v_position | (h_position << 16);
 296         *vbl = v_blank_start | (v_blank_end << 16);
 297
 298         return 0;
 299 }
 300
 301 static bool dm_is_idle(void *handle)
 302 {
 303         /* XXX todo */
 304         return true;
 305 }
 306
 307 static int dm_wait_for_idle(void *handle)
 308 {
 309         /* XXX todo */
 310         return 0;
 311 }
 312
 313 static bool dm_check_soft_reset(void *handle)
 314 {
 315         return false;
 316 }
 317
 318 static int dm_soft_reset(void *handle)
 319 {
 320         /* XXX todo */
 321         return 0;
 322 }
 323
 324 static struct amdgpu_crtc *
 325 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 326                      int otg_inst)
 327 {
 328         struct drm_device *dev = adev_to_drm(adev);
 329         struct drm_crtc *crtc;
 330         struct amdgpu_crtc *amdgpu_crtc;
 331
 332         if (WARN_ON(otg_inst == -1))
 333                 return adev->mode_info.crtcs[0];
 334
 335         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 336                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 337
 338                 if (amdgpu_crtc->otg_inst == otg_inst)
 339                         return amdgpu_crtc;
 340         }
 341
 342         return NULL;
 343 }
 344
 345 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 346                                               struct dm_crtc_state *new_state)
 347 {
 348         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 349                 return true;
 350         else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
 351                 return true;
 352         else
 353                 return false;
 354 }
 355
 356 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
 357                                         int planes_count)
 358 {
 359         int i, j;
 360
 361         for (i = 0, j = planes_count - 1; i < j; i++, j--)
 362                 swap(array_of_surface_update[i], array_of_surface_update[j]);
 363 }
 364
 365 /**
 366  * update_planes_and_stream_adapter() - Send planes to be updated in DC
 367  *
 368  * DC has a generic way to update planes and stream via
 369  * dc_update_planes_and_stream function; however, DM might need some
 370  * adjustments and preparation before calling it. This function is a wrapper
 371  * for the dc_update_planes_and_stream that does any required configuration
 372  * before passing control to DC.
 373  *
 374  * @dc: Display Core control structure
 375  * @update_type: specify whether it is FULL/MEDIUM/FAST update
 376  * @planes_count: planes count to update
 377  * @stream: stream state
 378  * @stream_update: stream update
 379  * @array_of_surface_update: dc surface update pointer
 380  *
 381  */
 382 static inline bool update_planes_and_stream_adapter(struct dc *dc,
 383                                                     int update_type,
 384                                                     int planes_count,
 385                                                     struct dc_stream_state *stream,
 386                                                     struct dc_stream_update *stream_update,
 387                                                     struct dc_surface_update *array_of_surface_update)
 388 {
 389         reverse_planes_order(array_of_surface_update, planes_count);
 390
 391         /*
 392          * Previous frame finished and HW is ready for optimization.
 393          */
 394         if (update_type == UPDATE_TYPE_FAST)
 395                 dc_post_update_surfaces_to_stream(dc);
 396
 397         return dc_update_planes_and_stream(dc,
 398                                            array_of_surface_update,
 399                                            planes_count,
 400                                            stream,
 401                                            stream_update);
 402 }
 403
 404 /**
 405  * dm_pflip_high_irq() - Handle pageflip interrupt
 406  * @interrupt_params: ignored
 407  *
 408  * Handles the pageflip interrupt by notifying all interested parties
 409  * that the pageflip has been completed.
 410  */
 411 static void dm_pflip_high_irq(void *interrupt_params)
 412 {
 413         struct amdgpu_crtc *amdgpu_crtc;
 414         struct common_irq_params *irq_params = interrupt_params;
 415         struct amdgpu_device *adev = irq_params->adev;
 416         struct drm_device *dev = adev_to_drm(adev);
 417         unsigned long flags;
 418         struct drm_pending_vblank_event *e;
 419         u32 vpos, hpos, v_blank_start, v_blank_end;
 420         bool vrr_active;
 421
 422         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 423
 424         /* IRQ could occur when in initial stage */
 425         /* TODO work and BO cleanup */
 426         if (amdgpu_crtc == NULL) {
 427                 drm_dbg_state(dev, "CRTC is null, returning.\n");
 428                 return;
 429         }
 430
 431         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 432
 433         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
 434                 drm_dbg_state(dev,
 435                               "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",
 436                               amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED,
 437                               amdgpu_crtc->crtc_id, amdgpu_crtc);
 438                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 439                 return;
 440         }
 441
 442         /* page flip completed. */
 443         e = amdgpu_crtc->event;
 444         amdgpu_crtc->event = NULL;
 445
 446         WARN_ON(!e);
 447
 448         vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
 449
 450         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 451         if (!vrr_active ||
 452             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 453                                       &v_blank_end, &hpos, &vpos) ||
 454             (vpos < v_blank_start)) {
 455                 /* Update to correct count and vblank timestamp if racing with
 456                  * vblank irq. This also updates to the correct vblank timestamp
 457                  * even in VRR mode, as scanout is past the front-porch atm.
 458                  */
 459                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 460
 461                 /* Wake up userspace by sending the pageflip event with proper
 462                  * count and timestamp of vblank of flip completion.
 463                  */
 464                 if (e) {
 465                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 466
 467                         /* Event sent, so done with vblank for this flip */
 468                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 469                 }
 470         } else if (e) {
 471                 /* VRR active and inside front-porch: vblank count and
 472                  * timestamp for pageflip event will only be up to date after
 473                  * drm_crtc_handle_vblank() has been executed from late vblank
 474                  * irq handler after start of back-porch (vline 0). We queue the
 475                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 476                  * updated timestamp and count, once it runs after us.
 477                  *
 478                  * We need to open-code this instead of using the helper
 479                  * drm_crtc_arm_vblank_event(), as that helper would
 480                  * call drm_crtc_accurate_vblank_count(), which we must
 481                  * not call in VRR mode while we are in front-porch!
 482                  */
 483
 484                 /* sequence will be replaced by real count during send-out. */
 485                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 486                 e->pipe = amdgpu_crtc->crtc_id;
 487
 488                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 489                 e = NULL;
 490         }
 491
 492         /* Keep track of vblank of this flip for flip throttling. We use the
 493          * cooked hw counter, as that one incremented at start of this vblank
 494          * of pageflip completion, so last_flip_vblank is the forbidden count
 495          * for queueing new pageflips if vsync + VRR is enabled.
 496          */
 497         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 498                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 499
 500         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 501         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 502
 503         drm_dbg_state(dev,
 504                       "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 505                       amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e);
 506 }
 507
 508 static void dm_vupdate_high_irq(void *interrupt_params)
 509 {
 510         struct common_irq_params *irq_params = interrupt_params;
 511         struct amdgpu_device *adev = irq_params->adev;
 512         struct amdgpu_crtc *acrtc;
 513         struct drm_device *drm_dev;
 514         struct drm_vblank_crtc *vblank;
 515         ktime_t frame_duration_ns, previous_timestamp;
 516         unsigned long flags;
 517         int vrr_active;
 518
 519         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 520
 521         if (acrtc) {
 522                 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 523                 drm_dev = acrtc->base.dev;
 524                 vblank = &drm_dev->vblank[acrtc->base.index];
 525                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 526                 frame_duration_ns = vblank->time - previous_timestamp;
 527
 528                 if (frame_duration_ns > 0) {
 529                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 530                                                 frame_duration_ns,
 531                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 532                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 533                 }
 534
 535                 drm_dbg_vbl(drm_dev,
 536                             "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
 537                             vrr_active);
 538
 539                 /* Core vblank handling is done here after end of front-porch in
 540                  * vrr mode, as vblank timestamping will give valid results
 541                  * while now done after front-porch. This will also deliver
 542                  * page-flip completion events that have been queued to us
 543                  * if a pageflip happened inside front-porch.
 544                  */
 545                 if (vrr_active) {
 546                         amdgpu_dm_crtc_handle_vblank(acrtc);
 547
 548                         /* BTR processing for pre-DCE12 ASICs */
 549                         if (acrtc->dm_irq_params.stream &&
 550                             adev->family < AMDGPU_FAMILY_AI) {
 551                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 552                                 mod_freesync_handle_v_update(
 553                                     adev->dm.freesync_module,
 554                                     acrtc->dm_irq_params.stream,
 555                                     &acrtc->dm_irq_params.vrr_params);
 556
 557                                 dc_stream_adjust_vmin_vmax(
 558                                     adev->dm.dc,
 559                                     acrtc->dm_irq_params.stream,
 560                                     &acrtc->dm_irq_params.vrr_params.adjust);
 561                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 562                         }
 563                 }
 564         }
 565 }
 566
 567 /**
 568  * dm_crtc_high_irq() - Handles CRTC interrupt
 569  * @interrupt_params: used for determining the CRTC instance
 570  *
 571  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 572  * event handler.
 573  */
 574 static void dm_crtc_high_irq(void *interrupt_params)
 575 {
 576         struct common_irq_params *irq_params = interrupt_params;
 577         struct amdgpu_device *adev = irq_params->adev;
 578         struct amdgpu_crtc *acrtc;
 579         unsigned long flags;
 580         int vrr_active;
 581
 582         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 583         if (!acrtc)
 584                 return;
 585
 586         vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 587
 588         drm_dbg_vbl(adev_to_drm(adev),
 589                     "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 590                     vrr_active, acrtc->dm_irq_params.active_planes);
 591
 592         /**
 593          * Core vblank handling at start of front-porch is only possible
 594          * in non-vrr mode, as only there vblank timestamping will give
 595          * valid results while done in front-porch. Otherwise defer it
 596          * to dm_vupdate_high_irq after end of front-porch.
 597          */
 598         if (!vrr_active)
 599                 amdgpu_dm_crtc_handle_vblank(acrtc);
 600
 601         /**
 602          * Following stuff must happen at start of vblank, for crc
 603          * computation and below-the-range btr support in vrr mode.
 604          */
 605         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 606
 607         /* BTR updates need to happen before VUPDATE on Vega and above. */
 608         if (adev->family < AMDGPU_FAMILY_AI)
 609                 return;
 610
 611         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 612
 613         if (acrtc->dm_irq_params.stream &&
 614             acrtc->dm_irq_params.vrr_params.supported &&
 615             acrtc->dm_irq_params.freesync_config.state ==
 616                     VRR_STATE_ACTIVE_VARIABLE) {
 617                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 618                                              acrtc->dm_irq_params.stream,
 619                                              &acrtc->dm_irq_params.vrr_params);
 620
 621                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 622                                            &acrtc->dm_irq_params.vrr_params.adjust);
 623         }
 624
 625         /*
 626          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 627          * In that case, pageflip completion interrupts won't fire and pageflip
 628          * completion events won't get delivered. Prevent this by sending
 629          * pending pageflip events from here if a flip is still pending.
 630          *
 631          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 632          * avoid race conditions between flip programming and completion,
 633          * which could cause too early flip completion events.
 634          */
 635         if (adev->family >= AMDGPU_FAMILY_RV &&
 636             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 637             acrtc->dm_irq_params.active_planes == 0) {
 638                 if (acrtc->event) {
 639                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 640                         acrtc->event = NULL;
 641                         drm_crtc_vblank_put(&acrtc->base);
 642                 }
 643                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 644         }
 645
 646         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 647 }
 648
 649 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 650 /**
 651  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 652  * DCN generation ASICs
 653  * @interrupt_params: interrupt parameters
 654  *
 655  * Used to set crc window/read out crc value at vertical line 0 position
 656  */
 657 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 658 {
 659         struct common_irq_params *irq_params = interrupt_params;
 660         struct amdgpu_device *adev = irq_params->adev;
 661         struct amdgpu_crtc *acrtc;
 662
 663         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 664
 665         if (!acrtc)
 666                 return;
 667
 668         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 669 }
 670 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 671
 672 /**
 673  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 674  * @adev: amdgpu_device pointer
 675  * @notify: dmub notification structure
 676  *
 677  * Dmub AUX or SET_CONFIG command completion processing callback
 678  * Copies dmub notification to DM which is to be read by AUX command.
 679  * issuing thread and also signals the event to wake up the thread.
 680  */
 681 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 682                                         struct dmub_notification *notify)
 683 {
 684         if (adev->dm.dmub_notify)
 685                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 686         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 687                 complete(&adev->dm.dmub_aux_transfer_done);
 688 }
 689
 690 /**
 691  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 692  * @adev: amdgpu_device pointer
 693  * @notify: dmub notification structure
 694  *
 695  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 696  * ink index and calls helper to do the processing.
 697  */
 698 static void dmub_hpd_callback(struct amdgpu_device *adev,
 699                               struct dmub_notification *notify)
 700 {
 701         struct amdgpu_dm_connector *aconnector;
 702         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 703         struct drm_connector *connector;
 704         struct drm_connector_list_iter iter;
 705         struct dc_link *link;
 706         u8 link_index = 0;
 707         struct drm_device *dev;
 708
 709         if (adev == NULL)
 710                 return;
 711
 712         if (notify == NULL) {
 713                 DRM_ERROR("DMUB HPD callback notification was NULL");
 714                 return;
 715         }
 716
 717         if (notify->link_index > adev->dm.dc->link_count) {
 718                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 719                 return;
 720         }
 721
 722         link_index = notify->link_index;
 723         link = adev->dm.dc->links[link_index];
 724         dev = adev->dm.ddev;
 725
 726         drm_connector_list_iter_begin(dev, &iter);
 727         drm_for_each_connector_iter(connector, &iter) {
 728                 aconnector = to_amdgpu_dm_connector(connector);
 729                 if (link && aconnector->dc_link == link) {
 730                         if (notify->type == DMUB_NOTIFICATION_HPD)
 731                                 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 732                         else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 733                                 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
 734                         else
 735                                 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
 736                                                 notify->type, link_index);
 737
 738                         hpd_aconnector = aconnector;
 739                         break;
 740                 }
 741         }
 742         drm_connector_list_iter_end(&iter);
 743
 744         if (hpd_aconnector) {
 745                 if (notify->type == DMUB_NOTIFICATION_HPD)
 746                         handle_hpd_irq_helper(hpd_aconnector);
 747                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 748                         handle_hpd_rx_irq(hpd_aconnector);
 749         }
 750 }
 751
 752 /**
 753  * register_dmub_notify_callback - Sets callback for DMUB notify
 754  * @adev: amdgpu_device pointer
 755  * @type: Type of dmub notification
 756  * @callback: Dmub interrupt callback function
 757  * @dmub_int_thread_offload: offload indicator
 758  *
 759  * API to register a dmub callback handler for a dmub notification
 760  * Also sets indicator whether callback processing to be offloaded.
 761  * to dmub interrupt handling thread
 762  * Return: true if successfully registered, false if there is existing registration
 763  */
 764 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 765                                           enum dmub_notification_type type,
 766                                           dmub_notify_interrupt_callback_t callback,
 767                                           bool dmub_int_thread_offload)
 768 {
 769         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 770                 adev->dm.dmub_callback[type] = callback;
 771                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 772         } else
 773                 return false;
 774
 775         return true;
 776 }
 777
 778 static void dm_handle_hpd_work(struct work_struct *work)
 779 {
 780         struct dmub_hpd_work *dmub_hpd_wrk;
 781
 782         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 783
 784         if (!dmub_hpd_wrk->dmub_notify) {
 785                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 786                 return;
 787         }
 788
 789         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 790                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 791                 dmub_hpd_wrk->dmub_notify);
 792         }
 793
 794         kfree(dmub_hpd_wrk->dmub_notify);
 795         kfree(dmub_hpd_wrk);
 796
 797 }
 798
 799 #define DMUB_TRACE_MAX_READ 64
 800 /**
 801  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 802  * @interrupt_params: used for determining the Outbox instance
 803  *
 804  * Handles the Outbox Interrupt
 805  * event handler.
 806  */
 807 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 808 {
 809         struct dmub_notification notify;
 810         struct common_irq_params *irq_params = interrupt_params;
 811         struct amdgpu_device *adev = irq_params->adev;
 812         struct amdgpu_display_manager *dm = &adev->dm;
 813         struct dmcub_trace_buf_entry entry = { 0 };
 814         u32 count = 0;
 815         struct dmub_hpd_work *dmub_hpd_wrk;
 816         struct dc_link *plink = NULL;
 817
 818         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 819                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 820
 821                 do {
 822                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 823                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 824                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 825                                 continue;
 826                         }
 827                         if (!dm->dmub_callback[notify.type]) {
 828                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 829                                 continue;
 830                         }
 831                         if (dm->dmub_thread_offload[notify.type] == true) {
 832                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 833                                 if (!dmub_hpd_wrk) {
 834                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 835                                         return;
 836                                 }
 837                                 dmub_hpd_wrk->dmub_notify = kmemdup(&notify, sizeof(struct dmub_notification),
 838                                                                     GFP_ATOMIC);
 839                                 if (!dmub_hpd_wrk->dmub_notify) {
 840                                         kfree(dmub_hpd_wrk);
 841                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 842                                         return;
 843                                 }
 844                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 845                                 dmub_hpd_wrk->adev = adev;
 846                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 847                                         plink = adev->dm.dc->links[notify.link_index];
 848                                         if (plink) {
 849                                                 plink->hpd_status =
 850                                                         notify.hpd_status == DP_HPD_PLUG;
 851                                         }
 852                                 }
 853                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 854                         } else {
 855                                 dm->dmub_callback[notify.type](adev, &notify);
 856                         }
 857                 } while (notify.pending_notification);
 858         }
 859
 860
 861         do {
 862                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 863                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 864                                                         entry.param0, entry.param1);
 865
 866                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 867                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 868                 } else
 869                         break;
 870
 871                 count++;
 872
 873         } while (count <= DMUB_TRACE_MAX_READ);
 874
 875         if (count > DMUB_TRACE_MAX_READ)
 876                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 877 }
 878
 879 static int dm_set_clockgating_state(void *handle,
 880                   enum amd_clockgating_state state)
 881 {
 882         return 0;
 883 }
 884
 885 static int dm_set_powergating_state(void *handle,
 886                   enum amd_powergating_state state)
 887 {
 888         return 0;
 889 }
 890
 891 /* Prototypes of private functions */
 892 static int dm_early_init(void *handle);
 893
 894 /* Allocate memory for FBC compressed data  */
 895 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 896 {
 897         struct drm_device *dev = connector->dev;
 898         struct amdgpu_device *adev = drm_to_adev(dev);
 899         struct dm_compressor_info *compressor = &adev->dm.compressor;
 900         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 901         struct drm_display_mode *mode;
 902         unsigned long max_size = 0;
 903
 904         if (adev->dm.dc->fbc_compressor == NULL)
 905                 return;
 906
 907         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 908                 return;
 909
 910         if (compressor->bo_ptr)
 911                 return;
 912
 913
 914         list_for_each_entry(mode, &connector->modes, head) {
 915                 if (max_size < mode->htotal * mode->vtotal)
 916                         max_size = mode->htotal * mode->vtotal;
 917         }
 918
 919         if (max_size) {
 920                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 921                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 922                             &compressor->gpu_addr, &compressor->cpu_addr);
 923
 924                 if (r)
 925                         DRM_ERROR("DM: Failed to initialize FBC\n");
 926                 else {
 927                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 928                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 929                 }
 930
 931         }
 932
 933 }
 934
 935 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 936                                           int pipe, bool *enabled,
 937                                           unsigned char *buf, int max_bytes)
 938 {
 939         struct drm_device *dev = dev_get_drvdata(kdev);
 940         struct amdgpu_device *adev = drm_to_adev(dev);
 941         struct drm_connector *connector;
 942         struct drm_connector_list_iter conn_iter;
 943         struct amdgpu_dm_connector *aconnector;
 944         int ret = 0;
 945
 946         *enabled = false;
 947
 948         mutex_lock(&adev->dm.audio_lock);
 949
 950         drm_connector_list_iter_begin(dev, &conn_iter);
 951         drm_for_each_connector_iter(connector, &conn_iter) {
 952                 aconnector = to_amdgpu_dm_connector(connector);
 953                 if (aconnector->audio_inst != port)
 954                         continue;
 955
 956                 *enabled = true;
 957                 ret = drm_eld_size(connector->eld);
 958                 memcpy(buf, connector->eld, min(max_bytes, ret));
 959
 960                 break;
 961         }
 962         drm_connector_list_iter_end(&conn_iter);
 963
 964         mutex_unlock(&adev->dm.audio_lock);
 965
 966         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 967
 968         return ret;
 969 }
 970
 971 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 972         .get_eld = amdgpu_dm_audio_component_get_eld,
 973 };
 974
 975 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 976                                        struct device *hda_kdev, void *data)
 977 {
 978         struct drm_device *dev = dev_get_drvdata(kdev);
 979         struct amdgpu_device *adev = drm_to_adev(dev);
 980         struct drm_audio_component *acomp = data;
 981
 982         acomp->ops = &amdgpu_dm_audio_component_ops;
 983         acomp->dev = kdev;
 984         adev->dm.audio_component = acomp;
 985
 986         return 0;
 987 }
 988
 989 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 990                                           struct device *hda_kdev, void *data)
 991 {
 992         struct drm_device *dev = dev_get_drvdata(kdev);
 993         struct amdgpu_device *adev = drm_to_adev(dev);
 994         struct drm_audio_component *acomp = data;
 995
 996         acomp->ops = NULL;
 997         acomp->dev = NULL;
 998         adev->dm.audio_component = NULL;
 999 }
1000
1001 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
1002         .bind   = amdgpu_dm_audio_component_bind,
1003         .unbind = amdgpu_dm_audio_component_unbind,
1004 };
1005
1006 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1007 {
1008         int i, ret;
1009
1010         if (!amdgpu_audio)
1011                 return 0;
1012
1013         adev->mode_info.audio.enabled = true;
1014
1015         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1016
1017         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1018                 adev->mode_info.audio.pin[i].channels = -1;
1019                 adev->mode_info.audio.pin[i].rate = -1;
1020                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1021                 adev->mode_info.audio.pin[i].status_bits = 0;
1022                 adev->mode_info.audio.pin[i].category_code = 0;
1023                 adev->mode_info.audio.pin[i].connected = false;
1024                 adev->mode_info.audio.pin[i].id =
1025                         adev->dm.dc->res_pool->audios[i]->inst;
1026                 adev->mode_info.audio.pin[i].offset = 0;
1027         }
1028
1029         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1030         if (ret < 0)
1031                 return ret;
1032
1033         adev->dm.audio_registered = true;
1034
1035         return 0;
1036 }
1037
1038 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1039 {
1040         if (!amdgpu_audio)
1041                 return;
1042
1043         if (!adev->mode_info.audio.enabled)
1044                 return;
1045
1046         if (adev->dm.audio_registered) {
1047                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1048                 adev->dm.audio_registered = false;
1049         }
1050
1051         /* TODO: Disable audio? */
1052
1053         adev->mode_info.audio.enabled = false;
1054 }
1055
1056 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1057 {
1058         struct drm_audio_component *acomp = adev->dm.audio_component;
1059
1060         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1061                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1062
1063                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1064                                                  pin, -1);
1065         }
1066 }
1067
1068 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1069 {
1070         const struct dmcub_firmware_header_v1_0 *hdr;
1071         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1072         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1073         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1074         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1075         struct abm *abm = adev->dm.dc->res_pool->abm;
1076         struct dc_context *ctx = adev->dm.dc->ctx;
1077         struct dmub_srv_hw_params hw_params;
1078         enum dmub_status status;
1079         const unsigned char *fw_inst_const, *fw_bss_data;
1080         u32 i, fw_inst_const_size, fw_bss_data_size;
1081         bool has_hw_support;
1082
1083         if (!dmub_srv)
1084                 /* DMUB isn't supported on the ASIC. */
1085                 return 0;
1086
1087         if (!fb_info) {
1088                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1089                 return -EINVAL;
1090         }
1091
1092         if (!dmub_fw) {
1093                 /* Firmware required for DMUB support. */
1094                 DRM_ERROR("No firmware provided for DMUB.\n");
1095                 return -EINVAL;
1096         }
1097
1098         /* initialize register offsets for ASICs with runtime initialization available */
1099         if (dmub_srv->hw_funcs.init_reg_offsets)
1100                 dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx);
1101
1102         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1103         if (status != DMUB_STATUS_OK) {
1104                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1105                 return -EINVAL;
1106         }
1107
1108         if (!has_hw_support) {
1109                 DRM_INFO("DMUB unsupported on ASIC\n");
1110                 return 0;
1111         }
1112
1113         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1114         status = dmub_srv_hw_reset(dmub_srv);
1115         if (status != DMUB_STATUS_OK)
1116                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1117
1118         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1119
1120         fw_inst_const = dmub_fw->data +
1121                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1122                         PSP_HEADER_BYTES;
1123
1124         fw_bss_data = dmub_fw->data +
1125                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1126                       le32_to_cpu(hdr->inst_const_bytes);
1127
1128         /* Copy firmware and bios info into FB memory. */
1129         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1130                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1131
1132         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1133
1134         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1135          * amdgpu_ucode_init_single_fw will load dmub firmware
1136          * fw_inst_const part to cw0; otherwise, the firmware back door load
1137          * will be done by dm_dmub_hw_init
1138          */
1139         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1140                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1141                                 fw_inst_const_size);
1142         }
1143
1144         if (fw_bss_data_size)
1145                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1146                        fw_bss_data, fw_bss_data_size);
1147
1148         /* Copy firmware bios info into FB memory. */
1149         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1150                adev->bios_size);
1151
1152         /* Reset regions that need to be reset. */
1153         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1154         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1155
1156         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1157                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1158
1159         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1160                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1161
1162         /* Initialize hardware. */
1163         memset(&hw_params, 0, sizeof(hw_params));
1164         hw_params.fb_base = adev->gmc.fb_start;
1165         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1166
1167         /* backdoor load firmware and trigger dmub running */
1168         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1169                 hw_params.load_inst_const = true;
1170
1171         if (dmcu)
1172                 hw_params.psp_version = dmcu->psp_version;
1173
1174         for (i = 0; i < fb_info->num_fb; ++i)
1175                 hw_params.fb[i] = &fb_info->fb[i];
1176
1177         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1178         case IP_VERSION(3, 1, 3):
1179         case IP_VERSION(3, 1, 4):
1180         case IP_VERSION(3, 5, 0):
1181                 hw_params.dpia_supported = true;
1182                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1183                 break;
1184         default:
1185                 break;
1186         }
1187
1188         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1189         if (status != DMUB_STATUS_OK) {
1190                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1191                 return -EINVAL;
1192         }
1193
1194         /* Wait for firmware load to finish. */
1195         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1196         if (status != DMUB_STATUS_OK)
1197                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1198
1199         /* Init DMCU and ABM if available. */
1200         if (dmcu && abm) {
1201                 dmcu->funcs->dmcu_init(dmcu);
1202                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1203         }
1204
1205         if (!adev->dm.dc->ctx->dmub_srv)
1206                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1207         if (!adev->dm.dc->ctx->dmub_srv) {
1208                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1209                 return -ENOMEM;
1210         }
1211
1212         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1213                  adev->dm.dmcub_fw_version);
1214
1215         return 0;
1216 }
1217
1218 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1219 {
1220         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1221         enum dmub_status status;
1222         bool init;
1223
1224         if (!dmub_srv) {
1225                 /* DMUB isn't supported on the ASIC. */
1226                 return;
1227         }
1228
1229         status = dmub_srv_is_hw_init(dmub_srv, &init);
1230         if (status != DMUB_STATUS_OK)
1231                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1232
1233         if (status == DMUB_STATUS_OK && init) {
1234                 /* Wait for firmware load to finish. */
1235                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1236                 if (status != DMUB_STATUS_OK)
1237                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1238         } else {
1239                 /* Perform the full hardware initialization. */
1240                 dm_dmub_hw_init(adev);
1241         }
1242 }
1243
1244 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1245 {
1246         u64 pt_base;
1247         u32 logical_addr_low;
1248         u32 logical_addr_high;
1249         u32 agp_base, agp_bot, agp_top;
1250         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1251
1252         memset(pa_config, 0, sizeof(*pa_config));
1253
1254         agp_base = 0;
1255         agp_bot = adev->gmc.agp_start >> 24;
1256         agp_top = adev->gmc.agp_end >> 24;
1257
1258         /* AGP aperture is disabled */
1259         if (agp_bot > agp_top) {
1260                 logical_addr_low = adev->gmc.fb_start >> 18;
1261                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1262                         /*
1263                          * Raven2 has a HW issue that it is unable to use the vram which
1264                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1265                          * workaround that increase system aperture high address (add 1)
1266                          * to get rid of the VM fault and hardware hang.
1267                          */
1268                         logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1269                 else
1270                         logical_addr_high = adev->gmc.fb_end >> 18;
1271         } else {
1272                 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1273                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1274                         /*
1275                          * Raven2 has a HW issue that it is unable to use the vram which
1276                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1277                          * workaround that increase system aperture high address (add 1)
1278                          * to get rid of the VM fault and hardware hang.
1279                          */
1280                         logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1281                 else
1282                         logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1283         }
1284
1285         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1286
1287         page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>
1288                                                    AMDGPU_GPU_PAGE_SHIFT);
1289         page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>
1290                                                   AMDGPU_GPU_PAGE_SHIFT);
1291         page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>
1292                                                  AMDGPU_GPU_PAGE_SHIFT);
1293         page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>
1294                                                 AMDGPU_GPU_PAGE_SHIFT);
1295         page_table_base.high_part = upper_32_bits(pt_base);
1296         page_table_base.low_part = lower_32_bits(pt_base);
1297
1298         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1299         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1300
1301         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24;
1302         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1303         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1304
1305         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1306         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1307         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1308
1309         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1310         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1311         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1312
1313         pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1314
1315 }
1316
1317 static void force_connector_state(
1318         struct amdgpu_dm_connector *aconnector,
1319         enum drm_connector_force force_state)
1320 {
1321         struct drm_connector *connector = &aconnector->base;
1322
1323         mutex_lock(&connector->dev->mode_config.mutex);
1324         aconnector->base.force = force_state;
1325         mutex_unlock(&connector->dev->mode_config.mutex);
1326
1327         mutex_lock(&aconnector->hpd_lock);
1328         drm_kms_helper_connector_hotplug_event(connector);
1329         mutex_unlock(&aconnector->hpd_lock);
1330 }
1331
1332 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1333 {
1334         struct hpd_rx_irq_offload_work *offload_work;
1335         struct amdgpu_dm_connector *aconnector;
1336         struct dc_link *dc_link;
1337         struct amdgpu_device *adev;
1338         enum dc_connection_type new_connection_type = dc_connection_none;
1339         unsigned long flags;
1340         union test_response test_response;
1341
1342         memset(&test_response, 0, sizeof(test_response));
1343
1344         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1345         aconnector = offload_work->offload_wq->aconnector;
1346
1347         if (!aconnector) {
1348                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1349                 goto skip;
1350         }
1351
1352         adev = drm_to_adev(aconnector->base.dev);
1353         dc_link = aconnector->dc_link;
1354
1355         mutex_lock(&aconnector->hpd_lock);
1356         if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1357                 DRM_ERROR("KMS: Failed to detect connector\n");
1358         mutex_unlock(&aconnector->hpd_lock);
1359
1360         if (new_connection_type == dc_connection_none)
1361                 goto skip;
1362
1363         if (amdgpu_in_reset(adev))
1364                 goto skip;
1365
1366         if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
1367                 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
1368                 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT);
1369                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1370                 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false;
1371                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1372                 goto skip;
1373         }
1374
1375         mutex_lock(&adev->dm.dc_lock);
1376         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1377                 dc_link_dp_handle_automated_test(dc_link);
1378
1379                 if (aconnector->timing_changed) {
1380                         /* force connector disconnect and reconnect */
1381                         force_connector_state(aconnector, DRM_FORCE_OFF);
1382                         msleep(100);
1383                         force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1384                 }
1385
1386                 test_response.bits.ACK = 1;
1387
1388                 core_link_write_dpcd(
1389                 dc_link,
1390                 DP_TEST_RESPONSE,
1391                 &test_response.raw,
1392                 sizeof(test_response));
1393         } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1394                         dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1395                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1396                 /* offload_work->data is from handle_hpd_rx_irq->
1397                  * schedule_hpd_rx_offload_work.this is defer handle
1398                  * for hpd short pulse. upon here, link status may be
1399                  * changed, need get latest link status from dpcd
1400                  * registers. if link status is good, skip run link
1401                  * training again.
1402                  */
1403                 union hpd_irq_data irq_data;
1404
1405                 memset(&irq_data, 0, sizeof(irq_data));
1406
1407                 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1408                  * request be added to work queue if link lost at end of dc_link_
1409                  * dp_handle_link_loss
1410                  */
1411                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1412                 offload_work->offload_wq->is_handling_link_loss = false;
1413                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1414
1415                 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1416                         dc_link_check_link_loss_status(dc_link, &irq_data))
1417                         dc_link_dp_handle_link_loss(dc_link);
1418         }
1419         mutex_unlock(&adev->dm.dc_lock);
1420
1421 skip:
1422         kfree(offload_work);
1423
1424 }
1425
1426 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1427 {
1428         int max_caps = dc->caps.max_links;
1429         int i = 0;
1430         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1431
1432         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1433
1434         if (!hpd_rx_offload_wq)
1435                 return NULL;
1436
1437
1438         for (i = 0; i < max_caps; i++) {
1439                 hpd_rx_offload_wq[i].wq =
1440                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1441
1442                 if (hpd_rx_offload_wq[i].wq == NULL) {
1443                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1444                         goto out_err;
1445                 }
1446
1447                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1448         }
1449
1450         return hpd_rx_offload_wq;
1451
1452 out_err:
1453         for (i = 0; i < max_caps; i++) {
1454                 if (hpd_rx_offload_wq[i].wq)
1455                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1456         }
1457         kfree(hpd_rx_offload_wq);
1458         return NULL;
1459 }
1460
1461 struct amdgpu_stutter_quirk {
1462         u16 chip_vendor;
1463         u16 chip_device;
1464         u16 subsys_vendor;
1465         u16 subsys_device;
1466         u8 revision;
1467 };
1468
1469 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1470         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1471         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1472         { 0, 0, 0, 0, 0 },
1473 };
1474
1475 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1476 {
1477         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1478
1479         while (p && p->chip_device != 0) {
1480                 if (pdev->vendor == p->chip_vendor &&
1481                     pdev->device == p->chip_device &&
1482                     pdev->subsystem_vendor == p->subsys_vendor &&
1483                     pdev->subsystem_device == p->subsys_device &&
1484                     pdev->revision == p->revision) {
1485                         return true;
1486                 }
1487                 ++p;
1488         }
1489         return false;
1490 }
1491
1492 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1493         {
1494                 .matches = {
1495                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1496                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1497                 },
1498         },
1499         {
1500                 .matches = {
1501                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1502                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1503                 },
1504         },
1505         {
1506                 .matches = {
1507                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1508                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1509                 },
1510         },
1511         {
1512                 .matches = {
1513                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1514                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1515                 },
1516         },
1517         {
1518                 .matches = {
1519                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1520                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1521                 },
1522         },
1523         {
1524                 .matches = {
1525                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1526                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1527                 },
1528         },
1529         {
1530                 .matches = {
1531                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1532                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1533                 },
1534         },
1535         {
1536                 .matches = {
1537                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1538                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1539                 },
1540         },
1541         {
1542                 .matches = {
1543                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1544                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1545                 },
1546         },
1547         {}
1548         /* TODO: refactor this from a fixed table to a dynamic option */
1549 };
1550
1551 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1552 {
1553         const struct dmi_system_id *dmi_id;
1554
1555         dm->aux_hpd_discon_quirk = false;
1556
1557         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1558         if (dmi_id) {
1559                 dm->aux_hpd_discon_quirk = true;
1560                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1561         }
1562 }
1563
1564 static int amdgpu_dm_init(struct amdgpu_device *adev)
1565 {
1566         struct dc_init_data init_data;
1567         struct dc_callback_init init_params;
1568         int r;
1569
1570         adev->dm.ddev = adev_to_drm(adev);
1571         adev->dm.adev = adev;
1572
1573         /* Zero all the fields */
1574         memset(&init_data, 0, sizeof(init_data));
1575         memset(&init_params, 0, sizeof(init_params));
1576
1577         mutex_init(&adev->dm.dpia_aux_lock);
1578         mutex_init(&adev->dm.dc_lock);
1579         mutex_init(&adev->dm.audio_lock);
1580
1581         if (amdgpu_dm_irq_init(adev)) {
1582                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1583                 goto error;
1584         }
1585
1586         init_data.asic_id.chip_family = adev->family;
1587
1588         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1589         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1590         init_data.asic_id.chip_id = adev->pdev->device;
1591
1592         init_data.asic_id.vram_width = adev->gmc.vram_width;
1593         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1594         init_data.asic_id.atombios_base_address =
1595                 adev->mode_info.atom_context->bios;
1596
1597         init_data.driver = adev;
1598
1599         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1600
1601         if (!adev->dm.cgs_device) {
1602                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1603                 goto error;
1604         }
1605
1606         init_data.cgs_device = adev->dm.cgs_device;
1607
1608         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1609
1610         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1611         case IP_VERSION(2, 1, 0):
1612                 switch (adev->dm.dmcub_fw_version) {
1613                 case 0: /* development */
1614                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1615                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1616                         init_data.flags.disable_dmcu = false;
1617                         break;
1618                 default:
1619                         init_data.flags.disable_dmcu = true;
1620                 }
1621                 break;
1622         case IP_VERSION(2, 0, 3):
1623                 init_data.flags.disable_dmcu = true;
1624                 break;
1625         default:
1626                 break;
1627         }
1628
1629         /* APU support S/G display by default except:
1630          * ASICs before Carrizo,
1631          * RAVEN1 (Users reported stability issue)
1632          */
1633
1634         if (adev->asic_type < CHIP_CARRIZO) {
1635                 init_data.flags.gpu_vm_support = false;
1636         } else if (adev->asic_type == CHIP_RAVEN) {
1637                 if (adev->apu_flags & AMD_APU_IS_RAVEN)
1638                         init_data.flags.gpu_vm_support = false;
1639                 else
1640                         init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0);
1641         } else {
1642                 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU);
1643         }
1644
1645         init_data.flags.gpu_vm_support = adev->mode_info.gpu_vm_support;
1646
1647         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1648                 init_data.flags.fbc_support = true;
1649
1650         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1651                 init_data.flags.multi_mon_pp_mclk_switch = true;
1652
1653         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1654                 init_data.flags.disable_fractional_pwm = true;
1655
1656         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1657                 init_data.flags.edp_no_power_sequencing = true;
1658
1659         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1660                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1661         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1662                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1663
1664         init_data.flags.seamless_boot_edp_requested = false;
1665
1666         if (amdgpu_device_seamless_boot_supported(adev)) {
1667                 init_data.flags.seamless_boot_edp_requested = true;
1668                 init_data.flags.allow_seamless_boot_optimization = true;
1669                 DRM_INFO("Seamless boot condition check passed\n");
1670         }
1671
1672         init_data.flags.enable_mipi_converter_optimization = true;
1673
1674         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1675         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1676         init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];
1677
1678         INIT_LIST_HEAD(&adev->dm.da_list);
1679
1680         retrieve_dmi_info(&adev->dm);
1681
1682         /* Display Core create. */
1683         adev->dm.dc = dc_create(&init_data);
1684
1685         if (adev->dm.dc) {
1686                 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,
1687                          dce_version_to_string(adev->dm.dc->ctx->dce_version));
1688         } else {
1689                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1690                 goto error;
1691         }
1692
1693         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1694                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1695                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1696         }
1697
1698         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1699                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1700         if (dm_should_disable_stutter(adev->pdev))
1701                 adev->dm.dc->debug.disable_stutter = true;
1702
1703         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1704                 adev->dm.dc->debug.disable_stutter = true;
1705
1706         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1707                 adev->dm.dc->debug.disable_dsc = true;
1708
1709         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1710                 adev->dm.dc->debug.disable_clock_gate = true;
1711
1712         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1713                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1714
1715         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1716
1717         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1718         adev->dm.dc->debug.ignore_cable_id = true;
1719
1720         /* TODO: There is a new drm mst change where the freedom of
1721          * vc_next_start_slot update is revoked/moved into drm, instead of in
1722          * driver. This forces us to make sure to get vc_next_start_slot updated
1723          * in drm function each time without considering if mst_state is active
1724          * or not. Otherwise, next time hotplug will give wrong start_slot
1725          * number. We are implementing a temporary solution to even notify drm
1726          * mst deallocation when link is no longer of MST type when uncommitting
1727          * the stream so we will have more time to work on a proper solution.
1728          * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1729          * should notify drm to do a complete "reset" of its states and stop
1730          * calling further drm mst functions when link is no longer of an MST
1731          * type. This could happen when we unplug an MST hubs/displays. When
1732          * uncommit stream comes later after unplug, we should just reset
1733          * hardware states only.
1734          */
1735         adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1736
1737         if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1738                 DRM_INFO("DP-HDMI FRL PCON supported\n");
1739
1740         r = dm_dmub_hw_init(adev);
1741         if (r) {
1742                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1743                 goto error;
1744         }
1745
1746         dc_hardware_init(adev->dm.dc);
1747
1748         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1749         if (!adev->dm.hpd_rx_offload_wq) {
1750                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1751                 goto error;
1752         }
1753
1754         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1755                 struct dc_phy_addr_space_config pa_config;
1756
1757                 mmhub_read_system_context(adev, &pa_config);
1758
1759                 // Call the DC init_memory func
1760                 dc_setup_system_context(adev->dm.dc, &pa_config);
1761         }
1762
1763         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1764         if (!adev->dm.freesync_module) {
1765                 DRM_ERROR(
1766                 "amdgpu: failed to initialize freesync_module.\n");
1767         } else
1768                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1769                                 adev->dm.freesync_module);
1770
1771         amdgpu_dm_init_color_mod();
1772
1773         if (adev->dm.dc->caps.max_links > 0) {
1774                 adev->dm.vblank_control_workqueue =
1775                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1776                 if (!adev->dm.vblank_control_workqueue)
1777                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1778         }
1779
1780         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1781                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1782
1783                 if (!adev->dm.hdcp_workqueue)
1784                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1785                 else
1786                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1787
1788                 dc_init_callbacks(adev->dm.dc, &init_params);
1789         }
1790         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1791                 init_completion(&adev->dm.dmub_aux_transfer_done);
1792                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1793                 if (!adev->dm.dmub_notify) {
1794                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1795                         goto error;
1796                 }
1797
1798                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1799                 if (!adev->dm.delayed_hpd_wq) {
1800                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1801                         goto error;
1802                 }
1803
1804                 amdgpu_dm_outbox_init(adev);
1805                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1806                         dmub_aux_setconfig_callback, false)) {
1807                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1808                         goto error;
1809                 }
1810                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1811                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1812                         goto error;
1813                 }
1814                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1815                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1816                         goto error;
1817                 }
1818         }
1819
1820         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1821          * It is expected that DMUB will resend any pending notifications at this point, for
1822          * example HPD from DPIA.
1823          */
1824         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1825                 dc_enable_dmub_outbox(adev->dm.dc);
1826
1827                 /* DPIA trace goes to dmesg logs only if outbox is enabled */
1828                 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE)
1829                         dc_dmub_srv_enable_dpia_trace(adev->dm.dc);
1830         }
1831
1832         if (amdgpu_dm_initialize_drm_device(adev)) {
1833                 DRM_ERROR(
1834                 "amdgpu: failed to initialize sw for display support.\n");
1835                 goto error;
1836         }
1837
1838         /* create fake encoders for MST */
1839         dm_dp_create_fake_mst_encoders(adev);
1840
1841         /* TODO: Add_display_info? */
1842
1843         /* TODO use dynamic cursor width */
1844         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1845         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1846
1847         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1848                 DRM_ERROR(
1849                 "amdgpu: failed to initialize sw for display support.\n");
1850                 goto error;
1851         }
1852
1853 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1854         adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1855         if (!adev->dm.secure_display_ctxs)
1856                 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");
1857 #endif
1858
1859         DRM_DEBUG_DRIVER("KMS initialized.\n");
1860
1861         return 0;
1862 error:
1863         amdgpu_dm_fini(adev);
1864
1865         return -EINVAL;
1866 }
1867
1868 static int amdgpu_dm_early_fini(void *handle)
1869 {
1870         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1871
1872         amdgpu_dm_audio_fini(adev);
1873
1874         return 0;
1875 }
1876
1877 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1878 {
1879         int i;
1880
1881         if (adev->dm.vblank_control_workqueue) {
1882                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1883                 adev->dm.vblank_control_workqueue = NULL;
1884         }
1885
1886         amdgpu_dm_destroy_drm_device(&adev->dm);
1887
1888 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1889         if (adev->dm.secure_display_ctxs) {
1890                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1891                         if (adev->dm.secure_display_ctxs[i].crtc) {
1892                                 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1893                                 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1894                         }
1895                 }
1896                 kfree(adev->dm.secure_display_ctxs);
1897                 adev->dm.secure_display_ctxs = NULL;
1898         }
1899 #endif
1900         if (adev->dm.hdcp_workqueue) {
1901                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1902                 adev->dm.hdcp_workqueue = NULL;
1903         }
1904
1905         if (adev->dm.dc)
1906                 dc_deinit_callbacks(adev->dm.dc);
1907
1908         if (adev->dm.dc)
1909                 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1910
1911         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1912                 kfree(adev->dm.dmub_notify);
1913                 adev->dm.dmub_notify = NULL;
1914                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1915                 adev->dm.delayed_hpd_wq = NULL;
1916         }
1917
1918         if (adev->dm.dmub_bo)
1919                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1920                                       &adev->dm.dmub_bo_gpu_addr,
1921                                       &adev->dm.dmub_bo_cpu_addr);
1922
1923         if (adev->dm.hpd_rx_offload_wq) {
1924                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1925                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1926                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1927                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1928                         }
1929                 }
1930
1931                 kfree(adev->dm.hpd_rx_offload_wq);
1932                 adev->dm.hpd_rx_offload_wq = NULL;
1933         }
1934
1935         /* DC Destroy TODO: Replace destroy DAL */
1936         if (adev->dm.dc)
1937                 dc_destroy(&adev->dm.dc);
1938         /*
1939          * TODO: pageflip, vlank interrupt
1940          *
1941          * amdgpu_dm_irq_fini(adev);
1942          */
1943
1944         if (adev->dm.cgs_device) {
1945                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1946                 adev->dm.cgs_device = NULL;
1947         }
1948         if (adev->dm.freesync_module) {
1949                 mod_freesync_destroy(adev->dm.freesync_module);
1950                 adev->dm.freesync_module = NULL;
1951         }
1952
1953         mutex_destroy(&adev->dm.audio_lock);
1954         mutex_destroy(&adev->dm.dc_lock);
1955         mutex_destroy(&adev->dm.dpia_aux_lock);
1956 }
1957
1958 static int load_dmcu_fw(struct amdgpu_device *adev)
1959 {
1960         const char *fw_name_dmcu = NULL;
1961         int r;
1962         const struct dmcu_firmware_header_v1_0 *hdr;
1963
1964         switch (adev->asic_type) {
1965 #if defined(CONFIG_DRM_AMD_DC_SI)
1966         case CHIP_TAHITI:
1967         case CHIP_PITCAIRN:
1968         case CHIP_VERDE:
1969         case CHIP_OLAND:
1970 #endif
1971         case CHIP_BONAIRE:
1972         case CHIP_HAWAII:
1973         case CHIP_KAVERI:
1974         case CHIP_KABINI:
1975         case CHIP_MULLINS:
1976         case CHIP_TONGA:
1977         case CHIP_FIJI:
1978         case CHIP_CARRIZO:
1979         case CHIP_STONEY:
1980         case CHIP_POLARIS11:
1981         case CHIP_POLARIS10:
1982         case CHIP_POLARIS12:
1983         case CHIP_VEGAM:
1984         case CHIP_VEGA10:
1985         case CHIP_VEGA12:
1986         case CHIP_VEGA20:
1987                 return 0;
1988         case CHIP_NAVI12:
1989                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1990                 break;
1991         case CHIP_RAVEN:
1992                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1993                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1994                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1995                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1996                 else
1997                         return 0;
1998                 break;
1999         default:
2000                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2001                 case IP_VERSION(2, 0, 2):
2002                 case IP_VERSION(2, 0, 3):
2003                 case IP_VERSION(2, 0, 0):
2004                 case IP_VERSION(2, 1, 0):
2005                 case IP_VERSION(3, 0, 0):
2006                 case IP_VERSION(3, 0, 2):
2007                 case IP_VERSION(3, 0, 3):
2008                 case IP_VERSION(3, 0, 1):
2009                 case IP_VERSION(3, 1, 2):
2010                 case IP_VERSION(3, 1, 3):
2011                 case IP_VERSION(3, 1, 4):
2012                 case IP_VERSION(3, 1, 5):
2013                 case IP_VERSION(3, 1, 6):
2014                 case IP_VERSION(3, 2, 0):
2015                 case IP_VERSION(3, 2, 1):
2016                 case IP_VERSION(3, 5, 0):
2017                         return 0;
2018                 default:
2019                         break;
2020                 }
2021                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2022                 return -EINVAL;
2023         }
2024
2025         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2026                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2027                 return 0;
2028         }
2029
2030         r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2031         if (r == -ENODEV) {
2032                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2033                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2034                 adev->dm.fw_dmcu = NULL;
2035                 return 0;
2036         }
2037         if (r) {
2038                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2039                         fw_name_dmcu);
2040                 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2041                 return r;
2042         }
2043
2044         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2045         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2046         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2047         adev->firmware.fw_size +=
2048                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2049
2050         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2051         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2052         adev->firmware.fw_size +=
2053                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2054
2055         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2056
2057         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2058
2059         return 0;
2060 }
2061
2062 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2063 {
2064         struct amdgpu_device *adev = ctx;
2065
2066         return dm_read_reg(adev->dm.dc->ctx, address);
2067 }
2068
2069 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2070                                      uint32_t value)
2071 {
2072         struct amdgpu_device *adev = ctx;
2073
2074         return dm_write_reg(adev->dm.dc->ctx, address, value);
2075 }
2076
2077 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2078 {
2079         struct dmub_srv_create_params create_params;
2080         struct dmub_srv_region_params region_params;
2081         struct dmub_srv_region_info region_info;
2082         struct dmub_srv_fb_params fb_params;
2083         struct dmub_srv_fb_info *fb_info;
2084         struct dmub_srv *dmub_srv;
2085         const struct dmcub_firmware_header_v1_0 *hdr;
2086         enum dmub_asic dmub_asic;
2087         enum dmub_status status;
2088         int r;
2089
2090         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2091         case IP_VERSION(2, 1, 0):
2092                 dmub_asic = DMUB_ASIC_DCN21;
2093                 break;
2094         case IP_VERSION(3, 0, 0):
2095                 dmub_asic = DMUB_ASIC_DCN30;
2096                 break;
2097         case IP_VERSION(3, 0, 1):
2098                 dmub_asic = DMUB_ASIC_DCN301;
2099                 break;
2100         case IP_VERSION(3, 0, 2):
2101                 dmub_asic = DMUB_ASIC_DCN302;
2102                 break;
2103         case IP_VERSION(3, 0, 3):
2104                 dmub_asic = DMUB_ASIC_DCN303;
2105                 break;
2106         case IP_VERSION(3, 1, 2):
2107         case IP_VERSION(3, 1, 3):
2108                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2109                 break;
2110         case IP_VERSION(3, 1, 4):
2111                 dmub_asic = DMUB_ASIC_DCN314;
2112                 break;
2113         case IP_VERSION(3, 1, 5):
2114                 dmub_asic = DMUB_ASIC_DCN315;
2115                 break;
2116         case IP_VERSION(3, 1, 6):
2117                 dmub_asic = DMUB_ASIC_DCN316;
2118                 break;
2119         case IP_VERSION(3, 2, 0):
2120                 dmub_asic = DMUB_ASIC_DCN32;
2121                 break;
2122         case IP_VERSION(3, 2, 1):
2123                 dmub_asic = DMUB_ASIC_DCN321;
2124                 break;
2125         case IP_VERSION(3, 5, 0):
2126                 dmub_asic = DMUB_ASIC_DCN35;
2127                 break;
2128         default:
2129                 /* ASIC doesn't support DMUB. */
2130                 return 0;
2131         }
2132
2133         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2134         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2135
2136         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2137                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2138                         AMDGPU_UCODE_ID_DMCUB;
2139                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2140                         adev->dm.dmub_fw;
2141                 adev->firmware.fw_size +=
2142                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2143
2144                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2145                          adev->dm.dmcub_fw_version);
2146         }
2147
2148
2149         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2150         dmub_srv = adev->dm.dmub_srv;
2151
2152         if (!dmub_srv) {
2153                 DRM_ERROR("Failed to allocate DMUB service!\n");
2154                 return -ENOMEM;
2155         }
2156
2157         memset(&create_params, 0, sizeof(create_params));
2158         create_params.user_ctx = adev;
2159         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2160         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2161         create_params.asic = dmub_asic;
2162
2163         /* Create the DMUB service. */
2164         status = dmub_srv_create(dmub_srv, &create_params);
2165         if (status != DMUB_STATUS_OK) {
2166                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2167                 return -EINVAL;
2168         }
2169
2170         /* Calculate the size of all the regions for the DMUB service. */
2171         memset(&region_params, 0, sizeof(region_params));
2172
2173         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2174                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2175         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2176         region_params.vbios_size = adev->bios_size;
2177         region_params.fw_bss_data = region_params.bss_data_size ?
2178                 adev->dm.dmub_fw->data +
2179                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2180                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2181         region_params.fw_inst_const =
2182                 adev->dm.dmub_fw->data +
2183                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2184                 PSP_HEADER_BYTES;
2185
2186         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2187                                            &region_info);
2188
2189         if (status != DMUB_STATUS_OK) {
2190                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2191                 return -EINVAL;
2192         }
2193
2194         /*
2195          * Allocate a framebuffer based on the total size of all the regions.
2196          * TODO: Move this into GART.
2197          */
2198         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2199                                     AMDGPU_GEM_DOMAIN_VRAM |
2200                                     AMDGPU_GEM_DOMAIN_GTT,
2201                                     &adev->dm.dmub_bo,
2202                                     &adev->dm.dmub_bo_gpu_addr,
2203                                     &adev->dm.dmub_bo_cpu_addr);
2204         if (r)
2205                 return r;
2206
2207         /* Rebase the regions on the framebuffer address. */
2208         memset(&fb_params, 0, sizeof(fb_params));
2209         fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2210         fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2211         fb_params.region_info = &region_info;
2212
2213         adev->dm.dmub_fb_info =
2214                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2215         fb_info = adev->dm.dmub_fb_info;
2216
2217         if (!fb_info) {
2218                 DRM_ERROR(
2219                         "Failed to allocate framebuffer info for DMUB service!\n");
2220                 return -ENOMEM;
2221         }
2222
2223         status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2224         if (status != DMUB_STATUS_OK) {
2225                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2226                 return -EINVAL;
2227         }
2228
2229         return 0;
2230 }
2231
2232 static int dm_sw_init(void *handle)
2233 {
2234         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2235         int r;
2236
2237         r = dm_dmub_sw_init(adev);
2238         if (r)
2239                 return r;
2240
2241         return load_dmcu_fw(adev);
2242 }
2243
2244 static int dm_sw_fini(void *handle)
2245 {
2246         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2247
2248         kfree(adev->dm.dmub_fb_info);
2249         adev->dm.dmub_fb_info = NULL;
2250
2251         if (adev->dm.dmub_srv) {
2252                 dmub_srv_destroy(adev->dm.dmub_srv);
2253                 adev->dm.dmub_srv = NULL;
2254         }
2255
2256         amdgpu_ucode_release(&adev->dm.dmub_fw);
2257         amdgpu_ucode_release(&adev->dm.fw_dmcu);
2258
2259         return 0;
2260 }
2261
2262 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2263 {
2264         struct amdgpu_dm_connector *aconnector;
2265         struct drm_connector *connector;
2266         struct drm_connector_list_iter iter;
2267         int ret = 0;
2268
2269         drm_connector_list_iter_begin(dev, &iter);
2270         drm_for_each_connector_iter(connector, &iter) {
2271                 aconnector = to_amdgpu_dm_connector(connector);
2272                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2273                     aconnector->mst_mgr.aux) {
2274                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2275                                          aconnector,
2276                                          aconnector->base.base.id);
2277
2278                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2279                         if (ret < 0) {
2280                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2281                                 aconnector->dc_link->type =
2282                                         dc_connection_single;
2283                                 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2284                                                                      aconnector->dc_link);
2285                                 break;
2286                         }
2287                 }
2288         }
2289         drm_connector_list_iter_end(&iter);
2290
2291         return ret;
2292 }
2293
2294 static int dm_late_init(void *handle)
2295 {
2296         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2297
2298         struct dmcu_iram_parameters params;
2299         unsigned int linear_lut[16];
2300         int i;
2301         struct dmcu *dmcu = NULL;
2302
2303         dmcu = adev->dm.dc->res_pool->dmcu;
2304
2305         for (i = 0; i < 16; i++)
2306                 linear_lut[i] = 0xFFFF * i / 15;
2307
2308         params.set = 0;
2309         params.backlight_ramping_override = false;
2310         params.backlight_ramping_start = 0xCCCC;
2311         params.backlight_ramping_reduction = 0xCCCCCCCC;
2312         params.backlight_lut_array_size = 16;
2313         params.backlight_lut_array = linear_lut;
2314
2315         /* Min backlight level after ABM reduction,  Don't allow below 1%
2316          * 0xFFFF x 0.01 = 0x28F
2317          */
2318         params.min_abm_backlight = 0x28F;
2319         /* In the case where abm is implemented on dmcub,
2320          * dmcu object will be null.
2321          * ABM 2.4 and up are implemented on dmcub.
2322          */
2323         if (dmcu) {
2324                 if (!dmcu_load_iram(dmcu, params))
2325                         return -EINVAL;
2326         } else if (adev->dm.dc->ctx->dmub_srv) {
2327                 struct dc_link *edp_links[MAX_NUM_EDP];
2328                 int edp_num;
2329
2330                 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2331                 for (i = 0; i < edp_num; i++) {
2332                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2333                                 return -EINVAL;
2334                 }
2335         }
2336
2337         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2338 }
2339
2340 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
2341 {
2342         int ret;
2343         u8 guid[16];
2344         u64 tmp64;
2345
2346         mutex_lock(&mgr->lock);
2347         if (!mgr->mst_primary)
2348                 goto out_fail;
2349
2350         if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {
2351                 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2352                 goto out_fail;
2353         }
2354
2355         ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
2356                                  DP_MST_EN |
2357                                  DP_UP_REQ_EN |
2358                                  DP_UPSTREAM_IS_SRC);
2359         if (ret < 0) {
2360                 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n");
2361                 goto out_fail;
2362         }
2363
2364         /* Some hubs forget their guids after they resume */
2365         ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
2366         if (ret != 16) {
2367                 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2368                 goto out_fail;
2369         }
2370
2371         if (memchr_inv(guid, 0, 16) == NULL) {
2372                 tmp64 = get_jiffies_64();
2373                 memcpy(&guid[0], &tmp64, sizeof(u64));
2374                 memcpy(&guid[8], &tmp64, sizeof(u64));
2375
2376                 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16);
2377
2378                 if (ret != 16) {
2379                         drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n");
2380                         goto out_fail;
2381                 }
2382         }
2383
2384         memcpy(mgr->mst_primary->guid, guid, 16);
2385
2386 out_fail:
2387         mutex_unlock(&mgr->lock);
2388 }
2389
2390 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2391 {
2392         struct amdgpu_dm_connector *aconnector;
2393         struct drm_connector *connector;
2394         struct drm_connector_list_iter iter;
2395         struct drm_dp_mst_topology_mgr *mgr;
2396
2397         drm_connector_list_iter_begin(dev, &iter);
2398         drm_for_each_connector_iter(connector, &iter) {
2399                 aconnector = to_amdgpu_dm_connector(connector);
2400                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2401                     aconnector->mst_root)
2402                         continue;
2403
2404                 mgr = &aconnector->mst_mgr;
2405
2406                 if (suspend) {
2407                         drm_dp_mst_topology_mgr_suspend(mgr);
2408                 } else {
2409                         /* if extended timeout is supported in hardware,
2410                          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2411                          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2412                          */
2413                         try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2414                         if (!dp_is_lttpr_present(aconnector->dc_link))
2415                                 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2416
2417                         /* TODO: move resume_mst_branch_status() into drm mst resume again
2418                          * once topology probing work is pulled out from mst resume into mst
2419                          * resume 2nd step. mst resume 2nd step should be called after old
2420                          * state getting restored (i.e. drm_atomic_helper_resume()).
2421                          */
2422                         resume_mst_branch_status(mgr);
2423                 }
2424         }
2425         drm_connector_list_iter_end(&iter);
2426 }
2427
2428 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2429 {
2430         int ret = 0;
2431
2432         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2433          * on window driver dc implementation.
2434          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2435          * should be passed to smu during boot up and resume from s3.
2436          * boot up: dc calculate dcn watermark clock settings within dc_create,
2437          * dcn20_resource_construct
2438          * then call pplib functions below to pass the settings to smu:
2439          * smu_set_watermarks_for_clock_ranges
2440          * smu_set_watermarks_table
2441          * navi10_set_watermarks_table
2442          * smu_write_watermarks_table
2443          *
2444          * For Renoir, clock settings of dcn watermark are also fixed values.
2445          * dc has implemented different flow for window driver:
2446          * dc_hardware_init / dc_set_power_state
2447          * dcn10_init_hw
2448          * notify_wm_ranges
2449          * set_wm_ranges
2450          * -- Linux
2451          * smu_set_watermarks_for_clock_ranges
2452          * renoir_set_watermarks_table
2453          * smu_write_watermarks_table
2454          *
2455          * For Linux,
2456          * dc_hardware_init -> amdgpu_dm_init
2457          * dc_set_power_state --> dm_resume
2458          *
2459          * therefore, this function apply to navi10/12/14 but not Renoir
2460          * *
2461          */
2462         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2463         case IP_VERSION(2, 0, 2):
2464         case IP_VERSION(2, 0, 0):
2465                 break;
2466         default:
2467                 return 0;
2468         }
2469
2470         ret = amdgpu_dpm_write_watermarks_table(adev);
2471         if (ret) {
2472                 DRM_ERROR("Failed to update WMTABLE!\n");
2473                 return ret;
2474         }
2475
2476         return 0;
2477 }
2478
2479 /**
2480  * dm_hw_init() - Initialize DC device
2481  * @handle: The base driver device containing the amdgpu_dm device.
2482  *
2483  * Initialize the &struct amdgpu_display_manager device. This involves calling
2484  * the initializers of each DM component, then populating the struct with them.
2485  *
2486  * Although the function implies hardware initialization, both hardware and
2487  * software are initialized here. Splitting them out to their relevant init
2488  * hooks is a future TODO item.
2489  *
2490  * Some notable things that are initialized here:
2491  *
2492  * - Display Core, both software and hardware
2493  * - DC modules that we need (freesync and color management)
2494  * - DRM software states
2495  * - Interrupt sources and handlers
2496  * - Vblank support
2497  * - Debug FS entries, if enabled
2498  */
2499 static int dm_hw_init(void *handle)
2500 {
2501         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2502         /* Create DAL display manager */
2503         amdgpu_dm_init(adev);
2504         amdgpu_dm_hpd_init(adev);
2505
2506         return 0;
2507 }
2508
2509 /**
2510  * dm_hw_fini() - Teardown DC device
2511  * @handle: The base driver device containing the amdgpu_dm device.
2512  *
2513  * Teardown components within &struct amdgpu_display_manager that require
2514  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2515  * were loaded. Also flush IRQ workqueues and disable them.
2516  */
2517 static int dm_hw_fini(void *handle)
2518 {
2519         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2520
2521         amdgpu_dm_hpd_fini(adev);
2522
2523         amdgpu_dm_irq_fini(adev);
2524         amdgpu_dm_fini(adev);
2525         return 0;
2526 }
2527
2528
2529 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2530                                  struct dc_state *state, bool enable)
2531 {
2532         enum dc_irq_source irq_source;
2533         struct amdgpu_crtc *acrtc;
2534         int rc = -EBUSY;
2535         int i = 0;
2536
2537         for (i = 0; i < state->stream_count; i++) {
2538                 acrtc = get_crtc_by_otg_inst(
2539                                 adev, state->stream_status[i].primary_otg_inst);
2540
2541                 if (acrtc && state->stream_status[i].plane_count != 0) {
2542                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2543                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2544                         if (rc)
2545                                 DRM_WARN("Failed to %s pflip interrupts\n",
2546                                          enable ? "enable" : "disable");
2547
2548                         if (enable) {
2549                                 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
2550                                         rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
2551                         } else
2552                                 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
2553
2554                         if (rc)
2555                                 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
2556
2557                         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2558                         /* During gpu-reset we disable and then enable vblank irq, so
2559                          * don't use amdgpu_irq_get/put() to avoid refcount change.
2560                          */
2561                         if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
2562                                 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
2563                 }
2564         }
2565
2566 }
2567
2568 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2569 {
2570         struct dc_state *context = NULL;
2571         enum dc_status res = DC_ERROR_UNEXPECTED;
2572         int i;
2573         struct dc_stream_state *del_streams[MAX_PIPES];
2574         int del_streams_count = 0;
2575
2576         memset(del_streams, 0, sizeof(del_streams));
2577
2578         context = dc_create_state(dc);
2579         if (context == NULL)
2580                 goto context_alloc_fail;
2581
2582         dc_resource_state_copy_construct_current(dc, context);
2583
2584         /* First remove from context all streams */
2585         for (i = 0; i < context->stream_count; i++) {
2586                 struct dc_stream_state *stream = context->streams[i];
2587
2588                 del_streams[del_streams_count++] = stream;
2589         }
2590
2591         /* Remove all planes for removed streams and then remove the streams */
2592         for (i = 0; i < del_streams_count; i++) {
2593                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2594                         res = DC_FAIL_DETACH_SURFACES;
2595                         goto fail;
2596                 }
2597
2598                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2599                 if (res != DC_OK)
2600                         goto fail;
2601         }
2602
2603         res = dc_commit_streams(dc, context->streams, context->stream_count);
2604
2605 fail:
2606         dc_release_state(context);
2607
2608 context_alloc_fail:
2609         return res;
2610 }
2611
2612 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2613 {
2614         int i;
2615
2616         if (dm->hpd_rx_offload_wq) {
2617                 for (i = 0; i < dm->dc->caps.max_links; i++)
2618                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2619         }
2620 }
2621
2622 static int dm_suspend(void *handle)
2623 {
2624         struct amdgpu_device *adev = handle;
2625         struct amdgpu_display_manager *dm = &adev->dm;
2626         int ret = 0;
2627
2628         if (amdgpu_in_reset(adev)) {
2629                 mutex_lock(&dm->dc_lock);
2630
2631                 dc_allow_idle_optimizations(adev->dm.dc, false);
2632
2633                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2634
2635                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2636
2637                 amdgpu_dm_commit_zero_streams(dm->dc);
2638
2639                 amdgpu_dm_irq_suspend(adev);
2640
2641                 hpd_rx_irq_work_suspend(dm);
2642
2643                 return ret;
2644         }
2645
2646         WARN_ON(adev->dm.cached_state);
2647         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2648         if (IS_ERR(adev->dm.cached_state))
2649                 return PTR_ERR(adev->dm.cached_state);
2650
2651         s3_handle_mst(adev_to_drm(adev), true);
2652
2653         amdgpu_dm_irq_suspend(adev);
2654
2655         hpd_rx_irq_work_suspend(dm);
2656
2657         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2658
2659         return 0;
2660 }
2661
2662 struct amdgpu_dm_connector *
2663 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2664                                              struct drm_crtc *crtc)
2665 {
2666         u32 i;
2667         struct drm_connector_state *new_con_state;
2668         struct drm_connector *connector;
2669         struct drm_crtc *crtc_from_state;
2670
2671         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2672                 crtc_from_state = new_con_state->crtc;
2673
2674                 if (crtc_from_state == crtc)
2675                         return to_amdgpu_dm_connector(connector);
2676         }
2677
2678         return NULL;
2679 }
2680
2681 static void emulated_link_detect(struct dc_link *link)
2682 {
2683         struct dc_sink_init_data sink_init_data = { 0 };
2684         struct display_sink_capability sink_caps = { 0 };
2685         enum dc_edid_status edid_status;
2686         struct dc_context *dc_ctx = link->ctx;
2687         struct drm_device *dev = adev_to_drm(dc_ctx->driver_context);
2688         struct dc_sink *sink = NULL;
2689         struct dc_sink *prev_sink = NULL;
2690
2691         link->type = dc_connection_none;
2692         prev_sink = link->local_sink;
2693
2694         if (prev_sink)
2695                 dc_sink_release(prev_sink);
2696
2697         switch (link->connector_signal) {
2698         case SIGNAL_TYPE_HDMI_TYPE_A: {
2699                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2700                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2701                 break;
2702         }
2703
2704         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2705                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2706                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2707                 break;
2708         }
2709
2710         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2711                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2712                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2713                 break;
2714         }
2715
2716         case SIGNAL_TYPE_LVDS: {
2717                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2718                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2719                 break;
2720         }
2721
2722         case SIGNAL_TYPE_EDP: {
2723                 sink_caps.transaction_type =
2724                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2725                 sink_caps.signal = SIGNAL_TYPE_EDP;
2726                 break;
2727         }
2728
2729         case SIGNAL_TYPE_DISPLAY_PORT: {
2730                 sink_caps.transaction_type =
2731                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2732                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2733                 break;
2734         }
2735
2736         default:
2737                 drm_err(dev, "Invalid connector type! signal:%d\n",
2738                         link->connector_signal);
2739                 return;
2740         }
2741
2742         sink_init_data.link = link;
2743         sink_init_data.sink_signal = sink_caps.signal;
2744
2745         sink = dc_sink_create(&sink_init_data);
2746         if (!sink) {
2747                 drm_err(dev, "Failed to create sink!\n");
2748                 return;
2749         }
2750
2751         /* dc_sink_create returns a new reference */
2752         link->local_sink = sink;
2753
2754         edid_status = dm_helpers_read_local_edid(
2755                         link->ctx,
2756                         link,
2757                         sink);
2758
2759         if (edid_status != EDID_OK)
2760                 drm_err(dev, "Failed to read EDID\n");
2761
2762 }
2763
2764 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2765                                      struct amdgpu_display_manager *dm)
2766 {
2767         struct {
2768                 struct dc_surface_update surface_updates[MAX_SURFACES];
2769                 struct dc_plane_info plane_infos[MAX_SURFACES];
2770                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2771                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2772                 struct dc_stream_update stream_update;
2773         } *bundle;
2774         int k, m;
2775
2776         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2777
2778         if (!bundle) {
2779                 drm_err(dm->ddev, "Failed to allocate update bundle\n");
2780                 goto cleanup;
2781         }
2782
2783         for (k = 0; k < dc_state->stream_count; k++) {
2784                 bundle->stream_update.stream = dc_state->streams[k];
2785
2786                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2787                         bundle->surface_updates[m].surface =
2788                                 dc_state->stream_status->plane_states[m];
2789                         bundle->surface_updates[m].surface->force_full_update =
2790                                 true;
2791                 }
2792
2793                 update_planes_and_stream_adapter(dm->dc,
2794                                          UPDATE_TYPE_FULL,
2795                                          dc_state->stream_status->plane_count,
2796                                          dc_state->streams[k],
2797                                          &bundle->stream_update,
2798                                          bundle->surface_updates);
2799         }
2800
2801 cleanup:
2802         kfree(bundle);
2803 }
2804
2805 static int dm_resume(void *handle)
2806 {
2807         struct amdgpu_device *adev = handle;
2808         struct drm_device *ddev = adev_to_drm(adev);
2809         struct amdgpu_display_manager *dm = &adev->dm;
2810         struct amdgpu_dm_connector *aconnector;
2811         struct drm_connector *connector;
2812         struct drm_connector_list_iter iter;
2813         struct drm_crtc *crtc;
2814         struct drm_crtc_state *new_crtc_state;
2815         struct dm_crtc_state *dm_new_crtc_state;
2816         struct drm_plane *plane;
2817         struct drm_plane_state *new_plane_state;
2818         struct dm_plane_state *dm_new_plane_state;
2819         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2820         enum dc_connection_type new_connection_type = dc_connection_none;
2821         struct dc_state *dc_state;
2822         int i, r, j, ret;
2823         bool need_hotplug = false;
2824
2825         if (dm->dc->caps.ips_support) {
2826                 dc_dmub_srv_exit_low_power_state(dm->dc);
2827         }
2828
2829         if (amdgpu_in_reset(adev)) {
2830                 dc_state = dm->cached_dc_state;
2831
2832                 /*
2833                  * The dc->current_state is backed up into dm->cached_dc_state
2834                  * before we commit 0 streams.
2835                  *
2836                  * DC will clear link encoder assignments on the real state
2837                  * but the changes won't propagate over to the copy we made
2838                  * before the 0 streams commit.
2839                  *
2840                  * DC expects that link encoder assignments are *not* valid
2841                  * when committing a state, so as a workaround we can copy
2842                  * off of the current state.
2843                  *
2844                  * We lose the previous assignments, but we had already
2845                  * commit 0 streams anyway.
2846                  */
2847                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2848
2849                 r = dm_dmub_hw_init(adev);
2850                 if (r)
2851                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2852
2853                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2854
2855                 dc_resume(dm->dc);
2856
2857                 amdgpu_dm_irq_resume_early(adev);
2858
2859                 for (i = 0; i < dc_state->stream_count; i++) {
2860                         dc_state->streams[i]->mode_changed = true;
2861                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2862                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2863                                         = 0xffffffff;
2864                         }
2865                 }
2866
2867                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2868                         amdgpu_dm_outbox_init(adev);
2869                         dc_enable_dmub_outbox(adev->dm.dc);
2870                 }
2871
2872                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2873
2874                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2875
2876                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2877
2878                 dc_release_state(dm->cached_dc_state);
2879                 dm->cached_dc_state = NULL;
2880
2881                 amdgpu_dm_irq_resume_late(adev);
2882
2883                 mutex_unlock(&dm->dc_lock);
2884
2885                 return 0;
2886         }
2887         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2888         dc_release_state(dm_state->context);
2889         dm_state->context = dc_create_state(dm->dc);
2890         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2891         dc_resource_state_construct(dm->dc, dm_state->context);
2892
2893         /* Before powering on DC we need to re-initialize DMUB. */
2894         dm_dmub_hw_resume(adev);
2895
2896         /* Re-enable outbox interrupts for DPIA. */
2897         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2898                 amdgpu_dm_outbox_init(adev);
2899                 dc_enable_dmub_outbox(adev->dm.dc);
2900         }
2901
2902         /* power on hardware */
2903          dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2904
2905         /* program HPD filter */
2906         dc_resume(dm->dc);
2907
2908         /*
2909          * early enable HPD Rx IRQ, should be done before set mode as short
2910          * pulse interrupts are used for MST
2911          */
2912         amdgpu_dm_irq_resume_early(adev);
2913
2914         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2915         s3_handle_mst(ddev, false);
2916
2917         /* Do detection*/
2918         drm_connector_list_iter_begin(ddev, &iter);
2919         drm_for_each_connector_iter(connector, &iter) {
2920                 aconnector = to_amdgpu_dm_connector(connector);
2921
2922                 if (!aconnector->dc_link)
2923                         continue;
2924
2925                 /*
2926                  * this is the case when traversing through already created end sink
2927                  * MST connectors, should be skipped
2928                  */
2929                 if (aconnector && aconnector->mst_root)
2930                         continue;
2931
2932                 mutex_lock(&aconnector->hpd_lock);
2933                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2934                         DRM_ERROR("KMS: Failed to detect connector\n");
2935
2936                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2937                         emulated_link_detect(aconnector->dc_link);
2938                 } else {
2939                         mutex_lock(&dm->dc_lock);
2940                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2941                         mutex_unlock(&dm->dc_lock);
2942                 }
2943
2944                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2945                         aconnector->fake_enable = false;
2946
2947                 if (aconnector->dc_sink)
2948                         dc_sink_release(aconnector->dc_sink);
2949                 aconnector->dc_sink = NULL;
2950                 amdgpu_dm_update_connector_after_detect(aconnector);
2951                 mutex_unlock(&aconnector->hpd_lock);
2952         }
2953         drm_connector_list_iter_end(&iter);
2954
2955         /* Force mode set in atomic commit */
2956         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2957                 new_crtc_state->active_changed = true;
2958
2959         /*
2960          * atomic_check is expected to create the dc states. We need to release
2961          * them here, since they were duplicated as part of the suspend
2962          * procedure.
2963          */
2964         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2965                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2966                 if (dm_new_crtc_state->stream) {
2967                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2968                         dc_stream_release(dm_new_crtc_state->stream);
2969                         dm_new_crtc_state->stream = NULL;
2970                 }
2971         }
2972
2973         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2974                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2975                 if (dm_new_plane_state->dc_state) {
2976                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2977                         dc_plane_state_release(dm_new_plane_state->dc_state);
2978                         dm_new_plane_state->dc_state = NULL;
2979                 }
2980         }
2981
2982         drm_atomic_helper_resume(ddev, dm->cached_state);
2983
2984         dm->cached_state = NULL;
2985
2986         /* Do mst topology probing after resuming cached state*/
2987         drm_connector_list_iter_begin(ddev, &iter);
2988         drm_for_each_connector_iter(connector, &iter) {
2989                 aconnector = to_amdgpu_dm_connector(connector);
2990                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2991                     aconnector->mst_root)
2992                         continue;
2993
2994                 ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true);
2995
2996                 if (ret < 0) {
2997                         dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2998                                         aconnector->dc_link);
2999                         need_hotplug = true;
3000                 }
3001         }
3002         drm_connector_list_iter_end(&iter);
3003
3004         if (need_hotplug)
3005                 drm_kms_helper_hotplug_event(ddev);
3006
3007         amdgpu_dm_irq_resume_late(adev);
3008
3009         amdgpu_dm_smu_write_watermarks_table(adev);
3010
3011         return 0;
3012 }
3013
3014 /**
3015  * DOC: DM Lifecycle
3016  *
3017  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
3018  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
3019  * the base driver's device list to be initialized and torn down accordingly.
3020  *
3021  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
3022  */
3023
3024 static const struct amd_ip_funcs amdgpu_dm_funcs = {
3025         .name = "dm",
3026         .early_init = dm_early_init,
3027         .late_init = dm_late_init,
3028         .sw_init = dm_sw_init,
3029         .sw_fini = dm_sw_fini,
3030         .early_fini = amdgpu_dm_early_fini,
3031         .hw_init = dm_hw_init,
3032         .hw_fini = dm_hw_fini,
3033         .suspend = dm_suspend,
3034         .resume = dm_resume,
3035         .is_idle = dm_is_idle,
3036         .wait_for_idle = dm_wait_for_idle,
3037         .check_soft_reset = dm_check_soft_reset,
3038         .soft_reset = dm_soft_reset,
3039         .set_clockgating_state = dm_set_clockgating_state,
3040         .set_powergating_state = dm_set_powergating_state,
3041 };
3042
3043 const struct amdgpu_ip_block_version dm_ip_block = {
3044         .type = AMD_IP_BLOCK_TYPE_DCE,
3045         .major = 1,
3046         .minor = 0,
3047         .rev = 0,
3048         .funcs = &amdgpu_dm_funcs,
3049 };
3050
3051
3052 /**
3053  * DOC: atomic
3054  *
3055  * *WIP*
3056  */
3057
3058 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
3059         .fb_create = amdgpu_display_user_framebuffer_create,
3060         .get_format_info = amdgpu_dm_plane_get_format_info,
3061         .atomic_check = amdgpu_dm_atomic_check,
3062         .atomic_commit = drm_atomic_helper_commit,
3063 };
3064
3065 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
3066         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
3067         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
3068 };
3069
3070 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
3071 {
3072         struct amdgpu_dm_backlight_caps *caps;
3073         struct drm_connector *conn_base;
3074         struct amdgpu_device *adev;
3075         struct drm_luminance_range_info *luminance_range;
3076
3077         if (aconnector->bl_idx == -1 ||
3078             aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
3079                 return;
3080
3081         conn_base = &aconnector->base;
3082         adev = drm_to_adev(conn_base->dev);
3083
3084         caps = &adev->dm.backlight_caps[aconnector->bl_idx];
3085         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3086         caps->aux_support = false;
3087
3088         if (caps->ext_caps->bits.oled == 1
3089             /*
3090              * ||
3091              * caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3092              * caps->ext_caps->bits.hdr_aux_backlight_control == 1
3093              */)
3094                 caps->aux_support = true;
3095
3096         if (amdgpu_backlight == 0)
3097                 caps->aux_support = false;
3098         else if (amdgpu_backlight == 1)
3099                 caps->aux_support = true;
3100
3101         luminance_range = &conn_base->display_info.luminance_range;
3102
3103         if (luminance_range->max_luminance) {
3104                 caps->aux_min_input_signal = luminance_range->min_luminance;
3105                 caps->aux_max_input_signal = luminance_range->max_luminance;
3106         } else {
3107                 caps->aux_min_input_signal = 0;
3108                 caps->aux_max_input_signal = 512;
3109         }
3110 }
3111
3112 void amdgpu_dm_update_connector_after_detect(
3113                 struct amdgpu_dm_connector *aconnector)
3114 {
3115         struct drm_connector *connector = &aconnector->base;
3116         struct drm_device *dev = connector->dev;
3117         struct dc_sink *sink;
3118
3119         /* MST handled by drm_mst framework */
3120         if (aconnector->mst_mgr.mst_state == true)
3121                 return;
3122
3123         sink = aconnector->dc_link->local_sink;
3124         if (sink)
3125                 dc_sink_retain(sink);
3126
3127         /*
3128          * Edid mgmt connector gets first update only in mode_valid hook and then
3129          * the connector sink is set to either fake or physical sink depends on link status.
3130          * Skip if already done during boot.
3131          */
3132         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3133                         && aconnector->dc_em_sink) {
3134
3135                 /*
3136                  * For S3 resume with headless use eml_sink to fake stream
3137                  * because on resume connector->sink is set to NULL
3138                  */
3139                 mutex_lock(&dev->mode_config.mutex);
3140
3141                 if (sink) {
3142                         if (aconnector->dc_sink) {
3143                                 amdgpu_dm_update_freesync_caps(connector, NULL);
3144                                 /*
3145                                  * retain and release below are used to
3146                                  * bump up refcount for sink because the link doesn't point
3147                                  * to it anymore after disconnect, so on next crtc to connector
3148                                  * reshuffle by UMD we will get into unwanted dc_sink release
3149                                  */
3150                                 dc_sink_release(aconnector->dc_sink);
3151                         }
3152                         aconnector->dc_sink = sink;
3153                         dc_sink_retain(aconnector->dc_sink);
3154                         amdgpu_dm_update_freesync_caps(connector,
3155                                         aconnector->edid);
3156                 } else {
3157                         amdgpu_dm_update_freesync_caps(connector, NULL);
3158                         if (!aconnector->dc_sink) {
3159                                 aconnector->dc_sink = aconnector->dc_em_sink;
3160                                 dc_sink_retain(aconnector->dc_sink);
3161                         }
3162                 }
3163
3164                 mutex_unlock(&dev->mode_config.mutex);
3165
3166                 if (sink)
3167                         dc_sink_release(sink);
3168                 return;
3169         }
3170
3171         /*
3172          * TODO: temporary guard to look for proper fix
3173          * if this sink is MST sink, we should not do anything
3174          */
3175         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3176                 dc_sink_release(sink);
3177                 return;
3178         }
3179
3180         if (aconnector->dc_sink == sink) {
3181                 /*
3182                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
3183                  * Do nothing!!
3184                  */
3185                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3186                                 aconnector->connector_id);
3187                 if (sink)
3188                         dc_sink_release(sink);
3189                 return;
3190         }
3191
3192         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3193                 aconnector->connector_id, aconnector->dc_sink, sink);
3194
3195         mutex_lock(&dev->mode_config.mutex);
3196
3197         /*
3198          * 1. Update status of the drm connector
3199          * 2. Send an event and let userspace tell us what to do
3200          */
3201         if (sink) {
3202                 /*
3203                  * TODO: check if we still need the S3 mode update workaround.
3204                  * If yes, put it here.
3205                  */
3206                 if (aconnector->dc_sink) {
3207                         amdgpu_dm_update_freesync_caps(connector, NULL);
3208                         dc_sink_release(aconnector->dc_sink);
3209                 }
3210
3211                 aconnector->dc_sink = sink;
3212                 dc_sink_retain(aconnector->dc_sink);
3213                 if (sink->dc_edid.length == 0) {
3214                         aconnector->edid = NULL;
3215                         if (aconnector->dc_link->aux_mode) {
3216                                 drm_dp_cec_unset_edid(
3217                                         &aconnector->dm_dp_aux.aux);
3218                         }
3219                 } else {
3220                         aconnector->edid =
3221                                 (struct edid *)sink->dc_edid.raw_edid;
3222
3223                         if (aconnector->dc_link->aux_mode)
3224                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3225                                                     aconnector->edid);
3226                 }
3227
3228                 if (!aconnector->timing_requested) {
3229                         aconnector->timing_requested =
3230                                 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3231                         if (!aconnector->timing_requested)
3232                                 drm_err(dev,
3233                                         "failed to create aconnector->requested_timing\n");
3234                 }
3235
3236                 drm_connector_update_edid_property(connector, aconnector->edid);
3237                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3238                 update_connector_ext_caps(aconnector);
3239         } else {
3240                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3241                 amdgpu_dm_update_freesync_caps(connector, NULL);
3242                 drm_connector_update_edid_property(connector, NULL);
3243                 aconnector->num_modes = 0;
3244                 dc_sink_release(aconnector->dc_sink);
3245                 aconnector->dc_sink = NULL;
3246                 aconnector->edid = NULL;
3247                 kfree(aconnector->timing_requested);
3248                 aconnector->timing_requested = NULL;
3249                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3250                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3251                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3252         }
3253
3254         mutex_unlock(&dev->mode_config.mutex);
3255
3256         update_subconnector_property(aconnector);
3257
3258         if (sink)
3259                 dc_sink_release(sink);
3260 }
3261
3262 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3263 {
3264         struct drm_connector *connector = &aconnector->base;
3265         struct drm_device *dev = connector->dev;
3266         enum dc_connection_type new_connection_type = dc_connection_none;
3267         struct amdgpu_device *adev = drm_to_adev(dev);
3268         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3269         bool ret = false;
3270
3271         if (adev->dm.disable_hpd_irq)
3272                 return;
3273
3274         /*
3275          * In case of failure or MST no need to update connector status or notify the OS
3276          * since (for MST case) MST does this in its own context.
3277          */
3278         mutex_lock(&aconnector->hpd_lock);
3279
3280         if (adev->dm.hdcp_workqueue) {
3281                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3282                 dm_con_state->update_hdcp = true;
3283         }
3284         if (aconnector->fake_enable)
3285                 aconnector->fake_enable = false;
3286
3287         aconnector->timing_changed = false;
3288
3289         if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3290                 DRM_ERROR("KMS: Failed to detect connector\n");
3291
3292         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3293                 emulated_link_detect(aconnector->dc_link);
3294
3295                 drm_modeset_lock_all(dev);
3296                 dm_restore_drm_connector_state(dev, connector);
3297                 drm_modeset_unlock_all(dev);
3298
3299                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3300                         drm_kms_helper_connector_hotplug_event(connector);
3301         } else {
3302                 mutex_lock(&adev->dm.dc_lock);
3303                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3304                 mutex_unlock(&adev->dm.dc_lock);
3305                 if (ret) {
3306                         amdgpu_dm_update_connector_after_detect(aconnector);
3307
3308                         drm_modeset_lock_all(dev);
3309                         dm_restore_drm_connector_state(dev, connector);
3310                         drm_modeset_unlock_all(dev);
3311
3312                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3313                                 drm_kms_helper_connector_hotplug_event(connector);
3314                 }
3315         }
3316         mutex_unlock(&aconnector->hpd_lock);
3317
3318 }
3319
3320 static void handle_hpd_irq(void *param)
3321 {
3322         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3323
3324         handle_hpd_irq_helper(aconnector);
3325
3326 }
3327
3328 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3329                                                         union hpd_irq_data hpd_irq_data)
3330 {
3331         struct hpd_rx_irq_offload_work *offload_work =
3332                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3333
3334         if (!offload_work) {
3335                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3336                 return;
3337         }
3338
3339         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3340         offload_work->data = hpd_irq_data;
3341         offload_work->offload_wq = offload_wq;
3342
3343         queue_work(offload_wq->wq, &offload_work->work);
3344         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3345 }
3346
3347 static void handle_hpd_rx_irq(void *param)
3348 {
3349         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3350         struct drm_connector *connector = &aconnector->base;
3351         struct drm_device *dev = connector->dev;
3352         struct dc_link *dc_link = aconnector->dc_link;
3353         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3354         bool result = false;
3355         enum dc_connection_type new_connection_type = dc_connection_none;
3356         struct amdgpu_device *adev = drm_to_adev(dev);
3357         union hpd_irq_data hpd_irq_data;
3358         bool link_loss = false;
3359         bool has_left_work = false;
3360         int idx = dc_link->link_index;
3361         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3362
3363         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3364
3365         if (adev->dm.disable_hpd_irq)
3366                 return;
3367
3368         /*
3369          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3370          * conflict, after implement i2c helper, this mutex should be
3371          * retired.
3372          */
3373         mutex_lock(&aconnector->hpd_lock);
3374
3375         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3376                                                 &link_loss, true, &has_left_work);
3377
3378         if (!has_left_work)
3379                 goto out;
3380
3381         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3382                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3383                 goto out;
3384         }
3385
3386         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3387                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3388                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3389                         bool skip = false;
3390
3391                         /*
3392                          * DOWN_REP_MSG_RDY is also handled by polling method
3393                          * mgr->cbs->poll_hpd_irq()
3394                          */
3395                         spin_lock(&offload_wq->offload_lock);
3396                         skip = offload_wq->is_handling_mst_msg_rdy_event;
3397
3398                         if (!skip)
3399                                 offload_wq->is_handling_mst_msg_rdy_event = true;
3400
3401                         spin_unlock(&offload_wq->offload_lock);
3402
3403                         if (!skip)
3404                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3405
3406                         goto out;
3407                 }
3408
3409                 if (link_loss) {
3410                         bool skip = false;
3411
3412                         spin_lock(&offload_wq->offload_lock);
3413                         skip = offload_wq->is_handling_link_loss;
3414
3415                         if (!skip)
3416                                 offload_wq->is_handling_link_loss = true;
3417
3418                         spin_unlock(&offload_wq->offload_lock);
3419
3420                         if (!skip)
3421                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3422
3423                         goto out;
3424                 }
3425         }
3426
3427 out:
3428         if (result && !is_mst_root_connector) {
3429                 /* Downstream Port status changed. */
3430                 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3431                         DRM_ERROR("KMS: Failed to detect connector\n");
3432
3433                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3434                         emulated_link_detect(dc_link);
3435
3436                         if (aconnector->fake_enable)
3437                                 aconnector->fake_enable = false;
3438
3439                         amdgpu_dm_update_connector_after_detect(aconnector);
3440
3441
3442                         drm_modeset_lock_all(dev);
3443                         dm_restore_drm_connector_state(dev, connector);
3444                         drm_modeset_unlock_all(dev);
3445
3446                         drm_kms_helper_connector_hotplug_event(connector);
3447                 } else {
3448                         bool ret = false;
3449
3450                         mutex_lock(&adev->dm.dc_lock);
3451                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3452                         mutex_unlock(&adev->dm.dc_lock);
3453
3454                         if (ret) {
3455                                 if (aconnector->fake_enable)
3456                                         aconnector->fake_enable = false;
3457
3458                                 amdgpu_dm_update_connector_after_detect(aconnector);
3459
3460                                 drm_modeset_lock_all(dev);
3461                                 dm_restore_drm_connector_state(dev, connector);
3462                                 drm_modeset_unlock_all(dev);
3463
3464                                 drm_kms_helper_connector_hotplug_event(connector);
3465                         }
3466                 }
3467         }
3468         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3469                 if (adev->dm.hdcp_workqueue)
3470                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3471         }
3472
3473         if (dc_link->type != dc_connection_mst_branch)
3474                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3475
3476         mutex_unlock(&aconnector->hpd_lock);
3477 }
3478
3479 static void register_hpd_handlers(struct amdgpu_device *adev)
3480 {
3481         struct drm_device *dev = adev_to_drm(adev);
3482         struct drm_connector *connector;
3483         struct amdgpu_dm_connector *aconnector;
3484         const struct dc_link *dc_link;
3485         struct dc_interrupt_params int_params = {0};
3486
3487         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3488         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3489
3490         list_for_each_entry(connector,
3491                         &dev->mode_config.connector_list, head) {
3492
3493                 aconnector = to_amdgpu_dm_connector(connector);
3494                 dc_link = aconnector->dc_link;
3495
3496                 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
3497                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3498                         int_params.irq_source = dc_link->irq_source_hpd;
3499
3500                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3501                                         handle_hpd_irq,
3502                                         (void *) aconnector);
3503                 }
3504
3505                 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {
3506
3507                         /* Also register for DP short pulse (hpd_rx). */
3508                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3509                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3510
3511                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3512                                         handle_hpd_rx_irq,
3513                                         (void *) aconnector);
3514                 }
3515
3516                 if (adev->dm.hpd_rx_offload_wq)
3517                         adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
3518                                 aconnector;
3519         }
3520 }
3521
3522 #if defined(CONFIG_DRM_AMD_DC_SI)
3523 /* Register IRQ sources and initialize IRQ callbacks */
3524 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3525 {
3526         struct dc *dc = adev->dm.dc;
3527         struct common_irq_params *c_irq_params;
3528         struct dc_interrupt_params int_params = {0};
3529         int r;
3530         int i;
3531         unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3532
3533         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3534         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3535
3536         /*
3537          * Actions of amdgpu_irq_add_id():
3538          * 1. Register a set() function with base driver.
3539          *    Base driver will call set() function to enable/disable an
3540          *    interrupt in DC hardware.
3541          * 2. Register amdgpu_dm_irq_handler().
3542          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3543          *    coming from DC hardware.
3544          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3545          *    for acknowledging and handling.
3546          */
3547
3548         /* Use VBLANK interrupt */
3549         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3550                 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);
3551                 if (r) {
3552                         DRM_ERROR("Failed to add crtc irq id!\n");
3553                         return r;
3554                 }
3555
3556                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3557                 int_params.irq_source =
3558                         dc_interrupt_to_irq_source(dc, i + 1, 0);
3559
3560                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3561
3562                 c_irq_params->adev = adev;
3563                 c_irq_params->irq_src = int_params.irq_source;
3564
3565                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3566                                 dm_crtc_high_irq, c_irq_params);
3567         }
3568
3569         /* Use GRPH_PFLIP interrupt */
3570         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3571                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3572                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3573                 if (r) {
3574                         DRM_ERROR("Failed to add page flip irq id!\n");
3575                         return r;
3576                 }
3577
3578                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3579                 int_params.irq_source =
3580                         dc_interrupt_to_irq_source(dc, i, 0);
3581
3582                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3583
3584                 c_irq_params->adev = adev;
3585                 c_irq_params->irq_src = int_params.irq_source;
3586
3587                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3588                                 dm_pflip_high_irq, c_irq_params);
3589
3590         }
3591
3592         /* HPD */
3593         r = amdgpu_irq_add_id(adev, client_id,
3594                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3595         if (r) {
3596                 DRM_ERROR("Failed to add hpd irq id!\n");
3597                 return r;
3598         }
3599
3600         register_hpd_handlers(adev);
3601
3602         return 0;
3603 }
3604 #endif
3605
3606 /* Register IRQ sources and initialize IRQ callbacks */
3607 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3608 {
3609         struct dc *dc = adev->dm.dc;
3610         struct common_irq_params *c_irq_params;
3611         struct dc_interrupt_params int_params = {0};
3612         int r;
3613         int i;
3614         unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3615
3616         if (adev->family >= AMDGPU_FAMILY_AI)
3617                 client_id = SOC15_IH_CLIENTID_DCE;
3618
3619         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3620         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3621
3622         /*
3623          * Actions of amdgpu_irq_add_id():
3624          * 1. Register a set() function with base driver.
3625          *    Base driver will call set() function to enable/disable an
3626          *    interrupt in DC hardware.
3627          * 2. Register amdgpu_dm_irq_handler().
3628          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3629          *    coming from DC hardware.
3630          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3631          *    for acknowledging and handling.
3632          */
3633
3634         /* Use VBLANK interrupt */
3635         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3636                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3637                 if (r) {
3638                         DRM_ERROR("Failed to add crtc irq id!\n");
3639                         return r;
3640                 }
3641
3642                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3643                 int_params.irq_source =
3644                         dc_interrupt_to_irq_source(dc, i, 0);
3645
3646                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3647
3648                 c_irq_params->adev = adev;
3649                 c_irq_params->irq_src = int_params.irq_source;
3650
3651                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3652                                 dm_crtc_high_irq, c_irq_params);
3653         }
3654
3655         /* Use VUPDATE interrupt */
3656         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3657                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3658                 if (r) {
3659                         DRM_ERROR("Failed to add vupdate irq id!\n");
3660                         return r;
3661                 }
3662
3663                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3664                 int_params.irq_source =
3665                         dc_interrupt_to_irq_source(dc, i, 0);
3666
3667                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3668
3669                 c_irq_params->adev = adev;
3670                 c_irq_params->irq_src = int_params.irq_source;
3671
3672                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3673                                 dm_vupdate_high_irq, c_irq_params);
3674         }
3675
3676         /* Use GRPH_PFLIP interrupt */
3677         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3678                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3679                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3680                 if (r) {
3681                         DRM_ERROR("Failed to add page flip irq id!\n");
3682                         return r;
3683                 }
3684
3685                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3686                 int_params.irq_source =
3687                         dc_interrupt_to_irq_source(dc, i, 0);
3688
3689                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3690
3691                 c_irq_params->adev = adev;
3692                 c_irq_params->irq_src = int_params.irq_source;
3693
3694                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3695                                 dm_pflip_high_irq, c_irq_params);
3696
3697         }
3698
3699         /* HPD */
3700         r = amdgpu_irq_add_id(adev, client_id,
3701                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3702         if (r) {
3703                 DRM_ERROR("Failed to add hpd irq id!\n");
3704                 return r;
3705         }
3706
3707         register_hpd_handlers(adev);
3708
3709         return 0;
3710 }
3711
3712 /* Register IRQ sources and initialize IRQ callbacks */
3713 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3714 {
3715         struct dc *dc = adev->dm.dc;
3716         struct common_irq_params *c_irq_params;
3717         struct dc_interrupt_params int_params = {0};
3718         int r;
3719         int i;
3720 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3721         static const unsigned int vrtl_int_srcid[] = {
3722                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3723                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3724                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3725                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3726                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3727                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3728         };
3729 #endif
3730
3731         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3732         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3733
3734         /*
3735          * Actions of amdgpu_irq_add_id():
3736          * 1. Register a set() function with base driver.
3737          *    Base driver will call set() function to enable/disable an
3738          *    interrupt in DC hardware.
3739          * 2. Register amdgpu_dm_irq_handler().
3740          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3741          *    coming from DC hardware.
3742          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3743          *    for acknowledging and handling.
3744          */
3745
3746         /* Use VSTARTUP interrupt */
3747         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3748                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3749                         i++) {
3750                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3751
3752                 if (r) {
3753                         DRM_ERROR("Failed to add crtc irq id!\n");
3754                         return r;
3755                 }
3756
3757                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3758                 int_params.irq_source =
3759                         dc_interrupt_to_irq_source(dc, i, 0);
3760
3761                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3762
3763                 c_irq_params->adev = adev;
3764                 c_irq_params->irq_src = int_params.irq_source;
3765
3766                 amdgpu_dm_irq_register_interrupt(
3767                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3768         }
3769
3770         /* Use otg vertical line interrupt */
3771 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3772         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3773                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3774                                 vrtl_int_srcid[i], &adev->vline0_irq);
3775
3776                 if (r) {
3777                         DRM_ERROR("Failed to add vline0 irq id!\n");
3778                         return r;
3779                 }
3780
3781                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3782                 int_params.irq_source =
3783                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3784
3785                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3786                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3787                         break;
3788                 }
3789
3790                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3791                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3792
3793                 c_irq_params->adev = adev;
3794                 c_irq_params->irq_src = int_params.irq_source;
3795
3796                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3797                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3798         }
3799 #endif
3800
3801         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3802          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3803          * to trigger at end of each vblank, regardless of state of the lock,
3804          * matching DCE behaviour.
3805          */
3806         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3807              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3808              i++) {
3809                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3810
3811                 if (r) {
3812                         DRM_ERROR("Failed to add vupdate irq id!\n");
3813                         return r;
3814                 }
3815
3816                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3817                 int_params.irq_source =
3818                         dc_interrupt_to_irq_source(dc, i, 0);
3819
3820                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3821
3822                 c_irq_params->adev = adev;
3823                 c_irq_params->irq_src = int_params.irq_source;
3824
3825                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3826                                 dm_vupdate_high_irq, c_irq_params);
3827         }
3828
3829         /* Use GRPH_PFLIP interrupt */
3830         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3831                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3832                         i++) {
3833                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3834                 if (r) {
3835                         DRM_ERROR("Failed to add page flip irq id!\n");
3836                         return r;
3837                 }
3838
3839                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3840                 int_params.irq_source =
3841                         dc_interrupt_to_irq_source(dc, i, 0);
3842
3843                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3844
3845                 c_irq_params->adev = adev;
3846                 c_irq_params->irq_src = int_params.irq_source;
3847
3848                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3849                                 dm_pflip_high_irq, c_irq_params);
3850
3851         }
3852
3853         /* HPD */
3854         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3855                         &adev->hpd_irq);
3856         if (r) {
3857                 DRM_ERROR("Failed to add hpd irq id!\n");
3858                 return r;
3859         }
3860
3861         register_hpd_handlers(adev);
3862
3863         return 0;
3864 }
3865 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3866 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3867 {
3868         struct dc *dc = adev->dm.dc;
3869         struct common_irq_params *c_irq_params;
3870         struct dc_interrupt_params int_params = {0};
3871         int r, i;
3872
3873         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3874         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3875
3876         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3877                         &adev->dmub_outbox_irq);
3878         if (r) {
3879                 DRM_ERROR("Failed to add outbox irq id!\n");
3880                 return r;
3881         }
3882
3883         if (dc->ctx->dmub_srv) {
3884                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3885                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3886                 int_params.irq_source =
3887                 dc_interrupt_to_irq_source(dc, i, 0);
3888
3889                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3890
3891                 c_irq_params->adev = adev;
3892                 c_irq_params->irq_src = int_params.irq_source;
3893
3894                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3895                                 dm_dmub_outbox1_low_irq, c_irq_params);
3896         }
3897
3898         return 0;
3899 }
3900
3901 /*
3902  * Acquires the lock for the atomic state object and returns
3903  * the new atomic state.
3904  *
3905  * This should only be called during atomic check.
3906  */
3907 int dm_atomic_get_state(struct drm_atomic_state *state,
3908                         struct dm_atomic_state **dm_state)
3909 {
3910         struct drm_device *dev = state->dev;
3911         struct amdgpu_device *adev = drm_to_adev(dev);
3912         struct amdgpu_display_manager *dm = &adev->dm;
3913         struct drm_private_state *priv_state;
3914
3915         if (*dm_state)
3916                 return 0;
3917
3918         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3919         if (IS_ERR(priv_state))
3920                 return PTR_ERR(priv_state);
3921
3922         *dm_state = to_dm_atomic_state(priv_state);
3923
3924         return 0;
3925 }
3926
3927 static struct dm_atomic_state *
3928 dm_atomic_get_new_state(struct drm_atomic_state *state)
3929 {
3930         struct drm_device *dev = state->dev;
3931         struct amdgpu_device *adev = drm_to_adev(dev);
3932         struct amdgpu_display_manager *dm = &adev->dm;
3933         struct drm_private_obj *obj;
3934         struct drm_private_state *new_obj_state;
3935         int i;
3936
3937         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3938                 if (obj->funcs == dm->atomic_obj.funcs)
3939                         return to_dm_atomic_state(new_obj_state);
3940         }
3941
3942         return NULL;
3943 }
3944
3945 static struct drm_private_state *
3946 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3947 {
3948         struct dm_atomic_state *old_state, *new_state;
3949
3950         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3951         if (!new_state)
3952                 return NULL;
3953
3954         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3955
3956         old_state = to_dm_atomic_state(obj->state);
3957
3958         if (old_state && old_state->context)
3959                 new_state->context = dc_copy_state(old_state->context);
3960
3961         if (!new_state->context) {
3962                 kfree(new_state);
3963                 return NULL;
3964         }
3965
3966         return &new_state->base;
3967 }
3968
3969 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3970                                     struct drm_private_state *state)
3971 {
3972         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3973
3974         if (dm_state && dm_state->context)
3975                 dc_release_state(dm_state->context);
3976
3977         kfree(dm_state);
3978 }
3979
3980 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3981         .atomic_duplicate_state = dm_atomic_duplicate_state,
3982         .atomic_destroy_state = dm_atomic_destroy_state,
3983 };
3984
3985 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3986 {
3987         struct dm_atomic_state *state;
3988         int r;
3989
3990         adev->mode_info.mode_config_initialized = true;
3991
3992         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3993         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3994
3995         adev_to_drm(adev)->mode_config.max_width = 16384;
3996         adev_to_drm(adev)->mode_config.max_height = 16384;
3997
3998         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3999         if (adev->asic_type == CHIP_HAWAII)
4000                 /* disable prefer shadow for now due to hibernation issues */
4001                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
4002         else
4003                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
4004         /* indicates support for immediate flip */
4005         adev_to_drm(adev)->mode_config.async_page_flip = true;
4006
4007         state = kzalloc(sizeof(*state), GFP_KERNEL);
4008         if (!state)
4009                 return -ENOMEM;
4010
4011         state->context = dc_create_state(adev->dm.dc);
4012         if (!state->context) {
4013                 kfree(state);
4014                 return -ENOMEM;
4015         }
4016
4017         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
4018
4019         drm_atomic_private_obj_init(adev_to_drm(adev),
4020                                     &adev->dm.atomic_obj,
4021                                     &state->base,
4022                                     &dm_atomic_state_funcs);
4023
4024         r = amdgpu_display_modeset_create_props(adev);
4025         if (r) {
4026                 dc_release_state(state->context);
4027                 kfree(state);
4028                 return r;
4029         }
4030
4031         r = amdgpu_dm_audio_init(adev);
4032         if (r) {
4033                 dc_release_state(state->context);
4034                 kfree(state);
4035                 return r;
4036         }
4037
4038         return 0;
4039 }
4040
4041 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4042 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4043 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4044
4045 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4046                                             int bl_idx)
4047 {
4048 #if defined(CONFIG_ACPI)
4049         struct amdgpu_dm_backlight_caps caps;
4050
4051         memset(&caps, 0, sizeof(caps));
4052
4053         if (dm->backlight_caps[bl_idx].caps_valid)
4054                 return;
4055
4056         amdgpu_acpi_get_backlight_caps(&caps);
4057         if (caps.caps_valid) {
4058                 dm->backlight_caps[bl_idx].caps_valid = true;
4059                 if (caps.aux_support)
4060                         return;
4061                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4062                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4063         } else {
4064                 dm->backlight_caps[bl_idx].min_input_signal =
4065                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4066                 dm->backlight_caps[bl_idx].max_input_signal =
4067                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4068         }
4069 #else
4070         if (dm->backlight_caps[bl_idx].aux_support)
4071                 return;
4072
4073         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4074         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4075 #endif
4076 }
4077
4078 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4079                                 unsigned int *min, unsigned int *max)
4080 {
4081         if (!caps)
4082                 return 0;
4083
4084         if (caps->aux_support) {
4085                 // Firmware limits are in nits, DC API wants millinits.
4086                 *max = 1000 * caps->aux_max_input_signal;
4087                 *min = 1000 * caps->aux_min_input_signal;
4088         } else {
4089                 // Firmware limits are 8-bit, PWM control is 16-bit.
4090                 *max = 0x101 * caps->max_input_signal;
4091                 *min = 0x101 * caps->min_input_signal;
4092         }
4093         return 1;
4094 }
4095
4096 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4097                                         uint32_t brightness)
4098 {
4099         unsigned int min, max;
4100
4101         if (!get_brightness_range(caps, &min, &max))
4102                 return brightness;
4103
4104         // Rescale 0..255 to min..max
4105         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4106                                        AMDGPU_MAX_BL_LEVEL);
4107 }
4108
4109 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4110                                       uint32_t brightness)
4111 {
4112         unsigned int min, max;
4113
4114         if (!get_brightness_range(caps, &min, &max))
4115                 return brightness;
4116
4117         if (brightness < min)
4118                 return 0;
4119         // Rescale min..max to 0..255
4120         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4121                                  max - min);
4122 }
4123
4124 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4125                                          int bl_idx,
4126                                          u32 user_brightness)
4127 {
4128         struct amdgpu_dm_backlight_caps caps;
4129         struct dc_link *link;
4130         u32 brightness;
4131         bool rc;
4132
4133         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4134         caps = dm->backlight_caps[bl_idx];
4135
4136         dm->brightness[bl_idx] = user_brightness;
4137         /* update scratch register */
4138         if (bl_idx == 0)
4139                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4140         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4141         link = (struct dc_link *)dm->backlight_link[bl_idx];
4142
4143         /* Change brightness based on AUX property */
4144         if (caps.aux_support) {
4145                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4146                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4147                 if (!rc)
4148                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4149         } else {
4150                 rc = dc_link_set_backlight_level(link, brightness, 0);
4151                 if (!rc)
4152                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4153         }
4154
4155         if (rc)
4156                 dm->actual_brightness[bl_idx] = user_brightness;
4157 }
4158
4159 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4160 {
4161         struct amdgpu_display_manager *dm = bl_get_data(bd);
4162         int i;
4163
4164         for (i = 0; i < dm->num_of_edps; i++) {
4165                 if (bd == dm->backlight_dev[i])
4166                         break;
4167         }
4168         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4169                 i = 0;
4170         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4171
4172         return 0;
4173 }
4174
4175 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4176                                          int bl_idx)
4177 {
4178         int ret;
4179         struct amdgpu_dm_backlight_caps caps;
4180         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4181
4182         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4183         caps = dm->backlight_caps[bl_idx];
4184
4185         if (caps.aux_support) {
4186                 u32 avg, peak;
4187                 bool rc;
4188
4189                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4190                 if (!rc)
4191                         return dm->brightness[bl_idx];
4192                 return convert_brightness_to_user(&caps, avg);
4193         }
4194
4195         ret = dc_link_get_backlight_level(link);
4196
4197         if (ret == DC_ERROR_UNEXPECTED)
4198                 return dm->brightness[bl_idx];
4199
4200         return convert_brightness_to_user(&caps, ret);
4201 }
4202
4203 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4204 {
4205         struct amdgpu_display_manager *dm = bl_get_data(bd);
4206         int i;
4207
4208         for (i = 0; i < dm->num_of_edps; i++) {
4209                 if (bd == dm->backlight_dev[i])
4210                         break;
4211         }
4212         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4213                 i = 0;
4214         return amdgpu_dm_backlight_get_level(dm, i);
4215 }
4216
4217 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4218         .options = BL_CORE_SUSPENDRESUME,
4219         .get_brightness = amdgpu_dm_backlight_get_brightness,
4220         .update_status  = amdgpu_dm_backlight_update_status,
4221 };
4222
4223 static void
4224 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4225 {
4226         struct drm_device *drm = aconnector->base.dev;
4227         struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4228         struct backlight_properties props = { 0 };
4229         char bl_name[16];
4230
4231         if (aconnector->bl_idx == -1)
4232                 return;
4233
4234         if (!acpi_video_backlight_use_native()) {
4235                 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4236                 /* Try registering an ACPI video backlight device instead. */
4237                 acpi_video_register_backlight();
4238                 return;
4239         }
4240
4241         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4242         props.brightness = AMDGPU_MAX_BL_LEVEL;
4243         props.type = BACKLIGHT_RAW;
4244
4245         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4246                  drm->primary->index + aconnector->bl_idx);
4247
4248         dm->backlight_dev[aconnector->bl_idx] =
4249                 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4250                                           &amdgpu_dm_backlight_ops, &props);
4251
4252         if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4253                 DRM_ERROR("DM: Backlight registration failed!\n");
4254                 dm->backlight_dev[aconnector->bl_idx] = NULL;
4255         } else
4256                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4257 }
4258
4259 static int initialize_plane(struct amdgpu_display_manager *dm,
4260                             struct amdgpu_mode_info *mode_info, int plane_id,
4261                             enum drm_plane_type plane_type,
4262                             const struct dc_plane_cap *plane_cap)
4263 {
4264         struct drm_plane *plane;
4265         unsigned long possible_crtcs;
4266         int ret = 0;
4267
4268         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4269         if (!plane) {
4270                 DRM_ERROR("KMS: Failed to allocate plane\n");
4271                 return -ENOMEM;
4272         }
4273         plane->type = plane_type;
4274
4275         /*
4276          * HACK: IGT tests expect that the primary plane for a CRTC
4277          * can only have one possible CRTC. Only expose support for
4278          * any CRTC if they're not going to be used as a primary plane
4279          * for a CRTC - like overlay or underlay planes.
4280          */
4281         possible_crtcs = 1 << plane_id;
4282         if (plane_id >= dm->dc->caps.max_streams)
4283                 possible_crtcs = 0xff;
4284
4285         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4286
4287         if (ret) {
4288                 DRM_ERROR("KMS: Failed to initialize plane\n");
4289                 kfree(plane);
4290                 return ret;
4291         }
4292
4293         if (mode_info)
4294                 mode_info->planes[plane_id] = plane;
4295
4296         return ret;
4297 }
4298
4299
4300 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4301                                    struct amdgpu_dm_connector *aconnector)
4302 {
4303         struct dc_link *link = aconnector->dc_link;
4304         int bl_idx = dm->num_of_edps;
4305
4306         if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4307             link->type == dc_connection_none)
4308                 return;
4309
4310         if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4311                 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4312                 return;
4313         }
4314
4315         aconnector->bl_idx = bl_idx;
4316
4317         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4318         dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4319         dm->backlight_link[bl_idx] = link;
4320         dm->num_of_edps++;
4321
4322         update_connector_ext_caps(aconnector);
4323 }
4324
4325 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4326
4327 /*
4328  * In this architecture, the association
4329  * connector -> encoder -> crtc
4330  * id not really requried. The crtc and connector will hold the
4331  * display_index as an abstraction to use with DAL component
4332  *
4333  * Returns 0 on success
4334  */
4335 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4336 {
4337         struct amdgpu_display_manager *dm = &adev->dm;
4338         s32 i;
4339         struct amdgpu_dm_connector *aconnector = NULL;
4340         struct amdgpu_encoder *aencoder = NULL;
4341         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4342         u32 link_cnt;
4343         s32 primary_planes;
4344         enum dc_connection_type new_connection_type = dc_connection_none;
4345         const struct dc_plane_cap *plane;
4346         bool psr_feature_enabled = false;
4347         bool replay_feature_enabled = false;
4348         int max_overlay = dm->dc->caps.max_slave_planes;
4349
4350         dm->display_indexes_num = dm->dc->caps.max_streams;
4351         /* Update the actual used number of crtc */
4352         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4353
4354         amdgpu_dm_set_irq_funcs(adev);
4355
4356         link_cnt = dm->dc->caps.max_links;
4357         if (amdgpu_dm_mode_config_init(dm->adev)) {
4358                 DRM_ERROR("DM: Failed to initialize mode config\n");
4359                 return -EINVAL;
4360         }
4361
4362         /* There is one primary plane per CRTC */
4363         primary_planes = dm->dc->caps.max_streams;
4364         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4365
4366         /*
4367          * Initialize primary planes, implicit planes for legacy IOCTLS.
4368          * Order is reversed to match iteration order in atomic check.
4369          */
4370         for (i = (primary_planes - 1); i >= 0; i--) {
4371                 plane = &dm->dc->caps.planes[i];
4372
4373                 if (initialize_plane(dm, mode_info, i,
4374                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4375                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4376                         goto fail;
4377                 }
4378         }
4379
4380         /*
4381          * Initialize overlay planes, index starting after primary planes.
4382          * These planes have a higher DRM index than the primary planes since
4383          * they should be considered as having a higher z-order.
4384          * Order is reversed to match iteration order in atomic check.
4385          *
4386          * Only support DCN for now, and only expose one so we don't encourage
4387          * userspace to use up all the pipes.
4388          */
4389         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4390                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4391
4392                 /* Do not create overlay if MPO disabled */
4393                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4394                         break;
4395
4396                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4397                         continue;
4398
4399                 if (!plane->pixel_format_support.argb8888)
4400                         continue;
4401
4402                 if (max_overlay-- == 0)
4403                         break;
4404
4405                 if (initialize_plane(dm, NULL, primary_planes + i,
4406                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4407                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4408                         goto fail;
4409                 }
4410         }
4411
4412         for (i = 0; i < dm->dc->caps.max_streams; i++)
4413                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4414                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4415                         goto fail;
4416                 }
4417
4418         /* Use Outbox interrupt */
4419         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4420         case IP_VERSION(3, 0, 0):
4421         case IP_VERSION(3, 1, 2):
4422         case IP_VERSION(3, 1, 3):
4423         case IP_VERSION(3, 1, 4):
4424         case IP_VERSION(3, 1, 5):
4425         case IP_VERSION(3, 1, 6):
4426         case IP_VERSION(3, 2, 0):
4427         case IP_VERSION(3, 2, 1):
4428         case IP_VERSION(2, 1, 0):
4429         case IP_VERSION(3, 5, 0):
4430                 if (register_outbox_irq_handlers(dm->adev)) {
4431                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4432                         goto fail;
4433                 }
4434                 break;
4435         default:
4436                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4437                               amdgpu_ip_version(adev, DCE_HWIP, 0));
4438         }
4439
4440         /* Determine whether to enable PSR support by default. */
4441         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4442                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4443                 case IP_VERSION(3, 1, 2):
4444                 case IP_VERSION(3, 1, 3):
4445                 case IP_VERSION(3, 1, 4):
4446                 case IP_VERSION(3, 1, 5):
4447                 case IP_VERSION(3, 1, 6):
4448                 case IP_VERSION(3, 2, 0):
4449                 case IP_VERSION(3, 2, 1):
4450                 case IP_VERSION(3, 5, 0):
4451                         psr_feature_enabled = true;
4452                         break;
4453                 default:
4454                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4455                         break;
4456                 }
4457         }
4458
4459         if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
4460                 switch (adev->ip_versions[DCE_HWIP][0]) {
4461                 case IP_VERSION(3, 1, 4):
4462                 case IP_VERSION(3, 1, 5):
4463                 case IP_VERSION(3, 1, 6):
4464                 case IP_VERSION(3, 2, 0):
4465                 case IP_VERSION(3, 2, 1):
4466                         replay_feature_enabled = true;
4467                         break;
4468                 default:
4469                         replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK;
4470                         break;
4471                 }
4472         }
4473         /* loops over all connectors on the board */
4474         for (i = 0; i < link_cnt; i++) {
4475                 struct dc_link *link = NULL;
4476
4477                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4478                         DRM_ERROR(
4479                                 "KMS: Cannot support more than %d display indexes\n",
4480                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4481                         continue;
4482                 }
4483
4484                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4485                 if (!aconnector)
4486                         goto fail;
4487
4488                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4489                 if (!aencoder)
4490                         goto fail;
4491
4492                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4493                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4494                         goto fail;
4495                 }
4496
4497                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4498                         DRM_ERROR("KMS: Failed to initialize connector\n");
4499                         goto fail;
4500                 }
4501
4502                 link = dc_get_link_at_index(dm->dc, i);
4503
4504                 if (!dc_link_detect_connection_type(link, &new_connection_type))
4505                         DRM_ERROR("KMS: Failed to detect connector\n");
4506
4507                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4508                         emulated_link_detect(link);
4509                         amdgpu_dm_update_connector_after_detect(aconnector);
4510                 } else {
4511                         bool ret = false;
4512
4513                         mutex_lock(&dm->dc_lock);
4514                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4515                         mutex_unlock(&dm->dc_lock);
4516
4517                         if (ret) {
4518                                 amdgpu_dm_update_connector_after_detect(aconnector);
4519                                 setup_backlight_device(dm, aconnector);
4520
4521                                 /*
4522                                  * Disable psr if replay can be enabled
4523                                  */
4524                                 if (replay_feature_enabled && amdgpu_dm_setup_replay(link, aconnector))
4525                                         psr_feature_enabled = false;
4526
4527                                 if (psr_feature_enabled)
4528                                         amdgpu_dm_set_psr_caps(link);
4529
4530                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4531                                  * PSR is also supported.
4532                                  */
4533                                 if (link->psr_settings.psr_feature_enabled)
4534                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4535                         }
4536                 }
4537                 amdgpu_set_panel_orientation(&aconnector->base);
4538         }
4539
4540         /* Software is initialized. Now we can register interrupt handlers. */
4541         switch (adev->asic_type) {
4542 #if defined(CONFIG_DRM_AMD_DC_SI)
4543         case CHIP_TAHITI:
4544         case CHIP_PITCAIRN:
4545         case CHIP_VERDE:
4546         case CHIP_OLAND:
4547                 if (dce60_register_irq_handlers(dm->adev)) {
4548                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4549                         goto fail;
4550                 }
4551                 break;
4552 #endif
4553         case CHIP_BONAIRE:
4554         case CHIP_HAWAII:
4555         case CHIP_KAVERI:
4556         case CHIP_KABINI:
4557         case CHIP_MULLINS:
4558         case CHIP_TONGA:
4559         case CHIP_FIJI:
4560         case CHIP_CARRIZO:
4561         case CHIP_STONEY:
4562         case CHIP_POLARIS11:
4563         case CHIP_POLARIS10:
4564         case CHIP_POLARIS12:
4565         case CHIP_VEGAM:
4566         case CHIP_VEGA10:
4567         case CHIP_VEGA12:
4568         case CHIP_VEGA20:
4569                 if (dce110_register_irq_handlers(dm->adev)) {
4570                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4571                         goto fail;
4572                 }
4573                 break;
4574         default:
4575                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4576                 case IP_VERSION(1, 0, 0):
4577                 case IP_VERSION(1, 0, 1):
4578                 case IP_VERSION(2, 0, 2):
4579                 case IP_VERSION(2, 0, 3):
4580                 case IP_VERSION(2, 0, 0):
4581                 case IP_VERSION(2, 1, 0):
4582                 case IP_VERSION(3, 0, 0):
4583                 case IP_VERSION(3, 0, 2):
4584                 case IP_VERSION(3, 0, 3):
4585                 case IP_VERSION(3, 0, 1):
4586                 case IP_VERSION(3, 1, 2):
4587                 case IP_VERSION(3, 1, 3):
4588                 case IP_VERSION(3, 1, 4):
4589                 case IP_VERSION(3, 1, 5):
4590                 case IP_VERSION(3, 1, 6):
4591                 case IP_VERSION(3, 2, 0):
4592                 case IP_VERSION(3, 2, 1):
4593                 case IP_VERSION(3, 5, 0):
4594                         if (dcn10_register_irq_handlers(dm->adev)) {
4595                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4596                                 goto fail;
4597                         }
4598                         break;
4599                 default:
4600                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4601                                         amdgpu_ip_version(adev, DCE_HWIP, 0));
4602                         goto fail;
4603                 }
4604                 break;
4605         }
4606
4607         return 0;
4608 fail:
4609         kfree(aencoder);
4610         kfree(aconnector);
4611
4612         return -EINVAL;
4613 }
4614
4615 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4616 {
4617         drm_atomic_private_obj_fini(&dm->atomic_obj);
4618 }
4619
4620 /******************************************************************************
4621  * amdgpu_display_funcs functions
4622  *****************************************************************************/
4623
4624 /*
4625  * dm_bandwidth_update - program display watermarks
4626  *
4627  * @adev: amdgpu_device pointer
4628  *
4629  * Calculate and program the display watermarks and line buffer allocation.
4630  */
4631 static void dm_bandwidth_update(struct amdgpu_device *adev)
4632 {
4633         /* TODO: implement later */
4634 }
4635
4636 static const struct amdgpu_display_funcs dm_display_funcs = {
4637         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4638         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4639         .backlight_set_level = NULL, /* never called for DC */
4640         .backlight_get_level = NULL, /* never called for DC */
4641         .hpd_sense = NULL,/* called unconditionally */
4642         .hpd_set_polarity = NULL, /* called unconditionally */
4643         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4644         .page_flip_get_scanoutpos =
4645                 dm_crtc_get_scanoutpos,/* called unconditionally */
4646         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4647         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4648 };
4649
4650 #if defined(CONFIG_DEBUG_KERNEL_DC)
4651
4652 static ssize_t s3_debug_store(struct device *device,
4653                               struct device_attribute *attr,
4654                               const char *buf,
4655                               size_t count)
4656 {
4657         int ret;
4658         int s3_state;
4659         struct drm_device *drm_dev = dev_get_drvdata(device);
4660         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4661
4662         ret = kstrtoint(buf, 0, &s3_state);
4663
4664         if (ret == 0) {
4665                 if (s3_state) {
4666                         dm_resume(adev);
4667                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4668                 } else
4669                         dm_suspend(adev);
4670         }
4671
4672         return ret == 0 ? count : 0;
4673 }
4674
4675 DEVICE_ATTR_WO(s3_debug);
4676
4677 #endif
4678
4679 static int dm_init_microcode(struct amdgpu_device *adev)
4680 {
4681         char *fw_name_dmub;
4682         int r;
4683
4684         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4685         case IP_VERSION(2, 1, 0):
4686                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4687                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4688                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4689                 break;
4690         case IP_VERSION(3, 0, 0):
4691                 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
4692                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4693                 else
4694                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4695                 break;
4696         case IP_VERSION(3, 0, 1):
4697                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4698                 break;
4699         case IP_VERSION(3, 0, 2):
4700                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4701                 break;
4702         case IP_VERSION(3, 0, 3):
4703                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4704                 break;
4705         case IP_VERSION(3, 1, 2):
4706         case IP_VERSION(3, 1, 3):
4707                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4708                 break;
4709         case IP_VERSION(3, 1, 4):
4710                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4711                 break;
4712         case IP_VERSION(3, 1, 5):
4713                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4714                 break;
4715         case IP_VERSION(3, 1, 6):
4716                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4717                 break;
4718         case IP_VERSION(3, 2, 0):
4719                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4720                 break;
4721         case IP_VERSION(3, 2, 1):
4722                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4723                 break;
4724         case IP_VERSION(3, 5, 0):
4725                 fw_name_dmub = FIRMWARE_DCN_35_DMUB;
4726                 break;
4727         default:
4728                 /* ASIC doesn't support DMUB. */
4729                 return 0;
4730         }
4731         r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4732         return r;
4733 }
4734
4735 static int dm_early_init(void *handle)
4736 {
4737         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4738         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4739         struct atom_context *ctx = mode_info->atom_context;
4740         int index = GetIndexIntoMasterTable(DATA, Object_Header);
4741         u16 data_offset;
4742
4743         /* if there is no object header, skip DM */
4744         if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4745                 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4746                 dev_info(adev->dev, "No object header, skipping DM\n");
4747                 return -ENOENT;
4748         }
4749
4750         switch (adev->asic_type) {
4751 #if defined(CONFIG_DRM_AMD_DC_SI)
4752         case CHIP_TAHITI:
4753         case CHIP_PITCAIRN:
4754         case CHIP_VERDE:
4755                 adev->mode_info.num_crtc = 6;
4756                 adev->mode_info.num_hpd = 6;
4757                 adev->mode_info.num_dig = 6;
4758                 break;
4759         case CHIP_OLAND:
4760                 adev->mode_info.num_crtc = 2;
4761                 adev->mode_info.num_hpd = 2;
4762                 adev->mode_info.num_dig = 2;
4763                 break;
4764 #endif
4765         case CHIP_BONAIRE:
4766         case CHIP_HAWAII:
4767                 adev->mode_info.num_crtc = 6;
4768                 adev->mode_info.num_hpd = 6;
4769                 adev->mode_info.num_dig = 6;
4770                 break;
4771         case CHIP_KAVERI:
4772                 adev->mode_info.num_crtc = 4;
4773                 adev->mode_info.num_hpd = 6;
4774                 adev->mode_info.num_dig = 7;
4775                 break;
4776         case CHIP_KABINI:
4777         case CHIP_MULLINS:
4778                 adev->mode_info.num_crtc = 2;
4779                 adev->mode_info.num_hpd = 6;
4780                 adev->mode_info.num_dig = 6;
4781                 break;
4782         case CHIP_FIJI:
4783         case CHIP_TONGA:
4784                 adev->mode_info.num_crtc = 6;
4785                 adev->mode_info.num_hpd = 6;
4786                 adev->mode_info.num_dig = 7;
4787                 break;
4788         case CHIP_CARRIZO:
4789                 adev->mode_info.num_crtc = 3;
4790                 adev->mode_info.num_hpd = 6;
4791                 adev->mode_info.num_dig = 9;
4792                 break;
4793         case CHIP_STONEY:
4794                 adev->mode_info.num_crtc = 2;
4795                 adev->mode_info.num_hpd = 6;
4796                 adev->mode_info.num_dig = 9;
4797                 break;
4798         case CHIP_POLARIS11:
4799         case CHIP_POLARIS12:
4800                 adev->mode_info.num_crtc = 5;
4801                 adev->mode_info.num_hpd = 5;
4802                 adev->mode_info.num_dig = 5;
4803                 break;
4804         case CHIP_POLARIS10:
4805         case CHIP_VEGAM:
4806                 adev->mode_info.num_crtc = 6;
4807                 adev->mode_info.num_hpd = 6;
4808                 adev->mode_info.num_dig = 6;
4809                 break;
4810         case CHIP_VEGA10:
4811         case CHIP_VEGA12:
4812         case CHIP_VEGA20:
4813                 adev->mode_info.num_crtc = 6;
4814                 adev->mode_info.num_hpd = 6;
4815                 adev->mode_info.num_dig = 6;
4816                 break;
4817         default:
4818
4819                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4820                 case IP_VERSION(2, 0, 2):
4821                 case IP_VERSION(3, 0, 0):
4822                         adev->mode_info.num_crtc = 6;
4823                         adev->mode_info.num_hpd = 6;
4824                         adev->mode_info.num_dig = 6;
4825                         break;
4826                 case IP_VERSION(2, 0, 0):
4827                 case IP_VERSION(3, 0, 2):
4828                         adev->mode_info.num_crtc = 5;
4829                         adev->mode_info.num_hpd = 5;
4830                         adev->mode_info.num_dig = 5;
4831                         break;
4832                 case IP_VERSION(2, 0, 3):
4833                 case IP_VERSION(3, 0, 3):
4834                         adev->mode_info.num_crtc = 2;
4835                         adev->mode_info.num_hpd = 2;
4836                         adev->mode_info.num_dig = 2;
4837                         break;
4838                 case IP_VERSION(1, 0, 0):
4839                 case IP_VERSION(1, 0, 1):
4840                 case IP_VERSION(3, 0, 1):
4841                 case IP_VERSION(2, 1, 0):
4842                 case IP_VERSION(3, 1, 2):
4843                 case IP_VERSION(3, 1, 3):
4844                 case IP_VERSION(3, 1, 4):
4845                 case IP_VERSION(3, 1, 5):
4846                 case IP_VERSION(3, 1, 6):
4847                 case IP_VERSION(3, 2, 0):
4848                 case IP_VERSION(3, 2, 1):
4849                 case IP_VERSION(3, 5, 0):
4850                         adev->mode_info.num_crtc = 4;
4851                         adev->mode_info.num_hpd = 4;
4852                         adev->mode_info.num_dig = 4;
4853                         break;
4854                 default:
4855                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4856                                         amdgpu_ip_version(adev, DCE_HWIP, 0));
4857                         return -EINVAL;
4858                 }
4859                 break;
4860         }
4861
4862         if (adev->mode_info.funcs == NULL)
4863                 adev->mode_info.funcs = &dm_display_funcs;
4864
4865         /*
4866          * Note: Do NOT change adev->audio_endpt_rreg and
4867          * adev->audio_endpt_wreg because they are initialised in
4868          * amdgpu_device_init()
4869          */
4870 #if defined(CONFIG_DEBUG_KERNEL_DC)
4871         device_create_file(
4872                 adev_to_drm(adev)->dev,
4873                 &dev_attr_s3_debug);
4874 #endif
4875         adev->dc_enabled = true;
4876
4877         return dm_init_microcode(adev);
4878 }
4879
4880 static bool modereset_required(struct drm_crtc_state *crtc_state)
4881 {
4882         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4883 }
4884
4885 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4886 {
4887         drm_encoder_cleanup(encoder);
4888         kfree(encoder);
4889 }
4890
4891 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4892         .destroy = amdgpu_dm_encoder_destroy,
4893 };
4894
4895 static int
4896 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4897                             const enum surface_pixel_format format,
4898                             enum dc_color_space *color_space)
4899 {
4900         bool full_range;
4901
4902         *color_space = COLOR_SPACE_SRGB;
4903
4904         /* DRM color properties only affect non-RGB formats. */
4905         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4906                 return 0;
4907
4908         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4909
4910         switch (plane_state->color_encoding) {
4911         case DRM_COLOR_YCBCR_BT601:
4912                 if (full_range)
4913                         *color_space = COLOR_SPACE_YCBCR601;
4914                 else
4915                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4916                 break;
4917
4918         case DRM_COLOR_YCBCR_BT709:
4919                 if (full_range)
4920                         *color_space = COLOR_SPACE_YCBCR709;
4921                 else
4922                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4923                 break;
4924
4925         case DRM_COLOR_YCBCR_BT2020:
4926                 if (full_range)
4927                         *color_space = COLOR_SPACE_2020_YCBCR;
4928                 else
4929                         return -EINVAL;
4930                 break;
4931
4932         default:
4933                 return -EINVAL;
4934         }
4935
4936         return 0;
4937 }
4938
4939 static int
4940 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4941                             const struct drm_plane_state *plane_state,
4942                             const u64 tiling_flags,
4943                             struct dc_plane_info *plane_info,
4944                             struct dc_plane_address *address,
4945                             bool tmz_surface,
4946                             bool force_disable_dcc)
4947 {
4948         const struct drm_framebuffer *fb = plane_state->fb;
4949         const struct amdgpu_framebuffer *afb =
4950                 to_amdgpu_framebuffer(plane_state->fb);
4951         int ret;
4952
4953         memset(plane_info, 0, sizeof(*plane_info));
4954
4955         switch (fb->format->format) {
4956         case DRM_FORMAT_C8:
4957                 plane_info->format =
4958                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4959                 break;
4960         case DRM_FORMAT_RGB565:
4961                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4962                 break;
4963         case DRM_FORMAT_XRGB8888:
4964         case DRM_FORMAT_ARGB8888:
4965                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4966                 break;
4967         case DRM_FORMAT_XRGB2101010:
4968         case DRM_FORMAT_ARGB2101010:
4969                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4970                 break;
4971         case DRM_FORMAT_XBGR2101010:
4972         case DRM_FORMAT_ABGR2101010:
4973                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4974                 break;
4975         case DRM_FORMAT_XBGR8888:
4976         case DRM_FORMAT_ABGR8888:
4977                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4978                 break;
4979         case DRM_FORMAT_NV21:
4980                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4981                 break;
4982         case DRM_FORMAT_NV12:
4983                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4984                 break;
4985         case DRM_FORMAT_P010:
4986                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4987                 break;
4988         case DRM_FORMAT_XRGB16161616F:
4989         case DRM_FORMAT_ARGB16161616F:
4990                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4991                 break;
4992         case DRM_FORMAT_XBGR16161616F:
4993         case DRM_FORMAT_ABGR16161616F:
4994                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4995                 break;
4996         case DRM_FORMAT_XRGB16161616:
4997         case DRM_FORMAT_ARGB16161616:
4998                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4999                 break;
5000         case DRM_FORMAT_XBGR16161616:
5001         case DRM_FORMAT_ABGR16161616:
5002                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
5003                 break;
5004         default:
5005                 DRM_ERROR(
5006                         "Unsupported screen format %p4cc\n",
5007                         &fb->format->format);
5008                 return -EINVAL;
5009         }
5010
5011         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
5012         case DRM_MODE_ROTATE_0:
5013                 plane_info->rotation = ROTATION_ANGLE_0;
5014                 break;
5015         case DRM_MODE_ROTATE_90:
5016                 plane_info->rotation = ROTATION_ANGLE_90;
5017                 break;
5018         case DRM_MODE_ROTATE_180:
5019                 plane_info->rotation = ROTATION_ANGLE_180;
5020                 break;
5021         case DRM_MODE_ROTATE_270:
5022                 plane_info->rotation = ROTATION_ANGLE_270;
5023                 break;
5024         default:
5025                 plane_info->rotation = ROTATION_ANGLE_0;
5026                 break;
5027         }
5028
5029
5030         plane_info->visible = true;
5031         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
5032
5033         plane_info->layer_index = plane_state->normalized_zpos;
5034
5035         ret = fill_plane_color_attributes(plane_state, plane_info->format,
5036                                           &plane_info->color_space);
5037         if (ret)
5038                 return ret;
5039
5040         ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
5041                                            plane_info->rotation, tiling_flags,
5042                                            &plane_info->tiling_info,
5043                                            &plane_info->plane_size,
5044                                            &plane_info->dcc, address,
5045                                            tmz_surface, force_disable_dcc);
5046         if (ret)
5047                 return ret;
5048
5049         amdgpu_dm_plane_fill_blending_from_plane_state(
5050                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
5051                 &plane_info->global_alpha, &plane_info->global_alpha_value);
5052
5053         return 0;
5054 }
5055
5056 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5057                                     struct dc_plane_state *dc_plane_state,
5058                                     struct drm_plane_state *plane_state,
5059                                     struct drm_crtc_state *crtc_state)
5060 {
5061         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5062         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5063         struct dc_scaling_info scaling_info;
5064         struct dc_plane_info plane_info;
5065         int ret;
5066         bool force_disable_dcc = false;
5067
5068         ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5069         if (ret)
5070                 return ret;
5071
5072         dc_plane_state->src_rect = scaling_info.src_rect;
5073         dc_plane_state->dst_rect = scaling_info.dst_rect;
5074         dc_plane_state->clip_rect = scaling_info.clip_rect;
5075         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5076
5077         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5078         ret = fill_dc_plane_info_and_addr(adev, plane_state,
5079                                           afb->tiling_flags,
5080                                           &plane_info,
5081                                           &dc_plane_state->address,
5082                                           afb->tmz_surface,
5083                                           force_disable_dcc);
5084         if (ret)
5085                 return ret;
5086
5087         dc_plane_state->format = plane_info.format;
5088         dc_plane_state->color_space = plane_info.color_space;
5089         dc_plane_state->format = plane_info.format;
5090         dc_plane_state->plane_size = plane_info.plane_size;
5091         dc_plane_state->rotation = plane_info.rotation;
5092         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5093         dc_plane_state->stereo_format = plane_info.stereo_format;
5094         dc_plane_state->tiling_info = plane_info.tiling_info;
5095         dc_plane_state->visible = plane_info.visible;
5096         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5097         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5098         dc_plane_state->global_alpha = plane_info.global_alpha;
5099         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5100         dc_plane_state->dcc = plane_info.dcc;
5101         dc_plane_state->layer_index = plane_info.layer_index;
5102         dc_plane_state->flip_int_enabled = true;
5103
5104         /*
5105          * Always set input transfer function, since plane state is refreshed
5106          * every time.
5107          */
5108         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5109         if (ret)
5110                 return ret;
5111
5112         return 0;
5113 }
5114
5115 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5116                                       struct rect *dirty_rect, int32_t x,
5117                                       s32 y, s32 width, s32 height,
5118                                       int *i, bool ffu)
5119 {
5120         WARN_ON(*i >= DC_MAX_DIRTY_RECTS);
5121
5122         dirty_rect->x = x;
5123         dirty_rect->y = y;
5124         dirty_rect->width = width;
5125         dirty_rect->height = height;
5126
5127         if (ffu)
5128                 drm_dbg(plane->dev,
5129                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5130                         plane->base.id, width, height);
5131         else
5132                 drm_dbg(plane->dev,
5133                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5134                         plane->base.id, x, y, width, height);
5135
5136         (*i)++;
5137 }
5138
5139 /**
5140  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5141  *
5142  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5143  *         remote fb
5144  * @old_plane_state: Old state of @plane
5145  * @new_plane_state: New state of @plane
5146  * @crtc_state: New state of CRTC connected to the @plane
5147  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5148  * @dirty_regions_changed: dirty regions changed
5149  *
5150  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5151  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5152  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5153  * amdgpu_dm's.
5154  *
5155  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5156  * plane with regions that require flushing to the eDP remote buffer. In
5157  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5158  * implicitly provide damage clips without any client support via the plane
5159  * bounds.
5160  */
5161 static void fill_dc_dirty_rects(struct drm_plane *plane,
5162                                 struct drm_plane_state *old_plane_state,
5163                                 struct drm_plane_state *new_plane_state,
5164                                 struct drm_crtc_state *crtc_state,
5165                                 struct dc_flip_addrs *flip_addrs,
5166                                 bool *dirty_regions_changed)
5167 {
5168         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5169         struct rect *dirty_rects = flip_addrs->dirty_rects;
5170         u32 num_clips;
5171         struct drm_mode_rect *clips;
5172         bool bb_changed;
5173         bool fb_changed;
5174         u32 i = 0;
5175         *dirty_regions_changed = false;
5176
5177         /*
5178          * Cursor plane has it's own dirty rect update interface. See
5179          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5180          */
5181         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5182                 return;
5183
5184         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5185         clips = drm_plane_get_damage_clips(new_plane_state);
5186
5187         if (!dm_crtc_state->mpo_requested) {
5188                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5189                         goto ffu;
5190
5191                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5192                         fill_dc_dirty_rect(new_plane_state->plane,
5193                                            &dirty_rects[flip_addrs->dirty_rect_count],
5194                                            clips->x1, clips->y1,
5195                                            clips->x2 - clips->x1, clips->y2 - clips->y1,
5196                                            &flip_addrs->dirty_rect_count,
5197                                            false);
5198                 return;
5199         }
5200
5201         /*
5202          * MPO is requested. Add entire plane bounding box to dirty rects if
5203          * flipped to or damaged.
5204          *
5205          * If plane is moved or resized, also add old bounding box to dirty
5206          * rects.
5207          */
5208         fb_changed = old_plane_state->fb->base.id !=
5209                      new_plane_state->fb->base.id;
5210         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5211                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
5212                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
5213                       old_plane_state->crtc_h != new_plane_state->crtc_h);
5214
5215         drm_dbg(plane->dev,
5216                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5217                 new_plane_state->plane->base.id,
5218                 bb_changed, fb_changed, num_clips);
5219
5220         *dirty_regions_changed = bb_changed;
5221
5222         if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS)
5223                 goto ffu;
5224
5225         if (bb_changed) {
5226                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5227                                    new_plane_state->crtc_x,
5228                                    new_plane_state->crtc_y,
5229                                    new_plane_state->crtc_w,
5230                                    new_plane_state->crtc_h, &i, false);
5231
5232                 /* Add old plane bounding-box if plane is moved or resized */
5233                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5234                                    old_plane_state->crtc_x,
5235                                    old_plane_state->crtc_y,
5236                                    old_plane_state->crtc_w,
5237                                    old_plane_state->crtc_h, &i, false);
5238         }
5239
5240         if (num_clips) {
5241                 for (; i < num_clips; clips++)
5242                         fill_dc_dirty_rect(new_plane_state->plane,
5243                                            &dirty_rects[i], clips->x1,
5244                                            clips->y1, clips->x2 - clips->x1,
5245                                            clips->y2 - clips->y1, &i, false);
5246         } else if (fb_changed && !bb_changed) {
5247                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5248                                    new_plane_state->crtc_x,
5249                                    new_plane_state->crtc_y,
5250                                    new_plane_state->crtc_w,
5251                                    new_plane_state->crtc_h, &i, false);
5252         }
5253
5254         flip_addrs->dirty_rect_count = i;
5255         return;
5256
5257 ffu:
5258         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5259                            dm_crtc_state->base.mode.crtc_hdisplay,
5260                            dm_crtc_state->base.mode.crtc_vdisplay,
5261                            &flip_addrs->dirty_rect_count, true);
5262 }
5263
5264 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5265                                            const struct dm_connector_state *dm_state,
5266                                            struct dc_stream_state *stream)
5267 {
5268         enum amdgpu_rmx_type rmx_type;
5269
5270         struct rect src = { 0 }; /* viewport in composition space*/
5271         struct rect dst = { 0 }; /* stream addressable area */
5272
5273         /* no mode. nothing to be done */
5274         if (!mode)
5275                 return;
5276
5277         /* Full screen scaling by default */
5278         src.width = mode->hdisplay;
5279         src.height = mode->vdisplay;
5280         dst.width = stream->timing.h_addressable;
5281         dst.height = stream->timing.v_addressable;
5282
5283         if (dm_state) {
5284                 rmx_type = dm_state->scaling;
5285                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5286                         if (src.width * dst.height <
5287                                         src.height * dst.width) {
5288                                 /* height needs less upscaling/more downscaling */
5289                                 dst.width = src.width *
5290                                                 dst.height / src.height;
5291                         } else {
5292                                 /* width needs less upscaling/more downscaling */
5293                                 dst.height = src.height *
5294                                                 dst.width / src.width;
5295                         }
5296                 } else if (rmx_type == RMX_CENTER) {
5297                         dst = src;
5298                 }
5299
5300                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5301                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5302
5303                 if (dm_state->underscan_enable) {
5304                         dst.x += dm_state->underscan_hborder / 2;
5305                         dst.y += dm_state->underscan_vborder / 2;
5306                         dst.width -= dm_state->underscan_hborder;
5307                         dst.height -= dm_state->underscan_vborder;
5308                 }
5309         }
5310
5311         stream->src = src;
5312         stream->dst = dst;
5313
5314         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5315                       dst.x, dst.y, dst.width, dst.height);
5316
5317 }
5318
5319 static enum dc_color_depth
5320 convert_color_depth_from_display_info(const struct drm_connector *connector,
5321                                       bool is_y420, int requested_bpc)
5322 {
5323         u8 bpc;
5324
5325         if (is_y420) {
5326                 bpc = 8;
5327
5328                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5329                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5330                         bpc = 16;
5331                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5332                         bpc = 12;
5333                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5334                         bpc = 10;
5335         } else {
5336                 bpc = (uint8_t)connector->display_info.bpc;
5337                 /* Assume 8 bpc by default if no bpc is specified. */
5338                 bpc = bpc ? bpc : 8;
5339         }
5340
5341         if (requested_bpc > 0) {
5342                 /*
5343                  * Cap display bpc based on the user requested value.
5344                  *
5345                  * The value for state->max_bpc may not correctly updated
5346                  * depending on when the connector gets added to the state
5347                  * or if this was called outside of atomic check, so it
5348                  * can't be used directly.
5349                  */
5350                 bpc = min_t(u8, bpc, requested_bpc);
5351
5352                 /* Round down to the nearest even number. */
5353                 bpc = bpc - (bpc & 1);
5354         }
5355
5356         switch (bpc) {
5357         case 0:
5358                 /*
5359                  * Temporary Work around, DRM doesn't parse color depth for
5360                  * EDID revision before 1.4
5361                  * TODO: Fix edid parsing
5362                  */
5363                 return COLOR_DEPTH_888;
5364         case 6:
5365                 return COLOR_DEPTH_666;
5366         case 8:
5367                 return COLOR_DEPTH_888;
5368         case 10:
5369                 return COLOR_DEPTH_101010;
5370         case 12:
5371                 return COLOR_DEPTH_121212;
5372         case 14:
5373                 return COLOR_DEPTH_141414;
5374         case 16:
5375                 return COLOR_DEPTH_161616;
5376         default:
5377                 return COLOR_DEPTH_UNDEFINED;
5378         }
5379 }
5380
5381 static enum dc_aspect_ratio
5382 get_aspect_ratio(const struct drm_display_mode *mode_in)
5383 {
5384         /* 1-1 mapping, since both enums follow the HDMI spec. */
5385         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5386 }
5387
5388 static enum dc_color_space
5389 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
5390                        const struct drm_connector_state *connector_state)
5391 {
5392         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5393
5394         switch (connector_state->colorspace) {
5395         case DRM_MODE_COLORIMETRY_BT601_YCC:
5396                 if (dc_crtc_timing->flags.Y_ONLY)
5397                         color_space = COLOR_SPACE_YCBCR601_LIMITED;
5398                 else
5399                         color_space = COLOR_SPACE_YCBCR601;
5400                 break;
5401         case DRM_MODE_COLORIMETRY_BT709_YCC:
5402                 if (dc_crtc_timing->flags.Y_ONLY)
5403                         color_space = COLOR_SPACE_YCBCR709_LIMITED;
5404                 else
5405                         color_space = COLOR_SPACE_YCBCR709;
5406                 break;
5407         case DRM_MODE_COLORIMETRY_OPRGB:
5408                 color_space = COLOR_SPACE_ADOBERGB;
5409                 break;
5410         case DRM_MODE_COLORIMETRY_BT2020_RGB:
5411         case DRM_MODE_COLORIMETRY_BT2020_YCC:
5412                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
5413                         color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
5414                 else
5415                         color_space = COLOR_SPACE_2020_YCBCR;
5416                 break;
5417         case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
5418         default:
5419                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
5420                         color_space = COLOR_SPACE_SRGB;
5421                 /*
5422                  * 27030khz is the separation point between HDTV and SDTV
5423                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5424                  * respectively
5425                  */
5426                 } else if (dc_crtc_timing->pix_clk_100hz > 270300) {
5427                         if (dc_crtc_timing->flags.Y_ONLY)
5428                                 color_space =
5429                                         COLOR_SPACE_YCBCR709_LIMITED;
5430                         else
5431                                 color_space = COLOR_SPACE_YCBCR709;
5432                 } else {
5433                         if (dc_crtc_timing->flags.Y_ONLY)
5434                                 color_space =
5435                                         COLOR_SPACE_YCBCR601_LIMITED;
5436                         else
5437                                 color_space = COLOR_SPACE_YCBCR601;
5438                 }
5439                 break;
5440         }
5441
5442         return color_space;
5443 }
5444
5445 static enum display_content_type
5446 get_output_content_type(const struct drm_connector_state *connector_state)
5447 {
5448         switch (connector_state->content_type) {
5449         default:
5450         case DRM_MODE_CONTENT_TYPE_NO_DATA:
5451                 return DISPLAY_CONTENT_TYPE_NO_DATA;
5452         case DRM_MODE_CONTENT_TYPE_GRAPHICS:
5453                 return DISPLAY_CONTENT_TYPE_GRAPHICS;
5454         case DRM_MODE_CONTENT_TYPE_PHOTO:
5455                 return DISPLAY_CONTENT_TYPE_PHOTO;
5456         case DRM_MODE_CONTENT_TYPE_CINEMA:
5457                 return DISPLAY_CONTENT_TYPE_CINEMA;
5458         case DRM_MODE_CONTENT_TYPE_GAME:
5459                 return DISPLAY_CONTENT_TYPE_GAME;
5460         }
5461 }
5462
5463 static bool adjust_colour_depth_from_display_info(
5464         struct dc_crtc_timing *timing_out,
5465         const struct drm_display_info *info)
5466 {
5467         enum dc_color_depth depth = timing_out->display_color_depth;
5468         int normalized_clk;
5469
5470         do {
5471                 normalized_clk = timing_out->pix_clk_100hz / 10;
5472                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5473                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5474                         normalized_clk /= 2;
5475                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5476                 switch (depth) {
5477                 case COLOR_DEPTH_888:
5478                         break;
5479                 case COLOR_DEPTH_101010:
5480                         normalized_clk = (normalized_clk * 30) / 24;
5481                         break;
5482                 case COLOR_DEPTH_121212:
5483                         normalized_clk = (normalized_clk * 36) / 24;
5484                         break;
5485                 case COLOR_DEPTH_161616:
5486                         normalized_clk = (normalized_clk * 48) / 24;
5487                         break;
5488                 default:
5489                         /* The above depths are the only ones valid for HDMI. */
5490                         return false;
5491                 }
5492                 if (normalized_clk <= info->max_tmds_clock) {
5493                         timing_out->display_color_depth = depth;
5494                         return true;
5495                 }
5496         } while (--depth > COLOR_DEPTH_666);
5497         return false;
5498 }
5499
5500 static void fill_stream_properties_from_drm_display_mode(
5501         struct dc_stream_state *stream,
5502         const struct drm_display_mode *mode_in,
5503         const struct drm_connector *connector,
5504         const struct drm_connector_state *connector_state,
5505         const struct dc_stream_state *old_stream,
5506         int requested_bpc)
5507 {
5508         struct dc_crtc_timing *timing_out = &stream->timing;
5509         const struct drm_display_info *info = &connector->display_info;
5510         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5511         struct hdmi_vendor_infoframe hv_frame;
5512         struct hdmi_avi_infoframe avi_frame;
5513
5514         memset(&hv_frame, 0, sizeof(hv_frame));
5515         memset(&avi_frame, 0, sizeof(avi_frame));
5516
5517         timing_out->h_border_left = 0;
5518         timing_out->h_border_right = 0;
5519         timing_out->v_border_top = 0;
5520         timing_out->v_border_bottom = 0;
5521         /* TODO: un-hardcode */
5522         if (drm_mode_is_420_only(info, mode_in)
5523                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5524                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5525         else if (drm_mode_is_420_also(info, mode_in)
5526                         && aconnector->force_yuv420_output)
5527                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5528         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5529                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5530                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5531         else
5532                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5533
5534         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5535         timing_out->display_color_depth = convert_color_depth_from_display_info(
5536                 connector,
5537                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5538                 requested_bpc);
5539         timing_out->scan_type = SCANNING_TYPE_NODATA;
5540         timing_out->hdmi_vic = 0;
5541
5542         if (old_stream) {
5543                 timing_out->vic = old_stream->timing.vic;
5544                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5545                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5546         } else {
5547                 timing_out->vic = drm_match_cea_mode(mode_in);
5548                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5549                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5550                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5551                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5552         }
5553
5554         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5555                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5556                 timing_out->vic = avi_frame.video_code;
5557                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5558                 timing_out->hdmi_vic = hv_frame.vic;
5559         }
5560
5561         if (is_freesync_video_mode(mode_in, aconnector)) {
5562                 timing_out->h_addressable = mode_in->hdisplay;
5563                 timing_out->h_total = mode_in->htotal;
5564                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5565                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5566                 timing_out->v_total = mode_in->vtotal;
5567                 timing_out->v_addressable = mode_in->vdisplay;
5568                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5569                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5570                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5571         } else {
5572                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5573                 timing_out->h_total = mode_in->crtc_htotal;
5574                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5575                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5576                 timing_out->v_total = mode_in->crtc_vtotal;
5577                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5578                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5579                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5580                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5581         }
5582
5583         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5584
5585         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5586         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5587         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5588                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5589                     drm_mode_is_420_also(info, mode_in) &&
5590                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5591                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5592                         adjust_colour_depth_from_display_info(timing_out, info);
5593                 }
5594         }
5595
5596         stream->output_color_space = get_output_color_space(timing_out, connector_state);
5597         stream->content_type = get_output_content_type(connector_state);
5598 }
5599
5600 static void fill_audio_info(struct audio_info *audio_info,
5601                             const struct drm_connector *drm_connector,
5602                             const struct dc_sink *dc_sink)
5603 {
5604         int i = 0;
5605         int cea_revision = 0;
5606         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5607
5608         audio_info->manufacture_id = edid_caps->manufacturer_id;
5609         audio_info->product_id = edid_caps->product_id;
5610
5611         cea_revision = drm_connector->display_info.cea_rev;
5612
5613         strscpy(audio_info->display_name,
5614                 edid_caps->display_name,
5615                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5616
5617         if (cea_revision >= 3) {
5618                 audio_info->mode_count = edid_caps->audio_mode_count;
5619
5620                 for (i = 0; i < audio_info->mode_count; ++i) {
5621                         audio_info->modes[i].format_code =
5622                                         (enum audio_format_code)
5623                                         (edid_caps->audio_modes[i].format_code);
5624                         audio_info->modes[i].channel_count =
5625                                         edid_caps->audio_modes[i].channel_count;
5626                         audio_info->modes[i].sample_rates.all =
5627                                         edid_caps->audio_modes[i].sample_rate;
5628                         audio_info->modes[i].sample_size =
5629                                         edid_caps->audio_modes[i].sample_size;
5630                 }
5631         }
5632
5633         audio_info->flags.all = edid_caps->speaker_flags;
5634
5635         /* TODO: We only check for the progressive mode, check for interlace mode too */
5636         if (drm_connector->latency_present[0]) {
5637                 audio_info->video_latency = drm_connector->video_latency[0];
5638                 audio_info->audio_latency = drm_connector->audio_latency[0];
5639         }
5640
5641         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5642
5643 }
5644
5645 static void
5646 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5647                                       struct drm_display_mode *dst_mode)
5648 {
5649         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5650         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5651         dst_mode->crtc_clock = src_mode->crtc_clock;
5652         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5653         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5654         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5655         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5656         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5657         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5658         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5659         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5660         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5661         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5662         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5663 }
5664
5665 static void
5666 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5667                                         const struct drm_display_mode *native_mode,
5668                                         bool scale_enabled)
5669 {
5670         if (scale_enabled) {
5671                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5672         } else if (native_mode->clock == drm_mode->clock &&
5673                         native_mode->htotal == drm_mode->htotal &&
5674                         native_mode->vtotal == drm_mode->vtotal) {
5675                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5676         } else {
5677                 /* no scaling nor amdgpu inserted, no need to patch */
5678         }
5679 }
5680
5681 static struct dc_sink *
5682 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5683 {
5684         struct dc_sink_init_data sink_init_data = { 0 };
5685         struct dc_sink *sink = NULL;
5686
5687         sink_init_data.link = aconnector->dc_link;
5688         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5689
5690         sink = dc_sink_create(&sink_init_data);
5691         if (!sink) {
5692                 DRM_ERROR("Failed to create sink!\n");
5693                 return NULL;
5694         }
5695         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5696
5697         return sink;
5698 }
5699
5700 static void set_multisync_trigger_params(
5701                 struct dc_stream_state *stream)
5702 {
5703         struct dc_stream_state *master = NULL;
5704
5705         if (stream->triggered_crtc_reset.enabled) {
5706                 master = stream->triggered_crtc_reset.event_source;
5707                 stream->triggered_crtc_reset.event =
5708                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5709                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5710                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5711         }
5712 }
5713
5714 static void set_master_stream(struct dc_stream_state *stream_set[],
5715                               int stream_count)
5716 {
5717         int j, highest_rfr = 0, master_stream = 0;
5718
5719         for (j = 0;  j < stream_count; j++) {
5720                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5721                         int refresh_rate = 0;
5722
5723                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5724                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5725                         if (refresh_rate > highest_rfr) {
5726                                 highest_rfr = refresh_rate;
5727                                 master_stream = j;
5728                         }
5729                 }
5730         }
5731         for (j = 0;  j < stream_count; j++) {
5732                 if (stream_set[j])
5733                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5734         }
5735 }
5736
5737 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5738 {
5739         int i = 0;
5740         struct dc_stream_state *stream;
5741
5742         if (context->stream_count < 2)
5743                 return;
5744         for (i = 0; i < context->stream_count ; i++) {
5745                 if (!context->streams[i])
5746                         continue;
5747                 /*
5748                  * TODO: add a function to read AMD VSDB bits and set
5749                  * crtc_sync_master.multi_sync_enabled flag
5750                  * For now it's set to false
5751                  */
5752         }
5753
5754         set_master_stream(context->streams, context->stream_count);
5755
5756         for (i = 0; i < context->stream_count ; i++) {
5757                 stream = context->streams[i];
5758
5759                 if (!stream)
5760                         continue;
5761
5762                 set_multisync_trigger_params(stream);
5763         }
5764 }
5765
5766 /**
5767  * DOC: FreeSync Video
5768  *
5769  * When a userspace application wants to play a video, the content follows a
5770  * standard format definition that usually specifies the FPS for that format.
5771  * The below list illustrates some video format and the expected FPS,
5772  * respectively:
5773  *
5774  * - TV/NTSC (23.976 FPS)
5775  * - Cinema (24 FPS)
5776  * - TV/PAL (25 FPS)
5777  * - TV/NTSC (29.97 FPS)
5778  * - TV/NTSC (30 FPS)
5779  * - Cinema HFR (48 FPS)
5780  * - TV/PAL (50 FPS)
5781  * - Commonly used (60 FPS)
5782  * - Multiples of 24 (48,72,96 FPS)
5783  *
5784  * The list of standards video format is not huge and can be added to the
5785  * connector modeset list beforehand. With that, userspace can leverage
5786  * FreeSync to extends the front porch in order to attain the target refresh
5787  * rate. Such a switch will happen seamlessly, without screen blanking or
5788  * reprogramming of the output in any other way. If the userspace requests a
5789  * modesetting change compatible with FreeSync modes that only differ in the
5790  * refresh rate, DC will skip the full update and avoid blink during the
5791  * transition. For example, the video player can change the modesetting from
5792  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5793  * causing any display blink. This same concept can be applied to a mode
5794  * setting change.
5795  */
5796 static struct drm_display_mode *
5797 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5798                 bool use_probed_modes)
5799 {
5800         struct drm_display_mode *m, *m_pref = NULL;
5801         u16 current_refresh, highest_refresh;
5802         struct list_head *list_head = use_probed_modes ?
5803                 &aconnector->base.probed_modes :
5804                 &aconnector->base.modes;
5805
5806         if (aconnector->freesync_vid_base.clock != 0)
5807                 return &aconnector->freesync_vid_base;
5808
5809         /* Find the preferred mode */
5810         list_for_each_entry(m, list_head, head) {
5811                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5812                         m_pref = m;
5813                         break;
5814                 }
5815         }
5816
5817         if (!m_pref) {
5818                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5819                 m_pref = list_first_entry_or_null(
5820                                 &aconnector->base.modes, struct drm_display_mode, head);
5821                 if (!m_pref) {
5822                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5823                         return NULL;
5824                 }
5825         }
5826
5827         highest_refresh = drm_mode_vrefresh(m_pref);
5828
5829         /*
5830          * Find the mode with highest refresh rate with same resolution.
5831          * For some monitors, preferred mode is not the mode with highest
5832          * supported refresh rate.
5833          */
5834         list_for_each_entry(m, list_head, head) {
5835                 current_refresh  = drm_mode_vrefresh(m);
5836
5837                 if (m->hdisplay == m_pref->hdisplay &&
5838                     m->vdisplay == m_pref->vdisplay &&
5839                     highest_refresh < current_refresh) {
5840                         highest_refresh = current_refresh;
5841                         m_pref = m;
5842                 }
5843         }
5844
5845         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5846         return m_pref;
5847 }
5848
5849 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5850                 struct amdgpu_dm_connector *aconnector)
5851 {
5852         struct drm_display_mode *high_mode;
5853         int timing_diff;
5854
5855         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5856         if (!high_mode || !mode)
5857                 return false;
5858
5859         timing_diff = high_mode->vtotal - mode->vtotal;
5860
5861         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5862             high_mode->hdisplay != mode->hdisplay ||
5863             high_mode->vdisplay != mode->vdisplay ||
5864             high_mode->hsync_start != mode->hsync_start ||
5865             high_mode->hsync_end != mode->hsync_end ||
5866             high_mode->htotal != mode->htotal ||
5867             high_mode->hskew != mode->hskew ||
5868             high_mode->vscan != mode->vscan ||
5869             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5870             high_mode->vsync_end - mode->vsync_end != timing_diff)
5871                 return false;
5872         else
5873                 return true;
5874 }
5875
5876 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5877                             struct dc_sink *sink, struct dc_stream_state *stream,
5878                             struct dsc_dec_dpcd_caps *dsc_caps)
5879 {
5880         stream->timing.flags.DSC = 0;
5881         dsc_caps->is_dsc_supported = false;
5882
5883         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5884             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5885                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5886                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5887                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5888                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5889                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5890                                 dsc_caps);
5891         }
5892 }
5893
5894
5895 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5896                                     struct dc_sink *sink, struct dc_stream_state *stream,
5897                                     struct dsc_dec_dpcd_caps *dsc_caps,
5898                                     uint32_t max_dsc_target_bpp_limit_override)
5899 {
5900         const struct dc_link_settings *verified_link_cap = NULL;
5901         u32 link_bw_in_kbps;
5902         u32 edp_min_bpp_x16, edp_max_bpp_x16;
5903         struct dc *dc = sink->ctx->dc;
5904         struct dc_dsc_bw_range bw_range = {0};
5905         struct dc_dsc_config dsc_cfg = {0};
5906         struct dc_dsc_config_options dsc_options = {0};
5907
5908         dc_dsc_get_default_config_option(dc, &dsc_options);
5909         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5910
5911         verified_link_cap = dc_link_get_link_cap(stream->link);
5912         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5913         edp_min_bpp_x16 = 8 * 16;
5914         edp_max_bpp_x16 = 8 * 16;
5915
5916         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5917                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5918
5919         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5920                 edp_min_bpp_x16 = edp_max_bpp_x16;
5921
5922         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5923                                 dc->debug.dsc_min_slice_height_override,
5924                                 edp_min_bpp_x16, edp_max_bpp_x16,
5925                                 dsc_caps,
5926                                 &stream->timing,
5927                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5928                                 &bw_range)) {
5929
5930                 if (bw_range.max_kbps < link_bw_in_kbps) {
5931                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5932                                         dsc_caps,
5933                                         &dsc_options,
5934                                         0,
5935                                         &stream->timing,
5936                                         dc_link_get_highest_encoding_format(aconnector->dc_link),
5937                                         &dsc_cfg)) {
5938                                 stream->timing.dsc_cfg = dsc_cfg;
5939                                 stream->timing.flags.DSC = 1;
5940                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5941                         }
5942                         return;
5943                 }
5944         }
5945
5946         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5947                                 dsc_caps,
5948                                 &dsc_options,
5949                                 link_bw_in_kbps,
5950                                 &stream->timing,
5951                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5952                                 &dsc_cfg)) {
5953                 stream->timing.dsc_cfg = dsc_cfg;
5954                 stream->timing.flags.DSC = 1;
5955         }
5956 }
5957
5958
5959 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5960                                         struct dc_sink *sink, struct dc_stream_state *stream,
5961                                         struct dsc_dec_dpcd_caps *dsc_caps)
5962 {
5963         struct drm_connector *drm_connector = &aconnector->base;
5964         u32 link_bandwidth_kbps;
5965         struct dc *dc = sink->ctx->dc;
5966         u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5967         u32 dsc_max_supported_bw_in_kbps;
5968         u32 max_dsc_target_bpp_limit_override =
5969                 drm_connector->display_info.max_dsc_bpp;
5970         struct dc_dsc_config_options dsc_options = {0};
5971
5972         dc_dsc_get_default_config_option(dc, &dsc_options);
5973         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5974
5975         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5976                                                         dc_link_get_link_cap(aconnector->dc_link));
5977
5978         /* Set DSC policy according to dsc_clock_en */
5979         dc_dsc_policy_set_enable_dsc_when_not_needed(
5980                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5981
5982         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5983             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5984             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5985
5986                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5987
5988         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5989                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5990                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5991                                                 dsc_caps,
5992                                                 &dsc_options,
5993                                                 link_bandwidth_kbps,
5994                                                 &stream->timing,
5995                                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5996                                                 &stream->timing.dsc_cfg)) {
5997                                 stream->timing.flags.DSC = 1;
5998                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5999                         }
6000                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
6001                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
6002                                         dc_link_get_highest_encoding_format(aconnector->dc_link));
6003                         max_supported_bw_in_kbps = link_bandwidth_kbps;
6004                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
6005
6006                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
6007                                         max_supported_bw_in_kbps > 0 &&
6008                                         dsc_max_supported_bw_in_kbps > 0)
6009                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
6010                                                 dsc_caps,
6011                                                 &dsc_options,
6012                                                 dsc_max_supported_bw_in_kbps,
6013                                                 &stream->timing,
6014                                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
6015                                                 &stream->timing.dsc_cfg)) {
6016                                         stream->timing.flags.DSC = 1;
6017                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
6018                                                                          __func__, drm_connector->name);
6019                                 }
6020                 }
6021         }
6022
6023         /* Overwrite the stream flag if DSC is enabled through debugfs */
6024         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
6025                 stream->timing.flags.DSC = 1;
6026
6027         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
6028                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
6029
6030         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
6031                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
6032
6033         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
6034                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
6035 }
6036
6037 static struct dc_stream_state *
6038 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6039                        const struct drm_display_mode *drm_mode,
6040                        const struct dm_connector_state *dm_state,
6041                        const struct dc_stream_state *old_stream,
6042                        int requested_bpc)
6043 {
6044         struct drm_display_mode *preferred_mode = NULL;
6045         struct drm_connector *drm_connector;
6046         const struct drm_connector_state *con_state = &dm_state->base;
6047         struct dc_stream_state *stream = NULL;
6048         struct drm_display_mode mode;
6049         struct drm_display_mode saved_mode;
6050         struct drm_display_mode *freesync_mode = NULL;
6051         bool native_mode_found = false;
6052         bool recalculate_timing = false;
6053         bool scale = dm_state->scaling != RMX_OFF;
6054         int mode_refresh;
6055         int preferred_refresh = 0;
6056         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
6057         struct dsc_dec_dpcd_caps dsc_caps;
6058
6059         struct dc_sink *sink = NULL;
6060
6061         drm_mode_init(&mode, drm_mode);
6062         memset(&saved_mode, 0, sizeof(saved_mode));
6063
6064         if (aconnector == NULL) {
6065                 DRM_ERROR("aconnector is NULL!\n");
6066                 return stream;
6067         }
6068
6069         drm_connector = &aconnector->base;
6070
6071         if (!aconnector->dc_sink) {
6072                 sink = create_fake_sink(aconnector);
6073                 if (!sink)
6074                         return stream;
6075         } else {
6076                 sink = aconnector->dc_sink;
6077                 dc_sink_retain(sink);
6078         }
6079
6080         stream = dc_create_stream_for_sink(sink);
6081
6082         if (stream == NULL) {
6083                 DRM_ERROR("Failed to create stream for sink!\n");
6084                 goto finish;
6085         }
6086
6087         stream->dm_stream_context = aconnector;
6088
6089         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6090                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
6091
6092         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
6093                 /* Search for preferred mode */
6094                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6095                         native_mode_found = true;
6096                         break;
6097                 }
6098         }
6099         if (!native_mode_found)
6100                 preferred_mode = list_first_entry_or_null(
6101                                 &aconnector->base.modes,
6102                                 struct drm_display_mode,
6103                                 head);
6104
6105         mode_refresh = drm_mode_vrefresh(&mode);
6106
6107         if (preferred_mode == NULL) {
6108                 /*
6109                  * This may not be an error, the use case is when we have no
6110                  * usermode calls to reset and set mode upon hotplug. In this
6111                  * case, we call set mode ourselves to restore the previous mode
6112                  * and the modelist may not be filled in time.
6113                  */
6114                 DRM_DEBUG_DRIVER("No preferred mode found\n");
6115         } else {
6116                 recalculate_timing = is_freesync_video_mode(&mode, aconnector);
6117                 if (recalculate_timing) {
6118                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6119                         drm_mode_copy(&saved_mode, &mode);
6120                         drm_mode_copy(&mode, freesync_mode);
6121                 } else {
6122                         decide_crtc_timing_for_drm_display_mode(
6123                                         &mode, preferred_mode, scale);
6124
6125                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
6126                 }
6127         }
6128
6129         if (recalculate_timing)
6130                 drm_mode_set_crtcinfo(&saved_mode, 0);
6131         else if (!old_stream)
6132                 drm_mode_set_crtcinfo(&mode, 0);
6133
6134         /*
6135          * If scaling is enabled and refresh rate didn't change
6136          * we copy the vic and polarities of the old timings
6137          */
6138         if (!scale || mode_refresh != preferred_refresh)
6139                 fill_stream_properties_from_drm_display_mode(
6140                         stream, &mode, &aconnector->base, con_state, NULL,
6141                         requested_bpc);
6142         else
6143                 fill_stream_properties_from_drm_display_mode(
6144                         stream, &mode, &aconnector->base, con_state, old_stream,
6145                         requested_bpc);
6146
6147         if (aconnector->timing_changed) {
6148                 drm_dbg(aconnector->base.dev,
6149                         "overriding timing for automated test, bpc %d, changing to %d\n",
6150                         stream->timing.display_color_depth,
6151                         aconnector->timing_requested->display_color_depth);
6152                 stream->timing = *aconnector->timing_requested;
6153         }
6154
6155         /* SST DSC determination policy */
6156         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6157         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6158                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6159
6160         update_stream_scaling_settings(&mode, dm_state, stream);
6161
6162         fill_audio_info(
6163                 &stream->audio_info,
6164                 drm_connector,
6165                 sink);
6166
6167         update_stream_signal(stream, sink);
6168
6169         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6170                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6171
6172         if (stream->link->psr_settings.psr_feature_enabled || stream->link->replay_settings.replay_feature_enabled) {
6173                 //
6174                 // should decide stream support vsc sdp colorimetry capability
6175                 // before building vsc info packet
6176                 //
6177                 stream->use_vsc_sdp_for_colorimetry = false;
6178                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6179                         stream->use_vsc_sdp_for_colorimetry =
6180                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6181                 } else {
6182                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6183                                 stream->use_vsc_sdp_for_colorimetry = true;
6184                 }
6185                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6186                         tf = TRANSFER_FUNC_GAMMA_22;
6187                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6188                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6189
6190         }
6191 finish:
6192         dc_sink_release(sink);
6193
6194         return stream;
6195 }
6196
6197 static enum drm_connector_status
6198 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6199 {
6200         bool connected;
6201         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6202
6203         /*
6204          * Notes:
6205          * 1. This interface is NOT called in context of HPD irq.
6206          * 2. This interface *is called* in context of user-mode ioctl. Which
6207          * makes it a bad place for *any* MST-related activity.
6208          */
6209
6210         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6211             !aconnector->fake_enable)
6212                 connected = (aconnector->dc_sink != NULL);
6213         else
6214                 connected = (aconnector->base.force == DRM_FORCE_ON ||
6215                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6216
6217         update_subconnector_property(aconnector);
6218
6219         return (connected ? connector_status_connected :
6220                         connector_status_disconnected);
6221 }
6222
6223 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6224                                             struct drm_connector_state *connector_state,
6225                                             struct drm_property *property,
6226                                             uint64_t val)
6227 {
6228         struct drm_device *dev = connector->dev;
6229         struct amdgpu_device *adev = drm_to_adev(dev);
6230         struct dm_connector_state *dm_old_state =
6231                 to_dm_connector_state(connector->state);
6232         struct dm_connector_state *dm_new_state =
6233                 to_dm_connector_state(connector_state);
6234
6235         int ret = -EINVAL;
6236
6237         if (property == dev->mode_config.scaling_mode_property) {
6238                 enum amdgpu_rmx_type rmx_type;
6239
6240                 switch (val) {
6241                 case DRM_MODE_SCALE_CENTER:
6242                         rmx_type = RMX_CENTER;
6243                         break;
6244                 case DRM_MODE_SCALE_ASPECT:
6245                         rmx_type = RMX_ASPECT;
6246                         break;
6247                 case DRM_MODE_SCALE_FULLSCREEN:
6248                         rmx_type = RMX_FULL;
6249                         break;
6250                 case DRM_MODE_SCALE_NONE:
6251                 default:
6252                         rmx_type = RMX_OFF;
6253                         break;
6254                 }
6255
6256                 if (dm_old_state->scaling == rmx_type)
6257                         return 0;
6258
6259                 dm_new_state->scaling = rmx_type;
6260                 ret = 0;
6261         } else if (property == adev->mode_info.underscan_hborder_property) {
6262                 dm_new_state->underscan_hborder = val;
6263                 ret = 0;
6264         } else if (property == adev->mode_info.underscan_vborder_property) {
6265                 dm_new_state->underscan_vborder = val;
6266                 ret = 0;
6267         } else if (property == adev->mode_info.underscan_property) {
6268                 dm_new_state->underscan_enable = val;
6269                 ret = 0;
6270         } else if (property == adev->mode_info.abm_level_property) {
6271                 dm_new_state->abm_level = val;
6272                 ret = 0;
6273         }
6274
6275         return ret;
6276 }
6277
6278 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6279                                             const struct drm_connector_state *state,
6280                                             struct drm_property *property,
6281                                             uint64_t *val)
6282 {
6283         struct drm_device *dev = connector->dev;
6284         struct amdgpu_device *adev = drm_to_adev(dev);
6285         struct dm_connector_state *dm_state =
6286                 to_dm_connector_state(state);
6287         int ret = -EINVAL;
6288
6289         if (property == dev->mode_config.scaling_mode_property) {
6290                 switch (dm_state->scaling) {
6291                 case RMX_CENTER:
6292                         *val = DRM_MODE_SCALE_CENTER;
6293                         break;
6294                 case RMX_ASPECT:
6295                         *val = DRM_MODE_SCALE_ASPECT;
6296                         break;
6297                 case RMX_FULL:
6298                         *val = DRM_MODE_SCALE_FULLSCREEN;
6299                         break;
6300                 case RMX_OFF:
6301                 default:
6302                         *val = DRM_MODE_SCALE_NONE;
6303                         break;
6304                 }
6305                 ret = 0;
6306         } else if (property == adev->mode_info.underscan_hborder_property) {
6307                 *val = dm_state->underscan_hborder;
6308                 ret = 0;
6309         } else if (property == adev->mode_info.underscan_vborder_property) {
6310                 *val = dm_state->underscan_vborder;
6311                 ret = 0;
6312         } else if (property == adev->mode_info.underscan_property) {
6313                 *val = dm_state->underscan_enable;
6314                 ret = 0;
6315         } else if (property == adev->mode_info.abm_level_property) {
6316                 *val = dm_state->abm_level;
6317                 ret = 0;
6318         }
6319
6320         return ret;
6321 }
6322
6323 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6324 {
6325         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6326
6327         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6328 }
6329
6330 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6331 {
6332         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6333         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6334         struct amdgpu_display_manager *dm = &adev->dm;
6335
6336         /*
6337          * Call only if mst_mgr was initialized before since it's not done
6338          * for all connector types.
6339          */
6340         if (aconnector->mst_mgr.dev)
6341                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6342
6343         if (aconnector->bl_idx != -1) {
6344                 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6345                 dm->backlight_dev[aconnector->bl_idx] = NULL;
6346         }
6347
6348         if (aconnector->dc_em_sink)
6349                 dc_sink_release(aconnector->dc_em_sink);
6350         aconnector->dc_em_sink = NULL;
6351         if (aconnector->dc_sink)
6352                 dc_sink_release(aconnector->dc_sink);
6353         aconnector->dc_sink = NULL;
6354
6355         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6356         drm_connector_unregister(connector);
6357         drm_connector_cleanup(connector);
6358         if (aconnector->i2c) {
6359                 i2c_del_adapter(&aconnector->i2c->base);
6360                 kfree(aconnector->i2c);
6361         }
6362         kfree(aconnector->dm_dp_aux.aux.name);
6363
6364         kfree(connector);
6365 }
6366
6367 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6368 {
6369         struct dm_connector_state *state =
6370                 to_dm_connector_state(connector->state);
6371
6372         if (connector->state)
6373                 __drm_atomic_helper_connector_destroy_state(connector->state);
6374
6375         kfree(state);
6376
6377         state = kzalloc(sizeof(*state), GFP_KERNEL);
6378
6379         if (state) {
6380                 state->scaling = RMX_OFF;
6381                 state->underscan_enable = false;
6382                 state->underscan_hborder = 0;
6383                 state->underscan_vborder = 0;
6384                 state->base.max_requested_bpc = 8;
6385                 state->vcpi_slots = 0;
6386                 state->pbn = 0;
6387
6388                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6389                         state->abm_level = amdgpu_dm_abm_level;
6390
6391                 __drm_atomic_helper_connector_reset(connector, &state->base);
6392         }
6393 }
6394
6395 struct drm_connector_state *
6396 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6397 {
6398         struct dm_connector_state *state =
6399                 to_dm_connector_state(connector->state);
6400
6401         struct dm_connector_state *new_state =
6402                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6403
6404         if (!new_state)
6405                 return NULL;
6406
6407         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6408
6409         new_state->freesync_capable = state->freesync_capable;
6410         new_state->abm_level = state->abm_level;
6411         new_state->scaling = state->scaling;
6412         new_state->underscan_enable = state->underscan_enable;
6413         new_state->underscan_hborder = state->underscan_hborder;
6414         new_state->underscan_vborder = state->underscan_vborder;
6415         new_state->vcpi_slots = state->vcpi_slots;
6416         new_state->pbn = state->pbn;
6417         return &new_state->base;
6418 }
6419
6420 static int
6421 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6422 {
6423         struct amdgpu_dm_connector *amdgpu_dm_connector =
6424                 to_amdgpu_dm_connector(connector);
6425         int r;
6426
6427         amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6428
6429         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6430             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6431                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6432                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6433                 if (r)
6434                         return r;
6435         }
6436
6437 #if defined(CONFIG_DEBUG_FS)
6438         connector_debugfs_init(amdgpu_dm_connector);
6439 #endif
6440
6441         return 0;
6442 }
6443
6444 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
6445 {
6446         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6447         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
6448         struct dc_link *dc_link = aconnector->dc_link;
6449         struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
6450         struct edid *edid;
6451
6452         /*
6453          * Note: drm_get_edid gets edid in the following order:
6454          * 1) override EDID if set via edid_override debugfs,
6455          * 2) firmware EDID if set via edid_firmware module parameter
6456          * 3) regular DDC read.
6457          */
6458         edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc);
6459         if (!edid) {
6460                 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
6461                 return;
6462         }
6463
6464         aconnector->edid = edid;
6465
6466         /* Update emulated (virtual) sink's EDID */
6467         if (dc_em_sink && dc_link) {
6468                 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
6469                 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH);
6470                 dm_helpers_parse_edid_caps(
6471                         dc_link,
6472                         &dc_em_sink->dc_edid,
6473                         &dc_em_sink->edid_caps);
6474         }
6475 }
6476
6477 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6478         .reset = amdgpu_dm_connector_funcs_reset,
6479         .detect = amdgpu_dm_connector_detect,
6480         .fill_modes = drm_helper_probe_single_connector_modes,
6481         .destroy = amdgpu_dm_connector_destroy,
6482         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6483         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6484         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6485         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6486         .late_register = amdgpu_dm_connector_late_register,
6487         .early_unregister = amdgpu_dm_connector_unregister,
6488         .force = amdgpu_dm_connector_funcs_force
6489 };
6490
6491 static int get_modes(struct drm_connector *connector)
6492 {
6493         return amdgpu_dm_connector_get_modes(connector);
6494 }
6495
6496 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6497 {
6498         struct drm_connector *connector = &aconnector->base;
6499         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(&aconnector->base);
6500         struct dc_sink_init_data init_params = {
6501                         .link = aconnector->dc_link,
6502                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6503         };
6504         struct edid *edid;
6505
6506         /*
6507          * Note: drm_get_edid gets edid in the following order:
6508          * 1) override EDID if set via edid_override debugfs,
6509          * 2) firmware EDID if set via edid_firmware module parameter
6510          * 3) regular DDC read.
6511          */
6512         edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc);
6513         if (!edid) {
6514                 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
6515                 return;
6516         }
6517
6518         aconnector->edid = edid;
6519
6520         aconnector->dc_em_sink = dc_link_add_remote_sink(
6521                 aconnector->dc_link,
6522                 (uint8_t *)edid,
6523                 (edid->extensions + 1) * EDID_LENGTH,
6524                 &init_params);
6525
6526         if (aconnector->base.force == DRM_FORCE_ON) {
6527                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6528                 aconnector->dc_link->local_sink :
6529                 aconnector->dc_em_sink;
6530                 dc_sink_retain(aconnector->dc_sink);
6531         }
6532 }
6533
6534 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6535 {
6536         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6537
6538         /*
6539          * In case of headless boot with force on for DP managed connector
6540          * Those settings have to be != 0 to get initial modeset
6541          */
6542         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6543                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6544                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6545         }
6546
6547         create_eml_sink(aconnector);
6548 }
6549
6550 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6551                                                 struct dc_stream_state *stream)
6552 {
6553         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6554         struct dc_plane_state *dc_plane_state = NULL;
6555         struct dc_state *dc_state = NULL;
6556
6557         if (!stream)
6558                 goto cleanup;
6559
6560         dc_plane_state = dc_create_plane_state(dc);
6561         if (!dc_plane_state)
6562                 goto cleanup;
6563
6564         dc_state = dc_create_state(dc);
6565         if (!dc_state)
6566                 goto cleanup;
6567
6568         /* populate stream to plane */
6569         dc_plane_state->src_rect.height  = stream->src.height;
6570         dc_plane_state->src_rect.width   = stream->src.width;
6571         dc_plane_state->dst_rect.height  = stream->src.height;
6572         dc_plane_state->dst_rect.width   = stream->src.width;
6573         dc_plane_state->clip_rect.height = stream->src.height;
6574         dc_plane_state->clip_rect.width  = stream->src.width;
6575         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6576         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6577         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6578         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6579         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6580         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6581         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6582         dc_plane_state->rotation = ROTATION_ANGLE_0;
6583         dc_plane_state->is_tiling_rotated = false;
6584         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6585
6586         dc_result = dc_validate_stream(dc, stream);
6587         if (dc_result == DC_OK)
6588                 dc_result = dc_validate_plane(dc, dc_plane_state);
6589
6590         if (dc_result == DC_OK)
6591                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6592
6593         if (dc_result == DC_OK && !dc_add_plane_to_context(
6594                                                 dc,
6595                                                 stream,
6596                                                 dc_plane_state,
6597                                                 dc_state))
6598                 dc_result = DC_FAIL_ATTACH_SURFACES;
6599
6600         if (dc_result == DC_OK)
6601                 dc_result = dc_validate_global_state(dc, dc_state, true);
6602
6603 cleanup:
6604         if (dc_state)
6605                 dc_release_state(dc_state);
6606
6607         if (dc_plane_state)
6608                 dc_plane_state_release(dc_plane_state);
6609
6610         return dc_result;
6611 }
6612
6613 struct dc_stream_state *
6614 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6615                                 const struct drm_display_mode *drm_mode,
6616                                 const struct dm_connector_state *dm_state,
6617                                 const struct dc_stream_state *old_stream)
6618 {
6619         struct drm_connector *connector = &aconnector->base;
6620         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6621         struct dc_stream_state *stream;
6622         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6623         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6624         enum dc_status dc_result = DC_OK;
6625
6626         do {
6627                 stream = create_stream_for_sink(aconnector, drm_mode,
6628                                                 dm_state, old_stream,
6629                                                 requested_bpc);
6630                 if (stream == NULL) {
6631                         DRM_ERROR("Failed to create stream for sink!\n");
6632                         break;
6633                 }
6634
6635                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6636                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6637                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6638
6639                 if (dc_result == DC_OK)
6640                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6641
6642                 if (dc_result != DC_OK) {
6643                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6644                                       drm_mode->hdisplay,
6645                                       drm_mode->vdisplay,
6646                                       drm_mode->clock,
6647                                       dc_result,
6648                                       dc_status_to_str(dc_result));
6649
6650                         dc_stream_release(stream);
6651                         stream = NULL;
6652                         requested_bpc -= 2; /* lower bpc to retry validation */
6653                 }
6654
6655         } while (stream == NULL && requested_bpc >= 6);
6656
6657         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6658                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6659
6660                 aconnector->force_yuv420_output = true;
6661                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6662                                                 dm_state, old_stream);
6663                 aconnector->force_yuv420_output = false;
6664         }
6665
6666         return stream;
6667 }
6668
6669 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6670                                    struct drm_display_mode *mode)
6671 {
6672         int result = MODE_ERROR;
6673         struct dc_sink *dc_sink;
6674         /* TODO: Unhardcode stream count */
6675         struct dc_stream_state *stream;
6676         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6677
6678         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6679                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6680                 return result;
6681
6682         /*
6683          * Only run this the first time mode_valid is called to initilialize
6684          * EDID mgmt
6685          */
6686         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6687                 !aconnector->dc_em_sink)
6688                 handle_edid_mgmt(aconnector);
6689
6690         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6691
6692         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6693                                 aconnector->base.force != DRM_FORCE_ON) {
6694                 DRM_ERROR("dc_sink is NULL!\n");
6695                 goto fail;
6696         }
6697
6698         drm_mode_set_crtcinfo(mode, 0);
6699
6700         stream = create_validate_stream_for_sink(aconnector, mode,
6701                                                  to_dm_connector_state(connector->state),
6702                                                  NULL);
6703         if (stream) {
6704                 dc_stream_release(stream);
6705                 result = MODE_OK;
6706         }
6707
6708 fail:
6709         /* TODO: error handling*/
6710         return result;
6711 }
6712
6713 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6714                                 struct dc_info_packet *out)
6715 {
6716         struct hdmi_drm_infoframe frame;
6717         unsigned char buf[30]; /* 26 + 4 */
6718         ssize_t len;
6719         int ret, i;
6720
6721         memset(out, 0, sizeof(*out));
6722
6723         if (!state->hdr_output_metadata)
6724                 return 0;
6725
6726         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6727         if (ret)
6728                 return ret;
6729
6730         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6731         if (len < 0)
6732                 return (int)len;
6733
6734         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6735         if (len != 30)
6736                 return -EINVAL;
6737
6738         /* Prepare the infopacket for DC. */
6739         switch (state->connector->connector_type) {
6740         case DRM_MODE_CONNECTOR_HDMIA:
6741                 out->hb0 = 0x87; /* type */
6742                 out->hb1 = 0x01; /* version */
6743                 out->hb2 = 0x1A; /* length */
6744                 out->sb[0] = buf[3]; /* checksum */
6745                 i = 1;
6746                 break;
6747
6748         case DRM_MODE_CONNECTOR_DisplayPort:
6749         case DRM_MODE_CONNECTOR_eDP:
6750                 out->hb0 = 0x00; /* sdp id, zero */
6751                 out->hb1 = 0x87; /* type */
6752                 out->hb2 = 0x1D; /* payload len - 1 */
6753                 out->hb3 = (0x13 << 2); /* sdp version */
6754                 out->sb[0] = 0x01; /* version */
6755                 out->sb[1] = 0x1A; /* length */
6756                 i = 2;
6757                 break;
6758
6759         default:
6760                 return -EINVAL;
6761         }
6762
6763         memcpy(&out->sb[i], &buf[4], 26);
6764         out->valid = true;
6765
6766         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6767                        sizeof(out->sb), false);
6768
6769         return 0;
6770 }
6771
6772 static int
6773 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6774                                  struct drm_atomic_state *state)
6775 {
6776         struct drm_connector_state *new_con_state =
6777                 drm_atomic_get_new_connector_state(state, conn);
6778         struct drm_connector_state *old_con_state =
6779                 drm_atomic_get_old_connector_state(state, conn);
6780         struct drm_crtc *crtc = new_con_state->crtc;
6781         struct drm_crtc_state *new_crtc_state;
6782         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6783         int ret;
6784
6785         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6786
6787         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6788                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6789                 if (ret < 0)
6790                         return ret;
6791         }
6792
6793         if (!crtc)
6794                 return 0;
6795
6796         if (new_con_state->colorspace != old_con_state->colorspace) {
6797                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6798                 if (IS_ERR(new_crtc_state))
6799                         return PTR_ERR(new_crtc_state);
6800
6801                 new_crtc_state->mode_changed = true;
6802         }
6803
6804         if (new_con_state->content_type != old_con_state->content_type) {
6805                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6806                 if (IS_ERR(new_crtc_state))
6807                         return PTR_ERR(new_crtc_state);
6808
6809                 new_crtc_state->mode_changed = true;
6810         }
6811
6812         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6813                 struct dc_info_packet hdr_infopacket;
6814
6815                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6816                 if (ret)
6817                         return ret;
6818
6819                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6820                 if (IS_ERR(new_crtc_state))
6821                         return PTR_ERR(new_crtc_state);
6822
6823                 /*
6824                  * DC considers the stream backends changed if the
6825                  * static metadata changes. Forcing the modeset also
6826                  * gives a simple way for userspace to switch from
6827                  * 8bpc to 10bpc when setting the metadata to enter
6828                  * or exit HDR.
6829                  *
6830                  * Changing the static metadata after it's been
6831                  * set is permissible, however. So only force a
6832                  * modeset if we're entering or exiting HDR.
6833                  */
6834                 new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
6835                         !old_con_state->hdr_output_metadata ||
6836                         !new_con_state->hdr_output_metadata;
6837         }
6838
6839         return 0;
6840 }
6841
6842 static const struct drm_connector_helper_funcs
6843 amdgpu_dm_connector_helper_funcs = {
6844         /*
6845          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6846          * modes will be filtered by drm_mode_validate_size(), and those modes
6847          * are missing after user start lightdm. So we need to renew modes list.
6848          * in get_modes call back, not just return the modes count
6849          */
6850         .get_modes = get_modes,
6851         .mode_valid = amdgpu_dm_connector_mode_valid,
6852         .atomic_check = amdgpu_dm_connector_atomic_check,
6853 };
6854
6855 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6856 {
6857
6858 }
6859
6860 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6861 {
6862         switch (display_color_depth) {
6863         case COLOR_DEPTH_666:
6864                 return 6;
6865         case COLOR_DEPTH_888:
6866                 return 8;
6867         case COLOR_DEPTH_101010:
6868                 return 10;
6869         case COLOR_DEPTH_121212:
6870                 return 12;
6871         case COLOR_DEPTH_141414:
6872                 return 14;
6873         case COLOR_DEPTH_161616:
6874                 return 16;
6875         default:
6876                 break;
6877         }
6878         return 0;
6879 }
6880
6881 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6882                                           struct drm_crtc_state *crtc_state,
6883                                           struct drm_connector_state *conn_state)
6884 {
6885         struct drm_atomic_state *state = crtc_state->state;
6886         struct drm_connector *connector = conn_state->connector;
6887         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6888         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6889         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6890         struct drm_dp_mst_topology_mgr *mst_mgr;
6891         struct drm_dp_mst_port *mst_port;
6892         struct drm_dp_mst_topology_state *mst_state;
6893         enum dc_color_depth color_depth;
6894         int clock, bpp = 0;
6895         bool is_y420 = false;
6896
6897         if (!aconnector->mst_output_port)
6898                 return 0;
6899
6900         mst_port = aconnector->mst_output_port;
6901         mst_mgr = &aconnector->mst_root->mst_mgr;
6902
6903         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6904                 return 0;
6905
6906         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6907         if (IS_ERR(mst_state))
6908                 return PTR_ERR(mst_state);
6909
6910         if (!mst_state->pbn_div)
6911                 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6912
6913         if (!state->duplicated) {
6914                 int max_bpc = conn_state->max_requested_bpc;
6915
6916                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6917                           aconnector->force_yuv420_output;
6918                 color_depth = convert_color_depth_from_display_info(connector,
6919                                                                     is_y420,
6920                                                                     max_bpc);
6921                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6922                 clock = adjusted_mode->clock;
6923                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6924         }
6925
6926         dm_new_connector_state->vcpi_slots =
6927                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6928                                               dm_new_connector_state->pbn);
6929         if (dm_new_connector_state->vcpi_slots < 0) {
6930                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6931                 return dm_new_connector_state->vcpi_slots;
6932         }
6933         return 0;
6934 }
6935
6936 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6937         .disable = dm_encoder_helper_disable,
6938         .atomic_check = dm_encoder_helper_atomic_check
6939 };
6940
6941 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6942                                             struct dc_state *dc_state,
6943                                             struct dsc_mst_fairness_vars *vars)
6944 {
6945         struct dc_stream_state *stream = NULL;
6946         struct drm_connector *connector;
6947         struct drm_connector_state *new_con_state;
6948         struct amdgpu_dm_connector *aconnector;
6949         struct dm_connector_state *dm_conn_state;
6950         int i, j, ret;
6951         int vcpi, pbn_div, pbn, slot_num = 0;
6952
6953         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6954
6955                 aconnector = to_amdgpu_dm_connector(connector);
6956
6957                 if (!aconnector->mst_output_port)
6958                         continue;
6959
6960                 if (!new_con_state || !new_con_state->crtc)
6961                         continue;
6962
6963                 dm_conn_state = to_dm_connector_state(new_con_state);
6964
6965                 for (j = 0; j < dc_state->stream_count; j++) {
6966                         stream = dc_state->streams[j];
6967                         if (!stream)
6968                                 continue;
6969
6970                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6971                                 break;
6972
6973                         stream = NULL;
6974                 }
6975
6976                 if (!stream)
6977                         continue;
6978
6979                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6980                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6981                 for (j = 0; j < dc_state->stream_count; j++) {
6982                         if (vars[j].aconnector == aconnector) {
6983                                 pbn = vars[j].pbn;
6984                                 break;
6985                         }
6986                 }
6987
6988                 if (j == dc_state->stream_count)
6989                         continue;
6990
6991                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6992
6993                 if (stream->timing.flags.DSC != 1) {
6994                         dm_conn_state->pbn = pbn;
6995                         dm_conn_state->vcpi_slots = slot_num;
6996
6997                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6998                                                            dm_conn_state->pbn, false);
6999                         if (ret < 0)
7000                                 return ret;
7001
7002                         continue;
7003                 }
7004
7005                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
7006                 if (vcpi < 0)
7007                         return vcpi;
7008
7009                 dm_conn_state->pbn = pbn;
7010                 dm_conn_state->vcpi_slots = vcpi;
7011         }
7012         return 0;
7013 }
7014
7015 static int to_drm_connector_type(enum signal_type st)
7016 {
7017         switch (st) {
7018         case SIGNAL_TYPE_HDMI_TYPE_A:
7019                 return DRM_MODE_CONNECTOR_HDMIA;
7020         case SIGNAL_TYPE_EDP:
7021                 return DRM_MODE_CONNECTOR_eDP;
7022         case SIGNAL_TYPE_LVDS:
7023                 return DRM_MODE_CONNECTOR_LVDS;
7024         case SIGNAL_TYPE_RGB:
7025                 return DRM_MODE_CONNECTOR_VGA;
7026         case SIGNAL_TYPE_DISPLAY_PORT:
7027         case SIGNAL_TYPE_DISPLAY_PORT_MST:
7028                 return DRM_MODE_CONNECTOR_DisplayPort;
7029         case SIGNAL_TYPE_DVI_DUAL_LINK:
7030         case SIGNAL_TYPE_DVI_SINGLE_LINK:
7031                 return DRM_MODE_CONNECTOR_DVID;
7032         case SIGNAL_TYPE_VIRTUAL:
7033                 return DRM_MODE_CONNECTOR_VIRTUAL;
7034
7035         default:
7036                 return DRM_MODE_CONNECTOR_Unknown;
7037         }
7038 }
7039
7040 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
7041 {
7042         struct drm_encoder *encoder;
7043
7044         /* There is only one encoder per connector */
7045         drm_connector_for_each_possible_encoder(connector, encoder)
7046                 return encoder;
7047
7048         return NULL;
7049 }
7050
7051 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
7052 {
7053         struct drm_encoder *encoder;
7054         struct amdgpu_encoder *amdgpu_encoder;
7055
7056         encoder = amdgpu_dm_connector_to_encoder(connector);
7057
7058         if (encoder == NULL)
7059                 return;
7060
7061         amdgpu_encoder = to_amdgpu_encoder(encoder);
7062
7063         amdgpu_encoder->native_mode.clock = 0;
7064
7065         if (!list_empty(&connector->probed_modes)) {
7066                 struct drm_display_mode *preferred_mode = NULL;
7067
7068                 list_for_each_entry(preferred_mode,
7069                                     &connector->probed_modes,
7070                                     head) {
7071                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
7072                                 amdgpu_encoder->native_mode = *preferred_mode;
7073
7074                         break;
7075                 }
7076
7077         }
7078 }
7079
7080 static struct drm_display_mode *
7081 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
7082                              char *name,
7083                              int hdisplay, int vdisplay)
7084 {
7085         struct drm_device *dev = encoder->dev;
7086         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7087         struct drm_display_mode *mode = NULL;
7088         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7089
7090         mode = drm_mode_duplicate(dev, native_mode);
7091
7092         if (mode == NULL)
7093                 return NULL;
7094
7095         mode->hdisplay = hdisplay;
7096         mode->vdisplay = vdisplay;
7097         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7098         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
7099
7100         return mode;
7101
7102 }
7103
7104 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
7105                                                  struct drm_connector *connector)
7106 {
7107         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7108         struct drm_display_mode *mode = NULL;
7109         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7110         struct amdgpu_dm_connector *amdgpu_dm_connector =
7111                                 to_amdgpu_dm_connector(connector);
7112         int i;
7113         int n;
7114         struct mode_size {
7115                 char name[DRM_DISPLAY_MODE_LEN];
7116                 int w;
7117                 int h;
7118         } common_modes[] = {
7119                 {  "640x480",  640,  480},
7120                 {  "800x600",  800,  600},
7121                 { "1024x768", 1024,  768},
7122                 { "1280x720", 1280,  720},
7123                 { "1280x800", 1280,  800},
7124                 {"1280x1024", 1280, 1024},
7125                 { "1440x900", 1440,  900},
7126                 {"1680x1050", 1680, 1050},
7127                 {"1600x1200", 1600, 1200},
7128                 {"1920x1080", 1920, 1080},
7129                 {"1920x1200", 1920, 1200}
7130         };
7131
7132         n = ARRAY_SIZE(common_modes);
7133
7134         for (i = 0; i < n; i++) {
7135                 struct drm_display_mode *curmode = NULL;
7136                 bool mode_existed = false;
7137
7138                 if (common_modes[i].w > native_mode->hdisplay ||
7139                     common_modes[i].h > native_mode->vdisplay ||
7140                    (common_modes[i].w == native_mode->hdisplay &&
7141                     common_modes[i].h == native_mode->vdisplay))
7142                         continue;
7143
7144                 list_for_each_entry(curmode, &connector->probed_modes, head) {
7145                         if (common_modes[i].w == curmode->hdisplay &&
7146                             common_modes[i].h == curmode->vdisplay) {
7147                                 mode_existed = true;
7148                                 break;
7149                         }
7150                 }
7151
7152                 if (mode_existed)
7153                         continue;
7154
7155                 mode = amdgpu_dm_create_common_mode(encoder,
7156                                 common_modes[i].name, common_modes[i].w,
7157                                 common_modes[i].h);
7158                 if (!mode)
7159                         continue;
7160
7161                 drm_mode_probed_add(connector, mode);
7162                 amdgpu_dm_connector->num_modes++;
7163         }
7164 }
7165
7166 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7167 {
7168         struct drm_encoder *encoder;
7169         struct amdgpu_encoder *amdgpu_encoder;
7170         const struct drm_display_mode *native_mode;
7171
7172         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7173             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7174                 return;
7175
7176         mutex_lock(&connector->dev->mode_config.mutex);
7177         amdgpu_dm_connector_get_modes(connector);
7178         mutex_unlock(&connector->dev->mode_config.mutex);
7179
7180         encoder = amdgpu_dm_connector_to_encoder(connector);
7181         if (!encoder)
7182                 return;
7183
7184         amdgpu_encoder = to_amdgpu_encoder(encoder);
7185
7186         native_mode = &amdgpu_encoder->native_mode;
7187         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7188                 return;
7189
7190         drm_connector_set_panel_orientation_with_quirk(connector,
7191                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7192                                                        native_mode->hdisplay,
7193                                                        native_mode->vdisplay);
7194 }
7195
7196 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7197                                               struct edid *edid)
7198 {
7199         struct amdgpu_dm_connector *amdgpu_dm_connector =
7200                         to_amdgpu_dm_connector(connector);
7201
7202         if (edid) {
7203                 /* empty probed_modes */
7204                 INIT_LIST_HEAD(&connector->probed_modes);
7205                 amdgpu_dm_connector->num_modes =
7206                                 drm_add_edid_modes(connector, edid);
7207
7208                 /* sorting the probed modes before calling function
7209                  * amdgpu_dm_get_native_mode() since EDID can have
7210                  * more than one preferred mode. The modes that are
7211                  * later in the probed mode list could be of higher
7212                  * and preferred resolution. For example, 3840x2160
7213                  * resolution in base EDID preferred timing and 4096x2160
7214                  * preferred resolution in DID extension block later.
7215                  */
7216                 drm_mode_sort(&connector->probed_modes);
7217                 amdgpu_dm_get_native_mode(connector);
7218
7219                 /* Freesync capabilities are reset by calling
7220                  * drm_add_edid_modes() and need to be
7221                  * restored here.
7222                  */
7223                 amdgpu_dm_update_freesync_caps(connector, edid);
7224         } else {
7225                 amdgpu_dm_connector->num_modes = 0;
7226         }
7227 }
7228
7229 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7230                               struct drm_display_mode *mode)
7231 {
7232         struct drm_display_mode *m;
7233
7234         list_for_each_entry(m, &aconnector->base.probed_modes, head) {
7235                 if (drm_mode_equal(m, mode))
7236                         return true;
7237         }
7238
7239         return false;
7240 }
7241
7242 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7243 {
7244         const struct drm_display_mode *m;
7245         struct drm_display_mode *new_mode;
7246         uint i;
7247         u32 new_modes_count = 0;
7248
7249         /* Standard FPS values
7250          *
7251          * 23.976       - TV/NTSC
7252          * 24           - Cinema
7253          * 25           - TV/PAL
7254          * 29.97        - TV/NTSC
7255          * 30           - TV/NTSC
7256          * 48           - Cinema HFR
7257          * 50           - TV/PAL
7258          * 60           - Commonly used
7259          * 48,72,96,120 - Multiples of 24
7260          */
7261         static const u32 common_rates[] = {
7262                 23976, 24000, 25000, 29970, 30000,
7263                 48000, 50000, 60000, 72000, 96000, 120000
7264         };
7265
7266         /*
7267          * Find mode with highest refresh rate with the same resolution
7268          * as the preferred mode. Some monitors report a preferred mode
7269          * with lower resolution than the highest refresh rate supported.
7270          */
7271
7272         m = get_highest_refresh_rate_mode(aconnector, true);
7273         if (!m)
7274                 return 0;
7275
7276         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7277                 u64 target_vtotal, target_vtotal_diff;
7278                 u64 num, den;
7279
7280                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7281                         continue;
7282
7283                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7284                     common_rates[i] > aconnector->max_vfreq * 1000)
7285                         continue;
7286
7287                 num = (unsigned long long)m->clock * 1000 * 1000;
7288                 den = common_rates[i] * (unsigned long long)m->htotal;
7289                 target_vtotal = div_u64(num, den);
7290                 target_vtotal_diff = target_vtotal - m->vtotal;
7291
7292                 /* Check for illegal modes */
7293                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7294                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7295                     m->vtotal + target_vtotal_diff < m->vsync_end)
7296                         continue;
7297
7298                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7299                 if (!new_mode)
7300                         goto out;
7301
7302                 new_mode->vtotal += (u16)target_vtotal_diff;
7303                 new_mode->vsync_start += (u16)target_vtotal_diff;
7304                 new_mode->vsync_end += (u16)target_vtotal_diff;
7305                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7306                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7307
7308                 if (!is_duplicate_mode(aconnector, new_mode)) {
7309                         drm_mode_probed_add(&aconnector->base, new_mode);
7310                         new_modes_count += 1;
7311                 } else
7312                         drm_mode_destroy(aconnector->base.dev, new_mode);
7313         }
7314  out:
7315         return new_modes_count;
7316 }
7317
7318 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7319                                                    struct edid *edid)
7320 {
7321         struct amdgpu_dm_connector *amdgpu_dm_connector =
7322                 to_amdgpu_dm_connector(connector);
7323
7324         if (!edid)
7325                 return;
7326
7327         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7328                 amdgpu_dm_connector->num_modes +=
7329                         add_fs_modes(amdgpu_dm_connector);
7330 }
7331
7332 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7333 {
7334         struct amdgpu_dm_connector *amdgpu_dm_connector =
7335                         to_amdgpu_dm_connector(connector);
7336         struct drm_encoder *encoder;
7337         struct edid *edid = amdgpu_dm_connector->edid;
7338         struct dc_link_settings *verified_link_cap =
7339                         &amdgpu_dm_connector->dc_link->verified_link_cap;
7340         const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7341
7342         encoder = amdgpu_dm_connector_to_encoder(connector);
7343
7344         if (!drm_edid_is_valid(edid)) {
7345                 amdgpu_dm_connector->num_modes =
7346                                 drm_add_modes_noedid(connector, 640, 480);
7347                 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7348                         amdgpu_dm_connector->num_modes +=
7349                                 drm_add_modes_noedid(connector, 1920, 1080);
7350         } else {
7351                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7352                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7353                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7354         }
7355         amdgpu_dm_fbc_init(connector);
7356
7357         return amdgpu_dm_connector->num_modes;
7358 }
7359
7360 static const u32 supported_colorspaces =
7361         BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
7362         BIT(DRM_MODE_COLORIMETRY_OPRGB) |
7363         BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
7364         BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
7365
7366 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7367                                      struct amdgpu_dm_connector *aconnector,
7368                                      int connector_type,
7369                                      struct dc_link *link,
7370                                      int link_index)
7371 {
7372         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7373
7374         /*
7375          * Some of the properties below require access to state, like bpc.
7376          * Allocate some default initial connector state with our reset helper.
7377          */
7378         if (aconnector->base.funcs->reset)
7379                 aconnector->base.funcs->reset(&aconnector->base);
7380
7381         aconnector->connector_id = link_index;
7382         aconnector->bl_idx = -1;
7383         aconnector->dc_link = link;
7384         aconnector->base.interlace_allowed = false;
7385         aconnector->base.doublescan_allowed = false;
7386         aconnector->base.stereo_allowed = false;
7387         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7388         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7389         aconnector->audio_inst = -1;
7390         aconnector->pack_sdp_v1_3 = false;
7391         aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7392         memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7393         mutex_init(&aconnector->hpd_lock);
7394         mutex_init(&aconnector->handle_mst_msg_ready);
7395
7396         /*
7397          * configure support HPD hot plug connector_>polled default value is 0
7398          * which means HPD hot plug not supported
7399          */
7400         switch (connector_type) {
7401         case DRM_MODE_CONNECTOR_HDMIA:
7402                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7403                 aconnector->base.ycbcr_420_allowed =
7404                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7405                 break;
7406         case DRM_MODE_CONNECTOR_DisplayPort:
7407                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7408                 link->link_enc = link_enc_cfg_get_link_enc(link);
7409                 ASSERT(link->link_enc);
7410                 if (link->link_enc)
7411                         aconnector->base.ycbcr_420_allowed =
7412                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7413                 break;
7414         case DRM_MODE_CONNECTOR_DVID:
7415                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7416                 break;
7417         default:
7418                 break;
7419         }
7420
7421         drm_object_attach_property(&aconnector->base.base,
7422                                 dm->ddev->mode_config.scaling_mode_property,
7423                                 DRM_MODE_SCALE_NONE);
7424
7425         drm_object_attach_property(&aconnector->base.base,
7426                                 adev->mode_info.underscan_property,
7427                                 UNDERSCAN_OFF);
7428         drm_object_attach_property(&aconnector->base.base,
7429                                 adev->mode_info.underscan_hborder_property,
7430                                 0);
7431         drm_object_attach_property(&aconnector->base.base,
7432                                 adev->mode_info.underscan_vborder_property,
7433                                 0);
7434
7435         if (!aconnector->mst_root)
7436                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7437
7438         aconnector->base.state->max_bpc = 16;
7439         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7440
7441         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7442             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7443                 drm_object_attach_property(&aconnector->base.base,
7444                                 adev->mode_info.abm_level_property, 0);
7445         }
7446
7447         if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7448                 /* Content Type is currently only implemented for HDMI. */
7449                 drm_connector_attach_content_type_property(&aconnector->base);
7450         }
7451
7452         if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7453                 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))
7454                         drm_connector_attach_colorspace_property(&aconnector->base);
7455         } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) ||
7456                    connector_type == DRM_MODE_CONNECTOR_eDP) {
7457                 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))
7458                         drm_connector_attach_colorspace_property(&aconnector->base);
7459         }
7460
7461         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7462             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7463             connector_type == DRM_MODE_CONNECTOR_eDP) {
7464                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7465
7466                 if (!aconnector->mst_root)
7467                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7468
7469                 if (adev->dm.hdcp_workqueue)
7470                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7471         }
7472 }
7473
7474 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7475                               struct i2c_msg *msgs, int num)
7476 {
7477         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7478         struct ddc_service *ddc_service = i2c->ddc_service;
7479         struct i2c_command cmd;
7480         int i;
7481         int result = -EIO;
7482
7483         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7484
7485         if (!cmd.payloads)
7486                 return result;
7487
7488         cmd.number_of_payloads = num;
7489         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7490         cmd.speed = 100;
7491
7492         for (i = 0; i < num; i++) {
7493                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7494                 cmd.payloads[i].address = msgs[i].addr;
7495                 cmd.payloads[i].length = msgs[i].len;
7496                 cmd.payloads[i].data = msgs[i].buf;
7497         }
7498
7499         if (dc_submit_i2c(
7500                         ddc_service->ctx->dc,
7501                         ddc_service->link->link_index,
7502                         &cmd))
7503                 result = num;
7504
7505         kfree(cmd.payloads);
7506         return result;
7507 }
7508
7509 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7510 {
7511         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7512 }
7513
7514 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7515         .master_xfer = amdgpu_dm_i2c_xfer,
7516         .functionality = amdgpu_dm_i2c_func,
7517 };
7518
7519 static struct amdgpu_i2c_adapter *
7520 create_i2c(struct ddc_service *ddc_service,
7521            int link_index,
7522            int *res)
7523 {
7524         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7525         struct amdgpu_i2c_adapter *i2c;
7526
7527         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7528         if (!i2c)
7529                 return NULL;
7530         i2c->base.owner = THIS_MODULE;
7531         i2c->base.class = I2C_CLASS_DDC;
7532         i2c->base.dev.parent = &adev->pdev->dev;
7533         i2c->base.algo = &amdgpu_dm_i2c_algo;
7534         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7535         i2c_set_adapdata(&i2c->base, i2c);
7536         i2c->ddc_service = ddc_service;
7537
7538         return i2c;
7539 }
7540
7541
7542 /*
7543  * Note: this function assumes that dc_link_detect() was called for the
7544  * dc_link which will be represented by this aconnector.
7545  */
7546 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7547                                     struct amdgpu_dm_connector *aconnector,
7548                                     u32 link_index,
7549                                     struct amdgpu_encoder *aencoder)
7550 {
7551         int res = 0;
7552         int connector_type;
7553         struct dc *dc = dm->dc;
7554         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7555         struct amdgpu_i2c_adapter *i2c;
7556
7557         link->priv = aconnector;
7558
7559
7560         i2c = create_i2c(link->ddc, link->link_index, &res);
7561         if (!i2c) {
7562                 DRM_ERROR("Failed to create i2c adapter data\n");
7563                 return -ENOMEM;
7564         }
7565
7566         aconnector->i2c = i2c;
7567         res = i2c_add_adapter(&i2c->base);
7568
7569         if (res) {
7570                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7571                 goto out_free;
7572         }
7573
7574         connector_type = to_drm_connector_type(link->connector_signal);
7575
7576         res = drm_connector_init_with_ddc(
7577                         dm->ddev,
7578                         &aconnector->base,
7579                         &amdgpu_dm_connector_funcs,
7580                         connector_type,
7581                         &i2c->base);
7582
7583         if (res) {
7584                 DRM_ERROR("connector_init failed\n");
7585                 aconnector->connector_id = -1;
7586                 goto out_free;
7587         }
7588
7589         drm_connector_helper_add(
7590                         &aconnector->base,
7591                         &amdgpu_dm_connector_helper_funcs);
7592
7593         amdgpu_dm_connector_init_helper(
7594                 dm,
7595                 aconnector,
7596                 connector_type,
7597                 link,
7598                 link_index);
7599
7600         drm_connector_attach_encoder(
7601                 &aconnector->base, &aencoder->base);
7602
7603         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7604                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7605                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7606
7607 out_free:
7608         if (res) {
7609                 kfree(i2c);
7610                 aconnector->i2c = NULL;
7611         }
7612         return res;
7613 }
7614
7615 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7616 {
7617         switch (adev->mode_info.num_crtc) {
7618         case 1:
7619                 return 0x1;
7620         case 2:
7621                 return 0x3;
7622         case 3:
7623                 return 0x7;
7624         case 4:
7625                 return 0xf;
7626         case 5:
7627                 return 0x1f;
7628         case 6:
7629         default:
7630                 return 0x3f;
7631         }
7632 }
7633
7634 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7635                                   struct amdgpu_encoder *aencoder,
7636                                   uint32_t link_index)
7637 {
7638         struct amdgpu_device *adev = drm_to_adev(dev);
7639
7640         int res = drm_encoder_init(dev,
7641                                    &aencoder->base,
7642                                    &amdgpu_dm_encoder_funcs,
7643                                    DRM_MODE_ENCODER_TMDS,
7644                                    NULL);
7645
7646         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7647
7648         if (!res)
7649                 aencoder->encoder_id = link_index;
7650         else
7651                 aencoder->encoder_id = -1;
7652
7653         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7654
7655         return res;
7656 }
7657
7658 static void manage_dm_interrupts(struct amdgpu_device *adev,
7659                                  struct amdgpu_crtc *acrtc,
7660                                  bool enable)
7661 {
7662         /*
7663          * We have no guarantee that the frontend index maps to the same
7664          * backend index - some even map to more than one.
7665          *
7666          * TODO: Use a different interrupt or check DC itself for the mapping.
7667          */
7668         int irq_type =
7669                 amdgpu_display_crtc_idx_to_irq_type(
7670                         adev,
7671                         acrtc->crtc_id);
7672
7673         if (enable) {
7674                 drm_crtc_vblank_on(&acrtc->base);
7675                 amdgpu_irq_get(
7676                         adev,
7677                         &adev->pageflip_irq,
7678                         irq_type);
7679 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7680                 amdgpu_irq_get(
7681                         adev,
7682                         &adev->vline0_irq,
7683                         irq_type);
7684 #endif
7685         } else {
7686 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7687                 amdgpu_irq_put(
7688                         adev,
7689                         &adev->vline0_irq,
7690                         irq_type);
7691 #endif
7692                 amdgpu_irq_put(
7693                         adev,
7694                         &adev->pageflip_irq,
7695                         irq_type);
7696                 drm_crtc_vblank_off(&acrtc->base);
7697         }
7698 }
7699
7700 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7701                                       struct amdgpu_crtc *acrtc)
7702 {
7703         int irq_type =
7704                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7705
7706         /**
7707          * This reads the current state for the IRQ and force reapplies
7708          * the setting to hardware.
7709          */
7710         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7711 }
7712
7713 static bool
7714 is_scaling_state_different(const struct dm_connector_state *dm_state,
7715                            const struct dm_connector_state *old_dm_state)
7716 {
7717         if (dm_state->scaling != old_dm_state->scaling)
7718                 return true;
7719         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7720                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7721                         return true;
7722         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7723                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7724                         return true;
7725         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7726                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7727                 return true;
7728         return false;
7729 }
7730
7731 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7732                                             struct drm_crtc_state *old_crtc_state,
7733                                             struct drm_connector_state *new_conn_state,
7734                                             struct drm_connector_state *old_conn_state,
7735                                             const struct drm_connector *connector,
7736                                             struct hdcp_workqueue *hdcp_w)
7737 {
7738         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7739         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7740
7741         pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7742                 connector->index, connector->status, connector->dpms);
7743         pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7744                 old_conn_state->content_protection, new_conn_state->content_protection);
7745
7746         if (old_crtc_state)
7747                 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7748                 old_crtc_state->enable,
7749                 old_crtc_state->active,
7750                 old_crtc_state->mode_changed,
7751                 old_crtc_state->active_changed,
7752                 old_crtc_state->connectors_changed);
7753
7754         if (new_crtc_state)
7755                 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7756                 new_crtc_state->enable,
7757                 new_crtc_state->active,
7758                 new_crtc_state->mode_changed,
7759                 new_crtc_state->active_changed,
7760                 new_crtc_state->connectors_changed);
7761
7762         /* hdcp content type change */
7763         if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7764             new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7765                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7766                 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7767                 return true;
7768         }
7769
7770         /* CP is being re enabled, ignore this */
7771         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7772             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7773                 if (new_crtc_state && new_crtc_state->mode_changed) {
7774                         new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7775                         pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7776                         return true;
7777                 }
7778                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7779                 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7780                 return false;
7781         }
7782
7783         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7784          *
7785          * Handles:     UNDESIRED -> ENABLED
7786          */
7787         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7788             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7789                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7790
7791         /* Stream removed and re-enabled
7792          *
7793          * Can sometimes overlap with the HPD case,
7794          * thus set update_hdcp to false to avoid
7795          * setting HDCP multiple times.
7796          *
7797          * Handles:     DESIRED -> DESIRED (Special case)
7798          */
7799         if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7800                 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7801                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7802                 dm_con_state->update_hdcp = false;
7803                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7804                         __func__);
7805                 return true;
7806         }
7807
7808         /* Hot-plug, headless s3, dpms
7809          *
7810          * Only start HDCP if the display is connected/enabled.
7811          * update_hdcp flag will be set to false until the next
7812          * HPD comes in.
7813          *
7814          * Handles:     DESIRED -> DESIRED (Special case)
7815          */
7816         if (dm_con_state->update_hdcp &&
7817         new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7818         connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7819                 dm_con_state->update_hdcp = false;
7820                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7821                         __func__);
7822                 return true;
7823         }
7824
7825         if (old_conn_state->content_protection == new_conn_state->content_protection) {
7826                 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7827                         if (new_crtc_state && new_crtc_state->mode_changed) {
7828                                 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7829                                         __func__);
7830                                 return true;
7831                         }
7832                         pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7833                                 __func__);
7834                         return false;
7835                 }
7836
7837                 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7838                 return false;
7839         }
7840
7841         if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7842                 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7843                         __func__);
7844                 return true;
7845         }
7846
7847         pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7848         return false;
7849 }
7850
7851 static void remove_stream(struct amdgpu_device *adev,
7852                           struct amdgpu_crtc *acrtc,
7853                           struct dc_stream_state *stream)
7854 {
7855         /* this is the update mode case */
7856
7857         acrtc->otg_inst = -1;
7858         acrtc->enabled = false;
7859 }
7860
7861 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7862 {
7863
7864         assert_spin_locked(&acrtc->base.dev->event_lock);
7865         WARN_ON(acrtc->event);
7866
7867         acrtc->event = acrtc->base.state->event;
7868
7869         /* Set the flip status */
7870         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7871
7872         /* Mark this event as consumed */
7873         acrtc->base.state->event = NULL;
7874
7875         drm_dbg_state(acrtc->base.dev,
7876                       "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7877                       acrtc->crtc_id);
7878 }
7879
7880 static void update_freesync_state_on_stream(
7881         struct amdgpu_display_manager *dm,
7882         struct dm_crtc_state *new_crtc_state,
7883         struct dc_stream_state *new_stream,
7884         struct dc_plane_state *surface,
7885         u32 flip_timestamp_in_us)
7886 {
7887         struct mod_vrr_params vrr_params;
7888         struct dc_info_packet vrr_infopacket = {0};
7889         struct amdgpu_device *adev = dm->adev;
7890         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7891         unsigned long flags;
7892         bool pack_sdp_v1_3 = false;
7893         struct amdgpu_dm_connector *aconn;
7894         enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7895
7896         if (!new_stream)
7897                 return;
7898
7899         /*
7900          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7901          * For now it's sufficient to just guard against these conditions.
7902          */
7903
7904         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7905                 return;
7906
7907         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7908         vrr_params = acrtc->dm_irq_params.vrr_params;
7909
7910         if (surface) {
7911                 mod_freesync_handle_preflip(
7912                         dm->freesync_module,
7913                         surface,
7914                         new_stream,
7915                         flip_timestamp_in_us,
7916                         &vrr_params);
7917
7918                 if (adev->family < AMDGPU_FAMILY_AI &&
7919                     amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7920                         mod_freesync_handle_v_update(dm->freesync_module,
7921                                                      new_stream, &vrr_params);
7922
7923                         /* Need to call this before the frame ends. */
7924                         dc_stream_adjust_vmin_vmax(dm->dc,
7925                                                    new_crtc_state->stream,
7926                                                    &vrr_params.adjust);
7927                 }
7928         }
7929
7930         aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7931
7932         if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) {
7933                 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7934
7935                 if (aconn->vsdb_info.amd_vsdb_version == 1)
7936                         packet_type = PACKET_TYPE_FS_V1;
7937                 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7938                         packet_type = PACKET_TYPE_FS_V2;
7939                 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7940                         packet_type = PACKET_TYPE_FS_V3;
7941
7942                 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7943                                         &new_stream->adaptive_sync_infopacket);
7944         }
7945
7946         mod_freesync_build_vrr_infopacket(
7947                 dm->freesync_module,
7948                 new_stream,
7949                 &vrr_params,
7950                 packet_type,
7951                 TRANSFER_FUNC_UNKNOWN,
7952                 &vrr_infopacket,
7953                 pack_sdp_v1_3);
7954
7955         new_crtc_state->freesync_vrr_info_changed |=
7956                 (memcmp(&new_crtc_state->vrr_infopacket,
7957                         &vrr_infopacket,
7958                         sizeof(vrr_infopacket)) != 0);
7959
7960         acrtc->dm_irq_params.vrr_params = vrr_params;
7961         new_crtc_state->vrr_infopacket = vrr_infopacket;
7962
7963         new_stream->vrr_infopacket = vrr_infopacket;
7964         new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7965
7966         if (new_crtc_state->freesync_vrr_info_changed)
7967                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7968                               new_crtc_state->base.crtc->base.id,
7969                               (int)new_crtc_state->base.vrr_enabled,
7970                               (int)vrr_params.state);
7971
7972         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7973 }
7974
7975 static void update_stream_irq_parameters(
7976         struct amdgpu_display_manager *dm,
7977         struct dm_crtc_state *new_crtc_state)
7978 {
7979         struct dc_stream_state *new_stream = new_crtc_state->stream;
7980         struct mod_vrr_params vrr_params;
7981         struct mod_freesync_config config = new_crtc_state->freesync_config;
7982         struct amdgpu_device *adev = dm->adev;
7983         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7984         unsigned long flags;
7985
7986         if (!new_stream)
7987                 return;
7988
7989         /*
7990          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7991          * For now it's sufficient to just guard against these conditions.
7992          */
7993         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7994                 return;
7995
7996         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7997         vrr_params = acrtc->dm_irq_params.vrr_params;
7998
7999         if (new_crtc_state->vrr_supported &&
8000             config.min_refresh_in_uhz &&
8001             config.max_refresh_in_uhz) {
8002                 /*
8003                  * if freesync compatible mode was set, config.state will be set
8004                  * in atomic check
8005                  */
8006                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
8007                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
8008                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
8009                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
8010                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
8011                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
8012                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
8013                 } else {
8014                         config.state = new_crtc_state->base.vrr_enabled ?
8015                                                      VRR_STATE_ACTIVE_VARIABLE :
8016                                                      VRR_STATE_INACTIVE;
8017                 }
8018         } else {
8019                 config.state = VRR_STATE_UNSUPPORTED;
8020         }
8021
8022         mod_freesync_build_vrr_params(dm->freesync_module,
8023                                       new_stream,
8024                                       &config, &vrr_params);
8025
8026         new_crtc_state->freesync_config = config;
8027         /* Copy state for access from DM IRQ handler */
8028         acrtc->dm_irq_params.freesync_config = config;
8029         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
8030         acrtc->dm_irq_params.vrr_params = vrr_params;
8031         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8032 }
8033
8034 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
8035                                             struct dm_crtc_state *new_state)
8036 {
8037         bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
8038         bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
8039
8040         if (!old_vrr_active && new_vrr_active) {
8041                 /* Transition VRR inactive -> active:
8042                  * While VRR is active, we must not disable vblank irq, as a
8043                  * reenable after disable would compute bogus vblank/pflip
8044                  * timestamps if it likely happened inside display front-porch.
8045                  *
8046                  * We also need vupdate irq for the actual core vblank handling
8047                  * at end of vblank.
8048                  */
8049                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
8050                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
8051                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
8052                                  __func__, new_state->base.crtc->base.id);
8053         } else if (old_vrr_active && !new_vrr_active) {
8054                 /* Transition VRR active -> inactive:
8055                  * Allow vblank irq disable again for fixed refresh rate.
8056                  */
8057                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
8058                 drm_crtc_vblank_put(new_state->base.crtc);
8059                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
8060                                  __func__, new_state->base.crtc->base.id);
8061         }
8062 }
8063
8064 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
8065 {
8066         struct drm_plane *plane;
8067         struct drm_plane_state *old_plane_state;
8068         int i;
8069
8070         /*
8071          * TODO: Make this per-stream so we don't issue redundant updates for
8072          * commits with multiple streams.
8073          */
8074         for_each_old_plane_in_state(state, plane, old_plane_state, i)
8075                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
8076                         amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
8077 }
8078
8079 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
8080 {
8081         struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
8082
8083         return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
8084 }
8085
8086 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
8087                                     struct drm_device *dev,
8088                                     struct amdgpu_display_manager *dm,
8089                                     struct drm_crtc *pcrtc,
8090                                     bool wait_for_vblank)
8091 {
8092         u32 i;
8093         u64 timestamp_ns = ktime_get_ns();
8094         struct drm_plane *plane;
8095         struct drm_plane_state *old_plane_state, *new_plane_state;
8096         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
8097         struct drm_crtc_state *new_pcrtc_state =
8098                         drm_atomic_get_new_crtc_state(state, pcrtc);
8099         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
8100         struct dm_crtc_state *dm_old_crtc_state =
8101                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
8102         int planes_count = 0, vpos, hpos;
8103         unsigned long flags;
8104         u32 target_vblank, last_flip_vblank;
8105         bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
8106         bool cursor_update = false;
8107         bool pflip_present = false;
8108         bool dirty_rects_changed = false;
8109         struct {
8110                 struct dc_surface_update surface_updates[MAX_SURFACES];
8111                 struct dc_plane_info plane_infos[MAX_SURFACES];
8112                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
8113                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
8114                 struct dc_stream_update stream_update;
8115         } *bundle;
8116
8117         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8118
8119         if (!bundle) {
8120                 drm_err(dev, "Failed to allocate update bundle\n");
8121                 goto cleanup;
8122         }
8123
8124         /*
8125          * Disable the cursor first if we're disabling all the planes.
8126          * It'll remain on the screen after the planes are re-enabled
8127          * if we don't.
8128          */
8129         if (acrtc_state->active_planes == 0)
8130                 amdgpu_dm_commit_cursors(state);
8131
8132         /* update planes when needed */
8133         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8134                 struct drm_crtc *crtc = new_plane_state->crtc;
8135                 struct drm_crtc_state *new_crtc_state;
8136                 struct drm_framebuffer *fb = new_plane_state->fb;
8137                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
8138                 bool plane_needs_flip;
8139                 struct dc_plane_state *dc_plane;
8140                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
8141
8142                 /* Cursor plane is handled after stream updates */
8143                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
8144                         if ((fb && crtc == pcrtc) ||
8145                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
8146                                 cursor_update = true;
8147
8148                         continue;
8149                 }
8150
8151                 if (!fb || !crtc || pcrtc != crtc)
8152                         continue;
8153
8154                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8155                 if (!new_crtc_state->active)
8156                         continue;
8157
8158                 dc_plane = dm_new_plane_state->dc_state;
8159                 if (!dc_plane)
8160                         continue;
8161
8162                 bundle->surface_updates[planes_count].surface = dc_plane;
8163                 if (new_pcrtc_state->color_mgmt_changed) {
8164                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8165                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
8166                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
8167                 }
8168
8169                 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
8170                                      &bundle->scaling_infos[planes_count]);
8171
8172                 bundle->surface_updates[planes_count].scaling_info =
8173                         &bundle->scaling_infos[planes_count];
8174
8175                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8176
8177                 pflip_present = pflip_present || plane_needs_flip;
8178
8179                 if (!plane_needs_flip) {
8180                         planes_count += 1;
8181                         continue;
8182                 }
8183
8184                 fill_dc_plane_info_and_addr(
8185                         dm->adev, new_plane_state,
8186                         afb->tiling_flags,
8187                         &bundle->plane_infos[planes_count],
8188                         &bundle->flip_addrs[planes_count].address,
8189                         afb->tmz_surface, false);
8190
8191                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8192                                  new_plane_state->plane->index,
8193                                  bundle->plane_infos[planes_count].dcc.enable);
8194
8195                 bundle->surface_updates[planes_count].plane_info =
8196                         &bundle->plane_infos[planes_count];
8197
8198                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled ||
8199                     acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
8200                         fill_dc_dirty_rects(plane, old_plane_state,
8201                                             new_plane_state, new_crtc_state,
8202                                             &bundle->flip_addrs[planes_count],
8203                                             &dirty_rects_changed);
8204
8205                         /*
8206                          * If the dirty regions changed, PSR-SU need to be disabled temporarily
8207                          * and enabled it again after dirty regions are stable to avoid video glitch.
8208                          * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8209                          * during the PSR-SU was disabled.
8210                          */
8211                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8212                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8213 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8214                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8215 #endif
8216                             dirty_rects_changed) {
8217                                 mutex_lock(&dm->dc_lock);
8218                                 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8219                                 timestamp_ns;
8220                                 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8221                                         amdgpu_dm_psr_disable(acrtc_state->stream);
8222                                 mutex_unlock(&dm->dc_lock);
8223                         }
8224                 }
8225
8226                 /*
8227                  * Only allow immediate flips for fast updates that don't
8228                  * change memory domain, FB pitch, DCC state, rotation or
8229                  * mirroring.
8230                  *
8231                  * dm_crtc_helper_atomic_check() only accepts async flips with
8232                  * fast updates.
8233                  */
8234                 if (crtc->state->async_flip &&
8235                     (acrtc_state->update_type != UPDATE_TYPE_FAST ||
8236                      get_mem_type(old_plane_state->fb) != get_mem_type(fb)))
8237                         drm_warn_once(state->dev,
8238                                       "[PLANE:%d:%s] async flip with non-fast update\n",
8239                                       plane->base.id, plane->name);
8240
8241                 bundle->flip_addrs[planes_count].flip_immediate =
8242                         crtc->state->async_flip &&
8243                         acrtc_state->update_type == UPDATE_TYPE_FAST &&
8244                         get_mem_type(old_plane_state->fb) == get_mem_type(fb);
8245
8246                 timestamp_ns = ktime_get_ns();
8247                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8248                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8249                 bundle->surface_updates[planes_count].surface = dc_plane;
8250
8251                 if (!bundle->surface_updates[planes_count].surface) {
8252                         DRM_ERROR("No surface for CRTC: id=%d\n",
8253                                         acrtc_attach->crtc_id);
8254                         continue;
8255                 }
8256
8257                 if (plane == pcrtc->primary)
8258                         update_freesync_state_on_stream(
8259                                 dm,
8260                                 acrtc_state,
8261                                 acrtc_state->stream,
8262                                 dc_plane,
8263                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8264
8265                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8266                                  __func__,
8267                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8268                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8269
8270                 planes_count += 1;
8271
8272         }
8273
8274         if (pflip_present) {
8275                 if (!vrr_active) {
8276                         /* Use old throttling in non-vrr fixed refresh rate mode
8277                          * to keep flip scheduling based on target vblank counts
8278                          * working in a backwards compatible way, e.g., for
8279                          * clients using the GLX_OML_sync_control extension or
8280                          * DRI3/Present extension with defined target_msc.
8281                          */
8282                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8283                 } else {
8284                         /* For variable refresh rate mode only:
8285                          * Get vblank of last completed flip to avoid > 1 vrr
8286                          * flips per video frame by use of throttling, but allow
8287                          * flip programming anywhere in the possibly large
8288                          * variable vrr vblank interval for fine-grained flip
8289                          * timing control and more opportunity to avoid stutter
8290                          * on late submission of flips.
8291                          */
8292                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8293                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8294                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8295                 }
8296
8297                 target_vblank = last_flip_vblank + wait_for_vblank;
8298
8299                 /*
8300                  * Wait until we're out of the vertical blank period before the one
8301                  * targeted by the flip
8302                  */
8303                 while ((acrtc_attach->enabled &&
8304                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8305                                                             0, &vpos, &hpos, NULL,
8306                                                             NULL, &pcrtc->hwmode)
8307                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8308                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8309                         (int)(target_vblank -
8310                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8311                         usleep_range(1000, 1100);
8312                 }
8313
8314                 /**
8315                  * Prepare the flip event for the pageflip interrupt to handle.
8316                  *
8317                  * This only works in the case where we've already turned on the
8318                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8319                  * from 0 -> n planes we have to skip a hardware generated event
8320                  * and rely on sending it from software.
8321                  */
8322                 if (acrtc_attach->base.state->event &&
8323                     acrtc_state->active_planes > 0) {
8324                         drm_crtc_vblank_get(pcrtc);
8325
8326                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8327
8328                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8329                         prepare_flip_isr(acrtc_attach);
8330
8331                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8332                 }
8333
8334                 if (acrtc_state->stream) {
8335                         if (acrtc_state->freesync_vrr_info_changed)
8336                                 bundle->stream_update.vrr_infopacket =
8337                                         &acrtc_state->stream->vrr_infopacket;
8338                 }
8339         } else if (cursor_update && acrtc_state->active_planes > 0 &&
8340                    acrtc_attach->base.state->event) {
8341                 drm_crtc_vblank_get(pcrtc);
8342
8343                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8344
8345                 acrtc_attach->event = acrtc_attach->base.state->event;
8346                 acrtc_attach->base.state->event = NULL;
8347
8348                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8349         }
8350
8351         /* Update the planes if changed or disable if we don't have any. */
8352         if ((planes_count || acrtc_state->active_planes == 0) &&
8353                 acrtc_state->stream) {
8354                 /*
8355                  * If PSR or idle optimizations are enabled then flush out
8356                  * any pending work before hardware programming.
8357                  */
8358                 if (dm->vblank_control_workqueue)
8359                         flush_workqueue(dm->vblank_control_workqueue);
8360
8361                 bundle->stream_update.stream = acrtc_state->stream;
8362                 if (new_pcrtc_state->mode_changed) {
8363                         bundle->stream_update.src = acrtc_state->stream->src;
8364                         bundle->stream_update.dst = acrtc_state->stream->dst;
8365                 }
8366
8367                 if (new_pcrtc_state->color_mgmt_changed) {
8368                         /*
8369                          * TODO: This isn't fully correct since we've actually
8370                          * already modified the stream in place.
8371                          */
8372                         bundle->stream_update.gamut_remap =
8373                                 &acrtc_state->stream->gamut_remap_matrix;
8374                         bundle->stream_update.output_csc_transform =
8375                                 &acrtc_state->stream->csc_color_matrix;
8376                         bundle->stream_update.out_transfer_func =
8377                                 acrtc_state->stream->out_transfer_func;
8378                 }
8379
8380                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8381                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8382                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8383
8384                 mutex_lock(&dm->dc_lock);
8385                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8386                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8387                         amdgpu_dm_psr_disable(acrtc_state->stream);
8388                 mutex_unlock(&dm->dc_lock);
8389
8390                 /*
8391                  * If FreeSync state on the stream has changed then we need to
8392                  * re-adjust the min/max bounds now that DC doesn't handle this
8393                  * as part of commit.
8394                  */
8395                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8396                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8397                         dc_stream_adjust_vmin_vmax(
8398                                 dm->dc, acrtc_state->stream,
8399                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8400                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8401                 }
8402                 mutex_lock(&dm->dc_lock);
8403                 update_planes_and_stream_adapter(dm->dc,
8404                                          acrtc_state->update_type,
8405                                          planes_count,
8406                                          acrtc_state->stream,
8407                                          &bundle->stream_update,
8408                                          bundle->surface_updates);
8409
8410                 /**
8411                  * Enable or disable the interrupts on the backend.
8412                  *
8413                  * Most pipes are put into power gating when unused.
8414                  *
8415                  * When power gating is enabled on a pipe we lose the
8416                  * interrupt enablement state when power gating is disabled.
8417                  *
8418                  * So we need to update the IRQ control state in hardware
8419                  * whenever the pipe turns on (since it could be previously
8420                  * power gated) or off (since some pipes can't be power gated
8421                  * on some ASICs).
8422                  */
8423                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8424                         dm_update_pflip_irq_state(drm_to_adev(dev),
8425                                                   acrtc_attach);
8426
8427                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8428                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8429                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8430                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8431
8432                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8433                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8434                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8435                         struct amdgpu_dm_connector *aconn =
8436                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8437
8438                         if (aconn->psr_skip_count > 0)
8439                                 aconn->psr_skip_count--;
8440
8441                         /* Allow PSR when skip count is 0. */
8442                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8443
8444                         /*
8445                          * If sink supports PSR SU, there is no need to rely on
8446                          * a vblank event disable request to enable PSR. PSR SU
8447                          * can be enabled immediately once OS demonstrates an
8448                          * adequate number of fast atomic commits to notify KMD
8449                          * of update events. See `vblank_control_worker()`.
8450                          */
8451                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8452                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8453 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8454                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8455 #endif
8456                             !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8457                             (timestamp_ns -
8458                             acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8459                             500000000)
8460                                 amdgpu_dm_psr_enable(acrtc_state->stream);
8461                 } else {
8462                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
8463                 }
8464
8465                 mutex_unlock(&dm->dc_lock);
8466         }
8467
8468         /*
8469          * Update cursor state *after* programming all the planes.
8470          * This avoids redundant programming in the case where we're going
8471          * to be disabling a single plane - those pipes are being disabled.
8472          */
8473         if (acrtc_state->active_planes)
8474                 amdgpu_dm_commit_cursors(state);
8475
8476 cleanup:
8477         kfree(bundle);
8478 }
8479
8480 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8481                                    struct drm_atomic_state *state)
8482 {
8483         struct amdgpu_device *adev = drm_to_adev(dev);
8484         struct amdgpu_dm_connector *aconnector;
8485         struct drm_connector *connector;
8486         struct drm_connector_state *old_con_state, *new_con_state;
8487         struct drm_crtc_state *new_crtc_state;
8488         struct dm_crtc_state *new_dm_crtc_state;
8489         const struct dc_stream_status *status;
8490         int i, inst;
8491
8492         /* Notify device removals. */
8493         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8494                 if (old_con_state->crtc != new_con_state->crtc) {
8495                         /* CRTC changes require notification. */
8496                         goto notify;
8497                 }
8498
8499                 if (!new_con_state->crtc)
8500                         continue;
8501
8502                 new_crtc_state = drm_atomic_get_new_crtc_state(
8503                         state, new_con_state->crtc);
8504
8505                 if (!new_crtc_state)
8506                         continue;
8507
8508                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8509                         continue;
8510
8511 notify:
8512                 aconnector = to_amdgpu_dm_connector(connector);
8513
8514                 mutex_lock(&adev->dm.audio_lock);
8515                 inst = aconnector->audio_inst;
8516                 aconnector->audio_inst = -1;
8517                 mutex_unlock(&adev->dm.audio_lock);
8518
8519                 amdgpu_dm_audio_eld_notify(adev, inst);
8520         }
8521
8522         /* Notify audio device additions. */
8523         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8524                 if (!new_con_state->crtc)
8525                         continue;
8526
8527                 new_crtc_state = drm_atomic_get_new_crtc_state(
8528                         state, new_con_state->crtc);
8529
8530                 if (!new_crtc_state)
8531                         continue;
8532
8533                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8534                         continue;
8535
8536                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8537                 if (!new_dm_crtc_state->stream)
8538                         continue;
8539
8540                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8541                 if (!status)
8542                         continue;
8543
8544                 aconnector = to_amdgpu_dm_connector(connector);
8545
8546                 mutex_lock(&adev->dm.audio_lock);
8547                 inst = status->audio_inst;
8548                 aconnector->audio_inst = inst;
8549                 mutex_unlock(&adev->dm.audio_lock);
8550
8551                 amdgpu_dm_audio_eld_notify(adev, inst);
8552         }
8553 }
8554
8555 /*
8556  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8557  * @crtc_state: the DRM CRTC state
8558  * @stream_state: the DC stream state.
8559  *
8560  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8561  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8562  */
8563 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8564                                                 struct dc_stream_state *stream_state)
8565 {
8566         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8567 }
8568
8569 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
8570                                         struct dc_state *dc_state)
8571 {
8572         struct drm_device *dev = state->dev;
8573         struct amdgpu_device *adev = drm_to_adev(dev);
8574         struct amdgpu_display_manager *dm = &adev->dm;
8575         struct drm_crtc *crtc;
8576         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8577         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8578         bool mode_set_reset_required = false;
8579         u32 i;
8580
8581         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
8582                                       new_crtc_state, i) {
8583                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8584
8585                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8586
8587                 if (old_crtc_state->active &&
8588                     (!new_crtc_state->active ||
8589                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8590                         manage_dm_interrupts(adev, acrtc, false);
8591                         dc_stream_release(dm_old_crtc_state->stream);
8592                 }
8593         }
8594
8595         drm_atomic_helper_calc_timestamping_constants(state);
8596
8597         /* update changed items */
8598         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8599                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8600
8601                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8602                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8603
8604                 drm_dbg_state(state->dev,
8605                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
8606                         acrtc->crtc_id,
8607                         new_crtc_state->enable,
8608                         new_crtc_state->active,
8609                         new_crtc_state->planes_changed,
8610                         new_crtc_state->mode_changed,
8611                         new_crtc_state->active_changed,
8612                         new_crtc_state->connectors_changed);
8613
8614                 /* Disable cursor if disabling crtc */
8615                 if (old_crtc_state->active && !new_crtc_state->active) {
8616                         struct dc_cursor_position position;
8617
8618                         memset(&position, 0, sizeof(position));
8619                         mutex_lock(&dm->dc_lock);
8620                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8621                         mutex_unlock(&dm->dc_lock);
8622                 }
8623
8624                 /* Copy all transient state flags into dc state */
8625                 if (dm_new_crtc_state->stream) {
8626                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8627                                                             dm_new_crtc_state->stream);
8628                 }
8629
8630                 /* handles headless hotplug case, updating new_state and
8631                  * aconnector as needed
8632                  */
8633
8634                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8635
8636                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8637
8638                         if (!dm_new_crtc_state->stream) {
8639                                 /*
8640                                  * this could happen because of issues with
8641                                  * userspace notifications delivery.
8642                                  * In this case userspace tries to set mode on
8643                                  * display which is disconnected in fact.
8644                                  * dc_sink is NULL in this case on aconnector.
8645                                  * We expect reset mode will come soon.
8646                                  *
8647                                  * This can also happen when unplug is done
8648                                  * during resume sequence ended
8649                                  *
8650                                  * In this case, we want to pretend we still
8651                                  * have a sink to keep the pipe running so that
8652                                  * hw state is consistent with the sw state
8653                                  */
8654                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8655                                                 __func__, acrtc->base.base.id);
8656                                 continue;
8657                         }
8658
8659                         if (dm_old_crtc_state->stream)
8660                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8661
8662                         pm_runtime_get_noresume(dev->dev);
8663
8664                         acrtc->enabled = true;
8665                         acrtc->hw_mode = new_crtc_state->mode;
8666                         crtc->hwmode = new_crtc_state->mode;
8667                         mode_set_reset_required = true;
8668                 } else if (modereset_required(new_crtc_state)) {
8669                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8670                         /* i.e. reset mode */
8671                         if (dm_old_crtc_state->stream)
8672                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8673
8674                         mode_set_reset_required = true;
8675                 }
8676         } /* for_each_crtc_in_state() */
8677
8678         /* if there mode set or reset, disable eDP PSR */
8679         if (mode_set_reset_required) {
8680                 if (dm->vblank_control_workqueue)
8681                         flush_workqueue(dm->vblank_control_workqueue);
8682
8683                 amdgpu_dm_psr_disable_all(dm);
8684         }
8685
8686         dm_enable_per_frame_crtc_master_sync(dc_state);
8687         mutex_lock(&dm->dc_lock);
8688         WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8689
8690         /* Allow idle optimization when vblank count is 0 for display off */
8691         if (dm->active_vblank_irq_count == 0)
8692                 dc_allow_idle_optimizations(dm->dc, true);
8693         mutex_unlock(&dm->dc_lock);
8694
8695         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8696                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8697
8698                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8699
8700                 if (dm_new_crtc_state->stream != NULL) {
8701                         const struct dc_stream_status *status =
8702                                         dc_stream_get_status(dm_new_crtc_state->stream);
8703
8704                         if (!status)
8705                                 status = dc_stream_get_status_from_state(dc_state,
8706                                                                          dm_new_crtc_state->stream);
8707                         if (!status)
8708                                 drm_err(dev,
8709                                         "got no status for stream %p on acrtc%p\n",
8710                                         dm_new_crtc_state->stream, acrtc);
8711                         else
8712                                 acrtc->otg_inst = status->primary_otg_inst;
8713                 }
8714         }
8715 }
8716
8717 /**
8718  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8719  * @state: The atomic state to commit
8720  *
8721  * This will tell DC to commit the constructed DC state from atomic_check,
8722  * programming the hardware. Any failures here implies a hardware failure, since
8723  * atomic check should have filtered anything non-kosher.
8724  */
8725 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8726 {
8727         struct drm_device *dev = state->dev;
8728         struct amdgpu_device *adev = drm_to_adev(dev);
8729         struct amdgpu_display_manager *dm = &adev->dm;
8730         struct dm_atomic_state *dm_state;
8731         struct dc_state *dc_state = NULL;
8732         u32 i, j;
8733         struct drm_crtc *crtc;
8734         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8735         unsigned long flags;
8736         bool wait_for_vblank = true;
8737         struct drm_connector *connector;
8738         struct drm_connector_state *old_con_state, *new_con_state;
8739         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8740         int crtc_disable_count = 0;
8741
8742         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8743
8744         if (dm->dc->caps.ips_support) {
8745                 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8746                         if (new_con_state->crtc &&
8747                                 new_con_state->crtc->state->active &&
8748                                 drm_atomic_crtc_needs_modeset(new_con_state->crtc->state)) {
8749                                 dc_dmub_srv_exit_low_power_state(dm->dc);
8750                                 break;
8751                         }
8752                 }
8753         }
8754
8755         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8756         drm_dp_mst_atomic_wait_for_dependencies(state);
8757
8758         dm_state = dm_atomic_get_new_state(state);
8759         if (dm_state && dm_state->context) {
8760                 dc_state = dm_state->context;
8761                 amdgpu_dm_commit_streams(state, dc_state);
8762         }
8763
8764         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8765                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8766                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8767                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8768
8769                 if (!adev->dm.hdcp_workqueue)
8770                         continue;
8771
8772                 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8773
8774                 if (!connector)
8775                         continue;
8776
8777                 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8778                         connector->index, connector->status, connector->dpms);
8779                 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8780                         old_con_state->content_protection, new_con_state->content_protection);
8781
8782                 if (aconnector->dc_sink) {
8783                         if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8784                                 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8785                                 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8786                                 aconnector->dc_sink->edid_caps.display_name);
8787                         }
8788                 }
8789
8790                 new_crtc_state = NULL;
8791                 old_crtc_state = NULL;
8792
8793                 if (acrtc) {
8794                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8795                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8796                 }
8797
8798                 if (old_crtc_state)
8799                         pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8800                         old_crtc_state->enable,
8801                         old_crtc_state->active,
8802                         old_crtc_state->mode_changed,
8803                         old_crtc_state->active_changed,
8804                         old_crtc_state->connectors_changed);
8805
8806                 if (new_crtc_state)
8807                         pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8808                         new_crtc_state->enable,
8809                         new_crtc_state->active,
8810                         new_crtc_state->mode_changed,
8811                         new_crtc_state->active_changed,
8812                         new_crtc_state->connectors_changed);
8813         }
8814
8815         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8816                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8817                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8818                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8819
8820                 if (!adev->dm.hdcp_workqueue)
8821                         continue;
8822
8823                 new_crtc_state = NULL;
8824                 old_crtc_state = NULL;
8825
8826                 if (acrtc) {
8827                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8828                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8829                 }
8830
8831                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8832
8833                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8834                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8835                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8836                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8837                         dm_new_con_state->update_hdcp = true;
8838                         continue;
8839                 }
8840
8841                 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8842                                                                                         old_con_state, connector, adev->dm.hdcp_workqueue)) {
8843                         /* when display is unplugged from mst hub, connctor will
8844                          * be destroyed within dm_dp_mst_connector_destroy. connector
8845                          * hdcp perperties, like type, undesired, desired, enabled,
8846                          * will be lost. So, save hdcp properties into hdcp_work within
8847                          * amdgpu_dm_atomic_commit_tail. if the same display is
8848                          * plugged back with same display index, its hdcp properties
8849                          * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8850                          */
8851
8852                         bool enable_encryption = false;
8853
8854                         if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8855                                 enable_encryption = true;
8856
8857                         if (aconnector->dc_link && aconnector->dc_sink &&
8858                                 aconnector->dc_link->type == dc_connection_mst_branch) {
8859                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8860                                 struct hdcp_workqueue *hdcp_w =
8861                                         &hdcp_work[aconnector->dc_link->link_index];
8862
8863                                 hdcp_w->hdcp_content_type[connector->index] =
8864                                         new_con_state->hdcp_content_type;
8865                                 hdcp_w->content_protection[connector->index] =
8866                                         new_con_state->content_protection;
8867                         }
8868
8869                         if (new_crtc_state && new_crtc_state->mode_changed &&
8870                                 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8871                                 enable_encryption = true;
8872
8873                         DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8874
8875                         hdcp_update_display(
8876                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8877                                 new_con_state->hdcp_content_type, enable_encryption);
8878                 }
8879         }
8880
8881         /* Handle connector state changes */
8882         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8883                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8884                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8885                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8886                 struct dc_surface_update *dummy_updates;
8887                 struct dc_stream_update stream_update;
8888                 struct dc_info_packet hdr_packet;
8889                 struct dc_stream_status *status = NULL;
8890                 bool abm_changed, hdr_changed, scaling_changed;
8891
8892                 memset(&stream_update, 0, sizeof(stream_update));
8893
8894                 if (acrtc) {
8895                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8896                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8897                 }
8898
8899                 /* Skip any modesets/resets */
8900                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8901                         continue;
8902
8903                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8904                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8905
8906                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8907                                                              dm_old_con_state);
8908
8909                 abm_changed = dm_new_crtc_state->abm_level !=
8910                               dm_old_crtc_state->abm_level;
8911
8912                 hdr_changed =
8913                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8914
8915                 if (!scaling_changed && !abm_changed && !hdr_changed)
8916                         continue;
8917
8918                 stream_update.stream = dm_new_crtc_state->stream;
8919                 if (scaling_changed) {
8920                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8921                                         dm_new_con_state, dm_new_crtc_state->stream);
8922
8923                         stream_update.src = dm_new_crtc_state->stream->src;
8924                         stream_update.dst = dm_new_crtc_state->stream->dst;
8925                 }
8926
8927                 if (abm_changed) {
8928                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8929
8930                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8931                 }
8932
8933                 if (hdr_changed) {
8934                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8935                         stream_update.hdr_static_metadata = &hdr_packet;
8936                 }
8937
8938                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8939
8940                 if (WARN_ON(!status))
8941                         continue;
8942
8943                 WARN_ON(!status->plane_count);
8944
8945                 /*
8946                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8947                  * Here we create an empty update on each plane.
8948                  * To fix this, DC should permit updating only stream properties.
8949                  */
8950                 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC);
8951                 for (j = 0; j < status->plane_count; j++)
8952                         dummy_updates[j].surface = status->plane_states[0];
8953
8954
8955                 mutex_lock(&dm->dc_lock);
8956                 dc_update_planes_and_stream(dm->dc,
8957                                             dummy_updates,
8958                                             status->plane_count,
8959                                             dm_new_crtc_state->stream,
8960                                             &stream_update);
8961                 mutex_unlock(&dm->dc_lock);
8962                 kfree(dummy_updates);
8963         }
8964
8965         /**
8966          * Enable interrupts for CRTCs that are newly enabled or went through
8967          * a modeset. It was intentionally deferred until after the front end
8968          * state was modified to wait until the OTG was on and so the IRQ
8969          * handlers didn't access stale or invalid state.
8970          */
8971         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8972                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8973 #ifdef CONFIG_DEBUG_FS
8974                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8975 #endif
8976                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8977                 if (old_crtc_state->active && !new_crtc_state->active)
8978                         crtc_disable_count++;
8979
8980                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8981                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8982
8983                 /* For freesync config update on crtc state and params for irq */
8984                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8985
8986 #ifdef CONFIG_DEBUG_FS
8987                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8988                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8989                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8990 #endif
8991
8992                 if (new_crtc_state->active &&
8993                     (!old_crtc_state->active ||
8994                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8995                         dc_stream_retain(dm_new_crtc_state->stream);
8996                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8997                         manage_dm_interrupts(adev, acrtc, true);
8998                 }
8999                 /* Handle vrr on->off / off->on transitions */
9000                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
9001
9002 #ifdef CONFIG_DEBUG_FS
9003                 if (new_crtc_state->active &&
9004                     (!old_crtc_state->active ||
9005                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
9006                         /**
9007                          * Frontend may have changed so reapply the CRC capture
9008                          * settings for the stream.
9009                          */
9010                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
9011 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
9012                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
9013                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9014                                         acrtc->dm_irq_params.window_param.update_win = true;
9015
9016                                         /**
9017                                          * It takes 2 frames for HW to stably generate CRC when
9018                                          * resuming from suspend, so we set skip_frame_cnt 2.
9019                                          */
9020                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
9021                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9022                                 }
9023 #endif
9024                                 if (amdgpu_dm_crtc_configure_crc_source(
9025                                         crtc, dm_new_crtc_state, cur_crc_src))
9026                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
9027                         }
9028                 }
9029 #endif
9030         }
9031
9032         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
9033                 if (new_crtc_state->async_flip)
9034                         wait_for_vblank = false;
9035
9036         /* update planes when needed per crtc*/
9037         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
9038                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9039
9040                 if (dm_new_crtc_state->stream)
9041                         amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);
9042         }
9043
9044         /* Update audio instances for each connector. */
9045         amdgpu_dm_commit_audio(dev, state);
9046
9047         /* restore the backlight level */
9048         for (i = 0; i < dm->num_of_edps; i++) {
9049                 if (dm->backlight_dev[i] &&
9050                     (dm->actual_brightness[i] != dm->brightness[i]))
9051                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
9052         }
9053
9054         /*
9055          * send vblank event on all events not handled in flip and
9056          * mark consumed event for drm_atomic_helper_commit_hw_done
9057          */
9058         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9059         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9060
9061                 if (new_crtc_state->event)
9062                         drm_send_event_locked(dev, &new_crtc_state->event->base);
9063
9064                 new_crtc_state->event = NULL;
9065         }
9066         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9067
9068         /* Signal HW programming completion */
9069         drm_atomic_helper_commit_hw_done(state);
9070
9071         if (wait_for_vblank)
9072                 drm_atomic_helper_wait_for_flip_done(dev, state);
9073
9074         drm_atomic_helper_cleanup_planes(dev, state);
9075
9076         /* Don't free the memory if we are hitting this as part of suspend.
9077          * This way we don't free any memory during suspend; see
9078          * amdgpu_bo_free_kernel().  The memory will be freed in the first
9079          * non-suspend modeset or when the driver is torn down.
9080          */
9081         if (!adev->in_suspend) {
9082                 /* return the stolen vga memory back to VRAM */
9083                 if (!adev->mman.keep_stolen_vga_memory)
9084                         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
9085                 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
9086         }
9087
9088         /*
9089          * Finally, drop a runtime PM reference for each newly disabled CRTC,
9090          * so we can put the GPU into runtime suspend if we're not driving any
9091          * displays anymore
9092          */
9093         for (i = 0; i < crtc_disable_count; i++)
9094                 pm_runtime_put_autosuspend(dev->dev);
9095         pm_runtime_mark_last_busy(dev->dev);
9096 }
9097
9098 static int dm_force_atomic_commit(struct drm_connector *connector)
9099 {
9100         int ret = 0;
9101         struct drm_device *ddev = connector->dev;
9102         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
9103         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9104         struct drm_plane *plane = disconnected_acrtc->base.primary;
9105         struct drm_connector_state *conn_state;
9106         struct drm_crtc_state *crtc_state;
9107         struct drm_plane_state *plane_state;
9108
9109         if (!state)
9110                 return -ENOMEM;
9111
9112         state->acquire_ctx = ddev->mode_config.acquire_ctx;
9113
9114         /* Construct an atomic state to restore previous display setting */
9115
9116         /*
9117          * Attach connectors to drm_atomic_state
9118          */
9119         conn_state = drm_atomic_get_connector_state(state, connector);
9120
9121         ret = PTR_ERR_OR_ZERO(conn_state);
9122         if (ret)
9123                 goto out;
9124
9125         /* Attach crtc to drm_atomic_state*/
9126         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
9127
9128         ret = PTR_ERR_OR_ZERO(crtc_state);
9129         if (ret)
9130                 goto out;
9131
9132         /* force a restore */
9133         crtc_state->mode_changed = true;
9134
9135         /* Attach plane to drm_atomic_state */
9136         plane_state = drm_atomic_get_plane_state(state, plane);
9137
9138         ret = PTR_ERR_OR_ZERO(plane_state);
9139         if (ret)
9140                 goto out;
9141
9142         /* Call commit internally with the state we just constructed */
9143         ret = drm_atomic_commit(state);
9144
9145 out:
9146         drm_atomic_state_put(state);
9147         if (ret)
9148                 DRM_ERROR("Restoring old state failed with %i\n", ret);
9149
9150         return ret;
9151 }
9152
9153 /*
9154  * This function handles all cases when set mode does not come upon hotplug.
9155  * This includes when a display is unplugged then plugged back into the
9156  * same port and when running without usermode desktop manager supprot
9157  */
9158 void dm_restore_drm_connector_state(struct drm_device *dev,
9159                                     struct drm_connector *connector)
9160 {
9161         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9162         struct amdgpu_crtc *disconnected_acrtc;
9163         struct dm_crtc_state *acrtc_state;
9164
9165         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
9166                 return;
9167
9168         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9169         if (!disconnected_acrtc)
9170                 return;
9171
9172         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
9173         if (!acrtc_state->stream)
9174                 return;
9175
9176         /*
9177          * If the previous sink is not released and different from the current,
9178          * we deduce we are in a state where we can not rely on usermode call
9179          * to turn on the display, so we do it here
9180          */
9181         if (acrtc_state->stream->sink != aconnector->dc_sink)
9182                 dm_force_atomic_commit(&aconnector->base);
9183 }
9184
9185 /*
9186  * Grabs all modesetting locks to serialize against any blocking commits,
9187  * Waits for completion of all non blocking commits.
9188  */
9189 static int do_aquire_global_lock(struct drm_device *dev,
9190                                  struct drm_atomic_state *state)
9191 {
9192         struct drm_crtc *crtc;
9193         struct drm_crtc_commit *commit;
9194         long ret;
9195
9196         /*
9197          * Adding all modeset locks to aquire_ctx will
9198          * ensure that when the framework release it the
9199          * extra locks we are locking here will get released to
9200          */
9201         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9202         if (ret)
9203                 return ret;
9204
9205         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9206                 spin_lock(&crtc->commit_lock);
9207                 commit = list_first_entry_or_null(&crtc->commit_list,
9208                                 struct drm_crtc_commit, commit_entry);
9209                 if (commit)
9210                         drm_crtc_commit_get(commit);
9211                 spin_unlock(&crtc->commit_lock);
9212
9213                 if (!commit)
9214                         continue;
9215
9216                 /*
9217                  * Make sure all pending HW programming completed and
9218                  * page flips done
9219                  */
9220                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9221
9222                 if (ret > 0)
9223                         ret = wait_for_completion_interruptible_timeout(
9224                                         &commit->flip_done, 10*HZ);
9225
9226                 if (ret == 0)
9227                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",
9228                                   crtc->base.id, crtc->name);
9229
9230                 drm_crtc_commit_put(commit);
9231         }
9232
9233         return ret < 0 ? ret : 0;
9234 }
9235
9236 static void get_freesync_config_for_crtc(
9237         struct dm_crtc_state *new_crtc_state,
9238         struct dm_connector_state *new_con_state)
9239 {
9240         struct mod_freesync_config config = {0};
9241         struct amdgpu_dm_connector *aconnector =
9242                         to_amdgpu_dm_connector(new_con_state->base.connector);
9243         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9244         int vrefresh = drm_mode_vrefresh(mode);
9245         bool fs_vid_mode = false;
9246
9247         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9248                                         vrefresh >= aconnector->min_vfreq &&
9249                                         vrefresh <= aconnector->max_vfreq;
9250
9251         if (new_crtc_state->vrr_supported) {
9252                 new_crtc_state->stream->ignore_msa_timing_param = true;
9253                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9254
9255                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9256                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9257                 config.vsif_supported = true;
9258                 config.btr = true;
9259
9260                 if (fs_vid_mode) {
9261                         config.state = VRR_STATE_ACTIVE_FIXED;
9262                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9263                         goto out;
9264                 } else if (new_crtc_state->base.vrr_enabled) {
9265                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9266                 } else {
9267                         config.state = VRR_STATE_INACTIVE;
9268                 }
9269         }
9270 out:
9271         new_crtc_state->freesync_config = config;
9272 }
9273
9274 static void reset_freesync_config_for_crtc(
9275         struct dm_crtc_state *new_crtc_state)
9276 {
9277         new_crtc_state->vrr_supported = false;
9278
9279         memset(&new_crtc_state->vrr_infopacket, 0,
9280                sizeof(new_crtc_state->vrr_infopacket));
9281 }
9282
9283 static bool
9284 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9285                                  struct drm_crtc_state *new_crtc_state)
9286 {
9287         const struct drm_display_mode *old_mode, *new_mode;
9288
9289         if (!old_crtc_state || !new_crtc_state)
9290                 return false;
9291
9292         old_mode = &old_crtc_state->mode;
9293         new_mode = &new_crtc_state->mode;
9294
9295         if (old_mode->clock       == new_mode->clock &&
9296             old_mode->hdisplay    == new_mode->hdisplay &&
9297             old_mode->vdisplay    == new_mode->vdisplay &&
9298             old_mode->htotal      == new_mode->htotal &&
9299             old_mode->vtotal      != new_mode->vtotal &&
9300             old_mode->hsync_start == new_mode->hsync_start &&
9301             old_mode->vsync_start != new_mode->vsync_start &&
9302             old_mode->hsync_end   == new_mode->hsync_end &&
9303             old_mode->vsync_end   != new_mode->vsync_end &&
9304             old_mode->hskew       == new_mode->hskew &&
9305             old_mode->vscan       == new_mode->vscan &&
9306             (old_mode->vsync_end - old_mode->vsync_start) ==
9307             (new_mode->vsync_end - new_mode->vsync_start))
9308                 return true;
9309
9310         return false;
9311 }
9312
9313 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)
9314 {
9315         u64 num, den, res;
9316         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9317
9318         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9319
9320         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9321         den = (unsigned long long)new_crtc_state->mode.htotal *
9322               (unsigned long long)new_crtc_state->mode.vtotal;
9323
9324         res = div_u64(num, den);
9325         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9326 }
9327
9328 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9329                          struct drm_atomic_state *state,
9330                          struct drm_crtc *crtc,
9331                          struct drm_crtc_state *old_crtc_state,
9332                          struct drm_crtc_state *new_crtc_state,
9333                          bool enable,
9334                          bool *lock_and_validation_needed)
9335 {
9336         struct dm_atomic_state *dm_state = NULL;
9337         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9338         struct dc_stream_state *new_stream;
9339         int ret = 0;
9340
9341         /*
9342          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9343          * update changed items
9344          */
9345         struct amdgpu_crtc *acrtc = NULL;
9346         struct amdgpu_dm_connector *aconnector = NULL;
9347         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9348         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9349
9350         new_stream = NULL;
9351
9352         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9353         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9354         acrtc = to_amdgpu_crtc(crtc);
9355         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9356
9357         /* TODO This hack should go away */
9358         if (aconnector && enable) {
9359                 /* Make sure fake sink is created in plug-in scenario */
9360                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9361                                                             &aconnector->base);
9362                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9363                                                             &aconnector->base);
9364
9365                 if (IS_ERR(drm_new_conn_state)) {
9366                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9367                         goto fail;
9368                 }
9369
9370                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9371                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9372
9373                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9374                         goto skip_modeset;
9375
9376                 new_stream = create_validate_stream_for_sink(aconnector,
9377                                                              &new_crtc_state->mode,
9378                                                              dm_new_conn_state,
9379                                                              dm_old_crtc_state->stream);
9380
9381                 /*
9382                  * we can have no stream on ACTION_SET if a display
9383                  * was disconnected during S3, in this case it is not an
9384                  * error, the OS will be updated after detection, and
9385                  * will do the right thing on next atomic commit
9386                  */
9387
9388                 if (!new_stream) {
9389                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9390                                         __func__, acrtc->base.base.id);
9391                         ret = -ENOMEM;
9392                         goto fail;
9393                 }
9394
9395                 /*
9396                  * TODO: Check VSDB bits to decide whether this should
9397                  * be enabled or not.
9398                  */
9399                 new_stream->triggered_crtc_reset.enabled =
9400                         dm->force_timing_sync;
9401
9402                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9403
9404                 ret = fill_hdr_info_packet(drm_new_conn_state,
9405                                            &new_stream->hdr_static_metadata);
9406                 if (ret)
9407                         goto fail;
9408
9409                 /*
9410                  * If we already removed the old stream from the context
9411                  * (and set the new stream to NULL) then we can't reuse
9412                  * the old stream even if the stream and scaling are unchanged.
9413                  * We'll hit the BUG_ON and black screen.
9414                  *
9415                  * TODO: Refactor this function to allow this check to work
9416                  * in all conditions.
9417                  */
9418                 if (dm_new_crtc_state->stream &&
9419                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9420                         goto skip_modeset;
9421
9422                 if (dm_new_crtc_state->stream &&
9423                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9424                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9425                         new_crtc_state->mode_changed = false;
9426                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9427                                          new_crtc_state->mode_changed);
9428                 }
9429         }
9430
9431         /* mode_changed flag may get updated above, need to check again */
9432         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9433                 goto skip_modeset;
9434
9435         drm_dbg_state(state->dev,
9436                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
9437                 acrtc->crtc_id,
9438                 new_crtc_state->enable,
9439                 new_crtc_state->active,
9440                 new_crtc_state->planes_changed,
9441                 new_crtc_state->mode_changed,
9442                 new_crtc_state->active_changed,
9443                 new_crtc_state->connectors_changed);
9444
9445         /* Remove stream for any changed/disabled CRTC */
9446         if (!enable) {
9447
9448                 if (!dm_old_crtc_state->stream)
9449                         goto skip_modeset;
9450
9451                 /* Unset freesync video if it was active before */
9452                 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9453                         dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9454                         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9455                 }
9456
9457                 /* Now check if we should set freesync video mode */
9458                 if (dm_new_crtc_state->stream &&
9459                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9460                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
9461                     is_timing_unchanged_for_freesync(new_crtc_state,
9462                                                      old_crtc_state)) {
9463                         new_crtc_state->mode_changed = false;
9464                         DRM_DEBUG_DRIVER(
9465                                 "Mode change not required for front porch change, setting mode_changed to %d",
9466                                 new_crtc_state->mode_changed);
9467
9468                         set_freesync_fixed_config(dm_new_crtc_state);
9469
9470                         goto skip_modeset;
9471                 } else if (aconnector &&
9472                            is_freesync_video_mode(&new_crtc_state->mode,
9473                                                   aconnector)) {
9474                         struct drm_display_mode *high_mode;
9475
9476                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
9477                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode))
9478                                 set_freesync_fixed_config(dm_new_crtc_state);
9479                 }
9480
9481                 ret = dm_atomic_get_state(state, &dm_state);
9482                 if (ret)
9483                         goto fail;
9484
9485                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9486                                 crtc->base.id);
9487
9488                 /* i.e. reset mode */
9489                 if (dc_remove_stream_from_ctx(
9490                                 dm->dc,
9491                                 dm_state->context,
9492                                 dm_old_crtc_state->stream) != DC_OK) {
9493                         ret = -EINVAL;
9494                         goto fail;
9495                 }
9496
9497                 dc_stream_release(dm_old_crtc_state->stream);
9498                 dm_new_crtc_state->stream = NULL;
9499
9500                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9501
9502                 *lock_and_validation_needed = true;
9503
9504         } else {/* Add stream for any updated/enabled CRTC */
9505                 /*
9506                  * Quick fix to prevent NULL pointer on new_stream when
9507                  * added MST connectors not found in existing crtc_state in the chained mode
9508                  * TODO: need to dig out the root cause of that
9509                  */
9510                 if (!aconnector)
9511                         goto skip_modeset;
9512
9513                 if (modereset_required(new_crtc_state))
9514                         goto skip_modeset;
9515
9516                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9517                                      dm_old_crtc_state->stream)) {
9518
9519                         WARN_ON(dm_new_crtc_state->stream);
9520
9521                         ret = dm_atomic_get_state(state, &dm_state);
9522                         if (ret)
9523                                 goto fail;
9524
9525                         dm_new_crtc_state->stream = new_stream;
9526
9527                         dc_stream_retain(new_stream);
9528
9529                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9530                                          crtc->base.id);
9531
9532                         if (dc_add_stream_to_ctx(
9533                                         dm->dc,
9534                                         dm_state->context,
9535                                         dm_new_crtc_state->stream) != DC_OK) {
9536                                 ret = -EINVAL;
9537                                 goto fail;
9538                         }
9539
9540                         *lock_and_validation_needed = true;
9541                 }
9542         }
9543
9544 skip_modeset:
9545         /* Release extra reference */
9546         if (new_stream)
9547                 dc_stream_release(new_stream);
9548
9549         /*
9550          * We want to do dc stream updates that do not require a
9551          * full modeset below.
9552          */
9553         if (!(enable && aconnector && new_crtc_state->active))
9554                 return 0;
9555         /*
9556          * Given above conditions, the dc state cannot be NULL because:
9557          * 1. We're in the process of enabling CRTCs (just been added
9558          *    to the dc context, or already is on the context)
9559          * 2. Has a valid connector attached, and
9560          * 3. Is currently active and enabled.
9561          * => The dc stream state currently exists.
9562          */
9563         BUG_ON(dm_new_crtc_state->stream == NULL);
9564
9565         /* Scaling or underscan settings */
9566         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9567                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
9568                 update_stream_scaling_settings(
9569                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9570
9571         /* ABM settings */
9572         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9573
9574         /*
9575          * Color management settings. We also update color properties
9576          * when a modeset is needed, to ensure it gets reprogrammed.
9577          */
9578         if (dm_new_crtc_state->base.color_mgmt_changed ||
9579             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9580                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9581                 if (ret)
9582                         goto fail;
9583         }
9584
9585         /* Update Freesync settings. */
9586         get_freesync_config_for_crtc(dm_new_crtc_state,
9587                                      dm_new_conn_state);
9588
9589         return ret;
9590
9591 fail:
9592         if (new_stream)
9593                 dc_stream_release(new_stream);
9594         return ret;
9595 }
9596
9597 static bool should_reset_plane(struct drm_atomic_state *state,
9598                                struct drm_plane *plane,
9599                                struct drm_plane_state *old_plane_state,
9600                                struct drm_plane_state *new_plane_state)
9601 {
9602         struct drm_plane *other;
9603         struct drm_plane_state *old_other_state, *new_other_state;
9604         struct drm_crtc_state *new_crtc_state;
9605         int i;
9606
9607         /*
9608          * TODO: Remove this hack once the checks below are sufficient
9609          * enough to determine when we need to reset all the planes on
9610          * the stream.
9611          */
9612         if (state->allow_modeset)
9613                 return true;
9614
9615         /* Exit early if we know that we're adding or removing the plane. */
9616         if (old_plane_state->crtc != new_plane_state->crtc)
9617                 return true;
9618
9619         /* old crtc == new_crtc == NULL, plane not in context. */
9620         if (!new_plane_state->crtc)
9621                 return false;
9622
9623         new_crtc_state =
9624                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9625
9626         if (!new_crtc_state)
9627                 return true;
9628
9629         /* CRTC Degamma changes currently require us to recreate planes. */
9630         if (new_crtc_state->color_mgmt_changed)
9631                 return true;
9632
9633         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9634                 return true;
9635
9636         /*
9637          * If there are any new primary or overlay planes being added or
9638          * removed then the z-order can potentially change. To ensure
9639          * correct z-order and pipe acquisition the current DC architecture
9640          * requires us to remove and recreate all existing planes.
9641          *
9642          * TODO: Come up with a more elegant solution for this.
9643          */
9644         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9645                 struct amdgpu_framebuffer *old_afb, *new_afb;
9646
9647                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9648                         continue;
9649
9650                 if (old_other_state->crtc != new_plane_state->crtc &&
9651                     new_other_state->crtc != new_plane_state->crtc)
9652                         continue;
9653
9654                 if (old_other_state->crtc != new_other_state->crtc)
9655                         return true;
9656
9657                 /* Src/dst size and scaling updates. */
9658                 if (old_other_state->src_w != new_other_state->src_w ||
9659                     old_other_state->src_h != new_other_state->src_h ||
9660                     old_other_state->crtc_w != new_other_state->crtc_w ||
9661                     old_other_state->crtc_h != new_other_state->crtc_h)
9662                         return true;
9663
9664                 /* Rotation / mirroring updates. */
9665                 if (old_other_state->rotation != new_other_state->rotation)
9666                         return true;
9667
9668                 /* Blending updates. */
9669                 if (old_other_state->pixel_blend_mode !=
9670                     new_other_state->pixel_blend_mode)
9671                         return true;
9672
9673                 /* Alpha updates. */
9674                 if (old_other_state->alpha != new_other_state->alpha)
9675                         return true;
9676
9677                 /* Colorspace changes. */
9678                 if (old_other_state->color_range != new_other_state->color_range ||
9679                     old_other_state->color_encoding != new_other_state->color_encoding)
9680                         return true;
9681
9682                 /* Framebuffer checks fall at the end. */
9683                 if (!old_other_state->fb || !new_other_state->fb)
9684                         continue;
9685
9686                 /* Pixel format changes can require bandwidth updates. */
9687                 if (old_other_state->fb->format != new_other_state->fb->format)
9688                         return true;
9689
9690                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9691                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9692
9693                 /* Tiling and DCC changes also require bandwidth updates. */
9694                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9695                     old_afb->base.modifier != new_afb->base.modifier)
9696                         return true;
9697         }
9698
9699         return false;
9700 }
9701
9702 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9703                               struct drm_plane_state *new_plane_state,
9704                               struct drm_framebuffer *fb)
9705 {
9706         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9707         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9708         unsigned int pitch;
9709         bool linear;
9710
9711         if (fb->width > new_acrtc->max_cursor_width ||
9712             fb->height > new_acrtc->max_cursor_height) {
9713                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9714                                  new_plane_state->fb->width,
9715                                  new_plane_state->fb->height);
9716                 return -EINVAL;
9717         }
9718         if (new_plane_state->src_w != fb->width << 16 ||
9719             new_plane_state->src_h != fb->height << 16) {
9720                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9721                 return -EINVAL;
9722         }
9723
9724         /* Pitch in pixels */
9725         pitch = fb->pitches[0] / fb->format->cpp[0];
9726
9727         if (fb->width != pitch) {
9728                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9729                                  fb->width, pitch);
9730                 return -EINVAL;
9731         }
9732
9733         switch (pitch) {
9734         case 64:
9735         case 128:
9736         case 256:
9737                 /* FB pitch is supported by cursor plane */
9738                 break;
9739         default:
9740                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9741                 return -EINVAL;
9742         }
9743
9744         /* Core DRM takes care of checking FB modifiers, so we only need to
9745          * check tiling flags when the FB doesn't have a modifier.
9746          */
9747         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9748                 if (adev->family < AMDGPU_FAMILY_AI) {
9749                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9750                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9751                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9752                 } else {
9753                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9754                 }
9755                 if (!linear) {
9756                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9757                         return -EINVAL;
9758                 }
9759         }
9760
9761         return 0;
9762 }
9763
9764 static int dm_update_plane_state(struct dc *dc,
9765                                  struct drm_atomic_state *state,
9766                                  struct drm_plane *plane,
9767                                  struct drm_plane_state *old_plane_state,
9768                                  struct drm_plane_state *new_plane_state,
9769                                  bool enable,
9770                                  bool *lock_and_validation_needed,
9771                                  bool *is_top_most_overlay)
9772 {
9773
9774         struct dm_atomic_state *dm_state = NULL;
9775         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9776         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9777         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9778         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9779         struct amdgpu_crtc *new_acrtc;
9780         bool needs_reset;
9781         int ret = 0;
9782
9783
9784         new_plane_crtc = new_plane_state->crtc;
9785         old_plane_crtc = old_plane_state->crtc;
9786         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9787         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9788
9789         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9790                 if (!enable || !new_plane_crtc ||
9791                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9792                         return 0;
9793
9794                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9795
9796                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9797                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9798                         return -EINVAL;
9799                 }
9800
9801                 if (new_plane_state->fb) {
9802                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9803                                                  new_plane_state->fb);
9804                         if (ret)
9805                                 return ret;
9806                 }
9807
9808                 return 0;
9809         }
9810
9811         needs_reset = should_reset_plane(state, plane, old_plane_state,
9812                                          new_plane_state);
9813
9814         /* Remove any changed/removed planes */
9815         if (!enable) {
9816                 if (!needs_reset)
9817                         return 0;
9818
9819                 if (!old_plane_crtc)
9820                         return 0;
9821
9822                 old_crtc_state = drm_atomic_get_old_crtc_state(
9823                                 state, old_plane_crtc);
9824                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9825
9826                 if (!dm_old_crtc_state->stream)
9827                         return 0;
9828
9829                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9830                                 plane->base.id, old_plane_crtc->base.id);
9831
9832                 ret = dm_atomic_get_state(state, &dm_state);
9833                 if (ret)
9834                         return ret;
9835
9836                 if (!dc_remove_plane_from_context(
9837                                 dc,
9838                                 dm_old_crtc_state->stream,
9839                                 dm_old_plane_state->dc_state,
9840                                 dm_state->context)) {
9841
9842                         return -EINVAL;
9843                 }
9844
9845                 if (dm_old_plane_state->dc_state)
9846                         dc_plane_state_release(dm_old_plane_state->dc_state);
9847
9848                 dm_new_plane_state->dc_state = NULL;
9849
9850                 *lock_and_validation_needed = true;
9851
9852         } else { /* Add new planes */
9853                 struct dc_plane_state *dc_new_plane_state;
9854
9855                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9856                         return 0;
9857
9858                 if (!new_plane_crtc)
9859                         return 0;
9860
9861                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9862                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9863
9864                 if (!dm_new_crtc_state->stream)
9865                         return 0;
9866
9867                 if (!needs_reset)
9868                         return 0;
9869
9870                 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9871                 if (ret)
9872                         return ret;
9873
9874                 WARN_ON(dm_new_plane_state->dc_state);
9875
9876                 dc_new_plane_state = dc_create_plane_state(dc);
9877                 if (!dc_new_plane_state)
9878                         return -ENOMEM;
9879
9880                 /* Block top most plane from being a video plane */
9881                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9882                         if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9883                                 return -EINVAL;
9884
9885                         *is_top_most_overlay = false;
9886                 }
9887
9888                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9889                                  plane->base.id, new_plane_crtc->base.id);
9890
9891                 ret = fill_dc_plane_attributes(
9892                         drm_to_adev(new_plane_crtc->dev),
9893                         dc_new_plane_state,
9894                         new_plane_state,
9895                         new_crtc_state);
9896                 if (ret) {
9897                         dc_plane_state_release(dc_new_plane_state);
9898                         return ret;
9899                 }
9900
9901                 ret = dm_atomic_get_state(state, &dm_state);
9902                 if (ret) {
9903                         dc_plane_state_release(dc_new_plane_state);
9904                         return ret;
9905                 }
9906
9907                 /*
9908                  * Any atomic check errors that occur after this will
9909                  * not need a release. The plane state will be attached
9910                  * to the stream, and therefore part of the atomic
9911                  * state. It'll be released when the atomic state is
9912                  * cleaned.
9913                  */
9914                 if (!dc_add_plane_to_context(
9915                                 dc,
9916                                 dm_new_crtc_state->stream,
9917                                 dc_new_plane_state,
9918                                 dm_state->context)) {
9919
9920                         dc_plane_state_release(dc_new_plane_state);
9921                         return -EINVAL;
9922                 }
9923
9924                 dm_new_plane_state->dc_state = dc_new_plane_state;
9925
9926                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9927
9928                 /* Tell DC to do a full surface update every time there
9929                  * is a plane change. Inefficient, but works for now.
9930                  */
9931                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9932
9933                 *lock_and_validation_needed = true;
9934         }
9935
9936
9937         return ret;
9938 }
9939
9940 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9941                                        int *src_w, int *src_h)
9942 {
9943         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9944         case DRM_MODE_ROTATE_90:
9945         case DRM_MODE_ROTATE_270:
9946                 *src_w = plane_state->src_h >> 16;
9947                 *src_h = plane_state->src_w >> 16;
9948                 break;
9949         case DRM_MODE_ROTATE_0:
9950         case DRM_MODE_ROTATE_180:
9951         default:
9952                 *src_w = plane_state->src_w >> 16;
9953                 *src_h = plane_state->src_h >> 16;
9954                 break;
9955         }
9956 }
9957
9958 static void
9959 dm_get_plane_scale(struct drm_plane_state *plane_state,
9960                    int *out_plane_scale_w, int *out_plane_scale_h)
9961 {
9962         int plane_src_w, plane_src_h;
9963
9964         dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h);
9965         *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w;
9966         *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h;
9967 }
9968
9969 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9970                                 struct drm_crtc *crtc,
9971                                 struct drm_crtc_state *new_crtc_state)
9972 {
9973         struct drm_plane *cursor = crtc->cursor, *plane, *underlying;
9974         struct drm_plane_state *old_plane_state, *new_plane_state;
9975         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9976         int i;
9977         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9978         bool any_relevant_change = false;
9979
9980         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9981          * cursor per pipe but it's going to inherit the scaling and
9982          * positioning from the underlying pipe. Check the cursor plane's
9983          * blending properties match the underlying planes'.
9984          */
9985
9986         /* If no plane was enabled or changed scaling, no need to check again */
9987         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9988                 int new_scale_w, new_scale_h, old_scale_w, old_scale_h;
9989
9990                 if (!new_plane_state || !new_plane_state->fb || new_plane_state->crtc != crtc)
9991                         continue;
9992
9993                 if (!old_plane_state || !old_plane_state->fb || old_plane_state->crtc != crtc) {
9994                         any_relevant_change = true;
9995                         break;
9996                 }
9997
9998                 if (new_plane_state->fb == old_plane_state->fb &&
9999                     new_plane_state->crtc_w == old_plane_state->crtc_w &&
10000                     new_plane_state->crtc_h == old_plane_state->crtc_h)
10001                         continue;
10002
10003                 dm_get_plane_scale(new_plane_state, &new_scale_w, &new_scale_h);
10004                 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h);
10005
10006                 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) {
10007                         any_relevant_change = true;
10008                         break;
10009                 }
10010         }
10011
10012         if (!any_relevant_change)
10013                 return 0;
10014
10015         new_cursor_state = drm_atomic_get_plane_state(state, cursor);
10016         if (IS_ERR(new_cursor_state))
10017                 return PTR_ERR(new_cursor_state);
10018
10019         if (!new_cursor_state->fb)
10020                 return 0;
10021
10022         dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h);
10023
10024         /* Need to check all enabled planes, even if this commit doesn't change
10025          * their state
10026          */
10027         i = drm_atomic_add_affected_planes(state, crtc);
10028         if (i)
10029                 return i;
10030
10031         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
10032                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
10033                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
10034                         continue;
10035
10036                 /* Ignore disabled planes */
10037                 if (!new_underlying_state->fb)
10038                         continue;
10039
10040                 dm_get_plane_scale(new_underlying_state,
10041                                    &underlying_scale_w, &underlying_scale_h);
10042
10043                 if (cursor_scale_w != underlying_scale_w ||
10044                     cursor_scale_h != underlying_scale_h) {
10045                         drm_dbg_atomic(crtc->dev,
10046                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
10047                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
10048                         return -EINVAL;
10049                 }
10050
10051                 /* If this plane covers the whole CRTC, no need to check planes underneath */
10052                 if (new_underlying_state->crtc_x <= 0 &&
10053                     new_underlying_state->crtc_y <= 0 &&
10054                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
10055                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
10056                         break;
10057         }
10058
10059         return 0;
10060 }
10061
10062 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
10063 {
10064         struct drm_connector *connector;
10065         struct drm_connector_state *conn_state, *old_conn_state;
10066         struct amdgpu_dm_connector *aconnector = NULL;
10067         int i;
10068
10069         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
10070                 if (!conn_state->crtc)
10071                         conn_state = old_conn_state;
10072
10073                 if (conn_state->crtc != crtc)
10074                         continue;
10075
10076                 aconnector = to_amdgpu_dm_connector(connector);
10077                 if (!aconnector->mst_output_port || !aconnector->mst_root)
10078                         aconnector = NULL;
10079                 else
10080                         break;
10081         }
10082
10083         if (!aconnector)
10084                 return 0;
10085
10086         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
10087 }
10088
10089 /**
10090  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
10091  *
10092  * @dev: The DRM device
10093  * @state: The atomic state to commit
10094  *
10095  * Validate that the given atomic state is programmable by DC into hardware.
10096  * This involves constructing a &struct dc_state reflecting the new hardware
10097  * state we wish to commit, then querying DC to see if it is programmable. It's
10098  * important not to modify the existing DC state. Otherwise, atomic_check
10099  * may unexpectedly commit hardware changes.
10100  *
10101  * When validating the DC state, it's important that the right locks are
10102  * acquired. For full updates case which removes/adds/updates streams on one
10103  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
10104  * that any such full update commit will wait for completion of any outstanding
10105  * flip using DRMs synchronization events.
10106  *
10107  * Note that DM adds the affected connectors for all CRTCs in state, when that
10108  * might not seem necessary. This is because DC stream creation requires the
10109  * DC sink, which is tied to the DRM connector state. Cleaning this up should
10110  * be possible but non-trivial - a possible TODO item.
10111  *
10112  * Return: -Error code if validation failed.
10113  */
10114 static int amdgpu_dm_atomic_check(struct drm_device *dev,
10115                                   struct drm_atomic_state *state)
10116 {
10117         struct amdgpu_device *adev = drm_to_adev(dev);
10118         struct dm_atomic_state *dm_state = NULL;
10119         struct dc *dc = adev->dm.dc;
10120         struct drm_connector *connector;
10121         struct drm_connector_state *old_con_state, *new_con_state;
10122         struct drm_crtc *crtc;
10123         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
10124         struct drm_plane *plane;
10125         struct drm_plane_state *old_plane_state, *new_plane_state;
10126         enum dc_status status;
10127         int ret, i;
10128         bool lock_and_validation_needed = false;
10129         bool is_top_most_overlay = true;
10130         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
10131         struct drm_dp_mst_topology_mgr *mgr;
10132         struct drm_dp_mst_topology_state *mst_state;
10133         struct dsc_mst_fairness_vars vars[MAX_PIPES];
10134
10135         trace_amdgpu_dm_atomic_check_begin(state);
10136
10137         ret = drm_atomic_helper_check_modeset(dev, state);
10138         if (ret) {
10139                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
10140                 goto fail;
10141         }
10142
10143         /* Check connector changes */
10144         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10145                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10146                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10147
10148                 /* Skip connectors that are disabled or part of modeset already. */
10149                 if (!new_con_state->crtc)
10150                         continue;
10151
10152                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
10153                 if (IS_ERR(new_crtc_state)) {
10154                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
10155                         ret = PTR_ERR(new_crtc_state);
10156                         goto fail;
10157                 }
10158
10159                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
10160                     dm_old_con_state->scaling != dm_new_con_state->scaling)
10161                         new_crtc_state->connectors_changed = true;
10162         }
10163
10164         if (dc_resource_is_dsc_encoding_supported(dc)) {
10165                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10166                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
10167                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
10168                                 if (ret) {
10169                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
10170                                         goto fail;
10171                                 }
10172                         }
10173                 }
10174         }
10175         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10176                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10177
10178                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
10179                     !new_crtc_state->color_mgmt_changed &&
10180                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
10181                         dm_old_crtc_state->dsc_force_changed == false)
10182                         continue;
10183
10184                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
10185                 if (ret) {
10186                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
10187                         goto fail;
10188                 }
10189
10190                 if (!new_crtc_state->enable)
10191                         continue;
10192
10193                 ret = drm_atomic_add_affected_connectors(state, crtc);
10194                 if (ret) {
10195                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
10196                         goto fail;
10197                 }
10198
10199                 ret = drm_atomic_add_affected_planes(state, crtc);
10200                 if (ret) {
10201                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
10202                         goto fail;
10203                 }
10204
10205                 if (dm_old_crtc_state->dsc_force_changed)
10206                         new_crtc_state->mode_changed = true;
10207         }
10208
10209         /*
10210          * Add all primary and overlay planes on the CRTC to the state
10211          * whenever a plane is enabled to maintain correct z-ordering
10212          * and to enable fast surface updates.
10213          */
10214         drm_for_each_crtc(crtc, dev) {
10215                 bool modified = false;
10216
10217                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10218                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10219                                 continue;
10220
10221                         if (new_plane_state->crtc == crtc ||
10222                             old_plane_state->crtc == crtc) {
10223                                 modified = true;
10224                                 break;
10225                         }
10226                 }
10227
10228                 if (!modified)
10229                         continue;
10230
10231                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
10232                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10233                                 continue;
10234
10235                         new_plane_state =
10236                                 drm_atomic_get_plane_state(state, plane);
10237
10238                         if (IS_ERR(new_plane_state)) {
10239                                 ret = PTR_ERR(new_plane_state);
10240                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
10241                                 goto fail;
10242                         }
10243                 }
10244         }
10245
10246         /*
10247          * DC consults the zpos (layer_index in DC terminology) to determine the
10248          * hw plane on which to enable the hw cursor (see
10249          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
10250          * atomic state, so call drm helper to normalize zpos.
10251          */
10252         ret = drm_atomic_normalize_zpos(dev, state);
10253         if (ret) {
10254                 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10255                 goto fail;
10256         }
10257
10258         /* Remove exiting planes if they are modified */
10259         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10260                 if (old_plane_state->fb && new_plane_state->fb &&
10261                     get_mem_type(old_plane_state->fb) !=
10262                     get_mem_type(new_plane_state->fb))
10263                         lock_and_validation_needed = true;
10264
10265                 ret = dm_update_plane_state(dc, state, plane,
10266                                             old_plane_state,
10267                                             new_plane_state,
10268                                             false,
10269                                             &lock_and_validation_needed,
10270                                             &is_top_most_overlay);
10271                 if (ret) {
10272                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10273                         goto fail;
10274                 }
10275         }
10276
10277         /* Disable all crtcs which require disable */
10278         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10279                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10280                                            old_crtc_state,
10281                                            new_crtc_state,
10282                                            false,
10283                                            &lock_and_validation_needed);
10284                 if (ret) {
10285                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10286                         goto fail;
10287                 }
10288         }
10289
10290         /* Enable all crtcs which require enable */
10291         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10292                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10293                                            old_crtc_state,
10294                                            new_crtc_state,
10295                                            true,
10296                                            &lock_and_validation_needed);
10297                 if (ret) {
10298                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10299                         goto fail;
10300                 }
10301         }
10302
10303         /* Add new/modified planes */
10304         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10305                 ret = dm_update_plane_state(dc, state, plane,
10306                                             old_plane_state,
10307                                             new_plane_state,
10308                                             true,
10309                                             &lock_and_validation_needed,
10310                                             &is_top_most_overlay);
10311                 if (ret) {
10312                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10313                         goto fail;
10314                 }
10315         }
10316
10317         if (dc_resource_is_dsc_encoding_supported(dc)) {
10318                 ret = pre_validate_dsc(state, &dm_state, vars);
10319                 if (ret != 0)
10320                         goto fail;
10321         }
10322
10323         /* Run this here since we want to validate the streams we created */
10324         ret = drm_atomic_helper_check_planes(dev, state);
10325         if (ret) {
10326                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10327                 goto fail;
10328         }
10329
10330         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10331                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10332                 if (dm_new_crtc_state->mpo_requested)
10333                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10334         }
10335
10336         /* Check cursor planes scaling */
10337         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10338                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10339                 if (ret) {
10340                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10341                         goto fail;
10342                 }
10343         }
10344
10345         if (state->legacy_cursor_update) {
10346                 /*
10347                  * This is a fast cursor update coming from the plane update
10348                  * helper, check if it can be done asynchronously for better
10349                  * performance.
10350                  */
10351                 state->async_update =
10352                         !drm_atomic_helper_async_check(dev, state);
10353
10354                 /*
10355                  * Skip the remaining global validation if this is an async
10356                  * update. Cursor updates can be done without affecting
10357                  * state or bandwidth calcs and this avoids the performance
10358                  * penalty of locking the private state object and
10359                  * allocating a new dc_state.
10360                  */
10361                 if (state->async_update)
10362                         return 0;
10363         }
10364
10365         /* Check scaling and underscan changes*/
10366         /* TODO Removed scaling changes validation due to inability to commit
10367          * new stream into context w\o causing full reset. Need to
10368          * decide how to handle.
10369          */
10370         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10371                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10372                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10373                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10374
10375                 /* Skip any modesets/resets */
10376                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10377                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10378                         continue;
10379
10380                 /* Skip any thing not scale or underscan changes */
10381                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10382                         continue;
10383
10384                 lock_and_validation_needed = true;
10385         }
10386
10387         /* set the slot info for each mst_state based on the link encoding format */
10388         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10389                 struct amdgpu_dm_connector *aconnector;
10390                 struct drm_connector *connector;
10391                 struct drm_connector_list_iter iter;
10392                 u8 link_coding_cap;
10393
10394                 drm_connector_list_iter_begin(dev, &iter);
10395                 drm_for_each_connector_iter(connector, &iter) {
10396                         if (connector->index == mst_state->mgr->conn_base_id) {
10397                                 aconnector = to_amdgpu_dm_connector(connector);
10398                                 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10399                                 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10400
10401                                 break;
10402                         }
10403                 }
10404                 drm_connector_list_iter_end(&iter);
10405         }
10406
10407         /**
10408          * Streams and planes are reset when there are changes that affect
10409          * bandwidth. Anything that affects bandwidth needs to go through
10410          * DC global validation to ensure that the configuration can be applied
10411          * to hardware.
10412          *
10413          * We have to currently stall out here in atomic_check for outstanding
10414          * commits to finish in this case because our IRQ handlers reference
10415          * DRM state directly - we can end up disabling interrupts too early
10416          * if we don't.
10417          *
10418          * TODO: Remove this stall and drop DM state private objects.
10419          */
10420         if (lock_and_validation_needed) {
10421                 ret = dm_atomic_get_state(state, &dm_state);
10422                 if (ret) {
10423                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10424                         goto fail;
10425                 }
10426
10427                 ret = do_aquire_global_lock(dev, state);
10428                 if (ret) {
10429                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10430                         goto fail;
10431                 }
10432
10433                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10434                 if (ret) {
10435                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10436                         ret = -EINVAL;
10437                         goto fail;
10438                 }
10439
10440                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10441                 if (ret) {
10442                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10443                         goto fail;
10444                 }
10445
10446                 /*
10447                  * Perform validation of MST topology in the state:
10448                  * We need to perform MST atomic check before calling
10449                  * dc_validate_global_state(), or there is a chance
10450                  * to get stuck in an infinite loop and hang eventually.
10451                  */
10452                 ret = drm_dp_mst_atomic_check(state);
10453                 if (ret) {
10454                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10455                         goto fail;
10456                 }
10457                 status = dc_validate_global_state(dc, dm_state->context, true);
10458                 if (status != DC_OK) {
10459                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10460                                        dc_status_to_str(status), status);
10461                         ret = -EINVAL;
10462                         goto fail;
10463                 }
10464         } else {
10465                 /*
10466                  * The commit is a fast update. Fast updates shouldn't change
10467                  * the DC context, affect global validation, and can have their
10468                  * commit work done in parallel with other commits not touching
10469                  * the same resource. If we have a new DC context as part of
10470                  * the DM atomic state from validation we need to free it and
10471                  * retain the existing one instead.
10472                  *
10473                  * Furthermore, since the DM atomic state only contains the DC
10474                  * context and can safely be annulled, we can free the state
10475                  * and clear the associated private object now to free
10476                  * some memory and avoid a possible use-after-free later.
10477                  */
10478
10479                 for (i = 0; i < state->num_private_objs; i++) {
10480                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10481
10482                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10483                                 int j = state->num_private_objs-1;
10484
10485                                 dm_atomic_destroy_state(obj,
10486                                                 state->private_objs[i].state);
10487
10488                                 /* If i is not at the end of the array then the
10489                                  * last element needs to be moved to where i was
10490                                  * before the array can safely be truncated.
10491                                  */
10492                                 if (i != j)
10493                                         state->private_objs[i] =
10494                                                 state->private_objs[j];
10495
10496                                 state->private_objs[j].ptr = NULL;
10497                                 state->private_objs[j].state = NULL;
10498                                 state->private_objs[j].old_state = NULL;
10499                                 state->private_objs[j].new_state = NULL;
10500
10501                                 state->num_private_objs = j;
10502                                 break;
10503                         }
10504                 }
10505         }
10506
10507         /* Store the overall update type for use later in atomic check. */
10508         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10509                 struct dm_crtc_state *dm_new_crtc_state =
10510                         to_dm_crtc_state(new_crtc_state);
10511
10512                 /*
10513                  * Only allow async flips for fast updates that don't change
10514                  * the FB pitch, the DCC state, rotation, etc.
10515                  */
10516                 if (new_crtc_state->async_flip && lock_and_validation_needed) {
10517                         drm_dbg_atomic(crtc->dev,
10518                                        "[CRTC:%d:%s] async flips are only supported for fast updates\n",
10519                                        crtc->base.id, crtc->name);
10520                         ret = -EINVAL;
10521                         goto fail;
10522                 }
10523
10524                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10525                         UPDATE_TYPE_FULL : UPDATE_TYPE_FAST;
10526         }
10527
10528         /* Must be success */
10529         WARN_ON(ret);
10530
10531         trace_amdgpu_dm_atomic_check_finish(state, ret);
10532
10533         return ret;
10534
10535 fail:
10536         if (ret == -EDEADLK)
10537                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10538         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10539                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10540         else
10541                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret);
10542
10543         trace_amdgpu_dm_atomic_check_finish(state, ret);
10544
10545         return ret;
10546 }
10547
10548 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10549                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10550 {
10551         u8 dpcd_data;
10552         bool capable = false;
10553
10554         if (amdgpu_dm_connector->dc_link &&
10555                 dm_helpers_dp_read_dpcd(
10556                                 NULL,
10557                                 amdgpu_dm_connector->dc_link,
10558                                 DP_DOWN_STREAM_PORT_COUNT,
10559                                 &dpcd_data,
10560                                 sizeof(dpcd_data))) {
10561                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10562         }
10563
10564         return capable;
10565 }
10566
10567 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10568                 unsigned int offset,
10569                 unsigned int total_length,
10570                 u8 *data,
10571                 unsigned int length,
10572                 struct amdgpu_hdmi_vsdb_info *vsdb)
10573 {
10574         bool res;
10575         union dmub_rb_cmd cmd;
10576         struct dmub_cmd_send_edid_cea *input;
10577         struct dmub_cmd_edid_cea_output *output;
10578
10579         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10580                 return false;
10581
10582         memset(&cmd, 0, sizeof(cmd));
10583
10584         input = &cmd.edid_cea.data.input;
10585
10586         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10587         cmd.edid_cea.header.sub_type = 0;
10588         cmd.edid_cea.header.payload_bytes =
10589                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10590         input->offset = offset;
10591         input->length = length;
10592         input->cea_total_length = total_length;
10593         memcpy(input->payload, data, length);
10594
10595         res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
10596         if (!res) {
10597                 DRM_ERROR("EDID CEA parser failed\n");
10598                 return false;
10599         }
10600
10601         output = &cmd.edid_cea.data.output;
10602
10603         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10604                 if (!output->ack.success) {
10605                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
10606                                         output->ack.offset);
10607                 }
10608         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10609                 if (!output->amd_vsdb.vsdb_found)
10610                         return false;
10611
10612                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10613                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10614                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10615                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10616         } else {
10617                 DRM_WARN("Unknown EDID CEA parser results\n");
10618                 return false;
10619         }
10620
10621         return true;
10622 }
10623
10624 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10625                 u8 *edid_ext, int len,
10626                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10627 {
10628         int i;
10629
10630         /* send extension block to DMCU for parsing */
10631         for (i = 0; i < len; i += 8) {
10632                 bool res;
10633                 int offset;
10634
10635                 /* send 8 bytes a time */
10636                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10637                         return false;
10638
10639                 if (i+8 == len) {
10640                         /* EDID block sent completed, expect result */
10641                         int version, min_rate, max_rate;
10642
10643                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10644                         if (res) {
10645                                 /* amd vsdb found */
10646                                 vsdb_info->freesync_supported = 1;
10647                                 vsdb_info->amd_vsdb_version = version;
10648                                 vsdb_info->min_refresh_rate_hz = min_rate;
10649                                 vsdb_info->max_refresh_rate_hz = max_rate;
10650                                 return true;
10651                         }
10652                         /* not amd vsdb */
10653                         return false;
10654                 }
10655
10656                 /* check for ack*/
10657                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10658                 if (!res)
10659                         return false;
10660         }
10661
10662         return false;
10663 }
10664
10665 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10666                 u8 *edid_ext, int len,
10667                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10668 {
10669         int i;
10670
10671         /* send extension block to DMCU for parsing */
10672         for (i = 0; i < len; i += 8) {
10673                 /* send 8 bytes a time */
10674                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10675                         return false;
10676         }
10677
10678         return vsdb_info->freesync_supported;
10679 }
10680
10681 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10682                 u8 *edid_ext, int len,
10683                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10684 {
10685         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10686         bool ret;
10687
10688         mutex_lock(&adev->dm.dc_lock);
10689         if (adev->dm.dmub_srv)
10690                 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10691         else
10692                 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10693         mutex_unlock(&adev->dm.dc_lock);
10694         return ret;
10695 }
10696
10697 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10698                           struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10699 {
10700         u8 *edid_ext = NULL;
10701         int i;
10702         int j = 0;
10703
10704         if (edid == NULL || edid->extensions == 0)
10705                 return -ENODEV;
10706
10707         /* Find DisplayID extension */
10708         for (i = 0; i < edid->extensions; i++) {
10709                 edid_ext = (void *)(edid + (i + 1));
10710                 if (edid_ext[0] == DISPLAYID_EXT)
10711                         break;
10712         }
10713
10714         while (j < EDID_LENGTH) {
10715                 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
10716                 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
10717
10718                 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID &&
10719                                 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) {
10720                         vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;
10721                         vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3;
10722                         DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode);
10723
10724                         return true;
10725                 }
10726                 j++;
10727         }
10728
10729         return false;
10730 }
10731
10732 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10733                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10734 {
10735         u8 *edid_ext = NULL;
10736         int i;
10737         bool valid_vsdb_found = false;
10738
10739         /*----- drm_find_cea_extension() -----*/
10740         /* No EDID or EDID extensions */
10741         if (edid == NULL || edid->extensions == 0)
10742                 return -ENODEV;
10743
10744         /* Find CEA extension */
10745         for (i = 0; i < edid->extensions; i++) {
10746                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10747                 if (edid_ext[0] == CEA_EXT)
10748                         break;
10749         }
10750
10751         if (i == edid->extensions)
10752                 return -ENODEV;
10753
10754         /*----- cea_db_offsets() -----*/
10755         if (edid_ext[0] != CEA_EXT)
10756                 return -ENODEV;
10757
10758         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10759
10760         return valid_vsdb_found ? i : -ENODEV;
10761 }
10762
10763 /**
10764  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10765  *
10766  * @connector: Connector to query.
10767  * @edid: EDID from monitor
10768  *
10769  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10770  * track of some of the display information in the internal data struct used by
10771  * amdgpu_dm. This function checks which type of connector we need to set the
10772  * FreeSync parameters.
10773  */
10774 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10775                                     struct edid *edid)
10776 {
10777         int i = 0;
10778         struct detailed_timing *timing;
10779         struct detailed_non_pixel *data;
10780         struct detailed_data_monitor_range *range;
10781         struct amdgpu_dm_connector *amdgpu_dm_connector =
10782                         to_amdgpu_dm_connector(connector);
10783         struct dm_connector_state *dm_con_state = NULL;
10784         struct dc_sink *sink;
10785
10786         struct drm_device *dev = connector->dev;
10787         struct amdgpu_device *adev = drm_to_adev(dev);
10788         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10789         bool freesync_capable = false;
10790         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10791
10792         if (!connector->state) {
10793                 DRM_ERROR("%s - Connector has no state", __func__);
10794                 goto update;
10795         }
10796
10797         sink = amdgpu_dm_connector->dc_sink ?
10798                 amdgpu_dm_connector->dc_sink :
10799                 amdgpu_dm_connector->dc_em_sink;
10800
10801         if (!edid || !sink) {
10802                 dm_con_state = to_dm_connector_state(connector->state);
10803
10804                 amdgpu_dm_connector->min_vfreq = 0;
10805                 amdgpu_dm_connector->max_vfreq = 0;
10806                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10807                 connector->display_info.monitor_range.min_vfreq = 0;
10808                 connector->display_info.monitor_range.max_vfreq = 0;
10809                 freesync_capable = false;
10810
10811                 goto update;
10812         }
10813
10814         dm_con_state = to_dm_connector_state(connector->state);
10815
10816         if (!adev->dm.freesync_module)
10817                 goto update;
10818
10819         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10820                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10821                 bool edid_check_required = false;
10822
10823                 if (edid) {
10824                         edid_check_required = is_dp_capable_without_timing_msa(
10825                                                 adev->dm.dc,
10826                                                 amdgpu_dm_connector);
10827                 }
10828
10829                 if (edid_check_required == true && (edid->version > 1 ||
10830                    (edid->version == 1 && edid->revision > 1))) {
10831                         for (i = 0; i < 4; i++) {
10832
10833                                 timing  = &edid->detailed_timings[i];
10834                                 data    = &timing->data.other_data;
10835                                 range   = &data->data.range;
10836                                 /*
10837                                  * Check if monitor has continuous frequency mode
10838                                  */
10839                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10840                                         continue;
10841                                 /*
10842                                  * Check for flag range limits only. If flag == 1 then
10843                                  * no additional timing information provided.
10844                                  * Default GTF, GTF Secondary curve and CVT are not
10845                                  * supported
10846                                  */
10847                                 if (range->flags != 1)
10848                                         continue;
10849
10850                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10851                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10852                                 amdgpu_dm_connector->pixel_clock_mhz =
10853                                         range->pixel_clock_mhz * 10;
10854
10855                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10856                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10857
10858                                 break;
10859                         }
10860
10861                         if (amdgpu_dm_connector->max_vfreq -
10862                             amdgpu_dm_connector->min_vfreq > 10) {
10863
10864                                 freesync_capable = true;
10865                         }
10866                 }
10867                 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10868
10869                 if (vsdb_info.replay_mode) {
10870                         amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;
10871                         amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version;
10872                         amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;
10873                 }
10874
10875         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10876                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10877                 if (i >= 0 && vsdb_info.freesync_supported) {
10878                         timing  = &edid->detailed_timings[i];
10879                         data    = &timing->data.other_data;
10880
10881                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10882                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10883                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10884                                 freesync_capable = true;
10885
10886                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10887                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10888                 }
10889         }
10890
10891         as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10892
10893         if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10894                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10895                 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10896
10897                         amdgpu_dm_connector->pack_sdp_v1_3 = true;
10898                         amdgpu_dm_connector->as_type = as_type;
10899                         amdgpu_dm_connector->vsdb_info = vsdb_info;
10900
10901                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10902                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10903                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10904                                 freesync_capable = true;
10905
10906                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10907                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10908                 }
10909         }
10910
10911 update:
10912         if (dm_con_state)
10913                 dm_con_state->freesync_capable = freesync_capable;
10914
10915         if (connector->vrr_capable_property)
10916                 drm_connector_set_vrr_capable_property(connector,
10917                                                        freesync_capable);
10918 }
10919
10920 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10921 {
10922         struct amdgpu_device *adev = drm_to_adev(dev);
10923         struct dc *dc = adev->dm.dc;
10924         int i;
10925
10926         mutex_lock(&adev->dm.dc_lock);
10927         if (dc->current_state) {
10928                 for (i = 0; i < dc->current_state->stream_count; ++i)
10929                         dc->current_state->streams[i]
10930                                 ->triggered_crtc_reset.enabled =
10931                                 adev->dm.force_timing_sync;
10932
10933                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10934                 dc_trigger_sync(dc, dc->current_state);
10935         }
10936         mutex_unlock(&adev->dm.dc_lock);
10937 }
10938
10939 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10940                        u32 value, const char *func_name)
10941 {
10942 #ifdef DM_CHECK_ADDR_0
10943         if (address == 0) {
10944                 drm_err(adev_to_drm(ctx->driver_context),
10945                         "invalid register write. address = 0");
10946                 return;
10947         }
10948 #endif
10949         cgs_write_register(ctx->cgs_device, address, value);
10950         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10951 }
10952
10953 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10954                           const char *func_name)
10955 {
10956         u32 value;
10957 #ifdef DM_CHECK_ADDR_0
10958         if (address == 0) {
10959                 drm_err(adev_to_drm(ctx->driver_context),
10960                         "invalid register read; address = 0\n");
10961                 return 0;
10962         }
10963 #endif
10964
10965         if (ctx->dmub_srv &&
10966             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10967             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10968                 ASSERT(false);
10969                 return 0;
10970         }
10971
10972         value = cgs_read_register(ctx->cgs_device, address);
10973
10974         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10975
10976         return value;
10977 }
10978
10979 int amdgpu_dm_process_dmub_aux_transfer_sync(
10980                 struct dc_context *ctx,
10981                 unsigned int link_index,
10982                 struct aux_payload *payload,
10983                 enum aux_return_code_type *operation_result)
10984 {
10985         struct amdgpu_device *adev = ctx->driver_context;
10986         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10987         int ret = -1;
10988
10989         mutex_lock(&adev->dm.dpia_aux_lock);
10990         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10991                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10992                 goto out;
10993         }
10994
10995         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10996                 DRM_ERROR("wait_for_completion_timeout timeout!");
10997                 *operation_result = AUX_RET_ERROR_TIMEOUT;
10998                 goto out;
10999         }
11000
11001         if (p_notify->result != AUX_RET_SUCCESS) {
11002                 /*
11003                  * Transient states before tunneling is enabled could
11004                  * lead to this error. We can ignore this for now.
11005                  */
11006                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
11007                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
11008                                         payload->address, payload->length,
11009                                         p_notify->result);
11010                 }
11011                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
11012                 goto out;
11013         }
11014
11015
11016         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
11017         if (!payload->write && p_notify->aux_reply.length &&
11018                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
11019
11020                 if (payload->length != p_notify->aux_reply.length) {
11021                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
11022                                 p_notify->aux_reply.length,
11023                                         payload->address, payload->length);
11024                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
11025                         goto out;
11026                 }
11027
11028                 memcpy(payload->data, p_notify->aux_reply.data,
11029                                 p_notify->aux_reply.length);
11030         }
11031
11032         /* success */
11033         ret = p_notify->aux_reply.length;
11034         *operation_result = p_notify->result;
11035 out:
11036         reinit_completion(&adev->dm.dmub_aux_transfer_done);
11037         mutex_unlock(&adev->dm.dpia_aux_lock);
11038         return ret;
11039 }
11040
11041 int amdgpu_dm_process_dmub_set_config_sync(
11042                 struct dc_context *ctx,
11043                 unsigned int link_index,
11044                 struct set_config_cmd_payload *payload,
11045                 enum set_config_status *operation_result)
11046 {
11047         struct amdgpu_device *adev = ctx->driver_context;
11048         bool is_cmd_complete;
11049         int ret;
11050
11051         mutex_lock(&adev->dm.dpia_aux_lock);
11052         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
11053                         link_index, payload, adev->dm.dmub_notify);
11054
11055         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
11056                 ret = 0;
11057                 *operation_result = adev->dm.dmub_notify->sc_status;
11058         } else {
11059                 DRM_ERROR("wait_for_completion_timeout timeout!");
11060                 ret = -1;
11061                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
11062         }
11063
11064         if (!is_cmd_complete)
11065                 reinit_completion(&adev->dm.dmub_aux_transfer_done);
11066         mutex_unlock(&adev->dm.dpia_aux_lock);
11067         return ret;
11068 }
11069
11070 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11071 {
11072         return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
11073 }
11074
11075 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11076 {
11077         return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);
11078 }