drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "link_enc_cfg.h"
  32 #include "dc/inc/core_types.h"
  33 #include "dal_asic_id.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "dc/inc/hw/dmcu.h"
  36 #include "dc/inc/hw/abm.h"
  37 #include "dc/dc_dmub_srv.h"
  38 #include "dc/dc_edid_parser.h"
  39 #include "dc/dc_stat.h"
  40 #include "amdgpu_dm_trace.h"
  41 #include "dpcd_defs.h"
  42 #include "link/protocols/link_dpcd.h"
  43 #include "link_service_types.h"
  44 #include "link/protocols/link_dp_capability.h"
  45 #include "link/protocols/link_ddc.h"
  46
  47 #include "vid.h"
  48 #include "amdgpu.h"
  49 #include "amdgpu_display.h"
  50 #include "amdgpu_ucode.h"
  51 #include "atom.h"
  52 #include "amdgpu_dm.h"
  53 #include "amdgpu_dm_plane.h"
  54 #include "amdgpu_dm_crtc.h"
  55 #include "amdgpu_dm_hdcp.h"
  56 #include <drm/display/drm_hdcp_helper.h>
  57 #include "amdgpu_pm.h"
  58 #include "amdgpu_atombios.h"
  59
  60 #include "amd_shared.h"
  61 #include "amdgpu_dm_irq.h"
  62 #include "dm_helpers.h"
  63 #include "amdgpu_dm_mst_types.h"
  64 #if defined(CONFIG_DEBUG_FS)
  65 #include "amdgpu_dm_debugfs.h"
  66 #endif
  67 #include "amdgpu_dm_psr.h"
  68
  69 #include "ivsrcid/ivsrcid_vislands30.h"
  70
  71 #include <linux/backlight.h>
  72 #include <linux/module.h>
  73 #include <linux/moduleparam.h>
  74 #include <linux/types.h>
  75 #include <linux/pm_runtime.h>
  76 #include <linux/pci.h>
  77 #include <linux/firmware.h>
  78 #include <linux/component.h>
  79 #include <linux/dmi.h>
  80
  81 #include <drm/display/drm_dp_mst_helper.h>
  82 #include <drm/display/drm_hdmi_helper.h>
  83 #include <drm/drm_atomic.h>
  84 #include <drm/drm_atomic_uapi.h>
  85 #include <drm/drm_atomic_helper.h>
  86 #include <drm/drm_blend.h>
  87 #include <drm/drm_fourcc.h>
  88 #include <drm/drm_edid.h>
  89 #include <drm/drm_vblank.h>
  90 #include <drm/drm_audio_component.h>
  91 #include <drm/drm_gem_atomic_helper.h>
  92 #include <drm/drm_plane_helper.h>
  93
  94 #include <acpi/video.h>
  95
  96 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  97
  98 #include "dcn/dcn_1_0_offset.h"
  99 #include "dcn/dcn_1_0_sh_mask.h"
 100 #include "soc15_hw_ip.h"
 101 #include "soc15_common.h"
 102 #include "vega10_ip_offset.h"
 103
 104 #include "gc/gc_11_0_0_offset.h"
 105 #include "gc/gc_11_0_0_sh_mask.h"
 106
 107 #include "modules/inc/mod_freesync.h"
 108 #include "modules/power/power_helpers.h"
 109
 110 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 111 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 112 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 113 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 114 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 115 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 116 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 117 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 118 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 119 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 120 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 121 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 122 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 123 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 124 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 125 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 126 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 127 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 128 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 129 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 130 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 131 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 132
 133 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 134 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 135 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 137
 138 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 139 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 140
 141 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 142 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 143
 144 /* Number of bytes in PSP header for firmware. */
 145 #define PSP_HEADER_BYTES 0x100
 146
 147 /* Number of bytes in PSP footer for firmware. */
 148 #define PSP_FOOTER_BYTES 0x100
 149
 150 /**
 151  * DOC: overview
 152  *
 153  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 154  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 155  * requests into DC requests, and DC responses into DRM responses.
 156  *
 157  * The root control structure is &struct amdgpu_display_manager.
 158  */
 159
 160 /* basic init/fini API */
 161 static int amdgpu_dm_init(struct amdgpu_device *adev);
 162 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 163 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 164
 165 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 166 {
 167         switch (link->dpcd_caps.dongle_type) {
 168         case DISPLAY_DONGLE_NONE:
 169                 return DRM_MODE_SUBCONNECTOR_Native;
 170         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 171                 return DRM_MODE_SUBCONNECTOR_VGA;
 172         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 173         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 174                 return DRM_MODE_SUBCONNECTOR_DVID;
 175         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 176         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 177                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 178         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 179         default:
 180                 return DRM_MODE_SUBCONNECTOR_Unknown;
 181         }
 182 }
 183
 184 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 185 {
 186         struct dc_link *link = aconnector->dc_link;
 187         struct drm_connector *connector = &aconnector->base;
 188         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 189
 190         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 191                 return;
 192
 193         if (aconnector->dc_sink)
 194                 subconnector = get_subconnector_type(link);
 195
 196         drm_object_property_set_value(&connector->base,
 197                         connector->dev->mode_config.dp_subconnector_property,
 198                         subconnector);
 199 }
 200
 201 /*
 202  * initializes drm_device display related structures, based on the information
 203  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 204  * drm_encoder, drm_mode_config
 205  *
 206  * Returns 0 on success
 207  */
 208 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 209 /* removes and deallocates the drm structures, created by the above function */
 210 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 211
 212 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 213                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 214                                     u32 link_index,
 215                                     struct amdgpu_encoder *amdgpu_encoder);
 216 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 217                                   struct amdgpu_encoder *aencoder,
 218                                   uint32_t link_index);
 219
 220 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 221
 222 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 223
 224 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 225                                   struct drm_atomic_state *state);
 226
 227 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 228 static void handle_hpd_rx_irq(void *param);
 229
 230 static bool
 231 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 232                                  struct drm_crtc_state *new_crtc_state);
 233 /*
 234  * dm_vblank_get_counter
 235  *
 236  * @brief
 237  * Get counter for number of vertical blanks
 238  *
 239  * @param
 240  * struct amdgpu_device *adev - [in] desired amdgpu device
 241  * int disp_idx - [in] which CRTC to get the counter from
 242  *
 243  * @return
 244  * Counter for vertical blanks
 245  */
 246 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 247 {
 248         if (crtc >= adev->mode_info.num_crtc)
 249                 return 0;
 250         else {
 251                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 252
 253                 if (acrtc->dm_irq_params.stream == NULL) {
 254                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 255                                   crtc);
 256                         return 0;
 257                 }
 258
 259                 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 260         }
 261 }
 262
 263 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 264                                   u32 *vbl, u32 *position)
 265 {
 266         u32 v_blank_start, v_blank_end, h_position, v_position;
 267
 268         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 269                 return -EINVAL;
 270         else {
 271                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 272
 273                 if (acrtc->dm_irq_params.stream ==  NULL) {
 274                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 275                                   crtc);
 276                         return 0;
 277                 }
 278
 279                 /*
 280                  * TODO rework base driver to use values directly.
 281                  * for now parse it back into reg-format
 282                  */
 283                 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 284                                          &v_blank_start,
 285                                          &v_blank_end,
 286                                          &h_position,
 287                                          &v_position);
 288
 289                 *position = v_position | (h_position << 16);
 290                 *vbl = v_blank_start | (v_blank_end << 16);
 291         }
 292
 293         return 0;
 294 }
 295
 296 static bool dm_is_idle(void *handle)
 297 {
 298         /* XXX todo */
 299         return true;
 300 }
 301
 302 static int dm_wait_for_idle(void *handle)
 303 {
 304         /* XXX todo */
 305         return 0;
 306 }
 307
 308 static bool dm_check_soft_reset(void *handle)
 309 {
 310         return false;
 311 }
 312
 313 static int dm_soft_reset(void *handle)
 314 {
 315         /* XXX todo */
 316         return 0;
 317 }
 318
 319 static struct amdgpu_crtc *
 320 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 321                      int otg_inst)
 322 {
 323         struct drm_device *dev = adev_to_drm(adev);
 324         struct drm_crtc *crtc;
 325         struct amdgpu_crtc *amdgpu_crtc;
 326
 327         if (WARN_ON(otg_inst == -1))
 328                 return adev->mode_info.crtcs[0];
 329
 330         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 331                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 332
 333                 if (amdgpu_crtc->otg_inst == otg_inst)
 334                         return amdgpu_crtc;
 335         }
 336
 337         return NULL;
 338 }
 339
 340 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 341                                               struct dm_crtc_state *new_state)
 342 {
 343         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 344                 return true;
 345         else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
 346                 return true;
 347         else
 348                 return false;
 349 }
 350
 351 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
 352                                         int planes_count)
 353 {
 354         int i, j;
 355
 356         for (i = 0, j = planes_count - 1; i < j; i++, j--)
 357                 swap(array_of_surface_update[i], array_of_surface_update[j]);
 358 }
 359
 360 /**
 361  * update_planes_and_stream_adapter() - Send planes to be updated in DC
 362  *
 363  * DC has a generic way to update planes and stream via
 364  * dc_update_planes_and_stream function; however, DM might need some
 365  * adjustments and preparation before calling it. This function is a wrapper
 366  * for the dc_update_planes_and_stream that does any required configuration
 367  * before passing control to DC.
 368  *
 369  * @dc: Display Core control structure
 370  * @update_type: specify whether it is FULL/MEDIUM/FAST update
 371  * @planes_count: planes count to update
 372  * @stream: stream state
 373  * @stream_update: stream update
 374  * @array_of_surface_update: dc surface update pointer
 375  *
 376  */
 377 static inline bool update_planes_and_stream_adapter(struct dc *dc,
 378                                                     int update_type,
 379                                                     int planes_count,
 380                                                     struct dc_stream_state *stream,
 381                                                     struct dc_stream_update *stream_update,
 382                                                     struct dc_surface_update *array_of_surface_update)
 383 {
 384         reverse_planes_order(array_of_surface_update, planes_count);
 385
 386         /*
 387          * Previous frame finished and HW is ready for optimization.
 388          */
 389         if (update_type == UPDATE_TYPE_FAST)
 390                 dc_post_update_surfaces_to_stream(dc);
 391
 392         return dc_update_planes_and_stream(dc,
 393                                            array_of_surface_update,
 394                                            planes_count,
 395                                            stream,
 396                                            stream_update);
 397 }
 398
 399 /**
 400  * dm_pflip_high_irq() - Handle pageflip interrupt
 401  * @interrupt_params: ignored
 402  *
 403  * Handles the pageflip interrupt by notifying all interested parties
 404  * that the pageflip has been completed.
 405  */
 406 static void dm_pflip_high_irq(void *interrupt_params)
 407 {
 408         struct amdgpu_crtc *amdgpu_crtc;
 409         struct common_irq_params *irq_params = interrupt_params;
 410         struct amdgpu_device *adev = irq_params->adev;
 411         unsigned long flags;
 412         struct drm_pending_vblank_event *e;
 413         u32 vpos, hpos, v_blank_start, v_blank_end;
 414         bool vrr_active;
 415
 416         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 417
 418         /* IRQ could occur when in initial stage */
 419         /* TODO work and BO cleanup */
 420         if (amdgpu_crtc == NULL) {
 421                 DC_LOG_PFLIP("CRTC is null, returning.\n");
 422                 return;
 423         }
 424
 425         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 426
 427         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 428                 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 429                                                  amdgpu_crtc->pflip_status,
 430                                                  AMDGPU_FLIP_SUBMITTED,
 431                                                  amdgpu_crtc->crtc_id,
 432                                                  amdgpu_crtc);
 433                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 434                 return;
 435         }
 436
 437         /* page flip completed. */
 438         e = amdgpu_crtc->event;
 439         amdgpu_crtc->event = NULL;
 440
 441         WARN_ON(!e);
 442
 443         vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
 444
 445         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 446         if (!vrr_active ||
 447             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 448                                       &v_blank_end, &hpos, &vpos) ||
 449             (vpos < v_blank_start)) {
 450                 /* Update to correct count and vblank timestamp if racing with
 451                  * vblank irq. This also updates to the correct vblank timestamp
 452                  * even in VRR mode, as scanout is past the front-porch atm.
 453                  */
 454                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 455
 456                 /* Wake up userspace by sending the pageflip event with proper
 457                  * count and timestamp of vblank of flip completion.
 458                  */
 459                 if (e) {
 460                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 461
 462                         /* Event sent, so done with vblank for this flip */
 463                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 464                 }
 465         } else if (e) {
 466                 /* VRR active and inside front-porch: vblank count and
 467                  * timestamp for pageflip event will only be up to date after
 468                  * drm_crtc_handle_vblank() has been executed from late vblank
 469                  * irq handler after start of back-porch (vline 0). We queue the
 470                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 471                  * updated timestamp and count, once it runs after us.
 472                  *
 473                  * We need to open-code this instead of using the helper
 474                  * drm_crtc_arm_vblank_event(), as that helper would
 475                  * call drm_crtc_accurate_vblank_count(), which we must
 476                  * not call in VRR mode while we are in front-porch!
 477                  */
 478
 479                 /* sequence will be replaced by real count during send-out. */
 480                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 481                 e->pipe = amdgpu_crtc->crtc_id;
 482
 483                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 484                 e = NULL;
 485         }
 486
 487         /* Keep track of vblank of this flip for flip throttling. We use the
 488          * cooked hw counter, as that one incremented at start of this vblank
 489          * of pageflip completion, so last_flip_vblank is the forbidden count
 490          * for queueing new pageflips if vsync + VRR is enabled.
 491          */
 492         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 493                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 494
 495         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 496         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 497
 498         DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 499                      amdgpu_crtc->crtc_id, amdgpu_crtc,
 500                      vrr_active, (int) !e);
 501 }
 502
 503 static void dm_vupdate_high_irq(void *interrupt_params)
 504 {
 505         struct common_irq_params *irq_params = interrupt_params;
 506         struct amdgpu_device *adev = irq_params->adev;
 507         struct amdgpu_crtc *acrtc;
 508         struct drm_device *drm_dev;
 509         struct drm_vblank_crtc *vblank;
 510         ktime_t frame_duration_ns, previous_timestamp;
 511         unsigned long flags;
 512         int vrr_active;
 513
 514         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 515
 516         if (acrtc) {
 517                 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 518                 drm_dev = acrtc->base.dev;
 519                 vblank = &drm_dev->vblank[acrtc->base.index];
 520                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 521                 frame_duration_ns = vblank->time - previous_timestamp;
 522
 523                 if (frame_duration_ns > 0) {
 524                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 525                                                 frame_duration_ns,
 526                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 527                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 528                 }
 529
 530                 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
 531                               acrtc->crtc_id,
 532                               vrr_active);
 533
 534                 /* Core vblank handling is done here after end of front-porch in
 535                  * vrr mode, as vblank timestamping will give valid results
 536                  * while now done after front-porch. This will also deliver
 537                  * page-flip completion events that have been queued to us
 538                  * if a pageflip happened inside front-porch.
 539                  */
 540                 if (vrr_active) {
 541                         amdgpu_dm_crtc_handle_vblank(acrtc);
 542
 543                         /* BTR processing for pre-DCE12 ASICs */
 544                         if (acrtc->dm_irq_params.stream &&
 545                             adev->family < AMDGPU_FAMILY_AI) {
 546                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 547                                 mod_freesync_handle_v_update(
 548                                     adev->dm.freesync_module,
 549                                     acrtc->dm_irq_params.stream,
 550                                     &acrtc->dm_irq_params.vrr_params);
 551
 552                                 dc_stream_adjust_vmin_vmax(
 553                                     adev->dm.dc,
 554                                     acrtc->dm_irq_params.stream,
 555                                     &acrtc->dm_irq_params.vrr_params.adjust);
 556                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 557                         }
 558                 }
 559         }
 560 }
 561
 562 /**
 563  * dm_crtc_high_irq() - Handles CRTC interrupt
 564  * @interrupt_params: used for determining the CRTC instance
 565  *
 566  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 567  * event handler.
 568  */
 569 static void dm_crtc_high_irq(void *interrupt_params)
 570 {
 571         struct common_irq_params *irq_params = interrupt_params;
 572         struct amdgpu_device *adev = irq_params->adev;
 573         struct amdgpu_crtc *acrtc;
 574         unsigned long flags;
 575         int vrr_active;
 576
 577         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 578         if (!acrtc)
 579                 return;
 580
 581         vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 582
 583         DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 584                       vrr_active, acrtc->dm_irq_params.active_planes);
 585
 586         /**
 587          * Core vblank handling at start of front-porch is only possible
 588          * in non-vrr mode, as only there vblank timestamping will give
 589          * valid results while done in front-porch. Otherwise defer it
 590          * to dm_vupdate_high_irq after end of front-porch.
 591          */
 592         if (!vrr_active)
 593                 amdgpu_dm_crtc_handle_vblank(acrtc);
 594
 595         /**
 596          * Following stuff must happen at start of vblank, for crc
 597          * computation and below-the-range btr support in vrr mode.
 598          */
 599         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 600
 601         /* BTR updates need to happen before VUPDATE on Vega and above. */
 602         if (adev->family < AMDGPU_FAMILY_AI)
 603                 return;
 604
 605         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 606
 607         if (acrtc->dm_irq_params.stream &&
 608             acrtc->dm_irq_params.vrr_params.supported &&
 609             acrtc->dm_irq_params.freesync_config.state ==
 610                     VRR_STATE_ACTIVE_VARIABLE) {
 611                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 612                                              acrtc->dm_irq_params.stream,
 613                                              &acrtc->dm_irq_params.vrr_params);
 614
 615                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 616                                            &acrtc->dm_irq_params.vrr_params.adjust);
 617         }
 618
 619         /*
 620          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 621          * In that case, pageflip completion interrupts won't fire and pageflip
 622          * completion events won't get delivered. Prevent this by sending
 623          * pending pageflip events from here if a flip is still pending.
 624          *
 625          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 626          * avoid race conditions between flip programming and completion,
 627          * which could cause too early flip completion events.
 628          */
 629         if (adev->family >= AMDGPU_FAMILY_RV &&
 630             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 631             acrtc->dm_irq_params.active_planes == 0) {
 632                 if (acrtc->event) {
 633                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 634                         acrtc->event = NULL;
 635                         drm_crtc_vblank_put(&acrtc->base);
 636                 }
 637                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 638         }
 639
 640         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 641 }
 642
 643 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 644 /**
 645  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 646  * DCN generation ASICs
 647  * @interrupt_params: interrupt parameters
 648  *
 649  * Used to set crc window/read out crc value at vertical line 0 position
 650  */
 651 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 652 {
 653         struct common_irq_params *irq_params = interrupt_params;
 654         struct amdgpu_device *adev = irq_params->adev;
 655         struct amdgpu_crtc *acrtc;
 656
 657         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 658
 659         if (!acrtc)
 660                 return;
 661
 662         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 663 }
 664 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 665
 666 /**
 667  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 668  * @adev: amdgpu_device pointer
 669  * @notify: dmub notification structure
 670  *
 671  * Dmub AUX or SET_CONFIG command completion processing callback
 672  * Copies dmub notification to DM which is to be read by AUX command.
 673  * issuing thread and also signals the event to wake up the thread.
 674  */
 675 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 676                                         struct dmub_notification *notify)
 677 {
 678         if (adev->dm.dmub_notify)
 679                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 680         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 681                 complete(&adev->dm.dmub_aux_transfer_done);
 682 }
 683
 684 /**
 685  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 686  * @adev: amdgpu_device pointer
 687  * @notify: dmub notification structure
 688  *
 689  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 690  * ink index and calls helper to do the processing.
 691  */
 692 static void dmub_hpd_callback(struct amdgpu_device *adev,
 693                               struct dmub_notification *notify)
 694 {
 695         struct amdgpu_dm_connector *aconnector;
 696         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 697         struct drm_connector *connector;
 698         struct drm_connector_list_iter iter;
 699         struct dc_link *link;
 700         u8 link_index = 0;
 701         struct drm_device *dev;
 702
 703         if (adev == NULL)
 704                 return;
 705
 706         if (notify == NULL) {
 707                 DRM_ERROR("DMUB HPD callback notification was NULL");
 708                 return;
 709         }
 710
 711         if (notify->link_index > adev->dm.dc->link_count) {
 712                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 713                 return;
 714         }
 715
 716         link_index = notify->link_index;
 717         link = adev->dm.dc->links[link_index];
 718         dev = adev->dm.ddev;
 719
 720         drm_connector_list_iter_begin(dev, &iter);
 721         drm_for_each_connector_iter(connector, &iter) {
 722                 aconnector = to_amdgpu_dm_connector(connector);
 723                 if (link && aconnector->dc_link == link) {
 724                         if (notify->type == DMUB_NOTIFICATION_HPD)
 725                                 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 726                         else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 727                                 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
 728                         else
 729                                 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
 730                                                 notify->type, link_index);
 731
 732                         hpd_aconnector = aconnector;
 733                         break;
 734                 }
 735         }
 736         drm_connector_list_iter_end(&iter);
 737
 738         if (hpd_aconnector) {
 739                 if (notify->type == DMUB_NOTIFICATION_HPD)
 740                         handle_hpd_irq_helper(hpd_aconnector);
 741                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 742                         handle_hpd_rx_irq(hpd_aconnector);
 743         }
 744 }
 745
 746 /**
 747  * register_dmub_notify_callback - Sets callback for DMUB notify
 748  * @adev: amdgpu_device pointer
 749  * @type: Type of dmub notification
 750  * @callback: Dmub interrupt callback function
 751  * @dmub_int_thread_offload: offload indicator
 752  *
 753  * API to register a dmub callback handler for a dmub notification
 754  * Also sets indicator whether callback processing to be offloaded.
 755  * to dmub interrupt handling thread
 756  * Return: true if successfully registered, false if there is existing registration
 757  */
 758 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 759                                           enum dmub_notification_type type,
 760                                           dmub_notify_interrupt_callback_t callback,
 761                                           bool dmub_int_thread_offload)
 762 {
 763         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 764                 adev->dm.dmub_callback[type] = callback;
 765                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 766         } else
 767                 return false;
 768
 769         return true;
 770 }
 771
 772 static void dm_handle_hpd_work(struct work_struct *work)
 773 {
 774         struct dmub_hpd_work *dmub_hpd_wrk;
 775
 776         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 777
 778         if (!dmub_hpd_wrk->dmub_notify) {
 779                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 780                 return;
 781         }
 782
 783         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 784                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 785                 dmub_hpd_wrk->dmub_notify);
 786         }
 787
 788         kfree(dmub_hpd_wrk->dmub_notify);
 789         kfree(dmub_hpd_wrk);
 790
 791 }
 792
 793 #define DMUB_TRACE_MAX_READ 64
 794 /**
 795  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 796  * @interrupt_params: used for determining the Outbox instance
 797  *
 798  * Handles the Outbox Interrupt
 799  * event handler.
 800  */
 801 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 802 {
 803         struct dmub_notification notify;
 804         struct common_irq_params *irq_params = interrupt_params;
 805         struct amdgpu_device *adev = irq_params->adev;
 806         struct amdgpu_display_manager *dm = &adev->dm;
 807         struct dmcub_trace_buf_entry entry = { 0 };
 808         u32 count = 0;
 809         struct dmub_hpd_work *dmub_hpd_wrk;
 810         struct dc_link *plink = NULL;
 811
 812         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 813                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 814
 815                 do {
 816                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 817                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 818                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 819                                 continue;
 820                         }
 821                         if (!dm->dmub_callback[notify.type]) {
 822                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 823                                 continue;
 824                         }
 825                         if (dm->dmub_thread_offload[notify.type] == true) {
 826                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 827                                 if (!dmub_hpd_wrk) {
 828                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 829                                         return;
 830                                 }
 831                                 dmub_hpd_wrk->dmub_notify = kmemdup(&notify, sizeof(struct dmub_notification),
 832                                                                     GFP_ATOMIC);
 833                                 if (!dmub_hpd_wrk->dmub_notify) {
 834                                         kfree(dmub_hpd_wrk);
 835                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 836                                         return;
 837                                 }
 838                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 839                                 dmub_hpd_wrk->adev = adev;
 840                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 841                                         plink = adev->dm.dc->links[notify.link_index];
 842                                         if (plink) {
 843                                                 plink->hpd_status =
 844                                                         notify.hpd_status == DP_HPD_PLUG;
 845                                         }
 846                                 }
 847                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 848                         } else {
 849                                 dm->dmub_callback[notify.type](adev, &notify);
 850                         }
 851                 } while (notify.pending_notification);
 852         }
 853
 854
 855         do {
 856                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 857                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 858                                                         entry.param0, entry.param1);
 859
 860                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 861                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 862                 } else
 863                         break;
 864
 865                 count++;
 866
 867         } while (count <= DMUB_TRACE_MAX_READ);
 868
 869         if (count > DMUB_TRACE_MAX_READ)
 870                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 871 }
 872
 873 static int dm_set_clockgating_state(void *handle,
 874                   enum amd_clockgating_state state)
 875 {
 876         return 0;
 877 }
 878
 879 static int dm_set_powergating_state(void *handle,
 880                   enum amd_powergating_state state)
 881 {
 882         return 0;
 883 }
 884
 885 /* Prototypes of private functions */
 886 static int dm_early_init(void* handle);
 887
 888 /* Allocate memory for FBC compressed data  */
 889 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 890 {
 891         struct drm_device *dev = connector->dev;
 892         struct amdgpu_device *adev = drm_to_adev(dev);
 893         struct dm_compressor_info *compressor = &adev->dm.compressor;
 894         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 895         struct drm_display_mode *mode;
 896         unsigned long max_size = 0;
 897
 898         if (adev->dm.dc->fbc_compressor == NULL)
 899                 return;
 900
 901         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 902                 return;
 903
 904         if (compressor->bo_ptr)
 905                 return;
 906
 907
 908         list_for_each_entry(mode, &connector->modes, head) {
 909                 if (max_size < mode->htotal * mode->vtotal)
 910                         max_size = mode->htotal * mode->vtotal;
 911         }
 912
 913         if (max_size) {
 914                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 915                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 916                             &compressor->gpu_addr, &compressor->cpu_addr);
 917
 918                 if (r)
 919                         DRM_ERROR("DM: Failed to initialize FBC\n");
 920                 else {
 921                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 922                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 923                 }
 924
 925         }
 926
 927 }
 928
 929 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 930                                           int pipe, bool *enabled,
 931                                           unsigned char *buf, int max_bytes)
 932 {
 933         struct drm_device *dev = dev_get_drvdata(kdev);
 934         struct amdgpu_device *adev = drm_to_adev(dev);
 935         struct drm_connector *connector;
 936         struct drm_connector_list_iter conn_iter;
 937         struct amdgpu_dm_connector *aconnector;
 938         int ret = 0;
 939
 940         *enabled = false;
 941
 942         mutex_lock(&adev->dm.audio_lock);
 943
 944         drm_connector_list_iter_begin(dev, &conn_iter);
 945         drm_for_each_connector_iter(connector, &conn_iter) {
 946                 aconnector = to_amdgpu_dm_connector(connector);
 947                 if (aconnector->audio_inst != port)
 948                         continue;
 949
 950                 *enabled = true;
 951                 ret = drm_eld_size(connector->eld);
 952                 memcpy(buf, connector->eld, min(max_bytes, ret));
 953
 954                 break;
 955         }
 956         drm_connector_list_iter_end(&conn_iter);
 957
 958         mutex_unlock(&adev->dm.audio_lock);
 959
 960         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 961
 962         return ret;
 963 }
 964
 965 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 966         .get_eld = amdgpu_dm_audio_component_get_eld,
 967 };
 968
 969 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 970                                        struct device *hda_kdev, void *data)
 971 {
 972         struct drm_device *dev = dev_get_drvdata(kdev);
 973         struct amdgpu_device *adev = drm_to_adev(dev);
 974         struct drm_audio_component *acomp = data;
 975
 976         acomp->ops = &amdgpu_dm_audio_component_ops;
 977         acomp->dev = kdev;
 978         adev->dm.audio_component = acomp;
 979
 980         return 0;
 981 }
 982
 983 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 984                                           struct device *hda_kdev, void *data)
 985 {
 986         struct drm_device *dev = dev_get_drvdata(kdev);
 987         struct amdgpu_device *adev = drm_to_adev(dev);
 988         struct drm_audio_component *acomp = data;
 989
 990         acomp->ops = NULL;
 991         acomp->dev = NULL;
 992         adev->dm.audio_component = NULL;
 993 }
 994
 995 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 996         .bind   = amdgpu_dm_audio_component_bind,
 997         .unbind = amdgpu_dm_audio_component_unbind,
 998 };
 999
1000 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1001 {
1002         int i, ret;
1003
1004         if (!amdgpu_audio)
1005                 return 0;
1006
1007         adev->mode_info.audio.enabled = true;
1008
1009         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1010
1011         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1012                 adev->mode_info.audio.pin[i].channels = -1;
1013                 adev->mode_info.audio.pin[i].rate = -1;
1014                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1015                 adev->mode_info.audio.pin[i].status_bits = 0;
1016                 adev->mode_info.audio.pin[i].category_code = 0;
1017                 adev->mode_info.audio.pin[i].connected = false;
1018                 adev->mode_info.audio.pin[i].id =
1019                         adev->dm.dc->res_pool->audios[i]->inst;
1020                 adev->mode_info.audio.pin[i].offset = 0;
1021         }
1022
1023         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1024         if (ret < 0)
1025                 return ret;
1026
1027         adev->dm.audio_registered = true;
1028
1029         return 0;
1030 }
1031
1032 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1033 {
1034         if (!amdgpu_audio)
1035                 return;
1036
1037         if (!adev->mode_info.audio.enabled)
1038                 return;
1039
1040         if (adev->dm.audio_registered) {
1041                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1042                 adev->dm.audio_registered = false;
1043         }
1044
1045         /* TODO: Disable audio? */
1046
1047         adev->mode_info.audio.enabled = false;
1048 }
1049
1050 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1051 {
1052         struct drm_audio_component *acomp = adev->dm.audio_component;
1053
1054         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1055                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1056
1057                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1058                                                  pin, -1);
1059         }
1060 }
1061
1062 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1063 {
1064         const struct dmcub_firmware_header_v1_0 *hdr;
1065         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1066         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1067         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1068         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1069         struct abm *abm = adev->dm.dc->res_pool->abm;
1070         struct dmub_srv_hw_params hw_params;
1071         enum dmub_status status;
1072         const unsigned char *fw_inst_const, *fw_bss_data;
1073         u32 i, fw_inst_const_size, fw_bss_data_size;
1074         bool has_hw_support;
1075
1076         if (!dmub_srv)
1077                 /* DMUB isn't supported on the ASIC. */
1078                 return 0;
1079
1080         if (!fb_info) {
1081                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1082                 return -EINVAL;
1083         }
1084
1085         if (!dmub_fw) {
1086                 /* Firmware required for DMUB support. */
1087                 DRM_ERROR("No firmware provided for DMUB.\n");
1088                 return -EINVAL;
1089         }
1090
1091         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1092         if (status != DMUB_STATUS_OK) {
1093                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1094                 return -EINVAL;
1095         }
1096
1097         if (!has_hw_support) {
1098                 DRM_INFO("DMUB unsupported on ASIC\n");
1099                 return 0;
1100         }
1101
1102         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1103         status = dmub_srv_hw_reset(dmub_srv);
1104         if (status != DMUB_STATUS_OK)
1105                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1106
1107         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1108
1109         fw_inst_const = dmub_fw->data +
1110                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1111                         PSP_HEADER_BYTES;
1112
1113         fw_bss_data = dmub_fw->data +
1114                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1115                       le32_to_cpu(hdr->inst_const_bytes);
1116
1117         /* Copy firmware and bios info into FB memory. */
1118         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1119                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1120
1121         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1122
1123         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1124          * amdgpu_ucode_init_single_fw will load dmub firmware
1125          * fw_inst_const part to cw0; otherwise, the firmware back door load
1126          * will be done by dm_dmub_hw_init
1127          */
1128         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1129                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1130                                 fw_inst_const_size);
1131         }
1132
1133         if (fw_bss_data_size)
1134                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1135                        fw_bss_data, fw_bss_data_size);
1136
1137         /* Copy firmware bios info into FB memory. */
1138         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1139                adev->bios_size);
1140
1141         /* Reset regions that need to be reset. */
1142         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1143         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1144
1145         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1146                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1147
1148         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1149                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1150
1151         /* Initialize hardware. */
1152         memset(&hw_params, 0, sizeof(hw_params));
1153         hw_params.fb_base = adev->gmc.fb_start;
1154         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1155
1156         /* backdoor load firmware and trigger dmub running */
1157         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1158                 hw_params.load_inst_const = true;
1159
1160         if (dmcu)
1161                 hw_params.psp_version = dmcu->psp_version;
1162
1163         for (i = 0; i < fb_info->num_fb; ++i)
1164                 hw_params.fb[i] = &fb_info->fb[i];
1165
1166         switch (adev->ip_versions[DCE_HWIP][0]) {
1167         case IP_VERSION(3, 1, 3):
1168         case IP_VERSION(3, 1, 4):
1169                 hw_params.dpia_supported = true;
1170                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1171                 break;
1172         default:
1173                 break;
1174         }
1175
1176         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1177         if (status != DMUB_STATUS_OK) {
1178                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1179                 return -EINVAL;
1180         }
1181
1182         /* Wait for firmware load to finish. */
1183         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1184         if (status != DMUB_STATUS_OK)
1185                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1186
1187         /* Init DMCU and ABM if available. */
1188         if (dmcu && abm) {
1189                 dmcu->funcs->dmcu_init(dmcu);
1190                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1191         }
1192
1193         if (!adev->dm.dc->ctx->dmub_srv)
1194                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1195         if (!adev->dm.dc->ctx->dmub_srv) {
1196                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1197                 return -ENOMEM;
1198         }
1199
1200         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1201                  adev->dm.dmcub_fw_version);
1202
1203         return 0;
1204 }
1205
1206 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1207 {
1208         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1209         enum dmub_status status;
1210         bool init;
1211
1212         if (!dmub_srv) {
1213                 /* DMUB isn't supported on the ASIC. */
1214                 return;
1215         }
1216
1217         status = dmub_srv_is_hw_init(dmub_srv, &init);
1218         if (status != DMUB_STATUS_OK)
1219                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1220
1221         if (status == DMUB_STATUS_OK && init) {
1222                 /* Wait for firmware load to finish. */
1223                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1224                 if (status != DMUB_STATUS_OK)
1225                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1226         } else {
1227                 /* Perform the full hardware initialization. */
1228                 dm_dmub_hw_init(adev);
1229         }
1230 }
1231
1232 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1233 {
1234         u64 pt_base;
1235         u32 logical_addr_low;
1236         u32 logical_addr_high;
1237         u32 agp_base, agp_bot, agp_top;
1238         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1239
1240         memset(pa_config, 0, sizeof(*pa_config));
1241
1242         agp_base = 0;
1243         agp_bot = adev->gmc.agp_start >> 24;
1244         agp_top = adev->gmc.agp_end >> 24;
1245
1246         /* AGP aperture is disabled */
1247         if (agp_bot == agp_top) {
1248                 logical_addr_low = adev->gmc.fb_start >> 18;
1249                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1250                         /*
1251                          * Raven2 has a HW issue that it is unable to use the vram which
1252                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1253                          * workaround that increase system aperture high address (add 1)
1254                          * to get rid of the VM fault and hardware hang.
1255                          */
1256                         logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1257                 else
1258                         logical_addr_high = adev->gmc.fb_end >> 18;
1259         } else {
1260                 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1261                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1262                         /*
1263                          * Raven2 has a HW issue that it is unable to use the vram which
1264                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1265                          * workaround that increase system aperture high address (add 1)
1266                          * to get rid of the VM fault and hardware hang.
1267                          */
1268                         logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1269                 else
1270                         logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1271         }
1272
1273         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1274
1275         page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1276         page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1277         page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1278         page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1279         page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1280         page_table_base.low_part = lower_32_bits(pt_base);
1281
1282         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1283         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1284
1285         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1286         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1287         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1288
1289         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1290         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1291         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1292
1293         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1294         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1295         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1296
1297         pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1298
1299 }
1300
1301 static void force_connector_state(
1302         struct amdgpu_dm_connector *aconnector,
1303         enum drm_connector_force force_state)
1304 {
1305         struct drm_connector *connector = &aconnector->base;
1306
1307         mutex_lock(&connector->dev->mode_config.mutex);
1308         aconnector->base.force = force_state;
1309         mutex_unlock(&connector->dev->mode_config.mutex);
1310
1311         mutex_lock(&aconnector->hpd_lock);
1312         drm_kms_helper_connector_hotplug_event(connector);
1313         mutex_unlock(&aconnector->hpd_lock);
1314 }
1315
1316 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1317 {
1318         struct hpd_rx_irq_offload_work *offload_work;
1319         struct amdgpu_dm_connector *aconnector;
1320         struct dc_link *dc_link;
1321         struct amdgpu_device *adev;
1322         enum dc_connection_type new_connection_type = dc_connection_none;
1323         unsigned long flags;
1324         union test_response test_response;
1325
1326         memset(&test_response, 0, sizeof(test_response));
1327
1328         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1329         aconnector = offload_work->offload_wq->aconnector;
1330
1331         if (!aconnector) {
1332                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1333                 goto skip;
1334         }
1335
1336         adev = drm_to_adev(aconnector->base.dev);
1337         dc_link = aconnector->dc_link;
1338
1339         mutex_lock(&aconnector->hpd_lock);
1340         if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1341                 DRM_ERROR("KMS: Failed to detect connector\n");
1342         mutex_unlock(&aconnector->hpd_lock);
1343
1344         if (new_connection_type == dc_connection_none)
1345                 goto skip;
1346
1347         if (amdgpu_in_reset(adev))
1348                 goto skip;
1349
1350         mutex_lock(&adev->dm.dc_lock);
1351         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1352                 dc_link_dp_handle_automated_test(dc_link);
1353
1354                 if (aconnector->timing_changed) {
1355                         /* force connector disconnect and reconnect */
1356                         force_connector_state(aconnector, DRM_FORCE_OFF);
1357                         msleep(100);
1358                         force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1359                 }
1360
1361                 test_response.bits.ACK = 1;
1362
1363                 core_link_write_dpcd(
1364                 dc_link,
1365                 DP_TEST_RESPONSE,
1366                 &test_response.raw,
1367                 sizeof(test_response));
1368         }
1369         else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1370                         dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1371                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1372                 /* offload_work->data is from handle_hpd_rx_irq->
1373                  * schedule_hpd_rx_offload_work.this is defer handle
1374                  * for hpd short pulse. upon here, link status may be
1375                  * changed, need get latest link status from dpcd
1376                  * registers. if link status is good, skip run link
1377                  * training again.
1378                  */
1379                 union hpd_irq_data irq_data;
1380
1381                 memset(&irq_data, 0, sizeof(irq_data));
1382
1383                 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1384                  * request be added to work queue if link lost at end of dc_link_
1385                  * dp_handle_link_loss
1386                  */
1387                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1388                 offload_work->offload_wq->is_handling_link_loss = false;
1389                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1390
1391                 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1392                         dc_link_check_link_loss_status(dc_link, &irq_data))
1393                         dc_link_dp_handle_link_loss(dc_link);
1394         }
1395         mutex_unlock(&adev->dm.dc_lock);
1396
1397 skip:
1398         kfree(offload_work);
1399
1400 }
1401
1402 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1403 {
1404         int max_caps = dc->caps.max_links;
1405         int i = 0;
1406         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1407
1408         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1409
1410         if (!hpd_rx_offload_wq)
1411                 return NULL;
1412
1413
1414         for (i = 0; i < max_caps; i++) {
1415                 hpd_rx_offload_wq[i].wq =
1416                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1417
1418                 if (hpd_rx_offload_wq[i].wq == NULL) {
1419                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1420                         goto out_err;
1421                 }
1422
1423                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1424         }
1425
1426         return hpd_rx_offload_wq;
1427
1428 out_err:
1429         for (i = 0; i < max_caps; i++) {
1430                 if (hpd_rx_offload_wq[i].wq)
1431                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1432         }
1433         kfree(hpd_rx_offload_wq);
1434         return NULL;
1435 }
1436
1437 struct amdgpu_stutter_quirk {
1438         u16 chip_vendor;
1439         u16 chip_device;
1440         u16 subsys_vendor;
1441         u16 subsys_device;
1442         u8 revision;
1443 };
1444
1445 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1446         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1447         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1448         { 0, 0, 0, 0, 0 },
1449 };
1450
1451 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1452 {
1453         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1454
1455         while (p && p->chip_device != 0) {
1456                 if (pdev->vendor == p->chip_vendor &&
1457                     pdev->device == p->chip_device &&
1458                     pdev->subsystem_vendor == p->subsys_vendor &&
1459                     pdev->subsystem_device == p->subsys_device &&
1460                     pdev->revision == p->revision) {
1461                         return true;
1462                 }
1463                 ++p;
1464         }
1465         return false;
1466 }
1467
1468 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1469         {
1470                 .matches = {
1471                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1472                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1473                 },
1474         },
1475         {
1476                 .matches = {
1477                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1478                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1479                 },
1480         },
1481         {
1482                 .matches = {
1483                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1484                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1485                 },
1486         },
1487         {
1488                 .matches = {
1489                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1490                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1491                 },
1492         },
1493         {
1494                 .matches = {
1495                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1496                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1497                 },
1498         },
1499         {
1500                 .matches = {
1501                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1502                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1503                 },
1504         },
1505         {
1506                 .matches = {
1507                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1508                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1509                 },
1510         },
1511         {
1512                 .matches = {
1513                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1514                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1515                 },
1516         },
1517         {
1518                 .matches = {
1519                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1520                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1521                 },
1522         },
1523         {}
1524         /* TODO: refactor this from a fixed table to a dynamic option */
1525 };
1526
1527 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1528 {
1529         const struct dmi_system_id *dmi_id;
1530
1531         dm->aux_hpd_discon_quirk = false;
1532
1533         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1534         if (dmi_id) {
1535                 dm->aux_hpd_discon_quirk = true;
1536                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1537         }
1538 }
1539
1540 static int amdgpu_dm_init(struct amdgpu_device *adev)
1541 {
1542         struct dc_init_data init_data;
1543         struct dc_callback_init init_params;
1544         int r;
1545
1546         adev->dm.ddev = adev_to_drm(adev);
1547         adev->dm.adev = adev;
1548
1549         /* Zero all the fields */
1550         memset(&init_data, 0, sizeof(init_data));
1551         memset(&init_params, 0, sizeof(init_params));
1552
1553         mutex_init(&adev->dm.dpia_aux_lock);
1554         mutex_init(&adev->dm.dc_lock);
1555         mutex_init(&adev->dm.audio_lock);
1556
1557         if(amdgpu_dm_irq_init(adev)) {
1558                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1559                 goto error;
1560         }
1561
1562         init_data.asic_id.chip_family = adev->family;
1563
1564         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1565         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1566         init_data.asic_id.chip_id = adev->pdev->device;
1567
1568         init_data.asic_id.vram_width = adev->gmc.vram_width;
1569         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1570         init_data.asic_id.atombios_base_address =
1571                 adev->mode_info.atom_context->bios;
1572
1573         init_data.driver = adev;
1574
1575         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1576
1577         if (!adev->dm.cgs_device) {
1578                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1579                 goto error;
1580         }
1581
1582         init_data.cgs_device = adev->dm.cgs_device;
1583
1584         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1585
1586         switch (adev->ip_versions[DCE_HWIP][0]) {
1587         case IP_VERSION(2, 1, 0):
1588                 switch (adev->dm.dmcub_fw_version) {
1589                 case 0: /* development */
1590                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1591                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1592                         init_data.flags.disable_dmcu = false;
1593                         break;
1594                 default:
1595                         init_data.flags.disable_dmcu = true;
1596                 }
1597                 break;
1598         case IP_VERSION(2, 0, 3):
1599                 init_data.flags.disable_dmcu = true;
1600                 break;
1601         default:
1602                 break;
1603         }
1604
1605         switch (adev->asic_type) {
1606         case CHIP_CARRIZO:
1607         case CHIP_STONEY:
1608                 init_data.flags.gpu_vm_support = true;
1609                 break;
1610         default:
1611                 switch (adev->ip_versions[DCE_HWIP][0]) {
1612                 case IP_VERSION(1, 0, 0):
1613                 case IP_VERSION(1, 0, 1):
1614                         /* enable S/G on PCO and RV2 */
1615                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1616                             (adev->apu_flags & AMD_APU_IS_PICASSO))
1617                                 init_data.flags.gpu_vm_support = true;
1618                         break;
1619                 case IP_VERSION(2, 1, 0):
1620                 case IP_VERSION(3, 0, 1):
1621                 case IP_VERSION(3, 1, 2):
1622                 case IP_VERSION(3, 1, 3):
1623                 case IP_VERSION(3, 1, 4):
1624                 case IP_VERSION(3, 1, 5):
1625                 case IP_VERSION(3, 1, 6):
1626                         init_data.flags.gpu_vm_support = true;
1627                         break;
1628                 default:
1629                         break;
1630                 }
1631                 break;
1632         }
1633         if (init_data.flags.gpu_vm_support &&
1634             (amdgpu_sg_display == 0))
1635                 init_data.flags.gpu_vm_support = false;
1636
1637         if (init_data.flags.gpu_vm_support)
1638                 adev->mode_info.gpu_vm_support = true;
1639
1640         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1641                 init_data.flags.fbc_support = true;
1642
1643         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1644                 init_data.flags.multi_mon_pp_mclk_switch = true;
1645
1646         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1647                 init_data.flags.disable_fractional_pwm = true;
1648
1649         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1650                 init_data.flags.edp_no_power_sequencing = true;
1651
1652         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1653                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1654         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1655                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1656
1657         init_data.flags.seamless_boot_edp_requested = false;
1658
1659         if (check_seamless_boot_capability(adev)) {
1660                 init_data.flags.seamless_boot_edp_requested = true;
1661                 init_data.flags.allow_seamless_boot_optimization = true;
1662                 DRM_INFO("Seamless boot condition check passed\n");
1663         }
1664
1665         init_data.flags.enable_mipi_converter_optimization = true;
1666
1667         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1668         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1669
1670         INIT_LIST_HEAD(&adev->dm.da_list);
1671
1672         retrieve_dmi_info(&adev->dm);
1673
1674         /* Display Core create. */
1675         adev->dm.dc = dc_create(&init_data);
1676
1677         if (adev->dm.dc) {
1678                 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,
1679                          dce_version_to_string(adev->dm.dc->ctx->dce_version));
1680         } else {
1681                 DRM_INFO("Display Core v%s failed to initialize on %s\n", DC_VER,
1682                          dce_version_to_string(adev->dm.dc->ctx->dce_version));
1683                 goto error;
1684         }
1685
1686         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1687                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1688                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1689         }
1690
1691         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1692                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1693         if (dm_should_disable_stutter(adev->pdev))
1694                 adev->dm.dc->debug.disable_stutter = true;
1695
1696         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1697                 adev->dm.dc->debug.disable_stutter = true;
1698
1699         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1700                 adev->dm.dc->debug.disable_dsc = true;
1701         }
1702
1703         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1704                 adev->dm.dc->debug.disable_clock_gate = true;
1705
1706         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1707                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1708
1709         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1710
1711         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1712         adev->dm.dc->debug.ignore_cable_id = true;
1713
1714         /* TODO: There is a new drm mst change where the freedom of
1715          * vc_next_start_slot update is revoked/moved into drm, instead of in
1716          * driver. This forces us to make sure to get vc_next_start_slot updated
1717          * in drm function each time without considering if mst_state is active
1718          * or not. Otherwise, next time hotplug will give wrong start_slot
1719          * number. We are implementing a temporary solution to even notify drm
1720          * mst deallocation when link is no longer of MST type when uncommitting
1721          * the stream so we will have more time to work on a proper solution.
1722          * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1723          * should notify drm to do a complete "reset" of its states and stop
1724          * calling further drm mst functions when link is no longer of an MST
1725          * type. This could happen when we unplug an MST hubs/displays. When
1726          * uncommit stream comes later after unplug, we should just reset
1727          * hardware states only.
1728          */
1729         adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1730
1731         if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1732                 DRM_INFO("DP-HDMI FRL PCON supported\n");
1733
1734         r = dm_dmub_hw_init(adev);
1735         if (r) {
1736                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1737                 goto error;
1738         }
1739
1740         dc_hardware_init(adev->dm.dc);
1741
1742         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1743         if (!adev->dm.hpd_rx_offload_wq) {
1744                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1745                 goto error;
1746         }
1747
1748         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1749                 struct dc_phy_addr_space_config pa_config;
1750
1751                 mmhub_read_system_context(adev, &pa_config);
1752
1753                 // Call the DC init_memory func
1754                 dc_setup_system_context(adev->dm.dc, &pa_config);
1755         }
1756
1757         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1758         if (!adev->dm.freesync_module) {
1759                 DRM_ERROR(
1760                 "amdgpu: failed to initialize freesync_module.\n");
1761         } else
1762                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1763                                 adev->dm.freesync_module);
1764
1765         amdgpu_dm_init_color_mod();
1766
1767         if (adev->dm.dc->caps.max_links > 0) {
1768                 adev->dm.vblank_control_workqueue =
1769                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1770                 if (!adev->dm.vblank_control_workqueue)
1771                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1772         }
1773
1774         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1775                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1776
1777                 if (!adev->dm.hdcp_workqueue)
1778                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1779                 else
1780                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1781
1782                 dc_init_callbacks(adev->dm.dc, &init_params);
1783         }
1784         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1785                 init_completion(&adev->dm.dmub_aux_transfer_done);
1786                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1787                 if (!adev->dm.dmub_notify) {
1788                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1789                         goto error;
1790                 }
1791
1792                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1793                 if (!adev->dm.delayed_hpd_wq) {
1794                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1795                         goto error;
1796                 }
1797
1798                 amdgpu_dm_outbox_init(adev);
1799                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1800                         dmub_aux_setconfig_callback, false)) {
1801                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1802                         goto error;
1803                 }
1804                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1805                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1806                         goto error;
1807                 }
1808                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1809                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1810                         goto error;
1811                 }
1812         }
1813
1814         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1815          * It is expected that DMUB will resend any pending notifications at this point, for
1816          * example HPD from DPIA.
1817          */
1818         if (dc_is_dmub_outbox_supported(adev->dm.dc))
1819                 dc_enable_dmub_outbox(adev->dm.dc);
1820
1821         if (amdgpu_dm_initialize_drm_device(adev)) {
1822                 DRM_ERROR(
1823                 "amdgpu: failed to initialize sw for display support.\n");
1824                 goto error;
1825         }
1826
1827         /* create fake encoders for MST */
1828         dm_dp_create_fake_mst_encoders(adev);
1829
1830         /* TODO: Add_display_info? */
1831
1832         /* TODO use dynamic cursor width */
1833         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1834         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1835
1836         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1837                 DRM_ERROR(
1838                 "amdgpu: failed to initialize sw for display support.\n");
1839                 goto error;
1840         }
1841
1842 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1843         adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1844         if (!adev->dm.secure_display_ctxs)
1845                 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");
1846 #endif
1847
1848         DRM_DEBUG_DRIVER("KMS initialized.\n");
1849
1850         return 0;
1851 error:
1852         amdgpu_dm_fini(adev);
1853
1854         return -EINVAL;
1855 }
1856
1857 static int amdgpu_dm_early_fini(void *handle)
1858 {
1859         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1860
1861         amdgpu_dm_audio_fini(adev);
1862
1863         return 0;
1864 }
1865
1866 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1867 {
1868         int i;
1869
1870         if (adev->dm.vblank_control_workqueue) {
1871                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1872                 adev->dm.vblank_control_workqueue = NULL;
1873         }
1874
1875         amdgpu_dm_destroy_drm_device(&adev->dm);
1876
1877 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1878         if (adev->dm.secure_display_ctxs) {
1879                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1880                         if (adev->dm.secure_display_ctxs[i].crtc) {
1881                                 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1882                                 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1883                         }
1884                 }
1885                 kfree(adev->dm.secure_display_ctxs);
1886                 adev->dm.secure_display_ctxs = NULL;
1887         }
1888 #endif
1889         if (adev->dm.hdcp_workqueue) {
1890                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1891                 adev->dm.hdcp_workqueue = NULL;
1892         }
1893
1894         if (adev->dm.dc)
1895                 dc_deinit_callbacks(adev->dm.dc);
1896
1897         if (adev->dm.dc)
1898                 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1899
1900         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1901                 kfree(adev->dm.dmub_notify);
1902                 adev->dm.dmub_notify = NULL;
1903                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1904                 adev->dm.delayed_hpd_wq = NULL;
1905         }
1906
1907         if (adev->dm.dmub_bo)
1908                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1909                                       &adev->dm.dmub_bo_gpu_addr,
1910                                       &adev->dm.dmub_bo_cpu_addr);
1911
1912         if (adev->dm.hpd_rx_offload_wq) {
1913                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1914                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1915                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1916                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1917                         }
1918                 }
1919
1920                 kfree(adev->dm.hpd_rx_offload_wq);
1921                 adev->dm.hpd_rx_offload_wq = NULL;
1922         }
1923
1924         /* DC Destroy TODO: Replace destroy DAL */
1925         if (adev->dm.dc)
1926                 dc_destroy(&adev->dm.dc);
1927         /*
1928          * TODO: pageflip, vlank interrupt
1929          *
1930          * amdgpu_dm_irq_fini(adev);
1931          */
1932
1933         if (adev->dm.cgs_device) {
1934                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1935                 adev->dm.cgs_device = NULL;
1936         }
1937         if (adev->dm.freesync_module) {
1938                 mod_freesync_destroy(adev->dm.freesync_module);
1939                 adev->dm.freesync_module = NULL;
1940         }
1941
1942         mutex_destroy(&adev->dm.audio_lock);
1943         mutex_destroy(&adev->dm.dc_lock);
1944         mutex_destroy(&adev->dm.dpia_aux_lock);
1945
1946         return;
1947 }
1948
1949 static int load_dmcu_fw(struct amdgpu_device *adev)
1950 {
1951         const char *fw_name_dmcu = NULL;
1952         int r;
1953         const struct dmcu_firmware_header_v1_0 *hdr;
1954
1955         switch(adev->asic_type) {
1956 #if defined(CONFIG_DRM_AMD_DC_SI)
1957         case CHIP_TAHITI:
1958         case CHIP_PITCAIRN:
1959         case CHIP_VERDE:
1960         case CHIP_OLAND:
1961 #endif
1962         case CHIP_BONAIRE:
1963         case CHIP_HAWAII:
1964         case CHIP_KAVERI:
1965         case CHIP_KABINI:
1966         case CHIP_MULLINS:
1967         case CHIP_TONGA:
1968         case CHIP_FIJI:
1969         case CHIP_CARRIZO:
1970         case CHIP_STONEY:
1971         case CHIP_POLARIS11:
1972         case CHIP_POLARIS10:
1973         case CHIP_POLARIS12:
1974         case CHIP_VEGAM:
1975         case CHIP_VEGA10:
1976         case CHIP_VEGA12:
1977         case CHIP_VEGA20:
1978                 return 0;
1979         case CHIP_NAVI12:
1980                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1981                 break;
1982         case CHIP_RAVEN:
1983                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1984                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1985                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1986                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1987                 else
1988                         return 0;
1989                 break;
1990         default:
1991                 switch (adev->ip_versions[DCE_HWIP][0]) {
1992                 case IP_VERSION(2, 0, 2):
1993                 case IP_VERSION(2, 0, 3):
1994                 case IP_VERSION(2, 0, 0):
1995                 case IP_VERSION(2, 1, 0):
1996                 case IP_VERSION(3, 0, 0):
1997                 case IP_VERSION(3, 0, 2):
1998                 case IP_VERSION(3, 0, 3):
1999                 case IP_VERSION(3, 0, 1):
2000                 case IP_VERSION(3, 1, 2):
2001                 case IP_VERSION(3, 1, 3):
2002                 case IP_VERSION(3, 1, 4):
2003                 case IP_VERSION(3, 1, 5):
2004                 case IP_VERSION(3, 1, 6):
2005                 case IP_VERSION(3, 2, 0):
2006                 case IP_VERSION(3, 2, 1):
2007                         return 0;
2008                 default:
2009                         break;
2010                 }
2011                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2012                 return -EINVAL;
2013         }
2014
2015         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2016                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2017                 return 0;
2018         }
2019
2020         r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2021         if (r == -ENODEV) {
2022                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2023                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2024                 adev->dm.fw_dmcu = NULL;
2025                 return 0;
2026         }
2027         if (r) {
2028                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2029                         fw_name_dmcu);
2030                 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2031                 return r;
2032         }
2033
2034         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2035         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2036         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2037         adev->firmware.fw_size +=
2038                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2039
2040         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2041         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2042         adev->firmware.fw_size +=
2043                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2044
2045         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2046
2047         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2048
2049         return 0;
2050 }
2051
2052 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2053 {
2054         struct amdgpu_device *adev = ctx;
2055
2056         return dm_read_reg(adev->dm.dc->ctx, address);
2057 }
2058
2059 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2060                                      uint32_t value)
2061 {
2062         struct amdgpu_device *adev = ctx;
2063
2064         return dm_write_reg(adev->dm.dc->ctx, address, value);
2065 }
2066
2067 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2068 {
2069         struct dmub_srv_create_params create_params;
2070         struct dmub_srv_region_params region_params;
2071         struct dmub_srv_region_info region_info;
2072         struct dmub_srv_fb_params fb_params;
2073         struct dmub_srv_fb_info *fb_info;
2074         struct dmub_srv *dmub_srv;
2075         const struct dmcub_firmware_header_v1_0 *hdr;
2076         enum dmub_asic dmub_asic;
2077         enum dmub_status status;
2078         int r;
2079
2080         switch (adev->ip_versions[DCE_HWIP][0]) {
2081         case IP_VERSION(2, 1, 0):
2082                 dmub_asic = DMUB_ASIC_DCN21;
2083                 break;
2084         case IP_VERSION(3, 0, 0):
2085                 dmub_asic = DMUB_ASIC_DCN30;
2086                 break;
2087         case IP_VERSION(3, 0, 1):
2088                 dmub_asic = DMUB_ASIC_DCN301;
2089                 break;
2090         case IP_VERSION(3, 0, 2):
2091                 dmub_asic = DMUB_ASIC_DCN302;
2092                 break;
2093         case IP_VERSION(3, 0, 3):
2094                 dmub_asic = DMUB_ASIC_DCN303;
2095                 break;
2096         case IP_VERSION(3, 1, 2):
2097         case IP_VERSION(3, 1, 3):
2098                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2099                 break;
2100         case IP_VERSION(3, 1, 4):
2101                 dmub_asic = DMUB_ASIC_DCN314;
2102                 break;
2103         case IP_VERSION(3, 1, 5):
2104                 dmub_asic = DMUB_ASIC_DCN315;
2105                 break;
2106         case IP_VERSION(3, 1, 6):
2107                 dmub_asic = DMUB_ASIC_DCN316;
2108                 break;
2109         case IP_VERSION(3, 2, 0):
2110                 dmub_asic = DMUB_ASIC_DCN32;
2111                 break;
2112         case IP_VERSION(3, 2, 1):
2113                 dmub_asic = DMUB_ASIC_DCN321;
2114                 break;
2115         default:
2116                 /* ASIC doesn't support DMUB. */
2117                 return 0;
2118         }
2119
2120         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2121         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2122
2123         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2124                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2125                         AMDGPU_UCODE_ID_DMCUB;
2126                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2127                         adev->dm.dmub_fw;
2128                 adev->firmware.fw_size +=
2129                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2130
2131                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2132                          adev->dm.dmcub_fw_version);
2133         }
2134
2135
2136         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2137         dmub_srv = adev->dm.dmub_srv;
2138
2139         if (!dmub_srv) {
2140                 DRM_ERROR("Failed to allocate DMUB service!\n");
2141                 return -ENOMEM;
2142         }
2143
2144         memset(&create_params, 0, sizeof(create_params));
2145         create_params.user_ctx = adev;
2146         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2147         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2148         create_params.asic = dmub_asic;
2149
2150         /* Create the DMUB service. */
2151         status = dmub_srv_create(dmub_srv, &create_params);
2152         if (status != DMUB_STATUS_OK) {
2153                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2154                 return -EINVAL;
2155         }
2156
2157         /* Calculate the size of all the regions for the DMUB service. */
2158         memset(&region_params, 0, sizeof(region_params));
2159
2160         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2161                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2162         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2163         region_params.vbios_size = adev->bios_size;
2164         region_params.fw_bss_data = region_params.bss_data_size ?
2165                 adev->dm.dmub_fw->data +
2166                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2167                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2168         region_params.fw_inst_const =
2169                 adev->dm.dmub_fw->data +
2170                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2171                 PSP_HEADER_BYTES;
2172
2173         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2174                                            &region_info);
2175
2176         if (status != DMUB_STATUS_OK) {
2177                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2178                 return -EINVAL;
2179         }
2180
2181         /*
2182          * Allocate a framebuffer based on the total size of all the regions.
2183          * TODO: Move this into GART.
2184          */
2185         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2186                                     AMDGPU_GEM_DOMAIN_VRAM |
2187                                     AMDGPU_GEM_DOMAIN_GTT,
2188                                     &adev->dm.dmub_bo,
2189                                     &adev->dm.dmub_bo_gpu_addr,
2190                                     &adev->dm.dmub_bo_cpu_addr);
2191         if (r)
2192                 return r;
2193
2194         /* Rebase the regions on the framebuffer address. */
2195         memset(&fb_params, 0, sizeof(fb_params));
2196         fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2197         fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2198         fb_params.region_info = &region_info;
2199
2200         adev->dm.dmub_fb_info =
2201                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2202         fb_info = adev->dm.dmub_fb_info;
2203
2204         if (!fb_info) {
2205                 DRM_ERROR(
2206                         "Failed to allocate framebuffer info for DMUB service!\n");
2207                 return -ENOMEM;
2208         }
2209
2210         status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2211         if (status != DMUB_STATUS_OK) {
2212                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2213                 return -EINVAL;
2214         }
2215
2216         return 0;
2217 }
2218
2219 static int dm_sw_init(void *handle)
2220 {
2221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2222         int r;
2223
2224         r = dm_dmub_sw_init(adev);
2225         if (r)
2226                 return r;
2227
2228         return load_dmcu_fw(adev);
2229 }
2230
2231 static int dm_sw_fini(void *handle)
2232 {
2233         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2234
2235         kfree(adev->dm.dmub_fb_info);
2236         adev->dm.dmub_fb_info = NULL;
2237
2238         if (adev->dm.dmub_srv) {
2239                 dmub_srv_destroy(adev->dm.dmub_srv);
2240                 adev->dm.dmub_srv = NULL;
2241         }
2242
2243         amdgpu_ucode_release(&adev->dm.dmub_fw);
2244         amdgpu_ucode_release(&adev->dm.fw_dmcu);
2245
2246         return 0;
2247 }
2248
2249 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2250 {
2251         struct amdgpu_dm_connector *aconnector;
2252         struct drm_connector *connector;
2253         struct drm_connector_list_iter iter;
2254         int ret = 0;
2255
2256         drm_connector_list_iter_begin(dev, &iter);
2257         drm_for_each_connector_iter(connector, &iter) {
2258                 aconnector = to_amdgpu_dm_connector(connector);
2259                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2260                     aconnector->mst_mgr.aux) {
2261                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2262                                          aconnector,
2263                                          aconnector->base.base.id);
2264
2265                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2266                         if (ret < 0) {
2267                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2268                                 aconnector->dc_link->type =
2269                                         dc_connection_single;
2270                                 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2271                                                                      aconnector->dc_link);
2272                                 break;
2273                         }
2274                 }
2275         }
2276         drm_connector_list_iter_end(&iter);
2277
2278         return ret;
2279 }
2280
2281 static int dm_late_init(void *handle)
2282 {
2283         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2284
2285         struct dmcu_iram_parameters params;
2286         unsigned int linear_lut[16];
2287         int i;
2288         struct dmcu *dmcu = NULL;
2289
2290         dmcu = adev->dm.dc->res_pool->dmcu;
2291
2292         for (i = 0; i < 16; i++)
2293                 linear_lut[i] = 0xFFFF * i / 15;
2294
2295         params.set = 0;
2296         params.backlight_ramping_override = false;
2297         params.backlight_ramping_start = 0xCCCC;
2298         params.backlight_ramping_reduction = 0xCCCCCCCC;
2299         params.backlight_lut_array_size = 16;
2300         params.backlight_lut_array = linear_lut;
2301
2302         /* Min backlight level after ABM reduction,  Don't allow below 1%
2303          * 0xFFFF x 0.01 = 0x28F
2304          */
2305         params.min_abm_backlight = 0x28F;
2306         /* In the case where abm is implemented on dmcub,
2307          * dmcu object will be null.
2308          * ABM 2.4 and up are implemented on dmcub.
2309          */
2310         if (dmcu) {
2311                 if (!dmcu_load_iram(dmcu, params))
2312                         return -EINVAL;
2313         } else if (adev->dm.dc->ctx->dmub_srv) {
2314                 struct dc_link *edp_links[MAX_NUM_EDP];
2315                 int edp_num;
2316
2317                 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2318                 for (i = 0; i < edp_num; i++) {
2319                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2320                                 return -EINVAL;
2321                 }
2322         }
2323
2324         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2325 }
2326
2327 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2328 {
2329         struct amdgpu_dm_connector *aconnector;
2330         struct drm_connector *connector;
2331         struct drm_connector_list_iter iter;
2332         struct drm_dp_mst_topology_mgr *mgr;
2333         int ret;
2334         bool need_hotplug = false;
2335
2336         drm_connector_list_iter_begin(dev, &iter);
2337         drm_for_each_connector_iter(connector, &iter) {
2338                 aconnector = to_amdgpu_dm_connector(connector);
2339                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2340                     aconnector->mst_root)
2341                         continue;
2342
2343                 mgr = &aconnector->mst_mgr;
2344
2345                 if (suspend) {
2346                         drm_dp_mst_topology_mgr_suspend(mgr);
2347                 } else {
2348                         /* if extended timeout is supported in hardware,
2349                          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2350                          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2351                          */
2352                         try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2353                         if (!dp_is_lttpr_present(aconnector->dc_link))
2354                                 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2355
2356                         ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2357                         if (ret < 0) {
2358                                 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2359                                         aconnector->dc_link);
2360                                 need_hotplug = true;
2361                         }
2362                 }
2363         }
2364         drm_connector_list_iter_end(&iter);
2365
2366         if (need_hotplug)
2367                 drm_kms_helper_hotplug_event(dev);
2368 }
2369
2370 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2371 {
2372         int ret = 0;
2373
2374         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2375          * on window driver dc implementation.
2376          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2377          * should be passed to smu during boot up and resume from s3.
2378          * boot up: dc calculate dcn watermark clock settings within dc_create,
2379          * dcn20_resource_construct
2380          * then call pplib functions below to pass the settings to smu:
2381          * smu_set_watermarks_for_clock_ranges
2382          * smu_set_watermarks_table
2383          * navi10_set_watermarks_table
2384          * smu_write_watermarks_table
2385          *
2386          * For Renoir, clock settings of dcn watermark are also fixed values.
2387          * dc has implemented different flow for window driver:
2388          * dc_hardware_init / dc_set_power_state
2389          * dcn10_init_hw
2390          * notify_wm_ranges
2391          * set_wm_ranges
2392          * -- Linux
2393          * smu_set_watermarks_for_clock_ranges
2394          * renoir_set_watermarks_table
2395          * smu_write_watermarks_table
2396          *
2397          * For Linux,
2398          * dc_hardware_init -> amdgpu_dm_init
2399          * dc_set_power_state --> dm_resume
2400          *
2401          * therefore, this function apply to navi10/12/14 but not Renoir
2402          * *
2403          */
2404         switch (adev->ip_versions[DCE_HWIP][0]) {
2405         case IP_VERSION(2, 0, 2):
2406         case IP_VERSION(2, 0, 0):
2407                 break;
2408         default:
2409                 return 0;
2410         }
2411
2412         ret = amdgpu_dpm_write_watermarks_table(adev);
2413         if (ret) {
2414                 DRM_ERROR("Failed to update WMTABLE!\n");
2415                 return ret;
2416         }
2417
2418         return 0;
2419 }
2420
2421 /**
2422  * dm_hw_init() - Initialize DC device
2423  * @handle: The base driver device containing the amdgpu_dm device.
2424  *
2425  * Initialize the &struct amdgpu_display_manager device. This involves calling
2426  * the initializers of each DM component, then populating the struct with them.
2427  *
2428  * Although the function implies hardware initialization, both hardware and
2429  * software are initialized here. Splitting them out to their relevant init
2430  * hooks is a future TODO item.
2431  *
2432  * Some notable things that are initialized here:
2433  *
2434  * - Display Core, both software and hardware
2435  * - DC modules that we need (freesync and color management)
2436  * - DRM software states
2437  * - Interrupt sources and handlers
2438  * - Vblank support
2439  * - Debug FS entries, if enabled
2440  */
2441 static int dm_hw_init(void *handle)
2442 {
2443         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2444         /* Create DAL display manager */
2445         amdgpu_dm_init(adev);
2446         amdgpu_dm_hpd_init(adev);
2447
2448         return 0;
2449 }
2450
2451 /**
2452  * dm_hw_fini() - Teardown DC device
2453  * @handle: The base driver device containing the amdgpu_dm device.
2454  *
2455  * Teardown components within &struct amdgpu_display_manager that require
2456  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2457  * were loaded. Also flush IRQ workqueues and disable them.
2458  */
2459 static int dm_hw_fini(void *handle)
2460 {
2461         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2462
2463         amdgpu_dm_hpd_fini(adev);
2464
2465         amdgpu_dm_irq_fini(adev);
2466         amdgpu_dm_fini(adev);
2467         return 0;
2468 }
2469
2470
2471 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2472                                  struct dc_state *state, bool enable)
2473 {
2474         enum dc_irq_source irq_source;
2475         struct amdgpu_crtc *acrtc;
2476         int rc = -EBUSY;
2477         int i = 0;
2478
2479         for (i = 0; i < state->stream_count; i++) {
2480                 acrtc = get_crtc_by_otg_inst(
2481                                 adev, state->stream_status[i].primary_otg_inst);
2482
2483                 if (acrtc && state->stream_status[i].plane_count != 0) {
2484                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2485                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2486                         if (rc)
2487                                 DRM_WARN("Failed to %s pflip interrupts\n",
2488                                          enable ? "enable" : "disable");
2489
2490                         if (enable) {
2491                                 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
2492                                         rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
2493                         } else
2494                                 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
2495
2496                         if (rc)
2497                                 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
2498
2499                         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2500                         /* During gpu-reset we disable and then enable vblank irq, so
2501                          * don't use amdgpu_irq_get/put() to avoid refcount change.
2502                          */
2503                         if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
2504                                 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
2505                 }
2506         }
2507
2508 }
2509
2510 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2511 {
2512         struct dc_state *context = NULL;
2513         enum dc_status res = DC_ERROR_UNEXPECTED;
2514         int i;
2515         struct dc_stream_state *del_streams[MAX_PIPES];
2516         int del_streams_count = 0;
2517
2518         memset(del_streams, 0, sizeof(del_streams));
2519
2520         context = dc_create_state(dc);
2521         if (context == NULL)
2522                 goto context_alloc_fail;
2523
2524         dc_resource_state_copy_construct_current(dc, context);
2525
2526         /* First remove from context all streams */
2527         for (i = 0; i < context->stream_count; i++) {
2528                 struct dc_stream_state *stream = context->streams[i];
2529
2530                 del_streams[del_streams_count++] = stream;
2531         }
2532
2533         /* Remove all planes for removed streams and then remove the streams */
2534         for (i = 0; i < del_streams_count; i++) {
2535                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2536                         res = DC_FAIL_DETACH_SURFACES;
2537                         goto fail;
2538                 }
2539
2540                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2541                 if (res != DC_OK)
2542                         goto fail;
2543         }
2544
2545         res = dc_commit_streams(dc, context->streams, context->stream_count);
2546
2547 fail:
2548         dc_release_state(context);
2549
2550 context_alloc_fail:
2551         return res;
2552 }
2553
2554 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2555 {
2556         int i;
2557
2558         if (dm->hpd_rx_offload_wq) {
2559                 for (i = 0; i < dm->dc->caps.max_links; i++)
2560                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2561         }
2562 }
2563
2564 static int dm_suspend(void *handle)
2565 {
2566         struct amdgpu_device *adev = handle;
2567         struct amdgpu_display_manager *dm = &adev->dm;
2568         int ret = 0;
2569
2570         if (amdgpu_in_reset(adev)) {
2571                 mutex_lock(&dm->dc_lock);
2572
2573                 dc_allow_idle_optimizations(adev->dm.dc, false);
2574
2575                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2576
2577                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2578
2579                 amdgpu_dm_commit_zero_streams(dm->dc);
2580
2581                 amdgpu_dm_irq_suspend(adev);
2582
2583                 hpd_rx_irq_work_suspend(dm);
2584
2585                 return ret;
2586         }
2587
2588         WARN_ON(adev->dm.cached_state);
2589         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2590
2591         s3_handle_mst(adev_to_drm(adev), true);
2592
2593         amdgpu_dm_irq_suspend(adev);
2594
2595         hpd_rx_irq_work_suspend(dm);
2596
2597         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2598
2599         return 0;
2600 }
2601
2602 struct amdgpu_dm_connector *
2603 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2604                                              struct drm_crtc *crtc)
2605 {
2606         u32 i;
2607         struct drm_connector_state *new_con_state;
2608         struct drm_connector *connector;
2609         struct drm_crtc *crtc_from_state;
2610
2611         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2612                 crtc_from_state = new_con_state->crtc;
2613
2614                 if (crtc_from_state == crtc)
2615                         return to_amdgpu_dm_connector(connector);
2616         }
2617
2618         return NULL;
2619 }
2620
2621 static void emulated_link_detect(struct dc_link *link)
2622 {
2623         struct dc_sink_init_data sink_init_data = { 0 };
2624         struct display_sink_capability sink_caps = { 0 };
2625         enum dc_edid_status edid_status;
2626         struct dc_context *dc_ctx = link->ctx;
2627         struct dc_sink *sink = NULL;
2628         struct dc_sink *prev_sink = NULL;
2629
2630         link->type = dc_connection_none;
2631         prev_sink = link->local_sink;
2632
2633         if (prev_sink)
2634                 dc_sink_release(prev_sink);
2635
2636         switch (link->connector_signal) {
2637         case SIGNAL_TYPE_HDMI_TYPE_A: {
2638                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2639                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2640                 break;
2641         }
2642
2643         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2644                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2645                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2646                 break;
2647         }
2648
2649         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2650                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2651                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2652                 break;
2653         }
2654
2655         case SIGNAL_TYPE_LVDS: {
2656                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2657                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2658                 break;
2659         }
2660
2661         case SIGNAL_TYPE_EDP: {
2662                 sink_caps.transaction_type =
2663                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2664                 sink_caps.signal = SIGNAL_TYPE_EDP;
2665                 break;
2666         }
2667
2668         case SIGNAL_TYPE_DISPLAY_PORT: {
2669                 sink_caps.transaction_type =
2670                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2671                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2672                 break;
2673         }
2674
2675         default:
2676                 DC_ERROR("Invalid connector type! signal:%d\n",
2677                         link->connector_signal);
2678                 return;
2679         }
2680
2681         sink_init_data.link = link;
2682         sink_init_data.sink_signal = sink_caps.signal;
2683
2684         sink = dc_sink_create(&sink_init_data);
2685         if (!sink) {
2686                 DC_ERROR("Failed to create sink!\n");
2687                 return;
2688         }
2689
2690         /* dc_sink_create returns a new reference */
2691         link->local_sink = sink;
2692
2693         edid_status = dm_helpers_read_local_edid(
2694                         link->ctx,
2695                         link,
2696                         sink);
2697
2698         if (edid_status != EDID_OK)
2699                 DC_ERROR("Failed to read EDID");
2700
2701 }
2702
2703 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2704                                      struct amdgpu_display_manager *dm)
2705 {
2706         struct {
2707                 struct dc_surface_update surface_updates[MAX_SURFACES];
2708                 struct dc_plane_info plane_infos[MAX_SURFACES];
2709                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2710                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2711                 struct dc_stream_update stream_update;
2712         } * bundle;
2713         int k, m;
2714
2715         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2716
2717         if (!bundle) {
2718                 dm_error("Failed to allocate update bundle\n");
2719                 goto cleanup;
2720         }
2721
2722         for (k = 0; k < dc_state->stream_count; k++) {
2723                 bundle->stream_update.stream = dc_state->streams[k];
2724
2725                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2726                         bundle->surface_updates[m].surface =
2727                                 dc_state->stream_status->plane_states[m];
2728                         bundle->surface_updates[m].surface->force_full_update =
2729                                 true;
2730                 }
2731
2732                 update_planes_and_stream_adapter(dm->dc,
2733                                          UPDATE_TYPE_FULL,
2734                                          dc_state->stream_status->plane_count,
2735                                          dc_state->streams[k],
2736                                          &bundle->stream_update,
2737                                          bundle->surface_updates);
2738         }
2739
2740 cleanup:
2741         kfree(bundle);
2742
2743         return;
2744 }
2745
2746 static int dm_resume(void *handle)
2747 {
2748         struct amdgpu_device *adev = handle;
2749         struct drm_device *ddev = adev_to_drm(adev);
2750         struct amdgpu_display_manager *dm = &adev->dm;
2751         struct amdgpu_dm_connector *aconnector;
2752         struct drm_connector *connector;
2753         struct drm_connector_list_iter iter;
2754         struct drm_crtc *crtc;
2755         struct drm_crtc_state *new_crtc_state;
2756         struct dm_crtc_state *dm_new_crtc_state;
2757         struct drm_plane *plane;
2758         struct drm_plane_state *new_plane_state;
2759         struct dm_plane_state *dm_new_plane_state;
2760         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2761         enum dc_connection_type new_connection_type = dc_connection_none;
2762         struct dc_state *dc_state;
2763         int i, r, j;
2764
2765         if (amdgpu_in_reset(adev)) {
2766                 dc_state = dm->cached_dc_state;
2767
2768                 /*
2769                  * The dc->current_state is backed up into dm->cached_dc_state
2770                  * before we commit 0 streams.
2771                  *
2772                  * DC will clear link encoder assignments on the real state
2773                  * but the changes won't propagate over to the copy we made
2774                  * before the 0 streams commit.
2775                  *
2776                  * DC expects that link encoder assignments are *not* valid
2777                  * when committing a state, so as a workaround we can copy
2778                  * off of the current state.
2779                  *
2780                  * We lose the previous assignments, but we had already
2781                  * commit 0 streams anyway.
2782                  */
2783                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2784
2785                 r = dm_dmub_hw_init(adev);
2786                 if (r)
2787                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2788
2789                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2790                 dc_resume(dm->dc);
2791
2792                 amdgpu_dm_irq_resume_early(adev);
2793
2794                 for (i = 0; i < dc_state->stream_count; i++) {
2795                         dc_state->streams[i]->mode_changed = true;
2796                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2797                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2798                                         = 0xffffffff;
2799                         }
2800                 }
2801
2802                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2803                         amdgpu_dm_outbox_init(adev);
2804                         dc_enable_dmub_outbox(adev->dm.dc);
2805                 }
2806
2807                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2808
2809                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2810
2811                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2812
2813                 dc_release_state(dm->cached_dc_state);
2814                 dm->cached_dc_state = NULL;
2815
2816                 amdgpu_dm_irq_resume_late(adev);
2817
2818                 mutex_unlock(&dm->dc_lock);
2819
2820                 return 0;
2821         }
2822         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2823         dc_release_state(dm_state->context);
2824         dm_state->context = dc_create_state(dm->dc);
2825         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2826         dc_resource_state_construct(dm->dc, dm_state->context);
2827
2828         /* Before powering on DC we need to re-initialize DMUB. */
2829         dm_dmub_hw_resume(adev);
2830
2831         /* Re-enable outbox interrupts for DPIA. */
2832         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2833                 amdgpu_dm_outbox_init(adev);
2834                 dc_enable_dmub_outbox(adev->dm.dc);
2835         }
2836
2837         /* power on hardware */
2838         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2839
2840         /* program HPD filter */
2841         dc_resume(dm->dc);
2842
2843         /*
2844          * early enable HPD Rx IRQ, should be done before set mode as short
2845          * pulse interrupts are used for MST
2846          */
2847         amdgpu_dm_irq_resume_early(adev);
2848
2849         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2850         s3_handle_mst(ddev, false);
2851
2852         /* Do detection*/
2853         drm_connector_list_iter_begin(ddev, &iter);
2854         drm_for_each_connector_iter(connector, &iter) {
2855                 aconnector = to_amdgpu_dm_connector(connector);
2856
2857                 if (!aconnector->dc_link)
2858                         continue;
2859
2860                 /*
2861                  * this is the case when traversing through already created
2862                  * MST connectors, should be skipped
2863                  */
2864                 if (aconnector && aconnector->mst_root)
2865                         continue;
2866
2867                 mutex_lock(&aconnector->hpd_lock);
2868                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2869                         DRM_ERROR("KMS: Failed to detect connector\n");
2870
2871                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2872                         emulated_link_detect(aconnector->dc_link);
2873                 } else {
2874                         mutex_lock(&dm->dc_lock);
2875                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2876                         mutex_unlock(&dm->dc_lock);
2877                 }
2878
2879                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2880                         aconnector->fake_enable = false;
2881
2882                 if (aconnector->dc_sink)
2883                         dc_sink_release(aconnector->dc_sink);
2884                 aconnector->dc_sink = NULL;
2885                 amdgpu_dm_update_connector_after_detect(aconnector);
2886                 mutex_unlock(&aconnector->hpd_lock);
2887         }
2888         drm_connector_list_iter_end(&iter);
2889
2890         /* Force mode set in atomic commit */
2891         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2892                 new_crtc_state->active_changed = true;
2893
2894         /*
2895          * atomic_check is expected to create the dc states. We need to release
2896          * them here, since they were duplicated as part of the suspend
2897          * procedure.
2898          */
2899         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2900                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2901                 if (dm_new_crtc_state->stream) {
2902                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2903                         dc_stream_release(dm_new_crtc_state->stream);
2904                         dm_new_crtc_state->stream = NULL;
2905                 }
2906         }
2907
2908         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2909                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2910                 if (dm_new_plane_state->dc_state) {
2911                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2912                         dc_plane_state_release(dm_new_plane_state->dc_state);
2913                         dm_new_plane_state->dc_state = NULL;
2914                 }
2915         }
2916
2917         drm_atomic_helper_resume(ddev, dm->cached_state);
2918
2919         dm->cached_state = NULL;
2920
2921         amdgpu_dm_irq_resume_late(adev);
2922
2923         amdgpu_dm_smu_write_watermarks_table(adev);
2924
2925         return 0;
2926 }
2927
2928 /**
2929  * DOC: DM Lifecycle
2930  *
2931  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2932  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2933  * the base driver's device list to be initialized and torn down accordingly.
2934  *
2935  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2936  */
2937
2938 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2939         .name = "dm",
2940         .early_init = dm_early_init,
2941         .late_init = dm_late_init,
2942         .sw_init = dm_sw_init,
2943         .sw_fini = dm_sw_fini,
2944         .early_fini = amdgpu_dm_early_fini,
2945         .hw_init = dm_hw_init,
2946         .hw_fini = dm_hw_fini,
2947         .suspend = dm_suspend,
2948         .resume = dm_resume,
2949         .is_idle = dm_is_idle,
2950         .wait_for_idle = dm_wait_for_idle,
2951         .check_soft_reset = dm_check_soft_reset,
2952         .soft_reset = dm_soft_reset,
2953         .set_clockgating_state = dm_set_clockgating_state,
2954         .set_powergating_state = dm_set_powergating_state,
2955 };
2956
2957 const struct amdgpu_ip_block_version dm_ip_block =
2958 {
2959         .type = AMD_IP_BLOCK_TYPE_DCE,
2960         .major = 1,
2961         .minor = 0,
2962         .rev = 0,
2963         .funcs = &amdgpu_dm_funcs,
2964 };
2965
2966
2967 /**
2968  * DOC: atomic
2969  *
2970  * *WIP*
2971  */
2972
2973 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2974         .fb_create = amdgpu_display_user_framebuffer_create,
2975         .get_format_info = amdgpu_dm_plane_get_format_info,
2976         .atomic_check = amdgpu_dm_atomic_check,
2977         .atomic_commit = drm_atomic_helper_commit,
2978 };
2979
2980 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2981         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2982         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2983 };
2984
2985 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2986 {
2987         struct amdgpu_dm_backlight_caps *caps;
2988         struct drm_connector *conn_base;
2989         struct amdgpu_device *adev;
2990         struct drm_luminance_range_info *luminance_range;
2991
2992         if (aconnector->bl_idx == -1 ||
2993             aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
2994                 return;
2995
2996         conn_base = &aconnector->base;
2997         adev = drm_to_adev(conn_base->dev);
2998
2999         caps = &adev->dm.backlight_caps[aconnector->bl_idx];
3000         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3001         caps->aux_support = false;
3002
3003         if (caps->ext_caps->bits.oled == 1 /*||
3004             caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3005             caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
3006                 caps->aux_support = true;
3007
3008         if (amdgpu_backlight == 0)
3009                 caps->aux_support = false;
3010         else if (amdgpu_backlight == 1)
3011                 caps->aux_support = true;
3012
3013         luminance_range = &conn_base->display_info.luminance_range;
3014
3015         if (luminance_range->max_luminance) {
3016                 caps->aux_min_input_signal = luminance_range->min_luminance;
3017                 caps->aux_max_input_signal = luminance_range->max_luminance;
3018         } else {
3019                 caps->aux_min_input_signal = 0;
3020                 caps->aux_max_input_signal = 512;
3021         }
3022 }
3023
3024 void amdgpu_dm_update_connector_after_detect(
3025                 struct amdgpu_dm_connector *aconnector)
3026 {
3027         struct drm_connector *connector = &aconnector->base;
3028         struct drm_device *dev = connector->dev;
3029         struct dc_sink *sink;
3030
3031         /* MST handled by drm_mst framework */
3032         if (aconnector->mst_mgr.mst_state == true)
3033                 return;
3034
3035         sink = aconnector->dc_link->local_sink;
3036         if (sink)
3037                 dc_sink_retain(sink);
3038
3039         /*
3040          * Edid mgmt connector gets first update only in mode_valid hook and then
3041          * the connector sink is set to either fake or physical sink depends on link status.
3042          * Skip if already done during boot.
3043          */
3044         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3045                         && aconnector->dc_em_sink) {
3046
3047                 /*
3048                  * For S3 resume with headless use eml_sink to fake stream
3049                  * because on resume connector->sink is set to NULL
3050                  */
3051                 mutex_lock(&dev->mode_config.mutex);
3052
3053                 if (sink) {
3054                         if (aconnector->dc_sink) {
3055                                 amdgpu_dm_update_freesync_caps(connector, NULL);
3056                                 /*
3057                                  * retain and release below are used to
3058                                  * bump up refcount for sink because the link doesn't point
3059                                  * to it anymore after disconnect, so on next crtc to connector
3060                                  * reshuffle by UMD we will get into unwanted dc_sink release
3061                                  */
3062                                 dc_sink_release(aconnector->dc_sink);
3063                         }
3064                         aconnector->dc_sink = sink;
3065                         dc_sink_retain(aconnector->dc_sink);
3066                         amdgpu_dm_update_freesync_caps(connector,
3067                                         aconnector->edid);
3068                 } else {
3069                         amdgpu_dm_update_freesync_caps(connector, NULL);
3070                         if (!aconnector->dc_sink) {
3071                                 aconnector->dc_sink = aconnector->dc_em_sink;
3072                                 dc_sink_retain(aconnector->dc_sink);
3073                         }
3074                 }
3075
3076                 mutex_unlock(&dev->mode_config.mutex);
3077
3078                 if (sink)
3079                         dc_sink_release(sink);
3080                 return;
3081         }
3082
3083         /*
3084          * TODO: temporary guard to look for proper fix
3085          * if this sink is MST sink, we should not do anything
3086          */
3087         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3088                 dc_sink_release(sink);
3089                 return;
3090         }
3091
3092         if (aconnector->dc_sink == sink) {
3093                 /*
3094                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
3095                  * Do nothing!!
3096                  */
3097                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3098                                 aconnector->connector_id);
3099                 if (sink)
3100                         dc_sink_release(sink);
3101                 return;
3102         }
3103
3104         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3105                 aconnector->connector_id, aconnector->dc_sink, sink);
3106
3107         mutex_lock(&dev->mode_config.mutex);
3108
3109         /*
3110          * 1. Update status of the drm connector
3111          * 2. Send an event and let userspace tell us what to do
3112          */
3113         if (sink) {
3114                 /*
3115                  * TODO: check if we still need the S3 mode update workaround.
3116                  * If yes, put it here.
3117                  */
3118                 if (aconnector->dc_sink) {
3119                         amdgpu_dm_update_freesync_caps(connector, NULL);
3120                         dc_sink_release(aconnector->dc_sink);
3121                 }
3122
3123                 aconnector->dc_sink = sink;
3124                 dc_sink_retain(aconnector->dc_sink);
3125                 if (sink->dc_edid.length == 0) {
3126                         aconnector->edid = NULL;
3127                         if (aconnector->dc_link->aux_mode) {
3128                                 drm_dp_cec_unset_edid(
3129                                         &aconnector->dm_dp_aux.aux);
3130                         }
3131                 } else {
3132                         aconnector->edid =
3133                                 (struct edid *)sink->dc_edid.raw_edid;
3134
3135                         if (aconnector->dc_link->aux_mode)
3136                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3137                                                     aconnector->edid);
3138                 }
3139
3140                 if (!aconnector->timing_requested) {
3141                         aconnector->timing_requested =
3142                                 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3143                         if (!aconnector->timing_requested)
3144                                 dm_error("failed to create aconnector->requested_timing\n");
3145                 }
3146
3147                 drm_connector_update_edid_property(connector, aconnector->edid);
3148                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3149                 update_connector_ext_caps(aconnector);
3150         } else {
3151                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3152                 amdgpu_dm_update_freesync_caps(connector, NULL);
3153                 drm_connector_update_edid_property(connector, NULL);
3154                 aconnector->num_modes = 0;
3155                 dc_sink_release(aconnector->dc_sink);
3156                 aconnector->dc_sink = NULL;
3157                 aconnector->edid = NULL;
3158                 kfree(aconnector->timing_requested);
3159                 aconnector->timing_requested = NULL;
3160                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3161                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3162                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3163         }
3164
3165         mutex_unlock(&dev->mode_config.mutex);
3166
3167         update_subconnector_property(aconnector);
3168
3169         if (sink)
3170                 dc_sink_release(sink);
3171 }
3172
3173 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3174 {
3175         struct drm_connector *connector = &aconnector->base;
3176         struct drm_device *dev = connector->dev;
3177         enum dc_connection_type new_connection_type = dc_connection_none;
3178         struct amdgpu_device *adev = drm_to_adev(dev);
3179         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3180         bool ret = false;
3181
3182         if (adev->dm.disable_hpd_irq)
3183                 return;
3184
3185         /*
3186          * In case of failure or MST no need to update connector status or notify the OS
3187          * since (for MST case) MST does this in its own context.
3188          */
3189         mutex_lock(&aconnector->hpd_lock);
3190
3191         if (adev->dm.hdcp_workqueue) {
3192                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3193                 dm_con_state->update_hdcp = true;
3194         }
3195         if (aconnector->fake_enable)
3196                 aconnector->fake_enable = false;
3197
3198         aconnector->timing_changed = false;
3199
3200         if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3201                 DRM_ERROR("KMS: Failed to detect connector\n");
3202
3203         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3204                 emulated_link_detect(aconnector->dc_link);
3205
3206                 drm_modeset_lock_all(dev);
3207                 dm_restore_drm_connector_state(dev, connector);
3208                 drm_modeset_unlock_all(dev);
3209
3210                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3211                         drm_kms_helper_connector_hotplug_event(connector);
3212         } else {
3213                 mutex_lock(&adev->dm.dc_lock);
3214                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3215                 mutex_unlock(&adev->dm.dc_lock);
3216                 if (ret) {
3217                         amdgpu_dm_update_connector_after_detect(aconnector);
3218
3219                         drm_modeset_lock_all(dev);
3220                         dm_restore_drm_connector_state(dev, connector);
3221                         drm_modeset_unlock_all(dev);
3222
3223                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3224                                 drm_kms_helper_connector_hotplug_event(connector);
3225                 }
3226         }
3227         mutex_unlock(&aconnector->hpd_lock);
3228
3229 }
3230
3231 static void handle_hpd_irq(void *param)
3232 {
3233         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3234
3235         handle_hpd_irq_helper(aconnector);
3236
3237 }
3238
3239 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
3240 {
3241         u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3242         u8 dret;
3243         bool new_irq_handled = false;
3244         int dpcd_addr;
3245         int dpcd_bytes_to_read;
3246
3247         const int max_process_count = 30;
3248         int process_count = 0;
3249
3250         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3251
3252         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3253                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3254                 /* DPCD 0x200 - 0x201 for downstream IRQ */
3255                 dpcd_addr = DP_SINK_COUNT;
3256         } else {
3257                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3258                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3259                 dpcd_addr = DP_SINK_COUNT_ESI;
3260         }
3261
3262         dret = drm_dp_dpcd_read(
3263                 &aconnector->dm_dp_aux.aux,
3264                 dpcd_addr,
3265                 esi,
3266                 dpcd_bytes_to_read);
3267
3268         while (dret == dpcd_bytes_to_read &&
3269                 process_count < max_process_count) {
3270                 u8 retry;
3271                 dret = 0;
3272
3273                 process_count++;
3274
3275                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3276                 /* handle HPD short pulse irq */
3277                 if (aconnector->mst_mgr.mst_state)
3278                         drm_dp_mst_hpd_irq(
3279                                 &aconnector->mst_mgr,
3280                                 esi,
3281                                 &new_irq_handled);
3282
3283                 if (new_irq_handled) {
3284                         /* ACK at DPCD to notify down stream */
3285                         const int ack_dpcd_bytes_to_write =
3286                                 dpcd_bytes_to_read - 1;
3287
3288                         for (retry = 0; retry < 3; retry++) {
3289                                 u8 wret;
3290
3291                                 wret = drm_dp_dpcd_write(
3292                                         &aconnector->dm_dp_aux.aux,
3293                                         dpcd_addr + 1,
3294                                         &esi[1],
3295                                         ack_dpcd_bytes_to_write);
3296                                 if (wret == ack_dpcd_bytes_to_write)
3297                                         break;
3298                         }
3299
3300                         /* check if there is new irq to be handled */
3301                         dret = drm_dp_dpcd_read(
3302                                 &aconnector->dm_dp_aux.aux,
3303                                 dpcd_addr,
3304                                 esi,
3305                                 dpcd_bytes_to_read);
3306
3307                         new_irq_handled = false;
3308                 } else {
3309                         break;
3310                 }
3311         }
3312
3313         if (process_count == max_process_count)
3314                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
3315 }
3316
3317 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3318                                                         union hpd_irq_data hpd_irq_data)
3319 {
3320         struct hpd_rx_irq_offload_work *offload_work =
3321                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3322
3323         if (!offload_work) {
3324                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3325                 return;
3326         }
3327
3328         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3329         offload_work->data = hpd_irq_data;
3330         offload_work->offload_wq = offload_wq;
3331
3332         queue_work(offload_wq->wq, &offload_work->work);
3333         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3334 }
3335
3336 static void handle_hpd_rx_irq(void *param)
3337 {
3338         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3339         struct drm_connector *connector = &aconnector->base;
3340         struct drm_device *dev = connector->dev;
3341         struct dc_link *dc_link = aconnector->dc_link;
3342         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3343         bool result = false;
3344         enum dc_connection_type new_connection_type = dc_connection_none;
3345         struct amdgpu_device *adev = drm_to_adev(dev);
3346         union hpd_irq_data hpd_irq_data;
3347         bool link_loss = false;
3348         bool has_left_work = false;
3349         int idx = dc_link->link_index;
3350         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3351
3352         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3353
3354         if (adev->dm.disable_hpd_irq)
3355                 return;
3356
3357         /*
3358          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3359          * conflict, after implement i2c helper, this mutex should be
3360          * retired.
3361          */
3362         mutex_lock(&aconnector->hpd_lock);
3363
3364         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3365                                                 &link_loss, true, &has_left_work);
3366
3367         if (!has_left_work)
3368                 goto out;
3369
3370         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3371                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3372                 goto out;
3373         }
3374
3375         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3376                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3377                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3378                         dm_handle_mst_sideband_msg(aconnector);
3379                         goto out;
3380                 }
3381
3382                 if (link_loss) {
3383                         bool skip = false;
3384
3385                         spin_lock(&offload_wq->offload_lock);
3386                         skip = offload_wq->is_handling_link_loss;
3387
3388                         if (!skip)
3389                                 offload_wq->is_handling_link_loss = true;
3390
3391                         spin_unlock(&offload_wq->offload_lock);
3392
3393                         if (!skip)
3394                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3395
3396                         goto out;
3397                 }
3398         }
3399
3400 out:
3401         if (result && !is_mst_root_connector) {
3402                 /* Downstream Port status changed. */
3403                 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3404                         DRM_ERROR("KMS: Failed to detect connector\n");
3405
3406                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3407                         emulated_link_detect(dc_link);
3408
3409                         if (aconnector->fake_enable)
3410                                 aconnector->fake_enable = false;
3411
3412                         amdgpu_dm_update_connector_after_detect(aconnector);
3413
3414
3415                         drm_modeset_lock_all(dev);
3416                         dm_restore_drm_connector_state(dev, connector);
3417                         drm_modeset_unlock_all(dev);
3418
3419                         drm_kms_helper_connector_hotplug_event(connector);
3420                 } else {
3421                         bool ret = false;
3422
3423                         mutex_lock(&adev->dm.dc_lock);
3424                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3425                         mutex_unlock(&adev->dm.dc_lock);
3426
3427                         if (ret) {
3428                                 if (aconnector->fake_enable)
3429                                         aconnector->fake_enable = false;
3430
3431                                 amdgpu_dm_update_connector_after_detect(aconnector);
3432
3433                                 drm_modeset_lock_all(dev);
3434                                 dm_restore_drm_connector_state(dev, connector);
3435                                 drm_modeset_unlock_all(dev);
3436
3437                                 drm_kms_helper_connector_hotplug_event(connector);
3438                         }
3439                 }
3440         }
3441         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3442                 if (adev->dm.hdcp_workqueue)
3443                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3444         }
3445
3446         if (dc_link->type != dc_connection_mst_branch)
3447                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3448
3449         mutex_unlock(&aconnector->hpd_lock);
3450 }
3451
3452 static void register_hpd_handlers(struct amdgpu_device *adev)
3453 {
3454         struct drm_device *dev = adev_to_drm(adev);
3455         struct drm_connector *connector;
3456         struct amdgpu_dm_connector *aconnector;
3457         const struct dc_link *dc_link;
3458         struct dc_interrupt_params int_params = {0};
3459
3460         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3461         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3462
3463         list_for_each_entry(connector,
3464                         &dev->mode_config.connector_list, head) {
3465
3466                 aconnector = to_amdgpu_dm_connector(connector);
3467                 dc_link = aconnector->dc_link;
3468
3469                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3470                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3471                         int_params.irq_source = dc_link->irq_source_hpd;
3472
3473                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3474                                         handle_hpd_irq,
3475                                         (void *) aconnector);
3476                 }
3477
3478                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3479
3480                         /* Also register for DP short pulse (hpd_rx). */
3481                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3482                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3483
3484                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3485                                         handle_hpd_rx_irq,
3486                                         (void *) aconnector);
3487
3488                         if (adev->dm.hpd_rx_offload_wq)
3489                                 adev->dm.hpd_rx_offload_wq[dc_link->link_index].aconnector =
3490                                         aconnector;
3491                 }
3492         }
3493 }
3494
3495 #if defined(CONFIG_DRM_AMD_DC_SI)
3496 /* Register IRQ sources and initialize IRQ callbacks */
3497 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3498 {
3499         struct dc *dc = adev->dm.dc;
3500         struct common_irq_params *c_irq_params;
3501         struct dc_interrupt_params int_params = {0};
3502         int r;
3503         int i;
3504         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3505
3506         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3507         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3508
3509         /*
3510          * Actions of amdgpu_irq_add_id():
3511          * 1. Register a set() function with base driver.
3512          *    Base driver will call set() function to enable/disable an
3513          *    interrupt in DC hardware.
3514          * 2. Register amdgpu_dm_irq_handler().
3515          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3516          *    coming from DC hardware.
3517          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3518          *    for acknowledging and handling. */
3519
3520         /* Use VBLANK interrupt */
3521         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3522                 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3523                 if (r) {
3524                         DRM_ERROR("Failed to add crtc irq id!\n");
3525                         return r;
3526                 }
3527
3528                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3529                 int_params.irq_source =
3530                         dc_interrupt_to_irq_source(dc, i+1 , 0);
3531
3532                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3533
3534                 c_irq_params->adev = adev;
3535                 c_irq_params->irq_src = int_params.irq_source;
3536
3537                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3538                                 dm_crtc_high_irq, c_irq_params);
3539         }
3540
3541         /* Use GRPH_PFLIP interrupt */
3542         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3543                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3544                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3545                 if (r) {
3546                         DRM_ERROR("Failed to add page flip irq id!\n");
3547                         return r;
3548                 }
3549
3550                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3551                 int_params.irq_source =
3552                         dc_interrupt_to_irq_source(dc, i, 0);
3553
3554                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3555
3556                 c_irq_params->adev = adev;
3557                 c_irq_params->irq_src = int_params.irq_source;
3558
3559                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3560                                 dm_pflip_high_irq, c_irq_params);
3561
3562         }
3563
3564         /* HPD */
3565         r = amdgpu_irq_add_id(adev, client_id,
3566                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3567         if (r) {
3568                 DRM_ERROR("Failed to add hpd irq id!\n");
3569                 return r;
3570         }
3571
3572         register_hpd_handlers(adev);
3573
3574         return 0;
3575 }
3576 #endif
3577
3578 /* Register IRQ sources and initialize IRQ callbacks */
3579 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3580 {
3581         struct dc *dc = adev->dm.dc;
3582         struct common_irq_params *c_irq_params;
3583         struct dc_interrupt_params int_params = {0};
3584         int r;
3585         int i;
3586         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3587
3588         if (adev->family >= AMDGPU_FAMILY_AI)
3589                 client_id = SOC15_IH_CLIENTID_DCE;
3590
3591         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3592         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3593
3594         /*
3595          * Actions of amdgpu_irq_add_id():
3596          * 1. Register a set() function with base driver.
3597          *    Base driver will call set() function to enable/disable an
3598          *    interrupt in DC hardware.
3599          * 2. Register amdgpu_dm_irq_handler().
3600          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3601          *    coming from DC hardware.
3602          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3603          *    for acknowledging and handling. */
3604
3605         /* Use VBLANK interrupt */
3606         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3607                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3608                 if (r) {
3609                         DRM_ERROR("Failed to add crtc irq id!\n");
3610                         return r;
3611                 }
3612
3613                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3614                 int_params.irq_source =
3615                         dc_interrupt_to_irq_source(dc, i, 0);
3616
3617                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3618
3619                 c_irq_params->adev = adev;
3620                 c_irq_params->irq_src = int_params.irq_source;
3621
3622                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3623                                 dm_crtc_high_irq, c_irq_params);
3624         }
3625
3626         /* Use VUPDATE interrupt */
3627         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3628                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3629                 if (r) {
3630                         DRM_ERROR("Failed to add vupdate irq id!\n");
3631                         return r;
3632                 }
3633
3634                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3635                 int_params.irq_source =
3636                         dc_interrupt_to_irq_source(dc, i, 0);
3637
3638                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3639
3640                 c_irq_params->adev = adev;
3641                 c_irq_params->irq_src = int_params.irq_source;
3642
3643                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3644                                 dm_vupdate_high_irq, c_irq_params);
3645         }
3646
3647         /* Use GRPH_PFLIP interrupt */
3648         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3649                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3650                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3651                 if (r) {
3652                         DRM_ERROR("Failed to add page flip irq id!\n");
3653                         return r;
3654                 }
3655
3656                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3657                 int_params.irq_source =
3658                         dc_interrupt_to_irq_source(dc, i, 0);
3659
3660                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3661
3662                 c_irq_params->adev = adev;
3663                 c_irq_params->irq_src = int_params.irq_source;
3664
3665                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3666                                 dm_pflip_high_irq, c_irq_params);
3667
3668         }
3669
3670         /* HPD */
3671         r = amdgpu_irq_add_id(adev, client_id,
3672                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3673         if (r) {
3674                 DRM_ERROR("Failed to add hpd irq id!\n");
3675                 return r;
3676         }
3677
3678         register_hpd_handlers(adev);
3679
3680         return 0;
3681 }
3682
3683 /* Register IRQ sources and initialize IRQ callbacks */
3684 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3685 {
3686         struct dc *dc = adev->dm.dc;
3687         struct common_irq_params *c_irq_params;
3688         struct dc_interrupt_params int_params = {0};
3689         int r;
3690         int i;
3691 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3692         static const unsigned int vrtl_int_srcid[] = {
3693                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3694                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3695                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3696                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3697                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3698                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3699         };
3700 #endif
3701
3702         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3703         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3704
3705         /*
3706          * Actions of amdgpu_irq_add_id():
3707          * 1. Register a set() function with base driver.
3708          *    Base driver will call set() function to enable/disable an
3709          *    interrupt in DC hardware.
3710          * 2. Register amdgpu_dm_irq_handler().
3711          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3712          *    coming from DC hardware.
3713          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3714          *    for acknowledging and handling.
3715          */
3716
3717         /* Use VSTARTUP interrupt */
3718         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3719                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3720                         i++) {
3721                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3722
3723                 if (r) {
3724                         DRM_ERROR("Failed to add crtc irq id!\n");
3725                         return r;
3726                 }
3727
3728                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3729                 int_params.irq_source =
3730                         dc_interrupt_to_irq_source(dc, i, 0);
3731
3732                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3733
3734                 c_irq_params->adev = adev;
3735                 c_irq_params->irq_src = int_params.irq_source;
3736
3737                 amdgpu_dm_irq_register_interrupt(
3738                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3739         }
3740
3741         /* Use otg vertical line interrupt */
3742 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3743         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3744                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3745                                 vrtl_int_srcid[i], &adev->vline0_irq);
3746
3747                 if (r) {
3748                         DRM_ERROR("Failed to add vline0 irq id!\n");
3749                         return r;
3750                 }
3751
3752                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3753                 int_params.irq_source =
3754                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3755
3756                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3757                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3758                         break;
3759                 }
3760
3761                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3762                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3763
3764                 c_irq_params->adev = adev;
3765                 c_irq_params->irq_src = int_params.irq_source;
3766
3767                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3768                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3769         }
3770 #endif
3771
3772         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3773          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3774          * to trigger at end of each vblank, regardless of state of the lock,
3775          * matching DCE behaviour.
3776          */
3777         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3778              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3779              i++) {
3780                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3781
3782                 if (r) {
3783                         DRM_ERROR("Failed to add vupdate irq id!\n");
3784                         return r;
3785                 }
3786
3787                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3788                 int_params.irq_source =
3789                         dc_interrupt_to_irq_source(dc, i, 0);
3790
3791                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3792
3793                 c_irq_params->adev = adev;
3794                 c_irq_params->irq_src = int_params.irq_source;
3795
3796                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3797                                 dm_vupdate_high_irq, c_irq_params);
3798         }
3799
3800         /* Use GRPH_PFLIP interrupt */
3801         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3802                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3803                         i++) {
3804                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3805                 if (r) {
3806                         DRM_ERROR("Failed to add page flip irq id!\n");
3807                         return r;
3808                 }
3809
3810                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3811                 int_params.irq_source =
3812                         dc_interrupt_to_irq_source(dc, i, 0);
3813
3814                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3815
3816                 c_irq_params->adev = adev;
3817                 c_irq_params->irq_src = int_params.irq_source;
3818
3819                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3820                                 dm_pflip_high_irq, c_irq_params);
3821
3822         }
3823
3824         /* HPD */
3825         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3826                         &adev->hpd_irq);
3827         if (r) {
3828                 DRM_ERROR("Failed to add hpd irq id!\n");
3829                 return r;
3830         }
3831
3832         register_hpd_handlers(adev);
3833
3834         return 0;
3835 }
3836 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3837 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3838 {
3839         struct dc *dc = adev->dm.dc;
3840         struct common_irq_params *c_irq_params;
3841         struct dc_interrupt_params int_params = {0};
3842         int r, i;
3843
3844         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3845         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3846
3847         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3848                         &adev->dmub_outbox_irq);
3849         if (r) {
3850                 DRM_ERROR("Failed to add outbox irq id!\n");
3851                 return r;
3852         }
3853
3854         if (dc->ctx->dmub_srv) {
3855                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3856                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3857                 int_params.irq_source =
3858                 dc_interrupt_to_irq_source(dc, i, 0);
3859
3860                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3861
3862                 c_irq_params->adev = adev;
3863                 c_irq_params->irq_src = int_params.irq_source;
3864
3865                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3866                                 dm_dmub_outbox1_low_irq, c_irq_params);
3867         }
3868
3869         return 0;
3870 }
3871
3872 /*
3873  * Acquires the lock for the atomic state object and returns
3874  * the new atomic state.
3875  *
3876  * This should only be called during atomic check.
3877  */
3878 int dm_atomic_get_state(struct drm_atomic_state *state,
3879                         struct dm_atomic_state **dm_state)
3880 {
3881         struct drm_device *dev = state->dev;
3882         struct amdgpu_device *adev = drm_to_adev(dev);
3883         struct amdgpu_display_manager *dm = &adev->dm;
3884         struct drm_private_state *priv_state;
3885
3886         if (*dm_state)
3887                 return 0;
3888
3889         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3890         if (IS_ERR(priv_state))
3891                 return PTR_ERR(priv_state);
3892
3893         *dm_state = to_dm_atomic_state(priv_state);
3894
3895         return 0;
3896 }
3897
3898 static struct dm_atomic_state *
3899 dm_atomic_get_new_state(struct drm_atomic_state *state)
3900 {
3901         struct drm_device *dev = state->dev;
3902         struct amdgpu_device *adev = drm_to_adev(dev);
3903         struct amdgpu_display_manager *dm = &adev->dm;
3904         struct drm_private_obj *obj;
3905         struct drm_private_state *new_obj_state;
3906         int i;
3907
3908         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3909                 if (obj->funcs == dm->atomic_obj.funcs)
3910                         return to_dm_atomic_state(new_obj_state);
3911         }
3912
3913         return NULL;
3914 }
3915
3916 static struct drm_private_state *
3917 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3918 {
3919         struct dm_atomic_state *old_state, *new_state;
3920
3921         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3922         if (!new_state)
3923                 return NULL;
3924
3925         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3926
3927         old_state = to_dm_atomic_state(obj->state);
3928
3929         if (old_state && old_state->context)
3930                 new_state->context = dc_copy_state(old_state->context);
3931
3932         if (!new_state->context) {
3933                 kfree(new_state);
3934                 return NULL;
3935         }
3936
3937         return &new_state->base;
3938 }
3939
3940 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3941                                     struct drm_private_state *state)
3942 {
3943         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3944
3945         if (dm_state && dm_state->context)
3946                 dc_release_state(dm_state->context);
3947
3948         kfree(dm_state);
3949 }
3950
3951 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3952         .atomic_duplicate_state = dm_atomic_duplicate_state,
3953         .atomic_destroy_state = dm_atomic_destroy_state,
3954 };
3955
3956 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3957 {
3958         struct dm_atomic_state *state;
3959         int r;
3960
3961         adev->mode_info.mode_config_initialized = true;
3962
3963         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3964         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3965
3966         adev_to_drm(adev)->mode_config.max_width = 16384;
3967         adev_to_drm(adev)->mode_config.max_height = 16384;
3968
3969         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3970         if (adev->asic_type == CHIP_HAWAII)
3971                 /* disable prefer shadow for now due to hibernation issues */
3972                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3973         else
3974                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3975         /* indicates support for immediate flip */
3976         adev_to_drm(adev)->mode_config.async_page_flip = true;
3977
3978         state = kzalloc(sizeof(*state), GFP_KERNEL);
3979         if (!state)
3980                 return -ENOMEM;
3981
3982         state->context = dc_create_state(adev->dm.dc);
3983         if (!state->context) {
3984                 kfree(state);
3985                 return -ENOMEM;
3986         }
3987
3988         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3989
3990         drm_atomic_private_obj_init(adev_to_drm(adev),
3991                                     &adev->dm.atomic_obj,
3992                                     &state->base,
3993                                     &dm_atomic_state_funcs);
3994
3995         r = amdgpu_display_modeset_create_props(adev);
3996         if (r) {
3997                 dc_release_state(state->context);
3998                 kfree(state);
3999                 return r;
4000         }
4001
4002         r = amdgpu_dm_audio_init(adev);
4003         if (r) {
4004                 dc_release_state(state->context);
4005                 kfree(state);
4006                 return r;
4007         }
4008
4009         return 0;
4010 }
4011
4012 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4013 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4014 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4015
4016 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4017                                             int bl_idx)
4018 {
4019 #if defined(CONFIG_ACPI)
4020         struct amdgpu_dm_backlight_caps caps;
4021
4022         memset(&caps, 0, sizeof(caps));
4023
4024         if (dm->backlight_caps[bl_idx].caps_valid)
4025                 return;
4026
4027         amdgpu_acpi_get_backlight_caps(&caps);
4028         if (caps.caps_valid) {
4029                 dm->backlight_caps[bl_idx].caps_valid = true;
4030                 if (caps.aux_support)
4031                         return;
4032                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4033                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4034         } else {
4035                 dm->backlight_caps[bl_idx].min_input_signal =
4036                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4037                 dm->backlight_caps[bl_idx].max_input_signal =
4038                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4039         }
4040 #else
4041         if (dm->backlight_caps[bl_idx].aux_support)
4042                 return;
4043
4044         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4045         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4046 #endif
4047 }
4048
4049 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4050                                 unsigned *min, unsigned *max)
4051 {
4052         if (!caps)
4053                 return 0;
4054
4055         if (caps->aux_support) {
4056                 // Firmware limits are in nits, DC API wants millinits.
4057                 *max = 1000 * caps->aux_max_input_signal;
4058                 *min = 1000 * caps->aux_min_input_signal;
4059         } else {
4060                 // Firmware limits are 8-bit, PWM control is 16-bit.
4061                 *max = 0x101 * caps->max_input_signal;
4062                 *min = 0x101 * caps->min_input_signal;
4063         }
4064         return 1;
4065 }
4066
4067 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4068                                         uint32_t brightness)
4069 {
4070         unsigned min, max;
4071
4072         if (!get_brightness_range(caps, &min, &max))
4073                 return brightness;
4074
4075         // Rescale 0..255 to min..max
4076         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4077                                        AMDGPU_MAX_BL_LEVEL);
4078 }
4079
4080 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4081                                       uint32_t brightness)
4082 {
4083         unsigned min, max;
4084
4085         if (!get_brightness_range(caps, &min, &max))
4086                 return brightness;
4087
4088         if (brightness < min)
4089                 return 0;
4090         // Rescale min..max to 0..255
4091         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4092                                  max - min);
4093 }
4094
4095 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4096                                          int bl_idx,
4097                                          u32 user_brightness)
4098 {
4099         struct amdgpu_dm_backlight_caps caps;
4100         struct dc_link *link;
4101         u32 brightness;
4102         bool rc;
4103
4104         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4105         caps = dm->backlight_caps[bl_idx];
4106
4107         dm->brightness[bl_idx] = user_brightness;
4108         /* update scratch register */
4109         if (bl_idx == 0)
4110                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4111         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4112         link = (struct dc_link *)dm->backlight_link[bl_idx];
4113
4114         /* Change brightness based on AUX property */
4115         if (caps.aux_support) {
4116                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4117                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4118                 if (!rc)
4119                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4120         } else {
4121                 rc = dc_link_set_backlight_level(link, brightness, 0);
4122                 if (!rc)
4123                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4124         }
4125
4126         if (rc)
4127                 dm->actual_brightness[bl_idx] = user_brightness;
4128 }
4129
4130 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4131 {
4132         struct amdgpu_display_manager *dm = bl_get_data(bd);
4133         int i;
4134
4135         for (i = 0; i < dm->num_of_edps; i++) {
4136                 if (bd == dm->backlight_dev[i])
4137                         break;
4138         }
4139         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4140                 i = 0;
4141         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4142
4143         return 0;
4144 }
4145
4146 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4147                                          int bl_idx)
4148 {
4149         struct amdgpu_dm_backlight_caps caps;
4150         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4151
4152         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4153         caps = dm->backlight_caps[bl_idx];
4154
4155         if (caps.aux_support) {
4156                 u32 avg, peak;
4157                 bool rc;
4158
4159                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4160                 if (!rc)
4161                         return dm->brightness[bl_idx];
4162                 return convert_brightness_to_user(&caps, avg);
4163         } else {
4164                 int ret = dc_link_get_backlight_level(link);
4165
4166                 if (ret == DC_ERROR_UNEXPECTED)
4167                         return dm->brightness[bl_idx];
4168                 return convert_brightness_to_user(&caps, ret);
4169         }
4170 }
4171
4172 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4173 {
4174         struct amdgpu_display_manager *dm = bl_get_data(bd);
4175         int i;
4176
4177         for (i = 0; i < dm->num_of_edps; i++) {
4178                 if (bd == dm->backlight_dev[i])
4179                         break;
4180         }
4181         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4182                 i = 0;
4183         return amdgpu_dm_backlight_get_level(dm, i);
4184 }
4185
4186 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4187         .options = BL_CORE_SUSPENDRESUME,
4188         .get_brightness = amdgpu_dm_backlight_get_brightness,
4189         .update_status  = amdgpu_dm_backlight_update_status,
4190 };
4191
4192 static void
4193 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4194 {
4195         struct drm_device *drm = aconnector->base.dev;
4196         struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4197         struct backlight_properties props = { 0 };
4198         char bl_name[16];
4199
4200         if (aconnector->bl_idx == -1)
4201                 return;
4202
4203         if (!acpi_video_backlight_use_native()) {
4204                 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4205                 /* Try registering an ACPI video backlight device instead. */
4206                 acpi_video_register_backlight();
4207                 return;
4208         }
4209
4210         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4211         props.brightness = AMDGPU_MAX_BL_LEVEL;
4212         props.type = BACKLIGHT_RAW;
4213
4214         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4215                  drm->primary->index + aconnector->bl_idx);
4216
4217         dm->backlight_dev[aconnector->bl_idx] =
4218                 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4219                                           &amdgpu_dm_backlight_ops, &props);
4220
4221         if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4222                 DRM_ERROR("DM: Backlight registration failed!\n");
4223                 dm->backlight_dev[aconnector->bl_idx] = NULL;
4224         } else
4225                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4226 }
4227
4228 static int initialize_plane(struct amdgpu_display_manager *dm,
4229                             struct amdgpu_mode_info *mode_info, int plane_id,
4230                             enum drm_plane_type plane_type,
4231                             const struct dc_plane_cap *plane_cap)
4232 {
4233         struct drm_plane *plane;
4234         unsigned long possible_crtcs;
4235         int ret = 0;
4236
4237         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4238         if (!plane) {
4239                 DRM_ERROR("KMS: Failed to allocate plane\n");
4240                 return -ENOMEM;
4241         }
4242         plane->type = plane_type;
4243
4244         /*
4245          * HACK: IGT tests expect that the primary plane for a CRTC
4246          * can only have one possible CRTC. Only expose support for
4247          * any CRTC if they're not going to be used as a primary plane
4248          * for a CRTC - like overlay or underlay planes.
4249          */
4250         possible_crtcs = 1 << plane_id;
4251         if (plane_id >= dm->dc->caps.max_streams)
4252                 possible_crtcs = 0xff;
4253
4254         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4255
4256         if (ret) {
4257                 DRM_ERROR("KMS: Failed to initialize plane\n");
4258                 kfree(plane);
4259                 return ret;
4260         }
4261
4262         if (mode_info)
4263                 mode_info->planes[plane_id] = plane;
4264
4265         return ret;
4266 }
4267
4268
4269 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4270                                    struct amdgpu_dm_connector *aconnector)
4271 {
4272         struct dc_link *link = aconnector->dc_link;
4273         int bl_idx = dm->num_of_edps;
4274
4275         if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4276             link->type == dc_connection_none)
4277                 return;
4278
4279         if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4280                 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4281                 return;
4282         }
4283
4284         aconnector->bl_idx = bl_idx;
4285
4286         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4287         dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4288         dm->backlight_link[bl_idx] = link;
4289         dm->num_of_edps++;
4290
4291         update_connector_ext_caps(aconnector);
4292 }
4293
4294 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4295
4296 /*
4297  * In this architecture, the association
4298  * connector -> encoder -> crtc
4299  * id not really requried. The crtc and connector will hold the
4300  * display_index as an abstraction to use with DAL component
4301  *
4302  * Returns 0 on success
4303  */
4304 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4305 {
4306         struct amdgpu_display_manager *dm = &adev->dm;
4307         s32 i;
4308         struct amdgpu_dm_connector *aconnector = NULL;
4309         struct amdgpu_encoder *aencoder = NULL;
4310         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4311         u32 link_cnt;
4312         s32 primary_planes;
4313         enum dc_connection_type new_connection_type = dc_connection_none;
4314         const struct dc_plane_cap *plane;
4315         bool psr_feature_enabled = false;
4316         int max_overlay = dm->dc->caps.max_slave_planes;
4317
4318         dm->display_indexes_num = dm->dc->caps.max_streams;
4319         /* Update the actual used number of crtc */
4320         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4321
4322         amdgpu_dm_set_irq_funcs(adev);
4323
4324         link_cnt = dm->dc->caps.max_links;
4325         if (amdgpu_dm_mode_config_init(dm->adev)) {
4326                 DRM_ERROR("DM: Failed to initialize mode config\n");
4327                 return -EINVAL;
4328         }
4329
4330         /* There is one primary plane per CRTC */
4331         primary_planes = dm->dc->caps.max_streams;
4332         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4333
4334         /*
4335          * Initialize primary planes, implicit planes for legacy IOCTLS.
4336          * Order is reversed to match iteration order in atomic check.
4337          */
4338         for (i = (primary_planes - 1); i >= 0; i--) {
4339                 plane = &dm->dc->caps.planes[i];
4340
4341                 if (initialize_plane(dm, mode_info, i,
4342                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4343                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4344                         goto fail;
4345                 }
4346         }
4347
4348         /*
4349          * Initialize overlay planes, index starting after primary planes.
4350          * These planes have a higher DRM index than the primary planes since
4351          * they should be considered as having a higher z-order.
4352          * Order is reversed to match iteration order in atomic check.
4353          *
4354          * Only support DCN for now, and only expose one so we don't encourage
4355          * userspace to use up all the pipes.
4356          */
4357         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4358                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4359
4360                 /* Do not create overlay if MPO disabled */
4361                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4362                         break;
4363
4364                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4365                         continue;
4366
4367                 if (!plane->pixel_format_support.argb8888)
4368                         continue;
4369
4370                 if (max_overlay-- == 0)
4371                         break;
4372
4373                 if (initialize_plane(dm, NULL, primary_planes + i,
4374                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4375                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4376                         goto fail;
4377                 }
4378         }
4379
4380         for (i = 0; i < dm->dc->caps.max_streams; i++)
4381                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4382                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4383                         goto fail;
4384                 }
4385
4386         /* Use Outbox interrupt */
4387         switch (adev->ip_versions[DCE_HWIP][0]) {
4388         case IP_VERSION(3, 0, 0):
4389         case IP_VERSION(3, 1, 2):
4390         case IP_VERSION(3, 1, 3):
4391         case IP_VERSION(3, 1, 4):
4392         case IP_VERSION(3, 1, 5):
4393         case IP_VERSION(3, 1, 6):
4394         case IP_VERSION(3, 2, 0):
4395         case IP_VERSION(3, 2, 1):
4396         case IP_VERSION(2, 1, 0):
4397                 if (register_outbox_irq_handlers(dm->adev)) {
4398                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4399                         goto fail;
4400                 }
4401                 break;
4402         default:
4403                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4404                               adev->ip_versions[DCE_HWIP][0]);
4405         }
4406
4407         /* Determine whether to enable PSR support by default. */
4408         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4409                 switch (adev->ip_versions[DCE_HWIP][0]) {
4410                 case IP_VERSION(3, 1, 2):
4411                 case IP_VERSION(3, 1, 3):
4412                 case IP_VERSION(3, 1, 4):
4413                 case IP_VERSION(3, 1, 5):
4414                 case IP_VERSION(3, 1, 6):
4415                 case IP_VERSION(3, 2, 0):
4416                 case IP_VERSION(3, 2, 1):
4417                         psr_feature_enabled = true;
4418                         break;
4419                 default:
4420                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4421                         break;
4422                 }
4423         }
4424
4425         /* loops over all connectors on the board */
4426         for (i = 0; i < link_cnt; i++) {
4427                 struct dc_link *link = NULL;
4428
4429                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4430                         DRM_ERROR(
4431                                 "KMS: Cannot support more than %d display indexes\n",
4432                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4433                         continue;
4434                 }
4435
4436                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4437                 if (!aconnector)
4438                         goto fail;
4439
4440                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4441                 if (!aencoder)
4442                         goto fail;
4443
4444                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4445                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4446                         goto fail;
4447                 }
4448
4449                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4450                         DRM_ERROR("KMS: Failed to initialize connector\n");
4451                         goto fail;
4452                 }
4453
4454                 link = dc_get_link_at_index(dm->dc, i);
4455
4456                 if (!dc_link_detect_connection_type(link, &new_connection_type))
4457                         DRM_ERROR("KMS: Failed to detect connector\n");
4458
4459                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4460                         emulated_link_detect(link);
4461                         amdgpu_dm_update_connector_after_detect(aconnector);
4462                 } else {
4463                         bool ret = false;
4464
4465                         mutex_lock(&dm->dc_lock);
4466                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4467                         mutex_unlock(&dm->dc_lock);
4468
4469                         if (ret) {
4470                                 amdgpu_dm_update_connector_after_detect(aconnector);
4471                                 setup_backlight_device(dm, aconnector);
4472
4473                                 if (psr_feature_enabled)
4474                                         amdgpu_dm_set_psr_caps(link);
4475
4476                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4477                                  * PSR is also supported.
4478                                  */
4479                                 if (link->psr_settings.psr_feature_enabled)
4480                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4481                         }
4482                 }
4483                 amdgpu_set_panel_orientation(&aconnector->base);
4484         }
4485
4486         /* If we didn't find a panel, notify the acpi video detection */
4487         if (dm->adev->flags & AMD_IS_APU && dm->num_of_edps == 0)
4488                 acpi_video_report_nolcd();
4489
4490         /* Software is initialized. Now we can register interrupt handlers. */
4491         switch (adev->asic_type) {
4492 #if defined(CONFIG_DRM_AMD_DC_SI)
4493         case CHIP_TAHITI:
4494         case CHIP_PITCAIRN:
4495         case CHIP_VERDE:
4496         case CHIP_OLAND:
4497                 if (dce60_register_irq_handlers(dm->adev)) {
4498                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4499                         goto fail;
4500                 }
4501                 break;
4502 #endif
4503         case CHIP_BONAIRE:
4504         case CHIP_HAWAII:
4505         case CHIP_KAVERI:
4506         case CHIP_KABINI:
4507         case CHIP_MULLINS:
4508         case CHIP_TONGA:
4509         case CHIP_FIJI:
4510         case CHIP_CARRIZO:
4511         case CHIP_STONEY:
4512         case CHIP_POLARIS11:
4513         case CHIP_POLARIS10:
4514         case CHIP_POLARIS12:
4515         case CHIP_VEGAM:
4516         case CHIP_VEGA10:
4517         case CHIP_VEGA12:
4518         case CHIP_VEGA20:
4519                 if (dce110_register_irq_handlers(dm->adev)) {
4520                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4521                         goto fail;
4522                 }
4523                 break;
4524         default:
4525                 switch (adev->ip_versions[DCE_HWIP][0]) {
4526                 case IP_VERSION(1, 0, 0):
4527                 case IP_VERSION(1, 0, 1):
4528                 case IP_VERSION(2, 0, 2):
4529                 case IP_VERSION(2, 0, 3):
4530                 case IP_VERSION(2, 0, 0):
4531                 case IP_VERSION(2, 1, 0):
4532                 case IP_VERSION(3, 0, 0):
4533                 case IP_VERSION(3, 0, 2):
4534                 case IP_VERSION(3, 0, 3):
4535                 case IP_VERSION(3, 0, 1):
4536                 case IP_VERSION(3, 1, 2):
4537                 case IP_VERSION(3, 1, 3):
4538                 case IP_VERSION(3, 1, 4):
4539                 case IP_VERSION(3, 1, 5):
4540                 case IP_VERSION(3, 1, 6):
4541                 case IP_VERSION(3, 2, 0):
4542                 case IP_VERSION(3, 2, 1):
4543                         if (dcn10_register_irq_handlers(dm->adev)) {
4544                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4545                                 goto fail;
4546                         }
4547                         break;
4548                 default:
4549                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4550                                         adev->ip_versions[DCE_HWIP][0]);
4551                         goto fail;
4552                 }
4553                 break;
4554         }
4555
4556         return 0;
4557 fail:
4558         kfree(aencoder);
4559         kfree(aconnector);
4560
4561         return -EINVAL;
4562 }
4563
4564 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4565 {
4566         drm_atomic_private_obj_fini(&dm->atomic_obj);
4567         return;
4568 }
4569
4570 /******************************************************************************
4571  * amdgpu_display_funcs functions
4572  *****************************************************************************/
4573
4574 /*
4575  * dm_bandwidth_update - program display watermarks
4576  *
4577  * @adev: amdgpu_device pointer
4578  *
4579  * Calculate and program the display watermarks and line buffer allocation.
4580  */
4581 static void dm_bandwidth_update(struct amdgpu_device *adev)
4582 {
4583         /* TODO: implement later */
4584 }
4585
4586 static const struct amdgpu_display_funcs dm_display_funcs = {
4587         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4588         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4589         .backlight_set_level = NULL, /* never called for DC */
4590         .backlight_get_level = NULL, /* never called for DC */
4591         .hpd_sense = NULL,/* called unconditionally */
4592         .hpd_set_polarity = NULL, /* called unconditionally */
4593         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4594         .page_flip_get_scanoutpos =
4595                 dm_crtc_get_scanoutpos,/* called unconditionally */
4596         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4597         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4598 };
4599
4600 #if defined(CONFIG_DEBUG_KERNEL_DC)
4601
4602 static ssize_t s3_debug_store(struct device *device,
4603                               struct device_attribute *attr,
4604                               const char *buf,
4605                               size_t count)
4606 {
4607         int ret;
4608         int s3_state;
4609         struct drm_device *drm_dev = dev_get_drvdata(device);
4610         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4611
4612         ret = kstrtoint(buf, 0, &s3_state);
4613
4614         if (ret == 0) {
4615                 if (s3_state) {
4616                         dm_resume(adev);
4617                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4618                 } else
4619                         dm_suspend(adev);
4620         }
4621
4622         return ret == 0 ? count : 0;
4623 }
4624
4625 DEVICE_ATTR_WO(s3_debug);
4626
4627 #endif
4628
4629 static int dm_init_microcode(struct amdgpu_device *adev)
4630 {
4631         char *fw_name_dmub;
4632         int r;
4633
4634         switch (adev->ip_versions[DCE_HWIP][0]) {
4635         case IP_VERSION(2, 1, 0):
4636                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4637                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4638                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4639                 break;
4640         case IP_VERSION(3, 0, 0):
4641                 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4642                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4643                 else
4644                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4645                 break;
4646         case IP_VERSION(3, 0, 1):
4647                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4648                 break;
4649         case IP_VERSION(3, 0, 2):
4650                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4651                 break;
4652         case IP_VERSION(3, 0, 3):
4653                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4654                 break;
4655         case IP_VERSION(3, 1, 2):
4656         case IP_VERSION(3, 1, 3):
4657                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4658                 break;
4659         case IP_VERSION(3, 1, 4):
4660                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4661                 break;
4662         case IP_VERSION(3, 1, 5):
4663                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4664                 break;
4665         case IP_VERSION(3, 1, 6):
4666                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4667                 break;
4668         case IP_VERSION(3, 2, 0):
4669                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4670                 break;
4671         case IP_VERSION(3, 2, 1):
4672                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4673                 break;
4674         default:
4675                 /* ASIC doesn't support DMUB. */
4676                 return 0;
4677         }
4678         r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4679         if (r)
4680                 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4681         return r;
4682 }
4683
4684 static int dm_early_init(void *handle)
4685 {
4686         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4687         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4688         struct atom_context *ctx = mode_info->atom_context;
4689         int index = GetIndexIntoMasterTable(DATA, Object_Header);
4690         u16 data_offset;
4691
4692         /* if there is no object header, skip DM */
4693         if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4694                 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4695                 dev_info(adev->dev, "No object header, skipping DM\n");
4696                 return -ENOENT;
4697         }
4698
4699         switch (adev->asic_type) {
4700 #if defined(CONFIG_DRM_AMD_DC_SI)
4701         case CHIP_TAHITI:
4702         case CHIP_PITCAIRN:
4703         case CHIP_VERDE:
4704                 adev->mode_info.num_crtc = 6;
4705                 adev->mode_info.num_hpd = 6;
4706                 adev->mode_info.num_dig = 6;
4707                 break;
4708         case CHIP_OLAND:
4709                 adev->mode_info.num_crtc = 2;
4710                 adev->mode_info.num_hpd = 2;
4711                 adev->mode_info.num_dig = 2;
4712                 break;
4713 #endif
4714         case CHIP_BONAIRE:
4715         case CHIP_HAWAII:
4716                 adev->mode_info.num_crtc = 6;
4717                 adev->mode_info.num_hpd = 6;
4718                 adev->mode_info.num_dig = 6;
4719                 break;
4720         case CHIP_KAVERI:
4721                 adev->mode_info.num_crtc = 4;
4722                 adev->mode_info.num_hpd = 6;
4723                 adev->mode_info.num_dig = 7;
4724                 break;
4725         case CHIP_KABINI:
4726         case CHIP_MULLINS:
4727                 adev->mode_info.num_crtc = 2;
4728                 adev->mode_info.num_hpd = 6;
4729                 adev->mode_info.num_dig = 6;
4730                 break;
4731         case CHIP_FIJI:
4732         case CHIP_TONGA:
4733                 adev->mode_info.num_crtc = 6;
4734                 adev->mode_info.num_hpd = 6;
4735                 adev->mode_info.num_dig = 7;
4736                 break;
4737         case CHIP_CARRIZO:
4738                 adev->mode_info.num_crtc = 3;
4739                 adev->mode_info.num_hpd = 6;
4740                 adev->mode_info.num_dig = 9;
4741                 break;
4742         case CHIP_STONEY:
4743                 adev->mode_info.num_crtc = 2;
4744                 adev->mode_info.num_hpd = 6;
4745                 adev->mode_info.num_dig = 9;
4746                 break;
4747         case CHIP_POLARIS11:
4748         case CHIP_POLARIS12:
4749                 adev->mode_info.num_crtc = 5;
4750                 adev->mode_info.num_hpd = 5;
4751                 adev->mode_info.num_dig = 5;
4752                 break;
4753         case CHIP_POLARIS10:
4754         case CHIP_VEGAM:
4755                 adev->mode_info.num_crtc = 6;
4756                 adev->mode_info.num_hpd = 6;
4757                 adev->mode_info.num_dig = 6;
4758                 break;
4759         case CHIP_VEGA10:
4760         case CHIP_VEGA12:
4761         case CHIP_VEGA20:
4762                 adev->mode_info.num_crtc = 6;
4763                 adev->mode_info.num_hpd = 6;
4764                 adev->mode_info.num_dig = 6;
4765                 break;
4766         default:
4767
4768                 switch (adev->ip_versions[DCE_HWIP][0]) {
4769                 case IP_VERSION(2, 0, 2):
4770                 case IP_VERSION(3, 0, 0):
4771                         adev->mode_info.num_crtc = 6;
4772                         adev->mode_info.num_hpd = 6;
4773                         adev->mode_info.num_dig = 6;
4774                         break;
4775                 case IP_VERSION(2, 0, 0):
4776                 case IP_VERSION(3, 0, 2):
4777                         adev->mode_info.num_crtc = 5;
4778                         adev->mode_info.num_hpd = 5;
4779                         adev->mode_info.num_dig = 5;
4780                         break;
4781                 case IP_VERSION(2, 0, 3):
4782                 case IP_VERSION(3, 0, 3):
4783                         adev->mode_info.num_crtc = 2;
4784                         adev->mode_info.num_hpd = 2;
4785                         adev->mode_info.num_dig = 2;
4786                         break;
4787                 case IP_VERSION(1, 0, 0):
4788                 case IP_VERSION(1, 0, 1):
4789                 case IP_VERSION(3, 0, 1):
4790                 case IP_VERSION(2, 1, 0):
4791                 case IP_VERSION(3, 1, 2):
4792                 case IP_VERSION(3, 1, 3):
4793                 case IP_VERSION(3, 1, 4):
4794                 case IP_VERSION(3, 1, 5):
4795                 case IP_VERSION(3, 1, 6):
4796                 case IP_VERSION(3, 2, 0):
4797                 case IP_VERSION(3, 2, 1):
4798                         adev->mode_info.num_crtc = 4;
4799                         adev->mode_info.num_hpd = 4;
4800                         adev->mode_info.num_dig = 4;
4801                         break;
4802                 default:
4803                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4804                                         adev->ip_versions[DCE_HWIP][0]);
4805                         return -EINVAL;
4806                 }
4807                 break;
4808         }
4809
4810         if (adev->mode_info.funcs == NULL)
4811                 adev->mode_info.funcs = &dm_display_funcs;
4812
4813         /*
4814          * Note: Do NOT change adev->audio_endpt_rreg and
4815          * adev->audio_endpt_wreg because they are initialised in
4816          * amdgpu_device_init()
4817          */
4818 #if defined(CONFIG_DEBUG_KERNEL_DC)
4819         device_create_file(
4820                 adev_to_drm(adev)->dev,
4821                 &dev_attr_s3_debug);
4822 #endif
4823         adev->dc_enabled = true;
4824
4825         return dm_init_microcode(adev);
4826 }
4827
4828 static bool modereset_required(struct drm_crtc_state *crtc_state)
4829 {
4830         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4831 }
4832
4833 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4834 {
4835         drm_encoder_cleanup(encoder);
4836         kfree(encoder);
4837 }
4838
4839 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4840         .destroy = amdgpu_dm_encoder_destroy,
4841 };
4842
4843 static int
4844 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4845                             const enum surface_pixel_format format,
4846                             enum dc_color_space *color_space)
4847 {
4848         bool full_range;
4849
4850         *color_space = COLOR_SPACE_SRGB;
4851
4852         /* DRM color properties only affect non-RGB formats. */
4853         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4854                 return 0;
4855
4856         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4857
4858         switch (plane_state->color_encoding) {
4859         case DRM_COLOR_YCBCR_BT601:
4860                 if (full_range)
4861                         *color_space = COLOR_SPACE_YCBCR601;
4862                 else
4863                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4864                 break;
4865
4866         case DRM_COLOR_YCBCR_BT709:
4867                 if (full_range)
4868                         *color_space = COLOR_SPACE_YCBCR709;
4869                 else
4870                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4871                 break;
4872
4873         case DRM_COLOR_YCBCR_BT2020:
4874                 if (full_range)
4875                         *color_space = COLOR_SPACE_2020_YCBCR;
4876                 else
4877                         return -EINVAL;
4878                 break;
4879
4880         default:
4881                 return -EINVAL;
4882         }
4883
4884         return 0;
4885 }
4886
4887 static int
4888 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4889                             const struct drm_plane_state *plane_state,
4890                             const u64 tiling_flags,
4891                             struct dc_plane_info *plane_info,
4892                             struct dc_plane_address *address,
4893                             bool tmz_surface,
4894                             bool force_disable_dcc)
4895 {
4896         const struct drm_framebuffer *fb = plane_state->fb;
4897         const struct amdgpu_framebuffer *afb =
4898                 to_amdgpu_framebuffer(plane_state->fb);
4899         int ret;
4900
4901         memset(plane_info, 0, sizeof(*plane_info));
4902
4903         switch (fb->format->format) {
4904         case DRM_FORMAT_C8:
4905                 plane_info->format =
4906                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4907                 break;
4908         case DRM_FORMAT_RGB565:
4909                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4910                 break;
4911         case DRM_FORMAT_XRGB8888:
4912         case DRM_FORMAT_ARGB8888:
4913                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4914                 break;
4915         case DRM_FORMAT_XRGB2101010:
4916         case DRM_FORMAT_ARGB2101010:
4917                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4918                 break;
4919         case DRM_FORMAT_XBGR2101010:
4920         case DRM_FORMAT_ABGR2101010:
4921                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4922                 break;
4923         case DRM_FORMAT_XBGR8888:
4924         case DRM_FORMAT_ABGR8888:
4925                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4926                 break;
4927         case DRM_FORMAT_NV21:
4928                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4929                 break;
4930         case DRM_FORMAT_NV12:
4931                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4932                 break;
4933         case DRM_FORMAT_P010:
4934                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4935                 break;
4936         case DRM_FORMAT_XRGB16161616F:
4937         case DRM_FORMAT_ARGB16161616F:
4938                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4939                 break;
4940         case DRM_FORMAT_XBGR16161616F:
4941         case DRM_FORMAT_ABGR16161616F:
4942                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4943                 break;
4944         case DRM_FORMAT_XRGB16161616:
4945         case DRM_FORMAT_ARGB16161616:
4946                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4947                 break;
4948         case DRM_FORMAT_XBGR16161616:
4949         case DRM_FORMAT_ABGR16161616:
4950                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4951                 break;
4952         default:
4953                 DRM_ERROR(
4954                         "Unsupported screen format %p4cc\n",
4955                         &fb->format->format);
4956                 return -EINVAL;
4957         }
4958
4959         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4960         case DRM_MODE_ROTATE_0:
4961                 plane_info->rotation = ROTATION_ANGLE_0;
4962                 break;
4963         case DRM_MODE_ROTATE_90:
4964                 plane_info->rotation = ROTATION_ANGLE_90;
4965                 break;
4966         case DRM_MODE_ROTATE_180:
4967                 plane_info->rotation = ROTATION_ANGLE_180;
4968                 break;
4969         case DRM_MODE_ROTATE_270:
4970                 plane_info->rotation = ROTATION_ANGLE_270;
4971                 break;
4972         default:
4973                 plane_info->rotation = ROTATION_ANGLE_0;
4974                 break;
4975         }
4976
4977
4978         plane_info->visible = true;
4979         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4980
4981         plane_info->layer_index = plane_state->normalized_zpos;
4982
4983         ret = fill_plane_color_attributes(plane_state, plane_info->format,
4984                                           &plane_info->color_space);
4985         if (ret)
4986                 return ret;
4987
4988         ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
4989                                            plane_info->rotation, tiling_flags,
4990                                            &plane_info->tiling_info,
4991                                            &plane_info->plane_size,
4992                                            &plane_info->dcc, address,
4993                                            tmz_surface, force_disable_dcc);
4994         if (ret)
4995                 return ret;
4996
4997         amdgpu_dm_plane_fill_blending_from_plane_state(
4998                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4999                 &plane_info->global_alpha, &plane_info->global_alpha_value);
5000
5001         return 0;
5002 }
5003
5004 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5005                                     struct dc_plane_state *dc_plane_state,
5006                                     struct drm_plane_state *plane_state,
5007                                     struct drm_crtc_state *crtc_state)
5008 {
5009         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5010         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5011         struct dc_scaling_info scaling_info;
5012         struct dc_plane_info plane_info;
5013         int ret;
5014         bool force_disable_dcc = false;
5015
5016         ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5017         if (ret)
5018                 return ret;
5019
5020         dc_plane_state->src_rect = scaling_info.src_rect;
5021         dc_plane_state->dst_rect = scaling_info.dst_rect;
5022         dc_plane_state->clip_rect = scaling_info.clip_rect;
5023         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5024
5025         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5026         ret = fill_dc_plane_info_and_addr(adev, plane_state,
5027                                           afb->tiling_flags,
5028                                           &plane_info,
5029                                           &dc_plane_state->address,
5030                                           afb->tmz_surface,
5031                                           force_disable_dcc);
5032         if (ret)
5033                 return ret;
5034
5035         dc_plane_state->format = plane_info.format;
5036         dc_plane_state->color_space = plane_info.color_space;
5037         dc_plane_state->format = plane_info.format;
5038         dc_plane_state->plane_size = plane_info.plane_size;
5039         dc_plane_state->rotation = plane_info.rotation;
5040         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5041         dc_plane_state->stereo_format = plane_info.stereo_format;
5042         dc_plane_state->tiling_info = plane_info.tiling_info;
5043         dc_plane_state->visible = plane_info.visible;
5044         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5045         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5046         dc_plane_state->global_alpha = plane_info.global_alpha;
5047         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5048         dc_plane_state->dcc = plane_info.dcc;
5049         dc_plane_state->layer_index = plane_info.layer_index;
5050         dc_plane_state->flip_int_enabled = true;
5051
5052         /*
5053          * Always set input transfer function, since plane state is refreshed
5054          * every time.
5055          */
5056         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5057         if (ret)
5058                 return ret;
5059
5060         return 0;
5061 }
5062
5063 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5064                                       struct rect *dirty_rect, int32_t x,
5065                                       s32 y, s32 width, s32 height,
5066                                       int *i, bool ffu)
5067 {
5068         if (*i > DC_MAX_DIRTY_RECTS)
5069                 return;
5070
5071         if (*i == DC_MAX_DIRTY_RECTS)
5072                 goto out;
5073
5074         dirty_rect->x = x;
5075         dirty_rect->y = y;
5076         dirty_rect->width = width;
5077         dirty_rect->height = height;
5078
5079         if (ffu)
5080                 drm_dbg(plane->dev,
5081                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5082                         plane->base.id, width, height);
5083         else
5084                 drm_dbg(plane->dev,
5085                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5086                         plane->base.id, x, y, width, height);
5087
5088 out:
5089         (*i)++;
5090 }
5091
5092 /**
5093  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5094  *
5095  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5096  *         remote fb
5097  * @old_plane_state: Old state of @plane
5098  * @new_plane_state: New state of @plane
5099  * @crtc_state: New state of CRTC connected to the @plane
5100  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5101  * @dirty_regions_changed: dirty regions changed
5102  *
5103  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5104  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5105  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5106  * amdgpu_dm's.
5107  *
5108  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5109  * plane with regions that require flushing to the eDP remote buffer. In
5110  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5111  * implicitly provide damage clips without any client support via the plane
5112  * bounds.
5113  */
5114 static void fill_dc_dirty_rects(struct drm_plane *plane,
5115                                 struct drm_plane_state *old_plane_state,
5116                                 struct drm_plane_state *new_plane_state,
5117                                 struct drm_crtc_state *crtc_state,
5118                                 struct dc_flip_addrs *flip_addrs,
5119                                 bool *dirty_regions_changed)
5120 {
5121         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5122         struct rect *dirty_rects = flip_addrs->dirty_rects;
5123         u32 num_clips;
5124         struct drm_mode_rect *clips;
5125         bool bb_changed;
5126         bool fb_changed;
5127         u32 i = 0;
5128         *dirty_regions_changed = false;
5129
5130         /*
5131          * Cursor plane has it's own dirty rect update interface. See
5132          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5133          */
5134         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5135                 return;
5136
5137         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5138         clips = drm_plane_get_damage_clips(new_plane_state);
5139
5140         if (!dm_crtc_state->mpo_requested) {
5141                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5142                         goto ffu;
5143
5144                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5145                         fill_dc_dirty_rect(new_plane_state->plane,
5146                                            &dirty_rects[flip_addrs->dirty_rect_count],
5147                                            clips->x1, clips->y1,
5148                                            clips->x2 - clips->x1, clips->y2 - clips->y1,
5149                                            &flip_addrs->dirty_rect_count,
5150                                            false);
5151                 return;
5152         }
5153
5154         /*
5155          * MPO is requested. Add entire plane bounding box to dirty rects if
5156          * flipped to or damaged.
5157          *
5158          * If plane is moved or resized, also add old bounding box to dirty
5159          * rects.
5160          */
5161         fb_changed = old_plane_state->fb->base.id !=
5162                      new_plane_state->fb->base.id;
5163         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5164                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
5165                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
5166                       old_plane_state->crtc_h != new_plane_state->crtc_h);
5167
5168         drm_dbg(plane->dev,
5169                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5170                 new_plane_state->plane->base.id,
5171                 bb_changed, fb_changed, num_clips);
5172
5173         *dirty_regions_changed = bb_changed;
5174
5175         if (bb_changed) {
5176                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5177                                    new_plane_state->crtc_x,
5178                                    new_plane_state->crtc_y,
5179                                    new_plane_state->crtc_w,
5180                                    new_plane_state->crtc_h, &i, false);
5181
5182                 /* Add old plane bounding-box if plane is moved or resized */
5183                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5184                                    old_plane_state->crtc_x,
5185                                    old_plane_state->crtc_y,
5186                                    old_plane_state->crtc_w,
5187                                    old_plane_state->crtc_h, &i, false);
5188         }
5189
5190         if (num_clips) {
5191                 for (; i < num_clips; clips++)
5192                         fill_dc_dirty_rect(new_plane_state->plane,
5193                                            &dirty_rects[i], clips->x1,
5194                                            clips->y1, clips->x2 - clips->x1,
5195                                            clips->y2 - clips->y1, &i, false);
5196         } else if (fb_changed && !bb_changed) {
5197                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5198                                    new_plane_state->crtc_x,
5199                                    new_plane_state->crtc_y,
5200                                    new_plane_state->crtc_w,
5201                                    new_plane_state->crtc_h, &i, false);
5202         }
5203
5204         if (i > DC_MAX_DIRTY_RECTS)
5205                 goto ffu;
5206
5207         flip_addrs->dirty_rect_count = i;
5208         return;
5209
5210 ffu:
5211         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5212                            dm_crtc_state->base.mode.crtc_hdisplay,
5213                            dm_crtc_state->base.mode.crtc_vdisplay,
5214                            &flip_addrs->dirty_rect_count, true);
5215 }
5216
5217 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5218                                            const struct dm_connector_state *dm_state,
5219                                            struct dc_stream_state *stream)
5220 {
5221         enum amdgpu_rmx_type rmx_type;
5222
5223         struct rect src = { 0 }; /* viewport in composition space*/
5224         struct rect dst = { 0 }; /* stream addressable area */
5225
5226         /* no mode. nothing to be done */
5227         if (!mode)
5228                 return;
5229
5230         /* Full screen scaling by default */
5231         src.width = mode->hdisplay;
5232         src.height = mode->vdisplay;
5233         dst.width = stream->timing.h_addressable;
5234         dst.height = stream->timing.v_addressable;
5235
5236         if (dm_state) {
5237                 rmx_type = dm_state->scaling;
5238                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5239                         if (src.width * dst.height <
5240                                         src.height * dst.width) {
5241                                 /* height needs less upscaling/more downscaling */
5242                                 dst.width = src.width *
5243                                                 dst.height / src.height;
5244                         } else {
5245                                 /* width needs less upscaling/more downscaling */
5246                                 dst.height = src.height *
5247                                                 dst.width / src.width;
5248                         }
5249                 } else if (rmx_type == RMX_CENTER) {
5250                         dst = src;
5251                 }
5252
5253                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5254                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5255
5256                 if (dm_state->underscan_enable) {
5257                         dst.x += dm_state->underscan_hborder / 2;
5258                         dst.y += dm_state->underscan_vborder / 2;
5259                         dst.width -= dm_state->underscan_hborder;
5260                         dst.height -= dm_state->underscan_vborder;
5261                 }
5262         }
5263
5264         stream->src = src;
5265         stream->dst = dst;
5266
5267         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5268                       dst.x, dst.y, dst.width, dst.height);
5269
5270 }
5271
5272 static enum dc_color_depth
5273 convert_color_depth_from_display_info(const struct drm_connector *connector,
5274                                       bool is_y420, int requested_bpc)
5275 {
5276         u8 bpc;
5277
5278         if (is_y420) {
5279                 bpc = 8;
5280
5281                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5282                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5283                         bpc = 16;
5284                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5285                         bpc = 12;
5286                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5287                         bpc = 10;
5288         } else {
5289                 bpc = (uint8_t)connector->display_info.bpc;
5290                 /* Assume 8 bpc by default if no bpc is specified. */
5291                 bpc = bpc ? bpc : 8;
5292         }
5293
5294         if (requested_bpc > 0) {
5295                 /*
5296                  * Cap display bpc based on the user requested value.
5297                  *
5298                  * The value for state->max_bpc may not correctly updated
5299                  * depending on when the connector gets added to the state
5300                  * or if this was called outside of atomic check, so it
5301                  * can't be used directly.
5302                  */
5303                 bpc = min_t(u8, bpc, requested_bpc);
5304
5305                 /* Round down to the nearest even number. */
5306                 bpc = bpc - (bpc & 1);
5307         }
5308
5309         switch (bpc) {
5310         case 0:
5311                 /*
5312                  * Temporary Work around, DRM doesn't parse color depth for
5313                  * EDID revision before 1.4
5314                  * TODO: Fix edid parsing
5315                  */
5316                 return COLOR_DEPTH_888;
5317         case 6:
5318                 return COLOR_DEPTH_666;
5319         case 8:
5320                 return COLOR_DEPTH_888;
5321         case 10:
5322                 return COLOR_DEPTH_101010;
5323         case 12:
5324                 return COLOR_DEPTH_121212;
5325         case 14:
5326                 return COLOR_DEPTH_141414;
5327         case 16:
5328                 return COLOR_DEPTH_161616;
5329         default:
5330                 return COLOR_DEPTH_UNDEFINED;
5331         }
5332 }
5333
5334 static enum dc_aspect_ratio
5335 get_aspect_ratio(const struct drm_display_mode *mode_in)
5336 {
5337         /* 1-1 mapping, since both enums follow the HDMI spec. */
5338         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5339 }
5340
5341 static enum dc_color_space
5342 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5343 {
5344         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5345
5346         switch (dc_crtc_timing->pixel_encoding) {
5347         case PIXEL_ENCODING_YCBCR422:
5348         case PIXEL_ENCODING_YCBCR444:
5349         case PIXEL_ENCODING_YCBCR420:
5350         {
5351                 /*
5352                  * 27030khz is the separation point between HDTV and SDTV
5353                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5354                  * respectively
5355                  */
5356                 if (dc_crtc_timing->pix_clk_100hz > 270300) {
5357                         if (dc_crtc_timing->flags.Y_ONLY)
5358                                 color_space =
5359                                         COLOR_SPACE_YCBCR709_LIMITED;
5360                         else
5361                                 color_space = COLOR_SPACE_YCBCR709;
5362                 } else {
5363                         if (dc_crtc_timing->flags.Y_ONLY)
5364                                 color_space =
5365                                         COLOR_SPACE_YCBCR601_LIMITED;
5366                         else
5367                                 color_space = COLOR_SPACE_YCBCR601;
5368                 }
5369
5370         }
5371         break;
5372         case PIXEL_ENCODING_RGB:
5373                 color_space = COLOR_SPACE_SRGB;
5374                 break;
5375
5376         default:
5377                 WARN_ON(1);
5378                 break;
5379         }
5380
5381         return color_space;
5382 }
5383
5384 static bool adjust_colour_depth_from_display_info(
5385         struct dc_crtc_timing *timing_out,
5386         const struct drm_display_info *info)
5387 {
5388         enum dc_color_depth depth = timing_out->display_color_depth;
5389         int normalized_clk;
5390         do {
5391                 normalized_clk = timing_out->pix_clk_100hz / 10;
5392                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5393                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5394                         normalized_clk /= 2;
5395                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5396                 switch (depth) {
5397                 case COLOR_DEPTH_888:
5398                         break;
5399                 case COLOR_DEPTH_101010:
5400                         normalized_clk = (normalized_clk * 30) / 24;
5401                         break;
5402                 case COLOR_DEPTH_121212:
5403                         normalized_clk = (normalized_clk * 36) / 24;
5404                         break;
5405                 case COLOR_DEPTH_161616:
5406                         normalized_clk = (normalized_clk * 48) / 24;
5407                         break;
5408                 default:
5409                         /* The above depths are the only ones valid for HDMI. */
5410                         return false;
5411                 }
5412                 if (normalized_clk <= info->max_tmds_clock) {
5413                         timing_out->display_color_depth = depth;
5414                         return true;
5415                 }
5416         } while (--depth > COLOR_DEPTH_666);
5417         return false;
5418 }
5419
5420 static void fill_stream_properties_from_drm_display_mode(
5421         struct dc_stream_state *stream,
5422         const struct drm_display_mode *mode_in,
5423         const struct drm_connector *connector,
5424         const struct drm_connector_state *connector_state,
5425         const struct dc_stream_state *old_stream,
5426         int requested_bpc)
5427 {
5428         struct dc_crtc_timing *timing_out = &stream->timing;
5429         const struct drm_display_info *info = &connector->display_info;
5430         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5431         struct hdmi_vendor_infoframe hv_frame;
5432         struct hdmi_avi_infoframe avi_frame;
5433
5434         memset(&hv_frame, 0, sizeof(hv_frame));
5435         memset(&avi_frame, 0, sizeof(avi_frame));
5436
5437         timing_out->h_border_left = 0;
5438         timing_out->h_border_right = 0;
5439         timing_out->v_border_top = 0;
5440         timing_out->v_border_bottom = 0;
5441         /* TODO: un-hardcode */
5442         if (drm_mode_is_420_only(info, mode_in)
5443                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5444                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5445         else if (drm_mode_is_420_also(info, mode_in)
5446                         && aconnector->force_yuv420_output)
5447                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5448         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5449                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5450                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5451         else
5452                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5453
5454         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5455         timing_out->display_color_depth = convert_color_depth_from_display_info(
5456                 connector,
5457                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5458                 requested_bpc);
5459         timing_out->scan_type = SCANNING_TYPE_NODATA;
5460         timing_out->hdmi_vic = 0;
5461
5462         if (old_stream) {
5463                 timing_out->vic = old_stream->timing.vic;
5464                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5465                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5466         } else {
5467                 timing_out->vic = drm_match_cea_mode(mode_in);
5468                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5469                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5470                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5471                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5472         }
5473
5474         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5475                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5476                 timing_out->vic = avi_frame.video_code;
5477                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5478                 timing_out->hdmi_vic = hv_frame.vic;
5479         }
5480
5481         if (is_freesync_video_mode(mode_in, aconnector)) {
5482                 timing_out->h_addressable = mode_in->hdisplay;
5483                 timing_out->h_total = mode_in->htotal;
5484                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5485                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5486                 timing_out->v_total = mode_in->vtotal;
5487                 timing_out->v_addressable = mode_in->vdisplay;
5488                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5489                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5490                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5491         } else {
5492                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5493                 timing_out->h_total = mode_in->crtc_htotal;
5494                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5495                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5496                 timing_out->v_total = mode_in->crtc_vtotal;
5497                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5498                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5499                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5500                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5501         }
5502
5503         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5504
5505         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5506         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5507         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5508                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5509                     drm_mode_is_420_also(info, mode_in) &&
5510                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5511                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5512                         adjust_colour_depth_from_display_info(timing_out, info);
5513                 }
5514         }
5515
5516         stream->output_color_space = get_output_color_space(timing_out);
5517 }
5518
5519 static void fill_audio_info(struct audio_info *audio_info,
5520                             const struct drm_connector *drm_connector,
5521                             const struct dc_sink *dc_sink)
5522 {
5523         int i = 0;
5524         int cea_revision = 0;
5525         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5526
5527         audio_info->manufacture_id = edid_caps->manufacturer_id;
5528         audio_info->product_id = edid_caps->product_id;
5529
5530         cea_revision = drm_connector->display_info.cea_rev;
5531
5532         strscpy(audio_info->display_name,
5533                 edid_caps->display_name,
5534                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5535
5536         if (cea_revision >= 3) {
5537                 audio_info->mode_count = edid_caps->audio_mode_count;
5538
5539                 for (i = 0; i < audio_info->mode_count; ++i) {
5540                         audio_info->modes[i].format_code =
5541                                         (enum audio_format_code)
5542                                         (edid_caps->audio_modes[i].format_code);
5543                         audio_info->modes[i].channel_count =
5544                                         edid_caps->audio_modes[i].channel_count;
5545                         audio_info->modes[i].sample_rates.all =
5546                                         edid_caps->audio_modes[i].sample_rate;
5547                         audio_info->modes[i].sample_size =
5548                                         edid_caps->audio_modes[i].sample_size;
5549                 }
5550         }
5551
5552         audio_info->flags.all = edid_caps->speaker_flags;
5553
5554         /* TODO: We only check for the progressive mode, check for interlace mode too */
5555         if (drm_connector->latency_present[0]) {
5556                 audio_info->video_latency = drm_connector->video_latency[0];
5557                 audio_info->audio_latency = drm_connector->audio_latency[0];
5558         }
5559
5560         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5561
5562 }
5563
5564 static void
5565 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5566                                       struct drm_display_mode *dst_mode)
5567 {
5568         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5569         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5570         dst_mode->crtc_clock = src_mode->crtc_clock;
5571         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5572         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5573         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5574         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5575         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5576         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5577         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5578         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5579         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5580         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5581         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5582 }
5583
5584 static void
5585 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5586                                         const struct drm_display_mode *native_mode,
5587                                         bool scale_enabled)
5588 {
5589         if (scale_enabled) {
5590                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5591         } else if (native_mode->clock == drm_mode->clock &&
5592                         native_mode->htotal == drm_mode->htotal &&
5593                         native_mode->vtotal == drm_mode->vtotal) {
5594                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5595         } else {
5596                 /* no scaling nor amdgpu inserted, no need to patch */
5597         }
5598 }
5599
5600 static struct dc_sink *
5601 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5602 {
5603         struct dc_sink_init_data sink_init_data = { 0 };
5604         struct dc_sink *sink = NULL;
5605         sink_init_data.link = aconnector->dc_link;
5606         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5607
5608         sink = dc_sink_create(&sink_init_data);
5609         if (!sink) {
5610                 DRM_ERROR("Failed to create sink!\n");
5611                 return NULL;
5612         }
5613         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5614
5615         return sink;
5616 }
5617
5618 static void set_multisync_trigger_params(
5619                 struct dc_stream_state *stream)
5620 {
5621         struct dc_stream_state *master = NULL;
5622
5623         if (stream->triggered_crtc_reset.enabled) {
5624                 master = stream->triggered_crtc_reset.event_source;
5625                 stream->triggered_crtc_reset.event =
5626                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5627                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5628                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5629         }
5630 }
5631
5632 static void set_master_stream(struct dc_stream_state *stream_set[],
5633                               int stream_count)
5634 {
5635         int j, highest_rfr = 0, master_stream = 0;
5636
5637         for (j = 0;  j < stream_count; j++) {
5638                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5639                         int refresh_rate = 0;
5640
5641                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5642                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5643                         if (refresh_rate > highest_rfr) {
5644                                 highest_rfr = refresh_rate;
5645                                 master_stream = j;
5646                         }
5647                 }
5648         }
5649         for (j = 0;  j < stream_count; j++) {
5650                 if (stream_set[j])
5651                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5652         }
5653 }
5654
5655 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5656 {
5657         int i = 0;
5658         struct dc_stream_state *stream;
5659
5660         if (context->stream_count < 2)
5661                 return;
5662         for (i = 0; i < context->stream_count ; i++) {
5663                 if (!context->streams[i])
5664                         continue;
5665                 /*
5666                  * TODO: add a function to read AMD VSDB bits and set
5667                  * crtc_sync_master.multi_sync_enabled flag
5668                  * For now it's set to false
5669                  */
5670         }
5671
5672         set_master_stream(context->streams, context->stream_count);
5673
5674         for (i = 0; i < context->stream_count ; i++) {
5675                 stream = context->streams[i];
5676
5677                 if (!stream)
5678                         continue;
5679
5680                 set_multisync_trigger_params(stream);
5681         }
5682 }
5683
5684 /**
5685  * DOC: FreeSync Video
5686  *
5687  * When a userspace application wants to play a video, the content follows a
5688  * standard format definition that usually specifies the FPS for that format.
5689  * The below list illustrates some video format and the expected FPS,
5690  * respectively:
5691  *
5692  * - TV/NTSC (23.976 FPS)
5693  * - Cinema (24 FPS)
5694  * - TV/PAL (25 FPS)
5695  * - TV/NTSC (29.97 FPS)
5696  * - TV/NTSC (30 FPS)
5697  * - Cinema HFR (48 FPS)
5698  * - TV/PAL (50 FPS)
5699  * - Commonly used (60 FPS)
5700  * - Multiples of 24 (48,72,96 FPS)
5701  *
5702  * The list of standards video format is not huge and can be added to the
5703  * connector modeset list beforehand. With that, userspace can leverage
5704  * FreeSync to extends the front porch in order to attain the target refresh
5705  * rate. Such a switch will happen seamlessly, without screen blanking or
5706  * reprogramming of the output in any other way. If the userspace requests a
5707  * modesetting change compatible with FreeSync modes that only differ in the
5708  * refresh rate, DC will skip the full update and avoid blink during the
5709  * transition. For example, the video player can change the modesetting from
5710  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5711  * causing any display blink. This same concept can be applied to a mode
5712  * setting change.
5713  */
5714 static struct drm_display_mode *
5715 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5716                 bool use_probed_modes)
5717 {
5718         struct drm_display_mode *m, *m_pref = NULL;
5719         u16 current_refresh, highest_refresh;
5720         struct list_head *list_head = use_probed_modes ?
5721                 &aconnector->base.probed_modes :
5722                 &aconnector->base.modes;
5723
5724         if (aconnector->freesync_vid_base.clock != 0)
5725                 return &aconnector->freesync_vid_base;
5726
5727         /* Find the preferred mode */
5728         list_for_each_entry (m, list_head, head) {
5729                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5730                         m_pref = m;
5731                         break;
5732                 }
5733         }
5734
5735         if (!m_pref) {
5736                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5737                 m_pref = list_first_entry_or_null(
5738                                 &aconnector->base.modes, struct drm_display_mode, head);
5739                 if (!m_pref) {
5740                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5741                         return NULL;
5742                 }
5743         }
5744
5745         highest_refresh = drm_mode_vrefresh(m_pref);
5746
5747         /*
5748          * Find the mode with highest refresh rate with same resolution.
5749          * For some monitors, preferred mode is not the mode with highest
5750          * supported refresh rate.
5751          */
5752         list_for_each_entry (m, list_head, head) {
5753                 current_refresh  = drm_mode_vrefresh(m);
5754
5755                 if (m->hdisplay == m_pref->hdisplay &&
5756                     m->vdisplay == m_pref->vdisplay &&
5757                     highest_refresh < current_refresh) {
5758                         highest_refresh = current_refresh;
5759                         m_pref = m;
5760                 }
5761         }
5762
5763         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5764         return m_pref;
5765 }
5766
5767 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5768                 struct amdgpu_dm_connector *aconnector)
5769 {
5770         struct drm_display_mode *high_mode;
5771         int timing_diff;
5772
5773         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5774         if (!high_mode || !mode)
5775                 return false;
5776
5777         timing_diff = high_mode->vtotal - mode->vtotal;
5778
5779         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5780             high_mode->hdisplay != mode->hdisplay ||
5781             high_mode->vdisplay != mode->vdisplay ||
5782             high_mode->hsync_start != mode->hsync_start ||
5783             high_mode->hsync_end != mode->hsync_end ||
5784             high_mode->htotal != mode->htotal ||
5785             high_mode->hskew != mode->hskew ||
5786             high_mode->vscan != mode->vscan ||
5787             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5788             high_mode->vsync_end - mode->vsync_end != timing_diff)
5789                 return false;
5790         else
5791                 return true;
5792 }
5793
5794 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5795                             struct dc_sink *sink, struct dc_stream_state *stream,
5796                             struct dsc_dec_dpcd_caps *dsc_caps)
5797 {
5798         stream->timing.flags.DSC = 0;
5799         dsc_caps->is_dsc_supported = false;
5800
5801         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5802             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5803                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5804                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5805                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5806                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5807                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5808                                 dsc_caps);
5809         }
5810 }
5811
5812
5813 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5814                                     struct dc_sink *sink, struct dc_stream_state *stream,
5815                                     struct dsc_dec_dpcd_caps *dsc_caps,
5816                                     uint32_t max_dsc_target_bpp_limit_override)
5817 {
5818         const struct dc_link_settings *verified_link_cap = NULL;
5819         u32 link_bw_in_kbps;
5820         u32 edp_min_bpp_x16, edp_max_bpp_x16;
5821         struct dc *dc = sink->ctx->dc;
5822         struct dc_dsc_bw_range bw_range = {0};
5823         struct dc_dsc_config dsc_cfg = {0};
5824         struct dc_dsc_config_options dsc_options = {0};
5825
5826         dc_dsc_get_default_config_option(dc, &dsc_options);
5827         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5828
5829         verified_link_cap = dc_link_get_link_cap(stream->link);
5830         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5831         edp_min_bpp_x16 = 8 * 16;
5832         edp_max_bpp_x16 = 8 * 16;
5833
5834         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5835                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5836
5837         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5838                 edp_min_bpp_x16 = edp_max_bpp_x16;
5839
5840         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5841                                 dc->debug.dsc_min_slice_height_override,
5842                                 edp_min_bpp_x16, edp_max_bpp_x16,
5843                                 dsc_caps,
5844                                 &stream->timing,
5845                                 &bw_range)) {
5846
5847                 if (bw_range.max_kbps < link_bw_in_kbps) {
5848                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5849                                         dsc_caps,
5850                                         &dsc_options,
5851                                         0,
5852                                         &stream->timing,
5853                                         &dsc_cfg)) {
5854                                 stream->timing.dsc_cfg = dsc_cfg;
5855                                 stream->timing.flags.DSC = 1;
5856                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5857                         }
5858                         return;
5859                 }
5860         }
5861
5862         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5863                                 dsc_caps,
5864                                 &dsc_options,
5865                                 link_bw_in_kbps,
5866                                 &stream->timing,
5867                                 &dsc_cfg)) {
5868                 stream->timing.dsc_cfg = dsc_cfg;
5869                 stream->timing.flags.DSC = 1;
5870         }
5871 }
5872
5873
5874 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5875                                         struct dc_sink *sink, struct dc_stream_state *stream,
5876                                         struct dsc_dec_dpcd_caps *dsc_caps)
5877 {
5878         struct drm_connector *drm_connector = &aconnector->base;
5879         u32 link_bandwidth_kbps;
5880         struct dc *dc = sink->ctx->dc;
5881         u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5882         u32 dsc_max_supported_bw_in_kbps;
5883         u32 max_dsc_target_bpp_limit_override =
5884                 drm_connector->display_info.max_dsc_bpp;
5885         struct dc_dsc_config_options dsc_options = {0};
5886
5887         dc_dsc_get_default_config_option(dc, &dsc_options);
5888         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5889
5890         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5891                                                         dc_link_get_link_cap(aconnector->dc_link));
5892
5893         /* Set DSC policy according to dsc_clock_en */
5894         dc_dsc_policy_set_enable_dsc_when_not_needed(
5895                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5896
5897         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5898             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5899             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5900
5901                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5902
5903         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5904                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5905                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5906                                                 dsc_caps,
5907                                                 &dsc_options,
5908                                                 link_bandwidth_kbps,
5909                                                 &stream->timing,
5910                                                 &stream->timing.dsc_cfg)) {
5911                                 stream->timing.flags.DSC = 1;
5912                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5913                         }
5914                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5915                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5916                         max_supported_bw_in_kbps = link_bandwidth_kbps;
5917                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5918
5919                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5920                                         max_supported_bw_in_kbps > 0 &&
5921                                         dsc_max_supported_bw_in_kbps > 0)
5922                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5923                                                 dsc_caps,
5924                                                 &dsc_options,
5925                                                 dsc_max_supported_bw_in_kbps,
5926                                                 &stream->timing,
5927                                                 &stream->timing.dsc_cfg)) {
5928                                         stream->timing.flags.DSC = 1;
5929                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5930                                                                          __func__, drm_connector->name);
5931                                 }
5932                 }
5933         }
5934
5935         /* Overwrite the stream flag if DSC is enabled through debugfs */
5936         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5937                 stream->timing.flags.DSC = 1;
5938
5939         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5940                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5941
5942         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5943                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5944
5945         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5946                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5947 }
5948
5949 static struct dc_stream_state *
5950 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5951                        const struct drm_display_mode *drm_mode,
5952                        const struct dm_connector_state *dm_state,
5953                        const struct dc_stream_state *old_stream,
5954                        int requested_bpc)
5955 {
5956         struct drm_display_mode *preferred_mode = NULL;
5957         struct drm_connector *drm_connector;
5958         const struct drm_connector_state *con_state =
5959                 dm_state ? &dm_state->base : NULL;
5960         struct dc_stream_state *stream = NULL;
5961         struct drm_display_mode mode;
5962         struct drm_display_mode saved_mode;
5963         struct drm_display_mode *freesync_mode = NULL;
5964         bool native_mode_found = false;
5965         bool recalculate_timing = false;
5966         bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5967         int mode_refresh;
5968         int preferred_refresh = 0;
5969         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
5970         struct dsc_dec_dpcd_caps dsc_caps;
5971
5972         struct dc_sink *sink = NULL;
5973
5974         drm_mode_init(&mode, drm_mode);
5975         memset(&saved_mode, 0, sizeof(saved_mode));
5976
5977         if (aconnector == NULL) {
5978                 DRM_ERROR("aconnector is NULL!\n");
5979                 return stream;
5980         }
5981
5982         drm_connector = &aconnector->base;
5983
5984         if (!aconnector->dc_sink) {
5985                 sink = create_fake_sink(aconnector);
5986                 if (!sink)
5987                         return stream;
5988         } else {
5989                 sink = aconnector->dc_sink;
5990                 dc_sink_retain(sink);
5991         }
5992
5993         stream = dc_create_stream_for_sink(sink);
5994
5995         if (stream == NULL) {
5996                 DRM_ERROR("Failed to create stream for sink!\n");
5997                 goto finish;
5998         }
5999
6000         stream->dm_stream_context = aconnector;
6001
6002         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6003                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
6004
6005         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
6006                 /* Search for preferred mode */
6007                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6008                         native_mode_found = true;
6009                         break;
6010                 }
6011         }
6012         if (!native_mode_found)
6013                 preferred_mode = list_first_entry_or_null(
6014                                 &aconnector->base.modes,
6015                                 struct drm_display_mode,
6016                                 head);
6017
6018         mode_refresh = drm_mode_vrefresh(&mode);
6019
6020         if (preferred_mode == NULL) {
6021                 /*
6022                  * This may not be an error, the use case is when we have no
6023                  * usermode calls to reset and set mode upon hotplug. In this
6024                  * case, we call set mode ourselves to restore the previous mode
6025                  * and the modelist may not be filled in in time.
6026                  */
6027                 DRM_DEBUG_DRIVER("No preferred mode found\n");
6028         } else {
6029                 recalculate_timing = amdgpu_freesync_vid_mode &&
6030                                  is_freesync_video_mode(&mode, aconnector);
6031                 if (recalculate_timing) {
6032                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6033                         drm_mode_copy(&saved_mode, &mode);
6034                         drm_mode_copy(&mode, freesync_mode);
6035                 } else {
6036                         decide_crtc_timing_for_drm_display_mode(
6037                                         &mode, preferred_mode, scale);
6038
6039                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
6040                 }
6041         }
6042
6043         if (recalculate_timing)
6044                 drm_mode_set_crtcinfo(&saved_mode, 0);
6045         else if (!dm_state)
6046                 drm_mode_set_crtcinfo(&mode, 0);
6047
6048         /*
6049         * If scaling is enabled and refresh rate didn't change
6050         * we copy the vic and polarities of the old timings
6051         */
6052         if (!scale || mode_refresh != preferred_refresh)
6053                 fill_stream_properties_from_drm_display_mode(
6054                         stream, &mode, &aconnector->base, con_state, NULL,
6055                         requested_bpc);
6056         else
6057                 fill_stream_properties_from_drm_display_mode(
6058                         stream, &mode, &aconnector->base, con_state, old_stream,
6059                         requested_bpc);
6060
6061         if (aconnector->timing_changed) {
6062                 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",
6063                                 __func__,
6064                                 stream->timing.display_color_depth,
6065                                 aconnector->timing_requested->display_color_depth);
6066                 stream->timing = *aconnector->timing_requested;
6067         }
6068
6069         /* SST DSC determination policy */
6070         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6071         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6072                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6073
6074         update_stream_scaling_settings(&mode, dm_state, stream);
6075
6076         fill_audio_info(
6077                 &stream->audio_info,
6078                 drm_connector,
6079                 sink);
6080
6081         update_stream_signal(stream, sink);
6082
6083         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6084                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6085
6086         if (stream->link->psr_settings.psr_feature_enabled) {
6087                 //
6088                 // should decide stream support vsc sdp colorimetry capability
6089                 // before building vsc info packet
6090                 //
6091                 stream->use_vsc_sdp_for_colorimetry = false;
6092                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6093                         stream->use_vsc_sdp_for_colorimetry =
6094                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6095                 } else {
6096                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6097                                 stream->use_vsc_sdp_for_colorimetry = true;
6098                 }
6099                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6100                         tf = TRANSFER_FUNC_GAMMA_22;
6101                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6102                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6103
6104         }
6105 finish:
6106         dc_sink_release(sink);
6107
6108         return stream;
6109 }
6110
6111 static enum drm_connector_status
6112 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6113 {
6114         bool connected;
6115         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6116
6117         /*
6118          * Notes:
6119          * 1. This interface is NOT called in context of HPD irq.
6120          * 2. This interface *is called* in context of user-mode ioctl. Which
6121          * makes it a bad place for *any* MST-related activity.
6122          */
6123
6124         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6125             !aconnector->fake_enable)
6126                 connected = (aconnector->dc_sink != NULL);
6127         else
6128                 connected = (aconnector->base.force == DRM_FORCE_ON ||
6129                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6130
6131         update_subconnector_property(aconnector);
6132
6133         return (connected ? connector_status_connected :
6134                         connector_status_disconnected);
6135 }
6136
6137 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6138                                             struct drm_connector_state *connector_state,
6139                                             struct drm_property *property,
6140                                             uint64_t val)
6141 {
6142         struct drm_device *dev = connector->dev;
6143         struct amdgpu_device *adev = drm_to_adev(dev);
6144         struct dm_connector_state *dm_old_state =
6145                 to_dm_connector_state(connector->state);
6146         struct dm_connector_state *dm_new_state =
6147                 to_dm_connector_state(connector_state);
6148
6149         int ret = -EINVAL;
6150
6151         if (property == dev->mode_config.scaling_mode_property) {
6152                 enum amdgpu_rmx_type rmx_type;
6153
6154                 switch (val) {
6155                 case DRM_MODE_SCALE_CENTER:
6156                         rmx_type = RMX_CENTER;
6157                         break;
6158                 case DRM_MODE_SCALE_ASPECT:
6159                         rmx_type = RMX_ASPECT;
6160                         break;
6161                 case DRM_MODE_SCALE_FULLSCREEN:
6162                         rmx_type = RMX_FULL;
6163                         break;
6164                 case DRM_MODE_SCALE_NONE:
6165                 default:
6166                         rmx_type = RMX_OFF;
6167                         break;
6168                 }
6169
6170                 if (dm_old_state->scaling == rmx_type)
6171                         return 0;
6172
6173                 dm_new_state->scaling = rmx_type;
6174                 ret = 0;
6175         } else if (property == adev->mode_info.underscan_hborder_property) {
6176                 dm_new_state->underscan_hborder = val;
6177                 ret = 0;
6178         } else if (property == adev->mode_info.underscan_vborder_property) {
6179                 dm_new_state->underscan_vborder = val;
6180                 ret = 0;
6181         } else if (property == adev->mode_info.underscan_property) {
6182                 dm_new_state->underscan_enable = val;
6183                 ret = 0;
6184         } else if (property == adev->mode_info.abm_level_property) {
6185                 dm_new_state->abm_level = val;
6186                 ret = 0;
6187         }
6188
6189         return ret;
6190 }
6191
6192 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6193                                             const struct drm_connector_state *state,
6194                                             struct drm_property *property,
6195                                             uint64_t *val)
6196 {
6197         struct drm_device *dev = connector->dev;
6198         struct amdgpu_device *adev = drm_to_adev(dev);
6199         struct dm_connector_state *dm_state =
6200                 to_dm_connector_state(state);
6201         int ret = -EINVAL;
6202
6203         if (property == dev->mode_config.scaling_mode_property) {
6204                 switch (dm_state->scaling) {
6205                 case RMX_CENTER:
6206                         *val = DRM_MODE_SCALE_CENTER;
6207                         break;
6208                 case RMX_ASPECT:
6209                         *val = DRM_MODE_SCALE_ASPECT;
6210                         break;
6211                 case RMX_FULL:
6212                         *val = DRM_MODE_SCALE_FULLSCREEN;
6213                         break;
6214                 case RMX_OFF:
6215                 default:
6216                         *val = DRM_MODE_SCALE_NONE;
6217                         break;
6218                 }
6219                 ret = 0;
6220         } else if (property == adev->mode_info.underscan_hborder_property) {
6221                 *val = dm_state->underscan_hborder;
6222                 ret = 0;
6223         } else if (property == adev->mode_info.underscan_vborder_property) {
6224                 *val = dm_state->underscan_vborder;
6225                 ret = 0;
6226         } else if (property == adev->mode_info.underscan_property) {
6227                 *val = dm_state->underscan_enable;
6228                 ret = 0;
6229         } else if (property == adev->mode_info.abm_level_property) {
6230                 *val = dm_state->abm_level;
6231                 ret = 0;
6232         }
6233
6234         return ret;
6235 }
6236
6237 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6238 {
6239         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6240
6241         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6242 }
6243
6244 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6245 {
6246         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6247         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6248         struct amdgpu_display_manager *dm = &adev->dm;
6249
6250         /*
6251          * Call only if mst_mgr was initialized before since it's not done
6252          * for all connector types.
6253          */
6254         if (aconnector->mst_mgr.dev)
6255                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6256
6257         if (aconnector->bl_idx != -1) {
6258                 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6259                 dm->backlight_dev[aconnector->bl_idx] = NULL;
6260         }
6261
6262         if (aconnector->dc_em_sink)
6263                 dc_sink_release(aconnector->dc_em_sink);
6264         aconnector->dc_em_sink = NULL;
6265         if (aconnector->dc_sink)
6266                 dc_sink_release(aconnector->dc_sink);
6267         aconnector->dc_sink = NULL;
6268
6269         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6270         drm_connector_unregister(connector);
6271         drm_connector_cleanup(connector);
6272         if (aconnector->i2c) {
6273                 i2c_del_adapter(&aconnector->i2c->base);
6274                 kfree(aconnector->i2c);
6275         }
6276         kfree(aconnector->dm_dp_aux.aux.name);
6277
6278         kfree(connector);
6279 }
6280
6281 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6282 {
6283         struct dm_connector_state *state =
6284                 to_dm_connector_state(connector->state);
6285
6286         if (connector->state)
6287                 __drm_atomic_helper_connector_destroy_state(connector->state);
6288
6289         kfree(state);
6290
6291         state = kzalloc(sizeof(*state), GFP_KERNEL);
6292
6293         if (state) {
6294                 state->scaling = RMX_OFF;
6295                 state->underscan_enable = false;
6296                 state->underscan_hborder = 0;
6297                 state->underscan_vborder = 0;
6298                 state->base.max_requested_bpc = 8;
6299                 state->vcpi_slots = 0;
6300                 state->pbn = 0;
6301
6302                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6303                         state->abm_level = amdgpu_dm_abm_level;
6304
6305                 __drm_atomic_helper_connector_reset(connector, &state->base);
6306         }
6307 }
6308
6309 struct drm_connector_state *
6310 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6311 {
6312         struct dm_connector_state *state =
6313                 to_dm_connector_state(connector->state);
6314
6315         struct dm_connector_state *new_state =
6316                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6317
6318         if (!new_state)
6319                 return NULL;
6320
6321         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6322
6323         new_state->freesync_capable = state->freesync_capable;
6324         new_state->abm_level = state->abm_level;
6325         new_state->scaling = state->scaling;
6326         new_state->underscan_enable = state->underscan_enable;
6327         new_state->underscan_hborder = state->underscan_hborder;
6328         new_state->underscan_vborder = state->underscan_vborder;
6329         new_state->vcpi_slots = state->vcpi_slots;
6330         new_state->pbn = state->pbn;
6331         return &new_state->base;
6332 }
6333
6334 static int
6335 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6336 {
6337         struct amdgpu_dm_connector *amdgpu_dm_connector =
6338                 to_amdgpu_dm_connector(connector);
6339         int r;
6340
6341         amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6342
6343         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6344             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6345                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6346                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6347                 if (r)
6348                         return r;
6349         }
6350
6351 #if defined(CONFIG_DEBUG_FS)
6352         connector_debugfs_init(amdgpu_dm_connector);
6353 #endif
6354
6355         return 0;
6356 }
6357
6358 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
6359 {
6360         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6361         struct dc_link *dc_link = aconnector->dc_link;
6362         struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
6363         struct edid *edid;
6364
6365         if (!connector->edid_override)
6366                 return;
6367
6368         drm_edid_override_connector_update(&aconnector->base);
6369         edid = aconnector->base.edid_blob_ptr->data;
6370         aconnector->edid = edid;
6371
6372         /* Update emulated (virtual) sink's EDID */
6373         if (dc_em_sink && dc_link) {
6374                 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
6375                 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH);
6376                 dm_helpers_parse_edid_caps(
6377                         dc_link,
6378                         &dc_em_sink->dc_edid,
6379                         &dc_em_sink->edid_caps);
6380         }
6381 }
6382
6383 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6384         .reset = amdgpu_dm_connector_funcs_reset,
6385         .detect = amdgpu_dm_connector_detect,
6386         .fill_modes = drm_helper_probe_single_connector_modes,
6387         .destroy = amdgpu_dm_connector_destroy,
6388         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6389         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6390         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6391         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6392         .late_register = amdgpu_dm_connector_late_register,
6393         .early_unregister = amdgpu_dm_connector_unregister,
6394         .force = amdgpu_dm_connector_funcs_force
6395 };
6396
6397 static int get_modes(struct drm_connector *connector)
6398 {
6399         return amdgpu_dm_connector_get_modes(connector);
6400 }
6401
6402 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6403 {
6404         struct dc_sink_init_data init_params = {
6405                         .link = aconnector->dc_link,
6406                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6407         };
6408         struct edid *edid;
6409
6410         if (!aconnector->base.edid_blob_ptr) {
6411                 /* if connector->edid_override valid, pass
6412                  * it to edid_override to edid_blob_ptr
6413                  */
6414
6415                 drm_edid_override_connector_update(&aconnector->base);
6416
6417                 if (!aconnector->base.edid_blob_ptr) {
6418                         DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6419                                         aconnector->base.name);
6420
6421                         aconnector->base.force = DRM_FORCE_OFF;
6422                         return;
6423                 }
6424         }
6425
6426         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6427
6428         aconnector->edid = edid;
6429
6430         aconnector->dc_em_sink = dc_link_add_remote_sink(
6431                 aconnector->dc_link,
6432                 (uint8_t *)edid,
6433                 (edid->extensions + 1) * EDID_LENGTH,
6434                 &init_params);
6435
6436         if (aconnector->base.force == DRM_FORCE_ON) {
6437                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6438                 aconnector->dc_link->local_sink :
6439                 aconnector->dc_em_sink;
6440                 dc_sink_retain(aconnector->dc_sink);
6441         }
6442 }
6443
6444 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6445 {
6446         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6447
6448         /*
6449          * In case of headless boot with force on for DP managed connector
6450          * Those settings have to be != 0 to get initial modeset
6451          */
6452         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6453                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6454                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6455         }
6456
6457         create_eml_sink(aconnector);
6458 }
6459
6460 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6461                                                 struct dc_stream_state *stream)
6462 {
6463         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6464         struct dc_plane_state *dc_plane_state = NULL;
6465         struct dc_state *dc_state = NULL;
6466
6467         if (!stream)
6468                 goto cleanup;
6469
6470         dc_plane_state = dc_create_plane_state(dc);
6471         if (!dc_plane_state)
6472                 goto cleanup;
6473
6474         dc_state = dc_create_state(dc);
6475         if (!dc_state)
6476                 goto cleanup;
6477
6478         /* populate stream to plane */
6479         dc_plane_state->src_rect.height  = stream->src.height;
6480         dc_plane_state->src_rect.width   = stream->src.width;
6481         dc_plane_state->dst_rect.height  = stream->src.height;
6482         dc_plane_state->dst_rect.width   = stream->src.width;
6483         dc_plane_state->clip_rect.height = stream->src.height;
6484         dc_plane_state->clip_rect.width  = stream->src.width;
6485         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6486         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6487         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6488         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6489         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6490         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6491         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6492         dc_plane_state->rotation = ROTATION_ANGLE_0;
6493         dc_plane_state->is_tiling_rotated = false;
6494         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6495
6496         dc_result = dc_validate_stream(dc, stream);
6497         if (dc_result == DC_OK)
6498                 dc_result = dc_validate_plane(dc, dc_plane_state);
6499
6500         if (dc_result == DC_OK)
6501                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6502
6503         if (dc_result == DC_OK && !dc_add_plane_to_context(
6504                                                 dc,
6505                                                 stream,
6506                                                 dc_plane_state,
6507                                                 dc_state))
6508                 dc_result = DC_FAIL_ATTACH_SURFACES;
6509
6510         if (dc_result == DC_OK)
6511                 dc_result = dc_validate_global_state(dc, dc_state, true);
6512
6513 cleanup:
6514         if (dc_state)
6515                 dc_release_state(dc_state);
6516
6517         if (dc_plane_state)
6518                 dc_plane_state_release(dc_plane_state);
6519
6520         return dc_result;
6521 }
6522
6523 struct dc_stream_state *
6524 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6525                                 const struct drm_display_mode *drm_mode,
6526                                 const struct dm_connector_state *dm_state,
6527                                 const struct dc_stream_state *old_stream)
6528 {
6529         struct drm_connector *connector = &aconnector->base;
6530         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6531         struct dc_stream_state *stream;
6532         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6533         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6534         enum dc_status dc_result = DC_OK;
6535
6536         do {
6537                 stream = create_stream_for_sink(aconnector, drm_mode,
6538                                                 dm_state, old_stream,
6539                                                 requested_bpc);
6540                 if (stream == NULL) {
6541                         DRM_ERROR("Failed to create stream for sink!\n");
6542                         break;
6543                 }
6544
6545                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6546                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6547                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6548
6549                 if (dc_result == DC_OK)
6550                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6551
6552                 if (dc_result != DC_OK) {
6553                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6554                                       drm_mode->hdisplay,
6555                                       drm_mode->vdisplay,
6556                                       drm_mode->clock,
6557                                       dc_result,
6558                                       dc_status_to_str(dc_result));
6559
6560                         dc_stream_release(stream);
6561                         stream = NULL;
6562                         requested_bpc -= 2; /* lower bpc to retry validation */
6563                 }
6564
6565         } while (stream == NULL && requested_bpc >= 6);
6566
6567         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6568                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6569
6570                 aconnector->force_yuv420_output = true;
6571                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6572                                                 dm_state, old_stream);
6573                 aconnector->force_yuv420_output = false;
6574         }
6575
6576         return stream;
6577 }
6578
6579 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6580                                    struct drm_display_mode *mode)
6581 {
6582         int result = MODE_ERROR;
6583         struct dc_sink *dc_sink;
6584         /* TODO: Unhardcode stream count */
6585         struct dc_stream_state *stream;
6586         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6587
6588         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6589                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6590                 return result;
6591
6592         /*
6593          * Only run this the first time mode_valid is called to initilialize
6594          * EDID mgmt
6595          */
6596         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6597                 !aconnector->dc_em_sink)
6598                 handle_edid_mgmt(aconnector);
6599
6600         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6601
6602         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6603                                 aconnector->base.force != DRM_FORCE_ON) {
6604                 DRM_ERROR("dc_sink is NULL!\n");
6605                 goto fail;
6606         }
6607
6608         stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6609         if (stream) {
6610                 dc_stream_release(stream);
6611                 result = MODE_OK;
6612         }
6613
6614 fail:
6615         /* TODO: error handling*/
6616         return result;
6617 }
6618
6619 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6620                                 struct dc_info_packet *out)
6621 {
6622         struct hdmi_drm_infoframe frame;
6623         unsigned char buf[30]; /* 26 + 4 */
6624         ssize_t len;
6625         int ret, i;
6626
6627         memset(out, 0, sizeof(*out));
6628
6629         if (!state->hdr_output_metadata)
6630                 return 0;
6631
6632         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6633         if (ret)
6634                 return ret;
6635
6636         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6637         if (len < 0)
6638                 return (int)len;
6639
6640         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6641         if (len != 30)
6642                 return -EINVAL;
6643
6644         /* Prepare the infopacket for DC. */
6645         switch (state->connector->connector_type) {
6646         case DRM_MODE_CONNECTOR_HDMIA:
6647                 out->hb0 = 0x87; /* type */
6648                 out->hb1 = 0x01; /* version */
6649                 out->hb2 = 0x1A; /* length */
6650                 out->sb[0] = buf[3]; /* checksum */
6651                 i = 1;
6652                 break;
6653
6654         case DRM_MODE_CONNECTOR_DisplayPort:
6655         case DRM_MODE_CONNECTOR_eDP:
6656                 out->hb0 = 0x00; /* sdp id, zero */
6657                 out->hb1 = 0x87; /* type */
6658                 out->hb2 = 0x1D; /* payload len - 1 */
6659                 out->hb3 = (0x13 << 2); /* sdp version */
6660                 out->sb[0] = 0x01; /* version */
6661                 out->sb[1] = 0x1A; /* length */
6662                 i = 2;
6663                 break;
6664
6665         default:
6666                 return -EINVAL;
6667         }
6668
6669         memcpy(&out->sb[i], &buf[4], 26);
6670         out->valid = true;
6671
6672         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6673                        sizeof(out->sb), false);
6674
6675         return 0;
6676 }
6677
6678 static int
6679 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6680                                  struct drm_atomic_state *state)
6681 {
6682         struct drm_connector_state *new_con_state =
6683                 drm_atomic_get_new_connector_state(state, conn);
6684         struct drm_connector_state *old_con_state =
6685                 drm_atomic_get_old_connector_state(state, conn);
6686         struct drm_crtc *crtc = new_con_state->crtc;
6687         struct drm_crtc_state *new_crtc_state;
6688         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6689         int ret;
6690
6691         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6692
6693         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6694                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6695                 if (ret < 0)
6696                         return ret;
6697         }
6698
6699         if (!crtc)
6700                 return 0;
6701
6702         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6703                 struct dc_info_packet hdr_infopacket;
6704
6705                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6706                 if (ret)
6707                         return ret;
6708
6709                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6710                 if (IS_ERR(new_crtc_state))
6711                         return PTR_ERR(new_crtc_state);
6712
6713                 /*
6714                  * DC considers the stream backends changed if the
6715                  * static metadata changes. Forcing the modeset also
6716                  * gives a simple way for userspace to switch from
6717                  * 8bpc to 10bpc when setting the metadata to enter
6718                  * or exit HDR.
6719                  *
6720                  * Changing the static metadata after it's been
6721                  * set is permissible, however. So only force a
6722                  * modeset if we're entering or exiting HDR.
6723                  */
6724                 new_crtc_state->mode_changed =
6725                         !old_con_state->hdr_output_metadata ||
6726                         !new_con_state->hdr_output_metadata;
6727         }
6728
6729         return 0;
6730 }
6731
6732 static const struct drm_connector_helper_funcs
6733 amdgpu_dm_connector_helper_funcs = {
6734         /*
6735          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6736          * modes will be filtered by drm_mode_validate_size(), and those modes
6737          * are missing after user start lightdm. So we need to renew modes list.
6738          * in get_modes call back, not just return the modes count
6739          */
6740         .get_modes = get_modes,
6741         .mode_valid = amdgpu_dm_connector_mode_valid,
6742         .atomic_check = amdgpu_dm_connector_atomic_check,
6743 };
6744
6745 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6746 {
6747
6748 }
6749
6750 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6751 {
6752         switch (display_color_depth) {
6753         case COLOR_DEPTH_666:
6754                 return 6;
6755         case COLOR_DEPTH_888:
6756                 return 8;
6757         case COLOR_DEPTH_101010:
6758                 return 10;
6759         case COLOR_DEPTH_121212:
6760                 return 12;
6761         case COLOR_DEPTH_141414:
6762                 return 14;
6763         case COLOR_DEPTH_161616:
6764                 return 16;
6765         default:
6766                 break;
6767         }
6768         return 0;
6769 }
6770
6771 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6772                                           struct drm_crtc_state *crtc_state,
6773                                           struct drm_connector_state *conn_state)
6774 {
6775         struct drm_atomic_state *state = crtc_state->state;
6776         struct drm_connector *connector = conn_state->connector;
6777         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6778         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6779         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6780         struct drm_dp_mst_topology_mgr *mst_mgr;
6781         struct drm_dp_mst_port *mst_port;
6782         struct drm_dp_mst_topology_state *mst_state;
6783         enum dc_color_depth color_depth;
6784         int clock, bpp = 0;
6785         bool is_y420 = false;
6786
6787         if (!aconnector->mst_output_port)
6788                 return 0;
6789
6790         mst_port = aconnector->mst_output_port;
6791         mst_mgr = &aconnector->mst_root->mst_mgr;
6792
6793         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6794                 return 0;
6795
6796         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6797         if (IS_ERR(mst_state))
6798                 return PTR_ERR(mst_state);
6799
6800         if (!mst_state->pbn_div)
6801                 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6802
6803         if (!state->duplicated) {
6804                 int max_bpc = conn_state->max_requested_bpc;
6805                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6806                           aconnector->force_yuv420_output;
6807                 color_depth = convert_color_depth_from_display_info(connector,
6808                                                                     is_y420,
6809                                                                     max_bpc);
6810                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6811                 clock = adjusted_mode->clock;
6812                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6813         }
6814
6815         dm_new_connector_state->vcpi_slots =
6816                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6817                                               dm_new_connector_state->pbn);
6818         if (dm_new_connector_state->vcpi_slots < 0) {
6819                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6820                 return dm_new_connector_state->vcpi_slots;
6821         }
6822         return 0;
6823 }
6824
6825 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6826         .disable = dm_encoder_helper_disable,
6827         .atomic_check = dm_encoder_helper_atomic_check
6828 };
6829
6830 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6831                                             struct dc_state *dc_state,
6832                                             struct dsc_mst_fairness_vars *vars)
6833 {
6834         struct dc_stream_state *stream = NULL;
6835         struct drm_connector *connector;
6836         struct drm_connector_state *new_con_state;
6837         struct amdgpu_dm_connector *aconnector;
6838         struct dm_connector_state *dm_conn_state;
6839         int i, j, ret;
6840         int vcpi, pbn_div, pbn, slot_num = 0;
6841
6842         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6843
6844                 aconnector = to_amdgpu_dm_connector(connector);
6845
6846                 if (!aconnector->mst_output_port)
6847                         continue;
6848
6849                 if (!new_con_state || !new_con_state->crtc)
6850                         continue;
6851
6852                 dm_conn_state = to_dm_connector_state(new_con_state);
6853
6854                 for (j = 0; j < dc_state->stream_count; j++) {
6855                         stream = dc_state->streams[j];
6856                         if (!stream)
6857                                 continue;
6858
6859                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6860                                 break;
6861
6862                         stream = NULL;
6863                 }
6864
6865                 if (!stream)
6866                         continue;
6867
6868                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6869                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6870                 for (j = 0; j < dc_state->stream_count; j++) {
6871                         if (vars[j].aconnector == aconnector) {
6872                                 pbn = vars[j].pbn;
6873                                 break;
6874                         }
6875                 }
6876
6877                 if (j == dc_state->stream_count)
6878                         continue;
6879
6880                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6881
6882                 if (stream->timing.flags.DSC != 1) {
6883                         dm_conn_state->pbn = pbn;
6884                         dm_conn_state->vcpi_slots = slot_num;
6885
6886                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6887                                                            dm_conn_state->pbn, false);
6888                         if (ret < 0)
6889                                 return ret;
6890
6891                         continue;
6892                 }
6893
6894                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
6895                 if (vcpi < 0)
6896                         return vcpi;
6897
6898                 dm_conn_state->pbn = pbn;
6899                 dm_conn_state->vcpi_slots = vcpi;
6900         }
6901         return 0;
6902 }
6903
6904 static int to_drm_connector_type(enum signal_type st)
6905 {
6906         switch (st) {
6907         case SIGNAL_TYPE_HDMI_TYPE_A:
6908                 return DRM_MODE_CONNECTOR_HDMIA;
6909         case SIGNAL_TYPE_EDP:
6910                 return DRM_MODE_CONNECTOR_eDP;
6911         case SIGNAL_TYPE_LVDS:
6912                 return DRM_MODE_CONNECTOR_LVDS;
6913         case SIGNAL_TYPE_RGB:
6914                 return DRM_MODE_CONNECTOR_VGA;
6915         case SIGNAL_TYPE_DISPLAY_PORT:
6916         case SIGNAL_TYPE_DISPLAY_PORT_MST:
6917                 return DRM_MODE_CONNECTOR_DisplayPort;
6918         case SIGNAL_TYPE_DVI_DUAL_LINK:
6919         case SIGNAL_TYPE_DVI_SINGLE_LINK:
6920                 return DRM_MODE_CONNECTOR_DVID;
6921         case SIGNAL_TYPE_VIRTUAL:
6922                 return DRM_MODE_CONNECTOR_VIRTUAL;
6923
6924         default:
6925                 return DRM_MODE_CONNECTOR_Unknown;
6926         }
6927 }
6928
6929 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6930 {
6931         struct drm_encoder *encoder;
6932
6933         /* There is only one encoder per connector */
6934         drm_connector_for_each_possible_encoder(connector, encoder)
6935                 return encoder;
6936
6937         return NULL;
6938 }
6939
6940 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6941 {
6942         struct drm_encoder *encoder;
6943         struct amdgpu_encoder *amdgpu_encoder;
6944
6945         encoder = amdgpu_dm_connector_to_encoder(connector);
6946
6947         if (encoder == NULL)
6948                 return;
6949
6950         amdgpu_encoder = to_amdgpu_encoder(encoder);
6951
6952         amdgpu_encoder->native_mode.clock = 0;
6953
6954         if (!list_empty(&connector->probed_modes)) {
6955                 struct drm_display_mode *preferred_mode = NULL;
6956
6957                 list_for_each_entry(preferred_mode,
6958                                     &connector->probed_modes,
6959                                     head) {
6960                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6961                                 amdgpu_encoder->native_mode = *preferred_mode;
6962
6963                         break;
6964                 }
6965
6966         }
6967 }
6968
6969 static struct drm_display_mode *
6970 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6971                              char *name,
6972                              int hdisplay, int vdisplay)
6973 {
6974         struct drm_device *dev = encoder->dev;
6975         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6976         struct drm_display_mode *mode = NULL;
6977         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6978
6979         mode = drm_mode_duplicate(dev, native_mode);
6980
6981         if (mode == NULL)
6982                 return NULL;
6983
6984         mode->hdisplay = hdisplay;
6985         mode->vdisplay = vdisplay;
6986         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6987         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6988
6989         return mode;
6990
6991 }
6992
6993 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6994                                                  struct drm_connector *connector)
6995 {
6996         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6997         struct drm_display_mode *mode = NULL;
6998         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6999         struct amdgpu_dm_connector *amdgpu_dm_connector =
7000                                 to_amdgpu_dm_connector(connector);
7001         int i;
7002         int n;
7003         struct mode_size {
7004                 char name[DRM_DISPLAY_MODE_LEN];
7005                 int w;
7006                 int h;
7007         } common_modes[] = {
7008                 {  "640x480",  640,  480},
7009                 {  "800x600",  800,  600},
7010                 { "1024x768", 1024,  768},
7011                 { "1280x720", 1280,  720},
7012                 { "1280x800", 1280,  800},
7013                 {"1280x1024", 1280, 1024},
7014                 { "1440x900", 1440,  900},
7015                 {"1680x1050", 1680, 1050},
7016                 {"1600x1200", 1600, 1200},
7017                 {"1920x1080", 1920, 1080},
7018                 {"1920x1200", 1920, 1200}
7019         };
7020
7021         n = ARRAY_SIZE(common_modes);
7022
7023         for (i = 0; i < n; i++) {
7024                 struct drm_display_mode *curmode = NULL;
7025                 bool mode_existed = false;
7026
7027                 if (common_modes[i].w > native_mode->hdisplay ||
7028                     common_modes[i].h > native_mode->vdisplay ||
7029                    (common_modes[i].w == native_mode->hdisplay &&
7030                     common_modes[i].h == native_mode->vdisplay))
7031                         continue;
7032
7033                 list_for_each_entry(curmode, &connector->probed_modes, head) {
7034                         if (common_modes[i].w == curmode->hdisplay &&
7035                             common_modes[i].h == curmode->vdisplay) {
7036                                 mode_existed = true;
7037                                 break;
7038                         }
7039                 }
7040
7041                 if (mode_existed)
7042                         continue;
7043
7044                 mode = amdgpu_dm_create_common_mode(encoder,
7045                                 common_modes[i].name, common_modes[i].w,
7046                                 common_modes[i].h);
7047                 if (!mode)
7048                         continue;
7049
7050                 drm_mode_probed_add(connector, mode);
7051                 amdgpu_dm_connector->num_modes++;
7052         }
7053 }
7054
7055 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7056 {
7057         struct drm_encoder *encoder;
7058         struct amdgpu_encoder *amdgpu_encoder;
7059         const struct drm_display_mode *native_mode;
7060
7061         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7062             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7063                 return;
7064
7065         mutex_lock(&connector->dev->mode_config.mutex);
7066         amdgpu_dm_connector_get_modes(connector);
7067         mutex_unlock(&connector->dev->mode_config.mutex);
7068
7069         encoder = amdgpu_dm_connector_to_encoder(connector);
7070         if (!encoder)
7071                 return;
7072
7073         amdgpu_encoder = to_amdgpu_encoder(encoder);
7074
7075         native_mode = &amdgpu_encoder->native_mode;
7076         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7077                 return;
7078
7079         drm_connector_set_panel_orientation_with_quirk(connector,
7080                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7081                                                        native_mode->hdisplay,
7082                                                        native_mode->vdisplay);
7083 }
7084
7085 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7086                                               struct edid *edid)
7087 {
7088         struct amdgpu_dm_connector *amdgpu_dm_connector =
7089                         to_amdgpu_dm_connector(connector);
7090
7091         if (edid) {
7092                 /* empty probed_modes */
7093                 INIT_LIST_HEAD(&connector->probed_modes);
7094                 amdgpu_dm_connector->num_modes =
7095                                 drm_add_edid_modes(connector, edid);
7096
7097                 /* sorting the probed modes before calling function
7098                  * amdgpu_dm_get_native_mode() since EDID can have
7099                  * more than one preferred mode. The modes that are
7100                  * later in the probed mode list could be of higher
7101                  * and preferred resolution. For example, 3840x2160
7102                  * resolution in base EDID preferred timing and 4096x2160
7103                  * preferred resolution in DID extension block later.
7104                  */
7105                 drm_mode_sort(&connector->probed_modes);
7106                 amdgpu_dm_get_native_mode(connector);
7107
7108                 /* Freesync capabilities are reset by calling
7109                  * drm_add_edid_modes() and need to be
7110                  * restored here.
7111                  */
7112                 amdgpu_dm_update_freesync_caps(connector, edid);
7113         } else {
7114                 amdgpu_dm_connector->num_modes = 0;
7115         }
7116 }
7117
7118 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7119                               struct drm_display_mode *mode)
7120 {
7121         struct drm_display_mode *m;
7122
7123         list_for_each_entry (m, &aconnector->base.probed_modes, head) {
7124                 if (drm_mode_equal(m, mode))
7125                         return true;
7126         }
7127
7128         return false;
7129 }
7130
7131 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7132 {
7133         const struct drm_display_mode *m;
7134         struct drm_display_mode *new_mode;
7135         uint i;
7136         u32 new_modes_count = 0;
7137
7138         /* Standard FPS values
7139          *
7140          * 23.976       - TV/NTSC
7141          * 24           - Cinema
7142          * 25           - TV/PAL
7143          * 29.97        - TV/NTSC
7144          * 30           - TV/NTSC
7145          * 48           - Cinema HFR
7146          * 50           - TV/PAL
7147          * 60           - Commonly used
7148          * 48,72,96,120 - Multiples of 24
7149          */
7150         static const u32 common_rates[] = {
7151                 23976, 24000, 25000, 29970, 30000,
7152                 48000, 50000, 60000, 72000, 96000, 120000
7153         };
7154
7155         /*
7156          * Find mode with highest refresh rate with the same resolution
7157          * as the preferred mode. Some monitors report a preferred mode
7158          * with lower resolution than the highest refresh rate supported.
7159          */
7160
7161         m = get_highest_refresh_rate_mode(aconnector, true);
7162         if (!m)
7163                 return 0;
7164
7165         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7166                 u64 target_vtotal, target_vtotal_diff;
7167                 u64 num, den;
7168
7169                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7170                         continue;
7171
7172                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7173                     common_rates[i] > aconnector->max_vfreq * 1000)
7174                         continue;
7175
7176                 num = (unsigned long long)m->clock * 1000 * 1000;
7177                 den = common_rates[i] * (unsigned long long)m->htotal;
7178                 target_vtotal = div_u64(num, den);
7179                 target_vtotal_diff = target_vtotal - m->vtotal;
7180
7181                 /* Check for illegal modes */
7182                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7183                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7184                     m->vtotal + target_vtotal_diff < m->vsync_end)
7185                         continue;
7186
7187                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7188                 if (!new_mode)
7189                         goto out;
7190
7191                 new_mode->vtotal += (u16)target_vtotal_diff;
7192                 new_mode->vsync_start += (u16)target_vtotal_diff;
7193                 new_mode->vsync_end += (u16)target_vtotal_diff;
7194                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7195                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7196
7197                 if (!is_duplicate_mode(aconnector, new_mode)) {
7198                         drm_mode_probed_add(&aconnector->base, new_mode);
7199                         new_modes_count += 1;
7200                 } else
7201                         drm_mode_destroy(aconnector->base.dev, new_mode);
7202         }
7203  out:
7204         return new_modes_count;
7205 }
7206
7207 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7208                                                    struct edid *edid)
7209 {
7210         struct amdgpu_dm_connector *amdgpu_dm_connector =
7211                 to_amdgpu_dm_connector(connector);
7212
7213         if (!(amdgpu_freesync_vid_mode && edid))
7214                 return;
7215
7216         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7217                 amdgpu_dm_connector->num_modes +=
7218                         add_fs_modes(amdgpu_dm_connector);
7219 }
7220
7221 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7222 {
7223         struct amdgpu_dm_connector *amdgpu_dm_connector =
7224                         to_amdgpu_dm_connector(connector);
7225         struct drm_encoder *encoder;
7226         struct edid *edid = amdgpu_dm_connector->edid;
7227         struct dc_link_settings *verified_link_cap =
7228                         &amdgpu_dm_connector->dc_link->verified_link_cap;
7229         const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7230
7231         encoder = amdgpu_dm_connector_to_encoder(connector);
7232
7233         if (!drm_edid_is_valid(edid)) {
7234                 amdgpu_dm_connector->num_modes =
7235                                 drm_add_modes_noedid(connector, 640, 480);
7236                 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7237                         amdgpu_dm_connector->num_modes +=
7238                                 drm_add_modes_noedid(connector, 1920, 1080);
7239         } else {
7240                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7241                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7242                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7243         }
7244         amdgpu_dm_fbc_init(connector);
7245
7246         return amdgpu_dm_connector->num_modes;
7247 }
7248
7249 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7250                                      struct amdgpu_dm_connector *aconnector,
7251                                      int connector_type,
7252                                      struct dc_link *link,
7253                                      int link_index)
7254 {
7255         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7256
7257         /*
7258          * Some of the properties below require access to state, like bpc.
7259          * Allocate some default initial connector state with our reset helper.
7260          */
7261         if (aconnector->base.funcs->reset)
7262                 aconnector->base.funcs->reset(&aconnector->base);
7263
7264         aconnector->connector_id = link_index;
7265         aconnector->bl_idx = -1;
7266         aconnector->dc_link = link;
7267         aconnector->base.interlace_allowed = false;
7268         aconnector->base.doublescan_allowed = false;
7269         aconnector->base.stereo_allowed = false;
7270         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7271         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7272         aconnector->audio_inst = -1;
7273         aconnector->pack_sdp_v1_3 = false;
7274         aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7275         memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7276         mutex_init(&aconnector->hpd_lock);
7277
7278         /*
7279          * configure support HPD hot plug connector_>polled default value is 0
7280          * which means HPD hot plug not supported
7281          */
7282         switch (connector_type) {
7283         case DRM_MODE_CONNECTOR_HDMIA:
7284                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7285                 aconnector->base.ycbcr_420_allowed =
7286                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7287                 break;
7288         case DRM_MODE_CONNECTOR_DisplayPort:
7289                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7290                 link->link_enc = link_enc_cfg_get_link_enc(link);
7291                 ASSERT(link->link_enc);
7292                 if (link->link_enc)
7293                         aconnector->base.ycbcr_420_allowed =
7294                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7295                 break;
7296         case DRM_MODE_CONNECTOR_DVID:
7297                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7298                 break;
7299         default:
7300                 break;
7301         }
7302
7303         drm_object_attach_property(&aconnector->base.base,
7304                                 dm->ddev->mode_config.scaling_mode_property,
7305                                 DRM_MODE_SCALE_NONE);
7306
7307         drm_object_attach_property(&aconnector->base.base,
7308                                 adev->mode_info.underscan_property,
7309                                 UNDERSCAN_OFF);
7310         drm_object_attach_property(&aconnector->base.base,
7311                                 adev->mode_info.underscan_hborder_property,
7312                                 0);
7313         drm_object_attach_property(&aconnector->base.base,
7314                                 adev->mode_info.underscan_vborder_property,
7315                                 0);
7316
7317         if (!aconnector->mst_root)
7318                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7319
7320         aconnector->base.state->max_bpc = 16;
7321         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7322
7323         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7324             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7325                 drm_object_attach_property(&aconnector->base.base,
7326                                 adev->mode_info.abm_level_property, 0);
7327         }
7328
7329         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7330             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7331             connector_type == DRM_MODE_CONNECTOR_eDP) {
7332                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7333
7334                 if (!aconnector->mst_root)
7335                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7336
7337                 if (adev->dm.hdcp_workqueue)
7338                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7339         }
7340 }
7341
7342 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7343                               struct i2c_msg *msgs, int num)
7344 {
7345         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7346         struct ddc_service *ddc_service = i2c->ddc_service;
7347         struct i2c_command cmd;
7348         int i;
7349         int result = -EIO;
7350
7351         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7352
7353         if (!cmd.payloads)
7354                 return result;
7355
7356         cmd.number_of_payloads = num;
7357         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7358         cmd.speed = 100;
7359
7360         for (i = 0; i < num; i++) {
7361                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7362                 cmd.payloads[i].address = msgs[i].addr;
7363                 cmd.payloads[i].length = msgs[i].len;
7364                 cmd.payloads[i].data = msgs[i].buf;
7365         }
7366
7367         if (dc_submit_i2c(
7368                         ddc_service->ctx->dc,
7369                         ddc_service->link->link_index,
7370                         &cmd))
7371                 result = num;
7372
7373         kfree(cmd.payloads);
7374         return result;
7375 }
7376
7377 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7378 {
7379         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7380 }
7381
7382 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7383         .master_xfer = amdgpu_dm_i2c_xfer,
7384         .functionality = amdgpu_dm_i2c_func,
7385 };
7386
7387 static struct amdgpu_i2c_adapter *
7388 create_i2c(struct ddc_service *ddc_service,
7389            int link_index,
7390            int *res)
7391 {
7392         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7393         struct amdgpu_i2c_adapter *i2c;
7394
7395         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7396         if (!i2c)
7397                 return NULL;
7398         i2c->base.owner = THIS_MODULE;
7399         i2c->base.class = I2C_CLASS_DDC;
7400         i2c->base.dev.parent = &adev->pdev->dev;
7401         i2c->base.algo = &amdgpu_dm_i2c_algo;
7402         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7403         i2c_set_adapdata(&i2c->base, i2c);
7404         i2c->ddc_service = ddc_service;
7405
7406         return i2c;
7407 }
7408
7409
7410 /*
7411  * Note: this function assumes that dc_link_detect() was called for the
7412  * dc_link which will be represented by this aconnector.
7413  */
7414 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7415                                     struct amdgpu_dm_connector *aconnector,
7416                                     u32 link_index,
7417                                     struct amdgpu_encoder *aencoder)
7418 {
7419         int res = 0;
7420         int connector_type;
7421         struct dc *dc = dm->dc;
7422         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7423         struct amdgpu_i2c_adapter *i2c;
7424
7425         link->priv = aconnector;
7426
7427         DRM_DEBUG_DRIVER("%s()\n", __func__);
7428
7429         i2c = create_i2c(link->ddc, link->link_index, &res);
7430         if (!i2c) {
7431                 DRM_ERROR("Failed to create i2c adapter data\n");
7432                 return -ENOMEM;
7433         }
7434
7435         aconnector->i2c = i2c;
7436         res = i2c_add_adapter(&i2c->base);
7437
7438         if (res) {
7439                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7440                 goto out_free;
7441         }
7442
7443         connector_type = to_drm_connector_type(link->connector_signal);
7444
7445         res = drm_connector_init_with_ddc(
7446                         dm->ddev,
7447                         &aconnector->base,
7448                         &amdgpu_dm_connector_funcs,
7449                         connector_type,
7450                         &i2c->base);
7451
7452         if (res) {
7453                 DRM_ERROR("connector_init failed\n");
7454                 aconnector->connector_id = -1;
7455                 goto out_free;
7456         }
7457
7458         drm_connector_helper_add(
7459                         &aconnector->base,
7460                         &amdgpu_dm_connector_helper_funcs);
7461
7462         amdgpu_dm_connector_init_helper(
7463                 dm,
7464                 aconnector,
7465                 connector_type,
7466                 link,
7467                 link_index);
7468
7469         drm_connector_attach_encoder(
7470                 &aconnector->base, &aencoder->base);
7471
7472         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7473                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7474                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7475
7476 out_free:
7477         if (res) {
7478                 kfree(i2c);
7479                 aconnector->i2c = NULL;
7480         }
7481         return res;
7482 }
7483
7484 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7485 {
7486         switch (adev->mode_info.num_crtc) {
7487         case 1:
7488                 return 0x1;
7489         case 2:
7490                 return 0x3;
7491         case 3:
7492                 return 0x7;
7493         case 4:
7494                 return 0xf;
7495         case 5:
7496                 return 0x1f;
7497         case 6:
7498         default:
7499                 return 0x3f;
7500         }
7501 }
7502
7503 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7504                                   struct amdgpu_encoder *aencoder,
7505                                   uint32_t link_index)
7506 {
7507         struct amdgpu_device *adev = drm_to_adev(dev);
7508
7509         int res = drm_encoder_init(dev,
7510                                    &aencoder->base,
7511                                    &amdgpu_dm_encoder_funcs,
7512                                    DRM_MODE_ENCODER_TMDS,
7513                                    NULL);
7514
7515         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7516
7517         if (!res)
7518                 aencoder->encoder_id = link_index;
7519         else
7520                 aencoder->encoder_id = -1;
7521
7522         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7523
7524         return res;
7525 }
7526
7527 static void manage_dm_interrupts(struct amdgpu_device *adev,
7528                                  struct amdgpu_crtc *acrtc,
7529                                  bool enable)
7530 {
7531         /*
7532          * We have no guarantee that the frontend index maps to the same
7533          * backend index - some even map to more than one.
7534          *
7535          * TODO: Use a different interrupt or check DC itself for the mapping.
7536          */
7537         int irq_type =
7538                 amdgpu_display_crtc_idx_to_irq_type(
7539                         adev,
7540                         acrtc->crtc_id);
7541
7542         if (enable) {
7543                 drm_crtc_vblank_on(&acrtc->base);
7544                 amdgpu_irq_get(
7545                         adev,
7546                         &adev->pageflip_irq,
7547                         irq_type);
7548 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7549                 amdgpu_irq_get(
7550                         adev,
7551                         &adev->vline0_irq,
7552                         irq_type);
7553 #endif
7554         } else {
7555 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7556                 amdgpu_irq_put(
7557                         adev,
7558                         &adev->vline0_irq,
7559                         irq_type);
7560 #endif
7561                 amdgpu_irq_put(
7562                         adev,
7563                         &adev->pageflip_irq,
7564                         irq_type);
7565                 drm_crtc_vblank_off(&acrtc->base);
7566         }
7567 }
7568
7569 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7570                                       struct amdgpu_crtc *acrtc)
7571 {
7572         int irq_type =
7573                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7574
7575         /**
7576          * This reads the current state for the IRQ and force reapplies
7577          * the setting to hardware.
7578          */
7579         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7580 }
7581
7582 static bool
7583 is_scaling_state_different(const struct dm_connector_state *dm_state,
7584                            const struct dm_connector_state *old_dm_state)
7585 {
7586         if (dm_state->scaling != old_dm_state->scaling)
7587                 return true;
7588         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7589                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7590                         return true;
7591         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7592                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7593                         return true;
7594         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7595                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7596                 return true;
7597         return false;
7598 }
7599
7600 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7601                                             struct drm_crtc_state *old_crtc_state,
7602                                             struct drm_connector_state *new_conn_state,
7603                                             struct drm_connector_state *old_conn_state,
7604                                             const struct drm_connector *connector,
7605                                             struct hdcp_workqueue *hdcp_w)
7606 {
7607         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7608         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7609
7610         pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7611                 connector->index, connector->status, connector->dpms);
7612         pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7613                 old_conn_state->content_protection, new_conn_state->content_protection);
7614
7615         if (old_crtc_state)
7616                 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7617                 old_crtc_state->enable,
7618                 old_crtc_state->active,
7619                 old_crtc_state->mode_changed,
7620                 old_crtc_state->active_changed,
7621                 old_crtc_state->connectors_changed);
7622
7623         if (new_crtc_state)
7624                 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7625                 new_crtc_state->enable,
7626                 new_crtc_state->active,
7627                 new_crtc_state->mode_changed,
7628                 new_crtc_state->active_changed,
7629                 new_crtc_state->connectors_changed);
7630
7631         /* hdcp content type change */
7632         if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7633             new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7634                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7635                 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7636                 return true;
7637         }
7638
7639         /* CP is being re enabled, ignore this */
7640         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7641             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7642                 if (new_crtc_state && new_crtc_state->mode_changed) {
7643                         new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7644                         pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7645                         return true;
7646                 }
7647                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7648                 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7649                 return false;
7650         }
7651
7652         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7653          *
7654          * Handles:     UNDESIRED -> ENABLED
7655          */
7656         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7657             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7658                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7659
7660         /* Stream removed and re-enabled
7661          *
7662          * Can sometimes overlap with the HPD case,
7663          * thus set update_hdcp to false to avoid
7664          * setting HDCP multiple times.
7665          *
7666          * Handles:     DESIRED -> DESIRED (Special case)
7667          */
7668         if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7669                 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7670                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7671                 dm_con_state->update_hdcp = false;
7672                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7673                         __func__);
7674                 return true;
7675         }
7676
7677         /* Hot-plug, headless s3, dpms
7678          *
7679          * Only start HDCP if the display is connected/enabled.
7680          * update_hdcp flag will be set to false until the next
7681          * HPD comes in.
7682          *
7683          * Handles:     DESIRED -> DESIRED (Special case)
7684          */
7685         if (dm_con_state->update_hdcp &&
7686         new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7687         connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7688                 dm_con_state->update_hdcp = false;
7689                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7690                         __func__);
7691                 return true;
7692         }
7693
7694         if (old_conn_state->content_protection == new_conn_state->content_protection) {
7695                 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7696                         if (new_crtc_state && new_crtc_state->mode_changed) {
7697                                 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7698                                         __func__);
7699                                 return true;
7700                         }
7701                         pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7702                                 __func__);
7703                         return false;
7704                 }
7705
7706                 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7707                 return false;
7708         }
7709
7710         if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7711                 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7712                         __func__);
7713                 return true;
7714         }
7715
7716         pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7717         return false;
7718 }
7719
7720 static void remove_stream(struct amdgpu_device *adev,
7721                           struct amdgpu_crtc *acrtc,
7722                           struct dc_stream_state *stream)
7723 {
7724         /* this is the update mode case */
7725
7726         acrtc->otg_inst = -1;
7727         acrtc->enabled = false;
7728 }
7729
7730 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7731 {
7732
7733         assert_spin_locked(&acrtc->base.dev->event_lock);
7734         WARN_ON(acrtc->event);
7735
7736         acrtc->event = acrtc->base.state->event;
7737
7738         /* Set the flip status */
7739         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7740
7741         /* Mark this event as consumed */
7742         acrtc->base.state->event = NULL;
7743
7744         DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7745                      acrtc->crtc_id);
7746 }
7747
7748 static void update_freesync_state_on_stream(
7749         struct amdgpu_display_manager *dm,
7750         struct dm_crtc_state *new_crtc_state,
7751         struct dc_stream_state *new_stream,
7752         struct dc_plane_state *surface,
7753         u32 flip_timestamp_in_us)
7754 {
7755         struct mod_vrr_params vrr_params;
7756         struct dc_info_packet vrr_infopacket = {0};
7757         struct amdgpu_device *adev = dm->adev;
7758         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7759         unsigned long flags;
7760         bool pack_sdp_v1_3 = false;
7761         struct amdgpu_dm_connector *aconn;
7762         enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7763
7764         if (!new_stream)
7765                 return;
7766
7767         /*
7768          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7769          * For now it's sufficient to just guard against these conditions.
7770          */
7771
7772         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7773                 return;
7774
7775         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7776         vrr_params = acrtc->dm_irq_params.vrr_params;
7777
7778         if (surface) {
7779                 mod_freesync_handle_preflip(
7780                         dm->freesync_module,
7781                         surface,
7782                         new_stream,
7783                         flip_timestamp_in_us,
7784                         &vrr_params);
7785
7786                 if (adev->family < AMDGPU_FAMILY_AI &&
7787                     amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7788                         mod_freesync_handle_v_update(dm->freesync_module,
7789                                                      new_stream, &vrr_params);
7790
7791                         /* Need to call this before the frame ends. */
7792                         dc_stream_adjust_vmin_vmax(dm->dc,
7793                                                    new_crtc_state->stream,
7794                                                    &vrr_params.adjust);
7795                 }
7796         }
7797
7798         aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7799
7800         if (aconn && aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
7801                 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7802
7803                 if (aconn->vsdb_info.amd_vsdb_version == 1)
7804                         packet_type = PACKET_TYPE_FS_V1;
7805                 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7806                         packet_type = PACKET_TYPE_FS_V2;
7807                 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7808                         packet_type = PACKET_TYPE_FS_V3;
7809
7810                 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7811                                         &new_stream->adaptive_sync_infopacket);
7812         }
7813
7814         mod_freesync_build_vrr_infopacket(
7815                 dm->freesync_module,
7816                 new_stream,
7817                 &vrr_params,
7818                 packet_type,
7819                 TRANSFER_FUNC_UNKNOWN,
7820                 &vrr_infopacket,
7821                 pack_sdp_v1_3);
7822
7823         new_crtc_state->freesync_vrr_info_changed |=
7824                 (memcmp(&new_crtc_state->vrr_infopacket,
7825                         &vrr_infopacket,
7826                         sizeof(vrr_infopacket)) != 0);
7827
7828         acrtc->dm_irq_params.vrr_params = vrr_params;
7829         new_crtc_state->vrr_infopacket = vrr_infopacket;
7830
7831         new_stream->vrr_infopacket = vrr_infopacket;
7832         new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7833
7834         if (new_crtc_state->freesync_vrr_info_changed)
7835                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7836                               new_crtc_state->base.crtc->base.id,
7837                               (int)new_crtc_state->base.vrr_enabled,
7838                               (int)vrr_params.state);
7839
7840         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7841 }
7842
7843 static void update_stream_irq_parameters(
7844         struct amdgpu_display_manager *dm,
7845         struct dm_crtc_state *new_crtc_state)
7846 {
7847         struct dc_stream_state *new_stream = new_crtc_state->stream;
7848         struct mod_vrr_params vrr_params;
7849         struct mod_freesync_config config = new_crtc_state->freesync_config;
7850         struct amdgpu_device *adev = dm->adev;
7851         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7852         unsigned long flags;
7853
7854         if (!new_stream)
7855                 return;
7856
7857         /*
7858          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7859          * For now it's sufficient to just guard against these conditions.
7860          */
7861         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7862                 return;
7863
7864         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7865         vrr_params = acrtc->dm_irq_params.vrr_params;
7866
7867         if (new_crtc_state->vrr_supported &&
7868             config.min_refresh_in_uhz &&
7869             config.max_refresh_in_uhz) {
7870                 /*
7871                  * if freesync compatible mode was set, config.state will be set
7872                  * in atomic check
7873                  */
7874                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7875                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7876                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7877                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7878                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7879                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7880                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7881                 } else {
7882                         config.state = new_crtc_state->base.vrr_enabled ?
7883                                                      VRR_STATE_ACTIVE_VARIABLE :
7884                                                      VRR_STATE_INACTIVE;
7885                 }
7886         } else {
7887                 config.state = VRR_STATE_UNSUPPORTED;
7888         }
7889
7890         mod_freesync_build_vrr_params(dm->freesync_module,
7891                                       new_stream,
7892                                       &config, &vrr_params);
7893
7894         new_crtc_state->freesync_config = config;
7895         /* Copy state for access from DM IRQ handler */
7896         acrtc->dm_irq_params.freesync_config = config;
7897         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7898         acrtc->dm_irq_params.vrr_params = vrr_params;
7899         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7900 }
7901
7902 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7903                                             struct dm_crtc_state *new_state)
7904 {
7905         bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
7906         bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
7907
7908         if (!old_vrr_active && new_vrr_active) {
7909                 /* Transition VRR inactive -> active:
7910                  * While VRR is active, we must not disable vblank irq, as a
7911                  * reenable after disable would compute bogus vblank/pflip
7912                  * timestamps if it likely happened inside display front-porch.
7913                  *
7914                  * We also need vupdate irq for the actual core vblank handling
7915                  * at end of vblank.
7916                  */
7917                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
7918                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
7919                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7920                                  __func__, new_state->base.crtc->base.id);
7921         } else if (old_vrr_active && !new_vrr_active) {
7922                 /* Transition VRR active -> inactive:
7923                  * Allow vblank irq disable again for fixed refresh rate.
7924                  */
7925                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
7926                 drm_crtc_vblank_put(new_state->base.crtc);
7927                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7928                                  __func__, new_state->base.crtc->base.id);
7929         }
7930 }
7931
7932 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7933 {
7934         struct drm_plane *plane;
7935         struct drm_plane_state *old_plane_state;
7936         int i;
7937
7938         /*
7939          * TODO: Make this per-stream so we don't issue redundant updates for
7940          * commits with multiple streams.
7941          */
7942         for_each_old_plane_in_state(state, plane, old_plane_state, i)
7943                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7944                         amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
7945 }
7946
7947 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
7948 {
7949         struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
7950
7951         return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
7952 }
7953
7954 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7955                                     struct dc_state *dc_state,
7956                                     struct drm_device *dev,
7957                                     struct amdgpu_display_manager *dm,
7958                                     struct drm_crtc *pcrtc,
7959                                     bool wait_for_vblank)
7960 {
7961         u32 i;
7962         u64 timestamp_ns = ktime_get_ns();
7963         struct drm_plane *plane;
7964         struct drm_plane_state *old_plane_state, *new_plane_state;
7965         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
7966         struct drm_crtc_state *new_pcrtc_state =
7967                         drm_atomic_get_new_crtc_state(state, pcrtc);
7968         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
7969         struct dm_crtc_state *dm_old_crtc_state =
7970                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
7971         int planes_count = 0, vpos, hpos;
7972         unsigned long flags;
7973         u32 target_vblank, last_flip_vblank;
7974         bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
7975         bool cursor_update = false;
7976         bool pflip_present = false;
7977         bool dirty_rects_changed = false;
7978         struct {
7979                 struct dc_surface_update surface_updates[MAX_SURFACES];
7980                 struct dc_plane_info plane_infos[MAX_SURFACES];
7981                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
7982                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7983                 struct dc_stream_update stream_update;
7984         } *bundle;
7985
7986         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7987
7988         if (!bundle) {
7989                 dm_error("Failed to allocate update bundle\n");
7990                 goto cleanup;
7991         }
7992
7993         /*
7994          * Disable the cursor first if we're disabling all the planes.
7995          * It'll remain on the screen after the planes are re-enabled
7996          * if we don't.
7997          */
7998         if (acrtc_state->active_planes == 0)
7999                 amdgpu_dm_commit_cursors(state);
8000
8001         /* update planes when needed */
8002         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8003                 struct drm_crtc *crtc = new_plane_state->crtc;
8004                 struct drm_crtc_state *new_crtc_state;
8005                 struct drm_framebuffer *fb = new_plane_state->fb;
8006                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
8007                 bool plane_needs_flip;
8008                 struct dc_plane_state *dc_plane;
8009                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
8010
8011                 /* Cursor plane is handled after stream updates */
8012                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
8013                         if ((fb && crtc == pcrtc) ||
8014                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
8015                                 cursor_update = true;
8016
8017                         continue;
8018                 }
8019
8020                 if (!fb || !crtc || pcrtc != crtc)
8021                         continue;
8022
8023                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8024                 if (!new_crtc_state->active)
8025                         continue;
8026
8027                 dc_plane = dm_new_plane_state->dc_state;
8028                 if (!dc_plane)
8029                         continue;
8030
8031                 bundle->surface_updates[planes_count].surface = dc_plane;
8032                 if (new_pcrtc_state->color_mgmt_changed) {
8033                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8034                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
8035                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
8036                 }
8037
8038                 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
8039                                      &bundle->scaling_infos[planes_count]);
8040
8041                 bundle->surface_updates[planes_count].scaling_info =
8042                         &bundle->scaling_infos[planes_count];
8043
8044                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8045
8046                 pflip_present = pflip_present || plane_needs_flip;
8047
8048                 if (!plane_needs_flip) {
8049                         planes_count += 1;
8050                         continue;
8051                 }
8052
8053                 fill_dc_plane_info_and_addr(
8054                         dm->adev, new_plane_state,
8055                         afb->tiling_flags,
8056                         &bundle->plane_infos[planes_count],
8057                         &bundle->flip_addrs[planes_count].address,
8058                         afb->tmz_surface, false);
8059
8060                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8061                                  new_plane_state->plane->index,
8062                                  bundle->plane_infos[planes_count].dcc.enable);
8063
8064                 bundle->surface_updates[planes_count].plane_info =
8065                         &bundle->plane_infos[planes_count];
8066
8067                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8068                         fill_dc_dirty_rects(plane, old_plane_state,
8069                                             new_plane_state, new_crtc_state,
8070                                             &bundle->flip_addrs[planes_count],
8071                                             &dirty_rects_changed);
8072
8073                         /*
8074                          * If the dirty regions changed, PSR-SU need to be disabled temporarily
8075                          * and enabled it again after dirty regions are stable to avoid video glitch.
8076                          * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8077                          * during the PSR-SU was disabled.
8078                          */
8079                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8080                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8081 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8082                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8083 #endif
8084                             dirty_rects_changed) {
8085                                 mutex_lock(&dm->dc_lock);
8086                                 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8087                                 timestamp_ns;
8088                                 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8089                                         amdgpu_dm_psr_disable(acrtc_state->stream);
8090                                 mutex_unlock(&dm->dc_lock);
8091                         }
8092                 }
8093
8094                 /*
8095                  * Only allow immediate flips for fast updates that don't
8096                  * change memory domain, FB pitch, DCC state, rotation or
8097                  * mirroring.
8098                  */
8099                 bundle->flip_addrs[planes_count].flip_immediate =
8100                         crtc->state->async_flip &&
8101                         acrtc_state->update_type == UPDATE_TYPE_FAST &&
8102                         get_mem_type(old_plane_state->fb) == get_mem_type(fb);
8103
8104                 timestamp_ns = ktime_get_ns();
8105                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8106                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8107                 bundle->surface_updates[planes_count].surface = dc_plane;
8108
8109                 if (!bundle->surface_updates[planes_count].surface) {
8110                         DRM_ERROR("No surface for CRTC: id=%d\n",
8111                                         acrtc_attach->crtc_id);
8112                         continue;
8113                 }
8114
8115                 if (plane == pcrtc->primary)
8116                         update_freesync_state_on_stream(
8117                                 dm,
8118                                 acrtc_state,
8119                                 acrtc_state->stream,
8120                                 dc_plane,
8121                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8122
8123                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8124                                  __func__,
8125                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8126                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8127
8128                 planes_count += 1;
8129
8130         }
8131
8132         if (pflip_present) {
8133                 if (!vrr_active) {
8134                         /* Use old throttling in non-vrr fixed refresh rate mode
8135                          * to keep flip scheduling based on target vblank counts
8136                          * working in a backwards compatible way, e.g., for
8137                          * clients using the GLX_OML_sync_control extension or
8138                          * DRI3/Present extension with defined target_msc.
8139                          */
8140                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8141                 }
8142                 else {
8143                         /* For variable refresh rate mode only:
8144                          * Get vblank of last completed flip to avoid > 1 vrr
8145                          * flips per video frame by use of throttling, but allow
8146                          * flip programming anywhere in the possibly large
8147                          * variable vrr vblank interval for fine-grained flip
8148                          * timing control and more opportunity to avoid stutter
8149                          * on late submission of flips.
8150                          */
8151                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8152                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8153                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8154                 }
8155
8156                 target_vblank = last_flip_vblank + wait_for_vblank;
8157
8158                 /*
8159                  * Wait until we're out of the vertical blank period before the one
8160                  * targeted by the flip
8161                  */
8162                 while ((acrtc_attach->enabled &&
8163                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8164                                                             0, &vpos, &hpos, NULL,
8165                                                             NULL, &pcrtc->hwmode)
8166                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8167                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8168                         (int)(target_vblank -
8169                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8170                         usleep_range(1000, 1100);
8171                 }
8172
8173                 /**
8174                  * Prepare the flip event for the pageflip interrupt to handle.
8175                  *
8176                  * This only works in the case where we've already turned on the
8177                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8178                  * from 0 -> n planes we have to skip a hardware generated event
8179                  * and rely on sending it from software.
8180                  */
8181                 if (acrtc_attach->base.state->event &&
8182                     acrtc_state->active_planes > 0) {
8183                         drm_crtc_vblank_get(pcrtc);
8184
8185                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8186
8187                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8188                         prepare_flip_isr(acrtc_attach);
8189
8190                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8191                 }
8192
8193                 if (acrtc_state->stream) {
8194                         if (acrtc_state->freesync_vrr_info_changed)
8195                                 bundle->stream_update.vrr_infopacket =
8196                                         &acrtc_state->stream->vrr_infopacket;
8197                 }
8198         } else if (cursor_update && acrtc_state->active_planes > 0 &&
8199                    acrtc_attach->base.state->event) {
8200                 drm_crtc_vblank_get(pcrtc);
8201
8202                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8203
8204                 acrtc_attach->event = acrtc_attach->base.state->event;
8205                 acrtc_attach->base.state->event = NULL;
8206
8207                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8208         }
8209
8210         /* Update the planes if changed or disable if we don't have any. */
8211         if ((planes_count || acrtc_state->active_planes == 0) &&
8212                 acrtc_state->stream) {
8213                 /*
8214                  * If PSR or idle optimizations are enabled then flush out
8215                  * any pending work before hardware programming.
8216                  */
8217                 if (dm->vblank_control_workqueue)
8218                         flush_workqueue(dm->vblank_control_workqueue);
8219
8220                 bundle->stream_update.stream = acrtc_state->stream;
8221                 if (new_pcrtc_state->mode_changed) {
8222                         bundle->stream_update.src = acrtc_state->stream->src;
8223                         bundle->stream_update.dst = acrtc_state->stream->dst;
8224                 }
8225
8226                 if (new_pcrtc_state->color_mgmt_changed) {
8227                         /*
8228                          * TODO: This isn't fully correct since we've actually
8229                          * already modified the stream in place.
8230                          */
8231                         bundle->stream_update.gamut_remap =
8232                                 &acrtc_state->stream->gamut_remap_matrix;
8233                         bundle->stream_update.output_csc_transform =
8234                                 &acrtc_state->stream->csc_color_matrix;
8235                         bundle->stream_update.out_transfer_func =
8236                                 acrtc_state->stream->out_transfer_func;
8237                 }
8238
8239                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8240                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8241                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8242
8243                 /*
8244                  * If FreeSync state on the stream has changed then we need to
8245                  * re-adjust the min/max bounds now that DC doesn't handle this
8246                  * as part of commit.
8247                  */
8248                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8249                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8250                         dc_stream_adjust_vmin_vmax(
8251                                 dm->dc, acrtc_state->stream,
8252                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8253                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8254                 }
8255                 mutex_lock(&dm->dc_lock);
8256                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8257                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8258                         amdgpu_dm_psr_disable(acrtc_state->stream);
8259
8260                 update_planes_and_stream_adapter(dm->dc,
8261                                          acrtc_state->update_type,
8262                                          planes_count,
8263                                          acrtc_state->stream,
8264                                          &bundle->stream_update,
8265                                          bundle->surface_updates);
8266
8267                 /**
8268                  * Enable or disable the interrupts on the backend.
8269                  *
8270                  * Most pipes are put into power gating when unused.
8271                  *
8272                  * When power gating is enabled on a pipe we lose the
8273                  * interrupt enablement state when power gating is disabled.
8274                  *
8275                  * So we need to update the IRQ control state in hardware
8276                  * whenever the pipe turns on (since it could be previously
8277                  * power gated) or off (since some pipes can't be power gated
8278                  * on some ASICs).
8279                  */
8280                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8281                         dm_update_pflip_irq_state(drm_to_adev(dev),
8282                                                   acrtc_attach);
8283
8284                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8285                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8286                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8287                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8288
8289                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8290                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8291                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8292                         struct amdgpu_dm_connector *aconn =
8293                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8294
8295                         if (aconn->psr_skip_count > 0)
8296                                 aconn->psr_skip_count--;
8297
8298                         /* Allow PSR when skip count is 0. */
8299                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8300
8301                         /*
8302                          * If sink supports PSR SU, there is no need to rely on
8303                          * a vblank event disable request to enable PSR. PSR SU
8304                          * can be enabled immediately once OS demonstrates an
8305                          * adequate number of fast atomic commits to notify KMD
8306                          * of update events. See `vblank_control_worker()`.
8307                          */
8308                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8309                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8310 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8311                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8312 #endif
8313                             !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8314                             (timestamp_ns -
8315                             acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8316                             500000000)
8317                                 amdgpu_dm_psr_enable(acrtc_state->stream);
8318                 } else {
8319                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
8320                 }
8321
8322                 mutex_unlock(&dm->dc_lock);
8323         }
8324
8325         /*
8326          * Update cursor state *after* programming all the planes.
8327          * This avoids redundant programming in the case where we're going
8328          * to be disabling a single plane - those pipes are being disabled.
8329          */
8330         if (acrtc_state->active_planes)
8331                 amdgpu_dm_commit_cursors(state);
8332
8333 cleanup:
8334         kfree(bundle);
8335 }
8336
8337 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8338                                    struct drm_atomic_state *state)
8339 {
8340         struct amdgpu_device *adev = drm_to_adev(dev);
8341         struct amdgpu_dm_connector *aconnector;
8342         struct drm_connector *connector;
8343         struct drm_connector_state *old_con_state, *new_con_state;
8344         struct drm_crtc_state *new_crtc_state;
8345         struct dm_crtc_state *new_dm_crtc_state;
8346         const struct dc_stream_status *status;
8347         int i, inst;
8348
8349         /* Notify device removals. */
8350         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8351                 if (old_con_state->crtc != new_con_state->crtc) {
8352                         /* CRTC changes require notification. */
8353                         goto notify;
8354                 }
8355
8356                 if (!new_con_state->crtc)
8357                         continue;
8358
8359                 new_crtc_state = drm_atomic_get_new_crtc_state(
8360                         state, new_con_state->crtc);
8361
8362                 if (!new_crtc_state)
8363                         continue;
8364
8365                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8366                         continue;
8367
8368 notify:
8369                 aconnector = to_amdgpu_dm_connector(connector);
8370
8371                 mutex_lock(&adev->dm.audio_lock);
8372                 inst = aconnector->audio_inst;
8373                 aconnector->audio_inst = -1;
8374                 mutex_unlock(&adev->dm.audio_lock);
8375
8376                 amdgpu_dm_audio_eld_notify(adev, inst);
8377         }
8378
8379         /* Notify audio device additions. */
8380         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8381                 if (!new_con_state->crtc)
8382                         continue;
8383
8384                 new_crtc_state = drm_atomic_get_new_crtc_state(
8385                         state, new_con_state->crtc);
8386
8387                 if (!new_crtc_state)
8388                         continue;
8389
8390                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8391                         continue;
8392
8393                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8394                 if (!new_dm_crtc_state->stream)
8395                         continue;
8396
8397                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8398                 if (!status)
8399                         continue;
8400
8401                 aconnector = to_amdgpu_dm_connector(connector);
8402
8403                 mutex_lock(&adev->dm.audio_lock);
8404                 inst = status->audio_inst;
8405                 aconnector->audio_inst = inst;
8406                 mutex_unlock(&adev->dm.audio_lock);
8407
8408                 amdgpu_dm_audio_eld_notify(adev, inst);
8409         }
8410 }
8411
8412 /*
8413  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8414  * @crtc_state: the DRM CRTC state
8415  * @stream_state: the DC stream state.
8416  *
8417  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8418  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8419  */
8420 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8421                                                 struct dc_stream_state *stream_state)
8422 {
8423         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8424 }
8425
8426 /**
8427  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8428  * @state: The atomic state to commit
8429  *
8430  * This will tell DC to commit the constructed DC state from atomic_check,
8431  * programming the hardware. Any failures here implies a hardware failure, since
8432  * atomic check should have filtered anything non-kosher.
8433  */
8434 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8435 {
8436         struct drm_device *dev = state->dev;
8437         struct amdgpu_device *adev = drm_to_adev(dev);
8438         struct amdgpu_display_manager *dm = &adev->dm;
8439         struct dm_atomic_state *dm_state;
8440         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8441         u32 i, j;
8442         struct drm_crtc *crtc;
8443         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8444         unsigned long flags;
8445         bool wait_for_vblank = true;
8446         struct drm_connector *connector;
8447         struct drm_connector_state *old_con_state, *new_con_state;
8448         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8449         int crtc_disable_count = 0;
8450         bool mode_set_reset_required = false;
8451         int r;
8452
8453         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8454
8455         r = drm_atomic_helper_wait_for_fences(dev, state, false);
8456         if (unlikely(r))
8457                 DRM_ERROR("Waiting for fences timed out!");
8458
8459         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8460         drm_dp_mst_atomic_wait_for_dependencies(state);
8461
8462         dm_state = dm_atomic_get_new_state(state);
8463         if (dm_state && dm_state->context) {
8464                 dc_state = dm_state->context;
8465         } else {
8466                 /* No state changes, retain current state. */
8467                 dc_state_temp = dc_create_state(dm->dc);
8468                 ASSERT(dc_state_temp);
8469                 dc_state = dc_state_temp;
8470                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8471         }
8472
8473         for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8474                                        new_crtc_state, i) {
8475                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8476
8477                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8478
8479                 if (old_crtc_state->active &&
8480                     (!new_crtc_state->active ||
8481                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8482                         manage_dm_interrupts(adev, acrtc, false);
8483                         dc_stream_release(dm_old_crtc_state->stream);
8484                 }
8485         }
8486
8487         drm_atomic_helper_calc_timestamping_constants(state);
8488
8489         /* update changed items */
8490         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8491                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8492
8493                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8494                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8495
8496                 drm_dbg_state(state->dev,
8497                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8498                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8499                         "connectors_changed:%d\n",
8500                         acrtc->crtc_id,
8501                         new_crtc_state->enable,
8502                         new_crtc_state->active,
8503                         new_crtc_state->planes_changed,
8504                         new_crtc_state->mode_changed,
8505                         new_crtc_state->active_changed,
8506                         new_crtc_state->connectors_changed);
8507
8508                 /* Disable cursor if disabling crtc */
8509                 if (old_crtc_state->active && !new_crtc_state->active) {
8510                         struct dc_cursor_position position;
8511
8512                         memset(&position, 0, sizeof(position));
8513                         mutex_lock(&dm->dc_lock);
8514                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8515                         mutex_unlock(&dm->dc_lock);
8516                 }
8517
8518                 /* Copy all transient state flags into dc state */
8519                 if (dm_new_crtc_state->stream) {
8520                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8521                                                             dm_new_crtc_state->stream);
8522                 }
8523
8524                 /* handles headless hotplug case, updating new_state and
8525                  * aconnector as needed
8526                  */
8527
8528                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8529
8530                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8531
8532                         if (!dm_new_crtc_state->stream) {
8533                                 /*
8534                                  * this could happen because of issues with
8535                                  * userspace notifications delivery.
8536                                  * In this case userspace tries to set mode on
8537                                  * display which is disconnected in fact.
8538                                  * dc_sink is NULL in this case on aconnector.
8539                                  * We expect reset mode will come soon.
8540                                  *
8541                                  * This can also happen when unplug is done
8542                                  * during resume sequence ended
8543                                  *
8544                                  * In this case, we want to pretend we still
8545                                  * have a sink to keep the pipe running so that
8546                                  * hw state is consistent with the sw state
8547                                  */
8548                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8549                                                 __func__, acrtc->base.base.id);
8550                                 continue;
8551                         }
8552
8553                         if (dm_old_crtc_state->stream)
8554                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8555
8556                         pm_runtime_get_noresume(dev->dev);
8557
8558                         acrtc->enabled = true;
8559                         acrtc->hw_mode = new_crtc_state->mode;
8560                         crtc->hwmode = new_crtc_state->mode;
8561                         mode_set_reset_required = true;
8562                 } else if (modereset_required(new_crtc_state)) {
8563                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8564                         /* i.e. reset mode */
8565                         if (dm_old_crtc_state->stream)
8566                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8567
8568                         mode_set_reset_required = true;
8569                 }
8570         } /* for_each_crtc_in_state() */
8571
8572         if (dc_state) {
8573                 /* if there mode set or reset, disable eDP PSR */
8574                 if (mode_set_reset_required) {
8575                         if (dm->vblank_control_workqueue)
8576                                 flush_workqueue(dm->vblank_control_workqueue);
8577
8578                         amdgpu_dm_psr_disable_all(dm);
8579                 }
8580
8581                 dm_enable_per_frame_crtc_master_sync(dc_state);
8582                 mutex_lock(&dm->dc_lock);
8583                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8584
8585                 /* Allow idle optimization when vblank count is 0 for display off */
8586                 if (dm->active_vblank_irq_count == 0)
8587                         dc_allow_idle_optimizations(dm->dc, true);
8588                 mutex_unlock(&dm->dc_lock);
8589         }
8590
8591         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8592                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8593
8594                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8595
8596                 if (dm_new_crtc_state->stream != NULL) {
8597                         const struct dc_stream_status *status =
8598                                         dc_stream_get_status(dm_new_crtc_state->stream);
8599
8600                         if (!status)
8601                                 status = dc_stream_get_status_from_state(dc_state,
8602                                                                          dm_new_crtc_state->stream);
8603                         if (!status)
8604                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8605                         else
8606                                 acrtc->otg_inst = status->primary_otg_inst;
8607                 }
8608         }
8609         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8610                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8611                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8612                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8613
8614                 if (!adev->dm.hdcp_workqueue)
8615                         continue;
8616
8617                 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8618
8619                 if (!connector)
8620                         continue;
8621
8622                 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8623                         connector->index, connector->status, connector->dpms);
8624                 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8625                         old_con_state->content_protection, new_con_state->content_protection);
8626
8627                 if (aconnector->dc_sink) {
8628                         if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8629                                 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8630                                 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8631                                 aconnector->dc_sink->edid_caps.display_name);
8632                         }
8633                 }
8634
8635                 new_crtc_state = NULL;
8636                 old_crtc_state = NULL;
8637
8638                 if (acrtc) {
8639                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8640                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8641                 }
8642
8643                 if (old_crtc_state)
8644                         pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8645                         old_crtc_state->enable,
8646                         old_crtc_state->active,
8647                         old_crtc_state->mode_changed,
8648                         old_crtc_state->active_changed,
8649                         old_crtc_state->connectors_changed);
8650
8651                 if (new_crtc_state)
8652                         pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8653                         new_crtc_state->enable,
8654                         new_crtc_state->active,
8655                         new_crtc_state->mode_changed,
8656                         new_crtc_state->active_changed,
8657                         new_crtc_state->connectors_changed);
8658         }
8659
8660         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8661                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8662                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8663                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8664
8665                 if (!adev->dm.hdcp_workqueue)
8666                         continue;
8667
8668                 new_crtc_state = NULL;
8669                 old_crtc_state = NULL;
8670
8671                 if (acrtc) {
8672                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8673                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8674                 }
8675
8676                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8677
8678                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8679                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8680                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8681                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8682                         dm_new_con_state->update_hdcp = true;
8683                         continue;
8684                 }
8685
8686                 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8687                                                                                         old_con_state, connector, adev->dm.hdcp_workqueue)) {
8688                         /* when display is unplugged from mst hub, connctor will
8689                          * be destroyed within dm_dp_mst_connector_destroy. connector
8690                          * hdcp perperties, like type, undesired, desired, enabled,
8691                          * will be lost. So, save hdcp properties into hdcp_work within
8692                          * amdgpu_dm_atomic_commit_tail. if the same display is
8693                          * plugged back with same display index, its hdcp properties
8694                          * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8695                          */
8696
8697                         bool enable_encryption = false;
8698
8699                         if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8700                                 enable_encryption = true;
8701
8702                         if (aconnector->dc_link && aconnector->dc_sink &&
8703                                 aconnector->dc_link->type == dc_connection_mst_branch) {
8704                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8705                                 struct hdcp_workqueue *hdcp_w =
8706                                         &hdcp_work[aconnector->dc_link->link_index];
8707
8708                                 hdcp_w->hdcp_content_type[connector->index] =
8709                                         new_con_state->hdcp_content_type;
8710                                 hdcp_w->content_protection[connector->index] =
8711                                         new_con_state->content_protection;
8712                         }
8713
8714                         if (new_crtc_state && new_crtc_state->mode_changed &&
8715                                 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8716                                 enable_encryption = true;
8717
8718                         DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8719
8720                         hdcp_update_display(
8721                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8722                                 new_con_state->hdcp_content_type, enable_encryption);
8723                 }
8724         }
8725
8726         /* Handle connector state changes */
8727         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8728                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8729                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8730                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8731                 struct dc_surface_update dummy_updates[MAX_SURFACES];
8732                 struct dc_stream_update stream_update;
8733                 struct dc_info_packet hdr_packet;
8734                 struct dc_stream_status *status = NULL;
8735                 bool abm_changed, hdr_changed, scaling_changed;
8736
8737                 memset(&dummy_updates, 0, sizeof(dummy_updates));
8738                 memset(&stream_update, 0, sizeof(stream_update));
8739
8740                 if (acrtc) {
8741                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8742                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8743                 }
8744
8745                 /* Skip any modesets/resets */
8746                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8747                         continue;
8748
8749                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8750                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8751
8752                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8753                                                              dm_old_con_state);
8754
8755                 abm_changed = dm_new_crtc_state->abm_level !=
8756                               dm_old_crtc_state->abm_level;
8757
8758                 hdr_changed =
8759                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8760
8761                 if (!scaling_changed && !abm_changed && !hdr_changed)
8762                         continue;
8763
8764                 stream_update.stream = dm_new_crtc_state->stream;
8765                 if (scaling_changed) {
8766                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8767                                         dm_new_con_state, dm_new_crtc_state->stream);
8768
8769                         stream_update.src = dm_new_crtc_state->stream->src;
8770                         stream_update.dst = dm_new_crtc_state->stream->dst;
8771                 }
8772
8773                 if (abm_changed) {
8774                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8775
8776                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8777                 }
8778
8779                 if (hdr_changed) {
8780                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8781                         stream_update.hdr_static_metadata = &hdr_packet;
8782                 }
8783
8784                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8785
8786                 if (WARN_ON(!status))
8787                         continue;
8788
8789                 WARN_ON(!status->plane_count);
8790
8791                 /*
8792                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8793                  * Here we create an empty update on each plane.
8794                  * To fix this, DC should permit updating only stream properties.
8795                  */
8796                 for (j = 0; j < status->plane_count; j++)
8797                         dummy_updates[j].surface = status->plane_states[0];
8798
8799
8800                 mutex_lock(&dm->dc_lock);
8801                 dc_update_planes_and_stream(dm->dc,
8802                                             dummy_updates,
8803                                             status->plane_count,
8804                                             dm_new_crtc_state->stream,
8805                                             &stream_update);
8806                 mutex_unlock(&dm->dc_lock);
8807         }
8808
8809         /**
8810          * Enable interrupts for CRTCs that are newly enabled or went through
8811          * a modeset. It was intentionally deferred until after the front end
8812          * state was modified to wait until the OTG was on and so the IRQ
8813          * handlers didn't access stale or invalid state.
8814          */
8815         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8816                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8817 #ifdef CONFIG_DEBUG_FS
8818                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8819 #endif
8820                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8821                 if (old_crtc_state->active && !new_crtc_state->active)
8822                         crtc_disable_count++;
8823
8824                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8825                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8826
8827                 /* For freesync config update on crtc state and params for irq */
8828                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8829
8830 #ifdef CONFIG_DEBUG_FS
8831                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8832                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8833                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8834 #endif
8835
8836                 if (new_crtc_state->active &&
8837                     (!old_crtc_state->active ||
8838                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8839                         dc_stream_retain(dm_new_crtc_state->stream);
8840                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8841                         manage_dm_interrupts(adev, acrtc, true);
8842                 }
8843                 /* Handle vrr on->off / off->on transitions */
8844                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8845
8846 #ifdef CONFIG_DEBUG_FS
8847                 if (new_crtc_state->active &&
8848                     (!old_crtc_state->active ||
8849                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8850                         /**
8851                          * Frontend may have changed so reapply the CRC capture
8852                          * settings for the stream.
8853                          */
8854                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8855 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8856                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8857                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8858                                         acrtc->dm_irq_params.window_param.update_win = true;
8859
8860                                         /**
8861                                          * It takes 2 frames for HW to stably generate CRC when
8862                                          * resuming from suspend, so we set skip_frame_cnt 2.
8863                                          */
8864                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8865                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8866                                 }
8867 #endif
8868                                 if (amdgpu_dm_crtc_configure_crc_source(
8869                                         crtc, dm_new_crtc_state, cur_crc_src))
8870                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
8871                         }
8872                 }
8873 #endif
8874         }
8875
8876         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8877                 if (new_crtc_state->async_flip)
8878                         wait_for_vblank = false;
8879
8880         /* update planes when needed per crtc*/
8881         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8882                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8883
8884                 if (dm_new_crtc_state->stream)
8885                         amdgpu_dm_commit_planes(state, dc_state, dev,
8886                                                 dm, crtc, wait_for_vblank);
8887         }
8888
8889         /* Update audio instances for each connector. */
8890         amdgpu_dm_commit_audio(dev, state);
8891
8892         /* restore the backlight level */
8893         for (i = 0; i < dm->num_of_edps; i++) {
8894                 if (dm->backlight_dev[i] &&
8895                     (dm->actual_brightness[i] != dm->brightness[i]))
8896                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8897         }
8898
8899         /*
8900          * send vblank event on all events not handled in flip and
8901          * mark consumed event for drm_atomic_helper_commit_hw_done
8902          */
8903         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8904         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8905
8906                 if (new_crtc_state->event)
8907                         drm_send_event_locked(dev, &new_crtc_state->event->base);
8908
8909                 new_crtc_state->event = NULL;
8910         }
8911         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8912
8913         /* Signal HW programming completion */
8914         drm_atomic_helper_commit_hw_done(state);
8915
8916         if (wait_for_vblank)
8917                 drm_atomic_helper_wait_for_flip_done(dev, state);
8918
8919         drm_atomic_helper_cleanup_planes(dev, state);
8920
8921         /* return the stolen vga memory back to VRAM */
8922         if (!adev->mman.keep_stolen_vga_memory)
8923                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8924         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8925
8926         /*
8927          * Finally, drop a runtime PM reference for each newly disabled CRTC,
8928          * so we can put the GPU into runtime suspend if we're not driving any
8929          * displays anymore
8930          */
8931         for (i = 0; i < crtc_disable_count; i++)
8932                 pm_runtime_put_autosuspend(dev->dev);
8933         pm_runtime_mark_last_busy(dev->dev);
8934
8935         if (dc_state_temp)
8936                 dc_release_state(dc_state_temp);
8937 }
8938
8939 static int dm_force_atomic_commit(struct drm_connector *connector)
8940 {
8941         int ret = 0;
8942         struct drm_device *ddev = connector->dev;
8943         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8944         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8945         struct drm_plane *plane = disconnected_acrtc->base.primary;
8946         struct drm_connector_state *conn_state;
8947         struct drm_crtc_state *crtc_state;
8948         struct drm_plane_state *plane_state;
8949
8950         if (!state)
8951                 return -ENOMEM;
8952
8953         state->acquire_ctx = ddev->mode_config.acquire_ctx;
8954
8955         /* Construct an atomic state to restore previous display setting */
8956
8957         /*
8958          * Attach connectors to drm_atomic_state
8959          */
8960         conn_state = drm_atomic_get_connector_state(state, connector);
8961
8962         ret = PTR_ERR_OR_ZERO(conn_state);
8963         if (ret)
8964                 goto out;
8965
8966         /* Attach crtc to drm_atomic_state*/
8967         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8968
8969         ret = PTR_ERR_OR_ZERO(crtc_state);
8970         if (ret)
8971                 goto out;
8972
8973         /* force a restore */
8974         crtc_state->mode_changed = true;
8975
8976         /* Attach plane to drm_atomic_state */
8977         plane_state = drm_atomic_get_plane_state(state, plane);
8978
8979         ret = PTR_ERR_OR_ZERO(plane_state);
8980         if (ret)
8981                 goto out;
8982
8983         /* Call commit internally with the state we just constructed */
8984         ret = drm_atomic_commit(state);
8985
8986 out:
8987         drm_atomic_state_put(state);
8988         if (ret)
8989                 DRM_ERROR("Restoring old state failed with %i\n", ret);
8990
8991         return ret;
8992 }
8993
8994 /*
8995  * This function handles all cases when set mode does not come upon hotplug.
8996  * This includes when a display is unplugged then plugged back into the
8997  * same port and when running without usermode desktop manager supprot
8998  */
8999 void dm_restore_drm_connector_state(struct drm_device *dev,
9000                                     struct drm_connector *connector)
9001 {
9002         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9003         struct amdgpu_crtc *disconnected_acrtc;
9004         struct dm_crtc_state *acrtc_state;
9005
9006         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
9007                 return;
9008
9009         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9010         if (!disconnected_acrtc)
9011                 return;
9012
9013         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
9014         if (!acrtc_state->stream)
9015                 return;
9016
9017         /*
9018          * If the previous sink is not released and different from the current,
9019          * we deduce we are in a state where we can not rely on usermode call
9020          * to turn on the display, so we do it here
9021          */
9022         if (acrtc_state->stream->sink != aconnector->dc_sink)
9023                 dm_force_atomic_commit(&aconnector->base);
9024 }
9025
9026 /*
9027  * Grabs all modesetting locks to serialize against any blocking commits,
9028  * Waits for completion of all non blocking commits.
9029  */
9030 static int do_aquire_global_lock(struct drm_device *dev,
9031                                  struct drm_atomic_state *state)
9032 {
9033         struct drm_crtc *crtc;
9034         struct drm_crtc_commit *commit;
9035         long ret;
9036
9037         /*
9038          * Adding all modeset locks to aquire_ctx will
9039          * ensure that when the framework release it the
9040          * extra locks we are locking here will get released to
9041          */
9042         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9043         if (ret)
9044                 return ret;
9045
9046         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9047                 spin_lock(&crtc->commit_lock);
9048                 commit = list_first_entry_or_null(&crtc->commit_list,
9049                                 struct drm_crtc_commit, commit_entry);
9050                 if (commit)
9051                         drm_crtc_commit_get(commit);
9052                 spin_unlock(&crtc->commit_lock);
9053
9054                 if (!commit)
9055                         continue;
9056
9057                 /*
9058                  * Make sure all pending HW programming completed and
9059                  * page flips done
9060                  */
9061                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9062
9063                 if (ret > 0)
9064                         ret = wait_for_completion_interruptible_timeout(
9065                                         &commit->flip_done, 10*HZ);
9066
9067                 if (ret == 0)
9068                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
9069                                   "timed out\n", crtc->base.id, crtc->name);
9070
9071                 drm_crtc_commit_put(commit);
9072         }
9073
9074         return ret < 0 ? ret : 0;
9075 }
9076
9077 static void get_freesync_config_for_crtc(
9078         struct dm_crtc_state *new_crtc_state,
9079         struct dm_connector_state *new_con_state)
9080 {
9081         struct mod_freesync_config config = {0};
9082         struct amdgpu_dm_connector *aconnector =
9083                         to_amdgpu_dm_connector(new_con_state->base.connector);
9084         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9085         int vrefresh = drm_mode_vrefresh(mode);
9086         bool fs_vid_mode = false;
9087
9088         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9089                                         vrefresh >= aconnector->min_vfreq &&
9090                                         vrefresh <= aconnector->max_vfreq;
9091
9092         if (new_crtc_state->vrr_supported) {
9093                 new_crtc_state->stream->ignore_msa_timing_param = true;
9094                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9095
9096                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9097                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9098                 config.vsif_supported = true;
9099                 config.btr = true;
9100
9101                 if (fs_vid_mode) {
9102                         config.state = VRR_STATE_ACTIVE_FIXED;
9103                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9104                         goto out;
9105                 } else if (new_crtc_state->base.vrr_enabled) {
9106                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9107                 } else {
9108                         config.state = VRR_STATE_INACTIVE;
9109                 }
9110         }
9111 out:
9112         new_crtc_state->freesync_config = config;
9113 }
9114
9115 static void reset_freesync_config_for_crtc(
9116         struct dm_crtc_state *new_crtc_state)
9117 {
9118         new_crtc_state->vrr_supported = false;
9119
9120         memset(&new_crtc_state->vrr_infopacket, 0,
9121                sizeof(new_crtc_state->vrr_infopacket));
9122 }
9123
9124 static bool
9125 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9126                                  struct drm_crtc_state *new_crtc_state)
9127 {
9128         const struct drm_display_mode *old_mode, *new_mode;
9129
9130         if (!old_crtc_state || !new_crtc_state)
9131                 return false;
9132
9133         old_mode = &old_crtc_state->mode;
9134         new_mode = &new_crtc_state->mode;
9135
9136         if (old_mode->clock       == new_mode->clock &&
9137             old_mode->hdisplay    == new_mode->hdisplay &&
9138             old_mode->vdisplay    == new_mode->vdisplay &&
9139             old_mode->htotal      == new_mode->htotal &&
9140             old_mode->vtotal      != new_mode->vtotal &&
9141             old_mode->hsync_start == new_mode->hsync_start &&
9142             old_mode->vsync_start != new_mode->vsync_start &&
9143             old_mode->hsync_end   == new_mode->hsync_end &&
9144             old_mode->vsync_end   != new_mode->vsync_end &&
9145             old_mode->hskew       == new_mode->hskew &&
9146             old_mode->vscan       == new_mode->vscan &&
9147             (old_mode->vsync_end - old_mode->vsync_start) ==
9148             (new_mode->vsync_end - new_mode->vsync_start))
9149                 return true;
9150
9151         return false;
9152 }
9153
9154 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
9155         u64 num, den, res;
9156         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9157
9158         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9159
9160         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9161         den = (unsigned long long)new_crtc_state->mode.htotal *
9162               (unsigned long long)new_crtc_state->mode.vtotal;
9163
9164         res = div_u64(num, den);
9165         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9166 }
9167
9168 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9169                          struct drm_atomic_state *state,
9170                          struct drm_crtc *crtc,
9171                          struct drm_crtc_state *old_crtc_state,
9172                          struct drm_crtc_state *new_crtc_state,
9173                          bool enable,
9174                          bool *lock_and_validation_needed)
9175 {
9176         struct dm_atomic_state *dm_state = NULL;
9177         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9178         struct dc_stream_state *new_stream;
9179         int ret = 0;
9180
9181         /*
9182          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9183          * update changed items
9184          */
9185         struct amdgpu_crtc *acrtc = NULL;
9186         struct amdgpu_dm_connector *aconnector = NULL;
9187         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9188         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9189
9190         new_stream = NULL;
9191
9192         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9193         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9194         acrtc = to_amdgpu_crtc(crtc);
9195         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9196
9197         /* TODO This hack should go away */
9198         if (aconnector && enable) {
9199                 /* Make sure fake sink is created in plug-in scenario */
9200                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9201                                                             &aconnector->base);
9202                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9203                                                             &aconnector->base);
9204
9205                 if (IS_ERR(drm_new_conn_state)) {
9206                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9207                         goto fail;
9208                 }
9209
9210                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9211                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9212
9213                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9214                         goto skip_modeset;
9215
9216                 new_stream = create_validate_stream_for_sink(aconnector,
9217                                                              &new_crtc_state->mode,
9218                                                              dm_new_conn_state,
9219                                                              dm_old_crtc_state->stream);
9220
9221                 /*
9222                  * we can have no stream on ACTION_SET if a display
9223                  * was disconnected during S3, in this case it is not an
9224                  * error, the OS will be updated after detection, and
9225                  * will do the right thing on next atomic commit
9226                  */
9227
9228                 if (!new_stream) {
9229                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9230                                         __func__, acrtc->base.base.id);
9231                         ret = -ENOMEM;
9232                         goto fail;
9233                 }
9234
9235                 /*
9236                  * TODO: Check VSDB bits to decide whether this should
9237                  * be enabled or not.
9238                  */
9239                 new_stream->triggered_crtc_reset.enabled =
9240                         dm->force_timing_sync;
9241
9242                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9243
9244                 ret = fill_hdr_info_packet(drm_new_conn_state,
9245                                            &new_stream->hdr_static_metadata);
9246                 if (ret)
9247                         goto fail;
9248
9249                 /*
9250                  * If we already removed the old stream from the context
9251                  * (and set the new stream to NULL) then we can't reuse
9252                  * the old stream even if the stream and scaling are unchanged.
9253                  * We'll hit the BUG_ON and black screen.
9254                  *
9255                  * TODO: Refactor this function to allow this check to work
9256                  * in all conditions.
9257                  */
9258                 if (amdgpu_freesync_vid_mode &&
9259                     dm_new_crtc_state->stream &&
9260                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9261                         goto skip_modeset;
9262
9263                 if (dm_new_crtc_state->stream &&
9264                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9265                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9266                         new_crtc_state->mode_changed = false;
9267                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9268                                          new_crtc_state->mode_changed);
9269                 }
9270         }
9271
9272         /* mode_changed flag may get updated above, need to check again */
9273         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9274                 goto skip_modeset;
9275
9276         drm_dbg_state(state->dev,
9277                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
9278                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
9279                 "connectors_changed:%d\n",
9280                 acrtc->crtc_id,
9281                 new_crtc_state->enable,
9282                 new_crtc_state->active,
9283                 new_crtc_state->planes_changed,
9284                 new_crtc_state->mode_changed,
9285                 new_crtc_state->active_changed,
9286                 new_crtc_state->connectors_changed);
9287
9288         /* Remove stream for any changed/disabled CRTC */
9289         if (!enable) {
9290
9291                 if (!dm_old_crtc_state->stream)
9292                         goto skip_modeset;
9293
9294                 /* Unset freesync video if it was active before */
9295                 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9296                         dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9297                         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9298                 }
9299
9300                 /* Now check if we should set freesync video mode */
9301                 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
9302                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9303                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
9304                     is_timing_unchanged_for_freesync(new_crtc_state,
9305                                                      old_crtc_state)) {
9306                         new_crtc_state->mode_changed = false;
9307                         DRM_DEBUG_DRIVER(
9308                                 "Mode change not required for front porch change, "
9309                                 "setting mode_changed to %d",
9310                                 new_crtc_state->mode_changed);
9311
9312                         set_freesync_fixed_config(dm_new_crtc_state);
9313
9314                         goto skip_modeset;
9315                 } else if (amdgpu_freesync_vid_mode && aconnector &&
9316                            is_freesync_video_mode(&new_crtc_state->mode,
9317                                                   aconnector)) {
9318                         struct drm_display_mode *high_mode;
9319
9320                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
9321                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
9322                                 set_freesync_fixed_config(dm_new_crtc_state);
9323                         }
9324                 }
9325
9326                 ret = dm_atomic_get_state(state, &dm_state);
9327                 if (ret)
9328                         goto fail;
9329
9330                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9331                                 crtc->base.id);
9332
9333                 /* i.e. reset mode */
9334                 if (dc_remove_stream_from_ctx(
9335                                 dm->dc,
9336                                 dm_state->context,
9337                                 dm_old_crtc_state->stream) != DC_OK) {
9338                         ret = -EINVAL;
9339                         goto fail;
9340                 }
9341
9342                 dc_stream_release(dm_old_crtc_state->stream);
9343                 dm_new_crtc_state->stream = NULL;
9344
9345                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9346
9347                 *lock_and_validation_needed = true;
9348
9349         } else {/* Add stream for any updated/enabled CRTC */
9350                 /*
9351                  * Quick fix to prevent NULL pointer on new_stream when
9352                  * added MST connectors not found in existing crtc_state in the chained mode
9353                  * TODO: need to dig out the root cause of that
9354                  */
9355                 if (!aconnector)
9356                         goto skip_modeset;
9357
9358                 if (modereset_required(new_crtc_state))
9359                         goto skip_modeset;
9360
9361                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9362                                      dm_old_crtc_state->stream)) {
9363
9364                         WARN_ON(dm_new_crtc_state->stream);
9365
9366                         ret = dm_atomic_get_state(state, &dm_state);
9367                         if (ret)
9368                                 goto fail;
9369
9370                         dm_new_crtc_state->stream = new_stream;
9371
9372                         dc_stream_retain(new_stream);
9373
9374                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9375                                          crtc->base.id);
9376
9377                         if (dc_add_stream_to_ctx(
9378                                         dm->dc,
9379                                         dm_state->context,
9380                                         dm_new_crtc_state->stream) != DC_OK) {
9381                                 ret = -EINVAL;
9382                                 goto fail;
9383                         }
9384
9385                         *lock_and_validation_needed = true;
9386                 }
9387         }
9388
9389 skip_modeset:
9390         /* Release extra reference */
9391         if (new_stream)
9392                 dc_stream_release(new_stream);
9393
9394         /*
9395          * We want to do dc stream updates that do not require a
9396          * full modeset below.
9397          */
9398         if (!(enable && aconnector && new_crtc_state->active))
9399                 return 0;
9400         /*
9401          * Given above conditions, the dc state cannot be NULL because:
9402          * 1. We're in the process of enabling CRTCs (just been added
9403          *    to the dc context, or already is on the context)
9404          * 2. Has a valid connector attached, and
9405          * 3. Is currently active and enabled.
9406          * => The dc stream state currently exists.
9407          */
9408         BUG_ON(dm_new_crtc_state->stream == NULL);
9409
9410         /* Scaling or underscan settings */
9411         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9412                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
9413                 update_stream_scaling_settings(
9414                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9415
9416         /* ABM settings */
9417         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9418
9419         /*
9420          * Color management settings. We also update color properties
9421          * when a modeset is needed, to ensure it gets reprogrammed.
9422          */
9423         if (dm_new_crtc_state->base.color_mgmt_changed ||
9424             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9425                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9426                 if (ret)
9427                         goto fail;
9428         }
9429
9430         /* Update Freesync settings. */
9431         get_freesync_config_for_crtc(dm_new_crtc_state,
9432                                      dm_new_conn_state);
9433
9434         return ret;
9435
9436 fail:
9437         if (new_stream)
9438                 dc_stream_release(new_stream);
9439         return ret;
9440 }
9441
9442 static bool should_reset_plane(struct drm_atomic_state *state,
9443                                struct drm_plane *plane,
9444                                struct drm_plane_state *old_plane_state,
9445                                struct drm_plane_state *new_plane_state)
9446 {
9447         struct drm_plane *other;
9448         struct drm_plane_state *old_other_state, *new_other_state;
9449         struct drm_crtc_state *new_crtc_state;
9450         int i;
9451
9452         /*
9453          * TODO: Remove this hack once the checks below are sufficient
9454          * enough to determine when we need to reset all the planes on
9455          * the stream.
9456          */
9457         if (state->allow_modeset)
9458                 return true;
9459
9460         /* Exit early if we know that we're adding or removing the plane. */
9461         if (old_plane_state->crtc != new_plane_state->crtc)
9462                 return true;
9463
9464         /* old crtc == new_crtc == NULL, plane not in context. */
9465         if (!new_plane_state->crtc)
9466                 return false;
9467
9468         new_crtc_state =
9469                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9470
9471         if (!new_crtc_state)
9472                 return true;
9473
9474         /* CRTC Degamma changes currently require us to recreate planes. */
9475         if (new_crtc_state->color_mgmt_changed)
9476                 return true;
9477
9478         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9479                 return true;
9480
9481         /*
9482          * If there are any new primary or overlay planes being added or
9483          * removed then the z-order can potentially change. To ensure
9484          * correct z-order and pipe acquisition the current DC architecture
9485          * requires us to remove and recreate all existing planes.
9486          *
9487          * TODO: Come up with a more elegant solution for this.
9488          */
9489         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9490                 struct amdgpu_framebuffer *old_afb, *new_afb;
9491                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9492                         continue;
9493
9494                 if (old_other_state->crtc != new_plane_state->crtc &&
9495                     new_other_state->crtc != new_plane_state->crtc)
9496                         continue;
9497
9498                 if (old_other_state->crtc != new_other_state->crtc)
9499                         return true;
9500
9501                 /* Src/dst size and scaling updates. */
9502                 if (old_other_state->src_w != new_other_state->src_w ||
9503                     old_other_state->src_h != new_other_state->src_h ||
9504                     old_other_state->crtc_w != new_other_state->crtc_w ||
9505                     old_other_state->crtc_h != new_other_state->crtc_h)
9506                         return true;
9507
9508                 /* Rotation / mirroring updates. */
9509                 if (old_other_state->rotation != new_other_state->rotation)
9510                         return true;
9511
9512                 /* Blending updates. */
9513                 if (old_other_state->pixel_blend_mode !=
9514                     new_other_state->pixel_blend_mode)
9515                         return true;
9516
9517                 /* Alpha updates. */
9518                 if (old_other_state->alpha != new_other_state->alpha)
9519                         return true;
9520
9521                 /* Colorspace changes. */
9522                 if (old_other_state->color_range != new_other_state->color_range ||
9523                     old_other_state->color_encoding != new_other_state->color_encoding)
9524                         return true;
9525
9526                 /* Framebuffer checks fall at the end. */
9527                 if (!old_other_state->fb || !new_other_state->fb)
9528                         continue;
9529
9530                 /* Pixel format changes can require bandwidth updates. */
9531                 if (old_other_state->fb->format != new_other_state->fb->format)
9532                         return true;
9533
9534                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9535                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9536
9537                 /* Tiling and DCC changes also require bandwidth updates. */
9538                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9539                     old_afb->base.modifier != new_afb->base.modifier)
9540                         return true;
9541         }
9542
9543         return false;
9544 }
9545
9546 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9547                               struct drm_plane_state *new_plane_state,
9548                               struct drm_framebuffer *fb)
9549 {
9550         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9551         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9552         unsigned int pitch;
9553         bool linear;
9554
9555         if (fb->width > new_acrtc->max_cursor_width ||
9556             fb->height > new_acrtc->max_cursor_height) {
9557                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9558                                  new_plane_state->fb->width,
9559                                  new_plane_state->fb->height);
9560                 return -EINVAL;
9561         }
9562         if (new_plane_state->src_w != fb->width << 16 ||
9563             new_plane_state->src_h != fb->height << 16) {
9564                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9565                 return -EINVAL;
9566         }
9567
9568         /* Pitch in pixels */
9569         pitch = fb->pitches[0] / fb->format->cpp[0];
9570
9571         if (fb->width != pitch) {
9572                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9573                                  fb->width, pitch);
9574                 return -EINVAL;
9575         }
9576
9577         switch (pitch) {
9578         case 64:
9579         case 128:
9580         case 256:
9581                 /* FB pitch is supported by cursor plane */
9582                 break;
9583         default:
9584                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9585                 return -EINVAL;
9586         }
9587
9588         /* Core DRM takes care of checking FB modifiers, so we only need to
9589          * check tiling flags when the FB doesn't have a modifier. */
9590         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9591                 if (adev->family < AMDGPU_FAMILY_AI) {
9592                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9593                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9594                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9595                 } else {
9596                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9597                 }
9598                 if (!linear) {
9599                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9600                         return -EINVAL;
9601                 }
9602         }
9603
9604         return 0;
9605 }
9606
9607 static int dm_update_plane_state(struct dc *dc,
9608                                  struct drm_atomic_state *state,
9609                                  struct drm_plane *plane,
9610                                  struct drm_plane_state *old_plane_state,
9611                                  struct drm_plane_state *new_plane_state,
9612                                  bool enable,
9613                                  bool *lock_and_validation_needed,
9614                                  bool *is_top_most_overlay)
9615 {
9616
9617         struct dm_atomic_state *dm_state = NULL;
9618         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9619         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9620         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9621         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9622         struct amdgpu_crtc *new_acrtc;
9623         bool needs_reset;
9624         int ret = 0;
9625
9626
9627         new_plane_crtc = new_plane_state->crtc;
9628         old_plane_crtc = old_plane_state->crtc;
9629         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9630         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9631
9632         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9633                 if (!enable || !new_plane_crtc ||
9634                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9635                         return 0;
9636
9637                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9638
9639                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9640                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9641                         return -EINVAL;
9642                 }
9643
9644                 if (new_plane_state->fb) {
9645                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9646                                                  new_plane_state->fb);
9647                         if (ret)
9648                                 return ret;
9649                 }
9650
9651                 return 0;
9652         }
9653
9654         needs_reset = should_reset_plane(state, plane, old_plane_state,
9655                                          new_plane_state);
9656
9657         /* Remove any changed/removed planes */
9658         if (!enable) {
9659                 if (!needs_reset)
9660                         return 0;
9661
9662                 if (!old_plane_crtc)
9663                         return 0;
9664
9665                 old_crtc_state = drm_atomic_get_old_crtc_state(
9666                                 state, old_plane_crtc);
9667                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9668
9669                 if (!dm_old_crtc_state->stream)
9670                         return 0;
9671
9672                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9673                                 plane->base.id, old_plane_crtc->base.id);
9674
9675                 ret = dm_atomic_get_state(state, &dm_state);
9676                 if (ret)
9677                         return ret;
9678
9679                 if (!dc_remove_plane_from_context(
9680                                 dc,
9681                                 dm_old_crtc_state->stream,
9682                                 dm_old_plane_state->dc_state,
9683                                 dm_state->context)) {
9684
9685                         return -EINVAL;
9686                 }
9687
9688                 if (dm_old_plane_state->dc_state)
9689                         dc_plane_state_release(dm_old_plane_state->dc_state);
9690
9691                 dm_new_plane_state->dc_state = NULL;
9692
9693                 *lock_and_validation_needed = true;
9694
9695         } else { /* Add new planes */
9696                 struct dc_plane_state *dc_new_plane_state;
9697
9698                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9699                         return 0;
9700
9701                 if (!new_plane_crtc)
9702                         return 0;
9703
9704                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9705                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9706
9707                 if (!dm_new_crtc_state->stream)
9708                         return 0;
9709
9710                 if (!needs_reset)
9711                         return 0;
9712
9713                 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9714                 if (ret)
9715                         return ret;
9716
9717                 WARN_ON(dm_new_plane_state->dc_state);
9718
9719                 dc_new_plane_state = dc_create_plane_state(dc);
9720                 if (!dc_new_plane_state)
9721                         return -ENOMEM;
9722
9723                 /* Block top most plane from being a video plane */
9724                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9725                         if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9726                                 return -EINVAL;
9727                         else
9728                                 *is_top_most_overlay = false;
9729                 }
9730
9731                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9732                                  plane->base.id, new_plane_crtc->base.id);
9733
9734                 ret = fill_dc_plane_attributes(
9735                         drm_to_adev(new_plane_crtc->dev),
9736                         dc_new_plane_state,
9737                         new_plane_state,
9738                         new_crtc_state);
9739                 if (ret) {
9740                         dc_plane_state_release(dc_new_plane_state);
9741                         return ret;
9742                 }
9743
9744                 ret = dm_atomic_get_state(state, &dm_state);
9745                 if (ret) {
9746                         dc_plane_state_release(dc_new_plane_state);
9747                         return ret;
9748                 }
9749
9750                 /*
9751                  * Any atomic check errors that occur after this will
9752                  * not need a release. The plane state will be attached
9753                  * to the stream, and therefore part of the atomic
9754                  * state. It'll be released when the atomic state is
9755                  * cleaned.
9756                  */
9757                 if (!dc_add_plane_to_context(
9758                                 dc,
9759                                 dm_new_crtc_state->stream,
9760                                 dc_new_plane_state,
9761                                 dm_state->context)) {
9762
9763                         dc_plane_state_release(dc_new_plane_state);
9764                         return -EINVAL;
9765                 }
9766
9767                 dm_new_plane_state->dc_state = dc_new_plane_state;
9768
9769                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9770
9771                 /* Tell DC to do a full surface update every time there
9772                  * is a plane change. Inefficient, but works for now.
9773                  */
9774                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9775
9776                 *lock_and_validation_needed = true;
9777         }
9778
9779
9780         return ret;
9781 }
9782
9783 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9784                                        int *src_w, int *src_h)
9785 {
9786         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9787         case DRM_MODE_ROTATE_90:
9788         case DRM_MODE_ROTATE_270:
9789                 *src_w = plane_state->src_h >> 16;
9790                 *src_h = plane_state->src_w >> 16;
9791                 break;
9792         case DRM_MODE_ROTATE_0:
9793         case DRM_MODE_ROTATE_180:
9794         default:
9795                 *src_w = plane_state->src_w >> 16;
9796                 *src_h = plane_state->src_h >> 16;
9797                 break;
9798         }
9799 }
9800
9801 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9802                                 struct drm_crtc *crtc,
9803                                 struct drm_crtc_state *new_crtc_state)
9804 {
9805         struct drm_plane *cursor = crtc->cursor, *underlying;
9806         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9807         int i;
9808         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9809         int cursor_src_w, cursor_src_h;
9810         int underlying_src_w, underlying_src_h;
9811
9812         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9813          * cursor per pipe but it's going to inherit the scaling and
9814          * positioning from the underlying pipe. Check the cursor plane's
9815          * blending properties match the underlying planes'. */
9816
9817         new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9818         if (!new_cursor_state || !new_cursor_state->fb) {
9819                 return 0;
9820         }
9821
9822         dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9823         cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9824         cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9825
9826         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9827                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9828                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9829                         continue;
9830
9831                 /* Ignore disabled planes */
9832                 if (!new_underlying_state->fb)
9833                         continue;
9834
9835                 dm_get_oriented_plane_size(new_underlying_state,
9836                                            &underlying_src_w, &underlying_src_h);
9837                 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9838                 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9839
9840                 if (cursor_scale_w != underlying_scale_w ||
9841                     cursor_scale_h != underlying_scale_h) {
9842                         drm_dbg_atomic(crtc->dev,
9843                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9844                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9845                         return -EINVAL;
9846                 }
9847
9848                 /* If this plane covers the whole CRTC, no need to check planes underneath */
9849                 if (new_underlying_state->crtc_x <= 0 &&
9850                     new_underlying_state->crtc_y <= 0 &&
9851                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9852                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9853                         break;
9854         }
9855
9856         return 0;
9857 }
9858
9859 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9860 {
9861         struct drm_connector *connector;
9862         struct drm_connector_state *conn_state, *old_conn_state;
9863         struct amdgpu_dm_connector *aconnector = NULL;
9864         int i;
9865         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9866                 if (!conn_state->crtc)
9867                         conn_state = old_conn_state;
9868
9869                 if (conn_state->crtc != crtc)
9870                         continue;
9871
9872                 aconnector = to_amdgpu_dm_connector(connector);
9873                 if (!aconnector->mst_output_port || !aconnector->mst_root)
9874                         aconnector = NULL;
9875                 else
9876                         break;
9877         }
9878
9879         if (!aconnector)
9880                 return 0;
9881
9882         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
9883 }
9884
9885 /**
9886  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9887  *
9888  * @dev: The DRM device
9889  * @state: The atomic state to commit
9890  *
9891  * Validate that the given atomic state is programmable by DC into hardware.
9892  * This involves constructing a &struct dc_state reflecting the new hardware
9893  * state we wish to commit, then querying DC to see if it is programmable. It's
9894  * important not to modify the existing DC state. Otherwise, atomic_check
9895  * may unexpectedly commit hardware changes.
9896  *
9897  * When validating the DC state, it's important that the right locks are
9898  * acquired. For full updates case which removes/adds/updates streams on one
9899  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9900  * that any such full update commit will wait for completion of any outstanding
9901  * flip using DRMs synchronization events.
9902  *
9903  * Note that DM adds the affected connectors for all CRTCs in state, when that
9904  * might not seem necessary. This is because DC stream creation requires the
9905  * DC sink, which is tied to the DRM connector state. Cleaning this up should
9906  * be possible but non-trivial - a possible TODO item.
9907  *
9908  * Return: -Error code if validation failed.
9909  */
9910 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9911                                   struct drm_atomic_state *state)
9912 {
9913         struct amdgpu_device *adev = drm_to_adev(dev);
9914         struct dm_atomic_state *dm_state = NULL;
9915         struct dc *dc = adev->dm.dc;
9916         struct drm_connector *connector;
9917         struct drm_connector_state *old_con_state, *new_con_state;
9918         struct drm_crtc *crtc;
9919         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9920         struct drm_plane *plane;
9921         struct drm_plane_state *old_plane_state, *new_plane_state;
9922         enum dc_status status;
9923         int ret, i;
9924         bool lock_and_validation_needed = false;
9925         bool is_top_most_overlay = true;
9926         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9927         struct drm_dp_mst_topology_mgr *mgr;
9928         struct drm_dp_mst_topology_state *mst_state;
9929         struct dsc_mst_fairness_vars vars[MAX_PIPES];
9930
9931         trace_amdgpu_dm_atomic_check_begin(state);
9932
9933         ret = drm_atomic_helper_check_modeset(dev, state);
9934         if (ret) {
9935                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9936                 goto fail;
9937         }
9938
9939         /* Check connector changes */
9940         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9941                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9942                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9943
9944                 /* Skip connectors that are disabled or part of modeset already. */
9945                 if (!new_con_state->crtc)
9946                         continue;
9947
9948                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9949                 if (IS_ERR(new_crtc_state)) {
9950                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
9951                         ret = PTR_ERR(new_crtc_state);
9952                         goto fail;
9953                 }
9954
9955                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
9956                     dm_old_con_state->scaling != dm_new_con_state->scaling)
9957                         new_crtc_state->connectors_changed = true;
9958         }
9959
9960         if (dc_resource_is_dsc_encoding_supported(dc)) {
9961                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9962                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9963                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
9964                                 if (ret) {
9965                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
9966                                         goto fail;
9967                                 }
9968                         }
9969                 }
9970         }
9971         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9972                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9973
9974                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
9975                     !new_crtc_state->color_mgmt_changed &&
9976                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9977                         dm_old_crtc_state->dsc_force_changed == false)
9978                         continue;
9979
9980                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
9981                 if (ret) {
9982                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
9983                         goto fail;
9984                 }
9985
9986                 if (!new_crtc_state->enable)
9987                         continue;
9988
9989                 ret = drm_atomic_add_affected_connectors(state, crtc);
9990                 if (ret) {
9991                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
9992                         goto fail;
9993                 }
9994
9995                 ret = drm_atomic_add_affected_planes(state, crtc);
9996                 if (ret) {
9997                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
9998                         goto fail;
9999                 }
10000
10001                 if (dm_old_crtc_state->dsc_force_changed)
10002                         new_crtc_state->mode_changed = true;
10003         }
10004
10005         /*
10006          * Add all primary and overlay planes on the CRTC to the state
10007          * whenever a plane is enabled to maintain correct z-ordering
10008          * and to enable fast surface updates.
10009          */
10010         drm_for_each_crtc(crtc, dev) {
10011                 bool modified = false;
10012
10013                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10014                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10015                                 continue;
10016
10017                         if (new_plane_state->crtc == crtc ||
10018                             old_plane_state->crtc == crtc) {
10019                                 modified = true;
10020                                 break;
10021                         }
10022                 }
10023
10024                 if (!modified)
10025                         continue;
10026
10027                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
10028                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10029                                 continue;
10030
10031                         new_plane_state =
10032                                 drm_atomic_get_plane_state(state, plane);
10033
10034                         if (IS_ERR(new_plane_state)) {
10035                                 ret = PTR_ERR(new_plane_state);
10036                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
10037                                 goto fail;
10038                         }
10039                 }
10040         }
10041
10042         /*
10043          * DC consults the zpos (layer_index in DC terminology) to determine the
10044          * hw plane on which to enable the hw cursor (see
10045          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
10046          * atomic state, so call drm helper to normalize zpos.
10047          */
10048         ret = drm_atomic_normalize_zpos(dev, state);
10049         if (ret) {
10050                 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10051                 goto fail;
10052         }
10053
10054         /* Remove exiting planes if they are modified */
10055         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10056                 ret = dm_update_plane_state(dc, state, plane,
10057                                             old_plane_state,
10058                                             new_plane_state,
10059                                             false,
10060                                             &lock_and_validation_needed,
10061                                             &is_top_most_overlay);
10062                 if (ret) {
10063                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10064                         goto fail;
10065                 }
10066         }
10067
10068         /* Disable all crtcs which require disable */
10069         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10070                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10071                                            old_crtc_state,
10072                                            new_crtc_state,
10073                                            false,
10074                                            &lock_and_validation_needed);
10075                 if (ret) {
10076                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10077                         goto fail;
10078                 }
10079         }
10080
10081         /* Enable all crtcs which require enable */
10082         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10083                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10084                                            old_crtc_state,
10085                                            new_crtc_state,
10086                                            true,
10087                                            &lock_and_validation_needed);
10088                 if (ret) {
10089                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10090                         goto fail;
10091                 }
10092         }
10093
10094         /* Add new/modified planes */
10095         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10096                 ret = dm_update_plane_state(dc, state, plane,
10097                                             old_plane_state,
10098                                             new_plane_state,
10099                                             true,
10100                                             &lock_and_validation_needed,
10101                                             &is_top_most_overlay);
10102                 if (ret) {
10103                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10104                         goto fail;
10105                 }
10106         }
10107
10108         if (dc_resource_is_dsc_encoding_supported(dc)) {
10109                 ret = pre_validate_dsc(state, &dm_state, vars);
10110                 if (ret != 0)
10111                         goto fail;
10112         }
10113
10114         /* Run this here since we want to validate the streams we created */
10115         ret = drm_atomic_helper_check_planes(dev, state);
10116         if (ret) {
10117                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10118                 goto fail;
10119         }
10120
10121         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10122                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10123                 if (dm_new_crtc_state->mpo_requested)
10124                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10125         }
10126
10127         /* Check cursor planes scaling */
10128         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10129                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10130                 if (ret) {
10131                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10132                         goto fail;
10133                 }
10134         }
10135
10136         if (state->legacy_cursor_update) {
10137                 /*
10138                  * This is a fast cursor update coming from the plane update
10139                  * helper, check if it can be done asynchronously for better
10140                  * performance.
10141                  */
10142                 state->async_update =
10143                         !drm_atomic_helper_async_check(dev, state);
10144
10145                 /*
10146                  * Skip the remaining global validation if this is an async
10147                  * update. Cursor updates can be done without affecting
10148                  * state or bandwidth calcs and this avoids the performance
10149                  * penalty of locking the private state object and
10150                  * allocating a new dc_state.
10151                  */
10152                 if (state->async_update)
10153                         return 0;
10154         }
10155
10156         /* Check scaling and underscan changes*/
10157         /* TODO Removed scaling changes validation due to inability to commit
10158          * new stream into context w\o causing full reset. Need to
10159          * decide how to handle.
10160          */
10161         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10162                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10163                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10164                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10165
10166                 /* Skip any modesets/resets */
10167                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10168                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10169                         continue;
10170
10171                 /* Skip any thing not scale or underscan changes */
10172                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10173                         continue;
10174
10175                 lock_and_validation_needed = true;
10176         }
10177
10178         /* set the slot info for each mst_state based on the link encoding format */
10179         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10180                 struct amdgpu_dm_connector *aconnector;
10181                 struct drm_connector *connector;
10182                 struct drm_connector_list_iter iter;
10183                 u8 link_coding_cap;
10184
10185                 drm_connector_list_iter_begin(dev, &iter);
10186                 drm_for_each_connector_iter(connector, &iter) {
10187                         if (connector->index == mst_state->mgr->conn_base_id) {
10188                                 aconnector = to_amdgpu_dm_connector(connector);
10189                                 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10190                                 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10191
10192                                 break;
10193                         }
10194                 }
10195                 drm_connector_list_iter_end(&iter);
10196         }
10197
10198         /**
10199          * Streams and planes are reset when there are changes that affect
10200          * bandwidth. Anything that affects bandwidth needs to go through
10201          * DC global validation to ensure that the configuration can be applied
10202          * to hardware.
10203          *
10204          * We have to currently stall out here in atomic_check for outstanding
10205          * commits to finish in this case because our IRQ handlers reference
10206          * DRM state directly - we can end up disabling interrupts too early
10207          * if we don't.
10208          *
10209          * TODO: Remove this stall and drop DM state private objects.
10210          */
10211         if (lock_and_validation_needed) {
10212                 ret = dm_atomic_get_state(state, &dm_state);
10213                 if (ret) {
10214                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10215                         goto fail;
10216                 }
10217
10218                 ret = do_aquire_global_lock(dev, state);
10219                 if (ret) {
10220                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10221                         goto fail;
10222                 }
10223
10224                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10225                 if (ret) {
10226                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10227                         ret = -EINVAL;
10228                         goto fail;
10229                 }
10230
10231                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10232                 if (ret) {
10233                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10234                         goto fail;
10235                 }
10236
10237                 /*
10238                  * Perform validation of MST topology in the state:
10239                  * We need to perform MST atomic check before calling
10240                  * dc_validate_global_state(), or there is a chance
10241                  * to get stuck in an infinite loop and hang eventually.
10242                  */
10243                 ret = drm_dp_mst_atomic_check(state);
10244                 if (ret) {
10245                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10246                         goto fail;
10247                 }
10248                 status = dc_validate_global_state(dc, dm_state->context, true);
10249                 if (status != DC_OK) {
10250                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10251                                        dc_status_to_str(status), status);
10252                         ret = -EINVAL;
10253                         goto fail;
10254                 }
10255         } else {
10256                 /*
10257                  * The commit is a fast update. Fast updates shouldn't change
10258                  * the DC context, affect global validation, and can have their
10259                  * commit work done in parallel with other commits not touching
10260                  * the same resource. If we have a new DC context as part of
10261                  * the DM atomic state from validation we need to free it and
10262                  * retain the existing one instead.
10263                  *
10264                  * Furthermore, since the DM atomic state only contains the DC
10265                  * context and can safely be annulled, we can free the state
10266                  * and clear the associated private object now to free
10267                  * some memory and avoid a possible use-after-free later.
10268                  */
10269
10270                 for (i = 0; i < state->num_private_objs; i++) {
10271                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10272
10273                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10274                                 int j = state->num_private_objs-1;
10275
10276                                 dm_atomic_destroy_state(obj,
10277                                                 state->private_objs[i].state);
10278
10279                                 /* If i is not at the end of the array then the
10280                                  * last element needs to be moved to where i was
10281                                  * before the array can safely be truncated.
10282                                  */
10283                                 if (i != j)
10284                                         state->private_objs[i] =
10285                                                 state->private_objs[j];
10286
10287                                 state->private_objs[j].ptr = NULL;
10288                                 state->private_objs[j].state = NULL;
10289                                 state->private_objs[j].old_state = NULL;
10290                                 state->private_objs[j].new_state = NULL;
10291
10292                                 state->num_private_objs = j;
10293                                 break;
10294                         }
10295                 }
10296         }
10297
10298         /* Store the overall update type for use later in atomic check. */
10299         for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
10300                 struct dm_crtc_state *dm_new_crtc_state =
10301                         to_dm_crtc_state(new_crtc_state);
10302
10303                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10304                                                          UPDATE_TYPE_FULL :
10305                                                          UPDATE_TYPE_FAST;
10306         }
10307
10308         /* Must be success */
10309         WARN_ON(ret);
10310
10311         trace_amdgpu_dm_atomic_check_finish(state, ret);
10312
10313         return ret;
10314
10315 fail:
10316         if (ret == -EDEADLK)
10317                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10318         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10319                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10320         else
10321                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
10322
10323         trace_amdgpu_dm_atomic_check_finish(state, ret);
10324
10325         return ret;
10326 }
10327
10328 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10329                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10330 {
10331         u8 dpcd_data;
10332         bool capable = false;
10333
10334         if (amdgpu_dm_connector->dc_link &&
10335                 dm_helpers_dp_read_dpcd(
10336                                 NULL,
10337                                 amdgpu_dm_connector->dc_link,
10338                                 DP_DOWN_STREAM_PORT_COUNT,
10339                                 &dpcd_data,
10340                                 sizeof(dpcd_data))) {
10341                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10342         }
10343
10344         return capable;
10345 }
10346
10347 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10348                 unsigned int offset,
10349                 unsigned int total_length,
10350                 u8 *data,
10351                 unsigned int length,
10352                 struct amdgpu_hdmi_vsdb_info *vsdb)
10353 {
10354         bool res;
10355         union dmub_rb_cmd cmd;
10356         struct dmub_cmd_send_edid_cea *input;
10357         struct dmub_cmd_edid_cea_output *output;
10358
10359         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10360                 return false;
10361
10362         memset(&cmd, 0, sizeof(cmd));
10363
10364         input = &cmd.edid_cea.data.input;
10365
10366         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10367         cmd.edid_cea.header.sub_type = 0;
10368         cmd.edid_cea.header.payload_bytes =
10369                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10370         input->offset = offset;
10371         input->length = length;
10372         input->cea_total_length = total_length;
10373         memcpy(input->payload, data, length);
10374
10375         res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
10376         if (!res) {
10377                 DRM_ERROR("EDID CEA parser failed\n");
10378                 return false;
10379         }
10380
10381         output = &cmd.edid_cea.data.output;
10382
10383         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10384                 if (!output->ack.success) {
10385                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
10386                                         output->ack.offset);
10387                 }
10388         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10389                 if (!output->amd_vsdb.vsdb_found)
10390                         return false;
10391
10392                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10393                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10394                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10395                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10396         } else {
10397                 DRM_WARN("Unknown EDID CEA parser results\n");
10398                 return false;
10399         }
10400
10401         return true;
10402 }
10403
10404 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10405                 u8 *edid_ext, int len,
10406                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10407 {
10408         int i;
10409
10410         /* send extension block to DMCU for parsing */
10411         for (i = 0; i < len; i += 8) {
10412                 bool res;
10413                 int offset;
10414
10415                 /* send 8 bytes a time */
10416                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10417                         return false;
10418
10419                 if (i+8 == len) {
10420                         /* EDID block sent completed, expect result */
10421                         int version, min_rate, max_rate;
10422
10423                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10424                         if (res) {
10425                                 /* amd vsdb found */
10426                                 vsdb_info->freesync_supported = 1;
10427                                 vsdb_info->amd_vsdb_version = version;
10428                                 vsdb_info->min_refresh_rate_hz = min_rate;
10429                                 vsdb_info->max_refresh_rate_hz = max_rate;
10430                                 return true;
10431                         }
10432                         /* not amd vsdb */
10433                         return false;
10434                 }
10435
10436                 /* check for ack*/
10437                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10438                 if (!res)
10439                         return false;
10440         }
10441
10442         return false;
10443 }
10444
10445 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10446                 u8 *edid_ext, int len,
10447                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10448 {
10449         int i;
10450
10451         /* send extension block to DMCU for parsing */
10452         for (i = 0; i < len; i += 8) {
10453                 /* send 8 bytes a time */
10454                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10455                         return false;
10456         }
10457
10458         return vsdb_info->freesync_supported;
10459 }
10460
10461 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10462                 u8 *edid_ext, int len,
10463                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10464 {
10465         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10466         bool ret;
10467
10468         mutex_lock(&adev->dm.dc_lock);
10469         if (adev->dm.dmub_srv)
10470                 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10471         else
10472                 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10473         mutex_unlock(&adev->dm.dc_lock);
10474         return ret;
10475 }
10476
10477 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10478                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10479 {
10480         u8 *edid_ext = NULL;
10481         int i;
10482         bool valid_vsdb_found = false;
10483
10484         /*----- drm_find_cea_extension() -----*/
10485         /* No EDID or EDID extensions */
10486         if (edid == NULL || edid->extensions == 0)
10487                 return -ENODEV;
10488
10489         /* Find CEA extension */
10490         for (i = 0; i < edid->extensions; i++) {
10491                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10492                 if (edid_ext[0] == CEA_EXT)
10493                         break;
10494         }
10495
10496         if (i == edid->extensions)
10497                 return -ENODEV;
10498
10499         /*----- cea_db_offsets() -----*/
10500         if (edid_ext[0] != CEA_EXT)
10501                 return -ENODEV;
10502
10503         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10504
10505         return valid_vsdb_found ? i : -ENODEV;
10506 }
10507
10508 /**
10509  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10510  *
10511  * @connector: Connector to query.
10512  * @edid: EDID from monitor
10513  *
10514  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10515  * track of some of the display information in the internal data struct used by
10516  * amdgpu_dm. This function checks which type of connector we need to set the
10517  * FreeSync parameters.
10518  */
10519 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10520                                     struct edid *edid)
10521 {
10522         int i = 0;
10523         struct detailed_timing *timing;
10524         struct detailed_non_pixel *data;
10525         struct detailed_data_monitor_range *range;
10526         struct amdgpu_dm_connector *amdgpu_dm_connector =
10527                         to_amdgpu_dm_connector(connector);
10528         struct dm_connector_state *dm_con_state = NULL;
10529         struct dc_sink *sink;
10530
10531         struct drm_device *dev = connector->dev;
10532         struct amdgpu_device *adev = drm_to_adev(dev);
10533         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10534         bool freesync_capable = false;
10535         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10536
10537         if (!connector->state) {
10538                 DRM_ERROR("%s - Connector has no state", __func__);
10539                 goto update;
10540         }
10541
10542         sink = amdgpu_dm_connector->dc_sink ?
10543                 amdgpu_dm_connector->dc_sink :
10544                 amdgpu_dm_connector->dc_em_sink;
10545
10546         if (!edid || !sink) {
10547                 dm_con_state = to_dm_connector_state(connector->state);
10548
10549                 amdgpu_dm_connector->min_vfreq = 0;
10550                 amdgpu_dm_connector->max_vfreq = 0;
10551                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10552                 connector->display_info.monitor_range.min_vfreq = 0;
10553                 connector->display_info.monitor_range.max_vfreq = 0;
10554                 freesync_capable = false;
10555
10556                 goto update;
10557         }
10558
10559         dm_con_state = to_dm_connector_state(connector->state);
10560
10561         if (!adev->dm.freesync_module)
10562                 goto update;
10563
10564         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10565                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10566                 bool edid_check_required = false;
10567
10568                 if (edid) {
10569                         edid_check_required = is_dp_capable_without_timing_msa(
10570                                                 adev->dm.dc,
10571                                                 amdgpu_dm_connector);
10572                 }
10573
10574                 if (edid_check_required == true && (edid->version > 1 ||
10575                    (edid->version == 1 && edid->revision > 1))) {
10576                         for (i = 0; i < 4; i++) {
10577
10578                                 timing  = &edid->detailed_timings[i];
10579                                 data    = &timing->data.other_data;
10580                                 range   = &data->data.range;
10581                                 /*
10582                                  * Check if monitor has continuous frequency mode
10583                                  */
10584                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10585                                         continue;
10586                                 /*
10587                                  * Check for flag range limits only. If flag == 1 then
10588                                  * no additional timing information provided.
10589                                  * Default GTF, GTF Secondary curve and CVT are not
10590                                  * supported
10591                                  */
10592                                 if (range->flags != 1)
10593                                         continue;
10594
10595                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10596                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10597                                 amdgpu_dm_connector->pixel_clock_mhz =
10598                                         range->pixel_clock_mhz * 10;
10599
10600                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10601                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10602
10603                                 break;
10604                         }
10605
10606                         if (amdgpu_dm_connector->max_vfreq -
10607                             amdgpu_dm_connector->min_vfreq > 10) {
10608
10609                                 freesync_capable = true;
10610                         }
10611                 }
10612         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10613                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10614                 if (i >= 0 && vsdb_info.freesync_supported) {
10615                         timing  = &edid->detailed_timings[i];
10616                         data    = &timing->data.other_data;
10617
10618                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10619                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10620                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10621                                 freesync_capable = true;
10622
10623                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10624                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10625                 }
10626         }
10627
10628         as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10629
10630         if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10631                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10632                 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10633
10634                         amdgpu_dm_connector->pack_sdp_v1_3 = true;
10635                         amdgpu_dm_connector->as_type = as_type;
10636                         amdgpu_dm_connector->vsdb_info = vsdb_info;
10637
10638                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10639                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10640                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10641                                 freesync_capable = true;
10642
10643                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10644                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10645                 }
10646         }
10647
10648 update:
10649         if (dm_con_state)
10650                 dm_con_state->freesync_capable = freesync_capable;
10651
10652         if (connector->vrr_capable_property)
10653                 drm_connector_set_vrr_capable_property(connector,
10654                                                        freesync_capable);
10655 }
10656
10657 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10658 {
10659         struct amdgpu_device *adev = drm_to_adev(dev);
10660         struct dc *dc = adev->dm.dc;
10661         int i;
10662
10663         mutex_lock(&adev->dm.dc_lock);
10664         if (dc->current_state) {
10665                 for (i = 0; i < dc->current_state->stream_count; ++i)
10666                         dc->current_state->streams[i]
10667                                 ->triggered_crtc_reset.enabled =
10668                                 adev->dm.force_timing_sync;
10669
10670                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10671                 dc_trigger_sync(dc, dc->current_state);
10672         }
10673         mutex_unlock(&adev->dm.dc_lock);
10674 }
10675
10676 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10677                        u32 value, const char *func_name)
10678 {
10679 #ifdef DM_CHECK_ADDR_0
10680         if (address == 0) {
10681                 DC_ERR("invalid register write. address = 0");
10682                 return;
10683         }
10684 #endif
10685         cgs_write_register(ctx->cgs_device, address, value);
10686         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10687 }
10688
10689 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10690                           const char *func_name)
10691 {
10692         u32 value;
10693 #ifdef DM_CHECK_ADDR_0
10694         if (address == 0) {
10695                 DC_ERR("invalid register read; address = 0\n");
10696                 return 0;
10697         }
10698 #endif
10699
10700         if (ctx->dmub_srv &&
10701             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10702             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10703                 ASSERT(false);
10704                 return 0;
10705         }
10706
10707         value = cgs_read_register(ctx->cgs_device, address);
10708
10709         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10710
10711         return value;
10712 }
10713
10714 int amdgpu_dm_process_dmub_aux_transfer_sync(
10715                 struct dc_context *ctx,
10716                 unsigned int link_index,
10717                 struct aux_payload *payload,
10718                 enum aux_return_code_type *operation_result)
10719 {
10720         struct amdgpu_device *adev = ctx->driver_context;
10721         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10722         int ret = -1;
10723
10724         mutex_lock(&adev->dm.dpia_aux_lock);
10725         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10726                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10727                 goto out;
10728         }
10729
10730         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10731                 DRM_ERROR("wait_for_completion_timeout timeout!");
10732                 *operation_result = AUX_RET_ERROR_TIMEOUT;
10733                 goto out;
10734         }
10735
10736         if (p_notify->result != AUX_RET_SUCCESS) {
10737                 /*
10738                  * Transient states before tunneling is enabled could
10739                  * lead to this error. We can ignore this for now.
10740                  */
10741                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10742                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10743                                         payload->address, payload->length,
10744                                         p_notify->result);
10745                 }
10746                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10747                 goto out;
10748         }
10749
10750
10751         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10752         if (!payload->write && p_notify->aux_reply.length &&
10753                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10754
10755                 if (payload->length != p_notify->aux_reply.length) {
10756                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10757                                 p_notify->aux_reply.length,
10758                                         payload->address, payload->length);
10759                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10760                         goto out;
10761                 }
10762
10763                 memcpy(payload->data, p_notify->aux_reply.data,
10764                                 p_notify->aux_reply.length);
10765         }
10766
10767         /* success */
10768         ret = p_notify->aux_reply.length;
10769         *operation_result = p_notify->result;
10770 out:
10771         reinit_completion(&adev->dm.dmub_aux_transfer_done);
10772         mutex_unlock(&adev->dm.dpia_aux_lock);
10773         return ret;
10774 }
10775
10776 int amdgpu_dm_process_dmub_set_config_sync(
10777                 struct dc_context *ctx,
10778                 unsigned int link_index,
10779                 struct set_config_cmd_payload *payload,
10780                 enum set_config_status *operation_result)
10781 {
10782         struct amdgpu_device *adev = ctx->driver_context;
10783         bool is_cmd_complete;
10784         int ret;
10785
10786         mutex_lock(&adev->dm.dpia_aux_lock);
10787         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10788                         link_index, payload, adev->dm.dmub_notify);
10789
10790         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10791                 ret = 0;
10792                 *operation_result = adev->dm.dmub_notify->sc_status;
10793         } else {
10794                 DRM_ERROR("wait_for_completion_timeout timeout!");
10795                 ret = -1;
10796                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10797         }
10798
10799         if (!is_cmd_complete)
10800                 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10801         mutex_unlock(&adev->dm.dpia_aux_lock);
10802         return ret;
10803 }
10804
10805 /*
10806  * Check whether seamless boot is supported.
10807  *
10808  * So far we only support seamless boot on CHIP_VANGOGH.
10809  * If everything goes well, we may consider expanding
10810  * seamless boot to other ASICs.
10811  */
10812 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10813 {
10814         switch (adev->ip_versions[DCE_HWIP][0]) {
10815         case IP_VERSION(3, 0, 1):
10816                 if (!adev->mman.keep_stolen_vga_memory)
10817                         return true;
10818                 break;
10819         default:
10820                 break;
10821         }
10822
10823         return false;
10824 }
10825
10826 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
10827 {
10828         return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
10829 }
10830
10831 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
10832 {
10833         return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);
10834 }