drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "link_enc_cfg.h"
  32 #include "dc/inc/core_types.h"
  33 #include "dal_asic_id.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "dc/inc/hw/dmcu.h"
  36 #include "dc/inc/hw/abm.h"
  37 #include "dc/dc_dmub_srv.h"
  38 #include "dc/dc_edid_parser.h"
  39 #include "dc/dc_stat.h"
  40 #include "amdgpu_dm_trace.h"
  41 #include "dpcd_defs.h"
  42 #include "link/protocols/link_dpcd.h"
  43 #include "link_service_types.h"
  44 #include "link/protocols/link_dp_capability.h"
  45 #include "link/protocols/link_ddc.h"
  46
  47 #include "vid.h"
  48 #include "amdgpu.h"
  49 #include "amdgpu_display.h"
  50 #include "amdgpu_ucode.h"
  51 #include "atom.h"
  52 #include "amdgpu_dm.h"
  53 #include "amdgpu_dm_plane.h"
  54 #include "amdgpu_dm_crtc.h"
  55 #include "amdgpu_dm_hdcp.h"
  56 #include <drm/display/drm_hdcp_helper.h>
  57 #include "amdgpu_pm.h"
  58 #include "amdgpu_atombios.h"
  59
  60 #include "amd_shared.h"
  61 #include "amdgpu_dm_irq.h"
  62 #include "dm_helpers.h"
  63 #include "amdgpu_dm_mst_types.h"
  64 #if defined(CONFIG_DEBUG_FS)
  65 #include "amdgpu_dm_debugfs.h"
  66 #endif
  67 #include "amdgpu_dm_psr.h"
  68
  69 #include "ivsrcid/ivsrcid_vislands30.h"
  70
  71 #include <linux/backlight.h>
  72 #include <linux/module.h>
  73 #include <linux/moduleparam.h>
  74 #include <linux/types.h>
  75 #include <linux/pm_runtime.h>
  76 #include <linux/pci.h>
  77 #include <linux/firmware.h>
  78 #include <linux/component.h>
  79 #include <linux/dmi.h>
  80
  81 #include <drm/display/drm_dp_mst_helper.h>
  82 #include <drm/display/drm_hdmi_helper.h>
  83 #include <drm/drm_atomic.h>
  84 #include <drm/drm_atomic_uapi.h>
  85 #include <drm/drm_atomic_helper.h>
  86 #include <drm/drm_blend.h>
  87 #include <drm/drm_fourcc.h>
  88 #include <drm/drm_edid.h>
  89 #include <drm/drm_vblank.h>
  90 #include <drm/drm_audio_component.h>
  91 #include <drm/drm_gem_atomic_helper.h>
  92 #include <drm/drm_plane_helper.h>
  93
  94 #include <acpi/video.h>
  95
  96 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  97
  98 #include "dcn/dcn_1_0_offset.h"
  99 #include "dcn/dcn_1_0_sh_mask.h"
 100 #include "soc15_hw_ip.h"
 101 #include "soc15_common.h"
 102 #include "vega10_ip_offset.h"
 103
 104 #include "gc/gc_11_0_0_offset.h"
 105 #include "gc/gc_11_0_0_sh_mask.h"
 106
 107 #include "modules/inc/mod_freesync.h"
 108 #include "modules/power/power_helpers.h"
 109
 110 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 111 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 112 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 113 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 114 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 115 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 116 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 117 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 118 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 119 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 120 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 121 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 122 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 123 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 124 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 125 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 126 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 127 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 128 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 129 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 130 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 131 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 132
 133 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 134 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 135 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 137
 138 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 139 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 140
 141 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 142 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 143
 144 /* Number of bytes in PSP header for firmware. */
 145 #define PSP_HEADER_BYTES 0x100
 146
 147 /* Number of bytes in PSP footer for firmware. */
 148 #define PSP_FOOTER_BYTES 0x100
 149
 150 /**
 151  * DOC: overview
 152  *
 153  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 154  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 155  * requests into DC requests, and DC responses into DRM responses.
 156  *
 157  * The root control structure is &struct amdgpu_display_manager.
 158  */
 159
 160 /* basic init/fini API */
 161 static int amdgpu_dm_init(struct amdgpu_device *adev);
 162 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 163 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 164
 165 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 166 {
 167         switch (link->dpcd_caps.dongle_type) {
 168         case DISPLAY_DONGLE_NONE:
 169                 return DRM_MODE_SUBCONNECTOR_Native;
 170         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 171                 return DRM_MODE_SUBCONNECTOR_VGA;
 172         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 173         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 174                 return DRM_MODE_SUBCONNECTOR_DVID;
 175         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 176         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 177                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 178         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 179         default:
 180                 return DRM_MODE_SUBCONNECTOR_Unknown;
 181         }
 182 }
 183
 184 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 185 {
 186         struct dc_link *link = aconnector->dc_link;
 187         struct drm_connector *connector = &aconnector->base;
 188         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 189
 190         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 191                 return;
 192
 193         if (aconnector->dc_sink)
 194                 subconnector = get_subconnector_type(link);
 195
 196         drm_object_property_set_value(&connector->base,
 197                         connector->dev->mode_config.dp_subconnector_property,
 198                         subconnector);
 199 }
 200
 201 /*
 202  * initializes drm_device display related structures, based on the information
 203  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 204  * drm_encoder, drm_mode_config
 205  *
 206  * Returns 0 on success
 207  */
 208 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 209 /* removes and deallocates the drm structures, created by the above function */
 210 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 211
 212 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 213                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 214                                     u32 link_index,
 215                                     struct amdgpu_encoder *amdgpu_encoder);
 216 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 217                                   struct amdgpu_encoder *aencoder,
 218                                   uint32_t link_index);
 219
 220 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 221
 222 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 223
 224 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 225                                   struct drm_atomic_state *state);
 226
 227 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 228 static void handle_hpd_rx_irq(void *param);
 229
 230 static bool
 231 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 232                                  struct drm_crtc_state *new_crtc_state);
 233 /*
 234  * dm_vblank_get_counter
 235  *
 236  * @brief
 237  * Get counter for number of vertical blanks
 238  *
 239  * @param
 240  * struct amdgpu_device *adev - [in] desired amdgpu device
 241  * int disp_idx - [in] which CRTC to get the counter from
 242  *
 243  * @return
 244  * Counter for vertical blanks
 245  */
 246 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 247 {
 248         if (crtc >= adev->mode_info.num_crtc)
 249                 return 0;
 250         else {
 251                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 252
 253                 if (acrtc->dm_irq_params.stream == NULL) {
 254                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 255                                   crtc);
 256                         return 0;
 257                 }
 258
 259                 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 260         }
 261 }
 262
 263 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 264                                   u32 *vbl, u32 *position)
 265 {
 266         u32 v_blank_start, v_blank_end, h_position, v_position;
 267
 268         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 269                 return -EINVAL;
 270         else {
 271                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 272
 273                 if (acrtc->dm_irq_params.stream ==  NULL) {
 274                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 275                                   crtc);
 276                         return 0;
 277                 }
 278
 279                 /*
 280                  * TODO rework base driver to use values directly.
 281                  * for now parse it back into reg-format
 282                  */
 283                 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 284                                          &v_blank_start,
 285                                          &v_blank_end,
 286                                          &h_position,
 287                                          &v_position);
 288
 289                 *position = v_position | (h_position << 16);
 290                 *vbl = v_blank_start | (v_blank_end << 16);
 291         }
 292
 293         return 0;
 294 }
 295
 296 static bool dm_is_idle(void *handle)
 297 {
 298         /* XXX todo */
 299         return true;
 300 }
 301
 302 static int dm_wait_for_idle(void *handle)
 303 {
 304         /* XXX todo */
 305         return 0;
 306 }
 307
 308 static bool dm_check_soft_reset(void *handle)
 309 {
 310         return false;
 311 }
 312
 313 static int dm_soft_reset(void *handle)
 314 {
 315         /* XXX todo */
 316         return 0;
 317 }
 318
 319 static struct amdgpu_crtc *
 320 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 321                      int otg_inst)
 322 {
 323         struct drm_device *dev = adev_to_drm(adev);
 324         struct drm_crtc *crtc;
 325         struct amdgpu_crtc *amdgpu_crtc;
 326
 327         if (WARN_ON(otg_inst == -1))
 328                 return adev->mode_info.crtcs[0];
 329
 330         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 331                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 332
 333                 if (amdgpu_crtc->otg_inst == otg_inst)
 334                         return amdgpu_crtc;
 335         }
 336
 337         return NULL;
 338 }
 339
 340 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 341                                               struct dm_crtc_state *new_state)
 342 {
 343         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 344                 return true;
 345         else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
 346                 return true;
 347         else
 348                 return false;
 349 }
 350
 351 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
 352                                         int planes_count)
 353 {
 354         int i, j;
 355
 356         for (i = 0, j = planes_count - 1; i < j; i++, j--)
 357                 swap(array_of_surface_update[i], array_of_surface_update[j]);
 358 }
 359
 360 /**
 361  * update_planes_and_stream_adapter() - Send planes to be updated in DC
 362  *
 363  * DC has a generic way to update planes and stream via
 364  * dc_update_planes_and_stream function; however, DM might need some
 365  * adjustments and preparation before calling it. This function is a wrapper
 366  * for the dc_update_planes_and_stream that does any required configuration
 367  * before passing control to DC.
 368  *
 369  * @dc: Display Core control structure
 370  * @update_type: specify whether it is FULL/MEDIUM/FAST update
 371  * @planes_count: planes count to update
 372  * @stream: stream state
 373  * @stream_update: stream update
 374  * @array_of_surface_update: dc surface update pointer
 375  *
 376  */
 377 static inline bool update_planes_and_stream_adapter(struct dc *dc,
 378                                                     int update_type,
 379                                                     int planes_count,
 380                                                     struct dc_stream_state *stream,
 381                                                     struct dc_stream_update *stream_update,
 382                                                     struct dc_surface_update *array_of_surface_update)
 383 {
 384         reverse_planes_order(array_of_surface_update, planes_count);
 385
 386         /*
 387          * Previous frame finished and HW is ready for optimization.
 388          */
 389         if (update_type == UPDATE_TYPE_FAST)
 390                 dc_post_update_surfaces_to_stream(dc);
 391
 392         return dc_update_planes_and_stream(dc,
 393                                            array_of_surface_update,
 394                                            planes_count,
 395                                            stream,
 396                                            stream_update);
 397 }
 398
 399 /**
 400  * dm_pflip_high_irq() - Handle pageflip interrupt
 401  * @interrupt_params: ignored
 402  *
 403  * Handles the pageflip interrupt by notifying all interested parties
 404  * that the pageflip has been completed.
 405  */
 406 static void dm_pflip_high_irq(void *interrupt_params)
 407 {
 408         struct amdgpu_crtc *amdgpu_crtc;
 409         struct common_irq_params *irq_params = interrupt_params;
 410         struct amdgpu_device *adev = irq_params->adev;
 411         unsigned long flags;
 412         struct drm_pending_vblank_event *e;
 413         u32 vpos, hpos, v_blank_start, v_blank_end;
 414         bool vrr_active;
 415
 416         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 417
 418         /* IRQ could occur when in initial stage */
 419         /* TODO work and BO cleanup */
 420         if (amdgpu_crtc == NULL) {
 421                 DC_LOG_PFLIP("CRTC is null, returning.\n");
 422                 return;
 423         }
 424
 425         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 426
 427         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 428                 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 429                                                  amdgpu_crtc->pflip_status,
 430                                                  AMDGPU_FLIP_SUBMITTED,
 431                                                  amdgpu_crtc->crtc_id,
 432                                                  amdgpu_crtc);
 433                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 434                 return;
 435         }
 436
 437         /* page flip completed. */
 438         e = amdgpu_crtc->event;
 439         amdgpu_crtc->event = NULL;
 440
 441         WARN_ON(!e);
 442
 443         vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
 444
 445         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 446         if (!vrr_active ||
 447             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 448                                       &v_blank_end, &hpos, &vpos) ||
 449             (vpos < v_blank_start)) {
 450                 /* Update to correct count and vblank timestamp if racing with
 451                  * vblank irq. This also updates to the correct vblank timestamp
 452                  * even in VRR mode, as scanout is past the front-porch atm.
 453                  */
 454                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 455
 456                 /* Wake up userspace by sending the pageflip event with proper
 457                  * count and timestamp of vblank of flip completion.
 458                  */
 459                 if (e) {
 460                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 461
 462                         /* Event sent, so done with vblank for this flip */
 463                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 464                 }
 465         } else if (e) {
 466                 /* VRR active and inside front-porch: vblank count and
 467                  * timestamp for pageflip event will only be up to date after
 468                  * drm_crtc_handle_vblank() has been executed from late vblank
 469                  * irq handler after start of back-porch (vline 0). We queue the
 470                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 471                  * updated timestamp and count, once it runs after us.
 472                  *
 473                  * We need to open-code this instead of using the helper
 474                  * drm_crtc_arm_vblank_event(), as that helper would
 475                  * call drm_crtc_accurate_vblank_count(), which we must
 476                  * not call in VRR mode while we are in front-porch!
 477                  */
 478
 479                 /* sequence will be replaced by real count during send-out. */
 480                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 481                 e->pipe = amdgpu_crtc->crtc_id;
 482
 483                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 484                 e = NULL;
 485         }
 486
 487         /* Keep track of vblank of this flip for flip throttling. We use the
 488          * cooked hw counter, as that one incremented at start of this vblank
 489          * of pageflip completion, so last_flip_vblank is the forbidden count
 490          * for queueing new pageflips if vsync + VRR is enabled.
 491          */
 492         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 493                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 494
 495         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 496         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 497
 498         DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 499                      amdgpu_crtc->crtc_id, amdgpu_crtc,
 500                      vrr_active, (int) !e);
 501 }
 502
 503 static void dm_vupdate_high_irq(void *interrupt_params)
 504 {
 505         struct common_irq_params *irq_params = interrupt_params;
 506         struct amdgpu_device *adev = irq_params->adev;
 507         struct amdgpu_crtc *acrtc;
 508         struct drm_device *drm_dev;
 509         struct drm_vblank_crtc *vblank;
 510         ktime_t frame_duration_ns, previous_timestamp;
 511         unsigned long flags;
 512         int vrr_active;
 513
 514         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 515
 516         if (acrtc) {
 517                 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 518                 drm_dev = acrtc->base.dev;
 519                 vblank = &drm_dev->vblank[acrtc->base.index];
 520                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 521                 frame_duration_ns = vblank->time - previous_timestamp;
 522
 523                 if (frame_duration_ns > 0) {
 524                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 525                                                 frame_duration_ns,
 526                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 527                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 528                 }
 529
 530                 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
 531                               acrtc->crtc_id,
 532                               vrr_active);
 533
 534                 /* Core vblank handling is done here after end of front-porch in
 535                  * vrr mode, as vblank timestamping will give valid results
 536                  * while now done after front-porch. This will also deliver
 537                  * page-flip completion events that have been queued to us
 538                  * if a pageflip happened inside front-porch.
 539                  */
 540                 if (vrr_active) {
 541                         amdgpu_dm_crtc_handle_vblank(acrtc);
 542
 543                         /* BTR processing for pre-DCE12 ASICs */
 544                         if (acrtc->dm_irq_params.stream &&
 545                             adev->family < AMDGPU_FAMILY_AI) {
 546                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 547                                 mod_freesync_handle_v_update(
 548                                     adev->dm.freesync_module,
 549                                     acrtc->dm_irq_params.stream,
 550                                     &acrtc->dm_irq_params.vrr_params);
 551
 552                                 dc_stream_adjust_vmin_vmax(
 553                                     adev->dm.dc,
 554                                     acrtc->dm_irq_params.stream,
 555                                     &acrtc->dm_irq_params.vrr_params.adjust);
 556                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 557                         }
 558                 }
 559         }
 560 }
 561
 562 /**
 563  * dm_crtc_high_irq() - Handles CRTC interrupt
 564  * @interrupt_params: used for determining the CRTC instance
 565  *
 566  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 567  * event handler.
 568  */
 569 static void dm_crtc_high_irq(void *interrupt_params)
 570 {
 571         struct common_irq_params *irq_params = interrupt_params;
 572         struct amdgpu_device *adev = irq_params->adev;
 573         struct amdgpu_crtc *acrtc;
 574         unsigned long flags;
 575         int vrr_active;
 576
 577         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 578         if (!acrtc)
 579                 return;
 580
 581         vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 582
 583         DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 584                       vrr_active, acrtc->dm_irq_params.active_planes);
 585
 586         /**
 587          * Core vblank handling at start of front-porch is only possible
 588          * in non-vrr mode, as only there vblank timestamping will give
 589          * valid results while done in front-porch. Otherwise defer it
 590          * to dm_vupdate_high_irq after end of front-porch.
 591          */
 592         if (!vrr_active)
 593                 amdgpu_dm_crtc_handle_vblank(acrtc);
 594
 595         /**
 596          * Following stuff must happen at start of vblank, for crc
 597          * computation and below-the-range btr support in vrr mode.
 598          */
 599         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 600
 601         /* BTR updates need to happen before VUPDATE on Vega and above. */
 602         if (adev->family < AMDGPU_FAMILY_AI)
 603                 return;
 604
 605         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 606
 607         if (acrtc->dm_irq_params.stream &&
 608             acrtc->dm_irq_params.vrr_params.supported &&
 609             acrtc->dm_irq_params.freesync_config.state ==
 610                     VRR_STATE_ACTIVE_VARIABLE) {
 611                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 612                                              acrtc->dm_irq_params.stream,
 613                                              &acrtc->dm_irq_params.vrr_params);
 614
 615                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 616                                            &acrtc->dm_irq_params.vrr_params.adjust);
 617         }
 618
 619         /*
 620          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 621          * In that case, pageflip completion interrupts won't fire and pageflip
 622          * completion events won't get delivered. Prevent this by sending
 623          * pending pageflip events from here if a flip is still pending.
 624          *
 625          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 626          * avoid race conditions between flip programming and completion,
 627          * which could cause too early flip completion events.
 628          */
 629         if (adev->family >= AMDGPU_FAMILY_RV &&
 630             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 631             acrtc->dm_irq_params.active_planes == 0) {
 632                 if (acrtc->event) {
 633                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 634                         acrtc->event = NULL;
 635                         drm_crtc_vblank_put(&acrtc->base);
 636                 }
 637                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 638         }
 639
 640         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 641 }
 642
 643 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 644 /**
 645  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 646  * DCN generation ASICs
 647  * @interrupt_params: interrupt parameters
 648  *
 649  * Used to set crc window/read out crc value at vertical line 0 position
 650  */
 651 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 652 {
 653         struct common_irq_params *irq_params = interrupt_params;
 654         struct amdgpu_device *adev = irq_params->adev;
 655         struct amdgpu_crtc *acrtc;
 656
 657         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 658
 659         if (!acrtc)
 660                 return;
 661
 662         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 663 }
 664 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 665
 666 /**
 667  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 668  * @adev: amdgpu_device pointer
 669  * @notify: dmub notification structure
 670  *
 671  * Dmub AUX or SET_CONFIG command completion processing callback
 672  * Copies dmub notification to DM which is to be read by AUX command.
 673  * issuing thread and also signals the event to wake up the thread.
 674  */
 675 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 676                                         struct dmub_notification *notify)
 677 {
 678         if (adev->dm.dmub_notify)
 679                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 680         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 681                 complete(&adev->dm.dmub_aux_transfer_done);
 682 }
 683
 684 /**
 685  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 686  * @adev: amdgpu_device pointer
 687  * @notify: dmub notification structure
 688  *
 689  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 690  * ink index and calls helper to do the processing.
 691  */
 692 static void dmub_hpd_callback(struct amdgpu_device *adev,
 693                               struct dmub_notification *notify)
 694 {
 695         struct amdgpu_dm_connector *aconnector;
 696         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 697         struct drm_connector *connector;
 698         struct drm_connector_list_iter iter;
 699         struct dc_link *link;
 700         u8 link_index = 0;
 701         struct drm_device *dev;
 702
 703         if (adev == NULL)
 704                 return;
 705
 706         if (notify == NULL) {
 707                 DRM_ERROR("DMUB HPD callback notification was NULL");
 708                 return;
 709         }
 710
 711         if (notify->link_index > adev->dm.dc->link_count) {
 712                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 713                 return;
 714         }
 715
 716         link_index = notify->link_index;
 717         link = adev->dm.dc->links[link_index];
 718         dev = adev->dm.ddev;
 719
 720         drm_connector_list_iter_begin(dev, &iter);
 721         drm_for_each_connector_iter(connector, &iter) {
 722                 aconnector = to_amdgpu_dm_connector(connector);
 723                 if (link && aconnector->dc_link == link) {
 724                         if (notify->type == DMUB_NOTIFICATION_HPD)
 725                                 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 726                         else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 727                                 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
 728                         else
 729                                 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
 730                                                 notify->type, link_index);
 731
 732                         hpd_aconnector = aconnector;
 733                         break;
 734                 }
 735         }
 736         drm_connector_list_iter_end(&iter);
 737
 738         if (hpd_aconnector) {
 739                 if (notify->type == DMUB_NOTIFICATION_HPD)
 740                         handle_hpd_irq_helper(hpd_aconnector);
 741                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 742                         handle_hpd_rx_irq(hpd_aconnector);
 743         }
 744 }
 745
 746 /**
 747  * register_dmub_notify_callback - Sets callback for DMUB notify
 748  * @adev: amdgpu_device pointer
 749  * @type: Type of dmub notification
 750  * @callback: Dmub interrupt callback function
 751  * @dmub_int_thread_offload: offload indicator
 752  *
 753  * API to register a dmub callback handler for a dmub notification
 754  * Also sets indicator whether callback processing to be offloaded.
 755  * to dmub interrupt handling thread
 756  * Return: true if successfully registered, false if there is existing registration
 757  */
 758 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 759                                           enum dmub_notification_type type,
 760                                           dmub_notify_interrupt_callback_t callback,
 761                                           bool dmub_int_thread_offload)
 762 {
 763         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 764                 adev->dm.dmub_callback[type] = callback;
 765                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 766         } else
 767                 return false;
 768
 769         return true;
 770 }
 771
 772 static void dm_handle_hpd_work(struct work_struct *work)
 773 {
 774         struct dmub_hpd_work *dmub_hpd_wrk;
 775
 776         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 777
 778         if (!dmub_hpd_wrk->dmub_notify) {
 779                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 780                 return;
 781         }
 782
 783         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 784                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 785                 dmub_hpd_wrk->dmub_notify);
 786         }
 787
 788         kfree(dmub_hpd_wrk->dmub_notify);
 789         kfree(dmub_hpd_wrk);
 790
 791 }
 792
 793 #define DMUB_TRACE_MAX_READ 64
 794 /**
 795  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 796  * @interrupt_params: used for determining the Outbox instance
 797  *
 798  * Handles the Outbox Interrupt
 799  * event handler.
 800  */
 801 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 802 {
 803         struct dmub_notification notify;
 804         struct common_irq_params *irq_params = interrupt_params;
 805         struct amdgpu_device *adev = irq_params->adev;
 806         struct amdgpu_display_manager *dm = &adev->dm;
 807         struct dmcub_trace_buf_entry entry = { 0 };
 808         u32 count = 0;
 809         struct dmub_hpd_work *dmub_hpd_wrk;
 810         struct dc_link *plink = NULL;
 811
 812         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 813                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 814
 815                 do {
 816                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 817                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 818                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 819                                 continue;
 820                         }
 821                         if (!dm->dmub_callback[notify.type]) {
 822                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 823                                 continue;
 824                         }
 825                         if (dm->dmub_thread_offload[notify.type] == true) {
 826                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 827                                 if (!dmub_hpd_wrk) {
 828                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 829                                         return;
 830                                 }
 831                                 dmub_hpd_wrk->dmub_notify = kmemdup(&notify, sizeof(struct dmub_notification),
 832                                                                     GFP_ATOMIC);
 833                                 if (!dmub_hpd_wrk->dmub_notify) {
 834                                         kfree(dmub_hpd_wrk);
 835                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 836                                         return;
 837                                 }
 838                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 839                                 dmub_hpd_wrk->adev = adev;
 840                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 841                                         plink = adev->dm.dc->links[notify.link_index];
 842                                         if (plink) {
 843                                                 plink->hpd_status =
 844                                                         notify.hpd_status == DP_HPD_PLUG;
 845                                         }
 846                                 }
 847                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 848                         } else {
 849                                 dm->dmub_callback[notify.type](adev, &notify);
 850                         }
 851                 } while (notify.pending_notification);
 852         }
 853
 854
 855         do {
 856                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 857                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 858                                                         entry.param0, entry.param1);
 859
 860                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 861                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 862                 } else
 863                         break;
 864
 865                 count++;
 866
 867         } while (count <= DMUB_TRACE_MAX_READ);
 868
 869         if (count > DMUB_TRACE_MAX_READ)
 870                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 871 }
 872
 873 static int dm_set_clockgating_state(void *handle,
 874                   enum amd_clockgating_state state)
 875 {
 876         return 0;
 877 }
 878
 879 static int dm_set_powergating_state(void *handle,
 880                   enum amd_powergating_state state)
 881 {
 882         return 0;
 883 }
 884
 885 /* Prototypes of private functions */
 886 static int dm_early_init(void* handle);
 887
 888 /* Allocate memory for FBC compressed data  */
 889 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 890 {
 891         struct drm_device *dev = connector->dev;
 892         struct amdgpu_device *adev = drm_to_adev(dev);
 893         struct dm_compressor_info *compressor = &adev->dm.compressor;
 894         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 895         struct drm_display_mode *mode;
 896         unsigned long max_size = 0;
 897
 898         if (adev->dm.dc->fbc_compressor == NULL)
 899                 return;
 900
 901         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 902                 return;
 903
 904         if (compressor->bo_ptr)
 905                 return;
 906
 907
 908         list_for_each_entry(mode, &connector->modes, head) {
 909                 if (max_size < mode->htotal * mode->vtotal)
 910                         max_size = mode->htotal * mode->vtotal;
 911         }
 912
 913         if (max_size) {
 914                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 915                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 916                             &compressor->gpu_addr, &compressor->cpu_addr);
 917
 918                 if (r)
 919                         DRM_ERROR("DM: Failed to initialize FBC\n");
 920                 else {
 921                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 922                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 923                 }
 924
 925         }
 926
 927 }
 928
 929 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 930                                           int pipe, bool *enabled,
 931                                           unsigned char *buf, int max_bytes)
 932 {
 933         struct drm_device *dev = dev_get_drvdata(kdev);
 934         struct amdgpu_device *adev = drm_to_adev(dev);
 935         struct drm_connector *connector;
 936         struct drm_connector_list_iter conn_iter;
 937         struct amdgpu_dm_connector *aconnector;
 938         int ret = 0;
 939
 940         *enabled = false;
 941
 942         mutex_lock(&adev->dm.audio_lock);
 943
 944         drm_connector_list_iter_begin(dev, &conn_iter);
 945         drm_for_each_connector_iter(connector, &conn_iter) {
 946                 aconnector = to_amdgpu_dm_connector(connector);
 947                 if (aconnector->audio_inst != port)
 948                         continue;
 949
 950                 *enabled = true;
 951                 ret = drm_eld_size(connector->eld);
 952                 memcpy(buf, connector->eld, min(max_bytes, ret));
 953
 954                 break;
 955         }
 956         drm_connector_list_iter_end(&conn_iter);
 957
 958         mutex_unlock(&adev->dm.audio_lock);
 959
 960         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 961
 962         return ret;
 963 }
 964
 965 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 966         .get_eld = amdgpu_dm_audio_component_get_eld,
 967 };
 968
 969 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 970                                        struct device *hda_kdev, void *data)
 971 {
 972         struct drm_device *dev = dev_get_drvdata(kdev);
 973         struct amdgpu_device *adev = drm_to_adev(dev);
 974         struct drm_audio_component *acomp = data;
 975
 976         acomp->ops = &amdgpu_dm_audio_component_ops;
 977         acomp->dev = kdev;
 978         adev->dm.audio_component = acomp;
 979
 980         return 0;
 981 }
 982
 983 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 984                                           struct device *hda_kdev, void *data)
 985 {
 986         struct drm_device *dev = dev_get_drvdata(kdev);
 987         struct amdgpu_device *adev = drm_to_adev(dev);
 988         struct drm_audio_component *acomp = data;
 989
 990         acomp->ops = NULL;
 991         acomp->dev = NULL;
 992         adev->dm.audio_component = NULL;
 993 }
 994
 995 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 996         .bind   = amdgpu_dm_audio_component_bind,
 997         .unbind = amdgpu_dm_audio_component_unbind,
 998 };
 999
1000 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1001 {
1002         int i, ret;
1003
1004         if (!amdgpu_audio)
1005                 return 0;
1006
1007         adev->mode_info.audio.enabled = true;
1008
1009         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1010
1011         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1012                 adev->mode_info.audio.pin[i].channels = -1;
1013                 adev->mode_info.audio.pin[i].rate = -1;
1014                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1015                 adev->mode_info.audio.pin[i].status_bits = 0;
1016                 adev->mode_info.audio.pin[i].category_code = 0;
1017                 adev->mode_info.audio.pin[i].connected = false;
1018                 adev->mode_info.audio.pin[i].id =
1019                         adev->dm.dc->res_pool->audios[i]->inst;
1020                 adev->mode_info.audio.pin[i].offset = 0;
1021         }
1022
1023         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1024         if (ret < 0)
1025                 return ret;
1026
1027         adev->dm.audio_registered = true;
1028
1029         return 0;
1030 }
1031
1032 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1033 {
1034         if (!amdgpu_audio)
1035                 return;
1036
1037         if (!adev->mode_info.audio.enabled)
1038                 return;
1039
1040         if (adev->dm.audio_registered) {
1041                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1042                 adev->dm.audio_registered = false;
1043         }
1044
1045         /* TODO: Disable audio? */
1046
1047         adev->mode_info.audio.enabled = false;
1048 }
1049
1050 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1051 {
1052         struct drm_audio_component *acomp = adev->dm.audio_component;
1053
1054         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1055                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1056
1057                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1058                                                  pin, -1);
1059         }
1060 }
1061
1062 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1063 {
1064         const struct dmcub_firmware_header_v1_0 *hdr;
1065         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1066         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1067         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1068         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1069         struct abm *abm = adev->dm.dc->res_pool->abm;
1070         struct dmub_srv_hw_params hw_params;
1071         enum dmub_status status;
1072         const unsigned char *fw_inst_const, *fw_bss_data;
1073         u32 i, fw_inst_const_size, fw_bss_data_size;
1074         bool has_hw_support;
1075
1076         if (!dmub_srv)
1077                 /* DMUB isn't supported on the ASIC. */
1078                 return 0;
1079
1080         if (!fb_info) {
1081                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1082                 return -EINVAL;
1083         }
1084
1085         if (!dmub_fw) {
1086                 /* Firmware required for DMUB support. */
1087                 DRM_ERROR("No firmware provided for DMUB.\n");
1088                 return -EINVAL;
1089         }
1090
1091         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1092         if (status != DMUB_STATUS_OK) {
1093                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1094                 return -EINVAL;
1095         }
1096
1097         if (!has_hw_support) {
1098                 DRM_INFO("DMUB unsupported on ASIC\n");
1099                 return 0;
1100         }
1101
1102         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1103         status = dmub_srv_hw_reset(dmub_srv);
1104         if (status != DMUB_STATUS_OK)
1105                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1106
1107         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1108
1109         fw_inst_const = dmub_fw->data +
1110                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1111                         PSP_HEADER_BYTES;
1112
1113         fw_bss_data = dmub_fw->data +
1114                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1115                       le32_to_cpu(hdr->inst_const_bytes);
1116
1117         /* Copy firmware and bios info into FB memory. */
1118         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1119                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1120
1121         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1122
1123         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1124          * amdgpu_ucode_init_single_fw will load dmub firmware
1125          * fw_inst_const part to cw0; otherwise, the firmware back door load
1126          * will be done by dm_dmub_hw_init
1127          */
1128         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1129                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1130                                 fw_inst_const_size);
1131         }
1132
1133         if (fw_bss_data_size)
1134                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1135                        fw_bss_data, fw_bss_data_size);
1136
1137         /* Copy firmware bios info into FB memory. */
1138         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1139                adev->bios_size);
1140
1141         /* Reset regions that need to be reset. */
1142         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1143         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1144
1145         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1146                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1147
1148         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1149                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1150
1151         /* Initialize hardware. */
1152         memset(&hw_params, 0, sizeof(hw_params));
1153         hw_params.fb_base = adev->gmc.fb_start;
1154         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1155
1156         /* backdoor load firmware and trigger dmub running */
1157         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1158                 hw_params.load_inst_const = true;
1159
1160         if (dmcu)
1161                 hw_params.psp_version = dmcu->psp_version;
1162
1163         for (i = 0; i < fb_info->num_fb; ++i)
1164                 hw_params.fb[i] = &fb_info->fb[i];
1165
1166         switch (adev->ip_versions[DCE_HWIP][0]) {
1167         case IP_VERSION(3, 1, 3):
1168         case IP_VERSION(3, 1, 4):
1169                 hw_params.dpia_supported = true;
1170                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1171                 break;
1172         default:
1173                 break;
1174         }
1175
1176         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1177         if (status != DMUB_STATUS_OK) {
1178                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1179                 return -EINVAL;
1180         }
1181
1182         /* Wait for firmware load to finish. */
1183         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1184         if (status != DMUB_STATUS_OK)
1185                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1186
1187         /* Init DMCU and ABM if available. */
1188         if (dmcu && abm) {
1189                 dmcu->funcs->dmcu_init(dmcu);
1190                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1191         }
1192
1193         if (!adev->dm.dc->ctx->dmub_srv)
1194                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1195         if (!adev->dm.dc->ctx->dmub_srv) {
1196                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1197                 return -ENOMEM;
1198         }
1199
1200         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1201                  adev->dm.dmcub_fw_version);
1202
1203         return 0;
1204 }
1205
1206 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1207 {
1208         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1209         enum dmub_status status;
1210         bool init;
1211
1212         if (!dmub_srv) {
1213                 /* DMUB isn't supported on the ASIC. */
1214                 return;
1215         }
1216
1217         status = dmub_srv_is_hw_init(dmub_srv, &init);
1218         if (status != DMUB_STATUS_OK)
1219                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1220
1221         if (status == DMUB_STATUS_OK && init) {
1222                 /* Wait for firmware load to finish. */
1223                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1224                 if (status != DMUB_STATUS_OK)
1225                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1226         } else {
1227                 /* Perform the full hardware initialization. */
1228                 dm_dmub_hw_init(adev);
1229         }
1230 }
1231
1232 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1233 {
1234         u64 pt_base;
1235         u32 logical_addr_low;
1236         u32 logical_addr_high;
1237         u32 agp_base, agp_bot, agp_top;
1238         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1239
1240         memset(pa_config, 0, sizeof(*pa_config));
1241
1242         agp_base = 0;
1243         agp_bot = adev->gmc.agp_start >> 24;
1244         agp_top = adev->gmc.agp_end >> 24;
1245
1246         /* AGP aperture is disabled */
1247         if (agp_bot == agp_top) {
1248                 logical_addr_low = adev->gmc.fb_start >> 18;
1249                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1250                         /*
1251                          * Raven2 has a HW issue that it is unable to use the vram which
1252                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1253                          * workaround that increase system aperture high address (add 1)
1254                          * to get rid of the VM fault and hardware hang.
1255                          */
1256                         logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1257                 else
1258                         logical_addr_high = adev->gmc.fb_end >> 18;
1259         } else {
1260                 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1261                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1262                         /*
1263                          * Raven2 has a HW issue that it is unable to use the vram which
1264                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1265                          * workaround that increase system aperture high address (add 1)
1266                          * to get rid of the VM fault and hardware hang.
1267                          */
1268                         logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1269                 else
1270                         logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1271         }
1272
1273         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1274
1275         page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1276         page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1277         page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1278         page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1279         page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1280         page_table_base.low_part = lower_32_bits(pt_base);
1281
1282         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1283         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1284
1285         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1286         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1287         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1288
1289         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1290         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1291         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1292
1293         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1294         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1295         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1296
1297         pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1298
1299 }
1300
1301 static void force_connector_state(
1302         struct amdgpu_dm_connector *aconnector,
1303         enum drm_connector_force force_state)
1304 {
1305         struct drm_connector *connector = &aconnector->base;
1306
1307         mutex_lock(&connector->dev->mode_config.mutex);
1308         aconnector->base.force = force_state;
1309         mutex_unlock(&connector->dev->mode_config.mutex);
1310
1311         mutex_lock(&aconnector->hpd_lock);
1312         drm_kms_helper_connector_hotplug_event(connector);
1313         mutex_unlock(&aconnector->hpd_lock);
1314 }
1315
1316 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1317 {
1318         struct hpd_rx_irq_offload_work *offload_work;
1319         struct amdgpu_dm_connector *aconnector;
1320         struct dc_link *dc_link;
1321         struct amdgpu_device *adev;
1322         enum dc_connection_type new_connection_type = dc_connection_none;
1323         unsigned long flags;
1324         union test_response test_response;
1325
1326         memset(&test_response, 0, sizeof(test_response));
1327
1328         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1329         aconnector = offload_work->offload_wq->aconnector;
1330
1331         if (!aconnector) {
1332                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1333                 goto skip;
1334         }
1335
1336         adev = drm_to_adev(aconnector->base.dev);
1337         dc_link = aconnector->dc_link;
1338
1339         mutex_lock(&aconnector->hpd_lock);
1340         if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1341                 DRM_ERROR("KMS: Failed to detect connector\n");
1342         mutex_unlock(&aconnector->hpd_lock);
1343
1344         if (new_connection_type == dc_connection_none)
1345                 goto skip;
1346
1347         if (amdgpu_in_reset(adev))
1348                 goto skip;
1349
1350         mutex_lock(&adev->dm.dc_lock);
1351         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1352                 dc_link_dp_handle_automated_test(dc_link);
1353
1354                 if (aconnector->timing_changed) {
1355                         /* force connector disconnect and reconnect */
1356                         force_connector_state(aconnector, DRM_FORCE_OFF);
1357                         msleep(100);
1358                         force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1359                 }
1360
1361                 test_response.bits.ACK = 1;
1362
1363                 core_link_write_dpcd(
1364                 dc_link,
1365                 DP_TEST_RESPONSE,
1366                 &test_response.raw,
1367                 sizeof(test_response));
1368         }
1369         else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1370                         dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1371                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1372                 /* offload_work->data is from handle_hpd_rx_irq->
1373                  * schedule_hpd_rx_offload_work.this is defer handle
1374                  * for hpd short pulse. upon here, link status may be
1375                  * changed, need get latest link status from dpcd
1376                  * registers. if link status is good, skip run link
1377                  * training again.
1378                  */
1379                 union hpd_irq_data irq_data;
1380
1381                 memset(&irq_data, 0, sizeof(irq_data));
1382
1383                 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1384                  * request be added to work queue if link lost at end of dc_link_
1385                  * dp_handle_link_loss
1386                  */
1387                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1388                 offload_work->offload_wq->is_handling_link_loss = false;
1389                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1390
1391                 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1392                         dc_link_check_link_loss_status(dc_link, &irq_data))
1393                         dc_link_dp_handle_link_loss(dc_link);
1394         }
1395         mutex_unlock(&adev->dm.dc_lock);
1396
1397 skip:
1398         kfree(offload_work);
1399
1400 }
1401
1402 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1403 {
1404         int max_caps = dc->caps.max_links;
1405         int i = 0;
1406         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1407
1408         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1409
1410         if (!hpd_rx_offload_wq)
1411                 return NULL;
1412
1413
1414         for (i = 0; i < max_caps; i++) {
1415                 hpd_rx_offload_wq[i].wq =
1416                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1417
1418                 if (hpd_rx_offload_wq[i].wq == NULL) {
1419                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1420                         goto out_err;
1421                 }
1422
1423                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1424         }
1425
1426         return hpd_rx_offload_wq;
1427
1428 out_err:
1429         for (i = 0; i < max_caps; i++) {
1430                 if (hpd_rx_offload_wq[i].wq)
1431                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1432         }
1433         kfree(hpd_rx_offload_wq);
1434         return NULL;
1435 }
1436
1437 struct amdgpu_stutter_quirk {
1438         u16 chip_vendor;
1439         u16 chip_device;
1440         u16 subsys_vendor;
1441         u16 subsys_device;
1442         u8 revision;
1443 };
1444
1445 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1446         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1447         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1448         { 0, 0, 0, 0, 0 },
1449 };
1450
1451 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1452 {
1453         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1454
1455         while (p && p->chip_device != 0) {
1456                 if (pdev->vendor == p->chip_vendor &&
1457                     pdev->device == p->chip_device &&
1458                     pdev->subsystem_vendor == p->subsys_vendor &&
1459                     pdev->subsystem_device == p->subsys_device &&
1460                     pdev->revision == p->revision) {
1461                         return true;
1462                 }
1463                 ++p;
1464         }
1465         return false;
1466 }
1467
1468 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1469         {
1470                 .matches = {
1471                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1472                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1473                 },
1474         },
1475         {
1476                 .matches = {
1477                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1478                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1479                 },
1480         },
1481         {
1482                 .matches = {
1483                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1484                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1485                 },
1486         },
1487         {
1488                 .matches = {
1489                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1490                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1491                 },
1492         },
1493         {
1494                 .matches = {
1495                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1496                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1497                 },
1498         },
1499         {
1500                 .matches = {
1501                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1502                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1503                 },
1504         },
1505         {
1506                 .matches = {
1507                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1508                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1509                 },
1510         },
1511         {
1512                 .matches = {
1513                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1514                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1515                 },
1516         },
1517         {
1518                 .matches = {
1519                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1520                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1521                 },
1522         },
1523         {}
1524         /* TODO: refactor this from a fixed table to a dynamic option */
1525 };
1526
1527 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1528 {
1529         const struct dmi_system_id *dmi_id;
1530
1531         dm->aux_hpd_discon_quirk = false;
1532
1533         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1534         if (dmi_id) {
1535                 dm->aux_hpd_discon_quirk = true;
1536                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1537         }
1538 }
1539
1540 static int amdgpu_dm_init(struct amdgpu_device *adev)
1541 {
1542         struct dc_init_data init_data;
1543         struct dc_callback_init init_params;
1544         int r;
1545
1546         adev->dm.ddev = adev_to_drm(adev);
1547         adev->dm.adev = adev;
1548
1549         /* Zero all the fields */
1550         memset(&init_data, 0, sizeof(init_data));
1551         memset(&init_params, 0, sizeof(init_params));
1552
1553         mutex_init(&adev->dm.dpia_aux_lock);
1554         mutex_init(&adev->dm.dc_lock);
1555         mutex_init(&adev->dm.audio_lock);
1556
1557         if(amdgpu_dm_irq_init(adev)) {
1558                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1559                 goto error;
1560         }
1561
1562         init_data.asic_id.chip_family = adev->family;
1563
1564         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1565         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1566         init_data.asic_id.chip_id = adev->pdev->device;
1567
1568         init_data.asic_id.vram_width = adev->gmc.vram_width;
1569         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1570         init_data.asic_id.atombios_base_address =
1571                 adev->mode_info.atom_context->bios;
1572
1573         init_data.driver = adev;
1574
1575         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1576
1577         if (!adev->dm.cgs_device) {
1578                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1579                 goto error;
1580         }
1581
1582         init_data.cgs_device = adev->dm.cgs_device;
1583
1584         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1585
1586         switch (adev->ip_versions[DCE_HWIP][0]) {
1587         case IP_VERSION(2, 1, 0):
1588                 switch (adev->dm.dmcub_fw_version) {
1589                 case 0: /* development */
1590                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1591                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1592                         init_data.flags.disable_dmcu = false;
1593                         break;
1594                 default:
1595                         init_data.flags.disable_dmcu = true;
1596                 }
1597                 break;
1598         case IP_VERSION(2, 0, 3):
1599                 init_data.flags.disable_dmcu = true;
1600                 break;
1601         default:
1602                 break;
1603         }
1604
1605         switch (adev->asic_type) {
1606         case CHIP_CARRIZO:
1607         case CHIP_STONEY:
1608                 init_data.flags.gpu_vm_support = true;
1609                 break;
1610         default:
1611                 switch (adev->ip_versions[DCE_HWIP][0]) {
1612                 case IP_VERSION(1, 0, 0):
1613                 case IP_VERSION(1, 0, 1):
1614                         /* enable S/G on PCO and RV2 */
1615                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1616                             (adev->apu_flags & AMD_APU_IS_PICASSO))
1617                                 init_data.flags.gpu_vm_support = true;
1618                         break;
1619                 case IP_VERSION(2, 1, 0):
1620                 case IP_VERSION(3, 0, 1):
1621                 case IP_VERSION(3, 1, 2):
1622                 case IP_VERSION(3, 1, 3):
1623                 case IP_VERSION(3, 1, 4):
1624                 case IP_VERSION(3, 1, 5):
1625                 case IP_VERSION(3, 1, 6):
1626                         init_data.flags.gpu_vm_support = true;
1627                         break;
1628                 default:
1629                         break;
1630                 }
1631                 break;
1632         }
1633         if (init_data.flags.gpu_vm_support &&
1634             (amdgpu_sg_display == 0))
1635                 init_data.flags.gpu_vm_support = false;
1636
1637         if (init_data.flags.gpu_vm_support)
1638                 adev->mode_info.gpu_vm_support = true;
1639
1640         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1641                 init_data.flags.fbc_support = true;
1642
1643         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1644                 init_data.flags.multi_mon_pp_mclk_switch = true;
1645
1646         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1647                 init_data.flags.disable_fractional_pwm = true;
1648
1649         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1650                 init_data.flags.edp_no_power_sequencing = true;
1651
1652         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1653                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1654         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1655                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1656
1657         init_data.flags.seamless_boot_edp_requested = false;
1658
1659         if (check_seamless_boot_capability(adev)) {
1660                 init_data.flags.seamless_boot_edp_requested = true;
1661                 init_data.flags.allow_seamless_boot_optimization = true;
1662                 DRM_INFO("Seamless boot condition check passed\n");
1663         }
1664
1665         init_data.flags.enable_mipi_converter_optimization = true;
1666
1667         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1668         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1669
1670         INIT_LIST_HEAD(&adev->dm.da_list);
1671
1672         retrieve_dmi_info(&adev->dm);
1673
1674         /* Display Core create. */
1675         adev->dm.dc = dc_create(&init_data);
1676
1677         if (adev->dm.dc) {
1678                 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,
1679                          dce_version_to_string(adev->dm.dc->ctx->dce_version));
1680         } else {
1681                 DRM_INFO("Display Core v%s failed to initialize on %s\n", DC_VER,
1682                          dce_version_to_string(adev->dm.dc->ctx->dce_version));
1683                 goto error;
1684         }
1685
1686         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1687                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1688                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1689         }
1690
1691         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1692                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1693         if (dm_should_disable_stutter(adev->pdev))
1694                 adev->dm.dc->debug.disable_stutter = true;
1695
1696         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1697                 adev->dm.dc->debug.disable_stutter = true;
1698
1699         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1700                 adev->dm.dc->debug.disable_dsc = true;
1701         }
1702
1703         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1704                 adev->dm.dc->debug.disable_clock_gate = true;
1705
1706         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1707                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1708
1709         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1710
1711         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1712         adev->dm.dc->debug.ignore_cable_id = true;
1713
1714         /* TODO: There is a new drm mst change where the freedom of
1715          * vc_next_start_slot update is revoked/moved into drm, instead of in
1716          * driver. This forces us to make sure to get vc_next_start_slot updated
1717          * in drm function each time without considering if mst_state is active
1718          * or not. Otherwise, next time hotplug will give wrong start_slot
1719          * number. We are implementing a temporary solution to even notify drm
1720          * mst deallocation when link is no longer of MST type when uncommitting
1721          * the stream so we will have more time to work on a proper solution.
1722          * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1723          * should notify drm to do a complete "reset" of its states and stop
1724          * calling further drm mst functions when link is no longer of an MST
1725          * type. This could happen when we unplug an MST hubs/displays. When
1726          * uncommit stream comes later after unplug, we should just reset
1727          * hardware states only.
1728          */
1729         adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1730
1731         if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1732                 DRM_INFO("DP-HDMI FRL PCON supported\n");
1733
1734         r = dm_dmub_hw_init(adev);
1735         if (r) {
1736                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1737                 goto error;
1738         }
1739
1740         dc_hardware_init(adev->dm.dc);
1741
1742         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1743         if (!adev->dm.hpd_rx_offload_wq) {
1744                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1745                 goto error;
1746         }
1747
1748         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1749                 struct dc_phy_addr_space_config pa_config;
1750
1751                 mmhub_read_system_context(adev, &pa_config);
1752
1753                 // Call the DC init_memory func
1754                 dc_setup_system_context(adev->dm.dc, &pa_config);
1755         }
1756
1757         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1758         if (!adev->dm.freesync_module) {
1759                 DRM_ERROR(
1760                 "amdgpu: failed to initialize freesync_module.\n");
1761         } else
1762                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1763                                 adev->dm.freesync_module);
1764
1765         amdgpu_dm_init_color_mod();
1766
1767         if (adev->dm.dc->caps.max_links > 0) {
1768                 adev->dm.vblank_control_workqueue =
1769                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1770                 if (!adev->dm.vblank_control_workqueue)
1771                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1772         }
1773
1774         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1775                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1776
1777                 if (!adev->dm.hdcp_workqueue)
1778                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1779                 else
1780                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1781
1782                 dc_init_callbacks(adev->dm.dc, &init_params);
1783         }
1784         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1785                 init_completion(&adev->dm.dmub_aux_transfer_done);
1786                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1787                 if (!adev->dm.dmub_notify) {
1788                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1789                         goto error;
1790                 }
1791
1792                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1793                 if (!adev->dm.delayed_hpd_wq) {
1794                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1795                         goto error;
1796                 }
1797
1798                 amdgpu_dm_outbox_init(adev);
1799                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1800                         dmub_aux_setconfig_callback, false)) {
1801                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1802                         goto error;
1803                 }
1804                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1805                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1806                         goto error;
1807                 }
1808                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1809                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1810                         goto error;
1811                 }
1812         }
1813
1814         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1815          * It is expected that DMUB will resend any pending notifications at this point, for
1816          * example HPD from DPIA.
1817          */
1818         if (dc_is_dmub_outbox_supported(adev->dm.dc))
1819                 dc_enable_dmub_outbox(adev->dm.dc);
1820
1821         if (amdgpu_dm_initialize_drm_device(adev)) {
1822                 DRM_ERROR(
1823                 "amdgpu: failed to initialize sw for display support.\n");
1824                 goto error;
1825         }
1826
1827         /* create fake encoders for MST */
1828         dm_dp_create_fake_mst_encoders(adev);
1829
1830         /* TODO: Add_display_info? */
1831
1832         /* TODO use dynamic cursor width */
1833         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1834         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1835
1836         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1837                 DRM_ERROR(
1838                 "amdgpu: failed to initialize sw for display support.\n");
1839                 goto error;
1840         }
1841
1842 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1843         adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1844         if (!adev->dm.secure_display_ctxs)
1845                 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");
1846 #endif
1847
1848         DRM_DEBUG_DRIVER("KMS initialized.\n");
1849
1850         return 0;
1851 error:
1852         amdgpu_dm_fini(adev);
1853
1854         return -EINVAL;
1855 }
1856
1857 static int amdgpu_dm_early_fini(void *handle)
1858 {
1859         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1860
1861         amdgpu_dm_audio_fini(adev);
1862
1863         return 0;
1864 }
1865
1866 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1867 {
1868         int i;
1869
1870         if (adev->dm.vblank_control_workqueue) {
1871                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1872                 adev->dm.vblank_control_workqueue = NULL;
1873         }
1874
1875         amdgpu_dm_destroy_drm_device(&adev->dm);
1876
1877 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1878         if (adev->dm.secure_display_ctxs) {
1879                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1880                         if (adev->dm.secure_display_ctxs[i].crtc) {
1881                                 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1882                                 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1883                         }
1884                 }
1885                 kfree(adev->dm.secure_display_ctxs);
1886                 adev->dm.secure_display_ctxs = NULL;
1887         }
1888 #endif
1889         if (adev->dm.hdcp_workqueue) {
1890                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1891                 adev->dm.hdcp_workqueue = NULL;
1892         }
1893
1894         if (adev->dm.dc)
1895                 dc_deinit_callbacks(adev->dm.dc);
1896
1897         if (adev->dm.dc)
1898                 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1899
1900         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1901                 kfree(adev->dm.dmub_notify);
1902                 adev->dm.dmub_notify = NULL;
1903                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1904                 adev->dm.delayed_hpd_wq = NULL;
1905         }
1906
1907         if (adev->dm.dmub_bo)
1908                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1909                                       &adev->dm.dmub_bo_gpu_addr,
1910                                       &adev->dm.dmub_bo_cpu_addr);
1911
1912         if (adev->dm.hpd_rx_offload_wq) {
1913                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1914                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1915                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1916                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1917                         }
1918                 }
1919
1920                 kfree(adev->dm.hpd_rx_offload_wq);
1921                 adev->dm.hpd_rx_offload_wq = NULL;
1922         }
1923
1924         /* DC Destroy TODO: Replace destroy DAL */
1925         if (adev->dm.dc)
1926                 dc_destroy(&adev->dm.dc);
1927         /*
1928          * TODO: pageflip, vlank interrupt
1929          *
1930          * amdgpu_dm_irq_fini(adev);
1931          */
1932
1933         if (adev->dm.cgs_device) {
1934                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1935                 adev->dm.cgs_device = NULL;
1936         }
1937         if (adev->dm.freesync_module) {
1938                 mod_freesync_destroy(adev->dm.freesync_module);
1939                 adev->dm.freesync_module = NULL;
1940         }
1941
1942         mutex_destroy(&adev->dm.audio_lock);
1943         mutex_destroy(&adev->dm.dc_lock);
1944         mutex_destroy(&adev->dm.dpia_aux_lock);
1945
1946         return;
1947 }
1948
1949 static int load_dmcu_fw(struct amdgpu_device *adev)
1950 {
1951         const char *fw_name_dmcu = NULL;
1952         int r;
1953         const struct dmcu_firmware_header_v1_0 *hdr;
1954
1955         switch(adev->asic_type) {
1956 #if defined(CONFIG_DRM_AMD_DC_SI)
1957         case CHIP_TAHITI:
1958         case CHIP_PITCAIRN:
1959         case CHIP_VERDE:
1960         case CHIP_OLAND:
1961 #endif
1962         case CHIP_BONAIRE:
1963         case CHIP_HAWAII:
1964         case CHIP_KAVERI:
1965         case CHIP_KABINI:
1966         case CHIP_MULLINS:
1967         case CHIP_TONGA:
1968         case CHIP_FIJI:
1969         case CHIP_CARRIZO:
1970         case CHIP_STONEY:
1971         case CHIP_POLARIS11:
1972         case CHIP_POLARIS10:
1973         case CHIP_POLARIS12:
1974         case CHIP_VEGAM:
1975         case CHIP_VEGA10:
1976         case CHIP_VEGA12:
1977         case CHIP_VEGA20:
1978                 return 0;
1979         case CHIP_NAVI12:
1980                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1981                 break;
1982         case CHIP_RAVEN:
1983                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1984                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1985                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1986                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1987                 else
1988                         return 0;
1989                 break;
1990         default:
1991                 switch (adev->ip_versions[DCE_HWIP][0]) {
1992                 case IP_VERSION(2, 0, 2):
1993                 case IP_VERSION(2, 0, 3):
1994                 case IP_VERSION(2, 0, 0):
1995                 case IP_VERSION(2, 1, 0):
1996                 case IP_VERSION(3, 0, 0):
1997                 case IP_VERSION(3, 0, 2):
1998                 case IP_VERSION(3, 0, 3):
1999                 case IP_VERSION(3, 0, 1):
2000                 case IP_VERSION(3, 1, 2):
2001                 case IP_VERSION(3, 1, 3):
2002                 case IP_VERSION(3, 1, 4):
2003                 case IP_VERSION(3, 1, 5):
2004                 case IP_VERSION(3, 1, 6):
2005                 case IP_VERSION(3, 2, 0):
2006                 case IP_VERSION(3, 2, 1):
2007                         return 0;
2008                 default:
2009                         break;
2010                 }
2011                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2012                 return -EINVAL;
2013         }
2014
2015         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2016                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2017                 return 0;
2018         }
2019
2020         r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2021         if (r == -ENODEV) {
2022                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2023                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2024                 adev->dm.fw_dmcu = NULL;
2025                 return 0;
2026         }
2027         if (r) {
2028                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2029                         fw_name_dmcu);
2030                 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2031                 return r;
2032         }
2033
2034         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2035         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2036         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2037         adev->firmware.fw_size +=
2038                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2039
2040         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2041         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2042         adev->firmware.fw_size +=
2043                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2044
2045         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2046
2047         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2048
2049         return 0;
2050 }
2051
2052 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2053 {
2054         struct amdgpu_device *adev = ctx;
2055
2056         return dm_read_reg(adev->dm.dc->ctx, address);
2057 }
2058
2059 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2060                                      uint32_t value)
2061 {
2062         struct amdgpu_device *adev = ctx;
2063
2064         return dm_write_reg(adev->dm.dc->ctx, address, value);
2065 }
2066
2067 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2068 {
2069         struct dmub_srv_create_params create_params;
2070         struct dmub_srv_region_params region_params;
2071         struct dmub_srv_region_info region_info;
2072         struct dmub_srv_fb_params fb_params;
2073         struct dmub_srv_fb_info *fb_info;
2074         struct dmub_srv *dmub_srv;
2075         const struct dmcub_firmware_header_v1_0 *hdr;
2076         enum dmub_asic dmub_asic;
2077         enum dmub_status status;
2078         int r;
2079
2080         switch (adev->ip_versions[DCE_HWIP][0]) {
2081         case IP_VERSION(2, 1, 0):
2082                 dmub_asic = DMUB_ASIC_DCN21;
2083                 break;
2084         case IP_VERSION(3, 0, 0):
2085                 dmub_asic = DMUB_ASIC_DCN30;
2086                 break;
2087         case IP_VERSION(3, 0, 1):
2088                 dmub_asic = DMUB_ASIC_DCN301;
2089                 break;
2090         case IP_VERSION(3, 0, 2):
2091                 dmub_asic = DMUB_ASIC_DCN302;
2092                 break;
2093         case IP_VERSION(3, 0, 3):
2094                 dmub_asic = DMUB_ASIC_DCN303;
2095                 break;
2096         case IP_VERSION(3, 1, 2):
2097         case IP_VERSION(3, 1, 3):
2098                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2099                 break;
2100         case IP_VERSION(3, 1, 4):
2101                 dmub_asic = DMUB_ASIC_DCN314;
2102                 break;
2103         case IP_VERSION(3, 1, 5):
2104                 dmub_asic = DMUB_ASIC_DCN315;
2105                 break;
2106         case IP_VERSION(3, 1, 6):
2107                 dmub_asic = DMUB_ASIC_DCN316;
2108                 break;
2109         case IP_VERSION(3, 2, 0):
2110                 dmub_asic = DMUB_ASIC_DCN32;
2111                 break;
2112         case IP_VERSION(3, 2, 1):
2113                 dmub_asic = DMUB_ASIC_DCN321;
2114                 break;
2115         default:
2116                 /* ASIC doesn't support DMUB. */
2117                 return 0;
2118         }
2119
2120         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2121         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2122
2123         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2124                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2125                         AMDGPU_UCODE_ID_DMCUB;
2126                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2127                         adev->dm.dmub_fw;
2128                 adev->firmware.fw_size +=
2129                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2130
2131                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2132                          adev->dm.dmcub_fw_version);
2133         }
2134
2135
2136         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2137         dmub_srv = adev->dm.dmub_srv;
2138
2139         if (!dmub_srv) {
2140                 DRM_ERROR("Failed to allocate DMUB service!\n");
2141                 return -ENOMEM;
2142         }
2143
2144         memset(&create_params, 0, sizeof(create_params));
2145         create_params.user_ctx = adev;
2146         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2147         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2148         create_params.asic = dmub_asic;
2149
2150         /* Create the DMUB service. */
2151         status = dmub_srv_create(dmub_srv, &create_params);
2152         if (status != DMUB_STATUS_OK) {
2153                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2154                 return -EINVAL;
2155         }
2156
2157         /* Calculate the size of all the regions for the DMUB service. */
2158         memset(&region_params, 0, sizeof(region_params));
2159
2160         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2161                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2162         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2163         region_params.vbios_size = adev->bios_size;
2164         region_params.fw_bss_data = region_params.bss_data_size ?
2165                 adev->dm.dmub_fw->data +
2166                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2167                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2168         region_params.fw_inst_const =
2169                 adev->dm.dmub_fw->data +
2170                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2171                 PSP_HEADER_BYTES;
2172
2173         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2174                                            &region_info);
2175
2176         if (status != DMUB_STATUS_OK) {
2177                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2178                 return -EINVAL;
2179         }
2180
2181         /*
2182          * Allocate a framebuffer based on the total size of all the regions.
2183          * TODO: Move this into GART.
2184          */
2185         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2186                                     AMDGPU_GEM_DOMAIN_VRAM |
2187                                     AMDGPU_GEM_DOMAIN_GTT,
2188                                     &adev->dm.dmub_bo,
2189                                     &adev->dm.dmub_bo_gpu_addr,
2190                                     &adev->dm.dmub_bo_cpu_addr);
2191         if (r)
2192                 return r;
2193
2194         /* Rebase the regions on the framebuffer address. */
2195         memset(&fb_params, 0, sizeof(fb_params));
2196         fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2197         fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2198         fb_params.region_info = &region_info;
2199
2200         adev->dm.dmub_fb_info =
2201                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2202         fb_info = adev->dm.dmub_fb_info;
2203
2204         if (!fb_info) {
2205                 DRM_ERROR(
2206                         "Failed to allocate framebuffer info for DMUB service!\n");
2207                 return -ENOMEM;
2208         }
2209
2210         status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2211         if (status != DMUB_STATUS_OK) {
2212                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2213                 return -EINVAL;
2214         }
2215
2216         return 0;
2217 }
2218
2219 static int dm_sw_init(void *handle)
2220 {
2221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2222         int r;
2223
2224         r = dm_dmub_sw_init(adev);
2225         if (r)
2226                 return r;
2227
2228         return load_dmcu_fw(adev);
2229 }
2230
2231 static int dm_sw_fini(void *handle)
2232 {
2233         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2234
2235         kfree(adev->dm.dmub_fb_info);
2236         adev->dm.dmub_fb_info = NULL;
2237
2238         if (adev->dm.dmub_srv) {
2239                 dmub_srv_destroy(adev->dm.dmub_srv);
2240                 adev->dm.dmub_srv = NULL;
2241         }
2242
2243         amdgpu_ucode_release(&adev->dm.dmub_fw);
2244         amdgpu_ucode_release(&adev->dm.fw_dmcu);
2245
2246         return 0;
2247 }
2248
2249 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2250 {
2251         struct amdgpu_dm_connector *aconnector;
2252         struct drm_connector *connector;
2253         struct drm_connector_list_iter iter;
2254         int ret = 0;
2255
2256         drm_connector_list_iter_begin(dev, &iter);
2257         drm_for_each_connector_iter(connector, &iter) {
2258                 aconnector = to_amdgpu_dm_connector(connector);
2259                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2260                     aconnector->mst_mgr.aux) {
2261                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2262                                          aconnector,
2263                                          aconnector->base.base.id);
2264
2265                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2266                         if (ret < 0) {
2267                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2268                                 aconnector->dc_link->type =
2269                                         dc_connection_single;
2270                                 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2271                                                                      aconnector->dc_link);
2272                                 break;
2273                         }
2274                 }
2275         }
2276         drm_connector_list_iter_end(&iter);
2277
2278         return ret;
2279 }
2280
2281 static int dm_late_init(void *handle)
2282 {
2283         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2284
2285         struct dmcu_iram_parameters params;
2286         unsigned int linear_lut[16];
2287         int i;
2288         struct dmcu *dmcu = NULL;
2289
2290         dmcu = adev->dm.dc->res_pool->dmcu;
2291
2292         for (i = 0; i < 16; i++)
2293                 linear_lut[i] = 0xFFFF * i / 15;
2294
2295         params.set = 0;
2296         params.backlight_ramping_override = false;
2297         params.backlight_ramping_start = 0xCCCC;
2298         params.backlight_ramping_reduction = 0xCCCCCCCC;
2299         params.backlight_lut_array_size = 16;
2300         params.backlight_lut_array = linear_lut;
2301
2302         /* Min backlight level after ABM reduction,  Don't allow below 1%
2303          * 0xFFFF x 0.01 = 0x28F
2304          */
2305         params.min_abm_backlight = 0x28F;
2306         /* In the case where abm is implemented on dmcub,
2307          * dmcu object will be null.
2308          * ABM 2.4 and up are implemented on dmcub.
2309          */
2310         if (dmcu) {
2311                 if (!dmcu_load_iram(dmcu, params))
2312                         return -EINVAL;
2313         } else if (adev->dm.dc->ctx->dmub_srv) {
2314                 struct dc_link *edp_links[MAX_NUM_EDP];
2315                 int edp_num;
2316
2317                 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2318                 for (i = 0; i < edp_num; i++) {
2319                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2320                                 return -EINVAL;
2321                 }
2322         }
2323
2324         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2325 }
2326
2327 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2328 {
2329         struct amdgpu_dm_connector *aconnector;
2330         struct drm_connector *connector;
2331         struct drm_connector_list_iter iter;
2332         struct drm_dp_mst_topology_mgr *mgr;
2333         int ret;
2334         bool need_hotplug = false;
2335
2336         drm_connector_list_iter_begin(dev, &iter);
2337         drm_for_each_connector_iter(connector, &iter) {
2338                 aconnector = to_amdgpu_dm_connector(connector);
2339                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2340                     aconnector->mst_root)
2341                         continue;
2342
2343                 mgr = &aconnector->mst_mgr;
2344
2345                 if (suspend) {
2346                         drm_dp_mst_topology_mgr_suspend(mgr);
2347                 } else {
2348                         /* if extended timeout is supported in hardware,
2349                          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2350                          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2351                          */
2352                         try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2353                         if (!dp_is_lttpr_present(aconnector->dc_link))
2354                                 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2355
2356                         ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2357                         if (ret < 0) {
2358                                 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2359                                         aconnector->dc_link);
2360                                 need_hotplug = true;
2361                         }
2362                 }
2363         }
2364         drm_connector_list_iter_end(&iter);
2365
2366         if (need_hotplug)
2367                 drm_kms_helper_hotplug_event(dev);
2368 }
2369
2370 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2371 {
2372         int ret = 0;
2373
2374         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2375          * on window driver dc implementation.
2376          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2377          * should be passed to smu during boot up and resume from s3.
2378          * boot up: dc calculate dcn watermark clock settings within dc_create,
2379          * dcn20_resource_construct
2380          * then call pplib functions below to pass the settings to smu:
2381          * smu_set_watermarks_for_clock_ranges
2382          * smu_set_watermarks_table
2383          * navi10_set_watermarks_table
2384          * smu_write_watermarks_table
2385          *
2386          * For Renoir, clock settings of dcn watermark are also fixed values.
2387          * dc has implemented different flow for window driver:
2388          * dc_hardware_init / dc_set_power_state
2389          * dcn10_init_hw
2390          * notify_wm_ranges
2391          * set_wm_ranges
2392          * -- Linux
2393          * smu_set_watermarks_for_clock_ranges
2394          * renoir_set_watermarks_table
2395          * smu_write_watermarks_table
2396          *
2397          * For Linux,
2398          * dc_hardware_init -> amdgpu_dm_init
2399          * dc_set_power_state --> dm_resume
2400          *
2401          * therefore, this function apply to navi10/12/14 but not Renoir
2402          * *
2403          */
2404         switch (adev->ip_versions[DCE_HWIP][0]) {
2405         case IP_VERSION(2, 0, 2):
2406         case IP_VERSION(2, 0, 0):
2407                 break;
2408         default:
2409                 return 0;
2410         }
2411
2412         ret = amdgpu_dpm_write_watermarks_table(adev);
2413         if (ret) {
2414                 DRM_ERROR("Failed to update WMTABLE!\n");
2415                 return ret;
2416         }
2417
2418         return 0;
2419 }
2420
2421 /**
2422  * dm_hw_init() - Initialize DC device
2423  * @handle: The base driver device containing the amdgpu_dm device.
2424  *
2425  * Initialize the &struct amdgpu_display_manager device. This involves calling
2426  * the initializers of each DM component, then populating the struct with them.
2427  *
2428  * Although the function implies hardware initialization, both hardware and
2429  * software are initialized here. Splitting them out to their relevant init
2430  * hooks is a future TODO item.
2431  *
2432  * Some notable things that are initialized here:
2433  *
2434  * - Display Core, both software and hardware
2435  * - DC modules that we need (freesync and color management)
2436  * - DRM software states
2437  * - Interrupt sources and handlers
2438  * - Vblank support
2439  * - Debug FS entries, if enabled
2440  */
2441 static int dm_hw_init(void *handle)
2442 {
2443         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2444         /* Create DAL display manager */
2445         amdgpu_dm_init(adev);
2446         amdgpu_dm_hpd_init(adev);
2447
2448         return 0;
2449 }
2450
2451 /**
2452  * dm_hw_fini() - Teardown DC device
2453  * @handle: The base driver device containing the amdgpu_dm device.
2454  *
2455  * Teardown components within &struct amdgpu_display_manager that require
2456  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2457  * were loaded. Also flush IRQ workqueues and disable them.
2458  */
2459 static int dm_hw_fini(void *handle)
2460 {
2461         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2462
2463         amdgpu_dm_hpd_fini(adev);
2464
2465         amdgpu_dm_irq_fini(adev);
2466         amdgpu_dm_fini(adev);
2467         return 0;
2468 }
2469
2470
2471 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2472                                  struct dc_state *state, bool enable)
2473 {
2474         enum dc_irq_source irq_source;
2475         struct amdgpu_crtc *acrtc;
2476         int rc = -EBUSY;
2477         int i = 0;
2478
2479         for (i = 0; i < state->stream_count; i++) {
2480                 acrtc = get_crtc_by_otg_inst(
2481                                 adev, state->stream_status[i].primary_otg_inst);
2482
2483                 if (acrtc && state->stream_status[i].plane_count != 0) {
2484                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2485                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2486                         if (rc)
2487                                 DRM_WARN("Failed to %s pflip interrupts\n",
2488                                          enable ? "enable" : "disable");
2489
2490                         if (enable) {
2491                                 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
2492                                         rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
2493                         } else
2494                                 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
2495
2496                         if (rc)
2497                                 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
2498
2499                         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2500                         /* During gpu-reset we disable and then enable vblank irq, so
2501                          * don't use amdgpu_irq_get/put() to avoid refcount change.
2502                          */
2503                         if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
2504                                 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
2505                 }
2506         }
2507
2508 }
2509
2510 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2511 {
2512         struct dc_state *context = NULL;
2513         enum dc_status res = DC_ERROR_UNEXPECTED;
2514         int i;
2515         struct dc_stream_state *del_streams[MAX_PIPES];
2516         int del_streams_count = 0;
2517
2518         memset(del_streams, 0, sizeof(del_streams));
2519
2520         context = dc_create_state(dc);
2521         if (context == NULL)
2522                 goto context_alloc_fail;
2523
2524         dc_resource_state_copy_construct_current(dc, context);
2525
2526         /* First remove from context all streams */
2527         for (i = 0; i < context->stream_count; i++) {
2528                 struct dc_stream_state *stream = context->streams[i];
2529
2530                 del_streams[del_streams_count++] = stream;
2531         }
2532
2533         /* Remove all planes for removed streams and then remove the streams */
2534         for (i = 0; i < del_streams_count; i++) {
2535                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2536                         res = DC_FAIL_DETACH_SURFACES;
2537                         goto fail;
2538                 }
2539
2540                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2541                 if (res != DC_OK)
2542                         goto fail;
2543         }
2544
2545         res = dc_commit_streams(dc, context->streams, context->stream_count);
2546
2547 fail:
2548         dc_release_state(context);
2549
2550 context_alloc_fail:
2551         return res;
2552 }
2553
2554 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2555 {
2556         int i;
2557
2558         if (dm->hpd_rx_offload_wq) {
2559                 for (i = 0; i < dm->dc->caps.max_links; i++)
2560                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2561         }
2562 }
2563
2564 static int dm_suspend(void *handle)
2565 {
2566         struct amdgpu_device *adev = handle;
2567         struct amdgpu_display_manager *dm = &adev->dm;
2568         int ret = 0;
2569
2570         if (amdgpu_in_reset(adev)) {
2571                 mutex_lock(&dm->dc_lock);
2572
2573                 dc_allow_idle_optimizations(adev->dm.dc, false);
2574
2575                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2576
2577                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2578
2579                 amdgpu_dm_commit_zero_streams(dm->dc);
2580
2581                 amdgpu_dm_irq_suspend(adev);
2582
2583                 hpd_rx_irq_work_suspend(dm);
2584
2585                 return ret;
2586         }
2587
2588         WARN_ON(adev->dm.cached_state);
2589         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2590
2591         s3_handle_mst(adev_to_drm(adev), true);
2592
2593         amdgpu_dm_irq_suspend(adev);
2594
2595         hpd_rx_irq_work_suspend(dm);
2596
2597         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2598
2599         return 0;
2600 }
2601
2602 struct amdgpu_dm_connector *
2603 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2604                                              struct drm_crtc *crtc)
2605 {
2606         u32 i;
2607         struct drm_connector_state *new_con_state;
2608         struct drm_connector *connector;
2609         struct drm_crtc *crtc_from_state;
2610
2611         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2612                 crtc_from_state = new_con_state->crtc;
2613
2614                 if (crtc_from_state == crtc)
2615                         return to_amdgpu_dm_connector(connector);
2616         }
2617
2618         return NULL;
2619 }
2620
2621 static void emulated_link_detect(struct dc_link *link)
2622 {
2623         struct dc_sink_init_data sink_init_data = { 0 };
2624         struct display_sink_capability sink_caps = { 0 };
2625         enum dc_edid_status edid_status;
2626         struct dc_context *dc_ctx = link->ctx;
2627         struct dc_sink *sink = NULL;
2628         struct dc_sink *prev_sink = NULL;
2629
2630         link->type = dc_connection_none;
2631         prev_sink = link->local_sink;
2632
2633         if (prev_sink)
2634                 dc_sink_release(prev_sink);
2635
2636         switch (link->connector_signal) {
2637         case SIGNAL_TYPE_HDMI_TYPE_A: {
2638                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2639                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2640                 break;
2641         }
2642
2643         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2644                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2645                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2646                 break;
2647         }
2648
2649         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2650                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2651                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2652                 break;
2653         }
2654
2655         case SIGNAL_TYPE_LVDS: {
2656                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2657                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2658                 break;
2659         }
2660
2661         case SIGNAL_TYPE_EDP: {
2662                 sink_caps.transaction_type =
2663                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2664                 sink_caps.signal = SIGNAL_TYPE_EDP;
2665                 break;
2666         }
2667
2668         case SIGNAL_TYPE_DISPLAY_PORT: {
2669                 sink_caps.transaction_type =
2670                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2671                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2672                 break;
2673         }
2674
2675         default:
2676                 DC_ERROR("Invalid connector type! signal:%d\n",
2677                         link->connector_signal);
2678                 return;
2679         }
2680
2681         sink_init_data.link = link;
2682         sink_init_data.sink_signal = sink_caps.signal;
2683
2684         sink = dc_sink_create(&sink_init_data);
2685         if (!sink) {
2686                 DC_ERROR("Failed to create sink!\n");
2687                 return;
2688         }
2689
2690         /* dc_sink_create returns a new reference */
2691         link->local_sink = sink;
2692
2693         edid_status = dm_helpers_read_local_edid(
2694                         link->ctx,
2695                         link,
2696                         sink);
2697
2698         if (edid_status != EDID_OK)
2699                 DC_ERROR("Failed to read EDID");
2700
2701 }
2702
2703 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2704                                      struct amdgpu_display_manager *dm)
2705 {
2706         struct {
2707                 struct dc_surface_update surface_updates[MAX_SURFACES];
2708                 struct dc_plane_info plane_infos[MAX_SURFACES];
2709                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2710                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2711                 struct dc_stream_update stream_update;
2712         } * bundle;
2713         int k, m;
2714
2715         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2716
2717         if (!bundle) {
2718                 dm_error("Failed to allocate update bundle\n");
2719                 goto cleanup;
2720         }
2721
2722         for (k = 0; k < dc_state->stream_count; k++) {
2723                 bundle->stream_update.stream = dc_state->streams[k];
2724
2725                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2726                         bundle->surface_updates[m].surface =
2727                                 dc_state->stream_status->plane_states[m];
2728                         bundle->surface_updates[m].surface->force_full_update =
2729                                 true;
2730                 }
2731
2732                 update_planes_and_stream_adapter(dm->dc,
2733                                          UPDATE_TYPE_FULL,
2734                                          dc_state->stream_status->plane_count,
2735                                          dc_state->streams[k],
2736                                          &bundle->stream_update,
2737                                          bundle->surface_updates);
2738         }
2739
2740 cleanup:
2741         kfree(bundle);
2742
2743         return;
2744 }
2745
2746 static int dm_resume(void *handle)
2747 {
2748         struct amdgpu_device *adev = handle;
2749         struct drm_device *ddev = adev_to_drm(adev);
2750         struct amdgpu_display_manager *dm = &adev->dm;
2751         struct amdgpu_dm_connector *aconnector;
2752         struct drm_connector *connector;
2753         struct drm_connector_list_iter iter;
2754         struct drm_crtc *crtc;
2755         struct drm_crtc_state *new_crtc_state;
2756         struct dm_crtc_state *dm_new_crtc_state;
2757         struct drm_plane *plane;
2758         struct drm_plane_state *new_plane_state;
2759         struct dm_plane_state *dm_new_plane_state;
2760         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2761         enum dc_connection_type new_connection_type = dc_connection_none;
2762         struct dc_state *dc_state;
2763         int i, r, j;
2764
2765         if (amdgpu_in_reset(adev)) {
2766                 dc_state = dm->cached_dc_state;
2767
2768                 /*
2769                  * The dc->current_state is backed up into dm->cached_dc_state
2770                  * before we commit 0 streams.
2771                  *
2772                  * DC will clear link encoder assignments on the real state
2773                  * but the changes won't propagate over to the copy we made
2774                  * before the 0 streams commit.
2775                  *
2776                  * DC expects that link encoder assignments are *not* valid
2777                  * when committing a state, so as a workaround we can copy
2778                  * off of the current state.
2779                  *
2780                  * We lose the previous assignments, but we had already
2781                  * commit 0 streams anyway.
2782                  */
2783                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2784
2785                 r = dm_dmub_hw_init(adev);
2786                 if (r)
2787                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2788
2789                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2790                 dc_resume(dm->dc);
2791
2792                 amdgpu_dm_irq_resume_early(adev);
2793
2794                 for (i = 0; i < dc_state->stream_count; i++) {
2795                         dc_state->streams[i]->mode_changed = true;
2796                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2797                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2798                                         = 0xffffffff;
2799                         }
2800                 }
2801
2802                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2803                         amdgpu_dm_outbox_init(adev);
2804                         dc_enable_dmub_outbox(adev->dm.dc);
2805                 }
2806
2807                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2808
2809                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2810
2811                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2812
2813                 dc_release_state(dm->cached_dc_state);
2814                 dm->cached_dc_state = NULL;
2815
2816                 amdgpu_dm_irq_resume_late(adev);
2817
2818                 mutex_unlock(&dm->dc_lock);
2819
2820                 return 0;
2821         }
2822         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2823         dc_release_state(dm_state->context);
2824         dm_state->context = dc_create_state(dm->dc);
2825         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2826         dc_resource_state_construct(dm->dc, dm_state->context);
2827
2828         /* Before powering on DC we need to re-initialize DMUB. */
2829         dm_dmub_hw_resume(adev);
2830
2831         /* Re-enable outbox interrupts for DPIA. */
2832         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2833                 amdgpu_dm_outbox_init(adev);
2834                 dc_enable_dmub_outbox(adev->dm.dc);
2835         }
2836
2837         /* power on hardware */
2838         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2839
2840         /* program HPD filter */
2841         dc_resume(dm->dc);
2842
2843         /*
2844          * early enable HPD Rx IRQ, should be done before set mode as short
2845          * pulse interrupts are used for MST
2846          */
2847         amdgpu_dm_irq_resume_early(adev);
2848
2849         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2850         s3_handle_mst(ddev, false);
2851
2852         /* Do detection*/
2853         drm_connector_list_iter_begin(ddev, &iter);
2854         drm_for_each_connector_iter(connector, &iter) {
2855                 aconnector = to_amdgpu_dm_connector(connector);
2856
2857                 if (!aconnector->dc_link)
2858                         continue;
2859
2860                 /*
2861                  * this is the case when traversing through already created
2862                  * MST connectors, should be skipped
2863                  */
2864                 if (aconnector && aconnector->mst_root)
2865                         continue;
2866
2867                 mutex_lock(&aconnector->hpd_lock);
2868                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2869                         DRM_ERROR("KMS: Failed to detect connector\n");
2870
2871                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2872                         emulated_link_detect(aconnector->dc_link);
2873                 } else {
2874                         mutex_lock(&dm->dc_lock);
2875                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2876                         mutex_unlock(&dm->dc_lock);
2877                 }
2878
2879                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2880                         aconnector->fake_enable = false;
2881
2882                 if (aconnector->dc_sink)
2883                         dc_sink_release(aconnector->dc_sink);
2884                 aconnector->dc_sink = NULL;
2885                 amdgpu_dm_update_connector_after_detect(aconnector);
2886                 mutex_unlock(&aconnector->hpd_lock);
2887         }
2888         drm_connector_list_iter_end(&iter);
2889
2890         /* Force mode set in atomic commit */
2891         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2892                 new_crtc_state->active_changed = true;
2893
2894         /*
2895          * atomic_check is expected to create the dc states. We need to release
2896          * them here, since they were duplicated as part of the suspend
2897          * procedure.
2898          */
2899         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2900                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2901                 if (dm_new_crtc_state->stream) {
2902                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2903                         dc_stream_release(dm_new_crtc_state->stream);
2904                         dm_new_crtc_state->stream = NULL;
2905                 }
2906         }
2907
2908         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2909                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2910                 if (dm_new_plane_state->dc_state) {
2911                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2912                         dc_plane_state_release(dm_new_plane_state->dc_state);
2913                         dm_new_plane_state->dc_state = NULL;
2914                 }
2915         }
2916
2917         drm_atomic_helper_resume(ddev, dm->cached_state);
2918
2919         dm->cached_state = NULL;
2920
2921         amdgpu_dm_irq_resume_late(adev);
2922
2923         amdgpu_dm_smu_write_watermarks_table(adev);
2924
2925         return 0;
2926 }
2927
2928 /**
2929  * DOC: DM Lifecycle
2930  *
2931  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2932  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2933  * the base driver's device list to be initialized and torn down accordingly.
2934  *
2935  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2936  */
2937
2938 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2939         .name = "dm",
2940         .early_init = dm_early_init,
2941         .late_init = dm_late_init,
2942         .sw_init = dm_sw_init,
2943         .sw_fini = dm_sw_fini,
2944         .early_fini = amdgpu_dm_early_fini,
2945         .hw_init = dm_hw_init,
2946         .hw_fini = dm_hw_fini,
2947         .suspend = dm_suspend,
2948         .resume = dm_resume,
2949         .is_idle = dm_is_idle,
2950         .wait_for_idle = dm_wait_for_idle,
2951         .check_soft_reset = dm_check_soft_reset,
2952         .soft_reset = dm_soft_reset,
2953         .set_clockgating_state = dm_set_clockgating_state,
2954         .set_powergating_state = dm_set_powergating_state,
2955 };
2956
2957 const struct amdgpu_ip_block_version dm_ip_block =
2958 {
2959         .type = AMD_IP_BLOCK_TYPE_DCE,
2960         .major = 1,
2961         .minor = 0,
2962         .rev = 0,
2963         .funcs = &amdgpu_dm_funcs,
2964 };
2965
2966
2967 /**
2968  * DOC: atomic
2969  *
2970  * *WIP*
2971  */
2972
2973 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2974         .fb_create = amdgpu_display_user_framebuffer_create,
2975         .get_format_info = amdgpu_dm_plane_get_format_info,
2976         .atomic_check = amdgpu_dm_atomic_check,
2977         .atomic_commit = drm_atomic_helper_commit,
2978 };
2979
2980 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2981         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2982         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2983 };
2984
2985 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2986 {
2987         struct amdgpu_dm_backlight_caps *caps;
2988         struct drm_connector *conn_base;
2989         struct amdgpu_device *adev;
2990         struct drm_luminance_range_info *luminance_range;
2991
2992         if (aconnector->bl_idx == -1 ||
2993             aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
2994                 return;
2995
2996         conn_base = &aconnector->base;
2997         adev = drm_to_adev(conn_base->dev);
2998
2999         caps = &adev->dm.backlight_caps[aconnector->bl_idx];
3000         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3001         caps->aux_support = false;
3002
3003         if (caps->ext_caps->bits.oled == 1 /*||
3004             caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3005             caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
3006                 caps->aux_support = true;
3007
3008         if (amdgpu_backlight == 0)
3009                 caps->aux_support = false;
3010         else if (amdgpu_backlight == 1)
3011                 caps->aux_support = true;
3012
3013         luminance_range = &conn_base->display_info.luminance_range;
3014
3015         if (luminance_range->max_luminance) {
3016                 caps->aux_min_input_signal = luminance_range->min_luminance;
3017                 caps->aux_max_input_signal = luminance_range->max_luminance;
3018         } else {
3019                 caps->aux_min_input_signal = 0;
3020                 caps->aux_max_input_signal = 512;
3021         }
3022 }
3023
3024 void amdgpu_dm_update_connector_after_detect(
3025                 struct amdgpu_dm_connector *aconnector)
3026 {
3027         struct drm_connector *connector = &aconnector->base;
3028         struct drm_device *dev = connector->dev;
3029         struct dc_sink *sink;
3030
3031         /* MST handled by drm_mst framework */
3032         if (aconnector->mst_mgr.mst_state == true)
3033                 return;
3034
3035         sink = aconnector->dc_link->local_sink;
3036         if (sink)
3037                 dc_sink_retain(sink);
3038
3039         /*
3040          * Edid mgmt connector gets first update only in mode_valid hook and then
3041          * the connector sink is set to either fake or physical sink depends on link status.
3042          * Skip if already done during boot.
3043          */
3044         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3045                         && aconnector->dc_em_sink) {
3046
3047                 /*
3048                  * For S3 resume with headless use eml_sink to fake stream
3049                  * because on resume connector->sink is set to NULL
3050                  */
3051                 mutex_lock(&dev->mode_config.mutex);
3052
3053                 if (sink) {
3054                         if (aconnector->dc_sink) {
3055                                 amdgpu_dm_update_freesync_caps(connector, NULL);
3056                                 /*
3057                                  * retain and release below are used to
3058                                  * bump up refcount for sink because the link doesn't point
3059                                  * to it anymore after disconnect, so on next crtc to connector
3060                                  * reshuffle by UMD we will get into unwanted dc_sink release
3061                                  */
3062                                 dc_sink_release(aconnector->dc_sink);
3063                         }
3064                         aconnector->dc_sink = sink;
3065                         dc_sink_retain(aconnector->dc_sink);
3066                         amdgpu_dm_update_freesync_caps(connector,
3067                                         aconnector->edid);
3068                 } else {
3069                         amdgpu_dm_update_freesync_caps(connector, NULL);
3070                         if (!aconnector->dc_sink) {
3071                                 aconnector->dc_sink = aconnector->dc_em_sink;
3072                                 dc_sink_retain(aconnector->dc_sink);
3073                         }
3074                 }
3075
3076                 mutex_unlock(&dev->mode_config.mutex);
3077
3078                 if (sink)
3079                         dc_sink_release(sink);
3080                 return;
3081         }
3082
3083         /*
3084          * TODO: temporary guard to look for proper fix
3085          * if this sink is MST sink, we should not do anything
3086          */
3087         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3088                 dc_sink_release(sink);
3089                 return;
3090         }
3091
3092         if (aconnector->dc_sink == sink) {
3093                 /*
3094                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
3095                  * Do nothing!!
3096                  */
3097                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3098                                 aconnector->connector_id);
3099                 if (sink)
3100                         dc_sink_release(sink);
3101                 return;
3102         }
3103
3104         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3105                 aconnector->connector_id, aconnector->dc_sink, sink);
3106
3107         mutex_lock(&dev->mode_config.mutex);
3108
3109         /*
3110          * 1. Update status of the drm connector
3111          * 2. Send an event and let userspace tell us what to do
3112          */
3113         if (sink) {
3114                 /*
3115                  * TODO: check if we still need the S3 mode update workaround.
3116                  * If yes, put it here.
3117                  */
3118                 if (aconnector->dc_sink) {
3119                         amdgpu_dm_update_freesync_caps(connector, NULL);
3120                         dc_sink_release(aconnector->dc_sink);
3121                 }
3122
3123                 aconnector->dc_sink = sink;
3124                 dc_sink_retain(aconnector->dc_sink);
3125                 if (sink->dc_edid.length == 0) {
3126                         aconnector->edid = NULL;
3127                         if (aconnector->dc_link->aux_mode) {
3128                                 drm_dp_cec_unset_edid(
3129                                         &aconnector->dm_dp_aux.aux);
3130                         }
3131                 } else {
3132                         aconnector->edid =
3133                                 (struct edid *)sink->dc_edid.raw_edid;
3134
3135                         if (aconnector->dc_link->aux_mode)
3136                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3137                                                     aconnector->edid);
3138                 }
3139
3140                 if (!aconnector->timing_requested) {
3141                         aconnector->timing_requested =
3142                                 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3143                         if (!aconnector->timing_requested)
3144                                 dm_error("failed to create aconnector->requested_timing\n");
3145                 }
3146
3147                 drm_connector_update_edid_property(connector, aconnector->edid);
3148                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3149                 update_connector_ext_caps(aconnector);
3150         } else {
3151                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3152                 amdgpu_dm_update_freesync_caps(connector, NULL);
3153                 drm_connector_update_edid_property(connector, NULL);
3154                 aconnector->num_modes = 0;
3155                 dc_sink_release(aconnector->dc_sink);
3156                 aconnector->dc_sink = NULL;
3157                 aconnector->edid = NULL;
3158                 kfree(aconnector->timing_requested);
3159                 aconnector->timing_requested = NULL;
3160                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3161                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3162                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3163         }
3164
3165         mutex_unlock(&dev->mode_config.mutex);
3166
3167         update_subconnector_property(aconnector);
3168
3169         if (sink)
3170                 dc_sink_release(sink);
3171 }
3172
3173 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3174 {
3175         struct drm_connector *connector = &aconnector->base;
3176         struct drm_device *dev = connector->dev;
3177         enum dc_connection_type new_connection_type = dc_connection_none;
3178         struct amdgpu_device *adev = drm_to_adev(dev);
3179         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3180         bool ret = false;
3181
3182         if (adev->dm.disable_hpd_irq)
3183                 return;
3184
3185         /*
3186          * In case of failure or MST no need to update connector status or notify the OS
3187          * since (for MST case) MST does this in its own context.
3188          */
3189         mutex_lock(&aconnector->hpd_lock);
3190
3191         if (adev->dm.hdcp_workqueue) {
3192                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3193                 dm_con_state->update_hdcp = true;
3194         }
3195         if (aconnector->fake_enable)
3196                 aconnector->fake_enable = false;
3197
3198         aconnector->timing_changed = false;
3199
3200         if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3201                 DRM_ERROR("KMS: Failed to detect connector\n");
3202
3203         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3204                 emulated_link_detect(aconnector->dc_link);
3205
3206                 drm_modeset_lock_all(dev);
3207                 dm_restore_drm_connector_state(dev, connector);
3208                 drm_modeset_unlock_all(dev);
3209
3210                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3211                         drm_kms_helper_connector_hotplug_event(connector);
3212         } else {
3213                 mutex_lock(&adev->dm.dc_lock);
3214                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3215                 mutex_unlock(&adev->dm.dc_lock);
3216                 if (ret) {
3217                         amdgpu_dm_update_connector_after_detect(aconnector);
3218
3219                         drm_modeset_lock_all(dev);
3220                         dm_restore_drm_connector_state(dev, connector);
3221                         drm_modeset_unlock_all(dev);
3222
3223                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3224                                 drm_kms_helper_connector_hotplug_event(connector);
3225                 }
3226         }
3227         mutex_unlock(&aconnector->hpd_lock);
3228
3229 }
3230
3231 static void handle_hpd_irq(void *param)
3232 {
3233         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3234
3235         handle_hpd_irq_helper(aconnector);
3236
3237 }
3238
3239 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
3240 {
3241         u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3242         u8 dret;
3243         bool new_irq_handled = false;
3244         int dpcd_addr;
3245         int dpcd_bytes_to_read;
3246
3247         const int max_process_count = 30;
3248         int process_count = 0;
3249
3250         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3251
3252         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3253                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3254                 /* DPCD 0x200 - 0x201 for downstream IRQ */
3255                 dpcd_addr = DP_SINK_COUNT;
3256         } else {
3257                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3258                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3259                 dpcd_addr = DP_SINK_COUNT_ESI;
3260         }
3261
3262         dret = drm_dp_dpcd_read(
3263                 &aconnector->dm_dp_aux.aux,
3264                 dpcd_addr,
3265                 esi,
3266                 dpcd_bytes_to_read);
3267
3268         while (dret == dpcd_bytes_to_read &&
3269                 process_count < max_process_count) {
3270                 u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {};
3271                 u8 retry;
3272                 dret = 0;
3273
3274                 process_count++;
3275
3276                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3277                 /* handle HPD short pulse irq */
3278                 if (aconnector->mst_mgr.mst_state)
3279                         drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr,
3280                                                         esi,
3281                                                         ack,
3282                                                         &new_irq_handled);
3283
3284                 if (new_irq_handled) {
3285                         /* ACK at DPCD to notify down stream */
3286                         for (retry = 0; retry < 3; retry++) {
3287                                 ssize_t wret;
3288
3289                                 wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux,
3290                                                           dpcd_addr + 1,
3291                                                           ack[1]);
3292                                 if (wret == 1)
3293                                         break;
3294                         }
3295
3296                         if (retry == 3) {
3297                                 DRM_ERROR("Failed to ack MST event.\n");
3298                                 return;
3299                         }
3300
3301                         drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr);
3302                         /* check if there is new irq to be handled */
3303                         dret = drm_dp_dpcd_read(
3304                                 &aconnector->dm_dp_aux.aux,
3305                                 dpcd_addr,
3306                                 esi,
3307                                 dpcd_bytes_to_read);
3308
3309                         new_irq_handled = false;
3310                 } else {
3311                         break;
3312                 }
3313         }
3314
3315         if (process_count == max_process_count)
3316                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
3317 }
3318
3319 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3320                                                         union hpd_irq_data hpd_irq_data)
3321 {
3322         struct hpd_rx_irq_offload_work *offload_work =
3323                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3324
3325         if (!offload_work) {
3326                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3327                 return;
3328         }
3329
3330         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3331         offload_work->data = hpd_irq_data;
3332         offload_work->offload_wq = offload_wq;
3333
3334         queue_work(offload_wq->wq, &offload_work->work);
3335         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3336 }
3337
3338 static void handle_hpd_rx_irq(void *param)
3339 {
3340         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3341         struct drm_connector *connector = &aconnector->base;
3342         struct drm_device *dev = connector->dev;
3343         struct dc_link *dc_link = aconnector->dc_link;
3344         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3345         bool result = false;
3346         enum dc_connection_type new_connection_type = dc_connection_none;
3347         struct amdgpu_device *adev = drm_to_adev(dev);
3348         union hpd_irq_data hpd_irq_data;
3349         bool link_loss = false;
3350         bool has_left_work = false;
3351         int idx = dc_link->link_index;
3352         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3353
3354         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3355
3356         if (adev->dm.disable_hpd_irq)
3357                 return;
3358
3359         /*
3360          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3361          * conflict, after implement i2c helper, this mutex should be
3362          * retired.
3363          */
3364         mutex_lock(&aconnector->hpd_lock);
3365
3366         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3367                                                 &link_loss, true, &has_left_work);
3368
3369         if (!has_left_work)
3370                 goto out;
3371
3372         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3373                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3374                 goto out;
3375         }
3376
3377         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3378                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3379                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3380                         dm_handle_mst_sideband_msg(aconnector);
3381                         goto out;
3382                 }
3383
3384                 if (link_loss) {
3385                         bool skip = false;
3386
3387                         spin_lock(&offload_wq->offload_lock);
3388                         skip = offload_wq->is_handling_link_loss;
3389
3390                         if (!skip)
3391                                 offload_wq->is_handling_link_loss = true;
3392
3393                         spin_unlock(&offload_wq->offload_lock);
3394
3395                         if (!skip)
3396                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3397
3398                         goto out;
3399                 }
3400         }
3401
3402 out:
3403         if (result && !is_mst_root_connector) {
3404                 /* Downstream Port status changed. */
3405                 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3406                         DRM_ERROR("KMS: Failed to detect connector\n");
3407
3408                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3409                         emulated_link_detect(dc_link);
3410
3411                         if (aconnector->fake_enable)
3412                                 aconnector->fake_enable = false;
3413
3414                         amdgpu_dm_update_connector_after_detect(aconnector);
3415
3416
3417                         drm_modeset_lock_all(dev);
3418                         dm_restore_drm_connector_state(dev, connector);
3419                         drm_modeset_unlock_all(dev);
3420
3421                         drm_kms_helper_connector_hotplug_event(connector);
3422                 } else {
3423                         bool ret = false;
3424
3425                         mutex_lock(&adev->dm.dc_lock);
3426                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3427                         mutex_unlock(&adev->dm.dc_lock);
3428
3429                         if (ret) {
3430                                 if (aconnector->fake_enable)
3431                                         aconnector->fake_enable = false;
3432
3433                                 amdgpu_dm_update_connector_after_detect(aconnector);
3434
3435                                 drm_modeset_lock_all(dev);
3436                                 dm_restore_drm_connector_state(dev, connector);
3437                                 drm_modeset_unlock_all(dev);
3438
3439                                 drm_kms_helper_connector_hotplug_event(connector);
3440                         }
3441                 }
3442         }
3443         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3444                 if (adev->dm.hdcp_workqueue)
3445                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3446         }
3447
3448         if (dc_link->type != dc_connection_mst_branch)
3449                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3450
3451         mutex_unlock(&aconnector->hpd_lock);
3452 }
3453
3454 static void register_hpd_handlers(struct amdgpu_device *adev)
3455 {
3456         struct drm_device *dev = adev_to_drm(adev);
3457         struct drm_connector *connector;
3458         struct amdgpu_dm_connector *aconnector;
3459         const struct dc_link *dc_link;
3460         struct dc_interrupt_params int_params = {0};
3461
3462         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3463         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3464
3465         list_for_each_entry(connector,
3466                         &dev->mode_config.connector_list, head) {
3467
3468                 aconnector = to_amdgpu_dm_connector(connector);
3469                 dc_link = aconnector->dc_link;
3470
3471                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3472                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3473                         int_params.irq_source = dc_link->irq_source_hpd;
3474
3475                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3476                                         handle_hpd_irq,
3477                                         (void *) aconnector);
3478                 }
3479
3480                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3481
3482                         /* Also register for DP short pulse (hpd_rx). */
3483                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3484                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3485
3486                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3487                                         handle_hpd_rx_irq,
3488                                         (void *) aconnector);
3489
3490                         if (adev->dm.hpd_rx_offload_wq)
3491                                 adev->dm.hpd_rx_offload_wq[dc_link->link_index].aconnector =
3492                                         aconnector;
3493                 }
3494         }
3495 }
3496
3497 #if defined(CONFIG_DRM_AMD_DC_SI)
3498 /* Register IRQ sources and initialize IRQ callbacks */
3499 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3500 {
3501         struct dc *dc = adev->dm.dc;
3502         struct common_irq_params *c_irq_params;
3503         struct dc_interrupt_params int_params = {0};
3504         int r;
3505         int i;
3506         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3507
3508         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3509         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3510
3511         /*
3512          * Actions of amdgpu_irq_add_id():
3513          * 1. Register a set() function with base driver.
3514          *    Base driver will call set() function to enable/disable an
3515          *    interrupt in DC hardware.
3516          * 2. Register amdgpu_dm_irq_handler().
3517          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3518          *    coming from DC hardware.
3519          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3520          *    for acknowledging and handling. */
3521
3522         /* Use VBLANK interrupt */
3523         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3524                 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3525                 if (r) {
3526                         DRM_ERROR("Failed to add crtc irq id!\n");
3527                         return r;
3528                 }
3529
3530                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3531                 int_params.irq_source =
3532                         dc_interrupt_to_irq_source(dc, i+1 , 0);
3533
3534                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3535
3536                 c_irq_params->adev = adev;
3537                 c_irq_params->irq_src = int_params.irq_source;
3538
3539                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3540                                 dm_crtc_high_irq, c_irq_params);
3541         }
3542
3543         /* Use GRPH_PFLIP interrupt */
3544         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3545                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3546                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3547                 if (r) {
3548                         DRM_ERROR("Failed to add page flip irq id!\n");
3549                         return r;
3550                 }
3551
3552                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3553                 int_params.irq_source =
3554                         dc_interrupt_to_irq_source(dc, i, 0);
3555
3556                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3557
3558                 c_irq_params->adev = adev;
3559                 c_irq_params->irq_src = int_params.irq_source;
3560
3561                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3562                                 dm_pflip_high_irq, c_irq_params);
3563
3564         }
3565
3566         /* HPD */
3567         r = amdgpu_irq_add_id(adev, client_id,
3568                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3569         if (r) {
3570                 DRM_ERROR("Failed to add hpd irq id!\n");
3571                 return r;
3572         }
3573
3574         register_hpd_handlers(adev);
3575
3576         return 0;
3577 }
3578 #endif
3579
3580 /* Register IRQ sources and initialize IRQ callbacks */
3581 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3582 {
3583         struct dc *dc = adev->dm.dc;
3584         struct common_irq_params *c_irq_params;
3585         struct dc_interrupt_params int_params = {0};
3586         int r;
3587         int i;
3588         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3589
3590         if (adev->family >= AMDGPU_FAMILY_AI)
3591                 client_id = SOC15_IH_CLIENTID_DCE;
3592
3593         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3594         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3595
3596         /*
3597          * Actions of amdgpu_irq_add_id():
3598          * 1. Register a set() function with base driver.
3599          *    Base driver will call set() function to enable/disable an
3600          *    interrupt in DC hardware.
3601          * 2. Register amdgpu_dm_irq_handler().
3602          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3603          *    coming from DC hardware.
3604          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3605          *    for acknowledging and handling. */
3606
3607         /* Use VBLANK interrupt */
3608         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3609                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3610                 if (r) {
3611                         DRM_ERROR("Failed to add crtc irq id!\n");
3612                         return r;
3613                 }
3614
3615                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3616                 int_params.irq_source =
3617                         dc_interrupt_to_irq_source(dc, i, 0);
3618
3619                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3620
3621                 c_irq_params->adev = adev;
3622                 c_irq_params->irq_src = int_params.irq_source;
3623
3624                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3625                                 dm_crtc_high_irq, c_irq_params);
3626         }
3627
3628         /* Use VUPDATE interrupt */
3629         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3630                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3631                 if (r) {
3632                         DRM_ERROR("Failed to add vupdate irq id!\n");
3633                         return r;
3634                 }
3635
3636                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3637                 int_params.irq_source =
3638                         dc_interrupt_to_irq_source(dc, i, 0);
3639
3640                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3641
3642                 c_irq_params->adev = adev;
3643                 c_irq_params->irq_src = int_params.irq_source;
3644
3645                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3646                                 dm_vupdate_high_irq, c_irq_params);
3647         }
3648
3649         /* Use GRPH_PFLIP interrupt */
3650         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3651                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3652                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3653                 if (r) {
3654                         DRM_ERROR("Failed to add page flip irq id!\n");
3655                         return r;
3656                 }
3657
3658                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3659                 int_params.irq_source =
3660                         dc_interrupt_to_irq_source(dc, i, 0);
3661
3662                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3663
3664                 c_irq_params->adev = adev;
3665                 c_irq_params->irq_src = int_params.irq_source;
3666
3667                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3668                                 dm_pflip_high_irq, c_irq_params);
3669
3670         }
3671
3672         /* HPD */
3673         r = amdgpu_irq_add_id(adev, client_id,
3674                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3675         if (r) {
3676                 DRM_ERROR("Failed to add hpd irq id!\n");
3677                 return r;
3678         }
3679
3680         register_hpd_handlers(adev);
3681
3682         return 0;
3683 }
3684
3685 /* Register IRQ sources and initialize IRQ callbacks */
3686 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3687 {
3688         struct dc *dc = adev->dm.dc;
3689         struct common_irq_params *c_irq_params;
3690         struct dc_interrupt_params int_params = {0};
3691         int r;
3692         int i;
3693 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3694         static const unsigned int vrtl_int_srcid[] = {
3695                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3696                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3697                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3698                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3699                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3700                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3701         };
3702 #endif
3703
3704         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3705         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3706
3707         /*
3708          * Actions of amdgpu_irq_add_id():
3709          * 1. Register a set() function with base driver.
3710          *    Base driver will call set() function to enable/disable an
3711          *    interrupt in DC hardware.
3712          * 2. Register amdgpu_dm_irq_handler().
3713          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3714          *    coming from DC hardware.
3715          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3716          *    for acknowledging and handling.
3717          */
3718
3719         /* Use VSTARTUP interrupt */
3720         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3721                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3722                         i++) {
3723                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3724
3725                 if (r) {
3726                         DRM_ERROR("Failed to add crtc irq id!\n");
3727                         return r;
3728                 }
3729
3730                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3731                 int_params.irq_source =
3732                         dc_interrupt_to_irq_source(dc, i, 0);
3733
3734                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3735
3736                 c_irq_params->adev = adev;
3737                 c_irq_params->irq_src = int_params.irq_source;
3738
3739                 amdgpu_dm_irq_register_interrupt(
3740                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3741         }
3742
3743         /* Use otg vertical line interrupt */
3744 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3745         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3746                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3747                                 vrtl_int_srcid[i], &adev->vline0_irq);
3748
3749                 if (r) {
3750                         DRM_ERROR("Failed to add vline0 irq id!\n");
3751                         return r;
3752                 }
3753
3754                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3755                 int_params.irq_source =
3756                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3757
3758                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3759                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3760                         break;
3761                 }
3762
3763                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3764                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3765
3766                 c_irq_params->adev = adev;
3767                 c_irq_params->irq_src = int_params.irq_source;
3768
3769                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3770                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3771         }
3772 #endif
3773
3774         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3775          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3776          * to trigger at end of each vblank, regardless of state of the lock,
3777          * matching DCE behaviour.
3778          */
3779         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3780              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3781              i++) {
3782                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3783
3784                 if (r) {
3785                         DRM_ERROR("Failed to add vupdate irq id!\n");
3786                         return r;
3787                 }
3788
3789                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3790                 int_params.irq_source =
3791                         dc_interrupt_to_irq_source(dc, i, 0);
3792
3793                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3794
3795                 c_irq_params->adev = adev;
3796                 c_irq_params->irq_src = int_params.irq_source;
3797
3798                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3799                                 dm_vupdate_high_irq, c_irq_params);
3800         }
3801
3802         /* Use GRPH_PFLIP interrupt */
3803         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3804                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3805                         i++) {
3806                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3807                 if (r) {
3808                         DRM_ERROR("Failed to add page flip irq id!\n");
3809                         return r;
3810                 }
3811
3812                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3813                 int_params.irq_source =
3814                         dc_interrupt_to_irq_source(dc, i, 0);
3815
3816                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3817
3818                 c_irq_params->adev = adev;
3819                 c_irq_params->irq_src = int_params.irq_source;
3820
3821                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3822                                 dm_pflip_high_irq, c_irq_params);
3823
3824         }
3825
3826         /* HPD */
3827         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3828                         &adev->hpd_irq);
3829         if (r) {
3830                 DRM_ERROR("Failed to add hpd irq id!\n");
3831                 return r;
3832         }
3833
3834         register_hpd_handlers(adev);
3835
3836         return 0;
3837 }
3838 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3839 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3840 {
3841         struct dc *dc = adev->dm.dc;
3842         struct common_irq_params *c_irq_params;
3843         struct dc_interrupt_params int_params = {0};
3844         int r, i;
3845
3846         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3847         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3848
3849         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3850                         &adev->dmub_outbox_irq);
3851         if (r) {
3852                 DRM_ERROR("Failed to add outbox irq id!\n");
3853                 return r;
3854         }
3855
3856         if (dc->ctx->dmub_srv) {
3857                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3858                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3859                 int_params.irq_source =
3860                 dc_interrupt_to_irq_source(dc, i, 0);
3861
3862                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3863
3864                 c_irq_params->adev = adev;
3865                 c_irq_params->irq_src = int_params.irq_source;
3866
3867                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3868                                 dm_dmub_outbox1_low_irq, c_irq_params);
3869         }
3870
3871         return 0;
3872 }
3873
3874 /*
3875  * Acquires the lock for the atomic state object and returns
3876  * the new atomic state.
3877  *
3878  * This should only be called during atomic check.
3879  */
3880 int dm_atomic_get_state(struct drm_atomic_state *state,
3881                         struct dm_atomic_state **dm_state)
3882 {
3883         struct drm_device *dev = state->dev;
3884         struct amdgpu_device *adev = drm_to_adev(dev);
3885         struct amdgpu_display_manager *dm = &adev->dm;
3886         struct drm_private_state *priv_state;
3887
3888         if (*dm_state)
3889                 return 0;
3890
3891         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3892         if (IS_ERR(priv_state))
3893                 return PTR_ERR(priv_state);
3894
3895         *dm_state = to_dm_atomic_state(priv_state);
3896
3897         return 0;
3898 }
3899
3900 static struct dm_atomic_state *
3901 dm_atomic_get_new_state(struct drm_atomic_state *state)
3902 {
3903         struct drm_device *dev = state->dev;
3904         struct amdgpu_device *adev = drm_to_adev(dev);
3905         struct amdgpu_display_manager *dm = &adev->dm;
3906         struct drm_private_obj *obj;
3907         struct drm_private_state *new_obj_state;
3908         int i;
3909
3910         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3911                 if (obj->funcs == dm->atomic_obj.funcs)
3912                         return to_dm_atomic_state(new_obj_state);
3913         }
3914
3915         return NULL;
3916 }
3917
3918 static struct drm_private_state *
3919 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3920 {
3921         struct dm_atomic_state *old_state, *new_state;
3922
3923         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3924         if (!new_state)
3925                 return NULL;
3926
3927         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3928
3929         old_state = to_dm_atomic_state(obj->state);
3930
3931         if (old_state && old_state->context)
3932                 new_state->context = dc_copy_state(old_state->context);
3933
3934         if (!new_state->context) {
3935                 kfree(new_state);
3936                 return NULL;
3937         }
3938
3939         return &new_state->base;
3940 }
3941
3942 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3943                                     struct drm_private_state *state)
3944 {
3945         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3946
3947         if (dm_state && dm_state->context)
3948                 dc_release_state(dm_state->context);
3949
3950         kfree(dm_state);
3951 }
3952
3953 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3954         .atomic_duplicate_state = dm_atomic_duplicate_state,
3955         .atomic_destroy_state = dm_atomic_destroy_state,
3956 };
3957
3958 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3959 {
3960         struct dm_atomic_state *state;
3961         int r;
3962
3963         adev->mode_info.mode_config_initialized = true;
3964
3965         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3966         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3967
3968         adev_to_drm(adev)->mode_config.max_width = 16384;
3969         adev_to_drm(adev)->mode_config.max_height = 16384;
3970
3971         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3972         if (adev->asic_type == CHIP_HAWAII)
3973                 /* disable prefer shadow for now due to hibernation issues */
3974                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3975         else
3976                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3977         /* indicates support for immediate flip */
3978         adev_to_drm(adev)->mode_config.async_page_flip = true;
3979
3980         state = kzalloc(sizeof(*state), GFP_KERNEL);
3981         if (!state)
3982                 return -ENOMEM;
3983
3984         state->context = dc_create_state(adev->dm.dc);
3985         if (!state->context) {
3986                 kfree(state);
3987                 return -ENOMEM;
3988         }
3989
3990         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3991
3992         drm_atomic_private_obj_init(adev_to_drm(adev),
3993                                     &adev->dm.atomic_obj,
3994                                     &state->base,
3995                                     &dm_atomic_state_funcs);
3996
3997         r = amdgpu_display_modeset_create_props(adev);
3998         if (r) {
3999                 dc_release_state(state->context);
4000                 kfree(state);
4001                 return r;
4002         }
4003
4004         r = amdgpu_dm_audio_init(adev);
4005         if (r) {
4006                 dc_release_state(state->context);
4007                 kfree(state);
4008                 return r;
4009         }
4010
4011         return 0;
4012 }
4013
4014 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4015 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4016 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4017
4018 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4019                                             int bl_idx)
4020 {
4021 #if defined(CONFIG_ACPI)
4022         struct amdgpu_dm_backlight_caps caps;
4023
4024         memset(&caps, 0, sizeof(caps));
4025
4026         if (dm->backlight_caps[bl_idx].caps_valid)
4027                 return;
4028
4029         amdgpu_acpi_get_backlight_caps(&caps);
4030         if (caps.caps_valid) {
4031                 dm->backlight_caps[bl_idx].caps_valid = true;
4032                 if (caps.aux_support)
4033                         return;
4034                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4035                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4036         } else {
4037                 dm->backlight_caps[bl_idx].min_input_signal =
4038                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4039                 dm->backlight_caps[bl_idx].max_input_signal =
4040                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4041         }
4042 #else
4043         if (dm->backlight_caps[bl_idx].aux_support)
4044                 return;
4045
4046         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4047         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4048 #endif
4049 }
4050
4051 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4052                                 unsigned *min, unsigned *max)
4053 {
4054         if (!caps)
4055                 return 0;
4056
4057         if (caps->aux_support) {
4058                 // Firmware limits are in nits, DC API wants millinits.
4059                 *max = 1000 * caps->aux_max_input_signal;
4060                 *min = 1000 * caps->aux_min_input_signal;
4061         } else {
4062                 // Firmware limits are 8-bit, PWM control is 16-bit.
4063                 *max = 0x101 * caps->max_input_signal;
4064                 *min = 0x101 * caps->min_input_signal;
4065         }
4066         return 1;
4067 }
4068
4069 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4070                                         uint32_t brightness)
4071 {
4072         unsigned min, max;
4073
4074         if (!get_brightness_range(caps, &min, &max))
4075                 return brightness;
4076
4077         // Rescale 0..255 to min..max
4078         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4079                                        AMDGPU_MAX_BL_LEVEL);
4080 }
4081
4082 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4083                                       uint32_t brightness)
4084 {
4085         unsigned min, max;
4086
4087         if (!get_brightness_range(caps, &min, &max))
4088                 return brightness;
4089
4090         if (brightness < min)
4091                 return 0;
4092         // Rescale min..max to 0..255
4093         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4094                                  max - min);
4095 }
4096
4097 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4098                                          int bl_idx,
4099                                          u32 user_brightness)
4100 {
4101         struct amdgpu_dm_backlight_caps caps;
4102         struct dc_link *link;
4103         u32 brightness;
4104         bool rc;
4105
4106         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4107         caps = dm->backlight_caps[bl_idx];
4108
4109         dm->brightness[bl_idx] = user_brightness;
4110         /* update scratch register */
4111         if (bl_idx == 0)
4112                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4113         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4114         link = (struct dc_link *)dm->backlight_link[bl_idx];
4115
4116         /* Change brightness based on AUX property */
4117         if (caps.aux_support) {
4118                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4119                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4120                 if (!rc)
4121                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4122         } else {
4123                 rc = dc_link_set_backlight_level(link, brightness, 0);
4124                 if (!rc)
4125                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4126         }
4127
4128         if (rc)
4129                 dm->actual_brightness[bl_idx] = user_brightness;
4130 }
4131
4132 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4133 {
4134         struct amdgpu_display_manager *dm = bl_get_data(bd);
4135         int i;
4136
4137         for (i = 0; i < dm->num_of_edps; i++) {
4138                 if (bd == dm->backlight_dev[i])
4139                         break;
4140         }
4141         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4142                 i = 0;
4143         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4144
4145         return 0;
4146 }
4147
4148 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4149                                          int bl_idx)
4150 {
4151         struct amdgpu_dm_backlight_caps caps;
4152         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4153
4154         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4155         caps = dm->backlight_caps[bl_idx];
4156
4157         if (caps.aux_support) {
4158                 u32 avg, peak;
4159                 bool rc;
4160
4161                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4162                 if (!rc)
4163                         return dm->brightness[bl_idx];
4164                 return convert_brightness_to_user(&caps, avg);
4165         } else {
4166                 int ret = dc_link_get_backlight_level(link);
4167
4168                 if (ret == DC_ERROR_UNEXPECTED)
4169                         return dm->brightness[bl_idx];
4170                 return convert_brightness_to_user(&caps, ret);
4171         }
4172 }
4173
4174 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4175 {
4176         struct amdgpu_display_manager *dm = bl_get_data(bd);
4177         int i;
4178
4179         for (i = 0; i < dm->num_of_edps; i++) {
4180                 if (bd == dm->backlight_dev[i])
4181                         break;
4182         }
4183         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4184                 i = 0;
4185         return amdgpu_dm_backlight_get_level(dm, i);
4186 }
4187
4188 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4189         .options = BL_CORE_SUSPENDRESUME,
4190         .get_brightness = amdgpu_dm_backlight_get_brightness,
4191         .update_status  = amdgpu_dm_backlight_update_status,
4192 };
4193
4194 static void
4195 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4196 {
4197         struct drm_device *drm = aconnector->base.dev;
4198         struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4199         struct backlight_properties props = { 0 };
4200         char bl_name[16];
4201
4202         if (aconnector->bl_idx == -1)
4203                 return;
4204
4205         if (!acpi_video_backlight_use_native()) {
4206                 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4207                 /* Try registering an ACPI video backlight device instead. */
4208                 acpi_video_register_backlight();
4209                 return;
4210         }
4211
4212         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4213         props.brightness = AMDGPU_MAX_BL_LEVEL;
4214         props.type = BACKLIGHT_RAW;
4215
4216         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4217                  drm->primary->index + aconnector->bl_idx);
4218
4219         dm->backlight_dev[aconnector->bl_idx] =
4220                 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4221                                           &amdgpu_dm_backlight_ops, &props);
4222
4223         if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4224                 DRM_ERROR("DM: Backlight registration failed!\n");
4225                 dm->backlight_dev[aconnector->bl_idx] = NULL;
4226         } else
4227                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4228 }
4229
4230 static int initialize_plane(struct amdgpu_display_manager *dm,
4231                             struct amdgpu_mode_info *mode_info, int plane_id,
4232                             enum drm_plane_type plane_type,
4233                             const struct dc_plane_cap *plane_cap)
4234 {
4235         struct drm_plane *plane;
4236         unsigned long possible_crtcs;
4237         int ret = 0;
4238
4239         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4240         if (!plane) {
4241                 DRM_ERROR("KMS: Failed to allocate plane\n");
4242                 return -ENOMEM;
4243         }
4244         plane->type = plane_type;
4245
4246         /*
4247          * HACK: IGT tests expect that the primary plane for a CRTC
4248          * can only have one possible CRTC. Only expose support for
4249          * any CRTC if they're not going to be used as a primary plane
4250          * for a CRTC - like overlay or underlay planes.
4251          */
4252         possible_crtcs = 1 << plane_id;
4253         if (plane_id >= dm->dc->caps.max_streams)
4254                 possible_crtcs = 0xff;
4255
4256         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4257
4258         if (ret) {
4259                 DRM_ERROR("KMS: Failed to initialize plane\n");
4260                 kfree(plane);
4261                 return ret;
4262         }
4263
4264         if (mode_info)
4265                 mode_info->planes[plane_id] = plane;
4266
4267         return ret;
4268 }
4269
4270
4271 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4272                                    struct amdgpu_dm_connector *aconnector)
4273 {
4274         struct dc_link *link = aconnector->dc_link;
4275         int bl_idx = dm->num_of_edps;
4276
4277         if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4278             link->type == dc_connection_none)
4279                 return;
4280
4281         if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4282                 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4283                 return;
4284         }
4285
4286         aconnector->bl_idx = bl_idx;
4287
4288         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4289         dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4290         dm->backlight_link[bl_idx] = link;
4291         dm->num_of_edps++;
4292
4293         update_connector_ext_caps(aconnector);
4294 }
4295
4296 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4297
4298 /*
4299  * In this architecture, the association
4300  * connector -> encoder -> crtc
4301  * id not really requried. The crtc and connector will hold the
4302  * display_index as an abstraction to use with DAL component
4303  *
4304  * Returns 0 on success
4305  */
4306 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4307 {
4308         struct amdgpu_display_manager *dm = &adev->dm;
4309         s32 i;
4310         struct amdgpu_dm_connector *aconnector = NULL;
4311         struct amdgpu_encoder *aencoder = NULL;
4312         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4313         u32 link_cnt;
4314         s32 primary_planes;
4315         enum dc_connection_type new_connection_type = dc_connection_none;
4316         const struct dc_plane_cap *plane;
4317         bool psr_feature_enabled = false;
4318         int max_overlay = dm->dc->caps.max_slave_planes;
4319
4320         dm->display_indexes_num = dm->dc->caps.max_streams;
4321         /* Update the actual used number of crtc */
4322         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4323
4324         amdgpu_dm_set_irq_funcs(adev);
4325
4326         link_cnt = dm->dc->caps.max_links;
4327         if (amdgpu_dm_mode_config_init(dm->adev)) {
4328                 DRM_ERROR("DM: Failed to initialize mode config\n");
4329                 return -EINVAL;
4330         }
4331
4332         /* There is one primary plane per CRTC */
4333         primary_planes = dm->dc->caps.max_streams;
4334         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4335
4336         /*
4337          * Initialize primary planes, implicit planes for legacy IOCTLS.
4338          * Order is reversed to match iteration order in atomic check.
4339          */
4340         for (i = (primary_planes - 1); i >= 0; i--) {
4341                 plane = &dm->dc->caps.planes[i];
4342
4343                 if (initialize_plane(dm, mode_info, i,
4344                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4345                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4346                         goto fail;
4347                 }
4348         }
4349
4350         /*
4351          * Initialize overlay planes, index starting after primary planes.
4352          * These planes have a higher DRM index than the primary planes since
4353          * they should be considered as having a higher z-order.
4354          * Order is reversed to match iteration order in atomic check.
4355          *
4356          * Only support DCN for now, and only expose one so we don't encourage
4357          * userspace to use up all the pipes.
4358          */
4359         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4360                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4361
4362                 /* Do not create overlay if MPO disabled */
4363                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4364                         break;
4365
4366                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4367                         continue;
4368
4369                 if (!plane->pixel_format_support.argb8888)
4370                         continue;
4371
4372                 if (max_overlay-- == 0)
4373                         break;
4374
4375                 if (initialize_plane(dm, NULL, primary_planes + i,
4376                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4377                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4378                         goto fail;
4379                 }
4380         }
4381
4382         for (i = 0; i < dm->dc->caps.max_streams; i++)
4383                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4384                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4385                         goto fail;
4386                 }
4387
4388         /* Use Outbox interrupt */
4389         switch (adev->ip_versions[DCE_HWIP][0]) {
4390         case IP_VERSION(3, 0, 0):
4391         case IP_VERSION(3, 1, 2):
4392         case IP_VERSION(3, 1, 3):
4393         case IP_VERSION(3, 1, 4):
4394         case IP_VERSION(3, 1, 5):
4395         case IP_VERSION(3, 1, 6):
4396         case IP_VERSION(3, 2, 0):
4397         case IP_VERSION(3, 2, 1):
4398         case IP_VERSION(2, 1, 0):
4399                 if (register_outbox_irq_handlers(dm->adev)) {
4400                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4401                         goto fail;
4402                 }
4403                 break;
4404         default:
4405                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4406                               adev->ip_versions[DCE_HWIP][0]);
4407         }
4408
4409         /* Determine whether to enable PSR support by default. */
4410         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4411                 switch (adev->ip_versions[DCE_HWIP][0]) {
4412                 case IP_VERSION(3, 1, 2):
4413                 case IP_VERSION(3, 1, 3):
4414                 case IP_VERSION(3, 1, 4):
4415                 case IP_VERSION(3, 1, 5):
4416                 case IP_VERSION(3, 1, 6):
4417                 case IP_VERSION(3, 2, 0):
4418                 case IP_VERSION(3, 2, 1):
4419                         psr_feature_enabled = true;
4420                         break;
4421                 default:
4422                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4423                         break;
4424                 }
4425         }
4426
4427         /* loops over all connectors on the board */
4428         for (i = 0; i < link_cnt; i++) {
4429                 struct dc_link *link = NULL;
4430
4431                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4432                         DRM_ERROR(
4433                                 "KMS: Cannot support more than %d display indexes\n",
4434                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4435                         continue;
4436                 }
4437
4438                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4439                 if (!aconnector)
4440                         goto fail;
4441
4442                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4443                 if (!aencoder)
4444                         goto fail;
4445
4446                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4447                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4448                         goto fail;
4449                 }
4450
4451                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4452                         DRM_ERROR("KMS: Failed to initialize connector\n");
4453                         goto fail;
4454                 }
4455
4456                 link = dc_get_link_at_index(dm->dc, i);
4457
4458                 if (!dc_link_detect_connection_type(link, &new_connection_type))
4459                         DRM_ERROR("KMS: Failed to detect connector\n");
4460
4461                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4462                         emulated_link_detect(link);
4463                         amdgpu_dm_update_connector_after_detect(aconnector);
4464                 } else {
4465                         bool ret = false;
4466
4467                         mutex_lock(&dm->dc_lock);
4468                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4469                         mutex_unlock(&dm->dc_lock);
4470
4471                         if (ret) {
4472                                 amdgpu_dm_update_connector_after_detect(aconnector);
4473                                 setup_backlight_device(dm, aconnector);
4474
4475                                 if (psr_feature_enabled)
4476                                         amdgpu_dm_set_psr_caps(link);
4477
4478                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4479                                  * PSR is also supported.
4480                                  */
4481                                 if (link->psr_settings.psr_feature_enabled)
4482                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4483                         }
4484                 }
4485                 amdgpu_set_panel_orientation(&aconnector->base);
4486         }
4487
4488         /* Software is initialized. Now we can register interrupt handlers. */
4489         switch (adev->asic_type) {
4490 #if defined(CONFIG_DRM_AMD_DC_SI)
4491         case CHIP_TAHITI:
4492         case CHIP_PITCAIRN:
4493         case CHIP_VERDE:
4494         case CHIP_OLAND:
4495                 if (dce60_register_irq_handlers(dm->adev)) {
4496                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4497                         goto fail;
4498                 }
4499                 break;
4500 #endif
4501         case CHIP_BONAIRE:
4502         case CHIP_HAWAII:
4503         case CHIP_KAVERI:
4504         case CHIP_KABINI:
4505         case CHIP_MULLINS:
4506         case CHIP_TONGA:
4507         case CHIP_FIJI:
4508         case CHIP_CARRIZO:
4509         case CHIP_STONEY:
4510         case CHIP_POLARIS11:
4511         case CHIP_POLARIS10:
4512         case CHIP_POLARIS12:
4513         case CHIP_VEGAM:
4514         case CHIP_VEGA10:
4515         case CHIP_VEGA12:
4516         case CHIP_VEGA20:
4517                 if (dce110_register_irq_handlers(dm->adev)) {
4518                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4519                         goto fail;
4520                 }
4521                 break;
4522         default:
4523                 switch (adev->ip_versions[DCE_HWIP][0]) {
4524                 case IP_VERSION(1, 0, 0):
4525                 case IP_VERSION(1, 0, 1):
4526                 case IP_VERSION(2, 0, 2):
4527                 case IP_VERSION(2, 0, 3):
4528                 case IP_VERSION(2, 0, 0):
4529                 case IP_VERSION(2, 1, 0):
4530                 case IP_VERSION(3, 0, 0):
4531                 case IP_VERSION(3, 0, 2):
4532                 case IP_VERSION(3, 0, 3):
4533                 case IP_VERSION(3, 0, 1):
4534                 case IP_VERSION(3, 1, 2):
4535                 case IP_VERSION(3, 1, 3):
4536                 case IP_VERSION(3, 1, 4):
4537                 case IP_VERSION(3, 1, 5):
4538                 case IP_VERSION(3, 1, 6):
4539                 case IP_VERSION(3, 2, 0):
4540                 case IP_VERSION(3, 2, 1):
4541                         if (dcn10_register_irq_handlers(dm->adev)) {
4542                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4543                                 goto fail;
4544                         }
4545                         break;
4546                 default:
4547                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4548                                         adev->ip_versions[DCE_HWIP][0]);
4549                         goto fail;
4550                 }
4551                 break;
4552         }
4553
4554         return 0;
4555 fail:
4556         kfree(aencoder);
4557         kfree(aconnector);
4558
4559         return -EINVAL;
4560 }
4561
4562 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4563 {
4564         drm_atomic_private_obj_fini(&dm->atomic_obj);
4565         return;
4566 }
4567
4568 /******************************************************************************
4569  * amdgpu_display_funcs functions
4570  *****************************************************************************/
4571
4572 /*
4573  * dm_bandwidth_update - program display watermarks
4574  *
4575  * @adev: amdgpu_device pointer
4576  *
4577  * Calculate and program the display watermarks and line buffer allocation.
4578  */
4579 static void dm_bandwidth_update(struct amdgpu_device *adev)
4580 {
4581         /* TODO: implement later */
4582 }
4583
4584 static const struct amdgpu_display_funcs dm_display_funcs = {
4585         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4586         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4587         .backlight_set_level = NULL, /* never called for DC */
4588         .backlight_get_level = NULL, /* never called for DC */
4589         .hpd_sense = NULL,/* called unconditionally */
4590         .hpd_set_polarity = NULL, /* called unconditionally */
4591         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4592         .page_flip_get_scanoutpos =
4593                 dm_crtc_get_scanoutpos,/* called unconditionally */
4594         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4595         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4596 };
4597
4598 #if defined(CONFIG_DEBUG_KERNEL_DC)
4599
4600 static ssize_t s3_debug_store(struct device *device,
4601                               struct device_attribute *attr,
4602                               const char *buf,
4603                               size_t count)
4604 {
4605         int ret;
4606         int s3_state;
4607         struct drm_device *drm_dev = dev_get_drvdata(device);
4608         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4609
4610         ret = kstrtoint(buf, 0, &s3_state);
4611
4612         if (ret == 0) {
4613                 if (s3_state) {
4614                         dm_resume(adev);
4615                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4616                 } else
4617                         dm_suspend(adev);
4618         }
4619
4620         return ret == 0 ? count : 0;
4621 }
4622
4623 DEVICE_ATTR_WO(s3_debug);
4624
4625 #endif
4626
4627 static int dm_init_microcode(struct amdgpu_device *adev)
4628 {
4629         char *fw_name_dmub;
4630         int r;
4631
4632         switch (adev->ip_versions[DCE_HWIP][0]) {
4633         case IP_VERSION(2, 1, 0):
4634                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4635                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4636                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4637                 break;
4638         case IP_VERSION(3, 0, 0):
4639                 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4640                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4641                 else
4642                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4643                 break;
4644         case IP_VERSION(3, 0, 1):
4645                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4646                 break;
4647         case IP_VERSION(3, 0, 2):
4648                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4649                 break;
4650         case IP_VERSION(3, 0, 3):
4651                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4652                 break;
4653         case IP_VERSION(3, 1, 2):
4654         case IP_VERSION(3, 1, 3):
4655                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4656                 break;
4657         case IP_VERSION(3, 1, 4):
4658                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4659                 break;
4660         case IP_VERSION(3, 1, 5):
4661                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4662                 break;
4663         case IP_VERSION(3, 1, 6):
4664                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4665                 break;
4666         case IP_VERSION(3, 2, 0):
4667                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4668                 break;
4669         case IP_VERSION(3, 2, 1):
4670                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4671                 break;
4672         default:
4673                 /* ASIC doesn't support DMUB. */
4674                 return 0;
4675         }
4676         r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4677         if (r)
4678                 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4679         return r;
4680 }
4681
4682 static int dm_early_init(void *handle)
4683 {
4684         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4685         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4686         struct atom_context *ctx = mode_info->atom_context;
4687         int index = GetIndexIntoMasterTable(DATA, Object_Header);
4688         u16 data_offset;
4689
4690         /* if there is no object header, skip DM */
4691         if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4692                 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4693                 dev_info(adev->dev, "No object header, skipping DM\n");
4694                 return -ENOENT;
4695         }
4696
4697         switch (adev->asic_type) {
4698 #if defined(CONFIG_DRM_AMD_DC_SI)
4699         case CHIP_TAHITI:
4700         case CHIP_PITCAIRN:
4701         case CHIP_VERDE:
4702                 adev->mode_info.num_crtc = 6;
4703                 adev->mode_info.num_hpd = 6;
4704                 adev->mode_info.num_dig = 6;
4705                 break;
4706         case CHIP_OLAND:
4707                 adev->mode_info.num_crtc = 2;
4708                 adev->mode_info.num_hpd = 2;
4709                 adev->mode_info.num_dig = 2;
4710                 break;
4711 #endif
4712         case CHIP_BONAIRE:
4713         case CHIP_HAWAII:
4714                 adev->mode_info.num_crtc = 6;
4715                 adev->mode_info.num_hpd = 6;
4716                 adev->mode_info.num_dig = 6;
4717                 break;
4718         case CHIP_KAVERI:
4719                 adev->mode_info.num_crtc = 4;
4720                 adev->mode_info.num_hpd = 6;
4721                 adev->mode_info.num_dig = 7;
4722                 break;
4723         case CHIP_KABINI:
4724         case CHIP_MULLINS:
4725                 adev->mode_info.num_crtc = 2;
4726                 adev->mode_info.num_hpd = 6;
4727                 adev->mode_info.num_dig = 6;
4728                 break;
4729         case CHIP_FIJI:
4730         case CHIP_TONGA:
4731                 adev->mode_info.num_crtc = 6;
4732                 adev->mode_info.num_hpd = 6;
4733                 adev->mode_info.num_dig = 7;
4734                 break;
4735         case CHIP_CARRIZO:
4736                 adev->mode_info.num_crtc = 3;
4737                 adev->mode_info.num_hpd = 6;
4738                 adev->mode_info.num_dig = 9;
4739                 break;
4740         case CHIP_STONEY:
4741                 adev->mode_info.num_crtc = 2;
4742                 adev->mode_info.num_hpd = 6;
4743                 adev->mode_info.num_dig = 9;
4744                 break;
4745         case CHIP_POLARIS11:
4746         case CHIP_POLARIS12:
4747                 adev->mode_info.num_crtc = 5;
4748                 adev->mode_info.num_hpd = 5;
4749                 adev->mode_info.num_dig = 5;
4750                 break;
4751         case CHIP_POLARIS10:
4752         case CHIP_VEGAM:
4753                 adev->mode_info.num_crtc = 6;
4754                 adev->mode_info.num_hpd = 6;
4755                 adev->mode_info.num_dig = 6;
4756                 break;
4757         case CHIP_VEGA10:
4758         case CHIP_VEGA12:
4759         case CHIP_VEGA20:
4760                 adev->mode_info.num_crtc = 6;
4761                 adev->mode_info.num_hpd = 6;
4762                 adev->mode_info.num_dig = 6;
4763                 break;
4764         default:
4765
4766                 switch (adev->ip_versions[DCE_HWIP][0]) {
4767                 case IP_VERSION(2, 0, 2):
4768                 case IP_VERSION(3, 0, 0):
4769                         adev->mode_info.num_crtc = 6;
4770                         adev->mode_info.num_hpd = 6;
4771                         adev->mode_info.num_dig = 6;
4772                         break;
4773                 case IP_VERSION(2, 0, 0):
4774                 case IP_VERSION(3, 0, 2):
4775                         adev->mode_info.num_crtc = 5;
4776                         adev->mode_info.num_hpd = 5;
4777                         adev->mode_info.num_dig = 5;
4778                         break;
4779                 case IP_VERSION(2, 0, 3):
4780                 case IP_VERSION(3, 0, 3):
4781                         adev->mode_info.num_crtc = 2;
4782                         adev->mode_info.num_hpd = 2;
4783                         adev->mode_info.num_dig = 2;
4784                         break;
4785                 case IP_VERSION(1, 0, 0):
4786                 case IP_VERSION(1, 0, 1):
4787                 case IP_VERSION(3, 0, 1):
4788                 case IP_VERSION(2, 1, 0):
4789                 case IP_VERSION(3, 1, 2):
4790                 case IP_VERSION(3, 1, 3):
4791                 case IP_VERSION(3, 1, 4):
4792                 case IP_VERSION(3, 1, 5):
4793                 case IP_VERSION(3, 1, 6):
4794                 case IP_VERSION(3, 2, 0):
4795                 case IP_VERSION(3, 2, 1):
4796                         adev->mode_info.num_crtc = 4;
4797                         adev->mode_info.num_hpd = 4;
4798                         adev->mode_info.num_dig = 4;
4799                         break;
4800                 default:
4801                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4802                                         adev->ip_versions[DCE_HWIP][0]);
4803                         return -EINVAL;
4804                 }
4805                 break;
4806         }
4807
4808         if (adev->mode_info.funcs == NULL)
4809                 adev->mode_info.funcs = &dm_display_funcs;
4810
4811         /*
4812          * Note: Do NOT change adev->audio_endpt_rreg and
4813          * adev->audio_endpt_wreg because they are initialised in
4814          * amdgpu_device_init()
4815          */
4816 #if defined(CONFIG_DEBUG_KERNEL_DC)
4817         device_create_file(
4818                 adev_to_drm(adev)->dev,
4819                 &dev_attr_s3_debug);
4820 #endif
4821         adev->dc_enabled = true;
4822
4823         return dm_init_microcode(adev);
4824 }
4825
4826 static bool modereset_required(struct drm_crtc_state *crtc_state)
4827 {
4828         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4829 }
4830
4831 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4832 {
4833         drm_encoder_cleanup(encoder);
4834         kfree(encoder);
4835 }
4836
4837 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4838         .destroy = amdgpu_dm_encoder_destroy,
4839 };
4840
4841 static int
4842 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4843                             const enum surface_pixel_format format,
4844                             enum dc_color_space *color_space)
4845 {
4846         bool full_range;
4847
4848         *color_space = COLOR_SPACE_SRGB;
4849
4850         /* DRM color properties only affect non-RGB formats. */
4851         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4852                 return 0;
4853
4854         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4855
4856         switch (plane_state->color_encoding) {
4857         case DRM_COLOR_YCBCR_BT601:
4858                 if (full_range)
4859                         *color_space = COLOR_SPACE_YCBCR601;
4860                 else
4861                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4862                 break;
4863
4864         case DRM_COLOR_YCBCR_BT709:
4865                 if (full_range)
4866                         *color_space = COLOR_SPACE_YCBCR709;
4867                 else
4868                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4869                 break;
4870
4871         case DRM_COLOR_YCBCR_BT2020:
4872                 if (full_range)
4873                         *color_space = COLOR_SPACE_2020_YCBCR;
4874                 else
4875                         return -EINVAL;
4876                 break;
4877
4878         default:
4879                 return -EINVAL;
4880         }
4881
4882         return 0;
4883 }
4884
4885 static int
4886 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4887                             const struct drm_plane_state *plane_state,
4888                             const u64 tiling_flags,
4889                             struct dc_plane_info *plane_info,
4890                             struct dc_plane_address *address,
4891                             bool tmz_surface,
4892                             bool force_disable_dcc)
4893 {
4894         const struct drm_framebuffer *fb = plane_state->fb;
4895         const struct amdgpu_framebuffer *afb =
4896                 to_amdgpu_framebuffer(plane_state->fb);
4897         int ret;
4898
4899         memset(plane_info, 0, sizeof(*plane_info));
4900
4901         switch (fb->format->format) {
4902         case DRM_FORMAT_C8:
4903                 plane_info->format =
4904                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4905                 break;
4906         case DRM_FORMAT_RGB565:
4907                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4908                 break;
4909         case DRM_FORMAT_XRGB8888:
4910         case DRM_FORMAT_ARGB8888:
4911                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4912                 break;
4913         case DRM_FORMAT_XRGB2101010:
4914         case DRM_FORMAT_ARGB2101010:
4915                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4916                 break;
4917         case DRM_FORMAT_XBGR2101010:
4918         case DRM_FORMAT_ABGR2101010:
4919                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4920                 break;
4921         case DRM_FORMAT_XBGR8888:
4922         case DRM_FORMAT_ABGR8888:
4923                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4924                 break;
4925         case DRM_FORMAT_NV21:
4926                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4927                 break;
4928         case DRM_FORMAT_NV12:
4929                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4930                 break;
4931         case DRM_FORMAT_P010:
4932                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4933                 break;
4934         case DRM_FORMAT_XRGB16161616F:
4935         case DRM_FORMAT_ARGB16161616F:
4936                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4937                 break;
4938         case DRM_FORMAT_XBGR16161616F:
4939         case DRM_FORMAT_ABGR16161616F:
4940                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4941                 break;
4942         case DRM_FORMAT_XRGB16161616:
4943         case DRM_FORMAT_ARGB16161616:
4944                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4945                 break;
4946         case DRM_FORMAT_XBGR16161616:
4947         case DRM_FORMAT_ABGR16161616:
4948                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4949                 break;
4950         default:
4951                 DRM_ERROR(
4952                         "Unsupported screen format %p4cc\n",
4953                         &fb->format->format);
4954                 return -EINVAL;
4955         }
4956
4957         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4958         case DRM_MODE_ROTATE_0:
4959                 plane_info->rotation = ROTATION_ANGLE_0;
4960                 break;
4961         case DRM_MODE_ROTATE_90:
4962                 plane_info->rotation = ROTATION_ANGLE_90;
4963                 break;
4964         case DRM_MODE_ROTATE_180:
4965                 plane_info->rotation = ROTATION_ANGLE_180;
4966                 break;
4967         case DRM_MODE_ROTATE_270:
4968                 plane_info->rotation = ROTATION_ANGLE_270;
4969                 break;
4970         default:
4971                 plane_info->rotation = ROTATION_ANGLE_0;
4972                 break;
4973         }
4974
4975
4976         plane_info->visible = true;
4977         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4978
4979         plane_info->layer_index = plane_state->normalized_zpos;
4980
4981         ret = fill_plane_color_attributes(plane_state, plane_info->format,
4982                                           &plane_info->color_space);
4983         if (ret)
4984                 return ret;
4985
4986         ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
4987                                            plane_info->rotation, tiling_flags,
4988                                            &plane_info->tiling_info,
4989                                            &plane_info->plane_size,
4990                                            &plane_info->dcc, address,
4991                                            tmz_surface, force_disable_dcc);
4992         if (ret)
4993                 return ret;
4994
4995         amdgpu_dm_plane_fill_blending_from_plane_state(
4996                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4997                 &plane_info->global_alpha, &plane_info->global_alpha_value);
4998
4999         return 0;
5000 }
5001
5002 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5003                                     struct dc_plane_state *dc_plane_state,
5004                                     struct drm_plane_state *plane_state,
5005                                     struct drm_crtc_state *crtc_state)
5006 {
5007         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5008         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5009         struct dc_scaling_info scaling_info;
5010         struct dc_plane_info plane_info;
5011         int ret;
5012         bool force_disable_dcc = false;
5013
5014         ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5015         if (ret)
5016                 return ret;
5017
5018         dc_plane_state->src_rect = scaling_info.src_rect;
5019         dc_plane_state->dst_rect = scaling_info.dst_rect;
5020         dc_plane_state->clip_rect = scaling_info.clip_rect;
5021         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5022
5023         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5024         ret = fill_dc_plane_info_and_addr(adev, plane_state,
5025                                           afb->tiling_flags,
5026                                           &plane_info,
5027                                           &dc_plane_state->address,
5028                                           afb->tmz_surface,
5029                                           force_disable_dcc);
5030         if (ret)
5031                 return ret;
5032
5033         dc_plane_state->format = plane_info.format;
5034         dc_plane_state->color_space = plane_info.color_space;
5035         dc_plane_state->format = plane_info.format;
5036         dc_plane_state->plane_size = plane_info.plane_size;
5037         dc_plane_state->rotation = plane_info.rotation;
5038         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5039         dc_plane_state->stereo_format = plane_info.stereo_format;
5040         dc_plane_state->tiling_info = plane_info.tiling_info;
5041         dc_plane_state->visible = plane_info.visible;
5042         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5043         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5044         dc_plane_state->global_alpha = plane_info.global_alpha;
5045         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5046         dc_plane_state->dcc = plane_info.dcc;
5047         dc_plane_state->layer_index = plane_info.layer_index;
5048         dc_plane_state->flip_int_enabled = true;
5049
5050         /*
5051          * Always set input transfer function, since plane state is refreshed
5052          * every time.
5053          */
5054         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5055         if (ret)
5056                 return ret;
5057
5058         return 0;
5059 }
5060
5061 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5062                                       struct rect *dirty_rect, int32_t x,
5063                                       s32 y, s32 width, s32 height,
5064                                       int *i, bool ffu)
5065 {
5066         if (*i > DC_MAX_DIRTY_RECTS)
5067                 return;
5068
5069         if (*i == DC_MAX_DIRTY_RECTS)
5070                 goto out;
5071
5072         dirty_rect->x = x;
5073         dirty_rect->y = y;
5074         dirty_rect->width = width;
5075         dirty_rect->height = height;
5076
5077         if (ffu)
5078                 drm_dbg(plane->dev,
5079                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5080                         plane->base.id, width, height);
5081         else
5082                 drm_dbg(plane->dev,
5083                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5084                         plane->base.id, x, y, width, height);
5085
5086 out:
5087         (*i)++;
5088 }
5089
5090 /**
5091  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5092  *
5093  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5094  *         remote fb
5095  * @old_plane_state: Old state of @plane
5096  * @new_plane_state: New state of @plane
5097  * @crtc_state: New state of CRTC connected to the @plane
5098  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5099  * @dirty_regions_changed: dirty regions changed
5100  *
5101  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5102  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5103  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5104  * amdgpu_dm's.
5105  *
5106  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5107  * plane with regions that require flushing to the eDP remote buffer. In
5108  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5109  * implicitly provide damage clips without any client support via the plane
5110  * bounds.
5111  */
5112 static void fill_dc_dirty_rects(struct drm_plane *plane,
5113                                 struct drm_plane_state *old_plane_state,
5114                                 struct drm_plane_state *new_plane_state,
5115                                 struct drm_crtc_state *crtc_state,
5116                                 struct dc_flip_addrs *flip_addrs,
5117                                 bool *dirty_regions_changed)
5118 {
5119         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5120         struct rect *dirty_rects = flip_addrs->dirty_rects;
5121         u32 num_clips;
5122         struct drm_mode_rect *clips;
5123         bool bb_changed;
5124         bool fb_changed;
5125         u32 i = 0;
5126         *dirty_regions_changed = false;
5127
5128         /*
5129          * Cursor plane has it's own dirty rect update interface. See
5130          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5131          */
5132         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5133                 return;
5134
5135         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5136         clips = drm_plane_get_damage_clips(new_plane_state);
5137
5138         if (!dm_crtc_state->mpo_requested) {
5139                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5140                         goto ffu;
5141
5142                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5143                         fill_dc_dirty_rect(new_plane_state->plane,
5144                                            &dirty_rects[flip_addrs->dirty_rect_count],
5145                                            clips->x1, clips->y1,
5146                                            clips->x2 - clips->x1, clips->y2 - clips->y1,
5147                                            &flip_addrs->dirty_rect_count,
5148                                            false);
5149                 return;
5150         }
5151
5152         /*
5153          * MPO is requested. Add entire plane bounding box to dirty rects if
5154          * flipped to or damaged.
5155          *
5156          * If plane is moved or resized, also add old bounding box to dirty
5157          * rects.
5158          */
5159         fb_changed = old_plane_state->fb->base.id !=
5160                      new_plane_state->fb->base.id;
5161         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5162                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
5163                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
5164                       old_plane_state->crtc_h != new_plane_state->crtc_h);
5165
5166         drm_dbg(plane->dev,
5167                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5168                 new_plane_state->plane->base.id,
5169                 bb_changed, fb_changed, num_clips);
5170
5171         *dirty_regions_changed = bb_changed;
5172
5173         if (bb_changed) {
5174                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5175                                    new_plane_state->crtc_x,
5176                                    new_plane_state->crtc_y,
5177                                    new_plane_state->crtc_w,
5178                                    new_plane_state->crtc_h, &i, false);
5179
5180                 /* Add old plane bounding-box if plane is moved or resized */
5181                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5182                                    old_plane_state->crtc_x,
5183                                    old_plane_state->crtc_y,
5184                                    old_plane_state->crtc_w,
5185                                    old_plane_state->crtc_h, &i, false);
5186         }
5187
5188         if (num_clips) {
5189                 for (; i < num_clips; clips++)
5190                         fill_dc_dirty_rect(new_plane_state->plane,
5191                                            &dirty_rects[i], clips->x1,
5192                                            clips->y1, clips->x2 - clips->x1,
5193                                            clips->y2 - clips->y1, &i, false);
5194         } else if (fb_changed && !bb_changed) {
5195                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5196                                    new_plane_state->crtc_x,
5197                                    new_plane_state->crtc_y,
5198                                    new_plane_state->crtc_w,
5199                                    new_plane_state->crtc_h, &i, false);
5200         }
5201
5202         if (i > DC_MAX_DIRTY_RECTS)
5203                 goto ffu;
5204
5205         flip_addrs->dirty_rect_count = i;
5206         return;
5207
5208 ffu:
5209         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5210                            dm_crtc_state->base.mode.crtc_hdisplay,
5211                            dm_crtc_state->base.mode.crtc_vdisplay,
5212                            &flip_addrs->dirty_rect_count, true);
5213 }
5214
5215 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5216                                            const struct dm_connector_state *dm_state,
5217                                            struct dc_stream_state *stream)
5218 {
5219         enum amdgpu_rmx_type rmx_type;
5220
5221         struct rect src = { 0 }; /* viewport in composition space*/
5222         struct rect dst = { 0 }; /* stream addressable area */
5223
5224         /* no mode. nothing to be done */
5225         if (!mode)
5226                 return;
5227
5228         /* Full screen scaling by default */
5229         src.width = mode->hdisplay;
5230         src.height = mode->vdisplay;
5231         dst.width = stream->timing.h_addressable;
5232         dst.height = stream->timing.v_addressable;
5233
5234         if (dm_state) {
5235                 rmx_type = dm_state->scaling;
5236                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5237                         if (src.width * dst.height <
5238                                         src.height * dst.width) {
5239                                 /* height needs less upscaling/more downscaling */
5240                                 dst.width = src.width *
5241                                                 dst.height / src.height;
5242                         } else {
5243                                 /* width needs less upscaling/more downscaling */
5244                                 dst.height = src.height *
5245                                                 dst.width / src.width;
5246                         }
5247                 } else if (rmx_type == RMX_CENTER) {
5248                         dst = src;
5249                 }
5250
5251                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5252                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5253
5254                 if (dm_state->underscan_enable) {
5255                         dst.x += dm_state->underscan_hborder / 2;
5256                         dst.y += dm_state->underscan_vborder / 2;
5257                         dst.width -= dm_state->underscan_hborder;
5258                         dst.height -= dm_state->underscan_vborder;
5259                 }
5260         }
5261
5262         stream->src = src;
5263         stream->dst = dst;
5264
5265         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5266                       dst.x, dst.y, dst.width, dst.height);
5267
5268 }
5269
5270 static enum dc_color_depth
5271 convert_color_depth_from_display_info(const struct drm_connector *connector,
5272                                       bool is_y420, int requested_bpc)
5273 {
5274         u8 bpc;
5275
5276         if (is_y420) {
5277                 bpc = 8;
5278
5279                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5280                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5281                         bpc = 16;
5282                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5283                         bpc = 12;
5284                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5285                         bpc = 10;
5286         } else {
5287                 bpc = (uint8_t)connector->display_info.bpc;
5288                 /* Assume 8 bpc by default if no bpc is specified. */
5289                 bpc = bpc ? bpc : 8;
5290         }
5291
5292         if (requested_bpc > 0) {
5293                 /*
5294                  * Cap display bpc based on the user requested value.
5295                  *
5296                  * The value for state->max_bpc may not correctly updated
5297                  * depending on when the connector gets added to the state
5298                  * or if this was called outside of atomic check, so it
5299                  * can't be used directly.
5300                  */
5301                 bpc = min_t(u8, bpc, requested_bpc);
5302
5303                 /* Round down to the nearest even number. */
5304                 bpc = bpc - (bpc & 1);
5305         }
5306
5307         switch (bpc) {
5308         case 0:
5309                 /*
5310                  * Temporary Work around, DRM doesn't parse color depth for
5311                  * EDID revision before 1.4
5312                  * TODO: Fix edid parsing
5313                  */
5314                 return COLOR_DEPTH_888;
5315         case 6:
5316                 return COLOR_DEPTH_666;
5317         case 8:
5318                 return COLOR_DEPTH_888;
5319         case 10:
5320                 return COLOR_DEPTH_101010;
5321         case 12:
5322                 return COLOR_DEPTH_121212;
5323         case 14:
5324                 return COLOR_DEPTH_141414;
5325         case 16:
5326                 return COLOR_DEPTH_161616;
5327         default:
5328                 return COLOR_DEPTH_UNDEFINED;
5329         }
5330 }
5331
5332 static enum dc_aspect_ratio
5333 get_aspect_ratio(const struct drm_display_mode *mode_in)
5334 {
5335         /* 1-1 mapping, since both enums follow the HDMI spec. */
5336         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5337 }
5338
5339 static enum dc_color_space
5340 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
5341                        const struct drm_connector_state *connector_state)
5342 {
5343         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5344
5345         switch (connector_state->colorspace) {
5346         case DRM_MODE_COLORIMETRY_BT601_YCC:
5347                 if (dc_crtc_timing->flags.Y_ONLY)
5348                         color_space = COLOR_SPACE_YCBCR601_LIMITED;
5349                 else
5350                         color_space = COLOR_SPACE_YCBCR601;
5351                 break;
5352         case DRM_MODE_COLORIMETRY_BT709_YCC:
5353                 if (dc_crtc_timing->flags.Y_ONLY)
5354                         color_space = COLOR_SPACE_YCBCR709_LIMITED;
5355                 else
5356                         color_space = COLOR_SPACE_YCBCR709;
5357                 break;
5358         case DRM_MODE_COLORIMETRY_OPRGB:
5359                 color_space = COLOR_SPACE_ADOBERGB;
5360                 break;
5361         case DRM_MODE_COLORIMETRY_BT2020_RGB:
5362         case DRM_MODE_COLORIMETRY_BT2020_YCC:
5363                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
5364                         color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
5365                 else
5366                         color_space = COLOR_SPACE_2020_YCBCR;
5367                 break;
5368         case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
5369         default:
5370                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
5371                         color_space = COLOR_SPACE_SRGB;
5372                 /*
5373                  * 27030khz is the separation point between HDTV and SDTV
5374                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5375                  * respectively
5376                  */
5377                 } else if (dc_crtc_timing->pix_clk_100hz > 270300) {
5378                         if (dc_crtc_timing->flags.Y_ONLY)
5379                                 color_space =
5380                                         COLOR_SPACE_YCBCR709_LIMITED;
5381                         else
5382                                 color_space = COLOR_SPACE_YCBCR709;
5383                 } else {
5384                         if (dc_crtc_timing->flags.Y_ONLY)
5385                                 color_space =
5386                                         COLOR_SPACE_YCBCR601_LIMITED;
5387                         else
5388                                 color_space = COLOR_SPACE_YCBCR601;
5389                 }
5390                 break;
5391         }
5392
5393         return color_space;
5394 }
5395
5396 static bool adjust_colour_depth_from_display_info(
5397         struct dc_crtc_timing *timing_out,
5398         const struct drm_display_info *info)
5399 {
5400         enum dc_color_depth depth = timing_out->display_color_depth;
5401         int normalized_clk;
5402         do {
5403                 normalized_clk = timing_out->pix_clk_100hz / 10;
5404                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5405                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5406                         normalized_clk /= 2;
5407                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5408                 switch (depth) {
5409                 case COLOR_DEPTH_888:
5410                         break;
5411                 case COLOR_DEPTH_101010:
5412                         normalized_clk = (normalized_clk * 30) / 24;
5413                         break;
5414                 case COLOR_DEPTH_121212:
5415                         normalized_clk = (normalized_clk * 36) / 24;
5416                         break;
5417                 case COLOR_DEPTH_161616:
5418                         normalized_clk = (normalized_clk * 48) / 24;
5419                         break;
5420                 default:
5421                         /* The above depths are the only ones valid for HDMI. */
5422                         return false;
5423                 }
5424                 if (normalized_clk <= info->max_tmds_clock) {
5425                         timing_out->display_color_depth = depth;
5426                         return true;
5427                 }
5428         } while (--depth > COLOR_DEPTH_666);
5429         return false;
5430 }
5431
5432 static void fill_stream_properties_from_drm_display_mode(
5433         struct dc_stream_state *stream,
5434         const struct drm_display_mode *mode_in,
5435         const struct drm_connector *connector,
5436         const struct drm_connector_state *connector_state,
5437         const struct dc_stream_state *old_stream,
5438         int requested_bpc)
5439 {
5440         struct dc_crtc_timing *timing_out = &stream->timing;
5441         const struct drm_display_info *info = &connector->display_info;
5442         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5443         struct hdmi_vendor_infoframe hv_frame;
5444         struct hdmi_avi_infoframe avi_frame;
5445
5446         memset(&hv_frame, 0, sizeof(hv_frame));
5447         memset(&avi_frame, 0, sizeof(avi_frame));
5448
5449         timing_out->h_border_left = 0;
5450         timing_out->h_border_right = 0;
5451         timing_out->v_border_top = 0;
5452         timing_out->v_border_bottom = 0;
5453         /* TODO: un-hardcode */
5454         if (drm_mode_is_420_only(info, mode_in)
5455                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5456                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5457         else if (drm_mode_is_420_also(info, mode_in)
5458                         && aconnector->force_yuv420_output)
5459                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5460         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5461                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5462                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5463         else
5464                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5465
5466         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5467         timing_out->display_color_depth = convert_color_depth_from_display_info(
5468                 connector,
5469                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5470                 requested_bpc);
5471         timing_out->scan_type = SCANNING_TYPE_NODATA;
5472         timing_out->hdmi_vic = 0;
5473
5474         if (old_stream) {
5475                 timing_out->vic = old_stream->timing.vic;
5476                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5477                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5478         } else {
5479                 timing_out->vic = drm_match_cea_mode(mode_in);
5480                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5481                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5482                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5483                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5484         }
5485
5486         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5487                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5488                 timing_out->vic = avi_frame.video_code;
5489                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5490                 timing_out->hdmi_vic = hv_frame.vic;
5491         }
5492
5493         if (is_freesync_video_mode(mode_in, aconnector)) {
5494                 timing_out->h_addressable = mode_in->hdisplay;
5495                 timing_out->h_total = mode_in->htotal;
5496                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5497                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5498                 timing_out->v_total = mode_in->vtotal;
5499                 timing_out->v_addressable = mode_in->vdisplay;
5500                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5501                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5502                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5503         } else {
5504                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5505                 timing_out->h_total = mode_in->crtc_htotal;
5506                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5507                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5508                 timing_out->v_total = mode_in->crtc_vtotal;
5509                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5510                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5511                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5512                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5513         }
5514
5515         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5516
5517         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5518         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5519         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5520                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5521                     drm_mode_is_420_also(info, mode_in) &&
5522                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5523                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5524                         adjust_colour_depth_from_display_info(timing_out, info);
5525                 }
5526         }
5527
5528         stream->output_color_space = get_output_color_space(timing_out, connector_state);
5529 }
5530
5531 static void fill_audio_info(struct audio_info *audio_info,
5532                             const struct drm_connector *drm_connector,
5533                             const struct dc_sink *dc_sink)
5534 {
5535         int i = 0;
5536         int cea_revision = 0;
5537         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5538
5539         audio_info->manufacture_id = edid_caps->manufacturer_id;
5540         audio_info->product_id = edid_caps->product_id;
5541
5542         cea_revision = drm_connector->display_info.cea_rev;
5543
5544         strscpy(audio_info->display_name,
5545                 edid_caps->display_name,
5546                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5547
5548         if (cea_revision >= 3) {
5549                 audio_info->mode_count = edid_caps->audio_mode_count;
5550
5551                 for (i = 0; i < audio_info->mode_count; ++i) {
5552                         audio_info->modes[i].format_code =
5553                                         (enum audio_format_code)
5554                                         (edid_caps->audio_modes[i].format_code);
5555                         audio_info->modes[i].channel_count =
5556                                         edid_caps->audio_modes[i].channel_count;
5557                         audio_info->modes[i].sample_rates.all =
5558                                         edid_caps->audio_modes[i].sample_rate;
5559                         audio_info->modes[i].sample_size =
5560                                         edid_caps->audio_modes[i].sample_size;
5561                 }
5562         }
5563
5564         audio_info->flags.all = edid_caps->speaker_flags;
5565
5566         /* TODO: We only check for the progressive mode, check for interlace mode too */
5567         if (drm_connector->latency_present[0]) {
5568                 audio_info->video_latency = drm_connector->video_latency[0];
5569                 audio_info->audio_latency = drm_connector->audio_latency[0];
5570         }
5571
5572         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5573
5574 }
5575
5576 static void
5577 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5578                                       struct drm_display_mode *dst_mode)
5579 {
5580         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5581         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5582         dst_mode->crtc_clock = src_mode->crtc_clock;
5583         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5584         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5585         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5586         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5587         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5588         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5589         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5590         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5591         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5592         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5593         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5594 }
5595
5596 static void
5597 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5598                                         const struct drm_display_mode *native_mode,
5599                                         bool scale_enabled)
5600 {
5601         if (scale_enabled) {
5602                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5603         } else if (native_mode->clock == drm_mode->clock &&
5604                         native_mode->htotal == drm_mode->htotal &&
5605                         native_mode->vtotal == drm_mode->vtotal) {
5606                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5607         } else {
5608                 /* no scaling nor amdgpu inserted, no need to patch */
5609         }
5610 }
5611
5612 static struct dc_sink *
5613 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5614 {
5615         struct dc_sink_init_data sink_init_data = { 0 };
5616         struct dc_sink *sink = NULL;
5617         sink_init_data.link = aconnector->dc_link;
5618         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5619
5620         sink = dc_sink_create(&sink_init_data);
5621         if (!sink) {
5622                 DRM_ERROR("Failed to create sink!\n");
5623                 return NULL;
5624         }
5625         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5626
5627         return sink;
5628 }
5629
5630 static void set_multisync_trigger_params(
5631                 struct dc_stream_state *stream)
5632 {
5633         struct dc_stream_state *master = NULL;
5634
5635         if (stream->triggered_crtc_reset.enabled) {
5636                 master = stream->triggered_crtc_reset.event_source;
5637                 stream->triggered_crtc_reset.event =
5638                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5639                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5640                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5641         }
5642 }
5643
5644 static void set_master_stream(struct dc_stream_state *stream_set[],
5645                               int stream_count)
5646 {
5647         int j, highest_rfr = 0, master_stream = 0;
5648
5649         for (j = 0;  j < stream_count; j++) {
5650                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5651                         int refresh_rate = 0;
5652
5653                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5654                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5655                         if (refresh_rate > highest_rfr) {
5656                                 highest_rfr = refresh_rate;
5657                                 master_stream = j;
5658                         }
5659                 }
5660         }
5661         for (j = 0;  j < stream_count; j++) {
5662                 if (stream_set[j])
5663                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5664         }
5665 }
5666
5667 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5668 {
5669         int i = 0;
5670         struct dc_stream_state *stream;
5671
5672         if (context->stream_count < 2)
5673                 return;
5674         for (i = 0; i < context->stream_count ; i++) {
5675                 if (!context->streams[i])
5676                         continue;
5677                 /*
5678                  * TODO: add a function to read AMD VSDB bits and set
5679                  * crtc_sync_master.multi_sync_enabled flag
5680                  * For now it's set to false
5681                  */
5682         }
5683
5684         set_master_stream(context->streams, context->stream_count);
5685
5686         for (i = 0; i < context->stream_count ; i++) {
5687                 stream = context->streams[i];
5688
5689                 if (!stream)
5690                         continue;
5691
5692                 set_multisync_trigger_params(stream);
5693         }
5694 }
5695
5696 /**
5697  * DOC: FreeSync Video
5698  *
5699  * When a userspace application wants to play a video, the content follows a
5700  * standard format definition that usually specifies the FPS for that format.
5701  * The below list illustrates some video format and the expected FPS,
5702  * respectively:
5703  *
5704  * - TV/NTSC (23.976 FPS)
5705  * - Cinema (24 FPS)
5706  * - TV/PAL (25 FPS)
5707  * - TV/NTSC (29.97 FPS)
5708  * - TV/NTSC (30 FPS)
5709  * - Cinema HFR (48 FPS)
5710  * - TV/PAL (50 FPS)
5711  * - Commonly used (60 FPS)
5712  * - Multiples of 24 (48,72,96 FPS)
5713  *
5714  * The list of standards video format is not huge and can be added to the
5715  * connector modeset list beforehand. With that, userspace can leverage
5716  * FreeSync to extends the front porch in order to attain the target refresh
5717  * rate. Such a switch will happen seamlessly, without screen blanking or
5718  * reprogramming of the output in any other way. If the userspace requests a
5719  * modesetting change compatible with FreeSync modes that only differ in the
5720  * refresh rate, DC will skip the full update and avoid blink during the
5721  * transition. For example, the video player can change the modesetting from
5722  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5723  * causing any display blink. This same concept can be applied to a mode
5724  * setting change.
5725  */
5726 static struct drm_display_mode *
5727 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5728                 bool use_probed_modes)
5729 {
5730         struct drm_display_mode *m, *m_pref = NULL;
5731         u16 current_refresh, highest_refresh;
5732         struct list_head *list_head = use_probed_modes ?
5733                 &aconnector->base.probed_modes :
5734                 &aconnector->base.modes;
5735
5736         if (aconnector->freesync_vid_base.clock != 0)
5737                 return &aconnector->freesync_vid_base;
5738
5739         /* Find the preferred mode */
5740         list_for_each_entry (m, list_head, head) {
5741                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5742                         m_pref = m;
5743                         break;
5744                 }
5745         }
5746
5747         if (!m_pref) {
5748                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5749                 m_pref = list_first_entry_or_null(
5750                                 &aconnector->base.modes, struct drm_display_mode, head);
5751                 if (!m_pref) {
5752                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5753                         return NULL;
5754                 }
5755         }
5756
5757         highest_refresh = drm_mode_vrefresh(m_pref);
5758
5759         /*
5760          * Find the mode with highest refresh rate with same resolution.
5761          * For some monitors, preferred mode is not the mode with highest
5762          * supported refresh rate.
5763          */
5764         list_for_each_entry (m, list_head, head) {
5765                 current_refresh  = drm_mode_vrefresh(m);
5766
5767                 if (m->hdisplay == m_pref->hdisplay &&
5768                     m->vdisplay == m_pref->vdisplay &&
5769                     highest_refresh < current_refresh) {
5770                         highest_refresh = current_refresh;
5771                         m_pref = m;
5772                 }
5773         }
5774
5775         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5776         return m_pref;
5777 }
5778
5779 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5780                 struct amdgpu_dm_connector *aconnector)
5781 {
5782         struct drm_display_mode *high_mode;
5783         int timing_diff;
5784
5785         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5786         if (!high_mode || !mode)
5787                 return false;
5788
5789         timing_diff = high_mode->vtotal - mode->vtotal;
5790
5791         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5792             high_mode->hdisplay != mode->hdisplay ||
5793             high_mode->vdisplay != mode->vdisplay ||
5794             high_mode->hsync_start != mode->hsync_start ||
5795             high_mode->hsync_end != mode->hsync_end ||
5796             high_mode->htotal != mode->htotal ||
5797             high_mode->hskew != mode->hskew ||
5798             high_mode->vscan != mode->vscan ||
5799             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5800             high_mode->vsync_end - mode->vsync_end != timing_diff)
5801                 return false;
5802         else
5803                 return true;
5804 }
5805
5806 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5807                             struct dc_sink *sink, struct dc_stream_state *stream,
5808                             struct dsc_dec_dpcd_caps *dsc_caps)
5809 {
5810         stream->timing.flags.DSC = 0;
5811         dsc_caps->is_dsc_supported = false;
5812
5813         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5814             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5815                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5816                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5817                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5818                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5819                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5820                                 dsc_caps);
5821         }
5822 }
5823
5824
5825 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5826                                     struct dc_sink *sink, struct dc_stream_state *stream,
5827                                     struct dsc_dec_dpcd_caps *dsc_caps,
5828                                     uint32_t max_dsc_target_bpp_limit_override)
5829 {
5830         const struct dc_link_settings *verified_link_cap = NULL;
5831         u32 link_bw_in_kbps;
5832         u32 edp_min_bpp_x16, edp_max_bpp_x16;
5833         struct dc *dc = sink->ctx->dc;
5834         struct dc_dsc_bw_range bw_range = {0};
5835         struct dc_dsc_config dsc_cfg = {0};
5836         struct dc_dsc_config_options dsc_options = {0};
5837
5838         dc_dsc_get_default_config_option(dc, &dsc_options);
5839         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5840
5841         verified_link_cap = dc_link_get_link_cap(stream->link);
5842         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5843         edp_min_bpp_x16 = 8 * 16;
5844         edp_max_bpp_x16 = 8 * 16;
5845
5846         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5847                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5848
5849         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5850                 edp_min_bpp_x16 = edp_max_bpp_x16;
5851
5852         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5853                                 dc->debug.dsc_min_slice_height_override,
5854                                 edp_min_bpp_x16, edp_max_bpp_x16,
5855                                 dsc_caps,
5856                                 &stream->timing,
5857                                 &bw_range)) {
5858
5859                 if (bw_range.max_kbps < link_bw_in_kbps) {
5860                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5861                                         dsc_caps,
5862                                         &dsc_options,
5863                                         0,
5864                                         &stream->timing,
5865                                         &dsc_cfg)) {
5866                                 stream->timing.dsc_cfg = dsc_cfg;
5867                                 stream->timing.flags.DSC = 1;
5868                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5869                         }
5870                         return;
5871                 }
5872         }
5873
5874         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5875                                 dsc_caps,
5876                                 &dsc_options,
5877                                 link_bw_in_kbps,
5878                                 &stream->timing,
5879                                 &dsc_cfg)) {
5880                 stream->timing.dsc_cfg = dsc_cfg;
5881                 stream->timing.flags.DSC = 1;
5882         }
5883 }
5884
5885
5886 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5887                                         struct dc_sink *sink, struct dc_stream_state *stream,
5888                                         struct dsc_dec_dpcd_caps *dsc_caps)
5889 {
5890         struct drm_connector *drm_connector = &aconnector->base;
5891         u32 link_bandwidth_kbps;
5892         struct dc *dc = sink->ctx->dc;
5893         u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5894         u32 dsc_max_supported_bw_in_kbps;
5895         u32 max_dsc_target_bpp_limit_override =
5896                 drm_connector->display_info.max_dsc_bpp;
5897         struct dc_dsc_config_options dsc_options = {0};
5898
5899         dc_dsc_get_default_config_option(dc, &dsc_options);
5900         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5901
5902         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5903                                                         dc_link_get_link_cap(aconnector->dc_link));
5904
5905         /* Set DSC policy according to dsc_clock_en */
5906         dc_dsc_policy_set_enable_dsc_when_not_needed(
5907                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5908
5909         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5910             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5911             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5912
5913                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5914
5915         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5916                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5917                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5918                                                 dsc_caps,
5919                                                 &dsc_options,
5920                                                 link_bandwidth_kbps,
5921                                                 &stream->timing,
5922                                                 &stream->timing.dsc_cfg)) {
5923                                 stream->timing.flags.DSC = 1;
5924                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5925                         }
5926                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5927                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5928                         max_supported_bw_in_kbps = link_bandwidth_kbps;
5929                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5930
5931                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5932                                         max_supported_bw_in_kbps > 0 &&
5933                                         dsc_max_supported_bw_in_kbps > 0)
5934                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5935                                                 dsc_caps,
5936                                                 &dsc_options,
5937                                                 dsc_max_supported_bw_in_kbps,
5938                                                 &stream->timing,
5939                                                 &stream->timing.dsc_cfg)) {
5940                                         stream->timing.flags.DSC = 1;
5941                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5942                                                                          __func__, drm_connector->name);
5943                                 }
5944                 }
5945         }
5946
5947         /* Overwrite the stream flag if DSC is enabled through debugfs */
5948         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5949                 stream->timing.flags.DSC = 1;
5950
5951         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5952                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5953
5954         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5955                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5956
5957         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5958                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5959 }
5960
5961 static struct dc_stream_state *
5962 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5963                        const struct drm_display_mode *drm_mode,
5964                        const struct dm_connector_state *dm_state,
5965                        const struct dc_stream_state *old_stream,
5966                        int requested_bpc)
5967 {
5968         struct drm_display_mode *preferred_mode = NULL;
5969         struct drm_connector *drm_connector;
5970         const struct drm_connector_state *con_state = &dm_state->base;
5971         struct dc_stream_state *stream = NULL;
5972         struct drm_display_mode mode;
5973         struct drm_display_mode saved_mode;
5974         struct drm_display_mode *freesync_mode = NULL;
5975         bool native_mode_found = false;
5976         bool recalculate_timing = false;
5977         bool scale = dm_state->scaling != RMX_OFF;
5978         int mode_refresh;
5979         int preferred_refresh = 0;
5980         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
5981         struct dsc_dec_dpcd_caps dsc_caps;
5982
5983         struct dc_sink *sink = NULL;
5984
5985         drm_mode_init(&mode, drm_mode);
5986         memset(&saved_mode, 0, sizeof(saved_mode));
5987
5988         if (aconnector == NULL) {
5989                 DRM_ERROR("aconnector is NULL!\n");
5990                 return stream;
5991         }
5992
5993         drm_connector = &aconnector->base;
5994
5995         if (!aconnector->dc_sink) {
5996                 sink = create_fake_sink(aconnector);
5997                 if (!sink)
5998                         return stream;
5999         } else {
6000                 sink = aconnector->dc_sink;
6001                 dc_sink_retain(sink);
6002         }
6003
6004         stream = dc_create_stream_for_sink(sink);
6005
6006         if (stream == NULL) {
6007                 DRM_ERROR("Failed to create stream for sink!\n");
6008                 goto finish;
6009         }
6010
6011         stream->dm_stream_context = aconnector;
6012
6013         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6014                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
6015
6016         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
6017                 /* Search for preferred mode */
6018                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6019                         native_mode_found = true;
6020                         break;
6021                 }
6022         }
6023         if (!native_mode_found)
6024                 preferred_mode = list_first_entry_or_null(
6025                                 &aconnector->base.modes,
6026                                 struct drm_display_mode,
6027                                 head);
6028
6029         mode_refresh = drm_mode_vrefresh(&mode);
6030
6031         if (preferred_mode == NULL) {
6032                 /*
6033                  * This may not be an error, the use case is when we have no
6034                  * usermode calls to reset and set mode upon hotplug. In this
6035                  * case, we call set mode ourselves to restore the previous mode
6036                  * and the modelist may not be filled in in time.
6037                  */
6038                 DRM_DEBUG_DRIVER("No preferred mode found\n");
6039         } else {
6040                 recalculate_timing = is_freesync_video_mode(&mode, aconnector);
6041                 if (recalculate_timing) {
6042                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6043                         drm_mode_copy(&saved_mode, &mode);
6044                         drm_mode_copy(&mode, freesync_mode);
6045                 } else {
6046                         decide_crtc_timing_for_drm_display_mode(
6047                                         &mode, preferred_mode, scale);
6048
6049                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
6050                 }
6051         }
6052
6053         if (recalculate_timing)
6054                 drm_mode_set_crtcinfo(&saved_mode, 0);
6055         else
6056                 drm_mode_set_crtcinfo(&mode, 0);
6057
6058         /*
6059         * If scaling is enabled and refresh rate didn't change
6060         * we copy the vic and polarities of the old timings
6061         */
6062         if (!scale || mode_refresh != preferred_refresh)
6063                 fill_stream_properties_from_drm_display_mode(
6064                         stream, &mode, &aconnector->base, con_state, NULL,
6065                         requested_bpc);
6066         else
6067                 fill_stream_properties_from_drm_display_mode(
6068                         stream, &mode, &aconnector->base, con_state, old_stream,
6069                         requested_bpc);
6070
6071         if (aconnector->timing_changed) {
6072                 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",
6073                                 __func__,
6074                                 stream->timing.display_color_depth,
6075                                 aconnector->timing_requested->display_color_depth);
6076                 stream->timing = *aconnector->timing_requested;
6077         }
6078
6079         /* SST DSC determination policy */
6080         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6081         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6082                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6083
6084         update_stream_scaling_settings(&mode, dm_state, stream);
6085
6086         fill_audio_info(
6087                 &stream->audio_info,
6088                 drm_connector,
6089                 sink);
6090
6091         update_stream_signal(stream, sink);
6092
6093         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6094                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6095
6096         if (stream->link->psr_settings.psr_feature_enabled) {
6097                 //
6098                 // should decide stream support vsc sdp colorimetry capability
6099                 // before building vsc info packet
6100                 //
6101                 stream->use_vsc_sdp_for_colorimetry = false;
6102                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6103                         stream->use_vsc_sdp_for_colorimetry =
6104                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6105                 } else {
6106                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6107                                 stream->use_vsc_sdp_for_colorimetry = true;
6108                 }
6109                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6110                         tf = TRANSFER_FUNC_GAMMA_22;
6111                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6112                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6113
6114         }
6115 finish:
6116         dc_sink_release(sink);
6117
6118         return stream;
6119 }
6120
6121 static enum drm_connector_status
6122 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6123 {
6124         bool connected;
6125         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6126
6127         /*
6128          * Notes:
6129          * 1. This interface is NOT called in context of HPD irq.
6130          * 2. This interface *is called* in context of user-mode ioctl. Which
6131          * makes it a bad place for *any* MST-related activity.
6132          */
6133
6134         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6135             !aconnector->fake_enable)
6136                 connected = (aconnector->dc_sink != NULL);
6137         else
6138                 connected = (aconnector->base.force == DRM_FORCE_ON ||
6139                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6140
6141         update_subconnector_property(aconnector);
6142
6143         return (connected ? connector_status_connected :
6144                         connector_status_disconnected);
6145 }
6146
6147 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6148                                             struct drm_connector_state *connector_state,
6149                                             struct drm_property *property,
6150                                             uint64_t val)
6151 {
6152         struct drm_device *dev = connector->dev;
6153         struct amdgpu_device *adev = drm_to_adev(dev);
6154         struct dm_connector_state *dm_old_state =
6155                 to_dm_connector_state(connector->state);
6156         struct dm_connector_state *dm_new_state =
6157                 to_dm_connector_state(connector_state);
6158
6159         int ret = -EINVAL;
6160
6161         if (property == dev->mode_config.scaling_mode_property) {
6162                 enum amdgpu_rmx_type rmx_type;
6163
6164                 switch (val) {
6165                 case DRM_MODE_SCALE_CENTER:
6166                         rmx_type = RMX_CENTER;
6167                         break;
6168                 case DRM_MODE_SCALE_ASPECT:
6169                         rmx_type = RMX_ASPECT;
6170                         break;
6171                 case DRM_MODE_SCALE_FULLSCREEN:
6172                         rmx_type = RMX_FULL;
6173                         break;
6174                 case DRM_MODE_SCALE_NONE:
6175                 default:
6176                         rmx_type = RMX_OFF;
6177                         break;
6178                 }
6179
6180                 if (dm_old_state->scaling == rmx_type)
6181                         return 0;
6182
6183                 dm_new_state->scaling = rmx_type;
6184                 ret = 0;
6185         } else if (property == adev->mode_info.underscan_hborder_property) {
6186                 dm_new_state->underscan_hborder = val;
6187                 ret = 0;
6188         } else if (property == adev->mode_info.underscan_vborder_property) {
6189                 dm_new_state->underscan_vborder = val;
6190                 ret = 0;
6191         } else if (property == adev->mode_info.underscan_property) {
6192                 dm_new_state->underscan_enable = val;
6193                 ret = 0;
6194         } else if (property == adev->mode_info.abm_level_property) {
6195                 dm_new_state->abm_level = val;
6196                 ret = 0;
6197         }
6198
6199         return ret;
6200 }
6201
6202 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6203                                             const struct drm_connector_state *state,
6204                                             struct drm_property *property,
6205                                             uint64_t *val)
6206 {
6207         struct drm_device *dev = connector->dev;
6208         struct amdgpu_device *adev = drm_to_adev(dev);
6209         struct dm_connector_state *dm_state =
6210                 to_dm_connector_state(state);
6211         int ret = -EINVAL;
6212
6213         if (property == dev->mode_config.scaling_mode_property) {
6214                 switch (dm_state->scaling) {
6215                 case RMX_CENTER:
6216                         *val = DRM_MODE_SCALE_CENTER;
6217                         break;
6218                 case RMX_ASPECT:
6219                         *val = DRM_MODE_SCALE_ASPECT;
6220                         break;
6221                 case RMX_FULL:
6222                         *val = DRM_MODE_SCALE_FULLSCREEN;
6223                         break;
6224                 case RMX_OFF:
6225                 default:
6226                         *val = DRM_MODE_SCALE_NONE;
6227                         break;
6228                 }
6229                 ret = 0;
6230         } else if (property == adev->mode_info.underscan_hborder_property) {
6231                 *val = dm_state->underscan_hborder;
6232                 ret = 0;
6233         } else if (property == adev->mode_info.underscan_vborder_property) {
6234                 *val = dm_state->underscan_vborder;
6235                 ret = 0;
6236         } else if (property == adev->mode_info.underscan_property) {
6237                 *val = dm_state->underscan_enable;
6238                 ret = 0;
6239         } else if (property == adev->mode_info.abm_level_property) {
6240                 *val = dm_state->abm_level;
6241                 ret = 0;
6242         }
6243
6244         return ret;
6245 }
6246
6247 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6248 {
6249         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6250
6251         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6252 }
6253
6254 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6255 {
6256         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6257         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6258         struct amdgpu_display_manager *dm = &adev->dm;
6259
6260         /*
6261          * Call only if mst_mgr was initialized before since it's not done
6262          * for all connector types.
6263          */
6264         if (aconnector->mst_mgr.dev)
6265                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6266
6267         if (aconnector->bl_idx != -1) {
6268                 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6269                 dm->backlight_dev[aconnector->bl_idx] = NULL;
6270         }
6271
6272         if (aconnector->dc_em_sink)
6273                 dc_sink_release(aconnector->dc_em_sink);
6274         aconnector->dc_em_sink = NULL;
6275         if (aconnector->dc_sink)
6276                 dc_sink_release(aconnector->dc_sink);
6277         aconnector->dc_sink = NULL;
6278
6279         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6280         drm_connector_unregister(connector);
6281         drm_connector_cleanup(connector);
6282         if (aconnector->i2c) {
6283                 i2c_del_adapter(&aconnector->i2c->base);
6284                 kfree(aconnector->i2c);
6285         }
6286         kfree(aconnector->dm_dp_aux.aux.name);
6287
6288         kfree(connector);
6289 }
6290
6291 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6292 {
6293         struct dm_connector_state *state =
6294                 to_dm_connector_state(connector->state);
6295
6296         if (connector->state)
6297                 __drm_atomic_helper_connector_destroy_state(connector->state);
6298
6299         kfree(state);
6300
6301         state = kzalloc(sizeof(*state), GFP_KERNEL);
6302
6303         if (state) {
6304                 state->scaling = RMX_OFF;
6305                 state->underscan_enable = false;
6306                 state->underscan_hborder = 0;
6307                 state->underscan_vborder = 0;
6308                 state->base.max_requested_bpc = 8;
6309                 state->vcpi_slots = 0;
6310                 state->pbn = 0;
6311
6312                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6313                         state->abm_level = amdgpu_dm_abm_level;
6314
6315                 __drm_atomic_helper_connector_reset(connector, &state->base);
6316         }
6317 }
6318
6319 struct drm_connector_state *
6320 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6321 {
6322         struct dm_connector_state *state =
6323                 to_dm_connector_state(connector->state);
6324
6325         struct dm_connector_state *new_state =
6326                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6327
6328         if (!new_state)
6329                 return NULL;
6330
6331         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6332
6333         new_state->freesync_capable = state->freesync_capable;
6334         new_state->abm_level = state->abm_level;
6335         new_state->scaling = state->scaling;
6336         new_state->underscan_enable = state->underscan_enable;
6337         new_state->underscan_hborder = state->underscan_hborder;
6338         new_state->underscan_vborder = state->underscan_vborder;
6339         new_state->vcpi_slots = state->vcpi_slots;
6340         new_state->pbn = state->pbn;
6341         return &new_state->base;
6342 }
6343
6344 static int
6345 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6346 {
6347         struct amdgpu_dm_connector *amdgpu_dm_connector =
6348                 to_amdgpu_dm_connector(connector);
6349         int r;
6350
6351         amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6352
6353         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6354             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6355                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6356                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6357                 if (r)
6358                         return r;
6359         }
6360
6361 #if defined(CONFIG_DEBUG_FS)
6362         connector_debugfs_init(amdgpu_dm_connector);
6363 #endif
6364
6365         return 0;
6366 }
6367
6368 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
6369 {
6370         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6371         struct dc_link *dc_link = aconnector->dc_link;
6372         struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
6373         struct edid *edid;
6374
6375         if (!connector->edid_override)
6376                 return;
6377
6378         drm_edid_override_connector_update(&aconnector->base);
6379         edid = aconnector->base.edid_blob_ptr->data;
6380         aconnector->edid = edid;
6381
6382         /* Update emulated (virtual) sink's EDID */
6383         if (dc_em_sink && dc_link) {
6384                 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
6385                 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH);
6386                 dm_helpers_parse_edid_caps(
6387                         dc_link,
6388                         &dc_em_sink->dc_edid,
6389                         &dc_em_sink->edid_caps);
6390         }
6391 }
6392
6393 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6394         .reset = amdgpu_dm_connector_funcs_reset,
6395         .detect = amdgpu_dm_connector_detect,
6396         .fill_modes = drm_helper_probe_single_connector_modes,
6397         .destroy = amdgpu_dm_connector_destroy,
6398         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6399         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6400         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6401         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6402         .late_register = amdgpu_dm_connector_late_register,
6403         .early_unregister = amdgpu_dm_connector_unregister,
6404         .force = amdgpu_dm_connector_funcs_force
6405 };
6406
6407 static int get_modes(struct drm_connector *connector)
6408 {
6409         return amdgpu_dm_connector_get_modes(connector);
6410 }
6411
6412 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6413 {
6414         struct dc_sink_init_data init_params = {
6415                         .link = aconnector->dc_link,
6416                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6417         };
6418         struct edid *edid;
6419
6420         if (!aconnector->base.edid_blob_ptr) {
6421                 /* if connector->edid_override valid, pass
6422                  * it to edid_override to edid_blob_ptr
6423                  */
6424
6425                 drm_edid_override_connector_update(&aconnector->base);
6426
6427                 if (!aconnector->base.edid_blob_ptr) {
6428                         DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6429                                         aconnector->base.name);
6430
6431                         aconnector->base.force = DRM_FORCE_OFF;
6432                         return;
6433                 }
6434         }
6435
6436         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6437
6438         aconnector->edid = edid;
6439
6440         aconnector->dc_em_sink = dc_link_add_remote_sink(
6441                 aconnector->dc_link,
6442                 (uint8_t *)edid,
6443                 (edid->extensions + 1) * EDID_LENGTH,
6444                 &init_params);
6445
6446         if (aconnector->base.force == DRM_FORCE_ON) {
6447                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6448                 aconnector->dc_link->local_sink :
6449                 aconnector->dc_em_sink;
6450                 dc_sink_retain(aconnector->dc_sink);
6451         }
6452 }
6453
6454 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6455 {
6456         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6457
6458         /*
6459          * In case of headless boot with force on for DP managed connector
6460          * Those settings have to be != 0 to get initial modeset
6461          */
6462         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6463                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6464                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6465         }
6466
6467         create_eml_sink(aconnector);
6468 }
6469
6470 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6471                                                 struct dc_stream_state *stream)
6472 {
6473         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6474         struct dc_plane_state *dc_plane_state = NULL;
6475         struct dc_state *dc_state = NULL;
6476
6477         if (!stream)
6478                 goto cleanup;
6479
6480         dc_plane_state = dc_create_plane_state(dc);
6481         if (!dc_plane_state)
6482                 goto cleanup;
6483
6484         dc_state = dc_create_state(dc);
6485         if (!dc_state)
6486                 goto cleanup;
6487
6488         /* populate stream to plane */
6489         dc_plane_state->src_rect.height  = stream->src.height;
6490         dc_plane_state->src_rect.width   = stream->src.width;
6491         dc_plane_state->dst_rect.height  = stream->src.height;
6492         dc_plane_state->dst_rect.width   = stream->src.width;
6493         dc_plane_state->clip_rect.height = stream->src.height;
6494         dc_plane_state->clip_rect.width  = stream->src.width;
6495         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6496         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6497         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6498         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6499         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6500         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6501         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6502         dc_plane_state->rotation = ROTATION_ANGLE_0;
6503         dc_plane_state->is_tiling_rotated = false;
6504         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6505
6506         dc_result = dc_validate_stream(dc, stream);
6507         if (dc_result == DC_OK)
6508                 dc_result = dc_validate_plane(dc, dc_plane_state);
6509
6510         if (dc_result == DC_OK)
6511                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6512
6513         if (dc_result == DC_OK && !dc_add_plane_to_context(
6514                                                 dc,
6515                                                 stream,
6516                                                 dc_plane_state,
6517                                                 dc_state))
6518                 dc_result = DC_FAIL_ATTACH_SURFACES;
6519
6520         if (dc_result == DC_OK)
6521                 dc_result = dc_validate_global_state(dc, dc_state, true);
6522
6523 cleanup:
6524         if (dc_state)
6525                 dc_release_state(dc_state);
6526
6527         if (dc_plane_state)
6528                 dc_plane_state_release(dc_plane_state);
6529
6530         return dc_result;
6531 }
6532
6533 struct dc_stream_state *
6534 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6535                                 const struct drm_display_mode *drm_mode,
6536                                 const struct dm_connector_state *dm_state,
6537                                 const struct dc_stream_state *old_stream)
6538 {
6539         struct drm_connector *connector = &aconnector->base;
6540         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6541         struct dc_stream_state *stream;
6542         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6543         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6544         enum dc_status dc_result = DC_OK;
6545
6546         do {
6547                 stream = create_stream_for_sink(aconnector, drm_mode,
6548                                                 dm_state, old_stream,
6549                                                 requested_bpc);
6550                 if (stream == NULL) {
6551                         DRM_ERROR("Failed to create stream for sink!\n");
6552                         break;
6553                 }
6554
6555                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6556                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6557                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6558
6559                 if (dc_result == DC_OK)
6560                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6561
6562                 if (dc_result != DC_OK) {
6563                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6564                                       drm_mode->hdisplay,
6565                                       drm_mode->vdisplay,
6566                                       drm_mode->clock,
6567                                       dc_result,
6568                                       dc_status_to_str(dc_result));
6569
6570                         dc_stream_release(stream);
6571                         stream = NULL;
6572                         requested_bpc -= 2; /* lower bpc to retry validation */
6573                 }
6574
6575         } while (stream == NULL && requested_bpc >= 6);
6576
6577         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6578                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6579
6580                 aconnector->force_yuv420_output = true;
6581                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6582                                                 dm_state, old_stream);
6583                 aconnector->force_yuv420_output = false;
6584         }
6585
6586         return stream;
6587 }
6588
6589 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6590                                    struct drm_display_mode *mode)
6591 {
6592         int result = MODE_ERROR;
6593         struct dc_sink *dc_sink;
6594         /* TODO: Unhardcode stream count */
6595         struct dc_stream_state *stream;
6596         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6597
6598         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6599                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6600                 return result;
6601
6602         /*
6603          * Only run this the first time mode_valid is called to initilialize
6604          * EDID mgmt
6605          */
6606         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6607                 !aconnector->dc_em_sink)
6608                 handle_edid_mgmt(aconnector);
6609
6610         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6611
6612         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6613                                 aconnector->base.force != DRM_FORCE_ON) {
6614                 DRM_ERROR("dc_sink is NULL!\n");
6615                 goto fail;
6616         }
6617
6618         stream = create_validate_stream_for_sink(aconnector, mode,
6619                                                  to_dm_connector_state(connector->state),
6620                                                  NULL);
6621         if (stream) {
6622                 dc_stream_release(stream);
6623                 result = MODE_OK;
6624         }
6625
6626 fail:
6627         /* TODO: error handling*/
6628         return result;
6629 }
6630
6631 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6632                                 struct dc_info_packet *out)
6633 {
6634         struct hdmi_drm_infoframe frame;
6635         unsigned char buf[30]; /* 26 + 4 */
6636         ssize_t len;
6637         int ret, i;
6638
6639         memset(out, 0, sizeof(*out));
6640
6641         if (!state->hdr_output_metadata)
6642                 return 0;
6643
6644         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6645         if (ret)
6646                 return ret;
6647
6648         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6649         if (len < 0)
6650                 return (int)len;
6651
6652         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6653         if (len != 30)
6654                 return -EINVAL;
6655
6656         /* Prepare the infopacket for DC. */
6657         switch (state->connector->connector_type) {
6658         case DRM_MODE_CONNECTOR_HDMIA:
6659                 out->hb0 = 0x87; /* type */
6660                 out->hb1 = 0x01; /* version */
6661                 out->hb2 = 0x1A; /* length */
6662                 out->sb[0] = buf[3]; /* checksum */
6663                 i = 1;
6664                 break;
6665
6666         case DRM_MODE_CONNECTOR_DisplayPort:
6667         case DRM_MODE_CONNECTOR_eDP:
6668                 out->hb0 = 0x00; /* sdp id, zero */
6669                 out->hb1 = 0x87; /* type */
6670                 out->hb2 = 0x1D; /* payload len - 1 */
6671                 out->hb3 = (0x13 << 2); /* sdp version */
6672                 out->sb[0] = 0x01; /* version */
6673                 out->sb[1] = 0x1A; /* length */
6674                 i = 2;
6675                 break;
6676
6677         default:
6678                 return -EINVAL;
6679         }
6680
6681         memcpy(&out->sb[i], &buf[4], 26);
6682         out->valid = true;
6683
6684         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6685                        sizeof(out->sb), false);
6686
6687         return 0;
6688 }
6689
6690 static int
6691 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6692                                  struct drm_atomic_state *state)
6693 {
6694         struct drm_connector_state *new_con_state =
6695                 drm_atomic_get_new_connector_state(state, conn);
6696         struct drm_connector_state *old_con_state =
6697                 drm_atomic_get_old_connector_state(state, conn);
6698         struct drm_crtc *crtc = new_con_state->crtc;
6699         struct drm_crtc_state *new_crtc_state;
6700         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6701         int ret;
6702
6703         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6704
6705         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6706                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6707                 if (ret < 0)
6708                         return ret;
6709         }
6710
6711         if (!crtc)
6712                 return 0;
6713
6714         if (new_con_state->colorspace != old_con_state->colorspace) {
6715                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6716                 if (IS_ERR(new_crtc_state))
6717                         return PTR_ERR(new_crtc_state);
6718
6719                 new_crtc_state->mode_changed = true;
6720         }
6721
6722         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6723                 struct dc_info_packet hdr_infopacket;
6724
6725                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6726                 if (ret)
6727                         return ret;
6728
6729                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6730                 if (IS_ERR(new_crtc_state))
6731                         return PTR_ERR(new_crtc_state);
6732
6733                 /*
6734                  * DC considers the stream backends changed if the
6735                  * static metadata changes. Forcing the modeset also
6736                  * gives a simple way for userspace to switch from
6737                  * 8bpc to 10bpc when setting the metadata to enter
6738                  * or exit HDR.
6739                  *
6740                  * Changing the static metadata after it's been
6741                  * set is permissible, however. So only force a
6742                  * modeset if we're entering or exiting HDR.
6743                  */
6744                 new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
6745                         !old_con_state->hdr_output_metadata ||
6746                         !new_con_state->hdr_output_metadata;
6747         }
6748
6749         return 0;
6750 }
6751
6752 static const struct drm_connector_helper_funcs
6753 amdgpu_dm_connector_helper_funcs = {
6754         /*
6755          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6756          * modes will be filtered by drm_mode_validate_size(), and those modes
6757          * are missing after user start lightdm. So we need to renew modes list.
6758          * in get_modes call back, not just return the modes count
6759          */
6760         .get_modes = get_modes,
6761         .mode_valid = amdgpu_dm_connector_mode_valid,
6762         .atomic_check = amdgpu_dm_connector_atomic_check,
6763 };
6764
6765 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6766 {
6767
6768 }
6769
6770 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6771 {
6772         switch (display_color_depth) {
6773         case COLOR_DEPTH_666:
6774                 return 6;
6775         case COLOR_DEPTH_888:
6776                 return 8;
6777         case COLOR_DEPTH_101010:
6778                 return 10;
6779         case COLOR_DEPTH_121212:
6780                 return 12;
6781         case COLOR_DEPTH_141414:
6782                 return 14;
6783         case COLOR_DEPTH_161616:
6784                 return 16;
6785         default:
6786                 break;
6787         }
6788         return 0;
6789 }
6790
6791 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6792                                           struct drm_crtc_state *crtc_state,
6793                                           struct drm_connector_state *conn_state)
6794 {
6795         struct drm_atomic_state *state = crtc_state->state;
6796         struct drm_connector *connector = conn_state->connector;
6797         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6798         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6799         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6800         struct drm_dp_mst_topology_mgr *mst_mgr;
6801         struct drm_dp_mst_port *mst_port;
6802         struct drm_dp_mst_topology_state *mst_state;
6803         enum dc_color_depth color_depth;
6804         int clock, bpp = 0;
6805         bool is_y420 = false;
6806
6807         if (!aconnector->mst_output_port)
6808                 return 0;
6809
6810         mst_port = aconnector->mst_output_port;
6811         mst_mgr = &aconnector->mst_root->mst_mgr;
6812
6813         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6814                 return 0;
6815
6816         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6817         if (IS_ERR(mst_state))
6818                 return PTR_ERR(mst_state);
6819
6820         if (!mst_state->pbn_div)
6821                 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6822
6823         if (!state->duplicated) {
6824                 int max_bpc = conn_state->max_requested_bpc;
6825                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6826                           aconnector->force_yuv420_output;
6827                 color_depth = convert_color_depth_from_display_info(connector,
6828                                                                     is_y420,
6829                                                                     max_bpc);
6830                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6831                 clock = adjusted_mode->clock;
6832                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6833         }
6834
6835         dm_new_connector_state->vcpi_slots =
6836                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6837                                               dm_new_connector_state->pbn);
6838         if (dm_new_connector_state->vcpi_slots < 0) {
6839                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6840                 return dm_new_connector_state->vcpi_slots;
6841         }
6842         return 0;
6843 }
6844
6845 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6846         .disable = dm_encoder_helper_disable,
6847         .atomic_check = dm_encoder_helper_atomic_check
6848 };
6849
6850 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6851                                             struct dc_state *dc_state,
6852                                             struct dsc_mst_fairness_vars *vars)
6853 {
6854         struct dc_stream_state *stream = NULL;
6855         struct drm_connector *connector;
6856         struct drm_connector_state *new_con_state;
6857         struct amdgpu_dm_connector *aconnector;
6858         struct dm_connector_state *dm_conn_state;
6859         int i, j, ret;
6860         int vcpi, pbn_div, pbn, slot_num = 0;
6861
6862         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6863
6864                 aconnector = to_amdgpu_dm_connector(connector);
6865
6866                 if (!aconnector->mst_output_port)
6867                         continue;
6868
6869                 if (!new_con_state || !new_con_state->crtc)
6870                         continue;
6871
6872                 dm_conn_state = to_dm_connector_state(new_con_state);
6873
6874                 for (j = 0; j < dc_state->stream_count; j++) {
6875                         stream = dc_state->streams[j];
6876                         if (!stream)
6877                                 continue;
6878
6879                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6880                                 break;
6881
6882                         stream = NULL;
6883                 }
6884
6885                 if (!stream)
6886                         continue;
6887
6888                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6889                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6890                 for (j = 0; j < dc_state->stream_count; j++) {
6891                         if (vars[j].aconnector == aconnector) {
6892                                 pbn = vars[j].pbn;
6893                                 break;
6894                         }
6895                 }
6896
6897                 if (j == dc_state->stream_count)
6898                         continue;
6899
6900                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6901
6902                 if (stream->timing.flags.DSC != 1) {
6903                         dm_conn_state->pbn = pbn;
6904                         dm_conn_state->vcpi_slots = slot_num;
6905
6906                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6907                                                            dm_conn_state->pbn, false);
6908                         if (ret < 0)
6909                                 return ret;
6910
6911                         continue;
6912                 }
6913
6914                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
6915                 if (vcpi < 0)
6916                         return vcpi;
6917
6918                 dm_conn_state->pbn = pbn;
6919                 dm_conn_state->vcpi_slots = vcpi;
6920         }
6921         return 0;
6922 }
6923
6924 static int to_drm_connector_type(enum signal_type st)
6925 {
6926         switch (st) {
6927         case SIGNAL_TYPE_HDMI_TYPE_A:
6928                 return DRM_MODE_CONNECTOR_HDMIA;
6929         case SIGNAL_TYPE_EDP:
6930                 return DRM_MODE_CONNECTOR_eDP;
6931         case SIGNAL_TYPE_LVDS:
6932                 return DRM_MODE_CONNECTOR_LVDS;
6933         case SIGNAL_TYPE_RGB:
6934                 return DRM_MODE_CONNECTOR_VGA;
6935         case SIGNAL_TYPE_DISPLAY_PORT:
6936         case SIGNAL_TYPE_DISPLAY_PORT_MST:
6937                 return DRM_MODE_CONNECTOR_DisplayPort;
6938         case SIGNAL_TYPE_DVI_DUAL_LINK:
6939         case SIGNAL_TYPE_DVI_SINGLE_LINK:
6940                 return DRM_MODE_CONNECTOR_DVID;
6941         case SIGNAL_TYPE_VIRTUAL:
6942                 return DRM_MODE_CONNECTOR_VIRTUAL;
6943
6944         default:
6945                 return DRM_MODE_CONNECTOR_Unknown;
6946         }
6947 }
6948
6949 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6950 {
6951         struct drm_encoder *encoder;
6952
6953         /* There is only one encoder per connector */
6954         drm_connector_for_each_possible_encoder(connector, encoder)
6955                 return encoder;
6956
6957         return NULL;
6958 }
6959
6960 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6961 {
6962         struct drm_encoder *encoder;
6963         struct amdgpu_encoder *amdgpu_encoder;
6964
6965         encoder = amdgpu_dm_connector_to_encoder(connector);
6966
6967         if (encoder == NULL)
6968                 return;
6969
6970         amdgpu_encoder = to_amdgpu_encoder(encoder);
6971
6972         amdgpu_encoder->native_mode.clock = 0;
6973
6974         if (!list_empty(&connector->probed_modes)) {
6975                 struct drm_display_mode *preferred_mode = NULL;
6976
6977                 list_for_each_entry(preferred_mode,
6978                                     &connector->probed_modes,
6979                                     head) {
6980                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6981                                 amdgpu_encoder->native_mode = *preferred_mode;
6982
6983                         break;
6984                 }
6985
6986         }
6987 }
6988
6989 static struct drm_display_mode *
6990 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6991                              char *name,
6992                              int hdisplay, int vdisplay)
6993 {
6994         struct drm_device *dev = encoder->dev;
6995         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6996         struct drm_display_mode *mode = NULL;
6997         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6998
6999         mode = drm_mode_duplicate(dev, native_mode);
7000
7001         if (mode == NULL)
7002                 return NULL;
7003
7004         mode->hdisplay = hdisplay;
7005         mode->vdisplay = vdisplay;
7006         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7007         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
7008
7009         return mode;
7010
7011 }
7012
7013 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
7014                                                  struct drm_connector *connector)
7015 {
7016         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7017         struct drm_display_mode *mode = NULL;
7018         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7019         struct amdgpu_dm_connector *amdgpu_dm_connector =
7020                                 to_amdgpu_dm_connector(connector);
7021         int i;
7022         int n;
7023         struct mode_size {
7024                 char name[DRM_DISPLAY_MODE_LEN];
7025                 int w;
7026                 int h;
7027         } common_modes[] = {
7028                 {  "640x480",  640,  480},
7029                 {  "800x600",  800,  600},
7030                 { "1024x768", 1024,  768},
7031                 { "1280x720", 1280,  720},
7032                 { "1280x800", 1280,  800},
7033                 {"1280x1024", 1280, 1024},
7034                 { "1440x900", 1440,  900},
7035                 {"1680x1050", 1680, 1050},
7036                 {"1600x1200", 1600, 1200},
7037                 {"1920x1080", 1920, 1080},
7038                 {"1920x1200", 1920, 1200}
7039         };
7040
7041         n = ARRAY_SIZE(common_modes);
7042
7043         for (i = 0; i < n; i++) {
7044                 struct drm_display_mode *curmode = NULL;
7045                 bool mode_existed = false;
7046
7047                 if (common_modes[i].w > native_mode->hdisplay ||
7048                     common_modes[i].h > native_mode->vdisplay ||
7049                    (common_modes[i].w == native_mode->hdisplay &&
7050                     common_modes[i].h == native_mode->vdisplay))
7051                         continue;
7052
7053                 list_for_each_entry(curmode, &connector->probed_modes, head) {
7054                         if (common_modes[i].w == curmode->hdisplay &&
7055                             common_modes[i].h == curmode->vdisplay) {
7056                                 mode_existed = true;
7057                                 break;
7058                         }
7059                 }
7060
7061                 if (mode_existed)
7062                         continue;
7063
7064                 mode = amdgpu_dm_create_common_mode(encoder,
7065                                 common_modes[i].name, common_modes[i].w,
7066                                 common_modes[i].h);
7067                 if (!mode)
7068                         continue;
7069
7070                 drm_mode_probed_add(connector, mode);
7071                 amdgpu_dm_connector->num_modes++;
7072         }
7073 }
7074
7075 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7076 {
7077         struct drm_encoder *encoder;
7078         struct amdgpu_encoder *amdgpu_encoder;
7079         const struct drm_display_mode *native_mode;
7080
7081         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7082             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7083                 return;
7084
7085         mutex_lock(&connector->dev->mode_config.mutex);
7086         amdgpu_dm_connector_get_modes(connector);
7087         mutex_unlock(&connector->dev->mode_config.mutex);
7088
7089         encoder = amdgpu_dm_connector_to_encoder(connector);
7090         if (!encoder)
7091                 return;
7092
7093         amdgpu_encoder = to_amdgpu_encoder(encoder);
7094
7095         native_mode = &amdgpu_encoder->native_mode;
7096         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7097                 return;
7098
7099         drm_connector_set_panel_orientation_with_quirk(connector,
7100                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7101                                                        native_mode->hdisplay,
7102                                                        native_mode->vdisplay);
7103 }
7104
7105 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7106                                               struct edid *edid)
7107 {
7108         struct amdgpu_dm_connector *amdgpu_dm_connector =
7109                         to_amdgpu_dm_connector(connector);
7110
7111         if (edid) {
7112                 /* empty probed_modes */
7113                 INIT_LIST_HEAD(&connector->probed_modes);
7114                 amdgpu_dm_connector->num_modes =
7115                                 drm_add_edid_modes(connector, edid);
7116
7117                 /* sorting the probed modes before calling function
7118                  * amdgpu_dm_get_native_mode() since EDID can have
7119                  * more than one preferred mode. The modes that are
7120                  * later in the probed mode list could be of higher
7121                  * and preferred resolution. For example, 3840x2160
7122                  * resolution in base EDID preferred timing and 4096x2160
7123                  * preferred resolution in DID extension block later.
7124                  */
7125                 drm_mode_sort(&connector->probed_modes);
7126                 amdgpu_dm_get_native_mode(connector);
7127
7128                 /* Freesync capabilities are reset by calling
7129                  * drm_add_edid_modes() and need to be
7130                  * restored here.
7131                  */
7132                 amdgpu_dm_update_freesync_caps(connector, edid);
7133         } else {
7134                 amdgpu_dm_connector->num_modes = 0;
7135         }
7136 }
7137
7138 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7139                               struct drm_display_mode *mode)
7140 {
7141         struct drm_display_mode *m;
7142
7143         list_for_each_entry (m, &aconnector->base.probed_modes, head) {
7144                 if (drm_mode_equal(m, mode))
7145                         return true;
7146         }
7147
7148         return false;
7149 }
7150
7151 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7152 {
7153         const struct drm_display_mode *m;
7154         struct drm_display_mode *new_mode;
7155         uint i;
7156         u32 new_modes_count = 0;
7157
7158         /* Standard FPS values
7159          *
7160          * 23.976       - TV/NTSC
7161          * 24           - Cinema
7162          * 25           - TV/PAL
7163          * 29.97        - TV/NTSC
7164          * 30           - TV/NTSC
7165          * 48           - Cinema HFR
7166          * 50           - TV/PAL
7167          * 60           - Commonly used
7168          * 48,72,96,120 - Multiples of 24
7169          */
7170         static const u32 common_rates[] = {
7171                 23976, 24000, 25000, 29970, 30000,
7172                 48000, 50000, 60000, 72000, 96000, 120000
7173         };
7174
7175         /*
7176          * Find mode with highest refresh rate with the same resolution
7177          * as the preferred mode. Some monitors report a preferred mode
7178          * with lower resolution than the highest refresh rate supported.
7179          */
7180
7181         m = get_highest_refresh_rate_mode(aconnector, true);
7182         if (!m)
7183                 return 0;
7184
7185         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7186                 u64 target_vtotal, target_vtotal_diff;
7187                 u64 num, den;
7188
7189                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7190                         continue;
7191
7192                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7193                     common_rates[i] > aconnector->max_vfreq * 1000)
7194                         continue;
7195
7196                 num = (unsigned long long)m->clock * 1000 * 1000;
7197                 den = common_rates[i] * (unsigned long long)m->htotal;
7198                 target_vtotal = div_u64(num, den);
7199                 target_vtotal_diff = target_vtotal - m->vtotal;
7200
7201                 /* Check for illegal modes */
7202                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7203                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7204                     m->vtotal + target_vtotal_diff < m->vsync_end)
7205                         continue;
7206
7207                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7208                 if (!new_mode)
7209                         goto out;
7210
7211                 new_mode->vtotal += (u16)target_vtotal_diff;
7212                 new_mode->vsync_start += (u16)target_vtotal_diff;
7213                 new_mode->vsync_end += (u16)target_vtotal_diff;
7214                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7215                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7216
7217                 if (!is_duplicate_mode(aconnector, new_mode)) {
7218                         drm_mode_probed_add(&aconnector->base, new_mode);
7219                         new_modes_count += 1;
7220                 } else
7221                         drm_mode_destroy(aconnector->base.dev, new_mode);
7222         }
7223  out:
7224         return new_modes_count;
7225 }
7226
7227 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7228                                                    struct edid *edid)
7229 {
7230         struct amdgpu_dm_connector *amdgpu_dm_connector =
7231                 to_amdgpu_dm_connector(connector);
7232
7233         if (!edid)
7234                 return;
7235
7236         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7237                 amdgpu_dm_connector->num_modes +=
7238                         add_fs_modes(amdgpu_dm_connector);
7239 }
7240
7241 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7242 {
7243         struct amdgpu_dm_connector *amdgpu_dm_connector =
7244                         to_amdgpu_dm_connector(connector);
7245         struct drm_encoder *encoder;
7246         struct edid *edid = amdgpu_dm_connector->edid;
7247         struct dc_link_settings *verified_link_cap =
7248                         &amdgpu_dm_connector->dc_link->verified_link_cap;
7249         const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7250
7251         encoder = amdgpu_dm_connector_to_encoder(connector);
7252
7253         if (!drm_edid_is_valid(edid)) {
7254                 amdgpu_dm_connector->num_modes =
7255                                 drm_add_modes_noedid(connector, 640, 480);
7256                 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7257                         amdgpu_dm_connector->num_modes +=
7258                                 drm_add_modes_noedid(connector, 1920, 1080);
7259         } else {
7260                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7261                 /* most eDP supports only timings from its edid,
7262                  * usually only detailed timings are available
7263                  * from eDP edid. timings which are not from edid
7264                  * may damage eDP
7265                  */
7266                 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
7267                         amdgpu_dm_connector_add_common_modes(encoder, connector);
7268                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7269         }
7270         amdgpu_dm_fbc_init(connector);
7271
7272         return amdgpu_dm_connector->num_modes;
7273 }
7274
7275 static const u32 supported_colorspaces =
7276         BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
7277         BIT(DRM_MODE_COLORIMETRY_OPRGB) |
7278         BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
7279         BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
7280
7281 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7282                                      struct amdgpu_dm_connector *aconnector,
7283                                      int connector_type,
7284                                      struct dc_link *link,
7285                                      int link_index)
7286 {
7287         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7288
7289         /*
7290          * Some of the properties below require access to state, like bpc.
7291          * Allocate some default initial connector state with our reset helper.
7292          */
7293         if (aconnector->base.funcs->reset)
7294                 aconnector->base.funcs->reset(&aconnector->base);
7295
7296         aconnector->connector_id = link_index;
7297         aconnector->bl_idx = -1;
7298         aconnector->dc_link = link;
7299         aconnector->base.interlace_allowed = false;
7300         aconnector->base.doublescan_allowed = false;
7301         aconnector->base.stereo_allowed = false;
7302         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7303         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7304         aconnector->audio_inst = -1;
7305         aconnector->pack_sdp_v1_3 = false;
7306         aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7307         memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7308         mutex_init(&aconnector->hpd_lock);
7309
7310         /*
7311          * configure support HPD hot plug connector_>polled default value is 0
7312          * which means HPD hot plug not supported
7313          */
7314         switch (connector_type) {
7315         case DRM_MODE_CONNECTOR_HDMIA:
7316                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7317                 aconnector->base.ycbcr_420_allowed =
7318                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7319                 break;
7320         case DRM_MODE_CONNECTOR_DisplayPort:
7321                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7322                 link->link_enc = link_enc_cfg_get_link_enc(link);
7323                 ASSERT(link->link_enc);
7324                 if (link->link_enc)
7325                         aconnector->base.ycbcr_420_allowed =
7326                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7327                 break;
7328         case DRM_MODE_CONNECTOR_DVID:
7329                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7330                 break;
7331         default:
7332                 break;
7333         }
7334
7335         drm_object_attach_property(&aconnector->base.base,
7336                                 dm->ddev->mode_config.scaling_mode_property,
7337                                 DRM_MODE_SCALE_NONE);
7338
7339         drm_object_attach_property(&aconnector->base.base,
7340                                 adev->mode_info.underscan_property,
7341                                 UNDERSCAN_OFF);
7342         drm_object_attach_property(&aconnector->base.base,
7343                                 adev->mode_info.underscan_hborder_property,
7344                                 0);
7345         drm_object_attach_property(&aconnector->base.base,
7346                                 adev->mode_info.underscan_vborder_property,
7347                                 0);
7348
7349         if (!aconnector->mst_root)
7350                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7351
7352         aconnector->base.state->max_bpc = 16;
7353         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7354
7355         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7356             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7357                 drm_object_attach_property(&aconnector->base.base,
7358                                 adev->mode_info.abm_level_property, 0);
7359         }
7360
7361         if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7362                 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))
7363                         drm_connector_attach_colorspace_property(&aconnector->base);
7364         } else if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7365                    connector_type == DRM_MODE_CONNECTOR_eDP) {
7366                 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))
7367                         drm_connector_attach_colorspace_property(&aconnector->base);
7368         }
7369
7370         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7371             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7372             connector_type == DRM_MODE_CONNECTOR_eDP) {
7373                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7374
7375                 if (!aconnector->mst_root)
7376                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7377
7378                 if (adev->dm.hdcp_workqueue)
7379                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7380         }
7381 }
7382
7383 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7384                               struct i2c_msg *msgs, int num)
7385 {
7386         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7387         struct ddc_service *ddc_service = i2c->ddc_service;
7388         struct i2c_command cmd;
7389         int i;
7390         int result = -EIO;
7391
7392         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7393
7394         if (!cmd.payloads)
7395                 return result;
7396
7397         cmd.number_of_payloads = num;
7398         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7399         cmd.speed = 100;
7400
7401         for (i = 0; i < num; i++) {
7402                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7403                 cmd.payloads[i].address = msgs[i].addr;
7404                 cmd.payloads[i].length = msgs[i].len;
7405                 cmd.payloads[i].data = msgs[i].buf;
7406         }
7407
7408         if (dc_submit_i2c(
7409                         ddc_service->ctx->dc,
7410                         ddc_service->link->link_index,
7411                         &cmd))
7412                 result = num;
7413
7414         kfree(cmd.payloads);
7415         return result;
7416 }
7417
7418 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7419 {
7420         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7421 }
7422
7423 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7424         .master_xfer = amdgpu_dm_i2c_xfer,
7425         .functionality = amdgpu_dm_i2c_func,
7426 };
7427
7428 static struct amdgpu_i2c_adapter *
7429 create_i2c(struct ddc_service *ddc_service,
7430            int link_index,
7431            int *res)
7432 {
7433         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7434         struct amdgpu_i2c_adapter *i2c;
7435
7436         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7437         if (!i2c)
7438                 return NULL;
7439         i2c->base.owner = THIS_MODULE;
7440         i2c->base.class = I2C_CLASS_DDC;
7441         i2c->base.dev.parent = &adev->pdev->dev;
7442         i2c->base.algo = &amdgpu_dm_i2c_algo;
7443         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7444         i2c_set_adapdata(&i2c->base, i2c);
7445         i2c->ddc_service = ddc_service;
7446
7447         return i2c;
7448 }
7449
7450
7451 /*
7452  * Note: this function assumes that dc_link_detect() was called for the
7453  * dc_link which will be represented by this aconnector.
7454  */
7455 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7456                                     struct amdgpu_dm_connector *aconnector,
7457                                     u32 link_index,
7458                                     struct amdgpu_encoder *aencoder)
7459 {
7460         int res = 0;
7461         int connector_type;
7462         struct dc *dc = dm->dc;
7463         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7464         struct amdgpu_i2c_adapter *i2c;
7465
7466         link->priv = aconnector;
7467
7468         DRM_DEBUG_DRIVER("%s()\n", __func__);
7469
7470         i2c = create_i2c(link->ddc, link->link_index, &res);
7471         if (!i2c) {
7472                 DRM_ERROR("Failed to create i2c adapter data\n");
7473                 return -ENOMEM;
7474         }
7475
7476         aconnector->i2c = i2c;
7477         res = i2c_add_adapter(&i2c->base);
7478
7479         if (res) {
7480                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7481                 goto out_free;
7482         }
7483
7484         connector_type = to_drm_connector_type(link->connector_signal);
7485
7486         res = drm_connector_init_with_ddc(
7487                         dm->ddev,
7488                         &aconnector->base,
7489                         &amdgpu_dm_connector_funcs,
7490                         connector_type,
7491                         &i2c->base);
7492
7493         if (res) {
7494                 DRM_ERROR("connector_init failed\n");
7495                 aconnector->connector_id = -1;
7496                 goto out_free;
7497         }
7498
7499         drm_connector_helper_add(
7500                         &aconnector->base,
7501                         &amdgpu_dm_connector_helper_funcs);
7502
7503         amdgpu_dm_connector_init_helper(
7504                 dm,
7505                 aconnector,
7506                 connector_type,
7507                 link,
7508                 link_index);
7509
7510         drm_connector_attach_encoder(
7511                 &aconnector->base, &aencoder->base);
7512
7513         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7514                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7515                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7516
7517 out_free:
7518         if (res) {
7519                 kfree(i2c);
7520                 aconnector->i2c = NULL;
7521         }
7522         return res;
7523 }
7524
7525 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7526 {
7527         switch (adev->mode_info.num_crtc) {
7528         case 1:
7529                 return 0x1;
7530         case 2:
7531                 return 0x3;
7532         case 3:
7533                 return 0x7;
7534         case 4:
7535                 return 0xf;
7536         case 5:
7537                 return 0x1f;
7538         case 6:
7539         default:
7540                 return 0x3f;
7541         }
7542 }
7543
7544 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7545                                   struct amdgpu_encoder *aencoder,
7546                                   uint32_t link_index)
7547 {
7548         struct amdgpu_device *adev = drm_to_adev(dev);
7549
7550         int res = drm_encoder_init(dev,
7551                                    &aencoder->base,
7552                                    &amdgpu_dm_encoder_funcs,
7553                                    DRM_MODE_ENCODER_TMDS,
7554                                    NULL);
7555
7556         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7557
7558         if (!res)
7559                 aencoder->encoder_id = link_index;
7560         else
7561                 aencoder->encoder_id = -1;
7562
7563         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7564
7565         return res;
7566 }
7567
7568 static void manage_dm_interrupts(struct amdgpu_device *adev,
7569                                  struct amdgpu_crtc *acrtc,
7570                                  bool enable)
7571 {
7572         /*
7573          * We have no guarantee that the frontend index maps to the same
7574          * backend index - some even map to more than one.
7575          *
7576          * TODO: Use a different interrupt or check DC itself for the mapping.
7577          */
7578         int irq_type =
7579                 amdgpu_display_crtc_idx_to_irq_type(
7580                         adev,
7581                         acrtc->crtc_id);
7582
7583         if (enable) {
7584                 drm_crtc_vblank_on(&acrtc->base);
7585                 amdgpu_irq_get(
7586                         adev,
7587                         &adev->pageflip_irq,
7588                         irq_type);
7589 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7590                 amdgpu_irq_get(
7591                         adev,
7592                         &adev->vline0_irq,
7593                         irq_type);
7594 #endif
7595         } else {
7596 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7597                 amdgpu_irq_put(
7598                         adev,
7599                         &adev->vline0_irq,
7600                         irq_type);
7601 #endif
7602                 amdgpu_irq_put(
7603                         adev,
7604                         &adev->pageflip_irq,
7605                         irq_type);
7606                 drm_crtc_vblank_off(&acrtc->base);
7607         }
7608 }
7609
7610 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7611                                       struct amdgpu_crtc *acrtc)
7612 {
7613         int irq_type =
7614                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7615
7616         /**
7617          * This reads the current state for the IRQ and force reapplies
7618          * the setting to hardware.
7619          */
7620         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7621 }
7622
7623 static bool
7624 is_scaling_state_different(const struct dm_connector_state *dm_state,
7625                            const struct dm_connector_state *old_dm_state)
7626 {
7627         if (dm_state->scaling != old_dm_state->scaling)
7628                 return true;
7629         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7630                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7631                         return true;
7632         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7633                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7634                         return true;
7635         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7636                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7637                 return true;
7638         return false;
7639 }
7640
7641 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7642                                             struct drm_crtc_state *old_crtc_state,
7643                                             struct drm_connector_state *new_conn_state,
7644                                             struct drm_connector_state *old_conn_state,
7645                                             const struct drm_connector *connector,
7646                                             struct hdcp_workqueue *hdcp_w)
7647 {
7648         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7649         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7650
7651         pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7652                 connector->index, connector->status, connector->dpms);
7653         pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7654                 old_conn_state->content_protection, new_conn_state->content_protection);
7655
7656         if (old_crtc_state)
7657                 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7658                 old_crtc_state->enable,
7659                 old_crtc_state->active,
7660                 old_crtc_state->mode_changed,
7661                 old_crtc_state->active_changed,
7662                 old_crtc_state->connectors_changed);
7663
7664         if (new_crtc_state)
7665                 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7666                 new_crtc_state->enable,
7667                 new_crtc_state->active,
7668                 new_crtc_state->mode_changed,
7669                 new_crtc_state->active_changed,
7670                 new_crtc_state->connectors_changed);
7671
7672         /* hdcp content type change */
7673         if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7674             new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7675                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7676                 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7677                 return true;
7678         }
7679
7680         /* CP is being re enabled, ignore this */
7681         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7682             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7683                 if (new_crtc_state && new_crtc_state->mode_changed) {
7684                         new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7685                         pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7686                         return true;
7687                 }
7688                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7689                 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7690                 return false;
7691         }
7692
7693         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7694          *
7695          * Handles:     UNDESIRED -> ENABLED
7696          */
7697         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7698             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7699                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7700
7701         /* Stream removed and re-enabled
7702          *
7703          * Can sometimes overlap with the HPD case,
7704          * thus set update_hdcp to false to avoid
7705          * setting HDCP multiple times.
7706          *
7707          * Handles:     DESIRED -> DESIRED (Special case)
7708          */
7709         if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7710                 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7711                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7712                 dm_con_state->update_hdcp = false;
7713                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7714                         __func__);
7715                 return true;
7716         }
7717
7718         /* Hot-plug, headless s3, dpms
7719          *
7720          * Only start HDCP if the display is connected/enabled.
7721          * update_hdcp flag will be set to false until the next
7722          * HPD comes in.
7723          *
7724          * Handles:     DESIRED -> DESIRED (Special case)
7725          */
7726         if (dm_con_state->update_hdcp &&
7727         new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7728         connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7729                 dm_con_state->update_hdcp = false;
7730                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7731                         __func__);
7732                 return true;
7733         }
7734
7735         if (old_conn_state->content_protection == new_conn_state->content_protection) {
7736                 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7737                         if (new_crtc_state && new_crtc_state->mode_changed) {
7738                                 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7739                                         __func__);
7740                                 return true;
7741                         }
7742                         pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7743                                 __func__);
7744                         return false;
7745                 }
7746
7747                 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7748                 return false;
7749         }
7750
7751         if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7752                 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7753                         __func__);
7754                 return true;
7755         }
7756
7757         pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7758         return false;
7759 }
7760
7761 static void remove_stream(struct amdgpu_device *adev,
7762                           struct amdgpu_crtc *acrtc,
7763                           struct dc_stream_state *stream)
7764 {
7765         /* this is the update mode case */
7766
7767         acrtc->otg_inst = -1;
7768         acrtc->enabled = false;
7769 }
7770
7771 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7772 {
7773
7774         assert_spin_locked(&acrtc->base.dev->event_lock);
7775         WARN_ON(acrtc->event);
7776
7777         acrtc->event = acrtc->base.state->event;
7778
7779         /* Set the flip status */
7780         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7781
7782         /* Mark this event as consumed */
7783         acrtc->base.state->event = NULL;
7784
7785         DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7786                      acrtc->crtc_id);
7787 }
7788
7789 static void update_freesync_state_on_stream(
7790         struct amdgpu_display_manager *dm,
7791         struct dm_crtc_state *new_crtc_state,
7792         struct dc_stream_state *new_stream,
7793         struct dc_plane_state *surface,
7794         u32 flip_timestamp_in_us)
7795 {
7796         struct mod_vrr_params vrr_params;
7797         struct dc_info_packet vrr_infopacket = {0};
7798         struct amdgpu_device *adev = dm->adev;
7799         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7800         unsigned long flags;
7801         bool pack_sdp_v1_3 = false;
7802         struct amdgpu_dm_connector *aconn;
7803         enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7804
7805         if (!new_stream)
7806                 return;
7807
7808         /*
7809          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7810          * For now it's sufficient to just guard against these conditions.
7811          */
7812
7813         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7814                 return;
7815
7816         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7817         vrr_params = acrtc->dm_irq_params.vrr_params;
7818
7819         if (surface) {
7820                 mod_freesync_handle_preflip(
7821                         dm->freesync_module,
7822                         surface,
7823                         new_stream,
7824                         flip_timestamp_in_us,
7825                         &vrr_params);
7826
7827                 if (adev->family < AMDGPU_FAMILY_AI &&
7828                     amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7829                         mod_freesync_handle_v_update(dm->freesync_module,
7830                                                      new_stream, &vrr_params);
7831
7832                         /* Need to call this before the frame ends. */
7833                         dc_stream_adjust_vmin_vmax(dm->dc,
7834                                                    new_crtc_state->stream,
7835                                                    &vrr_params.adjust);
7836                 }
7837         }
7838
7839         aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7840
7841         if (aconn && aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
7842                 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7843
7844                 if (aconn->vsdb_info.amd_vsdb_version == 1)
7845                         packet_type = PACKET_TYPE_FS_V1;
7846                 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7847                         packet_type = PACKET_TYPE_FS_V2;
7848                 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7849                         packet_type = PACKET_TYPE_FS_V3;
7850
7851                 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7852                                         &new_stream->adaptive_sync_infopacket);
7853         }
7854
7855         mod_freesync_build_vrr_infopacket(
7856                 dm->freesync_module,
7857                 new_stream,
7858                 &vrr_params,
7859                 packet_type,
7860                 TRANSFER_FUNC_UNKNOWN,
7861                 &vrr_infopacket,
7862                 pack_sdp_v1_3);
7863
7864         new_crtc_state->freesync_vrr_info_changed |=
7865                 (memcmp(&new_crtc_state->vrr_infopacket,
7866                         &vrr_infopacket,
7867                         sizeof(vrr_infopacket)) != 0);
7868
7869         acrtc->dm_irq_params.vrr_params = vrr_params;
7870         new_crtc_state->vrr_infopacket = vrr_infopacket;
7871
7872         new_stream->vrr_infopacket = vrr_infopacket;
7873         new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7874
7875         if (new_crtc_state->freesync_vrr_info_changed)
7876                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7877                               new_crtc_state->base.crtc->base.id,
7878                               (int)new_crtc_state->base.vrr_enabled,
7879                               (int)vrr_params.state);
7880
7881         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7882 }
7883
7884 static void update_stream_irq_parameters(
7885         struct amdgpu_display_manager *dm,
7886         struct dm_crtc_state *new_crtc_state)
7887 {
7888         struct dc_stream_state *new_stream = new_crtc_state->stream;
7889         struct mod_vrr_params vrr_params;
7890         struct mod_freesync_config config = new_crtc_state->freesync_config;
7891         struct amdgpu_device *adev = dm->adev;
7892         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7893         unsigned long flags;
7894
7895         if (!new_stream)
7896                 return;
7897
7898         /*
7899          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7900          * For now it's sufficient to just guard against these conditions.
7901          */
7902         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7903                 return;
7904
7905         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7906         vrr_params = acrtc->dm_irq_params.vrr_params;
7907
7908         if (new_crtc_state->vrr_supported &&
7909             config.min_refresh_in_uhz &&
7910             config.max_refresh_in_uhz) {
7911                 /*
7912                  * if freesync compatible mode was set, config.state will be set
7913                  * in atomic check
7914                  */
7915                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7916                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7917                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7918                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7919                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7920                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7921                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7922                 } else {
7923                         config.state = new_crtc_state->base.vrr_enabled ?
7924                                                      VRR_STATE_ACTIVE_VARIABLE :
7925                                                      VRR_STATE_INACTIVE;
7926                 }
7927         } else {
7928                 config.state = VRR_STATE_UNSUPPORTED;
7929         }
7930
7931         mod_freesync_build_vrr_params(dm->freesync_module,
7932                                       new_stream,
7933                                       &config, &vrr_params);
7934
7935         new_crtc_state->freesync_config = config;
7936         /* Copy state for access from DM IRQ handler */
7937         acrtc->dm_irq_params.freesync_config = config;
7938         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7939         acrtc->dm_irq_params.vrr_params = vrr_params;
7940         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7941 }
7942
7943 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7944                                             struct dm_crtc_state *new_state)
7945 {
7946         bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
7947         bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
7948
7949         if (!old_vrr_active && new_vrr_active) {
7950                 /* Transition VRR inactive -> active:
7951                  * While VRR is active, we must not disable vblank irq, as a
7952                  * reenable after disable would compute bogus vblank/pflip
7953                  * timestamps if it likely happened inside display front-porch.
7954                  *
7955                  * We also need vupdate irq for the actual core vblank handling
7956                  * at end of vblank.
7957                  */
7958                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
7959                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
7960                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7961                                  __func__, new_state->base.crtc->base.id);
7962         } else if (old_vrr_active && !new_vrr_active) {
7963                 /* Transition VRR active -> inactive:
7964                  * Allow vblank irq disable again for fixed refresh rate.
7965                  */
7966                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
7967                 drm_crtc_vblank_put(new_state->base.crtc);
7968                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7969                                  __func__, new_state->base.crtc->base.id);
7970         }
7971 }
7972
7973 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7974 {
7975         struct drm_plane *plane;
7976         struct drm_plane_state *old_plane_state;
7977         int i;
7978
7979         /*
7980          * TODO: Make this per-stream so we don't issue redundant updates for
7981          * commits with multiple streams.
7982          */
7983         for_each_old_plane_in_state(state, plane, old_plane_state, i)
7984                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7985                         amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
7986 }
7987
7988 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
7989 {
7990         struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
7991
7992         return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
7993 }
7994
7995 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7996                                     struct dc_state *dc_state,
7997                                     struct drm_device *dev,
7998                                     struct amdgpu_display_manager *dm,
7999                                     struct drm_crtc *pcrtc,
8000                                     bool wait_for_vblank)
8001 {
8002         u32 i;
8003         u64 timestamp_ns = ktime_get_ns();
8004         struct drm_plane *plane;
8005         struct drm_plane_state *old_plane_state, *new_plane_state;
8006         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
8007         struct drm_crtc_state *new_pcrtc_state =
8008                         drm_atomic_get_new_crtc_state(state, pcrtc);
8009         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
8010         struct dm_crtc_state *dm_old_crtc_state =
8011                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
8012         int planes_count = 0, vpos, hpos;
8013         unsigned long flags;
8014         u32 target_vblank, last_flip_vblank;
8015         bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
8016         bool cursor_update = false;
8017         bool pflip_present = false;
8018         bool dirty_rects_changed = false;
8019         struct {
8020                 struct dc_surface_update surface_updates[MAX_SURFACES];
8021                 struct dc_plane_info plane_infos[MAX_SURFACES];
8022                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
8023                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
8024                 struct dc_stream_update stream_update;
8025         } *bundle;
8026
8027         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8028
8029         if (!bundle) {
8030                 dm_error("Failed to allocate update bundle\n");
8031                 goto cleanup;
8032         }
8033
8034         /*
8035          * Disable the cursor first if we're disabling all the planes.
8036          * It'll remain on the screen after the planes are re-enabled
8037          * if we don't.
8038          */
8039         if (acrtc_state->active_planes == 0)
8040                 amdgpu_dm_commit_cursors(state);
8041
8042         /* update planes when needed */
8043         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8044                 struct drm_crtc *crtc = new_plane_state->crtc;
8045                 struct drm_crtc_state *new_crtc_state;
8046                 struct drm_framebuffer *fb = new_plane_state->fb;
8047                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
8048                 bool plane_needs_flip;
8049                 struct dc_plane_state *dc_plane;
8050                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
8051
8052                 /* Cursor plane is handled after stream updates */
8053                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
8054                         if ((fb && crtc == pcrtc) ||
8055                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
8056                                 cursor_update = true;
8057
8058                         continue;
8059                 }
8060
8061                 if (!fb || !crtc || pcrtc != crtc)
8062                         continue;
8063
8064                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8065                 if (!new_crtc_state->active)
8066                         continue;
8067
8068                 dc_plane = dm_new_plane_state->dc_state;
8069                 if (!dc_plane)
8070                         continue;
8071
8072                 bundle->surface_updates[planes_count].surface = dc_plane;
8073                 if (new_pcrtc_state->color_mgmt_changed) {
8074                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8075                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
8076                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
8077                 }
8078
8079                 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
8080                                      &bundle->scaling_infos[planes_count]);
8081
8082                 bundle->surface_updates[planes_count].scaling_info =
8083                         &bundle->scaling_infos[planes_count];
8084
8085                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8086
8087                 pflip_present = pflip_present || plane_needs_flip;
8088
8089                 if (!plane_needs_flip) {
8090                         planes_count += 1;
8091                         continue;
8092                 }
8093
8094                 fill_dc_plane_info_and_addr(
8095                         dm->adev, new_plane_state,
8096                         afb->tiling_flags,
8097                         &bundle->plane_infos[planes_count],
8098                         &bundle->flip_addrs[planes_count].address,
8099                         afb->tmz_surface, false);
8100
8101                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8102                                  new_plane_state->plane->index,
8103                                  bundle->plane_infos[planes_count].dcc.enable);
8104
8105                 bundle->surface_updates[planes_count].plane_info =
8106                         &bundle->plane_infos[planes_count];
8107
8108                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8109                         fill_dc_dirty_rects(plane, old_plane_state,
8110                                             new_plane_state, new_crtc_state,
8111                                             &bundle->flip_addrs[planes_count],
8112                                             &dirty_rects_changed);
8113
8114                         /*
8115                          * If the dirty regions changed, PSR-SU need to be disabled temporarily
8116                          * and enabled it again after dirty regions are stable to avoid video glitch.
8117                          * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8118                          * during the PSR-SU was disabled.
8119                          */
8120                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8121                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8122 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8123                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8124 #endif
8125                             dirty_rects_changed) {
8126                                 mutex_lock(&dm->dc_lock);
8127                                 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8128                                 timestamp_ns;
8129                                 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8130                                         amdgpu_dm_psr_disable(acrtc_state->stream);
8131                                 mutex_unlock(&dm->dc_lock);
8132                         }
8133                 }
8134
8135                 /*
8136                  * Only allow immediate flips for fast updates that don't
8137                  * change memory domain, FB pitch, DCC state, rotation or
8138                  * mirroring.
8139                  */
8140                 bundle->flip_addrs[planes_count].flip_immediate =
8141                         crtc->state->async_flip &&
8142                         acrtc_state->update_type == UPDATE_TYPE_FAST &&
8143                         get_mem_type(old_plane_state->fb) == get_mem_type(fb);
8144
8145                 timestamp_ns = ktime_get_ns();
8146                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8147                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8148                 bundle->surface_updates[planes_count].surface = dc_plane;
8149
8150                 if (!bundle->surface_updates[planes_count].surface) {
8151                         DRM_ERROR("No surface for CRTC: id=%d\n",
8152                                         acrtc_attach->crtc_id);
8153                         continue;
8154                 }
8155
8156                 if (plane == pcrtc->primary)
8157                         update_freesync_state_on_stream(
8158                                 dm,
8159                                 acrtc_state,
8160                                 acrtc_state->stream,
8161                                 dc_plane,
8162                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8163
8164                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8165                                  __func__,
8166                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8167                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8168
8169                 planes_count += 1;
8170
8171         }
8172
8173         if (pflip_present) {
8174                 if (!vrr_active) {
8175                         /* Use old throttling in non-vrr fixed refresh rate mode
8176                          * to keep flip scheduling based on target vblank counts
8177                          * working in a backwards compatible way, e.g., for
8178                          * clients using the GLX_OML_sync_control extension or
8179                          * DRI3/Present extension with defined target_msc.
8180                          */
8181                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8182                 }
8183                 else {
8184                         /* For variable refresh rate mode only:
8185                          * Get vblank of last completed flip to avoid > 1 vrr
8186                          * flips per video frame by use of throttling, but allow
8187                          * flip programming anywhere in the possibly large
8188                          * variable vrr vblank interval for fine-grained flip
8189                          * timing control and more opportunity to avoid stutter
8190                          * on late submission of flips.
8191                          */
8192                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8193                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8194                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8195                 }
8196
8197                 target_vblank = last_flip_vblank + wait_for_vblank;
8198
8199                 /*
8200                  * Wait until we're out of the vertical blank period before the one
8201                  * targeted by the flip
8202                  */
8203                 while ((acrtc_attach->enabled &&
8204                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8205                                                             0, &vpos, &hpos, NULL,
8206                                                             NULL, &pcrtc->hwmode)
8207                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8208                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8209                         (int)(target_vblank -
8210                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8211                         usleep_range(1000, 1100);
8212                 }
8213
8214                 /**
8215                  * Prepare the flip event for the pageflip interrupt to handle.
8216                  *
8217                  * This only works in the case where we've already turned on the
8218                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8219                  * from 0 -> n planes we have to skip a hardware generated event
8220                  * and rely on sending it from software.
8221                  */
8222                 if (acrtc_attach->base.state->event &&
8223                     acrtc_state->active_planes > 0) {
8224                         drm_crtc_vblank_get(pcrtc);
8225
8226                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8227
8228                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8229                         prepare_flip_isr(acrtc_attach);
8230
8231                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8232                 }
8233
8234                 if (acrtc_state->stream) {
8235                         if (acrtc_state->freesync_vrr_info_changed)
8236                                 bundle->stream_update.vrr_infopacket =
8237                                         &acrtc_state->stream->vrr_infopacket;
8238                 }
8239         } else if (cursor_update && acrtc_state->active_planes > 0 &&
8240                    acrtc_attach->base.state->event) {
8241                 drm_crtc_vblank_get(pcrtc);
8242
8243                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8244
8245                 acrtc_attach->event = acrtc_attach->base.state->event;
8246                 acrtc_attach->base.state->event = NULL;
8247
8248                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8249         }
8250
8251         /* Update the planes if changed or disable if we don't have any. */
8252         if ((planes_count || acrtc_state->active_planes == 0) &&
8253                 acrtc_state->stream) {
8254                 /*
8255                  * If PSR or idle optimizations are enabled then flush out
8256                  * any pending work before hardware programming.
8257                  */
8258                 if (dm->vblank_control_workqueue)
8259                         flush_workqueue(dm->vblank_control_workqueue);
8260
8261                 bundle->stream_update.stream = acrtc_state->stream;
8262                 if (new_pcrtc_state->mode_changed) {
8263                         bundle->stream_update.src = acrtc_state->stream->src;
8264                         bundle->stream_update.dst = acrtc_state->stream->dst;
8265                 }
8266
8267                 if (new_pcrtc_state->color_mgmt_changed) {
8268                         /*
8269                          * TODO: This isn't fully correct since we've actually
8270                          * already modified the stream in place.
8271                          */
8272                         bundle->stream_update.gamut_remap =
8273                                 &acrtc_state->stream->gamut_remap_matrix;
8274                         bundle->stream_update.output_csc_transform =
8275                                 &acrtc_state->stream->csc_color_matrix;
8276                         bundle->stream_update.out_transfer_func =
8277                                 acrtc_state->stream->out_transfer_func;
8278                 }
8279
8280                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8281                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8282                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8283
8284                 mutex_lock(&dm->dc_lock);
8285                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8286                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8287                         amdgpu_dm_psr_disable(acrtc_state->stream);
8288                 mutex_unlock(&dm->dc_lock);
8289
8290                 /*
8291                  * If FreeSync state on the stream has changed then we need to
8292                  * re-adjust the min/max bounds now that DC doesn't handle this
8293                  * as part of commit.
8294                  */
8295                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8296                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8297                         dc_stream_adjust_vmin_vmax(
8298                                 dm->dc, acrtc_state->stream,
8299                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8300                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8301                 }
8302                 mutex_lock(&dm->dc_lock);
8303                 update_planes_and_stream_adapter(dm->dc,
8304                                          acrtc_state->update_type,
8305                                          planes_count,
8306                                          acrtc_state->stream,
8307                                          &bundle->stream_update,
8308                                          bundle->surface_updates);
8309
8310                 /**
8311                  * Enable or disable the interrupts on the backend.
8312                  *
8313                  * Most pipes are put into power gating when unused.
8314                  *
8315                  * When power gating is enabled on a pipe we lose the
8316                  * interrupt enablement state when power gating is disabled.
8317                  *
8318                  * So we need to update the IRQ control state in hardware
8319                  * whenever the pipe turns on (since it could be previously
8320                  * power gated) or off (since some pipes can't be power gated
8321                  * on some ASICs).
8322                  */
8323                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8324                         dm_update_pflip_irq_state(drm_to_adev(dev),
8325                                                   acrtc_attach);
8326
8327                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8328                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8329                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8330                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8331
8332                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8333                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8334                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8335                         struct amdgpu_dm_connector *aconn =
8336                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8337
8338                         if (aconn->psr_skip_count > 0)
8339                                 aconn->psr_skip_count--;
8340
8341                         /* Allow PSR when skip count is 0. */
8342                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8343
8344                         /*
8345                          * If sink supports PSR SU, there is no need to rely on
8346                          * a vblank event disable request to enable PSR. PSR SU
8347                          * can be enabled immediately once OS demonstrates an
8348                          * adequate number of fast atomic commits to notify KMD
8349                          * of update events. See `vblank_control_worker()`.
8350                          */
8351                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8352                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8353 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8354                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8355 #endif
8356                             !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8357                             (timestamp_ns -
8358                             acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8359                             500000000)
8360                                 amdgpu_dm_psr_enable(acrtc_state->stream);
8361                 } else {
8362                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
8363                 }
8364
8365                 mutex_unlock(&dm->dc_lock);
8366         }
8367
8368         /*
8369          * Update cursor state *after* programming all the planes.
8370          * This avoids redundant programming in the case where we're going
8371          * to be disabling a single plane - those pipes are being disabled.
8372          */
8373         if (acrtc_state->active_planes)
8374                 amdgpu_dm_commit_cursors(state);
8375
8376 cleanup:
8377         kfree(bundle);
8378 }
8379
8380 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8381                                    struct drm_atomic_state *state)
8382 {
8383         struct amdgpu_device *adev = drm_to_adev(dev);
8384         struct amdgpu_dm_connector *aconnector;
8385         struct drm_connector *connector;
8386         struct drm_connector_state *old_con_state, *new_con_state;
8387         struct drm_crtc_state *new_crtc_state;
8388         struct dm_crtc_state *new_dm_crtc_state;
8389         const struct dc_stream_status *status;
8390         int i, inst;
8391
8392         /* Notify device removals. */
8393         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8394                 if (old_con_state->crtc != new_con_state->crtc) {
8395                         /* CRTC changes require notification. */
8396                         goto notify;
8397                 }
8398
8399                 if (!new_con_state->crtc)
8400                         continue;
8401
8402                 new_crtc_state = drm_atomic_get_new_crtc_state(
8403                         state, new_con_state->crtc);
8404
8405                 if (!new_crtc_state)
8406                         continue;
8407
8408                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8409                         continue;
8410
8411 notify:
8412                 aconnector = to_amdgpu_dm_connector(connector);
8413
8414                 mutex_lock(&adev->dm.audio_lock);
8415                 inst = aconnector->audio_inst;
8416                 aconnector->audio_inst = -1;
8417                 mutex_unlock(&adev->dm.audio_lock);
8418
8419                 amdgpu_dm_audio_eld_notify(adev, inst);
8420         }
8421
8422         /* Notify audio device additions. */
8423         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8424                 if (!new_con_state->crtc)
8425                         continue;
8426
8427                 new_crtc_state = drm_atomic_get_new_crtc_state(
8428                         state, new_con_state->crtc);
8429
8430                 if (!new_crtc_state)
8431                         continue;
8432
8433                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8434                         continue;
8435
8436                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8437                 if (!new_dm_crtc_state->stream)
8438                         continue;
8439
8440                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8441                 if (!status)
8442                         continue;
8443
8444                 aconnector = to_amdgpu_dm_connector(connector);
8445
8446                 mutex_lock(&adev->dm.audio_lock);
8447                 inst = status->audio_inst;
8448                 aconnector->audio_inst = inst;
8449                 mutex_unlock(&adev->dm.audio_lock);
8450
8451                 amdgpu_dm_audio_eld_notify(adev, inst);
8452         }
8453 }
8454
8455 /*
8456  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8457  * @crtc_state: the DRM CRTC state
8458  * @stream_state: the DC stream state.
8459  *
8460  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8461  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8462  */
8463 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8464                                                 struct dc_stream_state *stream_state)
8465 {
8466         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8467 }
8468
8469 /**
8470  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8471  * @state: The atomic state to commit
8472  *
8473  * This will tell DC to commit the constructed DC state from atomic_check,
8474  * programming the hardware. Any failures here implies a hardware failure, since
8475  * atomic check should have filtered anything non-kosher.
8476  */
8477 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8478 {
8479         struct drm_device *dev = state->dev;
8480         struct amdgpu_device *adev = drm_to_adev(dev);
8481         struct amdgpu_display_manager *dm = &adev->dm;
8482         struct dm_atomic_state *dm_state;
8483         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8484         u32 i, j;
8485         struct drm_crtc *crtc;
8486         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8487         unsigned long flags;
8488         bool wait_for_vblank = true;
8489         struct drm_connector *connector;
8490         struct drm_connector_state *old_con_state, *new_con_state;
8491         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8492         int crtc_disable_count = 0;
8493         bool mode_set_reset_required = false;
8494         int r;
8495
8496         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8497
8498         r = drm_atomic_helper_wait_for_fences(dev, state, false);
8499         if (unlikely(r))
8500                 DRM_ERROR("Waiting for fences timed out!");
8501
8502         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8503         drm_dp_mst_atomic_wait_for_dependencies(state);
8504
8505         dm_state = dm_atomic_get_new_state(state);
8506         if (dm_state && dm_state->context) {
8507                 dc_state = dm_state->context;
8508         } else {
8509                 /* No state changes, retain current state. */
8510                 dc_state_temp = dc_create_state(dm->dc);
8511                 ASSERT(dc_state_temp);
8512                 dc_state = dc_state_temp;
8513                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8514         }
8515
8516         for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8517                                        new_crtc_state, i) {
8518                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8519
8520                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8521
8522                 if (old_crtc_state->active &&
8523                     (!new_crtc_state->active ||
8524                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8525                         manage_dm_interrupts(adev, acrtc, false);
8526                         dc_stream_release(dm_old_crtc_state->stream);
8527                 }
8528         }
8529
8530         drm_atomic_helper_calc_timestamping_constants(state);
8531
8532         /* update changed items */
8533         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8534                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8535
8536                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8537                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8538
8539                 drm_dbg_state(state->dev,
8540                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8541                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8542                         "connectors_changed:%d\n",
8543                         acrtc->crtc_id,
8544                         new_crtc_state->enable,
8545                         new_crtc_state->active,
8546                         new_crtc_state->planes_changed,
8547                         new_crtc_state->mode_changed,
8548                         new_crtc_state->active_changed,
8549                         new_crtc_state->connectors_changed);
8550
8551                 /* Disable cursor if disabling crtc */
8552                 if (old_crtc_state->active && !new_crtc_state->active) {
8553                         struct dc_cursor_position position;
8554
8555                         memset(&position, 0, sizeof(position));
8556                         mutex_lock(&dm->dc_lock);
8557                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8558                         mutex_unlock(&dm->dc_lock);
8559                 }
8560
8561                 /* Copy all transient state flags into dc state */
8562                 if (dm_new_crtc_state->stream) {
8563                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8564                                                             dm_new_crtc_state->stream);
8565                 }
8566
8567                 /* handles headless hotplug case, updating new_state and
8568                  * aconnector as needed
8569                  */
8570
8571                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8572
8573                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8574
8575                         if (!dm_new_crtc_state->stream) {
8576                                 /*
8577                                  * this could happen because of issues with
8578                                  * userspace notifications delivery.
8579                                  * In this case userspace tries to set mode on
8580                                  * display which is disconnected in fact.
8581                                  * dc_sink is NULL in this case on aconnector.
8582                                  * We expect reset mode will come soon.
8583                                  *
8584                                  * This can also happen when unplug is done
8585                                  * during resume sequence ended
8586                                  *
8587                                  * In this case, we want to pretend we still
8588                                  * have a sink to keep the pipe running so that
8589                                  * hw state is consistent with the sw state
8590                                  */
8591                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8592                                                 __func__, acrtc->base.base.id);
8593                                 continue;
8594                         }
8595
8596                         if (dm_old_crtc_state->stream)
8597                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8598
8599                         pm_runtime_get_noresume(dev->dev);
8600
8601                         acrtc->enabled = true;
8602                         acrtc->hw_mode = new_crtc_state->mode;
8603                         crtc->hwmode = new_crtc_state->mode;
8604                         mode_set_reset_required = true;
8605                 } else if (modereset_required(new_crtc_state)) {
8606                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8607                         /* i.e. reset mode */
8608                         if (dm_old_crtc_state->stream)
8609                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8610
8611                         mode_set_reset_required = true;
8612                 }
8613         } /* for_each_crtc_in_state() */
8614
8615         if (dc_state) {
8616                 /* if there mode set or reset, disable eDP PSR */
8617                 if (mode_set_reset_required) {
8618                         if (dm->vblank_control_workqueue)
8619                                 flush_workqueue(dm->vblank_control_workqueue);
8620
8621                         amdgpu_dm_psr_disable_all(dm);
8622                 }
8623
8624                 dm_enable_per_frame_crtc_master_sync(dc_state);
8625                 mutex_lock(&dm->dc_lock);
8626                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8627
8628                 /* Allow idle optimization when vblank count is 0 for display off */
8629                 if (dm->active_vblank_irq_count == 0)
8630                         dc_allow_idle_optimizations(dm->dc, true);
8631                 mutex_unlock(&dm->dc_lock);
8632         }
8633
8634         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8635                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8636
8637                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8638
8639                 if (dm_new_crtc_state->stream != NULL) {
8640                         const struct dc_stream_status *status =
8641                                         dc_stream_get_status(dm_new_crtc_state->stream);
8642
8643                         if (!status)
8644                                 status = dc_stream_get_status_from_state(dc_state,
8645                                                                          dm_new_crtc_state->stream);
8646                         if (!status)
8647                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8648                         else
8649                                 acrtc->otg_inst = status->primary_otg_inst;
8650                 }
8651         }
8652         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8653                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8654                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8655                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8656
8657                 if (!adev->dm.hdcp_workqueue)
8658                         continue;
8659
8660                 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8661
8662                 if (!connector)
8663                         continue;
8664
8665                 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8666                         connector->index, connector->status, connector->dpms);
8667                 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8668                         old_con_state->content_protection, new_con_state->content_protection);
8669
8670                 if (aconnector->dc_sink) {
8671                         if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8672                                 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8673                                 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8674                                 aconnector->dc_sink->edid_caps.display_name);
8675                         }
8676                 }
8677
8678                 new_crtc_state = NULL;
8679                 old_crtc_state = NULL;
8680
8681                 if (acrtc) {
8682                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8683                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8684                 }
8685
8686                 if (old_crtc_state)
8687                         pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8688                         old_crtc_state->enable,
8689                         old_crtc_state->active,
8690                         old_crtc_state->mode_changed,
8691                         old_crtc_state->active_changed,
8692                         old_crtc_state->connectors_changed);
8693
8694                 if (new_crtc_state)
8695                         pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8696                         new_crtc_state->enable,
8697                         new_crtc_state->active,
8698                         new_crtc_state->mode_changed,
8699                         new_crtc_state->active_changed,
8700                         new_crtc_state->connectors_changed);
8701         }
8702
8703         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8704                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8705                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8706                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8707
8708                 if (!adev->dm.hdcp_workqueue)
8709                         continue;
8710
8711                 new_crtc_state = NULL;
8712                 old_crtc_state = NULL;
8713
8714                 if (acrtc) {
8715                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8716                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8717                 }
8718
8719                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8720
8721                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8722                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8723                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8724                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8725                         dm_new_con_state->update_hdcp = true;
8726                         continue;
8727                 }
8728
8729                 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8730                                                                                         old_con_state, connector, adev->dm.hdcp_workqueue)) {
8731                         /* when display is unplugged from mst hub, connctor will
8732                          * be destroyed within dm_dp_mst_connector_destroy. connector
8733                          * hdcp perperties, like type, undesired, desired, enabled,
8734                          * will be lost. So, save hdcp properties into hdcp_work within
8735                          * amdgpu_dm_atomic_commit_tail. if the same display is
8736                          * plugged back with same display index, its hdcp properties
8737                          * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8738                          */
8739
8740                         bool enable_encryption = false;
8741
8742                         if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8743                                 enable_encryption = true;
8744
8745                         if (aconnector->dc_link && aconnector->dc_sink &&
8746                                 aconnector->dc_link->type == dc_connection_mst_branch) {
8747                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8748                                 struct hdcp_workqueue *hdcp_w =
8749                                         &hdcp_work[aconnector->dc_link->link_index];
8750
8751                                 hdcp_w->hdcp_content_type[connector->index] =
8752                                         new_con_state->hdcp_content_type;
8753                                 hdcp_w->content_protection[connector->index] =
8754                                         new_con_state->content_protection;
8755                         }
8756
8757                         if (new_crtc_state && new_crtc_state->mode_changed &&
8758                                 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8759                                 enable_encryption = true;
8760
8761                         DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8762
8763                         hdcp_update_display(
8764                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8765                                 new_con_state->hdcp_content_type, enable_encryption);
8766                 }
8767         }
8768
8769         /* Handle connector state changes */
8770         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8771                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8772                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8773                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8774                 struct dc_surface_update dummy_updates[MAX_SURFACES];
8775                 struct dc_stream_update stream_update;
8776                 struct dc_info_packet hdr_packet;
8777                 struct dc_stream_status *status = NULL;
8778                 bool abm_changed, hdr_changed, scaling_changed;
8779
8780                 memset(&dummy_updates, 0, sizeof(dummy_updates));
8781                 memset(&stream_update, 0, sizeof(stream_update));
8782
8783                 if (acrtc) {
8784                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8785                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8786                 }
8787
8788                 /* Skip any modesets/resets */
8789                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8790                         continue;
8791
8792                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8793                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8794
8795                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8796                                                              dm_old_con_state);
8797
8798                 abm_changed = dm_new_crtc_state->abm_level !=
8799                               dm_old_crtc_state->abm_level;
8800
8801                 hdr_changed =
8802                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8803
8804                 if (!scaling_changed && !abm_changed && !hdr_changed)
8805                         continue;
8806
8807                 stream_update.stream = dm_new_crtc_state->stream;
8808                 if (scaling_changed) {
8809                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8810                                         dm_new_con_state, dm_new_crtc_state->stream);
8811
8812                         stream_update.src = dm_new_crtc_state->stream->src;
8813                         stream_update.dst = dm_new_crtc_state->stream->dst;
8814                 }
8815
8816                 if (abm_changed) {
8817                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8818
8819                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8820                 }
8821
8822                 if (hdr_changed) {
8823                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8824                         stream_update.hdr_static_metadata = &hdr_packet;
8825                 }
8826
8827                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8828
8829                 if (WARN_ON(!status))
8830                         continue;
8831
8832                 WARN_ON(!status->plane_count);
8833
8834                 /*
8835                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8836                  * Here we create an empty update on each plane.
8837                  * To fix this, DC should permit updating only stream properties.
8838                  */
8839                 for (j = 0; j < status->plane_count; j++)
8840                         dummy_updates[j].surface = status->plane_states[0];
8841
8842
8843                 mutex_lock(&dm->dc_lock);
8844                 dc_update_planes_and_stream(dm->dc,
8845                                             dummy_updates,
8846                                             status->plane_count,
8847                                             dm_new_crtc_state->stream,
8848                                             &stream_update);
8849                 mutex_unlock(&dm->dc_lock);
8850         }
8851
8852         /**
8853          * Enable interrupts for CRTCs that are newly enabled or went through
8854          * a modeset. It was intentionally deferred until after the front end
8855          * state was modified to wait until the OTG was on and so the IRQ
8856          * handlers didn't access stale or invalid state.
8857          */
8858         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8859                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8860 #ifdef CONFIG_DEBUG_FS
8861                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8862 #endif
8863                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8864                 if (old_crtc_state->active && !new_crtc_state->active)
8865                         crtc_disable_count++;
8866
8867                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8868                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8869
8870                 /* For freesync config update on crtc state and params for irq */
8871                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8872
8873 #ifdef CONFIG_DEBUG_FS
8874                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8875                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8876                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8877 #endif
8878
8879                 if (new_crtc_state->active &&
8880                     (!old_crtc_state->active ||
8881                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8882                         dc_stream_retain(dm_new_crtc_state->stream);
8883                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8884                         manage_dm_interrupts(adev, acrtc, true);
8885                 }
8886                 /* Handle vrr on->off / off->on transitions */
8887                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8888
8889 #ifdef CONFIG_DEBUG_FS
8890                 if (new_crtc_state->active &&
8891                     (!old_crtc_state->active ||
8892                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8893                         /**
8894                          * Frontend may have changed so reapply the CRC capture
8895                          * settings for the stream.
8896                          */
8897                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8898 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8899                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8900                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8901                                         acrtc->dm_irq_params.window_param.update_win = true;
8902
8903                                         /**
8904                                          * It takes 2 frames for HW to stably generate CRC when
8905                                          * resuming from suspend, so we set skip_frame_cnt 2.
8906                                          */
8907                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8908                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8909                                 }
8910 #endif
8911                                 if (amdgpu_dm_crtc_configure_crc_source(
8912                                         crtc, dm_new_crtc_state, cur_crc_src))
8913                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
8914                         }
8915                 }
8916 #endif
8917         }
8918
8919         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8920                 if (new_crtc_state->async_flip)
8921                         wait_for_vblank = false;
8922
8923         /* update planes when needed per crtc*/
8924         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8925                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8926
8927                 if (dm_new_crtc_state->stream)
8928                         amdgpu_dm_commit_planes(state, dc_state, dev,
8929                                                 dm, crtc, wait_for_vblank);
8930         }
8931
8932         /* Update audio instances for each connector. */
8933         amdgpu_dm_commit_audio(dev, state);
8934
8935         /* restore the backlight level */
8936         for (i = 0; i < dm->num_of_edps; i++) {
8937                 if (dm->backlight_dev[i] &&
8938                     (dm->actual_brightness[i] != dm->brightness[i]))
8939                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8940         }
8941
8942         /*
8943          * send vblank event on all events not handled in flip and
8944          * mark consumed event for drm_atomic_helper_commit_hw_done
8945          */
8946         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8947         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8948
8949                 if (new_crtc_state->event)
8950                         drm_send_event_locked(dev, &new_crtc_state->event->base);
8951
8952                 new_crtc_state->event = NULL;
8953         }
8954         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8955
8956         /* Signal HW programming completion */
8957         drm_atomic_helper_commit_hw_done(state);
8958
8959         if (wait_for_vblank)
8960                 drm_atomic_helper_wait_for_flip_done(dev, state);
8961
8962         drm_atomic_helper_cleanup_planes(dev, state);
8963
8964         /* Don't free the memory if we are hitting this as part of suspend.
8965          * This way we don't free any memory during suspend; see
8966          * amdgpu_bo_free_kernel().  The memory will be freed in the first
8967          * non-suspend modeset or when the driver is torn down.
8968          */
8969         if (!adev->in_suspend) {
8970                 /* return the stolen vga memory back to VRAM */
8971                 if (!adev->mman.keep_stolen_vga_memory)
8972                         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8973                 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8974         }
8975
8976         /*
8977          * Finally, drop a runtime PM reference for each newly disabled CRTC,
8978          * so we can put the GPU into runtime suspend if we're not driving any
8979          * displays anymore
8980          */
8981         for (i = 0; i < crtc_disable_count; i++)
8982                 pm_runtime_put_autosuspend(dev->dev);
8983         pm_runtime_mark_last_busy(dev->dev);
8984
8985         if (dc_state_temp)
8986                 dc_release_state(dc_state_temp);
8987 }
8988
8989 static int dm_force_atomic_commit(struct drm_connector *connector)
8990 {
8991         int ret = 0;
8992         struct drm_device *ddev = connector->dev;
8993         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8994         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8995         struct drm_plane *plane = disconnected_acrtc->base.primary;
8996         struct drm_connector_state *conn_state;
8997         struct drm_crtc_state *crtc_state;
8998         struct drm_plane_state *plane_state;
8999
9000         if (!state)
9001                 return -ENOMEM;
9002
9003         state->acquire_ctx = ddev->mode_config.acquire_ctx;
9004
9005         /* Construct an atomic state to restore previous display setting */
9006
9007         /*
9008          * Attach connectors to drm_atomic_state
9009          */
9010         conn_state = drm_atomic_get_connector_state(state, connector);
9011
9012         ret = PTR_ERR_OR_ZERO(conn_state);
9013         if (ret)
9014                 goto out;
9015
9016         /* Attach crtc to drm_atomic_state*/
9017         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
9018
9019         ret = PTR_ERR_OR_ZERO(crtc_state);
9020         if (ret)
9021                 goto out;
9022
9023         /* force a restore */
9024         crtc_state->mode_changed = true;
9025
9026         /* Attach plane to drm_atomic_state */
9027         plane_state = drm_atomic_get_plane_state(state, plane);
9028
9029         ret = PTR_ERR_OR_ZERO(plane_state);
9030         if (ret)
9031                 goto out;
9032
9033         /* Call commit internally with the state we just constructed */
9034         ret = drm_atomic_commit(state);
9035
9036 out:
9037         drm_atomic_state_put(state);
9038         if (ret)
9039                 DRM_ERROR("Restoring old state failed with %i\n", ret);
9040
9041         return ret;
9042 }
9043
9044 /*
9045  * This function handles all cases when set mode does not come upon hotplug.
9046  * This includes when a display is unplugged then plugged back into the
9047  * same port and when running without usermode desktop manager supprot
9048  */
9049 void dm_restore_drm_connector_state(struct drm_device *dev,
9050                                     struct drm_connector *connector)
9051 {
9052         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9053         struct amdgpu_crtc *disconnected_acrtc;
9054         struct dm_crtc_state *acrtc_state;
9055
9056         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
9057                 return;
9058
9059         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9060         if (!disconnected_acrtc)
9061                 return;
9062
9063         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
9064         if (!acrtc_state->stream)
9065                 return;
9066
9067         /*
9068          * If the previous sink is not released and different from the current,
9069          * we deduce we are in a state where we can not rely on usermode call
9070          * to turn on the display, so we do it here
9071          */
9072         if (acrtc_state->stream->sink != aconnector->dc_sink)
9073                 dm_force_atomic_commit(&aconnector->base);
9074 }
9075
9076 /*
9077  * Grabs all modesetting locks to serialize against any blocking commits,
9078  * Waits for completion of all non blocking commits.
9079  */
9080 static int do_aquire_global_lock(struct drm_device *dev,
9081                                  struct drm_atomic_state *state)
9082 {
9083         struct drm_crtc *crtc;
9084         struct drm_crtc_commit *commit;
9085         long ret;
9086
9087         /*
9088          * Adding all modeset locks to aquire_ctx will
9089          * ensure that when the framework release it the
9090          * extra locks we are locking here will get released to
9091          */
9092         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9093         if (ret)
9094                 return ret;
9095
9096         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9097                 spin_lock(&crtc->commit_lock);
9098                 commit = list_first_entry_or_null(&crtc->commit_list,
9099                                 struct drm_crtc_commit, commit_entry);
9100                 if (commit)
9101                         drm_crtc_commit_get(commit);
9102                 spin_unlock(&crtc->commit_lock);
9103
9104                 if (!commit)
9105                         continue;
9106
9107                 /*
9108                  * Make sure all pending HW programming completed and
9109                  * page flips done
9110                  */
9111                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9112
9113                 if (ret > 0)
9114                         ret = wait_for_completion_interruptible_timeout(
9115                                         &commit->flip_done, 10*HZ);
9116
9117                 if (ret == 0)
9118                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
9119                                   "timed out\n", crtc->base.id, crtc->name);
9120
9121                 drm_crtc_commit_put(commit);
9122         }
9123
9124         return ret < 0 ? ret : 0;
9125 }
9126
9127 static void get_freesync_config_for_crtc(
9128         struct dm_crtc_state *new_crtc_state,
9129         struct dm_connector_state *new_con_state)
9130 {
9131         struct mod_freesync_config config = {0};
9132         struct amdgpu_dm_connector *aconnector =
9133                         to_amdgpu_dm_connector(new_con_state->base.connector);
9134         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9135         int vrefresh = drm_mode_vrefresh(mode);
9136         bool fs_vid_mode = false;
9137
9138         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9139                                         vrefresh >= aconnector->min_vfreq &&
9140                                         vrefresh <= aconnector->max_vfreq;
9141
9142         if (new_crtc_state->vrr_supported) {
9143                 new_crtc_state->stream->ignore_msa_timing_param = true;
9144                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9145
9146                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9147                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9148                 config.vsif_supported = true;
9149                 config.btr = true;
9150
9151                 if (fs_vid_mode) {
9152                         config.state = VRR_STATE_ACTIVE_FIXED;
9153                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9154                         goto out;
9155                 } else if (new_crtc_state->base.vrr_enabled) {
9156                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9157                 } else {
9158                         config.state = VRR_STATE_INACTIVE;
9159                 }
9160         }
9161 out:
9162         new_crtc_state->freesync_config = config;
9163 }
9164
9165 static void reset_freesync_config_for_crtc(
9166         struct dm_crtc_state *new_crtc_state)
9167 {
9168         new_crtc_state->vrr_supported = false;
9169
9170         memset(&new_crtc_state->vrr_infopacket, 0,
9171                sizeof(new_crtc_state->vrr_infopacket));
9172 }
9173
9174 static bool
9175 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9176                                  struct drm_crtc_state *new_crtc_state)
9177 {
9178         const struct drm_display_mode *old_mode, *new_mode;
9179
9180         if (!old_crtc_state || !new_crtc_state)
9181                 return false;
9182
9183         old_mode = &old_crtc_state->mode;
9184         new_mode = &new_crtc_state->mode;
9185
9186         if (old_mode->clock       == new_mode->clock &&
9187             old_mode->hdisplay    == new_mode->hdisplay &&
9188             old_mode->vdisplay    == new_mode->vdisplay &&
9189             old_mode->htotal      == new_mode->htotal &&
9190             old_mode->vtotal      != new_mode->vtotal &&
9191             old_mode->hsync_start == new_mode->hsync_start &&
9192             old_mode->vsync_start != new_mode->vsync_start &&
9193             old_mode->hsync_end   == new_mode->hsync_end &&
9194             old_mode->vsync_end   != new_mode->vsync_end &&
9195             old_mode->hskew       == new_mode->hskew &&
9196             old_mode->vscan       == new_mode->vscan &&
9197             (old_mode->vsync_end - old_mode->vsync_start) ==
9198             (new_mode->vsync_end - new_mode->vsync_start))
9199                 return true;
9200
9201         return false;
9202 }
9203
9204 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
9205         u64 num, den, res;
9206         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9207
9208         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9209
9210         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9211         den = (unsigned long long)new_crtc_state->mode.htotal *
9212               (unsigned long long)new_crtc_state->mode.vtotal;
9213
9214         res = div_u64(num, den);
9215         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9216 }
9217
9218 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9219                          struct drm_atomic_state *state,
9220                          struct drm_crtc *crtc,
9221                          struct drm_crtc_state *old_crtc_state,
9222                          struct drm_crtc_state *new_crtc_state,
9223                          bool enable,
9224                          bool *lock_and_validation_needed)
9225 {
9226         struct dm_atomic_state *dm_state = NULL;
9227         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9228         struct dc_stream_state *new_stream;
9229         int ret = 0;
9230
9231         /*
9232          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9233          * update changed items
9234          */
9235         struct amdgpu_crtc *acrtc = NULL;
9236         struct amdgpu_dm_connector *aconnector = NULL;
9237         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9238         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9239
9240         new_stream = NULL;
9241
9242         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9243         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9244         acrtc = to_amdgpu_crtc(crtc);
9245         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9246
9247         /* TODO This hack should go away */
9248         if (aconnector && enable) {
9249                 /* Make sure fake sink is created in plug-in scenario */
9250                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9251                                                             &aconnector->base);
9252                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9253                                                             &aconnector->base);
9254
9255                 if (IS_ERR(drm_new_conn_state)) {
9256                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9257                         goto fail;
9258                 }
9259
9260                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9261                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9262
9263                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9264                         goto skip_modeset;
9265
9266                 new_stream = create_validate_stream_for_sink(aconnector,
9267                                                              &new_crtc_state->mode,
9268                                                              dm_new_conn_state,
9269                                                              dm_old_crtc_state->stream);
9270
9271                 /*
9272                  * we can have no stream on ACTION_SET if a display
9273                  * was disconnected during S3, in this case it is not an
9274                  * error, the OS will be updated after detection, and
9275                  * will do the right thing on next atomic commit
9276                  */
9277
9278                 if (!new_stream) {
9279                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9280                                         __func__, acrtc->base.base.id);
9281                         ret = -ENOMEM;
9282                         goto fail;
9283                 }
9284
9285                 /*
9286                  * TODO: Check VSDB bits to decide whether this should
9287                  * be enabled or not.
9288                  */
9289                 new_stream->triggered_crtc_reset.enabled =
9290                         dm->force_timing_sync;
9291
9292                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9293
9294                 ret = fill_hdr_info_packet(drm_new_conn_state,
9295                                            &new_stream->hdr_static_metadata);
9296                 if (ret)
9297                         goto fail;
9298
9299                 /*
9300                  * If we already removed the old stream from the context
9301                  * (and set the new stream to NULL) then we can't reuse
9302                  * the old stream even if the stream and scaling are unchanged.
9303                  * We'll hit the BUG_ON and black screen.
9304                  *
9305                  * TODO: Refactor this function to allow this check to work
9306                  * in all conditions.
9307                  */
9308                 if (dm_new_crtc_state->stream &&
9309                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9310                         goto skip_modeset;
9311
9312                 if (dm_new_crtc_state->stream &&
9313                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9314                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9315                         new_crtc_state->mode_changed = false;
9316                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9317                                          new_crtc_state->mode_changed);
9318                 }
9319         }
9320
9321         /* mode_changed flag may get updated above, need to check again */
9322         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9323                 goto skip_modeset;
9324
9325         drm_dbg_state(state->dev,
9326                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
9327                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
9328                 "connectors_changed:%d\n",
9329                 acrtc->crtc_id,
9330                 new_crtc_state->enable,
9331                 new_crtc_state->active,
9332                 new_crtc_state->planes_changed,
9333                 new_crtc_state->mode_changed,
9334                 new_crtc_state->active_changed,
9335                 new_crtc_state->connectors_changed);
9336
9337         /* Remove stream for any changed/disabled CRTC */
9338         if (!enable) {
9339
9340                 if (!dm_old_crtc_state->stream)
9341                         goto skip_modeset;
9342
9343                 /* Unset freesync video if it was active before */
9344                 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9345                         dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9346                         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9347                 }
9348
9349                 /* Now check if we should set freesync video mode */
9350                 if (dm_new_crtc_state->stream &&
9351                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9352                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
9353                     is_timing_unchanged_for_freesync(new_crtc_state,
9354                                                      old_crtc_state)) {
9355                         new_crtc_state->mode_changed = false;
9356                         DRM_DEBUG_DRIVER(
9357                                 "Mode change not required for front porch change, "
9358                                 "setting mode_changed to %d",
9359                                 new_crtc_state->mode_changed);
9360
9361                         set_freesync_fixed_config(dm_new_crtc_state);
9362
9363                         goto skip_modeset;
9364                 } else if (aconnector &&
9365                            is_freesync_video_mode(&new_crtc_state->mode,
9366                                                   aconnector)) {
9367                         struct drm_display_mode *high_mode;
9368
9369                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
9370                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
9371                                 set_freesync_fixed_config(dm_new_crtc_state);
9372                         }
9373                 }
9374
9375                 ret = dm_atomic_get_state(state, &dm_state);
9376                 if (ret)
9377                         goto fail;
9378
9379                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9380                                 crtc->base.id);
9381
9382                 /* i.e. reset mode */
9383                 if (dc_remove_stream_from_ctx(
9384                                 dm->dc,
9385                                 dm_state->context,
9386                                 dm_old_crtc_state->stream) != DC_OK) {
9387                         ret = -EINVAL;
9388                         goto fail;
9389                 }
9390
9391                 dc_stream_release(dm_old_crtc_state->stream);
9392                 dm_new_crtc_state->stream = NULL;
9393
9394                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9395
9396                 *lock_and_validation_needed = true;
9397
9398         } else {/* Add stream for any updated/enabled CRTC */
9399                 /*
9400                  * Quick fix to prevent NULL pointer on new_stream when
9401                  * added MST connectors not found in existing crtc_state in the chained mode
9402                  * TODO: need to dig out the root cause of that
9403                  */
9404                 if (!aconnector)
9405                         goto skip_modeset;
9406
9407                 if (modereset_required(new_crtc_state))
9408                         goto skip_modeset;
9409
9410                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9411                                      dm_old_crtc_state->stream)) {
9412
9413                         WARN_ON(dm_new_crtc_state->stream);
9414
9415                         ret = dm_atomic_get_state(state, &dm_state);
9416                         if (ret)
9417                                 goto fail;
9418
9419                         dm_new_crtc_state->stream = new_stream;
9420
9421                         dc_stream_retain(new_stream);
9422
9423                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9424                                          crtc->base.id);
9425
9426                         if (dc_add_stream_to_ctx(
9427                                         dm->dc,
9428                                         dm_state->context,
9429                                         dm_new_crtc_state->stream) != DC_OK) {
9430                                 ret = -EINVAL;
9431                                 goto fail;
9432                         }
9433
9434                         *lock_and_validation_needed = true;
9435                 }
9436         }
9437
9438 skip_modeset:
9439         /* Release extra reference */
9440         if (new_stream)
9441                 dc_stream_release(new_stream);
9442
9443         /*
9444          * We want to do dc stream updates that do not require a
9445          * full modeset below.
9446          */
9447         if (!(enable && aconnector && new_crtc_state->active))
9448                 return 0;
9449         /*
9450          * Given above conditions, the dc state cannot be NULL because:
9451          * 1. We're in the process of enabling CRTCs (just been added
9452          *    to the dc context, or already is on the context)
9453          * 2. Has a valid connector attached, and
9454          * 3. Is currently active and enabled.
9455          * => The dc stream state currently exists.
9456          */
9457         BUG_ON(dm_new_crtc_state->stream == NULL);
9458
9459         /* Scaling or underscan settings */
9460         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9461                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
9462                 update_stream_scaling_settings(
9463                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9464
9465         /* ABM settings */
9466         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9467
9468         /*
9469          * Color management settings. We also update color properties
9470          * when a modeset is needed, to ensure it gets reprogrammed.
9471          */
9472         if (dm_new_crtc_state->base.color_mgmt_changed ||
9473             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9474                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9475                 if (ret)
9476                         goto fail;
9477         }
9478
9479         /* Update Freesync settings. */
9480         get_freesync_config_for_crtc(dm_new_crtc_state,
9481                                      dm_new_conn_state);
9482
9483         return ret;
9484
9485 fail:
9486         if (new_stream)
9487                 dc_stream_release(new_stream);
9488         return ret;
9489 }
9490
9491 static bool should_reset_plane(struct drm_atomic_state *state,
9492                                struct drm_plane *plane,
9493                                struct drm_plane_state *old_plane_state,
9494                                struct drm_plane_state *new_plane_state)
9495 {
9496         struct drm_plane *other;
9497         struct drm_plane_state *old_other_state, *new_other_state;
9498         struct drm_crtc_state *new_crtc_state;
9499         int i;
9500
9501         /*
9502          * TODO: Remove this hack once the checks below are sufficient
9503          * enough to determine when we need to reset all the planes on
9504          * the stream.
9505          */
9506         if (state->allow_modeset)
9507                 return true;
9508
9509         /* Exit early if we know that we're adding or removing the plane. */
9510         if (old_plane_state->crtc != new_plane_state->crtc)
9511                 return true;
9512
9513         /* old crtc == new_crtc == NULL, plane not in context. */
9514         if (!new_plane_state->crtc)
9515                 return false;
9516
9517         new_crtc_state =
9518                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9519
9520         if (!new_crtc_state)
9521                 return true;
9522
9523         /* CRTC Degamma changes currently require us to recreate planes. */
9524         if (new_crtc_state->color_mgmt_changed)
9525                 return true;
9526
9527         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9528                 return true;
9529
9530         /*
9531          * If there are any new primary or overlay planes being added or
9532          * removed then the z-order can potentially change. To ensure
9533          * correct z-order and pipe acquisition the current DC architecture
9534          * requires us to remove and recreate all existing planes.
9535          *
9536          * TODO: Come up with a more elegant solution for this.
9537          */
9538         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9539                 struct amdgpu_framebuffer *old_afb, *new_afb;
9540                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9541                         continue;
9542
9543                 if (old_other_state->crtc != new_plane_state->crtc &&
9544                     new_other_state->crtc != new_plane_state->crtc)
9545                         continue;
9546
9547                 if (old_other_state->crtc != new_other_state->crtc)
9548                         return true;
9549
9550                 /* Src/dst size and scaling updates. */
9551                 if (old_other_state->src_w != new_other_state->src_w ||
9552                     old_other_state->src_h != new_other_state->src_h ||
9553                     old_other_state->crtc_w != new_other_state->crtc_w ||
9554                     old_other_state->crtc_h != new_other_state->crtc_h)
9555                         return true;
9556
9557                 /* Rotation / mirroring updates. */
9558                 if (old_other_state->rotation != new_other_state->rotation)
9559                         return true;
9560
9561                 /* Blending updates. */
9562                 if (old_other_state->pixel_blend_mode !=
9563                     new_other_state->pixel_blend_mode)
9564                         return true;
9565
9566                 /* Alpha updates. */
9567                 if (old_other_state->alpha != new_other_state->alpha)
9568                         return true;
9569
9570                 /* Colorspace changes. */
9571                 if (old_other_state->color_range != new_other_state->color_range ||
9572                     old_other_state->color_encoding != new_other_state->color_encoding)
9573                         return true;
9574
9575                 /* Framebuffer checks fall at the end. */
9576                 if (!old_other_state->fb || !new_other_state->fb)
9577                         continue;
9578
9579                 /* Pixel format changes can require bandwidth updates. */
9580                 if (old_other_state->fb->format != new_other_state->fb->format)
9581                         return true;
9582
9583                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9584                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9585
9586                 /* Tiling and DCC changes also require bandwidth updates. */
9587                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9588                     old_afb->base.modifier != new_afb->base.modifier)
9589                         return true;
9590         }
9591
9592         return false;
9593 }
9594
9595 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9596                               struct drm_plane_state *new_plane_state,
9597                               struct drm_framebuffer *fb)
9598 {
9599         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9600         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9601         unsigned int pitch;
9602         bool linear;
9603
9604         if (fb->width > new_acrtc->max_cursor_width ||
9605             fb->height > new_acrtc->max_cursor_height) {
9606                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9607                                  new_plane_state->fb->width,
9608                                  new_plane_state->fb->height);
9609                 return -EINVAL;
9610         }
9611         if (new_plane_state->src_w != fb->width << 16 ||
9612             new_plane_state->src_h != fb->height << 16) {
9613                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9614                 return -EINVAL;
9615         }
9616
9617         /* Pitch in pixels */
9618         pitch = fb->pitches[0] / fb->format->cpp[0];
9619
9620         if (fb->width != pitch) {
9621                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9622                                  fb->width, pitch);
9623                 return -EINVAL;
9624         }
9625
9626         switch (pitch) {
9627         case 64:
9628         case 128:
9629         case 256:
9630                 /* FB pitch is supported by cursor plane */
9631                 break;
9632         default:
9633                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9634                 return -EINVAL;
9635         }
9636
9637         /* Core DRM takes care of checking FB modifiers, so we only need to
9638          * check tiling flags when the FB doesn't have a modifier. */
9639         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9640                 if (adev->family < AMDGPU_FAMILY_AI) {
9641                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9642                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9643                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9644                 } else {
9645                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9646                 }
9647                 if (!linear) {
9648                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9649                         return -EINVAL;
9650                 }
9651         }
9652
9653         return 0;
9654 }
9655
9656 static int dm_update_plane_state(struct dc *dc,
9657                                  struct drm_atomic_state *state,
9658                                  struct drm_plane *plane,
9659                                  struct drm_plane_state *old_plane_state,
9660                                  struct drm_plane_state *new_plane_state,
9661                                  bool enable,
9662                                  bool *lock_and_validation_needed,
9663                                  bool *is_top_most_overlay)
9664 {
9665
9666         struct dm_atomic_state *dm_state = NULL;
9667         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9668         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9669         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9670         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9671         struct amdgpu_crtc *new_acrtc;
9672         bool needs_reset;
9673         int ret = 0;
9674
9675
9676         new_plane_crtc = new_plane_state->crtc;
9677         old_plane_crtc = old_plane_state->crtc;
9678         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9679         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9680
9681         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9682                 if (!enable || !new_plane_crtc ||
9683                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9684                         return 0;
9685
9686                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9687
9688                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9689                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9690                         return -EINVAL;
9691                 }
9692
9693                 if (new_plane_state->fb) {
9694                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9695                                                  new_plane_state->fb);
9696                         if (ret)
9697                                 return ret;
9698                 }
9699
9700                 return 0;
9701         }
9702
9703         needs_reset = should_reset_plane(state, plane, old_plane_state,
9704                                          new_plane_state);
9705
9706         /* Remove any changed/removed planes */
9707         if (!enable) {
9708                 if (!needs_reset)
9709                         return 0;
9710
9711                 if (!old_plane_crtc)
9712                         return 0;
9713
9714                 old_crtc_state = drm_atomic_get_old_crtc_state(
9715                                 state, old_plane_crtc);
9716                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9717
9718                 if (!dm_old_crtc_state->stream)
9719                         return 0;
9720
9721                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9722                                 plane->base.id, old_plane_crtc->base.id);
9723
9724                 ret = dm_atomic_get_state(state, &dm_state);
9725                 if (ret)
9726                         return ret;
9727
9728                 if (!dc_remove_plane_from_context(
9729                                 dc,
9730                                 dm_old_crtc_state->stream,
9731                                 dm_old_plane_state->dc_state,
9732                                 dm_state->context)) {
9733
9734                         return -EINVAL;
9735                 }
9736
9737                 if (dm_old_plane_state->dc_state)
9738                         dc_plane_state_release(dm_old_plane_state->dc_state);
9739
9740                 dm_new_plane_state->dc_state = NULL;
9741
9742                 *lock_and_validation_needed = true;
9743
9744         } else { /* Add new planes */
9745                 struct dc_plane_state *dc_new_plane_state;
9746
9747                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9748                         return 0;
9749
9750                 if (!new_plane_crtc)
9751                         return 0;
9752
9753                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9754                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9755
9756                 if (!dm_new_crtc_state->stream)
9757                         return 0;
9758
9759                 if (!needs_reset)
9760                         return 0;
9761
9762                 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9763                 if (ret)
9764                         return ret;
9765
9766                 WARN_ON(dm_new_plane_state->dc_state);
9767
9768                 dc_new_plane_state = dc_create_plane_state(dc);
9769                 if (!dc_new_plane_state)
9770                         return -ENOMEM;
9771
9772                 /* Block top most plane from being a video plane */
9773                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9774                         if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9775                                 return -EINVAL;
9776                         else
9777                                 *is_top_most_overlay = false;
9778                 }
9779
9780                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9781                                  plane->base.id, new_plane_crtc->base.id);
9782
9783                 ret = fill_dc_plane_attributes(
9784                         drm_to_adev(new_plane_crtc->dev),
9785                         dc_new_plane_state,
9786                         new_plane_state,
9787                         new_crtc_state);
9788                 if (ret) {
9789                         dc_plane_state_release(dc_new_plane_state);
9790                         return ret;
9791                 }
9792
9793                 ret = dm_atomic_get_state(state, &dm_state);
9794                 if (ret) {
9795                         dc_plane_state_release(dc_new_plane_state);
9796                         return ret;
9797                 }
9798
9799                 /*
9800                  * Any atomic check errors that occur after this will
9801                  * not need a release. The plane state will be attached
9802                  * to the stream, and therefore part of the atomic
9803                  * state. It'll be released when the atomic state is
9804                  * cleaned.
9805                  */
9806                 if (!dc_add_plane_to_context(
9807                                 dc,
9808                                 dm_new_crtc_state->stream,
9809                                 dc_new_plane_state,
9810                                 dm_state->context)) {
9811
9812                         dc_plane_state_release(dc_new_plane_state);
9813                         return -EINVAL;
9814                 }
9815
9816                 dm_new_plane_state->dc_state = dc_new_plane_state;
9817
9818                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9819
9820                 /* Tell DC to do a full surface update every time there
9821                  * is a plane change. Inefficient, but works for now.
9822                  */
9823                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9824
9825                 *lock_and_validation_needed = true;
9826         }
9827
9828
9829         return ret;
9830 }
9831
9832 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9833                                        int *src_w, int *src_h)
9834 {
9835         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9836         case DRM_MODE_ROTATE_90:
9837         case DRM_MODE_ROTATE_270:
9838                 *src_w = plane_state->src_h >> 16;
9839                 *src_h = plane_state->src_w >> 16;
9840                 break;
9841         case DRM_MODE_ROTATE_0:
9842         case DRM_MODE_ROTATE_180:
9843         default:
9844                 *src_w = plane_state->src_w >> 16;
9845                 *src_h = plane_state->src_h >> 16;
9846                 break;
9847         }
9848 }
9849
9850 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9851                                 struct drm_crtc *crtc,
9852                                 struct drm_crtc_state *new_crtc_state)
9853 {
9854         struct drm_plane *cursor = crtc->cursor, *underlying;
9855         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9856         int i;
9857         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9858         int cursor_src_w, cursor_src_h;
9859         int underlying_src_w, underlying_src_h;
9860
9861         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9862          * cursor per pipe but it's going to inherit the scaling and
9863          * positioning from the underlying pipe. Check the cursor plane's
9864          * blending properties match the underlying planes'. */
9865
9866         new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9867         if (!new_cursor_state || !new_cursor_state->fb) {
9868                 return 0;
9869         }
9870
9871         dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9872         cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9873         cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9874
9875         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9876                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9877                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9878                         continue;
9879
9880                 /* Ignore disabled planes */
9881                 if (!new_underlying_state->fb)
9882                         continue;
9883
9884                 dm_get_oriented_plane_size(new_underlying_state,
9885                                            &underlying_src_w, &underlying_src_h);
9886                 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9887                 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9888
9889                 if (cursor_scale_w != underlying_scale_w ||
9890                     cursor_scale_h != underlying_scale_h) {
9891                         drm_dbg_atomic(crtc->dev,
9892                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9893                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9894                         return -EINVAL;
9895                 }
9896
9897                 /* If this plane covers the whole CRTC, no need to check planes underneath */
9898                 if (new_underlying_state->crtc_x <= 0 &&
9899                     new_underlying_state->crtc_y <= 0 &&
9900                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9901                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9902                         break;
9903         }
9904
9905         return 0;
9906 }
9907
9908 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9909 {
9910         struct drm_connector *connector;
9911         struct drm_connector_state *conn_state, *old_conn_state;
9912         struct amdgpu_dm_connector *aconnector = NULL;
9913         int i;
9914         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9915                 if (!conn_state->crtc)
9916                         conn_state = old_conn_state;
9917
9918                 if (conn_state->crtc != crtc)
9919                         continue;
9920
9921                 aconnector = to_amdgpu_dm_connector(connector);
9922                 if (!aconnector->mst_output_port || !aconnector->mst_root)
9923                         aconnector = NULL;
9924                 else
9925                         break;
9926         }
9927
9928         if (!aconnector)
9929                 return 0;
9930
9931         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
9932 }
9933
9934 /**
9935  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9936  *
9937  * @dev: The DRM device
9938  * @state: The atomic state to commit
9939  *
9940  * Validate that the given atomic state is programmable by DC into hardware.
9941  * This involves constructing a &struct dc_state reflecting the new hardware
9942  * state we wish to commit, then querying DC to see if it is programmable. It's
9943  * important not to modify the existing DC state. Otherwise, atomic_check
9944  * may unexpectedly commit hardware changes.
9945  *
9946  * When validating the DC state, it's important that the right locks are
9947  * acquired. For full updates case which removes/adds/updates streams on one
9948  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9949  * that any such full update commit will wait for completion of any outstanding
9950  * flip using DRMs synchronization events.
9951  *
9952  * Note that DM adds the affected connectors for all CRTCs in state, when that
9953  * might not seem necessary. This is because DC stream creation requires the
9954  * DC sink, which is tied to the DRM connector state. Cleaning this up should
9955  * be possible but non-trivial - a possible TODO item.
9956  *
9957  * Return: -Error code if validation failed.
9958  */
9959 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9960                                   struct drm_atomic_state *state)
9961 {
9962         struct amdgpu_device *adev = drm_to_adev(dev);
9963         struct dm_atomic_state *dm_state = NULL;
9964         struct dc *dc = adev->dm.dc;
9965         struct drm_connector *connector;
9966         struct drm_connector_state *old_con_state, *new_con_state;
9967         struct drm_crtc *crtc;
9968         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9969         struct drm_plane *plane;
9970         struct drm_plane_state *old_plane_state, *new_plane_state;
9971         enum dc_status status;
9972         int ret, i;
9973         bool lock_and_validation_needed = false;
9974         bool is_top_most_overlay = true;
9975         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9976         struct drm_dp_mst_topology_mgr *mgr;
9977         struct drm_dp_mst_topology_state *mst_state;
9978         struct dsc_mst_fairness_vars vars[MAX_PIPES];
9979
9980         trace_amdgpu_dm_atomic_check_begin(state);
9981
9982         ret = drm_atomic_helper_check_modeset(dev, state);
9983         if (ret) {
9984                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9985                 goto fail;
9986         }
9987
9988         /* Check connector changes */
9989         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9990                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9991                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9992
9993                 /* Skip connectors that are disabled or part of modeset already. */
9994                 if (!new_con_state->crtc)
9995                         continue;
9996
9997                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9998                 if (IS_ERR(new_crtc_state)) {
9999                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
10000                         ret = PTR_ERR(new_crtc_state);
10001                         goto fail;
10002                 }
10003
10004                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
10005                     dm_old_con_state->scaling != dm_new_con_state->scaling)
10006                         new_crtc_state->connectors_changed = true;
10007         }
10008
10009         if (dc_resource_is_dsc_encoding_supported(dc)) {
10010                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10011                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
10012                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
10013                                 if (ret) {
10014                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
10015                                         goto fail;
10016                                 }
10017                         }
10018                 }
10019         }
10020         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10021                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10022
10023                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
10024                     !new_crtc_state->color_mgmt_changed &&
10025                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
10026                         dm_old_crtc_state->dsc_force_changed == false)
10027                         continue;
10028
10029                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
10030                 if (ret) {
10031                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
10032                         goto fail;
10033                 }
10034
10035                 if (!new_crtc_state->enable)
10036                         continue;
10037
10038                 ret = drm_atomic_add_affected_connectors(state, crtc);
10039                 if (ret) {
10040                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
10041                         goto fail;
10042                 }
10043
10044                 ret = drm_atomic_add_affected_planes(state, crtc);
10045                 if (ret) {
10046                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
10047                         goto fail;
10048                 }
10049
10050                 if (dm_old_crtc_state->dsc_force_changed)
10051                         new_crtc_state->mode_changed = true;
10052         }
10053
10054         /*
10055          * Add all primary and overlay planes on the CRTC to the state
10056          * whenever a plane is enabled to maintain correct z-ordering
10057          * and to enable fast surface updates.
10058          */
10059         drm_for_each_crtc(crtc, dev) {
10060                 bool modified = false;
10061
10062                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10063                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10064                                 continue;
10065
10066                         if (new_plane_state->crtc == crtc ||
10067                             old_plane_state->crtc == crtc) {
10068                                 modified = true;
10069                                 break;
10070                         }
10071                 }
10072
10073                 if (!modified)
10074                         continue;
10075
10076                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
10077                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10078                                 continue;
10079
10080                         new_plane_state =
10081                                 drm_atomic_get_plane_state(state, plane);
10082
10083                         if (IS_ERR(new_plane_state)) {
10084                                 ret = PTR_ERR(new_plane_state);
10085                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
10086                                 goto fail;
10087                         }
10088                 }
10089         }
10090
10091         /*
10092          * DC consults the zpos (layer_index in DC terminology) to determine the
10093          * hw plane on which to enable the hw cursor (see
10094          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
10095          * atomic state, so call drm helper to normalize zpos.
10096          */
10097         ret = drm_atomic_normalize_zpos(dev, state);
10098         if (ret) {
10099                 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10100                 goto fail;
10101         }
10102
10103         /* Remove exiting planes if they are modified */
10104         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10105                 ret = dm_update_plane_state(dc, state, plane,
10106                                             old_plane_state,
10107                                             new_plane_state,
10108                                             false,
10109                                             &lock_and_validation_needed,
10110                                             &is_top_most_overlay);
10111                 if (ret) {
10112                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10113                         goto fail;
10114                 }
10115         }
10116
10117         /* Disable all crtcs which require disable */
10118         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10119                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10120                                            old_crtc_state,
10121                                            new_crtc_state,
10122                                            false,
10123                                            &lock_and_validation_needed);
10124                 if (ret) {
10125                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10126                         goto fail;
10127                 }
10128         }
10129
10130         /* Enable all crtcs which require enable */
10131         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10132                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10133                                            old_crtc_state,
10134                                            new_crtc_state,
10135                                            true,
10136                                            &lock_and_validation_needed);
10137                 if (ret) {
10138                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10139                         goto fail;
10140                 }
10141         }
10142
10143         /* Add new/modified planes */
10144         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10145                 ret = dm_update_plane_state(dc, state, plane,
10146                                             old_plane_state,
10147                                             new_plane_state,
10148                                             true,
10149                                             &lock_and_validation_needed,
10150                                             &is_top_most_overlay);
10151                 if (ret) {
10152                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10153                         goto fail;
10154                 }
10155         }
10156
10157         if (dc_resource_is_dsc_encoding_supported(dc)) {
10158                 ret = pre_validate_dsc(state, &dm_state, vars);
10159                 if (ret != 0)
10160                         goto fail;
10161         }
10162
10163         /* Run this here since we want to validate the streams we created */
10164         ret = drm_atomic_helper_check_planes(dev, state);
10165         if (ret) {
10166                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10167                 goto fail;
10168         }
10169
10170         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10171                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10172                 if (dm_new_crtc_state->mpo_requested)
10173                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10174         }
10175
10176         /* Check cursor planes scaling */
10177         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10178                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10179                 if (ret) {
10180                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10181                         goto fail;
10182                 }
10183         }
10184
10185         if (state->legacy_cursor_update) {
10186                 /*
10187                  * This is a fast cursor update coming from the plane update
10188                  * helper, check if it can be done asynchronously for better
10189                  * performance.
10190                  */
10191                 state->async_update =
10192                         !drm_atomic_helper_async_check(dev, state);
10193
10194                 /*
10195                  * Skip the remaining global validation if this is an async
10196                  * update. Cursor updates can be done without affecting
10197                  * state or bandwidth calcs and this avoids the performance
10198                  * penalty of locking the private state object and
10199                  * allocating a new dc_state.
10200                  */
10201                 if (state->async_update)
10202                         return 0;
10203         }
10204
10205         /* Check scaling and underscan changes*/
10206         /* TODO Removed scaling changes validation due to inability to commit
10207          * new stream into context w\o causing full reset. Need to
10208          * decide how to handle.
10209          */
10210         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10211                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10212                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10213                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10214
10215                 /* Skip any modesets/resets */
10216                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10217                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10218                         continue;
10219
10220                 /* Skip any thing not scale or underscan changes */
10221                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10222                         continue;
10223
10224                 lock_and_validation_needed = true;
10225         }
10226
10227         /* set the slot info for each mst_state based on the link encoding format */
10228         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10229                 struct amdgpu_dm_connector *aconnector;
10230                 struct drm_connector *connector;
10231                 struct drm_connector_list_iter iter;
10232                 u8 link_coding_cap;
10233
10234                 drm_connector_list_iter_begin(dev, &iter);
10235                 drm_for_each_connector_iter(connector, &iter) {
10236                         if (connector->index == mst_state->mgr->conn_base_id) {
10237                                 aconnector = to_amdgpu_dm_connector(connector);
10238                                 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10239                                 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10240
10241                                 break;
10242                         }
10243                 }
10244                 drm_connector_list_iter_end(&iter);
10245         }
10246
10247         /**
10248          * Streams and planes are reset when there are changes that affect
10249          * bandwidth. Anything that affects bandwidth needs to go through
10250          * DC global validation to ensure that the configuration can be applied
10251          * to hardware.
10252          *
10253          * We have to currently stall out here in atomic_check for outstanding
10254          * commits to finish in this case because our IRQ handlers reference
10255          * DRM state directly - we can end up disabling interrupts too early
10256          * if we don't.
10257          *
10258          * TODO: Remove this stall and drop DM state private objects.
10259          */
10260         if (lock_and_validation_needed) {
10261                 ret = dm_atomic_get_state(state, &dm_state);
10262                 if (ret) {
10263                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10264                         goto fail;
10265                 }
10266
10267                 ret = do_aquire_global_lock(dev, state);
10268                 if (ret) {
10269                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10270                         goto fail;
10271                 }
10272
10273                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10274                 if (ret) {
10275                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10276                         ret = -EINVAL;
10277                         goto fail;
10278                 }
10279
10280                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10281                 if (ret) {
10282                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10283                         goto fail;
10284                 }
10285
10286                 /*
10287                  * Perform validation of MST topology in the state:
10288                  * We need to perform MST atomic check before calling
10289                  * dc_validate_global_state(), or there is a chance
10290                  * to get stuck in an infinite loop and hang eventually.
10291                  */
10292                 ret = drm_dp_mst_atomic_check(state);
10293                 if (ret) {
10294                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10295                         goto fail;
10296                 }
10297                 status = dc_validate_global_state(dc, dm_state->context, true);
10298                 if (status != DC_OK) {
10299                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10300                                        dc_status_to_str(status), status);
10301                         ret = -EINVAL;
10302                         goto fail;
10303                 }
10304         } else {
10305                 /*
10306                  * The commit is a fast update. Fast updates shouldn't change
10307                  * the DC context, affect global validation, and can have their
10308                  * commit work done in parallel with other commits not touching
10309                  * the same resource. If we have a new DC context as part of
10310                  * the DM atomic state from validation we need to free it and
10311                  * retain the existing one instead.
10312                  *
10313                  * Furthermore, since the DM atomic state only contains the DC
10314                  * context and can safely be annulled, we can free the state
10315                  * and clear the associated private object now to free
10316                  * some memory and avoid a possible use-after-free later.
10317                  */
10318
10319                 for (i = 0; i < state->num_private_objs; i++) {
10320                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10321
10322                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10323                                 int j = state->num_private_objs-1;
10324
10325                                 dm_atomic_destroy_state(obj,
10326                                                 state->private_objs[i].state);
10327
10328                                 /* If i is not at the end of the array then the
10329                                  * last element needs to be moved to where i was
10330                                  * before the array can safely be truncated.
10331                                  */
10332                                 if (i != j)
10333                                         state->private_objs[i] =
10334                                                 state->private_objs[j];
10335
10336                                 state->private_objs[j].ptr = NULL;
10337                                 state->private_objs[j].state = NULL;
10338                                 state->private_objs[j].old_state = NULL;
10339                                 state->private_objs[j].new_state = NULL;
10340
10341                                 state->num_private_objs = j;
10342                                 break;
10343                         }
10344                 }
10345         }
10346
10347         /* Store the overall update type for use later in atomic check. */
10348         for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
10349                 struct dm_crtc_state *dm_new_crtc_state =
10350                         to_dm_crtc_state(new_crtc_state);
10351
10352                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10353                                                          UPDATE_TYPE_FULL :
10354                                                          UPDATE_TYPE_FAST;
10355         }
10356
10357         /* Must be success */
10358         WARN_ON(ret);
10359
10360         trace_amdgpu_dm_atomic_check_finish(state, ret);
10361
10362         return ret;
10363
10364 fail:
10365         if (ret == -EDEADLK)
10366                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10367         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10368                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10369         else
10370                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
10371
10372         trace_amdgpu_dm_atomic_check_finish(state, ret);
10373
10374         return ret;
10375 }
10376
10377 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10378                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10379 {
10380         u8 dpcd_data;
10381         bool capable = false;
10382
10383         if (amdgpu_dm_connector->dc_link &&
10384                 dm_helpers_dp_read_dpcd(
10385                                 NULL,
10386                                 amdgpu_dm_connector->dc_link,
10387                                 DP_DOWN_STREAM_PORT_COUNT,
10388                                 &dpcd_data,
10389                                 sizeof(dpcd_data))) {
10390                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10391         }
10392
10393         return capable;
10394 }
10395
10396 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10397                 unsigned int offset,
10398                 unsigned int total_length,
10399                 u8 *data,
10400                 unsigned int length,
10401                 struct amdgpu_hdmi_vsdb_info *vsdb)
10402 {
10403         bool res;
10404         union dmub_rb_cmd cmd;
10405         struct dmub_cmd_send_edid_cea *input;
10406         struct dmub_cmd_edid_cea_output *output;
10407
10408         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10409                 return false;
10410
10411         memset(&cmd, 0, sizeof(cmd));
10412
10413         input = &cmd.edid_cea.data.input;
10414
10415         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10416         cmd.edid_cea.header.sub_type = 0;
10417         cmd.edid_cea.header.payload_bytes =
10418                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10419         input->offset = offset;
10420         input->length = length;
10421         input->cea_total_length = total_length;
10422         memcpy(input->payload, data, length);
10423
10424         res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
10425         if (!res) {
10426                 DRM_ERROR("EDID CEA parser failed\n");
10427                 return false;
10428         }
10429
10430         output = &cmd.edid_cea.data.output;
10431
10432         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10433                 if (!output->ack.success) {
10434                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
10435                                         output->ack.offset);
10436                 }
10437         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10438                 if (!output->amd_vsdb.vsdb_found)
10439                         return false;
10440
10441                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10442                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10443                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10444                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10445         } else {
10446                 DRM_WARN("Unknown EDID CEA parser results\n");
10447                 return false;
10448         }
10449
10450         return true;
10451 }
10452
10453 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10454                 u8 *edid_ext, int len,
10455                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10456 {
10457         int i;
10458
10459         /* send extension block to DMCU for parsing */
10460         for (i = 0; i < len; i += 8) {
10461                 bool res;
10462                 int offset;
10463
10464                 /* send 8 bytes a time */
10465                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10466                         return false;
10467
10468                 if (i+8 == len) {
10469                         /* EDID block sent completed, expect result */
10470                         int version, min_rate, max_rate;
10471
10472                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10473                         if (res) {
10474                                 /* amd vsdb found */
10475                                 vsdb_info->freesync_supported = 1;
10476                                 vsdb_info->amd_vsdb_version = version;
10477                                 vsdb_info->min_refresh_rate_hz = min_rate;
10478                                 vsdb_info->max_refresh_rate_hz = max_rate;
10479                                 return true;
10480                         }
10481                         /* not amd vsdb */
10482                         return false;
10483                 }
10484
10485                 /* check for ack*/
10486                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10487                 if (!res)
10488                         return false;
10489         }
10490
10491         return false;
10492 }
10493
10494 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10495                 u8 *edid_ext, int len,
10496                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10497 {
10498         int i;
10499
10500         /* send extension block to DMCU for parsing */
10501         for (i = 0; i < len; i += 8) {
10502                 /* send 8 bytes a time */
10503                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10504                         return false;
10505         }
10506
10507         return vsdb_info->freesync_supported;
10508 }
10509
10510 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10511                 u8 *edid_ext, int len,
10512                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10513 {
10514         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10515         bool ret;
10516
10517         mutex_lock(&adev->dm.dc_lock);
10518         if (adev->dm.dmub_srv)
10519                 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10520         else
10521                 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10522         mutex_unlock(&adev->dm.dc_lock);
10523         return ret;
10524 }
10525
10526 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10527                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10528 {
10529         u8 *edid_ext = NULL;
10530         int i;
10531         bool valid_vsdb_found = false;
10532
10533         /*----- drm_find_cea_extension() -----*/
10534         /* No EDID or EDID extensions */
10535         if (edid == NULL || edid->extensions == 0)
10536                 return -ENODEV;
10537
10538         /* Find CEA extension */
10539         for (i = 0; i < edid->extensions; i++) {
10540                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10541                 if (edid_ext[0] == CEA_EXT)
10542                         break;
10543         }
10544
10545         if (i == edid->extensions)
10546                 return -ENODEV;
10547
10548         /*----- cea_db_offsets() -----*/
10549         if (edid_ext[0] != CEA_EXT)
10550                 return -ENODEV;
10551
10552         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10553
10554         return valid_vsdb_found ? i : -ENODEV;
10555 }
10556
10557 /**
10558  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10559  *
10560  * @connector: Connector to query.
10561  * @edid: EDID from monitor
10562  *
10563  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10564  * track of some of the display information in the internal data struct used by
10565  * amdgpu_dm. This function checks which type of connector we need to set the
10566  * FreeSync parameters.
10567  */
10568 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10569                                     struct edid *edid)
10570 {
10571         int i = 0;
10572         struct detailed_timing *timing;
10573         struct detailed_non_pixel *data;
10574         struct detailed_data_monitor_range *range;
10575         struct amdgpu_dm_connector *amdgpu_dm_connector =
10576                         to_amdgpu_dm_connector(connector);
10577         struct dm_connector_state *dm_con_state = NULL;
10578         struct dc_sink *sink;
10579
10580         struct drm_device *dev = connector->dev;
10581         struct amdgpu_device *adev = drm_to_adev(dev);
10582         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10583         bool freesync_capable = false;
10584         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10585
10586         if (!connector->state) {
10587                 DRM_ERROR("%s - Connector has no state", __func__);
10588                 goto update;
10589         }
10590
10591         sink = amdgpu_dm_connector->dc_sink ?
10592                 amdgpu_dm_connector->dc_sink :
10593                 amdgpu_dm_connector->dc_em_sink;
10594
10595         if (!edid || !sink) {
10596                 dm_con_state = to_dm_connector_state(connector->state);
10597
10598                 amdgpu_dm_connector->min_vfreq = 0;
10599                 amdgpu_dm_connector->max_vfreq = 0;
10600                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10601                 connector->display_info.monitor_range.min_vfreq = 0;
10602                 connector->display_info.monitor_range.max_vfreq = 0;
10603                 freesync_capable = false;
10604
10605                 goto update;
10606         }
10607
10608         dm_con_state = to_dm_connector_state(connector->state);
10609
10610         if (!adev->dm.freesync_module)
10611                 goto update;
10612
10613         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10614                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10615                 bool edid_check_required = false;
10616
10617                 if (edid) {
10618                         edid_check_required = is_dp_capable_without_timing_msa(
10619                                                 adev->dm.dc,
10620                                                 amdgpu_dm_connector);
10621                 }
10622
10623                 if (edid_check_required == true && (edid->version > 1 ||
10624                    (edid->version == 1 && edid->revision > 1))) {
10625                         for (i = 0; i < 4; i++) {
10626
10627                                 timing  = &edid->detailed_timings[i];
10628                                 data    = &timing->data.other_data;
10629                                 range   = &data->data.range;
10630                                 /*
10631                                  * Check if monitor has continuous frequency mode
10632                                  */
10633                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10634                                         continue;
10635                                 /*
10636                                  * Check for flag range limits only. If flag == 1 then
10637                                  * no additional timing information provided.
10638                                  * Default GTF, GTF Secondary curve and CVT are not
10639                                  * supported
10640                                  */
10641                                 if (range->flags != 1)
10642                                         continue;
10643
10644                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10645                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10646                                 amdgpu_dm_connector->pixel_clock_mhz =
10647                                         range->pixel_clock_mhz * 10;
10648
10649                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10650                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10651
10652                                 break;
10653                         }
10654
10655                         if (amdgpu_dm_connector->max_vfreq -
10656                             amdgpu_dm_connector->min_vfreq > 10) {
10657
10658                                 freesync_capable = true;
10659                         }
10660                 }
10661         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10662                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10663                 if (i >= 0 && vsdb_info.freesync_supported) {
10664                         timing  = &edid->detailed_timings[i];
10665                         data    = &timing->data.other_data;
10666
10667                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10668                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10669                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10670                                 freesync_capable = true;
10671
10672                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10673                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10674                 }
10675         }
10676
10677         as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10678
10679         if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10680                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10681                 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10682
10683                         amdgpu_dm_connector->pack_sdp_v1_3 = true;
10684                         amdgpu_dm_connector->as_type = as_type;
10685                         amdgpu_dm_connector->vsdb_info = vsdb_info;
10686
10687                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10688                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10689                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10690                                 freesync_capable = true;
10691
10692                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10693                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10694                 }
10695         }
10696
10697 update:
10698         if (dm_con_state)
10699                 dm_con_state->freesync_capable = freesync_capable;
10700
10701         if (connector->vrr_capable_property)
10702                 drm_connector_set_vrr_capable_property(connector,
10703                                                        freesync_capable);
10704 }
10705
10706 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10707 {
10708         struct amdgpu_device *adev = drm_to_adev(dev);
10709         struct dc *dc = adev->dm.dc;
10710         int i;
10711
10712         mutex_lock(&adev->dm.dc_lock);
10713         if (dc->current_state) {
10714                 for (i = 0; i < dc->current_state->stream_count; ++i)
10715                         dc->current_state->streams[i]
10716                                 ->triggered_crtc_reset.enabled =
10717                                 adev->dm.force_timing_sync;
10718
10719                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10720                 dc_trigger_sync(dc, dc->current_state);
10721         }
10722         mutex_unlock(&adev->dm.dc_lock);
10723 }
10724
10725 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10726                        u32 value, const char *func_name)
10727 {
10728 #ifdef DM_CHECK_ADDR_0
10729         if (address == 0) {
10730                 DC_ERR("invalid register write. address = 0");
10731                 return;
10732         }
10733 #endif
10734         cgs_write_register(ctx->cgs_device, address, value);
10735         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10736 }
10737
10738 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10739                           const char *func_name)
10740 {
10741         u32 value;
10742 #ifdef DM_CHECK_ADDR_0
10743         if (address == 0) {
10744                 DC_ERR("invalid register read; address = 0\n");
10745                 return 0;
10746         }
10747 #endif
10748
10749         if (ctx->dmub_srv &&
10750             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10751             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10752                 ASSERT(false);
10753                 return 0;
10754         }
10755
10756         value = cgs_read_register(ctx->cgs_device, address);
10757
10758         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10759
10760         return value;
10761 }
10762
10763 int amdgpu_dm_process_dmub_aux_transfer_sync(
10764                 struct dc_context *ctx,
10765                 unsigned int link_index,
10766                 struct aux_payload *payload,
10767                 enum aux_return_code_type *operation_result)
10768 {
10769         struct amdgpu_device *adev = ctx->driver_context;
10770         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10771         int ret = -1;
10772
10773         mutex_lock(&adev->dm.dpia_aux_lock);
10774         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10775                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10776                 goto out;
10777         }
10778
10779         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10780                 DRM_ERROR("wait_for_completion_timeout timeout!");
10781                 *operation_result = AUX_RET_ERROR_TIMEOUT;
10782                 goto out;
10783         }
10784
10785         if (p_notify->result != AUX_RET_SUCCESS) {
10786                 /*
10787                  * Transient states before tunneling is enabled could
10788                  * lead to this error. We can ignore this for now.
10789                  */
10790                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10791                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10792                                         payload->address, payload->length,
10793                                         p_notify->result);
10794                 }
10795                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10796                 goto out;
10797         }
10798
10799
10800         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10801         if (!payload->write && p_notify->aux_reply.length &&
10802                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10803
10804                 if (payload->length != p_notify->aux_reply.length) {
10805                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10806                                 p_notify->aux_reply.length,
10807                                         payload->address, payload->length);
10808                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10809                         goto out;
10810                 }
10811
10812                 memcpy(payload->data, p_notify->aux_reply.data,
10813                                 p_notify->aux_reply.length);
10814         }
10815
10816         /* success */
10817         ret = p_notify->aux_reply.length;
10818         *operation_result = p_notify->result;
10819 out:
10820         reinit_completion(&adev->dm.dmub_aux_transfer_done);
10821         mutex_unlock(&adev->dm.dpia_aux_lock);
10822         return ret;
10823 }
10824
10825 int amdgpu_dm_process_dmub_set_config_sync(
10826                 struct dc_context *ctx,
10827                 unsigned int link_index,
10828                 struct set_config_cmd_payload *payload,
10829                 enum set_config_status *operation_result)
10830 {
10831         struct amdgpu_device *adev = ctx->driver_context;
10832         bool is_cmd_complete;
10833         int ret;
10834
10835         mutex_lock(&adev->dm.dpia_aux_lock);
10836         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10837                         link_index, payload, adev->dm.dmub_notify);
10838
10839         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10840                 ret = 0;
10841                 *operation_result = adev->dm.dmub_notify->sc_status;
10842         } else {
10843                 DRM_ERROR("wait_for_completion_timeout timeout!");
10844                 ret = -1;
10845                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10846         }
10847
10848         if (!is_cmd_complete)
10849                 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10850         mutex_unlock(&adev->dm.dpia_aux_lock);
10851         return ret;
10852 }
10853
10854 /*
10855  * Check whether seamless boot is supported.
10856  *
10857  * So far we only support seamless boot on CHIP_VANGOGH.
10858  * If everything goes well, we may consider expanding
10859  * seamless boot to other ASICs.
10860  */
10861 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10862 {
10863         switch (adev->ip_versions[DCE_HWIP][0]) {
10864         case IP_VERSION(3, 0, 1):
10865                 if (!adev->mman.keep_stolen_vga_memory)
10866                         return true;
10867                 break;
10868         default:
10869                 break;
10870         }
10871
10872         return false;
10873 }
10874
10875 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
10876 {
10877         return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
10878 }
10879
10880 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
10881 {
10882         return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);
10883 }