drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_uvd.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "soc15_common.h"
  31 #include "mmsch_v1_0.h"
  32
  33 #include "uvd/uvd_7_0_offset.h"
  34 #include "uvd/uvd_7_0_sh_mask.h"
  35 #include "vce/vce_4_0_offset.h"
  36 #include "vce/vce_4_0_default.h"
  37 #include "vce/vce_4_0_sh_mask.h"
  38 #include "nbif/nbif_6_1_offset.h"
  39 #include "hdp/hdp_4_0_offset.h"
  40 #include "mmhub/mmhub_1_0_offset.h"
  41 #include "mmhub/mmhub_1_0_sh_mask.h"
  42 #include "ivsrcid/uvd/irqsrcs_uvd_7_0.h"
  43
  44 #define mmUVD_PG0_CC_UVD_HARVESTING                                                                    0x00c7
  45 #define mmUVD_PG0_CC_UVD_HARVESTING_BASE_IDX                                                           1
  46 //UVD_PG0_CC_UVD_HARVESTING
  47 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE__SHIFT                                                         0x1
  48 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK                                                           0x00000002L
  49
  50 #define UVD7_MAX_HW_INSTANCES_VEGA20                    2
  51
  52 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  53 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  54 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  55 static int uvd_v7_0_start(struct amdgpu_device *adev);
  56 static void uvd_v7_0_stop(struct amdgpu_device *adev);
  57 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev);
  58
  59 static int amdgpu_ih_clientid_uvds[] = {
  60         SOC15_IH_CLIENTID_UVD,
  61         SOC15_IH_CLIENTID_UVD1
  62 };
  63
  64 /**
  65  * uvd_v7_0_ring_get_rptr - get read pointer
  66  *
  67  * @ring: amdgpu_ring pointer
  68  *
  69  * Returns the current hardware read pointer
  70  */
  71 static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
  72 {
  73         struct amdgpu_device *adev = ring->adev;
  74
  75         return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
  76 }
  77
  78 /**
  79  * uvd_v7_0_enc_ring_get_rptr - get enc read pointer
  80  *
  81  * @ring: amdgpu_ring pointer
  82  *
  83  * Returns the current hardware enc read pointer
  84  */
  85 static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
  86 {
  87         struct amdgpu_device *adev = ring->adev;
  88
  89         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
  90                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);
  91         else
  92                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);
  93 }
  94
  95 /**
  96  * uvd_v7_0_ring_get_wptr - get write pointer
  97  *
  98  * @ring: amdgpu_ring pointer
  99  *
 100  * Returns the current hardware write pointer
 101  */
 102 static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring)
 103 {
 104         struct amdgpu_device *adev = ring->adev;
 105
 106         return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
 107 }
 108
 109 /**
 110  * uvd_v7_0_enc_ring_get_wptr - get enc write pointer
 111  *
 112  * @ring: amdgpu_ring pointer
 113  *
 114  * Returns the current hardware enc write pointer
 115  */
 116 static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 117 {
 118         struct amdgpu_device *adev = ring->adev;
 119
 120         if (ring->use_doorbell)
 121                 return adev->wb.wb[ring->wptr_offs];
 122
 123         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
 124                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);
 125         else
 126                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);
 127 }
 128
 129 /**
 130  * uvd_v7_0_ring_set_wptr - set write pointer
 131  *
 132  * @ring: amdgpu_ring pointer
 133  *
 134  * Commits the write pointer to the hardware
 135  */
 136 static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring)
 137 {
 138         struct amdgpu_device *adev = ring->adev;
 139
 140         WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 141 }
 142
 143 /**
 144  * uvd_v7_0_enc_ring_set_wptr - set enc write pointer
 145  *
 146  * @ring: amdgpu_ring pointer
 147  *
 148  * Commits the enc write pointer to the hardware
 149  */
 150 static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 151 {
 152         struct amdgpu_device *adev = ring->adev;
 153
 154         if (ring->use_doorbell) {
 155                 /* XXX check if swapping is necessary on BE */
 156                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
 157                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 158                 return;
 159         }
 160
 161         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
 162                 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR,
 163                         lower_32_bits(ring->wptr));
 164         else
 165                 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2,
 166                         lower_32_bits(ring->wptr));
 167 }
 168
 169 /**
 170  * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working
 171  *
 172  * @ring: the engine to test on
 173  *
 174  */
 175 static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
 176 {
 177         struct amdgpu_device *adev = ring->adev;
 178         uint32_t rptr;
 179         unsigned i;
 180         int r;
 181
 182         if (amdgpu_sriov_vf(adev))
 183                 return 0;
 184
 185         r = amdgpu_ring_alloc(ring, 16);
 186         if (r)
 187                 return r;
 188
 189         rptr = amdgpu_ring_get_rptr(ring);
 190
 191         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
 192         amdgpu_ring_commit(ring);
 193
 194         for (i = 0; i < adev->usec_timeout; i++) {
 195                 if (amdgpu_ring_get_rptr(ring) != rptr)
 196                         break;
 197                 DRM_UDELAY(1);
 198         }
 199
 200         if (i >= adev->usec_timeout)
 201                 r = -ETIMEDOUT;
 202
 203         return r;
 204 }
 205
 206 /**
 207  * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg
 208  *
 209  * @adev: amdgpu_device pointer
 210  * @ring: ring we should submit the msg to
 211  * @handle: session handle to use
 212  * @fence: optional fence to return
 213  *
 214  * Open up a stream for HW test
 215  */
 216 static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 217                                        struct dma_fence **fence)
 218 {
 219         const unsigned ib_size_dw = 16;
 220         struct amdgpu_job *job;
 221         struct amdgpu_ib *ib;
 222         struct dma_fence *f = NULL;
 223         uint64_t dummy;
 224         int i, r;
 225
 226         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 227         if (r)
 228                 return r;
 229
 230         ib = &job->ibs[0];
 231         dummy = ib->gpu_addr + 1024;
 232
 233         ib->length_dw = 0;
 234         ib->ptr[ib->length_dw++] = 0x00000018;
 235         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 236         ib->ptr[ib->length_dw++] = handle;
 237         ib->ptr[ib->length_dw++] = 0x00000000;
 238         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 239         ib->ptr[ib->length_dw++] = dummy;
 240
 241         ib->ptr[ib->length_dw++] = 0x00000014;
 242         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 243         ib->ptr[ib->length_dw++] = 0x0000001c;
 244         ib->ptr[ib->length_dw++] = 0x00000000;
 245         ib->ptr[ib->length_dw++] = 0x00000000;
 246
 247         ib->ptr[ib->length_dw++] = 0x00000008;
 248         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 249
 250         for (i = ib->length_dw; i < ib_size_dw; ++i)
 251                 ib->ptr[i] = 0x0;
 252
 253         r = amdgpu_job_submit_direct(job, ring, &f);
 254         if (r)
 255                 goto err;
 256
 257         if (fence)
 258                 *fence = dma_fence_get(f);
 259         dma_fence_put(f);
 260         return 0;
 261
 262 err:
 263         amdgpu_job_free(job);
 264         return r;
 265 }
 266
 267 /**
 268  * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
 269  *
 270  * @adev: amdgpu_device pointer
 271  * @ring: ring we should submit the msg to
 272  * @handle: session handle to use
 273  * @fence: optional fence to return
 274  *
 275  * Close up a stream for HW test or if userspace failed to do so
 276  */
 277 static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 278                                 struct dma_fence **fence)
 279 {
 280         const unsigned ib_size_dw = 16;
 281         struct amdgpu_job *job;
 282         struct amdgpu_ib *ib;
 283         struct dma_fence *f = NULL;
 284         uint64_t dummy;
 285         int i, r;
 286
 287         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 288         if (r)
 289                 return r;
 290
 291         ib = &job->ibs[0];
 292         dummy = ib->gpu_addr + 1024;
 293
 294         ib->length_dw = 0;
 295         ib->ptr[ib->length_dw++] = 0x00000018;
 296         ib->ptr[ib->length_dw++] = 0x00000001;
 297         ib->ptr[ib->length_dw++] = handle;
 298         ib->ptr[ib->length_dw++] = 0x00000000;
 299         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 300         ib->ptr[ib->length_dw++] = dummy;
 301
 302         ib->ptr[ib->length_dw++] = 0x00000014;
 303         ib->ptr[ib->length_dw++] = 0x00000002;
 304         ib->ptr[ib->length_dw++] = 0x0000001c;
 305         ib->ptr[ib->length_dw++] = 0x00000000;
 306         ib->ptr[ib->length_dw++] = 0x00000000;
 307
 308         ib->ptr[ib->length_dw++] = 0x00000008;
 309         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 310
 311         for (i = ib->length_dw; i < ib_size_dw; ++i)
 312                 ib->ptr[i] = 0x0;
 313
 314         r = amdgpu_job_submit_direct(job, ring, &f);
 315         if (r)
 316                 goto err;
 317
 318         if (fence)
 319                 *fence = dma_fence_get(f);
 320         dma_fence_put(f);
 321         return 0;
 322
 323 err:
 324         amdgpu_job_free(job);
 325         return r;
 326 }
 327
 328 /**
 329  * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working
 330  *
 331  * @ring: the engine to test on
 332  *
 333  */
 334 static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 335 {
 336         struct dma_fence *fence = NULL;
 337         long r;
 338
 339         r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL);
 340         if (r)
 341                 goto error;
 342
 343         r = uvd_v7_0_enc_get_destroy_msg(ring, 1, &fence);
 344         if (r)
 345                 goto error;
 346
 347         r = dma_fence_wait_timeout(fence, false, timeout);
 348         if (r == 0)
 349                 r = -ETIMEDOUT;
 350         else if (r > 0)
 351                 r = 0;
 352
 353 error:
 354         dma_fence_put(fence);
 355         return r;
 356 }
 357
 358 static int uvd_v7_0_early_init(void *handle)
 359 {
 360         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 361
 362         if (adev->asic_type == CHIP_VEGA20) {
 363                 u32 harvest;
 364                 int i;
 365
 366                 adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20;
 367                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 368                         harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING);
 369                         if (harvest & UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK) {
 370                                 adev->uvd.harvest_config |= 1 << i;
 371                         }
 372                 }
 373                 if (adev->uvd.harvest_config == (AMDGPU_UVD_HARVEST_UVD0 |
 374                                                  AMDGPU_UVD_HARVEST_UVD1))
 375                         /* both instances are harvested, disable the block */
 376                         return -ENOENT;
 377         } else {
 378                 adev->uvd.num_uvd_inst = 1;
 379         }
 380
 381         if (amdgpu_sriov_vf(adev))
 382                 adev->uvd.num_enc_rings = 1;
 383         else
 384                 adev->uvd.num_enc_rings = 2;
 385         uvd_v7_0_set_ring_funcs(adev);
 386         uvd_v7_0_set_enc_ring_funcs(adev);
 387         uvd_v7_0_set_irq_funcs(adev);
 388
 389         return 0;
 390 }
 391
 392 static int uvd_v7_0_sw_init(void *handle)
 393 {
 394         struct amdgpu_ring *ring;
 395
 396         int i, j, r;
 397         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 398
 399         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 400                 if (adev->uvd.harvest_config & (1 << j))
 401                         continue;
 402                 /* UVD TRAP */
 403                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq);
 404                 if (r)
 405                         return r;
 406
 407                 /* UVD ENC TRAP */
 408                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 409                         r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq);
 410                         if (r)
 411                                 return r;
 412                 }
 413         }
 414
 415         r = amdgpu_uvd_sw_init(adev);
 416         if (r)
 417                 return r;
 418
 419         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 420                 const struct common_firmware_header *hdr;
 421                 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 422                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD;
 423                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;
 424                 adev->firmware.fw_size +=
 425                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 426
 427                 if (adev->uvd.num_uvd_inst == UVD7_MAX_HW_INSTANCES_VEGA20) {
 428                         adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].ucode_id = AMDGPU_UCODE_ID_UVD1;
 429                         adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].fw = adev->uvd.fw;
 430                         adev->firmware.fw_size +=
 431                                 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 432                 }
 433                 DRM_INFO("PSP loading UVD firmware\n");
 434         }
 435
 436         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 437                 if (adev->uvd.harvest_config & (1 << j))
 438                         continue;
 439                 if (!amdgpu_sriov_vf(adev)) {
 440                         ring = &adev->uvd.inst[j].ring;
 441                         sprintf(ring->name, "uvd_%d", ring->me);
 442                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
 443                         if (r)
 444                                 return r;
 445                 }
 446
 447                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 448                         ring = &adev->uvd.inst[j].ring_enc[i];
 449                         sprintf(ring->name, "uvd_enc_%d.%d", ring->me, i);
 450                         if (amdgpu_sriov_vf(adev)) {
 451                                 ring->use_doorbell = true;
 452
 453                                 /* currently only use the first enconding ring for
 454                                  * sriov, so set unused location for other unused rings.
 455                                  */
 456                                 if (i == 0)
 457                                         ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring0_1 * 2;
 458                                 else
 459                                         ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring2_3 * 2 + 1;
 460                         }
 461                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
 462                         if (r)
 463                                 return r;
 464                 }
 465         }
 466
 467         r = amdgpu_uvd_resume(adev);
 468         if (r)
 469                 return r;
 470
 471         r = amdgpu_uvd_entity_init(adev);
 472         if (r)
 473                 return r;
 474
 475         r = amdgpu_virt_alloc_mm_table(adev);
 476         if (r)
 477                 return r;
 478
 479         return r;
 480 }
 481
 482 static int uvd_v7_0_sw_fini(void *handle)
 483 {
 484         int i, j, r;
 485         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 486
 487         amdgpu_virt_free_mm_table(adev);
 488
 489         r = amdgpu_uvd_suspend(adev);
 490         if (r)
 491                 return r;
 492
 493         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 494                 if (adev->uvd.harvest_config & (1 << j))
 495                         continue;
 496                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 497                         amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
 498         }
 499         return amdgpu_uvd_sw_fini(adev);
 500 }
 501
 502 /**
 503  * uvd_v7_0_hw_init - start and test UVD block
 504  *
 505  * @adev: amdgpu_device pointer
 506  *
 507  * Initialize the hardware, boot up the VCPU and do some testing
 508  */
 509 static int uvd_v7_0_hw_init(void *handle)
 510 {
 511         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 512         struct amdgpu_ring *ring;
 513         uint32_t tmp;
 514         int i, j, r;
 515
 516         if (amdgpu_sriov_vf(adev))
 517                 r = uvd_v7_0_sriov_start(adev);
 518         else
 519                 r = uvd_v7_0_start(adev);
 520         if (r)
 521                 goto done;
 522
 523         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 524                 if (adev->uvd.harvest_config & (1 << j))
 525                         continue;
 526                 ring = &adev->uvd.inst[j].ring;
 527
 528                 if (!amdgpu_sriov_vf(adev)) {
 529                         r = amdgpu_ring_test_helper(ring);
 530                         if (r)
 531                                 goto done;
 532
 533                         r = amdgpu_ring_alloc(ring, 10);
 534                         if (r) {
 535                                 DRM_ERROR("amdgpu: (%d)ring failed to lock UVD ring (%d).\n", j, r);
 536                                 goto done;
 537                         }
 538
 539                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 540                                 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);
 541                         amdgpu_ring_write(ring, tmp);
 542                         amdgpu_ring_write(ring, 0xFFFFF);
 543
 544                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 545                                 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);
 546                         amdgpu_ring_write(ring, tmp);
 547                         amdgpu_ring_write(ring, 0xFFFFF);
 548
 549                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 550                                 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);
 551                         amdgpu_ring_write(ring, tmp);
 552                         amdgpu_ring_write(ring, 0xFFFFF);
 553
 554                         /* Clear timeout status bits */
 555                         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
 556                                 mmUVD_SEMA_TIMEOUT_STATUS), 0));
 557                         amdgpu_ring_write(ring, 0x8);
 558
 559                         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
 560                                 mmUVD_SEMA_CNTL), 0));
 561                         amdgpu_ring_write(ring, 3);
 562
 563                         amdgpu_ring_commit(ring);
 564                 }
 565
 566                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 567                         ring = &adev->uvd.inst[j].ring_enc[i];
 568                         r = amdgpu_ring_test_helper(ring);
 569                         if (r)
 570                                 goto done;
 571                 }
 572         }
 573 done:
 574         if (!r)
 575                 DRM_INFO("UVD and UVD ENC initialized successfully.\n");
 576
 577         return r;
 578 }
 579
 580 /**
 581  * uvd_v7_0_hw_fini - stop the hardware block
 582  *
 583  * @adev: amdgpu_device pointer
 584  *
 585  * Stop the UVD block, mark ring as not ready any more
 586  */
 587 static int uvd_v7_0_hw_fini(void *handle)
 588 {
 589         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 590         int i;
 591
 592         if (!amdgpu_sriov_vf(adev))
 593                 uvd_v7_0_stop(adev);
 594         else {
 595                 /* full access mode, so don't touch any UVD register */
 596                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
 597         }
 598
 599         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 600                 if (adev->uvd.harvest_config & (1 << i))
 601                         continue;
 602                 adev->uvd.inst[i].ring.sched.ready = false;
 603         }
 604
 605         return 0;
 606 }
 607
 608 static int uvd_v7_0_suspend(void *handle)
 609 {
 610         int r;
 611         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 612
 613         r = uvd_v7_0_hw_fini(adev);
 614         if (r)
 615                 return r;
 616
 617         return amdgpu_uvd_suspend(adev);
 618 }
 619
 620 static int uvd_v7_0_resume(void *handle)
 621 {
 622         int r;
 623         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 624
 625         r = amdgpu_uvd_resume(adev);
 626         if (r)
 627                 return r;
 628
 629         return uvd_v7_0_hw_init(adev);
 630 }
 631
 632 /**
 633  * uvd_v7_0_mc_resume - memory controller programming
 634  *
 635  * @adev: amdgpu_device pointer
 636  *
 637  * Let the UVD memory controller know it's offsets
 638  */
 639 static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
 640 {
 641         uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
 642         uint32_t offset;
 643         int i;
 644
 645         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 646                 if (adev->uvd.harvest_config & (1 << i))
 647                         continue;
 648                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 649                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 650                                 i == 0 ?
 651                                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo:
 652                                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_lo);
 653                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 654                                 i == 0 ?
 655                                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi:
 656                                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_hi);
 657                         WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
 658                         offset = 0;
 659                 } else {
 660                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 661                                 lower_32_bits(adev->uvd.inst[i].gpu_addr));
 662                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 663                                 upper_32_bits(adev->uvd.inst[i].gpu_addr));
 664                         offset = size;
 665                         WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
 666                                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 667                 }
 668
 669                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
 670
 671                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 672                                 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 673                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 674                                 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 675                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21));
 676                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE);
 677
 678                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 679                                 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 680                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 681                                 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 682                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));
 683                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2,
 684                                 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 685
 686                 WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG,
 687                                 adev->gfx.config.gb_addr_config);
 688                 WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG,
 689                                 adev->gfx.config.gb_addr_config);
 690                 WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG,
 691                                 adev->gfx.config.gb_addr_config);
 692
 693                 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 694         }
 695 }
 696
 697 static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
 698                                 struct amdgpu_mm_table *table)
 699 {
 700         uint32_t data = 0, loop;
 701         uint64_t addr = table->gpu_addr;
 702         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr;
 703         uint32_t size;
 704         int i;
 705
 706         size = header->header_size + header->vce_table_size + header->uvd_table_size;
 707
 708         /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */
 709         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
 710         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
 711
 712         /* 2, update vmid of descriptor */
 713         data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID);
 714         data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK;
 715         data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */
 716         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data);
 717
 718         /* 3, notify mmsch about the size of this descriptor */
 719         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size);
 720
 721         /* 4, set resp to zero */
 722         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
 723
 724         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 725                 if (adev->uvd.harvest_config & (1 << i))
 726                         continue;
 727                 WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0);
 728                 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0;
 729                 adev->uvd.inst[i].ring_enc[0].wptr = 0;
 730                 adev->uvd.inst[i].ring_enc[0].wptr_old = 0;
 731         }
 732         /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
 733         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001);
 734
 735         data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
 736         loop = 1000;
 737         while ((data & 0x10000002) != 0x10000002) {
 738                 udelay(10);
 739                 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
 740                 loop--;
 741                 if (!loop)
 742                         break;
 743         }
 744
 745         if (!loop) {
 746                 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
 747                 return -EBUSY;
 748         }
 749
 750         return 0;
 751 }
 752
 753 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
 754 {
 755         struct amdgpu_ring *ring;
 756         uint32_t offset, size, tmp;
 757         uint32_t table_size = 0;
 758         struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} };
 759         struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
 760         struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} };
 761         struct mmsch_v1_0_cmd_end end = { {0} };
 762         uint32_t *init_table = adev->virt.mm_table.cpu_addr;
 763         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table;
 764         uint8_t i = 0;
 765
 766         direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
 767         direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
 768         direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING;
 769         end.cmd_header.command_type = MMSCH_COMMAND__END;
 770
 771         if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) {
 772                 header->version = MMSCH_VERSION;
 773                 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2;
 774
 775                 if (header->vce_table_offset == 0 && header->vce_table_size == 0)
 776                         header->uvd_table_offset = header->header_size;
 777                 else
 778                         header->uvd_table_offset = header->vce_table_size + header->vce_table_offset;
 779
 780                 init_table += header->uvd_table_offset;
 781
 782                 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 783                         if (adev->uvd.harvest_config & (1 << i))
 784                                 continue;
 785                         ring = &adev->uvd.inst[i].ring;
 786                         ring->wptr = 0;
 787                         size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 788
 789                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
 790                                                            0xFFFFFFFF, 0x00000004);
 791                         /* mc resume*/
 792                         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 793                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i,
 794                                                         mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 795                                                         adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo);
 796                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i,
 797                                                         mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 798                                                         adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi);
 799                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0);
 800                                 offset = 0;
 801                         } else {
 802                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 803                                                             lower_32_bits(adev->uvd.inst[i].gpu_addr));
 804                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 805                                                             upper_32_bits(adev->uvd.inst[i].gpu_addr));
 806                                 offset = size;
 807                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
 808                                                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 809
 810                         }
 811
 812                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size);
 813
 814                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 815                                                     lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 816                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 817                                                     upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 818                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
 819                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
 820
 821                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 822                                                     lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 823                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 824                                                     upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 825                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
 826                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
 827                                                     AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 828
 829                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
 830                         /* mc resume end*/
 831
 832                         /* disable clock gating */
 833                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL),
 834                                                            ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0);
 835
 836                         /* disable interupt */
 837                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
 838                                                            ~UVD_MASTINT_EN__VCPU_EN_MASK, 0);
 839
 840                         /* stall UMC and register bus before resetting VCPU */
 841                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
 842                                                            ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 843                                                            UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 844
 845                         /* put LMI, VCPU, RBC etc... into reset */
 846                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
 847                                                     (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 848                                                                UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 849                                                                UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 850                                                                UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 851                                                                UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 852                                                                UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 853                                                                UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 854                                                                UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK));
 855
 856                         /* initialize UVD memory controller */
 857                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL),
 858                                                     (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 859                                                                UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 860                                                                UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 861                                                                UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 862                                                                UVD_LMI_CTRL__REQ_MODE_MASK |
 863                                                                0x00100000L));
 864
 865                         /* take all subblocks out of reset, except VCPU */
 866                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
 867                                                     UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 868
 869                         /* enable VCPU clock */
 870                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
 871                                                     UVD_VCPU_CNTL__CLK_EN_MASK);
 872
 873                         /* enable master interrupt */
 874                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
 875                                                            ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 876                                                            (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 877
 878                         /* clear the bit 4 of UVD_STATUS */
 879                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
 880                                                            ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0);
 881
 882                         /* force RBC into idle state */
 883                         size = order_base_2(ring->ring_size);
 884                         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
 885                         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 886                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
 887
 888                         ring = &adev->uvd.inst[i].ring_enc[0];
 889                         ring->wptr = 0;
 890                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr);
 891                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
 892                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4);
 893
 894                         /* boot up the VCPU */
 895                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0);
 896
 897                         /* enable UMC */
 898                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
 899                                                                                            ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
 900
 901                         MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02);
 902                 }
 903                 /* add end packet */
 904                 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
 905                 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
 906                 header->uvd_table_size = table_size;
 907
 908         }
 909         return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table);
 910 }
 911
 912 /**
 913  * uvd_v7_0_start - start UVD block
 914  *
 915  * @adev: amdgpu_device pointer
 916  *
 917  * Setup and start the UVD block
 918  */
 919 static int uvd_v7_0_start(struct amdgpu_device *adev)
 920 {
 921         struct amdgpu_ring *ring;
 922         uint32_t rb_bufsz, tmp;
 923         uint32_t lmi_swap_cntl;
 924         uint32_t mp_swap_cntl;
 925         int i, j, k, r;
 926
 927         for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
 928                 if (adev->uvd.harvest_config & (1 << k))
 929                         continue;
 930                 /* disable DPG */
 931                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,
 932                                 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 933         }
 934
 935         /* disable byte swapping */
 936         lmi_swap_cntl = 0;
 937         mp_swap_cntl = 0;
 938
 939         uvd_v7_0_mc_resume(adev);
 940
 941         for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
 942                 if (adev->uvd.harvest_config & (1 << k))
 943                         continue;
 944                 ring = &adev->uvd.inst[k].ring;
 945                 /* disable clock gating */
 946                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0,
 947                                 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK);
 948
 949                 /* disable interupt */
 950                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,
 951                                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
 952
 953                 /* stall UMC and register bus before resetting VCPU */
 954                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2),
 955                                 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 956                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 957                 mdelay(1);
 958
 959                 /* put LMI, VCPU, RBC etc... into reset */
 960                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
 961                         UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 962                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 963                         UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 964                         UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 965                         UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 966                         UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 967                         UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 968                         UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 969                 mdelay(5);
 970
 971                 /* initialize UVD memory controller */
 972                 WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL,
 973                         (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 974                         UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 975                         UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 976                         UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 977                         UVD_LMI_CTRL__REQ_MODE_MASK |
 978                         0x00100000L);
 979
 980 #ifdef __BIG_ENDIAN
 981                 /* swap (8 in 32) RB and IB */
 982                 lmi_swap_cntl = 0xa;
 983                 mp_swap_cntl = 0;
 984 #endif
 985                 WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 986                 WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 987
 988                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040);
 989                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0);
 990                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040);
 991                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0);
 992                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0);
 993                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88);
 994
 995                 /* take all subblocks out of reset, except VCPU */
 996                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
 997                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 998                 mdelay(5);
 999
1000                 /* enable VCPU clock */
1001                 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL,
1002                                 UVD_VCPU_CNTL__CLK_EN_MASK);
1003
1004                 /* enable UMC */
1005                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0,
1006                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1007
1008                 /* boot up the VCPU */
1009                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0);
1010                 mdelay(10);
1011
1012                 for (i = 0; i < 10; ++i) {
1013                         uint32_t status;
1014
1015                         for (j = 0; j < 100; ++j) {
1016                                 status = RREG32_SOC15(UVD, k, mmUVD_STATUS);
1017                                 if (status & 2)
1018                                         break;
1019                                 mdelay(10);
1020                         }
1021                         r = 0;
1022                         if (status & 2)
1023                                 break;
1024
1025                         DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k);
1026                         WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET),
1027                                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1028                                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1029                         mdelay(10);
1030                         WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0,
1031                                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1032                         mdelay(10);
1033                         r = -1;
1034                 }
1035
1036                 if (r) {
1037                         DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k);
1038                         return r;
1039                 }
1040                 /* enable master interrupt */
1041                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),
1042                         (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
1043                         ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
1044
1045                 /* clear the bit 4 of UVD_STATUS */
1046                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,
1047                                 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1048
1049                 /* force RBC into idle state */
1050                 rb_bufsz = order_base_2(ring->ring_size);
1051                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1052                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1053                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1054                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
1055                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1056                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1057                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp);
1058
1059                 /* set the write pointer delay */
1060                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0);
1061
1062                 /* set the wb address */
1063                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR,
1064                                 (upper_32_bits(ring->gpu_addr) >> 2));
1065
1066                 /* programm the RB_BASE for ring buffer */
1067                 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1068                                 lower_32_bits(ring->gpu_addr));
1069                 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1070                                 upper_32_bits(ring->gpu_addr));
1071
1072                 /* Initialize the ring buffer's read and write pointers */
1073                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0);
1074
1075                 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);
1076                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR,
1077                                 lower_32_bits(ring->wptr));
1078
1079                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0,
1080                                 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1081
1082                 ring = &adev->uvd.inst[k].ring_enc[0];
1083                 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1084                 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1085                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr);
1086                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1087                 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4);
1088
1089                 ring = &adev->uvd.inst[k].ring_enc[1];
1090                 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1091                 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1092                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1093                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1094                 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4);
1095         }
1096         return 0;
1097 }
1098
1099 /**
1100  * uvd_v7_0_stop - stop UVD block
1101  *
1102  * @adev: amdgpu_device pointer
1103  *
1104  * stop the UVD block
1105  */
1106 static void uvd_v7_0_stop(struct amdgpu_device *adev)
1107 {
1108         uint8_t i = 0;
1109
1110         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
1111                 if (adev->uvd.harvest_config & (1 << i))
1112                         continue;
1113                 /* force RBC into idle state */
1114                 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101);
1115
1116                 /* Stall UMC and register bus before resetting VCPU */
1117                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
1118                                 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1119                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1120                 mdelay(1);
1121
1122                 /* put VCPU into reset */
1123                 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET,
1124                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1125                 mdelay(5);
1126
1127                 /* disable VCPU clock */
1128                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0);
1129
1130                 /* Unstall UMC and register bus */
1131                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
1132                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1133         }
1134 }
1135
1136 /**
1137  * uvd_v7_0_ring_emit_fence - emit an fence & trap command
1138  *
1139  * @ring: amdgpu_ring pointer
1140  * @fence: fence to emit
1141  *
1142  * Write a fence and a trap command to the ring.
1143  */
1144 static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1145                                      unsigned flags)
1146 {
1147         struct amdgpu_device *adev = ring->adev;
1148
1149         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1150
1151         amdgpu_ring_write(ring,
1152                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1153         amdgpu_ring_write(ring, seq);
1154         amdgpu_ring_write(ring,
1155                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1156         amdgpu_ring_write(ring, addr & 0xffffffff);
1157         amdgpu_ring_write(ring,
1158                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1159         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1160         amdgpu_ring_write(ring,
1161                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1162         amdgpu_ring_write(ring, 0);
1163
1164         amdgpu_ring_write(ring,
1165                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1166         amdgpu_ring_write(ring, 0);
1167         amdgpu_ring_write(ring,
1168                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1169         amdgpu_ring_write(ring, 0);
1170         amdgpu_ring_write(ring,
1171                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1172         amdgpu_ring_write(ring, 2);
1173 }
1174
1175 /**
1176  * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command
1177  *
1178  * @ring: amdgpu_ring pointer
1179  * @fence: fence to emit
1180  *
1181  * Write enc a fence and a trap command to the ring.
1182  */
1183 static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1184                         u64 seq, unsigned flags)
1185 {
1186
1187         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1188
1189         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
1190         amdgpu_ring_write(ring, addr);
1191         amdgpu_ring_write(ring, upper_32_bits(addr));
1192         amdgpu_ring_write(ring, seq);
1193         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
1194 }
1195
1196 /**
1197  * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing
1198  *
1199  * @ring: amdgpu_ring pointer
1200  */
1201 static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1202 {
1203         /* The firmware doesn't seem to like touching registers at this point. */
1204 }
1205
1206 /**
1207  * uvd_v7_0_ring_test_ring - register write test
1208  *
1209  * @ring: amdgpu_ring pointer
1210  *
1211  * Test if we can successfully write to the context register
1212  */
1213 static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1214 {
1215         struct amdgpu_device *adev = ring->adev;
1216         uint32_t tmp = 0;
1217         unsigned i;
1218         int r;
1219
1220         WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD);
1221         r = amdgpu_ring_alloc(ring, 3);
1222         if (r)
1223                 return r;
1224
1225         amdgpu_ring_write(ring,
1226                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1227         amdgpu_ring_write(ring, 0xDEADBEEF);
1228         amdgpu_ring_commit(ring);
1229         for (i = 0; i < adev->usec_timeout; i++) {
1230                 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID);
1231                 if (tmp == 0xDEADBEEF)
1232                         break;
1233                 DRM_UDELAY(1);
1234         }
1235
1236         if (i >= adev->usec_timeout)
1237                 r = -ETIMEDOUT;
1238
1239         return r;
1240 }
1241
1242 /**
1243  * uvd_v7_0_ring_patch_cs_in_place - Patch the IB for command submission.
1244  *
1245  * @p: the CS parser with the IBs
1246  * @ib_idx: which IB to patch
1247  *
1248  */
1249 static int uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
1250                                            uint32_t ib_idx)
1251 {
1252         struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
1253         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
1254         unsigned i;
1255
1256         /* No patching necessary for the first instance */
1257         if (!ring->me)
1258                 return 0;
1259
1260         for (i = 0; i < ib->length_dw; i += 2) {
1261                 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i);
1262
1263                 reg -= p->adev->reg_offset[UVD_HWIP][0][1];
1264                 reg += p->adev->reg_offset[UVD_HWIP][1][1];
1265
1266                 amdgpu_set_ib_value(p, ib_idx, i, reg);
1267         }
1268         return 0;
1269 }
1270
1271 /**
1272  * uvd_v7_0_ring_emit_ib - execute indirect buffer
1273  *
1274  * @ring: amdgpu_ring pointer
1275  * @ib: indirect buffer to execute
1276  *
1277  * Write ring commands to execute the indirect buffer
1278  */
1279 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
1280                                   struct amdgpu_job *job,
1281                                   struct amdgpu_ib *ib,
1282                                   uint32_t flags)
1283 {
1284         struct amdgpu_device *adev = ring->adev;
1285         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1286
1287         amdgpu_ring_write(ring,
1288                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0));
1289         amdgpu_ring_write(ring, vmid);
1290
1291         amdgpu_ring_write(ring,
1292                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1293         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1294         amdgpu_ring_write(ring,
1295                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1296         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1297         amdgpu_ring_write(ring,
1298                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));
1299         amdgpu_ring_write(ring, ib->length_dw);
1300 }
1301
1302 /**
1303  * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer
1304  *
1305  * @ring: amdgpu_ring pointer
1306  * @ib: indirect buffer to execute
1307  *
1308  * Write enc ring commands to execute the indirect buffer
1309  */
1310 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1311                                         struct amdgpu_job *job,
1312                                         struct amdgpu_ib *ib,
1313                                         uint32_t flags)
1314 {
1315         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1316
1317         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1318         amdgpu_ring_write(ring, vmid);
1319         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1320         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1321         amdgpu_ring_write(ring, ib->length_dw);
1322 }
1323
1324 static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
1325                                     uint32_t reg, uint32_t val)
1326 {
1327         struct amdgpu_device *adev = ring->adev;
1328
1329         amdgpu_ring_write(ring,
1330                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1331         amdgpu_ring_write(ring, reg << 2);
1332         amdgpu_ring_write(ring,
1333                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1334         amdgpu_ring_write(ring, val);
1335         amdgpu_ring_write(ring,
1336                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1337         amdgpu_ring_write(ring, 8);
1338 }
1339
1340 static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1341                                         uint32_t val, uint32_t mask)
1342 {
1343         struct amdgpu_device *adev = ring->adev;
1344
1345         amdgpu_ring_write(ring,
1346                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1347         amdgpu_ring_write(ring, reg << 2);
1348         amdgpu_ring_write(ring,
1349                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1350         amdgpu_ring_write(ring, val);
1351         amdgpu_ring_write(ring,
1352                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0));
1353         amdgpu_ring_write(ring, mask);
1354         amdgpu_ring_write(ring,
1355                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1356         amdgpu_ring_write(ring, 12);
1357 }
1358
1359 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1360                                         unsigned vmid, uint64_t pd_addr)
1361 {
1362         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1363         uint32_t data0, data1, mask;
1364
1365         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1366
1367         /* wait for reg writes */
1368         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1369         data1 = lower_32_bits(pd_addr);
1370         mask = 0xffffffff;
1371         uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask);
1372 }
1373
1374 static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1375 {
1376         struct amdgpu_device *adev = ring->adev;
1377         int i;
1378
1379         WARN_ON(ring->wptr % 2 || count % 2);
1380
1381         for (i = 0; i < count / 2; i++) {
1382                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));
1383                 amdgpu_ring_write(ring, 0);
1384         }
1385 }
1386
1387 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1388 {
1389         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1390 }
1391
1392 static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1393                                             uint32_t reg, uint32_t val,
1394                                             uint32_t mask)
1395 {
1396         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1397         amdgpu_ring_write(ring, reg << 2);
1398         amdgpu_ring_write(ring, mask);
1399         amdgpu_ring_write(ring, val);
1400 }
1401
1402 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1403                                             unsigned int vmid, uint64_t pd_addr)
1404 {
1405         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1406
1407         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1408
1409         /* wait for reg writes */
1410         uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1411                                         lower_32_bits(pd_addr), 0xffffffff);
1412 }
1413
1414 static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1415                                         uint32_t reg, uint32_t val)
1416 {
1417         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1418         amdgpu_ring_write(ring, reg << 2);
1419         amdgpu_ring_write(ring, val);
1420 }
1421
1422 #if 0
1423 static bool uvd_v7_0_is_idle(void *handle)
1424 {
1425         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1426
1427         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1428 }
1429
1430 static int uvd_v7_0_wait_for_idle(void *handle)
1431 {
1432         unsigned i;
1433         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1434
1435         for (i = 0; i < adev->usec_timeout; i++) {
1436                 if (uvd_v7_0_is_idle(handle))
1437                         return 0;
1438         }
1439         return -ETIMEDOUT;
1440 }
1441
1442 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
1443 static bool uvd_v7_0_check_soft_reset(void *handle)
1444 {
1445         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1446         u32 srbm_soft_reset = 0;
1447         u32 tmp = RREG32(mmSRBM_STATUS);
1448
1449         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1450             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1451             (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
1452                     AMDGPU_UVD_STATUS_BUSY_MASK))
1453                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1454                                 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1455
1456         if (srbm_soft_reset) {
1457                 adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset;
1458                 return true;
1459         } else {
1460                 adev->uvd.inst[ring->me].srbm_soft_reset = 0;
1461                 return false;
1462         }
1463 }
1464
1465 static int uvd_v7_0_pre_soft_reset(void *handle)
1466 {
1467         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1468
1469         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1470                 return 0;
1471
1472         uvd_v7_0_stop(adev);
1473         return 0;
1474 }
1475
1476 static int uvd_v7_0_soft_reset(void *handle)
1477 {
1478         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1479         u32 srbm_soft_reset;
1480
1481         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1482                 return 0;
1483         srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset;
1484
1485         if (srbm_soft_reset) {
1486                 u32 tmp;
1487
1488                 tmp = RREG32(mmSRBM_SOFT_RESET);
1489                 tmp |= srbm_soft_reset;
1490                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1491                 WREG32(mmSRBM_SOFT_RESET, tmp);
1492                 tmp = RREG32(mmSRBM_SOFT_RESET);
1493
1494                 udelay(50);
1495
1496                 tmp &= ~srbm_soft_reset;
1497                 WREG32(mmSRBM_SOFT_RESET, tmp);
1498                 tmp = RREG32(mmSRBM_SOFT_RESET);
1499
1500                 /* Wait a little for things to settle down */
1501                 udelay(50);
1502         }
1503
1504         return 0;
1505 }
1506
1507 static int uvd_v7_0_post_soft_reset(void *handle)
1508 {
1509         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1510
1511         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1512                 return 0;
1513
1514         mdelay(5);
1515
1516         return uvd_v7_0_start(adev);
1517 }
1518 #endif
1519
1520 static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev,
1521                                         struct amdgpu_irq_src *source,
1522                                         unsigned type,
1523                                         enum amdgpu_interrupt_state state)
1524 {
1525         // TODO
1526         return 0;
1527 }
1528
1529 static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev,
1530                                       struct amdgpu_irq_src *source,
1531                                       struct amdgpu_iv_entry *entry)
1532 {
1533         uint32_t ip_instance;
1534
1535         switch (entry->client_id) {
1536         case SOC15_IH_CLIENTID_UVD:
1537                 ip_instance = 0;
1538                 break;
1539         case SOC15_IH_CLIENTID_UVD1:
1540                 ip_instance = 1;
1541                 break;
1542         default:
1543                 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
1544                 return 0;
1545         }
1546
1547         DRM_DEBUG("IH: UVD TRAP\n");
1548
1549         switch (entry->src_id) {
1550         case 124:
1551                 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring);
1552                 break;
1553         case 119:
1554                 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]);
1555                 break;
1556         case 120:
1557                 if (!amdgpu_sriov_vf(adev))
1558                         amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]);
1559                 break;
1560         default:
1561                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1562                           entry->src_id, entry->src_data[0]);
1563                 break;
1564         }
1565
1566         return 0;
1567 }
1568
1569 #if 0
1570 static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev)
1571 {
1572         uint32_t data, data1, data2, suvd_flags;
1573
1574         data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1575         data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1576         data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);
1577
1578         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1579                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1580
1581         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1582                      UVD_SUVD_CGC_GATE__SIT_MASK |
1583                      UVD_SUVD_CGC_GATE__SMP_MASK |
1584                      UVD_SUVD_CGC_GATE__SCM_MASK |
1585                      UVD_SUVD_CGC_GATE__SDB_MASK;
1586
1587         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1588                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1589                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1590
1591         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1592                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1593                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1594                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1595                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1596                         UVD_CGC_CTRL__SYS_MODE_MASK |
1597                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1598                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1599                         UVD_CGC_CTRL__REGS_MODE_MASK |
1600                         UVD_CGC_CTRL__RBC_MODE_MASK |
1601                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1602                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1603                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1604                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1605                         UVD_CGC_CTRL__MPC_MODE_MASK |
1606                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1607                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1608                         UVD_CGC_CTRL__WCB_MODE_MASK |
1609                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1610                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1611                         UVD_CGC_CTRL__JPEG2_MODE_MASK |
1612                         UVD_CGC_CTRL__SCPU_MODE_MASK);
1613         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1614                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1615                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1616                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1617                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1618         data1 |= suvd_flags;
1619
1620         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
1621         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0);
1622         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1623         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);
1624 }
1625
1626 static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev)
1627 {
1628         uint32_t data, data1, cgc_flags, suvd_flags;
1629
1630         data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE);
1631         data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1632
1633         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1634                 UVD_CGC_GATE__UDEC_MASK |
1635                 UVD_CGC_GATE__MPEG2_MASK |
1636                 UVD_CGC_GATE__RBC_MASK |
1637                 UVD_CGC_GATE__LMI_MC_MASK |
1638                 UVD_CGC_GATE__IDCT_MASK |
1639                 UVD_CGC_GATE__MPRD_MASK |
1640                 UVD_CGC_GATE__MPC_MASK |
1641                 UVD_CGC_GATE__LBSI_MASK |
1642                 UVD_CGC_GATE__LRBBM_MASK |
1643                 UVD_CGC_GATE__UDEC_RE_MASK |
1644                 UVD_CGC_GATE__UDEC_CM_MASK |
1645                 UVD_CGC_GATE__UDEC_IT_MASK |
1646                 UVD_CGC_GATE__UDEC_DB_MASK |
1647                 UVD_CGC_GATE__UDEC_MP_MASK |
1648                 UVD_CGC_GATE__WCB_MASK |
1649                 UVD_CGC_GATE__VCPU_MASK |
1650                 UVD_CGC_GATE__SCPU_MASK |
1651                 UVD_CGC_GATE__JPEG_MASK |
1652                 UVD_CGC_GATE__JPEG2_MASK;
1653
1654         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1655                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1656                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1657                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1658                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1659
1660         data |= cgc_flags;
1661         data1 |= suvd_flags;
1662
1663         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data);
1664         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1665 }
1666
1667 static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
1668 {
1669         u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
1670
1671         if (enable)
1672                 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1673                         GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1674         else
1675                 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1676                          GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1677
1678         WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
1679 }
1680
1681
1682 static int uvd_v7_0_set_clockgating_state(void *handle,
1683                                           enum amd_clockgating_state state)
1684 {
1685         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1686         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1687
1688         uvd_v7_0_set_bypass_mode(adev, enable);
1689
1690         if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
1691                 return 0;
1692
1693         if (enable) {
1694                 /* disable HW gating and enable Sw gating */
1695                 uvd_v7_0_set_sw_clock_gating(adev);
1696         } else {
1697                 /* wait for STATUS to clear */
1698                 if (uvd_v7_0_wait_for_idle(handle))
1699                         return -EBUSY;
1700
1701                 /* enable HW gates because UVD is idle */
1702                 /* uvd_v7_0_set_hw_clock_gating(adev); */
1703         }
1704
1705         return 0;
1706 }
1707
1708 static int uvd_v7_0_set_powergating_state(void *handle,
1709                                           enum amd_powergating_state state)
1710 {
1711         /* This doesn't actually powergate the UVD block.
1712          * That's done in the dpm code via the SMC.  This
1713          * just re-inits the block as necessary.  The actual
1714          * gating still happens in the dpm code.  We should
1715          * revisit this when there is a cleaner line between
1716          * the smc and the hw blocks
1717          */
1718         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1719
1720         if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
1721                 return 0;
1722
1723         WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1724
1725         if (state == AMD_PG_STATE_GATE) {
1726                 uvd_v7_0_stop(adev);
1727                 return 0;
1728         } else {
1729                 return uvd_v7_0_start(adev);
1730         }
1731 }
1732 #endif
1733
1734 static int uvd_v7_0_set_clockgating_state(void *handle,
1735                                           enum amd_clockgating_state state)
1736 {
1737         /* needed for driver unload*/
1738         return 0;
1739 }
1740
1741 const struct amd_ip_funcs uvd_v7_0_ip_funcs = {
1742         .name = "uvd_v7_0",
1743         .early_init = uvd_v7_0_early_init,
1744         .late_init = NULL,
1745         .sw_init = uvd_v7_0_sw_init,
1746         .sw_fini = uvd_v7_0_sw_fini,
1747         .hw_init = uvd_v7_0_hw_init,
1748         .hw_fini = uvd_v7_0_hw_fini,
1749         .suspend = uvd_v7_0_suspend,
1750         .resume = uvd_v7_0_resume,
1751         .is_idle = NULL /* uvd_v7_0_is_idle */,
1752         .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */,
1753         .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */,
1754         .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */,
1755         .soft_reset = NULL /* uvd_v7_0_soft_reset */,
1756         .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */,
1757         .set_clockgating_state = uvd_v7_0_set_clockgating_state,
1758         .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */,
1759 };
1760
1761 static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
1762         .type = AMDGPU_RING_TYPE_UVD,
1763         .align_mask = 0xf,
1764         .support_64bit_ptrs = false,
1765         .vmhub = AMDGPU_MMHUB,
1766         .get_rptr = uvd_v7_0_ring_get_rptr,
1767         .get_wptr = uvd_v7_0_ring_get_wptr,
1768         .set_wptr = uvd_v7_0_ring_set_wptr,
1769         .patch_cs_in_place = uvd_v7_0_ring_patch_cs_in_place,
1770         .emit_frame_size =
1771                 6 + /* hdp invalidate */
1772                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1773                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1774                 8 + /* uvd_v7_0_ring_emit_vm_flush */
1775                 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
1776         .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
1777         .emit_ib = uvd_v7_0_ring_emit_ib,
1778         .emit_fence = uvd_v7_0_ring_emit_fence,
1779         .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
1780         .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
1781         .test_ring = uvd_v7_0_ring_test_ring,
1782         .test_ib = amdgpu_uvd_ring_test_ib,
1783         .insert_nop = uvd_v7_0_ring_insert_nop,
1784         .pad_ib = amdgpu_ring_generic_pad_ib,
1785         .begin_use = amdgpu_uvd_ring_begin_use,
1786         .end_use = amdgpu_uvd_ring_end_use,
1787         .emit_wreg = uvd_v7_0_ring_emit_wreg,
1788         .emit_reg_wait = uvd_v7_0_ring_emit_reg_wait,
1789         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1790 };
1791
1792 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
1793         .type = AMDGPU_RING_TYPE_UVD_ENC,
1794         .align_mask = 0x3f,
1795         .nop = HEVC_ENC_CMD_NO_OP,
1796         .support_64bit_ptrs = false,
1797         .vmhub = AMDGPU_MMHUB,
1798         .get_rptr = uvd_v7_0_enc_ring_get_rptr,
1799         .get_wptr = uvd_v7_0_enc_ring_get_wptr,
1800         .set_wptr = uvd_v7_0_enc_ring_set_wptr,
1801         .emit_frame_size =
1802                 3 + 3 + /* hdp flush / invalidate */
1803                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1804                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1805                 4 + /* uvd_v7_0_enc_ring_emit_vm_flush */
1806                 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
1807                 1, /* uvd_v7_0_enc_ring_insert_end */
1808         .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */
1809         .emit_ib = uvd_v7_0_enc_ring_emit_ib,
1810         .emit_fence = uvd_v7_0_enc_ring_emit_fence,
1811         .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush,
1812         .test_ring = uvd_v7_0_enc_ring_test_ring,
1813         .test_ib = uvd_v7_0_enc_ring_test_ib,
1814         .insert_nop = amdgpu_ring_insert_nop,
1815         .insert_end = uvd_v7_0_enc_ring_insert_end,
1816         .pad_ib = amdgpu_ring_generic_pad_ib,
1817         .begin_use = amdgpu_uvd_ring_begin_use,
1818         .end_use = amdgpu_uvd_ring_end_use,
1819         .emit_wreg = uvd_v7_0_enc_ring_emit_wreg,
1820         .emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait,
1821         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1822 };
1823
1824 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
1825 {
1826         int i;
1827
1828         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
1829                 if (adev->uvd.harvest_config & (1 << i))
1830                         continue;
1831                 adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs;
1832                 adev->uvd.inst[i].ring.me = i;
1833                 DRM_INFO("UVD(%d) is enabled in VM mode\n", i);
1834         }
1835 }
1836
1837 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1838 {
1839         int i, j;
1840
1841         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
1842                 if (adev->uvd.harvest_config & (1 << j))
1843                         continue;
1844                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
1845                         adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;
1846                         adev->uvd.inst[j].ring_enc[i].me = j;
1847                 }
1848
1849                 DRM_INFO("UVD(%d) ENC is enabled in VM mode\n", j);
1850         }
1851 }
1852
1853 static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = {
1854         .set = uvd_v7_0_set_interrupt_state,
1855         .process = uvd_v7_0_process_interrupt,
1856 };
1857
1858 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1859 {
1860         int i;
1861
1862         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
1863                 if (adev->uvd.harvest_config & (1 << i))
1864                         continue;
1865                 adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1;
1866                 adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs;
1867         }
1868 }
1869
1870 const struct amdgpu_ip_block_version uvd_v7_0_ip_block =
1871 {
1872                 .type = AMD_IP_BLOCK_TYPE_UVD,
1873                 .major = 7,
1874                 .minor = 0,
1875                 .rev = 0,
1876                 .funcs = &uvd_v7_0_ip_funcs,
1877 };