2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
28 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_atombios.h"
32 #include "amdgpu_ih.h"
33 #include "amdgpu_uvd.h"
34 #include "amdgpu_vce.h"
35 #include "amdgpu_ucode.h"
36 #include "amdgpu_psp.h"
40 #include "uvd/uvd_7_0_offset.h"
41 #include "gc/gc_9_0_offset.h"
42 #include "gc/gc_9_0_sh_mask.h"
43 #include "sdma0/sdma0_4_0_offset.h"
44 #include "sdma1/sdma1_4_0_offset.h"
45 #include "nbio/nbio_7_0_default.h"
46 #include "nbio/nbio_7_0_offset.h"
47 #include "nbio/nbio_7_0_sh_mask.h"
48 #include "nbio/nbio_7_0_smn.h"
49 #include "mp/mp_9_0_offset.h"
52 #include "soc15_common.h"
55 #include "gfxhub_v1_0.h"
56 #include "mmhub_v1_0.h"
59 #include "nbio_v6_1.h"
60 #include "nbio_v7_0.h"
61 #include "nbio_v7_4.h"
63 #include "vega10_ih.h"
64 #include "vega20_ih.h"
65 #include "navi10_ih.h"
66 #include "sdma_v4_0.h"
71 #include "jpeg_v2_0.h"
73 #include "jpeg_v2_5.h"
74 #include "smuio_v9_0.h"
75 #include "smuio_v11_0.h"
76 #include "smuio_v13_0.h"
77 #include "dce_virtual.h"
79 #include "amdgpu_smu.h"
80 #include "amdgpu_ras.h"
81 #include "amdgpu_xgmi.h"
82 #include <uapi/linux/kfd_ioctl.h>
84 #define mmMP0_MISC_CGTT_CTRL0 0x01b9
85 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0
86 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
87 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
89 /* Vega, Raven, Arcturus */
90 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
93 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
96 .max_pixels_per_frame = 4096 * 2304,
100 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
103 .max_pixels_per_frame = 4096 * 2304,
108 static const struct amdgpu_video_codecs vega_video_codecs_encode =
110 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array),
111 .codec_array = vega_video_codecs_encode_array,
115 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =
118 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
121 .max_pixels_per_frame = 4096 * 4096,
125 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
128 .max_pixels_per_frame = 4096 * 4096,
132 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
135 .max_pixels_per_frame = 4096 * 4096,
139 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
142 .max_pixels_per_frame = 4096 * 4096,
146 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
149 .max_pixels_per_frame = 4096 * 4096,
153 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
156 .max_pixels_per_frame = 4096 * 4096,
161 static const struct amdgpu_video_codecs vega_video_codecs_decode =
163 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array),
164 .codec_array = vega_video_codecs_decode_array,
168 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =
171 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
174 .max_pixels_per_frame = 4096 * 4096,
178 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
181 .max_pixels_per_frame = 4096 * 4096,
185 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
188 .max_pixels_per_frame = 4096 * 4096,
192 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
195 .max_pixels_per_frame = 4096 * 4096,
199 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
202 .max_pixels_per_frame = 4096 * 4096,
206 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
209 .max_pixels_per_frame = 4096 * 4096,
213 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
216 .max_pixels_per_frame = 4096 * 4096,
221 static const struct amdgpu_video_codecs rv_video_codecs_decode =
223 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array),
224 .codec_array = rv_video_codecs_decode_array,
227 /* Renoir, Arcturus */
228 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =
231 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
234 .max_pixels_per_frame = 4096 * 4096,
238 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
241 .max_pixels_per_frame = 4096 * 4096,
245 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
248 .max_pixels_per_frame = 4096 * 4096,
252 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
255 .max_pixels_per_frame = 4096 * 4096,
259 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
262 .max_pixels_per_frame = 4096 * 4096,
266 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
269 .max_pixels_per_frame = 4096 * 4096,
273 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
276 .max_pixels_per_frame = 4096 * 4096,
281 static const struct amdgpu_video_codecs rn_video_codecs_decode =
283 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),
284 .codec_array = rn_video_codecs_decode_array,
287 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
288 const struct amdgpu_video_codecs **codecs)
290 switch (adev->asic_type) {
295 *codecs = &vega_video_codecs_encode;
297 *codecs = &vega_video_codecs_decode;
301 *codecs = &vega_video_codecs_encode;
303 *codecs = &rv_video_codecs_decode;
308 *codecs = &vega_video_codecs_encode;
310 *codecs = &rn_video_codecs_decode;
318 * Indirect registers accessor
320 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
322 unsigned long address, data;
323 address = adev->nbio.funcs->get_pcie_index_offset(adev);
324 data = adev->nbio.funcs->get_pcie_data_offset(adev);
326 return amdgpu_device_indirect_rreg(adev, address, data, reg);
329 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
331 unsigned long address, data;
333 address = adev->nbio.funcs->get_pcie_index_offset(adev);
334 data = adev->nbio.funcs->get_pcie_data_offset(adev);
336 amdgpu_device_indirect_wreg(adev, address, data, reg, v);
339 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
341 unsigned long address, data;
342 address = adev->nbio.funcs->get_pcie_index_offset(adev);
343 data = adev->nbio.funcs->get_pcie_data_offset(adev);
345 return amdgpu_device_indirect_rreg64(adev, address, data, reg);
348 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
350 unsigned long address, data;
352 address = adev->nbio.funcs->get_pcie_index_offset(adev);
353 data = adev->nbio.funcs->get_pcie_data_offset(adev);
355 amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
358 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
360 unsigned long flags, address, data;
363 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
364 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
366 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
367 WREG32(address, ((reg) & 0x1ff));
369 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
373 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
375 unsigned long flags, address, data;
377 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
378 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
380 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
381 WREG32(address, ((reg) & 0x1ff));
383 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
386 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
388 unsigned long flags, address, data;
391 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
392 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
394 spin_lock_irqsave(&adev->didt_idx_lock, flags);
395 WREG32(address, (reg));
397 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
401 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
403 unsigned long flags, address, data;
405 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
406 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
408 spin_lock_irqsave(&adev->didt_idx_lock, flags);
409 WREG32(address, (reg));
411 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
414 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
419 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
420 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
421 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
422 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
426 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
430 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
431 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
432 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
433 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
436 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
441 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
442 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
443 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
444 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
448 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
452 spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
453 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
454 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
455 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
458 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
460 return adev->nbio.funcs->get_memsize(adev);
463 static u32 soc15_get_xclk(struct amdgpu_device *adev)
465 u32 reference_clock = adev->clock.spll.reference_freq;
467 if (adev->asic_type == CHIP_RENOIR)
469 if (adev->asic_type == CHIP_RAVEN)
470 return reference_clock / 4;
472 return reference_clock;
476 void soc15_grbm_select(struct amdgpu_device *adev,
477 u32 me, u32 pipe, u32 queue, u32 vmid)
479 u32 grbm_gfx_cntl = 0;
480 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
481 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
482 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
483 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
485 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
488 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
493 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
499 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
500 u8 *bios, u32 length_bytes)
504 uint32_t rom_index_offset;
505 uint32_t rom_data_offset;
509 if (length_bytes == 0)
511 /* APU vbios image is part of sbios image */
512 if (adev->flags & AMD_IS_APU)
515 dw_ptr = (u32 *)bios;
516 length_dw = ALIGN(length_bytes, 4) / 4;
519 adev->smuio.funcs->get_rom_index_offset(adev);
521 adev->smuio.funcs->get_rom_data_offset(adev);
523 /* set rom index to 0 */
524 WREG32(rom_index_offset, 0);
525 /* read out the rom data */
526 for (i = 0; i < length_dw; i++)
527 dw_ptr[i] = RREG32(rom_data_offset);
532 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
533 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
534 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
535 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
536 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
537 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
538 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
539 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
540 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
541 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
542 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
543 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
544 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
545 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
546 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
547 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
548 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
549 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
550 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
551 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
552 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
555 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
556 u32 sh_num, u32 reg_offset)
560 mutex_lock(&adev->grbm_idx_mutex);
561 if (se_num != 0xffffffff || sh_num != 0xffffffff)
562 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
564 val = RREG32(reg_offset);
566 if (se_num != 0xffffffff || sh_num != 0xffffffff)
567 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
568 mutex_unlock(&adev->grbm_idx_mutex);
572 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
573 bool indexed, u32 se_num,
574 u32 sh_num, u32 reg_offset)
577 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
579 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
580 return adev->gfx.config.gb_addr_config;
581 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
582 return adev->gfx.config.db_debug2;
583 return RREG32(reg_offset);
587 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
588 u32 sh_num, u32 reg_offset, u32 *value)
591 struct soc15_allowed_register_entry *en;
594 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
595 en = &soc15_allowed_read_registers[i];
596 if (adev->reg_offset[en->hwip][en->inst] &&
597 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
601 *value = soc15_get_register_value(adev,
602 soc15_allowed_read_registers[i].grbm_indexed,
603 se_num, sh_num, reg_offset);
611 * soc15_program_register_sequence - program an array of registers.
613 * @adev: amdgpu_device pointer
614 * @regs: pointer to the register array
615 * @array_size: size of the register array
617 * Programs an array or registers with and and or masks.
618 * This is a helper for setting golden registers.
621 void soc15_program_register_sequence(struct amdgpu_device *adev,
622 const struct soc15_reg_golden *regs,
623 const u32 array_size)
625 const struct soc15_reg_golden *entry;
629 for (i = 0; i < array_size; ++i) {
631 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
633 if (entry->and_mask == 0xffffffff) {
634 tmp = entry->or_mask;
637 tmp &= ~(entry->and_mask);
638 tmp |= (entry->or_mask & entry->and_mask);
641 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
642 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
643 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
644 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
645 WREG32_RLC(reg, tmp);
653 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
655 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
658 /* avoid NBIF got stuck when do RAS recovery in BACO reset */
659 if (ras && ras->supported)
660 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
662 ret = amdgpu_dpm_baco_reset(adev);
666 /* re-enable doorbell interrupt after BACO exit */
667 if (ras && ras->supported)
668 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
673 static enum amd_reset_method
674 soc15_asic_reset_method(struct amdgpu_device *adev)
676 bool baco_reset = false;
677 bool connected_to_cpu = false;
678 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
680 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu)
681 connected_to_cpu = true;
683 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
684 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
685 amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
686 amdgpu_reset_method == AMD_RESET_METHOD_PCI) {
687 /* If connected to cpu, driver only support mode2 */
688 if (connected_to_cpu)
689 return AMD_RESET_METHOD_MODE2;
690 return amdgpu_reset_method;
693 if (amdgpu_reset_method != -1)
694 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
695 amdgpu_reset_method);
697 switch (adev->asic_type) {
700 return AMD_RESET_METHOD_MODE2;
704 baco_reset = amdgpu_dpm_is_baco_supported(adev);
707 if (adev->psp.sos_fw_version >= 0x80067)
708 baco_reset = amdgpu_dpm_is_baco_supported(adev);
711 * 1. PMFW version > 0x284300: all cases use baco
712 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
714 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400)
719 * 1.connected to cpu: driver issue mode2 reset
720 * 2.discret gpu: driver issue mode1 reset
722 if (connected_to_cpu)
723 return AMD_RESET_METHOD_MODE2;
730 return AMD_RESET_METHOD_BACO;
732 return AMD_RESET_METHOD_MODE1;
735 static int soc15_asic_reset(struct amdgpu_device *adev)
737 /* original raven doesn't have full asic reset */
738 if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
739 !(adev->apu_flags & AMD_APU_IS_RAVEN2))
742 switch (soc15_asic_reset_method(adev)) {
743 case AMD_RESET_METHOD_PCI:
744 dev_info(adev->dev, "PCI reset\n");
745 return amdgpu_device_pci_reset(adev);
746 case AMD_RESET_METHOD_BACO:
747 dev_info(adev->dev, "BACO reset\n");
748 return soc15_asic_baco_reset(adev);
749 case AMD_RESET_METHOD_MODE2:
750 dev_info(adev->dev, "MODE2 reset\n");
751 return amdgpu_dpm_mode2_reset(adev);
753 dev_info(adev->dev, "MODE1 reset\n");
754 return amdgpu_device_mode1_reset(adev);
758 static bool soc15_supports_baco(struct amdgpu_device *adev)
760 switch (adev->asic_type) {
764 return amdgpu_dpm_is_baco_supported(adev);
766 if (adev->psp.sos_fw_version >= 0x80067)
767 return amdgpu_dpm_is_baco_supported(adev);
774 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
775 u32 cntl_reg, u32 status_reg)
780 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
784 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
788 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
793 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
800 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
802 if (pci_is_root_bus(adev->pdev->bus))
805 if (amdgpu_pcie_gen2 == 0)
808 if (adev->flags & AMD_IS_APU)
811 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
812 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
818 static void soc15_program_aspm(struct amdgpu_device *adev)
821 if (amdgpu_aspm == 0)
827 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
830 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
831 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
834 static const struct amdgpu_ip_block_version vega10_common_ip_block =
836 .type = AMD_IP_BLOCK_TYPE_COMMON,
840 .funcs = &soc15_common_ip_funcs,
843 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
845 return adev->nbio.funcs->get_rev_id(adev);
848 static void soc15_reg_base_init(struct amdgpu_device *adev)
852 /* Set IP register base before any HW register access */
853 switch (adev->asic_type) {
857 vega10_reg_base_init(adev);
860 /* It's safe to do ip discovery here for Renior,
861 * it doesn't support SRIOV. */
862 if (amdgpu_discovery) {
863 r = amdgpu_discovery_reg_base_init(adev);
866 DRM_WARN("failed to init reg base from ip discovery table, "
867 "fallback to legacy init method\n");
869 vega10_reg_base_init(adev);
872 vega20_reg_base_init(adev);
875 arct_reg_base_init(adev);
878 aldebaran_reg_base_init(adev);
881 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
886 void soc15_set_virt_ops(struct amdgpu_device *adev)
888 adev->virt.ops = &xgpu_ai_virt_ops;
890 /* init soc15 reg base early enough so we can
891 * request request full access for sriov before
893 soc15_reg_base_init(adev);
896 int soc15_set_ip_blocks(struct amdgpu_device *adev)
898 /* for bare metal case */
899 if (!amdgpu_sriov_vf(adev))
900 soc15_reg_base_init(adev);
902 if (adev->flags & AMD_IS_APU) {
903 adev->nbio.funcs = &nbio_v7_0_funcs;
904 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
905 } else if (adev->asic_type == CHIP_VEGA20 ||
906 adev->asic_type == CHIP_ARCTURUS ||
907 adev->asic_type == CHIP_ALDEBARAN) {
908 adev->nbio.funcs = &nbio_v7_4_funcs;
909 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
911 adev->nbio.funcs = &nbio_v6_1_funcs;
912 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
914 adev->hdp.funcs = &hdp_v4_0_funcs;
916 if (adev->asic_type == CHIP_VEGA20 ||
917 adev->asic_type == CHIP_ARCTURUS ||
918 adev->asic_type == CHIP_ALDEBARAN)
919 adev->df.funcs = &df_v3_6_funcs;
921 adev->df.funcs = &df_v1_7_funcs;
923 if (adev->asic_type == CHIP_VEGA20 ||
924 adev->asic_type == CHIP_ARCTURUS)
925 adev->smuio.funcs = &smuio_v11_0_funcs;
926 else if (adev->asic_type == CHIP_ALDEBARAN)
927 adev->smuio.funcs = &smuio_v13_0_funcs;
929 adev->smuio.funcs = &smuio_v9_0_funcs;
931 adev->rev_id = soc15_get_rev_id(adev);
933 switch (adev->asic_type) {
937 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
938 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
940 /* For Vega10 SR-IOV, PSP need to be initialized before IH */
941 if (amdgpu_sriov_vf(adev)) {
942 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
943 if (adev->asic_type == CHIP_VEGA20)
944 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
946 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
948 if (adev->asic_type == CHIP_VEGA20)
949 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
951 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
953 if (adev->asic_type == CHIP_VEGA20)
954 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
956 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
957 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
958 if (adev->asic_type == CHIP_VEGA20)
959 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
961 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
964 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
965 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
966 if (is_support_sw_smu(adev)) {
967 if (!amdgpu_sriov_vf(adev))
968 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
970 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
972 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
973 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
974 #if defined(CONFIG_DRM_AMD_DC)
975 else if (amdgpu_device_has_dc_support(adev))
976 amdgpu_device_ip_block_add(adev, &dm_ip_block);
978 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {
979 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
980 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
984 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
985 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
986 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
987 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
988 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
989 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
990 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
991 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
992 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
993 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
994 #if defined(CONFIG_DRM_AMD_DC)
995 else if (amdgpu_device_has_dc_support(adev))
996 amdgpu_device_ip_block_add(adev, &dm_ip_block);
998 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
1001 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1002 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1004 if (amdgpu_sriov_vf(adev)) {
1005 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1006 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
1007 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1009 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1010 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1011 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
1014 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1015 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1016 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1017 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1018 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1020 if (amdgpu_sriov_vf(adev)) {
1021 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1022 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
1024 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
1026 if (!amdgpu_sriov_vf(adev))
1027 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
1030 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1031 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1032 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
1033 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1034 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
1035 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
1036 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1037 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1038 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1039 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
1040 #if defined(CONFIG_DRM_AMD_DC)
1041 else if (amdgpu_device_has_dc_support(adev))
1042 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1044 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
1045 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
1047 case CHIP_ALDEBARAN:
1048 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1049 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1051 if (amdgpu_sriov_vf(adev)) {
1052 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1053 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
1054 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1056 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1057 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
1058 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
1061 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1062 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1064 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
1065 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
1066 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
1075 static bool soc15_need_full_reset(struct amdgpu_device *adev)
1077 /* change this when we implement soft reset */
1081 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
1084 uint32_t perfctr = 0;
1085 uint64_t cnt0_of, cnt1_of;
1088 /* This reports 0 on APUs, so return to avoid writing/reading registers
1089 * that may or may not be different from their GPU counterparts
1091 if (adev->flags & AMD_IS_APU)
1094 /* Set the 2 events that we wish to watch, defined above */
1095 /* Reg 40 is # received msgs */
1096 /* Reg 104 is # of posted requests sent */
1097 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
1098 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
1100 /* Write to enable desired perf counters */
1101 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
1102 /* Zero out and enable the perf counters
1104 * Bit 0 = Start all counters(1)
1105 * Bit 2 = Global counter reset enable(1)
1107 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
1111 /* Load the shadow and disable the perf counters
1113 * Bit 0 = Stop counters(0)
1114 * Bit 1 = Load the shadow counters(1)
1116 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
1118 /* Read register values to get any >32bit overflow */
1119 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
1120 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
1121 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
1123 /* Get the values and add the overflow */
1124 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
1125 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
1128 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
1131 uint32_t perfctr = 0;
1132 uint64_t cnt0_of, cnt1_of;
1135 /* This reports 0 on APUs, so return to avoid writing/reading registers
1136 * that may or may not be different from their GPU counterparts
1138 if (adev->flags & AMD_IS_APU)
1141 /* Set the 2 events that we wish to watch, defined above */
1142 /* Reg 40 is # received msgs */
1143 /* Reg 108 is # of posted requests sent on VG20 */
1144 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
1146 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
1149 /* Write to enable desired perf counters */
1150 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
1151 /* Zero out and enable the perf counters
1153 * Bit 0 = Start all counters(1)
1154 * Bit 2 = Global counter reset enable(1)
1156 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
1160 /* Load the shadow and disable the perf counters
1162 * Bit 0 = Stop counters(0)
1163 * Bit 1 = Load the shadow counters(1)
1165 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
1167 /* Read register values to get any >32bit overflow */
1168 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
1169 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
1170 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
1172 /* Get the values and add the overflow */
1173 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
1174 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
1177 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
1181 /* Just return false for soc15 GPUs. Reset does not seem to
1184 if (!amdgpu_passthrough(adev))
1187 if (adev->flags & AMD_IS_APU)
1190 /* Check sOS sign of life register to confirm sys driver and sOS
1191 * are already been loaded.
1193 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1200 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
1202 uint64_t nak_r, nak_g;
1204 /* Get the number of NAKs received and generated */
1205 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
1206 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
1208 /* Add the total number of NAKs, i.e the number of replays */
1209 return (nak_r + nak_g);
1212 static void soc15_pre_asic_init(struct amdgpu_device *adev)
1214 gmc_v9_0_restore_registers(adev);
1217 static const struct amdgpu_asic_funcs soc15_asic_funcs =
1219 .read_disabled_bios = &soc15_read_disabled_bios,
1220 .read_bios_from_rom = &soc15_read_bios_from_rom,
1221 .read_register = &soc15_read_register,
1222 .reset = &soc15_asic_reset,
1223 .reset_method = &soc15_asic_reset_method,
1224 .set_vga_state = &soc15_vga_set_state,
1225 .get_xclk = &soc15_get_xclk,
1226 .set_uvd_clocks = &soc15_set_uvd_clocks,
1227 .set_vce_clocks = &soc15_set_vce_clocks,
1228 .get_config_memsize = &soc15_get_config_memsize,
1229 .need_full_reset = &soc15_need_full_reset,
1230 .init_doorbell_index = &vega10_doorbell_index_init,
1231 .get_pcie_usage = &soc15_get_pcie_usage,
1232 .need_reset_on_init = &soc15_need_reset_on_init,
1233 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1234 .supports_baco = &soc15_supports_baco,
1235 .pre_asic_init = &soc15_pre_asic_init,
1236 .query_video_codecs = &soc15_query_video_codecs,
1239 static const struct amdgpu_asic_funcs vega20_asic_funcs =
1241 .read_disabled_bios = &soc15_read_disabled_bios,
1242 .read_bios_from_rom = &soc15_read_bios_from_rom,
1243 .read_register = &soc15_read_register,
1244 .reset = &soc15_asic_reset,
1245 .reset_method = &soc15_asic_reset_method,
1246 .set_vga_state = &soc15_vga_set_state,
1247 .get_xclk = &soc15_get_xclk,
1248 .set_uvd_clocks = &soc15_set_uvd_clocks,
1249 .set_vce_clocks = &soc15_set_vce_clocks,
1250 .get_config_memsize = &soc15_get_config_memsize,
1251 .need_full_reset = &soc15_need_full_reset,
1252 .init_doorbell_index = &vega20_doorbell_index_init,
1253 .get_pcie_usage = &vega20_get_pcie_usage,
1254 .need_reset_on_init = &soc15_need_reset_on_init,
1255 .get_pcie_replay_count = &soc15_get_pcie_replay_count,
1256 .supports_baco = &soc15_supports_baco,
1257 .pre_asic_init = &soc15_pre_asic_init,
1258 .query_video_codecs = &soc15_query_video_codecs,
1261 static int soc15_common_early_init(void *handle)
1263 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1264 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1266 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1267 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1268 adev->smc_rreg = NULL;
1269 adev->smc_wreg = NULL;
1270 adev->pcie_rreg = &soc15_pcie_rreg;
1271 adev->pcie_wreg = &soc15_pcie_wreg;
1272 adev->pcie_rreg64 = &soc15_pcie_rreg64;
1273 adev->pcie_wreg64 = &soc15_pcie_wreg64;
1274 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
1275 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
1276 adev->didt_rreg = &soc15_didt_rreg;
1277 adev->didt_wreg = &soc15_didt_wreg;
1278 adev->gc_cac_rreg = &soc15_gc_cac_rreg;
1279 adev->gc_cac_wreg = &soc15_gc_cac_wreg;
1280 adev->se_cac_rreg = &soc15_se_cac_rreg;
1281 adev->se_cac_wreg = &soc15_se_cac_wreg;
1284 adev->external_rev_id = 0xFF;
1285 switch (adev->asic_type) {
1287 adev->asic_funcs = &soc15_asic_funcs;
1288 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1289 AMD_CG_SUPPORT_GFX_MGLS |
1290 AMD_CG_SUPPORT_GFX_RLC_LS |
1291 AMD_CG_SUPPORT_GFX_CP_LS |
1292 AMD_CG_SUPPORT_GFX_3D_CGCG |
1293 AMD_CG_SUPPORT_GFX_3D_CGLS |
1294 AMD_CG_SUPPORT_GFX_CGCG |
1295 AMD_CG_SUPPORT_GFX_CGLS |
1296 AMD_CG_SUPPORT_BIF_MGCG |
1297 AMD_CG_SUPPORT_BIF_LS |
1298 AMD_CG_SUPPORT_HDP_LS |
1299 AMD_CG_SUPPORT_DRM_MGCG |
1300 AMD_CG_SUPPORT_DRM_LS |
1301 AMD_CG_SUPPORT_ROM_MGCG |
1302 AMD_CG_SUPPORT_DF_MGCG |
1303 AMD_CG_SUPPORT_SDMA_MGCG |
1304 AMD_CG_SUPPORT_SDMA_LS |
1305 AMD_CG_SUPPORT_MC_MGCG |
1306 AMD_CG_SUPPORT_MC_LS;
1308 adev->external_rev_id = 0x1;
1311 adev->asic_funcs = &soc15_asic_funcs;
1312 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1313 AMD_CG_SUPPORT_GFX_MGLS |
1314 AMD_CG_SUPPORT_GFX_CGCG |
1315 AMD_CG_SUPPORT_GFX_CGLS |
1316 AMD_CG_SUPPORT_GFX_3D_CGCG |
1317 AMD_CG_SUPPORT_GFX_3D_CGLS |
1318 AMD_CG_SUPPORT_GFX_CP_LS |
1319 AMD_CG_SUPPORT_MC_LS |
1320 AMD_CG_SUPPORT_MC_MGCG |
1321 AMD_CG_SUPPORT_SDMA_MGCG |
1322 AMD_CG_SUPPORT_SDMA_LS |
1323 AMD_CG_SUPPORT_BIF_MGCG |
1324 AMD_CG_SUPPORT_BIF_LS |
1325 AMD_CG_SUPPORT_HDP_MGCG |
1326 AMD_CG_SUPPORT_HDP_LS |
1327 AMD_CG_SUPPORT_ROM_MGCG |
1328 AMD_CG_SUPPORT_VCE_MGCG |
1329 AMD_CG_SUPPORT_UVD_MGCG;
1331 adev->external_rev_id = adev->rev_id + 0x14;
1334 adev->asic_funcs = &vega20_asic_funcs;
1335 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1336 AMD_CG_SUPPORT_GFX_MGLS |
1337 AMD_CG_SUPPORT_GFX_CGCG |
1338 AMD_CG_SUPPORT_GFX_CGLS |
1339 AMD_CG_SUPPORT_GFX_3D_CGCG |
1340 AMD_CG_SUPPORT_GFX_3D_CGLS |
1341 AMD_CG_SUPPORT_GFX_CP_LS |
1342 AMD_CG_SUPPORT_MC_LS |
1343 AMD_CG_SUPPORT_MC_MGCG |
1344 AMD_CG_SUPPORT_SDMA_MGCG |
1345 AMD_CG_SUPPORT_SDMA_LS |
1346 AMD_CG_SUPPORT_BIF_MGCG |
1347 AMD_CG_SUPPORT_BIF_LS |
1348 AMD_CG_SUPPORT_HDP_MGCG |
1349 AMD_CG_SUPPORT_HDP_LS |
1350 AMD_CG_SUPPORT_ROM_MGCG |
1351 AMD_CG_SUPPORT_VCE_MGCG |
1352 AMD_CG_SUPPORT_UVD_MGCG;
1354 adev->external_rev_id = adev->rev_id + 0x28;
1357 adev->asic_funcs = &soc15_asic_funcs;
1358 if (adev->pdev->device == 0x15dd)
1359 adev->apu_flags |= AMD_APU_IS_RAVEN;
1360 if (adev->pdev->device == 0x15d8)
1361 adev->apu_flags |= AMD_APU_IS_PICASSO;
1362 if (adev->rev_id >= 0x8)
1363 adev->apu_flags |= AMD_APU_IS_RAVEN2;
1365 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1366 adev->external_rev_id = adev->rev_id + 0x79;
1367 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1368 adev->external_rev_id = adev->rev_id + 0x41;
1369 else if (adev->rev_id == 1)
1370 adev->external_rev_id = adev->rev_id + 0x20;
1372 adev->external_rev_id = adev->rev_id + 0x01;
1374 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1375 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1376 AMD_CG_SUPPORT_GFX_MGLS |
1377 AMD_CG_SUPPORT_GFX_CP_LS |
1378 AMD_CG_SUPPORT_GFX_3D_CGCG |
1379 AMD_CG_SUPPORT_GFX_3D_CGLS |
1380 AMD_CG_SUPPORT_GFX_CGCG |
1381 AMD_CG_SUPPORT_GFX_CGLS |
1382 AMD_CG_SUPPORT_BIF_LS |
1383 AMD_CG_SUPPORT_HDP_LS |
1384 AMD_CG_SUPPORT_MC_MGCG |
1385 AMD_CG_SUPPORT_MC_LS |
1386 AMD_CG_SUPPORT_SDMA_MGCG |
1387 AMD_CG_SUPPORT_SDMA_LS |
1388 AMD_CG_SUPPORT_VCN_MGCG;
1390 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1391 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1392 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1393 AMD_CG_SUPPORT_GFX_MGLS |
1394 AMD_CG_SUPPORT_GFX_CP_LS |
1395 AMD_CG_SUPPORT_GFX_3D_CGCG |
1396 AMD_CG_SUPPORT_GFX_3D_CGLS |
1397 AMD_CG_SUPPORT_GFX_CGCG |
1398 AMD_CG_SUPPORT_GFX_CGLS |
1399 AMD_CG_SUPPORT_BIF_LS |
1400 AMD_CG_SUPPORT_HDP_LS |
1401 AMD_CG_SUPPORT_MC_MGCG |
1402 AMD_CG_SUPPORT_MC_LS |
1403 AMD_CG_SUPPORT_SDMA_MGCG |
1404 AMD_CG_SUPPORT_SDMA_LS;
1406 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1407 AMD_PG_SUPPORT_MMHUB |
1410 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1411 AMD_CG_SUPPORT_GFX_MGLS |
1412 AMD_CG_SUPPORT_GFX_RLC_LS |
1413 AMD_CG_SUPPORT_GFX_CP_LS |
1414 AMD_CG_SUPPORT_GFX_3D_CGCG |
1415 AMD_CG_SUPPORT_GFX_3D_CGLS |
1416 AMD_CG_SUPPORT_GFX_CGCG |
1417 AMD_CG_SUPPORT_GFX_CGLS |
1418 AMD_CG_SUPPORT_BIF_MGCG |
1419 AMD_CG_SUPPORT_BIF_LS |
1420 AMD_CG_SUPPORT_HDP_MGCG |
1421 AMD_CG_SUPPORT_HDP_LS |
1422 AMD_CG_SUPPORT_DRM_MGCG |
1423 AMD_CG_SUPPORT_DRM_LS |
1424 AMD_CG_SUPPORT_MC_MGCG |
1425 AMD_CG_SUPPORT_MC_LS |
1426 AMD_CG_SUPPORT_SDMA_MGCG |
1427 AMD_CG_SUPPORT_SDMA_LS |
1428 AMD_CG_SUPPORT_VCN_MGCG;
1430 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1434 adev->asic_funcs = &vega20_asic_funcs;
1435 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1436 AMD_CG_SUPPORT_GFX_MGLS |
1437 AMD_CG_SUPPORT_GFX_CGCG |
1438 AMD_CG_SUPPORT_GFX_CGLS |
1439 AMD_CG_SUPPORT_GFX_CP_LS |
1440 AMD_CG_SUPPORT_HDP_MGCG |
1441 AMD_CG_SUPPORT_HDP_LS |
1442 AMD_CG_SUPPORT_SDMA_MGCG |
1443 AMD_CG_SUPPORT_SDMA_LS |
1444 AMD_CG_SUPPORT_MC_MGCG |
1445 AMD_CG_SUPPORT_MC_LS |
1446 AMD_CG_SUPPORT_IH_CG |
1447 AMD_CG_SUPPORT_VCN_MGCG |
1448 AMD_CG_SUPPORT_JPEG_MGCG;
1449 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1450 adev->external_rev_id = adev->rev_id + 0x32;
1453 adev->asic_funcs = &soc15_asic_funcs;
1454 if ((adev->pdev->device == 0x1636) ||
1455 (adev->pdev->device == 0x164c))
1456 adev->apu_flags |= AMD_APU_IS_RENOIR;
1458 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;
1460 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1461 adev->external_rev_id = adev->rev_id + 0x91;
1463 adev->external_rev_id = adev->rev_id + 0xa1;
1464 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1465 AMD_CG_SUPPORT_GFX_MGLS |
1466 AMD_CG_SUPPORT_GFX_3D_CGCG |
1467 AMD_CG_SUPPORT_GFX_3D_CGLS |
1468 AMD_CG_SUPPORT_GFX_CGCG |
1469 AMD_CG_SUPPORT_GFX_CGLS |
1470 AMD_CG_SUPPORT_GFX_CP_LS |
1471 AMD_CG_SUPPORT_MC_MGCG |
1472 AMD_CG_SUPPORT_MC_LS |
1473 AMD_CG_SUPPORT_SDMA_MGCG |
1474 AMD_CG_SUPPORT_SDMA_LS |
1475 AMD_CG_SUPPORT_BIF_LS |
1476 AMD_CG_SUPPORT_HDP_LS |
1477 AMD_CG_SUPPORT_VCN_MGCG |
1478 AMD_CG_SUPPORT_JPEG_MGCG |
1479 AMD_CG_SUPPORT_IH_CG |
1480 AMD_CG_SUPPORT_ATHUB_LS |
1481 AMD_CG_SUPPORT_ATHUB_MGCG |
1482 AMD_CG_SUPPORT_DF_MGCG;
1483 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1484 AMD_PG_SUPPORT_VCN |
1485 AMD_PG_SUPPORT_JPEG |
1486 AMD_PG_SUPPORT_VCN_DPG;
1488 case CHIP_ALDEBARAN:
1489 adev->asic_funcs = &vega20_asic_funcs;
1490 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1491 AMD_CG_SUPPORT_GFX_MGLS |
1492 AMD_CG_SUPPORT_GFX_CGCG |
1493 AMD_CG_SUPPORT_GFX_CGLS |
1494 AMD_CG_SUPPORT_GFX_CP_LS |
1495 AMD_CG_SUPPORT_HDP_LS |
1496 AMD_CG_SUPPORT_SDMA_MGCG |
1497 AMD_CG_SUPPORT_SDMA_LS |
1498 AMD_CG_SUPPORT_IH_CG;
1499 /*AMD_CG_SUPPORT_VCN_MGCG |AMD_CG_SUPPORT_JPEG_MGCG;*/
1500 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
1501 adev->external_rev_id = adev->rev_id + 0x3c;
1504 /* FIXME: not supported yet */
1508 if (amdgpu_sriov_vf(adev)) {
1509 amdgpu_virt_init_setting(adev);
1510 xgpu_ai_mailbox_set_irq_funcs(adev);
1516 static int soc15_common_late_init(void *handle)
1518 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1521 if (amdgpu_sriov_vf(adev))
1522 xgpu_ai_mailbox_get_irq(adev);
1524 if (adev->hdp.funcs->reset_ras_error_count)
1525 adev->hdp.funcs->reset_ras_error_count(adev);
1527 if (adev->nbio.funcs->ras_late_init)
1528 r = adev->nbio.funcs->ras_late_init(adev);
1533 static int soc15_common_sw_init(void *handle)
1535 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1537 if (amdgpu_sriov_vf(adev))
1538 xgpu_ai_mailbox_add_irq_id(adev);
1540 adev->df.funcs->sw_init(adev);
1545 static int soc15_common_sw_fini(void *handle)
1547 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1549 amdgpu_nbio_ras_fini(adev);
1550 adev->df.funcs->sw_fini(adev);
1554 static void soc15_doorbell_range_init(struct amdgpu_device *adev)
1557 struct amdgpu_ring *ring;
1559 /* sdma/ih doorbell range are programed by hypervisor */
1560 if (!amdgpu_sriov_vf(adev)) {
1561 for (i = 0; i < adev->sdma.num_instances; i++) {
1562 ring = &adev->sdma.instance[i].ring;
1563 adev->nbio.funcs->sdma_doorbell_range(adev, i,
1564 ring->use_doorbell, ring->doorbell_index,
1565 adev->doorbell_index.sdma_doorbell_range);
1568 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
1569 adev->irq.ih.doorbell_index);
1573 static int soc15_common_hw_init(void *handle)
1575 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1577 /* enable pcie gen2/3 link */
1578 soc15_pcie_gen3_enable(adev);
1580 soc15_program_aspm(adev);
1581 /* setup nbio registers */
1582 adev->nbio.funcs->init_registers(adev);
1583 /* remap HDP registers to a hole in mmio space,
1584 * for the purpose of expose those registers
1587 if (adev->nbio.funcs->remap_hdp_registers)
1588 adev->nbio.funcs->remap_hdp_registers(adev);
1590 /* enable the doorbell aperture */
1591 soc15_enable_doorbell_aperture(adev, true);
1592 /* HW doorbell routing policy: doorbell writing not
1593 * in SDMA/IH/MM/ACV range will be routed to CP. So
1594 * we need to init SDMA/IH/MM/ACV doorbell range prior
1595 * to CP ip block init and ring test.
1597 soc15_doorbell_range_init(adev);
1602 static int soc15_common_hw_fini(void *handle)
1604 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1606 /* disable the doorbell aperture */
1607 soc15_enable_doorbell_aperture(adev, false);
1608 if (amdgpu_sriov_vf(adev))
1609 xgpu_ai_mailbox_put_irq(adev);
1611 if (adev->nbio.ras_if &&
1612 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1613 if (adev->nbio.funcs->init_ras_controller_interrupt)
1614 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1615 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt)
1616 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1622 static int soc15_common_suspend(void *handle)
1624 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1626 return soc15_common_hw_fini(adev);
1629 static int soc15_common_resume(void *handle)
1631 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1633 return soc15_common_hw_init(adev);
1636 static bool soc15_common_is_idle(void *handle)
1641 static int soc15_common_wait_for_idle(void *handle)
1646 static int soc15_common_soft_reset(void *handle)
1651 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1655 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1657 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1658 data &= ~(0x01000000 |
1667 data |= (0x01000000 |
1677 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1680 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1684 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1686 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1692 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1695 static int soc15_common_set_clockgating_state(void *handle,
1696 enum amd_clockgating_state state)
1698 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1700 if (amdgpu_sriov_vf(adev))
1703 switch (adev->asic_type) {
1707 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1708 state == AMD_CG_STATE_GATE);
1709 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1710 state == AMD_CG_STATE_GATE);
1711 adev->hdp.funcs->update_clock_gating(adev,
1712 state == AMD_CG_STATE_GATE);
1713 soc15_update_drm_clock_gating(adev,
1714 state == AMD_CG_STATE_GATE);
1715 soc15_update_drm_light_sleep(adev,
1716 state == AMD_CG_STATE_GATE);
1717 adev->smuio.funcs->update_rom_clock_gating(adev,
1718 state == AMD_CG_STATE_GATE);
1719 adev->df.funcs->update_medium_grain_clock_gating(adev,
1720 state == AMD_CG_STATE_GATE);
1724 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1725 state == AMD_CG_STATE_GATE);
1726 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1727 state == AMD_CG_STATE_GATE);
1728 adev->hdp.funcs->update_clock_gating(adev,
1729 state == AMD_CG_STATE_GATE);
1730 soc15_update_drm_clock_gating(adev,
1731 state == AMD_CG_STATE_GATE);
1732 soc15_update_drm_light_sleep(adev,
1733 state == AMD_CG_STATE_GATE);
1736 case CHIP_ALDEBARAN:
1737 adev->hdp.funcs->update_clock_gating(adev,
1738 state == AMD_CG_STATE_GATE);
1746 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
1748 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1751 if (amdgpu_sriov_vf(adev))
1754 adev->nbio.funcs->get_clockgating_state(adev, flags);
1756 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1758 if (adev->asic_type != CHIP_ALDEBARAN) {
1760 /* AMD_CG_SUPPORT_DRM_MGCG */
1761 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1762 if (!(data & 0x01000000))
1763 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1765 /* AMD_CG_SUPPORT_DRM_LS */
1766 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1768 *flags |= AMD_CG_SUPPORT_DRM_LS;
1771 /* AMD_CG_SUPPORT_ROM_MGCG */
1772 adev->smuio.funcs->get_clock_gating_state(adev, flags);
1774 adev->df.funcs->get_clockgating_state(adev, flags);
1777 static int soc15_common_set_powergating_state(void *handle,
1778 enum amd_powergating_state state)
1784 const struct amd_ip_funcs soc15_common_ip_funcs = {
1785 .name = "soc15_common",
1786 .early_init = soc15_common_early_init,
1787 .late_init = soc15_common_late_init,
1788 .sw_init = soc15_common_sw_init,
1789 .sw_fini = soc15_common_sw_fini,
1790 .hw_init = soc15_common_hw_init,
1791 .hw_fini = soc15_common_hw_fini,
1792 .suspend = soc15_common_suspend,
1793 .resume = soc15_common_resume,
1794 .is_idle = soc15_common_is_idle,
1795 .wait_for_idle = soc15_common_wait_for_idle,
1796 .soft_reset = soc15_common_soft_reset,
1797 .set_clockgating_state = soc15_common_set_clockgating_state,
1798 .set_powergating_state = soc15_common_set_powergating_state,
1799 .get_clockgating_state= soc15_common_get_clockgating_state,