drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_3_0_offset.h"
  34 #include "gc/gc_10_3_0_sh_mask.h"
  35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
  38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
  39
  40 #include "soc15_common.h"
  41 #include "soc15.h"
  42 #include "navi10_sdma_pkt_open.h"
  43 #include "nbio_v2_3.h"
  44 #include "sdma_common.h"
  45 #include "sdma_v5_2.h"
  46
  47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
  48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
  50
  51 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
  52
  53 #define SDMA1_REG_OFFSET 0x600
  54 #define SDMA3_REG_OFFSET 0x400
  55 #define SDMA0_HYP_DEC_REG_START 0x5880
  56 #define SDMA0_HYP_DEC_REG_END 0x5893
  57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  58
  59 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
  60 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
  61 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
  62 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
  63
  64 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
  65 {
  66         u32 base;
  67
  68         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
  69             internal_offset <= SDMA0_HYP_DEC_REG_END) {
  70                 base = adev->reg_offset[GC_HWIP][0][1];
  71                 if (instance != 0)
  72                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
  73         } else {
  74                 if (instance < 2) {
  75                         base = adev->reg_offset[GC_HWIP][0][0];
  76                         if (instance == 1)
  77                                 internal_offset += SDMA1_REG_OFFSET;
  78                 } else {
  79                         base = adev->reg_offset[GC_HWIP][0][2];
  80                         if (instance == 3)
  81                                 internal_offset += SDMA3_REG_OFFSET;
  82                 }
  83         }
  84
  85         return base + internal_offset;
  86 }
  87
  88 static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
  89 {
  90         switch (adev->asic_type) {
  91         case CHIP_SIENNA_CICHLID:
  92         case CHIP_NAVY_FLOUNDER:
  93         case CHIP_VANGOGH:
  94         case CHIP_DIMGREY_CAVEFISH:
  95                 break;
  96         default:
  97                 break;
  98         }
  99 }
 100
 101 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
 102 {
 103         int err = 0;
 104         const struct sdma_firmware_header_v1_0 *hdr;
 105
 106         err = amdgpu_ucode_validate(sdma_inst->fw);
 107         if (err)
 108                 return err;
 109
 110         hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
 111         sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
 112         sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
 113
 114         if (sdma_inst->feature_version >= 20)
 115                 sdma_inst->burst_nop = true;
 116
 117         return 0;
 118 }
 119
 120 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
 121 {
 122         release_firmware(adev->sdma.instance[0].fw);
 123
 124         memset((void *)adev->sdma.instance, 0,
 125                sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
 126 }
 127
 128 /**
 129  * sdma_v5_2_init_microcode - load ucode images from disk
 130  *
 131  * @adev: amdgpu_device pointer
 132  *
 133  * Use the firmware interface to load the ucode images into
 134  * the driver (not loaded into hw).
 135  * Returns 0 on success, error on failure.
 136  */
 137
 138 // emulation only, won't work on real chip
 139 // navi10 real chip need to use PSP to load firmware
 140 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
 141 {
 142         const char *chip_name;
 143         char fw_name[40];
 144         int err = 0, i;
 145         struct amdgpu_firmware_info *info = NULL;
 146         const struct common_firmware_header *header = NULL;
 147
 148         if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID))
 149                 return 0;
 150
 151         DRM_DEBUG("\n");
 152
 153         switch (adev->asic_type) {
 154         case CHIP_SIENNA_CICHLID:
 155                 chip_name = "sienna_cichlid";
 156                 break;
 157         case CHIP_NAVY_FLOUNDER:
 158                 chip_name = "navy_flounder";
 159                 break;
 160         case CHIP_VANGOGH:
 161                 chip_name = "vangogh";
 162                 break;
 163         case CHIP_DIMGREY_CAVEFISH:
 164                 chip_name = "dimgrey_cavefish";
 165                 break;
 166         default:
 167                 BUG();
 168         }
 169
 170         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 171
 172         err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
 173         if (err)
 174                 goto out;
 175
 176         err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
 177         if (err)
 178                 goto out;
 179
 180         for (i = 1; i < adev->sdma.num_instances; i++)
 181                 memcpy((void *)&adev->sdma.instance[i],
 182                        (void *)&adev->sdma.instance[0],
 183                        sizeof(struct amdgpu_sdma_instance));
 184
 185         DRM_DEBUG("psp_load == '%s'\n",
 186                   adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 187
 188         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 189                 for (i = 0; i < adev->sdma.num_instances; i++) {
 190                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 191                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 192                         info->fw = adev->sdma.instance[i].fw;
 193                         header = (const struct common_firmware_header *)info->fw->data;
 194                         adev->firmware.fw_size +=
 195                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 196                 }
 197         }
 198
 199 out:
 200         if (err) {
 201                 DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
 202                 sdma_v5_2_destroy_inst_ctx(adev);
 203         }
 204         return err;
 205 }
 206
 207 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
 208 {
 209         unsigned ret;
 210
 211         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 212         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 213         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 214         amdgpu_ring_write(ring, 1);
 215         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 216         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 217
 218         return ret;
 219 }
 220
 221 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
 222                                            unsigned offset)
 223 {
 224         unsigned cur;
 225
 226         BUG_ON(offset > ring->buf_mask);
 227         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 228
 229         cur = (ring->wptr - 1) & ring->buf_mask;
 230         if (cur > offset)
 231                 ring->ring[offset] = cur - offset;
 232         else
 233                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 234 }
 235
 236 /**
 237  * sdma_v5_2_ring_get_rptr - get the current read pointer
 238  *
 239  * @ring: amdgpu ring pointer
 240  *
 241  * Get the current rptr from the hardware (NAVI10+).
 242  */
 243 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
 244 {
 245         u64 *rptr;
 246
 247         /* XXX check if swapping is necessary on BE */
 248         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 249
 250         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 251         return ((*rptr) >> 2);
 252 }
 253
 254 /**
 255  * sdma_v5_2_ring_get_wptr - get the current write pointer
 256  *
 257  * @ring: amdgpu ring pointer
 258  *
 259  * Get the current wptr from the hardware (NAVI10+).
 260  */
 261 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
 262 {
 263         struct amdgpu_device *adev = ring->adev;
 264         u64 wptr;
 265
 266         if (ring->use_doorbell) {
 267                 /* XXX check if swapping is necessary on BE */
 268                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 269                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 270         } else {
 271                 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 272                 wptr = wptr << 32;
 273                 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 274                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 275         }
 276
 277         return wptr >> 2;
 278 }
 279
 280 /**
 281  * sdma_v5_2_ring_set_wptr - commit the write pointer
 282  *
 283  * @ring: amdgpu ring pointer
 284  *
 285  * Write the wptr back to the hardware (NAVI10+).
 286  */
 287 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
 288 {
 289         struct amdgpu_device *adev = ring->adev;
 290
 291         DRM_DEBUG("Setting write pointer\n");
 292         if (ring->use_doorbell) {
 293                 DRM_DEBUG("Using doorbell -- "
 294                                 "wptr_offs == 0x%08x "
 295                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 296                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 297                                 ring->wptr_offs,
 298                                 lower_32_bits(ring->wptr << 2),
 299                                 upper_32_bits(ring->wptr << 2));
 300                 /* XXX check if swapping is necessary on BE */
 301                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 302                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 303                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 304                                 ring->doorbell_index, ring->wptr << 2);
 305                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 306         } else {
 307                 DRM_DEBUG("Not using doorbell -- "
 308                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 309                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 310                                 ring->me,
 311                                 lower_32_bits(ring->wptr << 2),
 312                                 ring->me,
 313                                 upper_32_bits(ring->wptr << 2));
 314                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 315                         lower_32_bits(ring->wptr << 2));
 316                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 317                         upper_32_bits(ring->wptr << 2));
 318         }
 319 }
 320
 321 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 322 {
 323         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 324         int i;
 325
 326         for (i = 0; i < count; i++)
 327                 if (sdma && sdma->burst_nop && (i == 0))
 328                         amdgpu_ring_write(ring, ring->funcs->nop |
 329                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 330                 else
 331                         amdgpu_ring_write(ring, ring->funcs->nop);
 332 }
 333
 334 /**
 335  * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
 336  *
 337  * @ring: amdgpu ring pointer
 338  * @job: job to retrieve vmid from
 339  * @ib: IB object to schedule
 340  * @flags: unused
 341  *
 342  * Schedule an IB in the DMA ring.
 343  */
 344 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
 345                                    struct amdgpu_job *job,
 346                                    struct amdgpu_ib *ib,
 347                                    uint32_t flags)
 348 {
 349         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 350         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 351
 352         /* An IB packet must end on a 8 DW boundary--the next dword
 353          * must be on a 8-dword boundary. Our IB packet below is 6
 354          * dwords long, thus add x number of NOPs, such that, in
 355          * modular arithmetic,
 356          * wptr + 6 + x = 8k, k >= 0, which in C is,
 357          * (wptr + 6 + x) % 8 = 0.
 358          * The expression below, is a solution of x.
 359          */
 360         sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 361
 362         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 363                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 364         /* base must be 32 byte aligned */
 365         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 366         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 367         amdgpu_ring_write(ring, ib->length_dw);
 368         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 369         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 370 }
 371
 372 /**
 373  * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse
 374  *
 375  * @ring: amdgpu ring pointer
 376  * @job: job to retrieve vmid from
 377  * @ib: IB object to schedule
 378  *
 379  * flush the IB by graphics cache rinse.
 380  */
 381 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
 382 {
 383     uint32_t gcr_cntl =
 384                     SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
 385                         SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
 386                         SDMA_GCR_GLI_INV(1);
 387
 388         /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
 389         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
 390         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
 391         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
 392                         SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
 393         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
 394                         SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
 395         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
 396                         SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
 397 }
 398
 399 /**
 400  * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 401  *
 402  * @ring: amdgpu ring pointer
 403  *
 404  * Emit an hdp flush packet on the requested DMA ring.
 405  */
 406 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 407 {
 408         struct amdgpu_device *adev = ring->adev;
 409         u32 ref_and_mask = 0;
 410         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 411
 412         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 413
 414         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 415                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 416                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 417         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 418         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 419         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 420         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 421         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 422                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 423 }
 424
 425 /**
 426  * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
 427  *
 428  * @ring: amdgpu ring pointer
 429  * @addr: address
 430  * @seq: sequence number
 431  * @flags: fence related flags
 432  *
 433  * Add a DMA fence packet to the ring to write
 434  * the fence seq number and DMA trap packet to generate
 435  * an interrupt if needed.
 436  */
 437 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 438                                       unsigned flags)
 439 {
 440         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 441         /* write the fence */
 442         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 443                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 444         /* zero in first two bits */
 445         BUG_ON(addr & 0x3);
 446         amdgpu_ring_write(ring, lower_32_bits(addr));
 447         amdgpu_ring_write(ring, upper_32_bits(addr));
 448         amdgpu_ring_write(ring, lower_32_bits(seq));
 449
 450         /* optionally write high bits as well */
 451         if (write64bit) {
 452                 addr += 4;
 453                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 454                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 455                 /* zero in first two bits */
 456                 BUG_ON(addr & 0x3);
 457                 amdgpu_ring_write(ring, lower_32_bits(addr));
 458                 amdgpu_ring_write(ring, upper_32_bits(addr));
 459                 amdgpu_ring_write(ring, upper_32_bits(seq));
 460         }
 461
 462         if (flags & AMDGPU_FENCE_FLAG_INT) {
 463                 /* generate an interrupt */
 464                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 465                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 466         }
 467 }
 468
 469
 470 /**
 471  * sdma_v5_2_gfx_stop - stop the gfx async dma engines
 472  *
 473  * @adev: amdgpu_device pointer
 474  *
 475  * Stop the gfx async dma ring buffers.
 476  */
 477 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
 478 {
 479         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 480         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 481         struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
 482         struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
 483         u32 rb_cntl, ib_cntl;
 484         int i;
 485
 486         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 487             (adev->mman.buffer_funcs_ring == sdma1) ||
 488             (adev->mman.buffer_funcs_ring == sdma2) ||
 489             (adev->mman.buffer_funcs_ring == sdma3))
 490                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 491
 492         for (i = 0; i < adev->sdma.num_instances; i++) {
 493                 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 494                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 495                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 496                 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 497                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 498                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 499         }
 500 }
 501
 502 /**
 503  * sdma_v5_2_rlc_stop - stop the compute async dma engines
 504  *
 505  * @adev: amdgpu_device pointer
 506  *
 507  * Stop the compute async dma queues.
 508  */
 509 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
 510 {
 511         /* XXX todo */
 512 }
 513
 514 /**
 515  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 516  *
 517  * @adev: amdgpu_device pointer
 518  * @enable: enable/disable the DMA MEs context switch.
 519  *
 520  * Halt or unhalt the async dma engines context switch.
 521  */
 522 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 523 {
 524         u32 f32_cntl, phase_quantum = 0;
 525         int i;
 526
 527         if (amdgpu_sdma_phase_quantum) {
 528                 unsigned value = amdgpu_sdma_phase_quantum;
 529                 unsigned unit = 0;
 530
 531                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 532                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 533                         value = (value + 1) >> 1;
 534                         unit++;
 535                 }
 536                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 537                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 538                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 539                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 540                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 541                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 542                         WARN_ONCE(1,
 543                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 544                                   value << unit);
 545                 }
 546                 phase_quantum =
 547                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 548                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 549         }
 550
 551         for (i = 0; i < adev->sdma.num_instances; i++) {
 552                 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 553                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 554                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 555                 if (enable && amdgpu_sdma_phase_quantum) {
 556                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 557                                phase_quantum);
 558                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 559                                phase_quantum);
 560                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 561                                phase_quantum);
 562                 }
 563                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 564         }
 565
 566 }
 567
 568 /**
 569  * sdma_v5_2_enable - stop the async dma engines
 570  *
 571  * @adev: amdgpu_device pointer
 572  * @enable: enable/disable the DMA MEs.
 573  *
 574  * Halt or unhalt the async dma engines.
 575  */
 576 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
 577 {
 578         u32 f32_cntl;
 579         int i;
 580
 581         if (!enable) {
 582                 sdma_v5_2_gfx_stop(adev);
 583                 sdma_v5_2_rlc_stop(adev);
 584         }
 585
 586         for (i = 0; i < adev->sdma.num_instances; i++) {
 587                 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 588                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 589                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 590         }
 591 }
 592
 593 /**
 594  * sdma_v5_2_gfx_resume - setup and start the async dma engines
 595  *
 596  * @adev: amdgpu_device pointer
 597  *
 598  * Set up the gfx DMA ring buffers and enable them.
 599  * Returns 0 for success, error for failure.
 600  */
 601 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 602 {
 603         struct amdgpu_ring *ring;
 604         u32 rb_cntl, ib_cntl;
 605         u32 rb_bufsz;
 606         u32 wb_offset;
 607         u32 doorbell;
 608         u32 doorbell_offset;
 609         u32 temp;
 610         u32 wptr_poll_cntl;
 611         u64 wptr_gpu_addr;
 612         int i, r;
 613
 614         for (i = 0; i < adev->sdma.num_instances; i++) {
 615                 ring = &adev->sdma.instance[i].ring;
 616                 wb_offset = (ring->rptr_offs * 4);
 617
 618                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 619
 620                 /* Set ring buffer size in dwords */
 621                 rb_bufsz = order_base_2(ring->ring_size / 4);
 622                 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 623                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 624 #ifdef __BIG_ENDIAN
 625                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 626                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 627                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 628 #endif
 629                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 630
 631                 /* Initialize the ring buffer's read and write pointers */
 632                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 633                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 634                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 635                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 636
 637                 /* setup the wptr shadow polling */
 638                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 639                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 640                        lower_32_bits(wptr_gpu_addr));
 641                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 642                        upper_32_bits(wptr_gpu_addr));
 643                 wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i,
 644                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 645                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 646                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 647                                                F32_POLL_ENABLE, 1);
 648                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 649                        wptr_poll_cntl);
 650
 651                 /* set the wb address whether it's enabled or not */
 652                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 653                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 654                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 655                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 656
 657                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 658
 659                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 660                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 661
 662                 ring->wptr = 0;
 663
 664                 /* before programing wptr to a less value, need set minor_ptr_update first */
 665                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 666
 667                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 668                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 669                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 670                 }
 671
 672                 doorbell = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 673                 doorbell_offset = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 674
 675                 if (ring->use_doorbell) {
 676                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 677                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 678                                         OFFSET, ring->doorbell_index);
 679                 } else {
 680                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 681                 }
 682                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 683                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 684
 685                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 686                                                       ring->doorbell_index,
 687                                                       adev->doorbell_index.sdma_doorbell_range);
 688
 689                 if (amdgpu_sriov_vf(adev))
 690                         sdma_v5_2_ring_set_wptr(ring);
 691
 692                 /* set minor_ptr_update to 0 after wptr programed */
 693                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 694
 695                 /* set utc l1 enable flag always to 1 */
 696                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 697                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 698
 699                 /* enable MCBP */
 700                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 701                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 702
 703                 /* Set up RESP_MODE to non-copy addresses */
 704                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 705                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 706                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 707                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 708
 709                 /* program default cache read and write policy */
 710                 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 711                 /* clean read policy and write policy bits */
 712                 temp &= 0xFF0FFF;
 713                 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 714                          (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
 715                          SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
 716                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 717
 718                 if (!amdgpu_sriov_vf(adev)) {
 719                         /* unhalt engine */
 720                         temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 721                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 722                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 723                 }
 724
 725                 /* enable DMA RB */
 726                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 727                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 728
 729                 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 730                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 731 #ifdef __BIG_ENDIAN
 732                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 733 #endif
 734                 /* enable DMA IBs */
 735                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 736
 737                 ring->sched.ready = true;
 738
 739                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 740                         sdma_v5_2_ctx_switch_enable(adev, true);
 741                         sdma_v5_2_enable(adev, true);
 742                 }
 743
 744                 r = amdgpu_ring_test_ring(ring);
 745                 if (r) {
 746                         ring->sched.ready = false;
 747                         return r;
 748                 }
 749
 750                 if (adev->mman.buffer_funcs_ring == ring)
 751                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 752         }
 753
 754         return 0;
 755 }
 756
 757 /**
 758  * sdma_v5_2_rlc_resume - setup and start the async dma engines
 759  *
 760  * @adev: amdgpu_device pointer
 761  *
 762  * Set up the compute DMA queues and enable them.
 763  * Returns 0 for success, error for failure.
 764  */
 765 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
 766 {
 767         return 0;
 768 }
 769
 770 /**
 771  * sdma_v5_2_load_microcode - load the sDMA ME ucode
 772  *
 773  * @adev: amdgpu_device pointer
 774  *
 775  * Loads the sDMA0/1/2/3 ucode.
 776  * Returns 0 for success, -EINVAL if the ucode is not available.
 777  */
 778 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
 779 {
 780         const struct sdma_firmware_header_v1_0 *hdr;
 781         const __le32 *fw_data;
 782         u32 fw_size;
 783         int i, j;
 784
 785         /* halt the MEs */
 786         sdma_v5_2_enable(adev, false);
 787
 788         for (i = 0; i < adev->sdma.num_instances; i++) {
 789                 if (!adev->sdma.instance[i].fw)
 790                         return -EINVAL;
 791
 792                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 793                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 794                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 795
 796                 fw_data = (const __le32 *)
 797                         (adev->sdma.instance[i].fw->data +
 798                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 799
 800                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 801
 802                 for (j = 0; j < fw_size; j++) {
 803                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 804                                 msleep(1);
 805                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 806                 }
 807
 808                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 809         }
 810
 811         return 0;
 812 }
 813
 814 static int sdma_v5_2_soft_reset(void *handle)
 815 {
 816         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 817         u32 grbm_soft_reset;
 818         u32 tmp;
 819         int i;
 820
 821         for (i = 0; i < adev->sdma.num_instances; i++) {
 822                 grbm_soft_reset = REG_SET_FIELD(0,
 823                                                 GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
 824                                                 1);
 825                 grbm_soft_reset <<= i;
 826
 827                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 828                 tmp |= grbm_soft_reset;
 829                 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
 830                 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 831                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 832
 833                 udelay(50);
 834
 835                 tmp &= ~grbm_soft_reset;
 836                 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 837                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 838
 839                 udelay(50);
 840         }
 841
 842         return 0;
 843 }
 844
 845 /**
 846  * sdma_v5_2_start - setup and start the async dma engines
 847  *
 848  * @adev: amdgpu_device pointer
 849  *
 850  * Set up the DMA engines and enable them.
 851  * Returns 0 for success, error for failure.
 852  */
 853 static int sdma_v5_2_start(struct amdgpu_device *adev)
 854 {
 855         int r = 0;
 856
 857         if (amdgpu_sriov_vf(adev)) {
 858                 sdma_v5_2_ctx_switch_enable(adev, false);
 859                 sdma_v5_2_enable(adev, false);
 860
 861                 /* set RB registers */
 862                 r = sdma_v5_2_gfx_resume(adev);
 863                 return r;
 864         }
 865
 866         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 867                 r = sdma_v5_2_load_microcode(adev);
 868                 if (r)
 869                         return r;
 870
 871                 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
 872                 if (amdgpu_emu_mode == 1)
 873                         msleep(1000);
 874         }
 875
 876         sdma_v5_2_soft_reset(adev);
 877         /* unhalt the MEs */
 878         sdma_v5_2_enable(adev, true);
 879         /* enable sdma ring preemption */
 880         sdma_v5_2_ctx_switch_enable(adev, true);
 881
 882         /* start the gfx rings and rlc compute queues */
 883         r = sdma_v5_2_gfx_resume(adev);
 884         if (r)
 885                 return r;
 886         r = sdma_v5_2_rlc_resume(adev);
 887
 888         return r;
 889 }
 890
 891 /**
 892  * sdma_v5_2_ring_test_ring - simple async dma engine test
 893  *
 894  * @ring: amdgpu_ring structure holding ring information
 895  *
 896  * Test the DMA engine by writing using it to write an
 897  * value to memory.
 898  * Returns 0 for success, error for failure.
 899  */
 900 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
 901 {
 902         struct amdgpu_device *adev = ring->adev;
 903         unsigned i;
 904         unsigned index;
 905         int r;
 906         u32 tmp;
 907         u64 gpu_addr;
 908
 909         r = amdgpu_device_wb_get(adev, &index);
 910         if (r) {
 911                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 912                 return r;
 913         }
 914
 915         gpu_addr = adev->wb.gpu_addr + (index * 4);
 916         tmp = 0xCAFEDEAD;
 917         adev->wb.wb[index] = cpu_to_le32(tmp);
 918
 919         r = amdgpu_ring_alloc(ring, 5);
 920         if (r) {
 921                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 922                 amdgpu_device_wb_free(adev, index);
 923                 return r;
 924         }
 925
 926         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 927                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 928         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 929         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 930         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 931         amdgpu_ring_write(ring, 0xDEADBEEF);
 932         amdgpu_ring_commit(ring);
 933
 934         for (i = 0; i < adev->usec_timeout; i++) {
 935                 tmp = le32_to_cpu(adev->wb.wb[index]);
 936                 if (tmp == 0xDEADBEEF)
 937                         break;
 938                 if (amdgpu_emu_mode == 1)
 939                         msleep(1);
 940                 else
 941                         udelay(1);
 942         }
 943
 944         if (i >= adev->usec_timeout)
 945                 r = -ETIMEDOUT;
 946
 947         amdgpu_device_wb_free(adev, index);
 948
 949         return r;
 950 }
 951
 952 /**
 953  * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
 954  *
 955  * @ring: amdgpu_ring structure holding ring information
 956  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 957  *
 958  * Test a simple IB in the DMA ring.
 959  * Returns 0 on success, error on failure.
 960  */
 961 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 962 {
 963         struct amdgpu_device *adev = ring->adev;
 964         struct amdgpu_ib ib;
 965         struct dma_fence *f = NULL;
 966         unsigned index;
 967         long r;
 968         u32 tmp = 0;
 969         u64 gpu_addr;
 970
 971         r = amdgpu_device_wb_get(adev, &index);
 972         if (r) {
 973                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 974                 return r;
 975         }
 976
 977         gpu_addr = adev->wb.gpu_addr + (index * 4);
 978         tmp = 0xCAFEDEAD;
 979         adev->wb.wb[index] = cpu_to_le32(tmp);
 980         memset(&ib, 0, sizeof(ib));
 981         r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
 982         if (r) {
 983                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 984                 goto err0;
 985         }
 986
 987         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 988                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 989         ib.ptr[1] = lower_32_bits(gpu_addr);
 990         ib.ptr[2] = upper_32_bits(gpu_addr);
 991         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 992         ib.ptr[4] = 0xDEADBEEF;
 993         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 994         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 995         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 996         ib.length_dw = 8;
 997
 998         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 999         if (r)
1000                 goto err1;
1001
1002         r = dma_fence_wait_timeout(f, false, timeout);
1003         if (r == 0) {
1004                 DRM_ERROR("amdgpu: IB test timed out\n");
1005                 r = -ETIMEDOUT;
1006                 goto err1;
1007         } else if (r < 0) {
1008                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1009                 goto err1;
1010         }
1011         tmp = le32_to_cpu(adev->wb.wb[index]);
1012         if (tmp == 0xDEADBEEF)
1013                 r = 0;
1014         else
1015                 r = -EINVAL;
1016
1017 err1:
1018         amdgpu_ib_free(adev, &ib, NULL);
1019         dma_fence_put(f);
1020 err0:
1021         amdgpu_device_wb_free(adev, index);
1022         return r;
1023 }
1024
1025
1026 /**
1027  * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
1028  *
1029  * @ib: indirect buffer to fill with commands
1030  * @pe: addr of the page entry
1031  * @src: src addr to copy from
1032  * @count: number of page entries to update
1033  *
1034  * Update PTEs by copying them from the GART using sDMA.
1035  */
1036 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1037                                   uint64_t pe, uint64_t src,
1038                                   unsigned count)
1039 {
1040         unsigned bytes = count * 8;
1041
1042         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1043                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1044         ib->ptr[ib->length_dw++] = bytes - 1;
1045         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1046         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1047         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1048         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1049         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1050
1051 }
1052
1053 /**
1054  * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1055  *
1056  * @ib: indirect buffer to fill with commands
1057  * @pe: addr of the page entry
1058  * @value: dst addr to write into pe
1059  * @count: number of page entries to update
1060  * @incr: increase next addr by incr bytes
1061  *
1062  * Update PTEs by writing them manually using sDMA.
1063  */
1064 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1065                                    uint64_t value, unsigned count,
1066                                    uint32_t incr)
1067 {
1068         unsigned ndw = count * 2;
1069
1070         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1071                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1072         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1073         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1074         ib->ptr[ib->length_dw++] = ndw - 1;
1075         for (; ndw > 0; ndw -= 2) {
1076                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1077                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1078                 value += incr;
1079         }
1080 }
1081
1082 /**
1083  * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1084  *
1085  * @ib: indirect buffer to fill with commands
1086  * @pe: addr of the page entry
1087  * @addr: dst addr to write into pe
1088  * @count: number of page entries to update
1089  * @incr: increase next addr by incr bytes
1090  * @flags: access flags
1091  *
1092  * Update the page tables using sDMA.
1093  */
1094 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1095                                      uint64_t pe,
1096                                      uint64_t addr, unsigned count,
1097                                      uint32_t incr, uint64_t flags)
1098 {
1099         /* for physically contiguous pages (vram) */
1100         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1101         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1102         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1103         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1104         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1105         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1106         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1107         ib->ptr[ib->length_dw++] = incr; /* increment size */
1108         ib->ptr[ib->length_dw++] = 0;
1109         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1110 }
1111
1112 /**
1113  * sdma_v5_2_ring_pad_ib - pad the IB
1114  *
1115  * @ib: indirect buffer to fill with padding
1116  * @ring: amdgpu_ring structure holding ring information
1117  *
1118  * Pad the IB with NOPs to a boundary multiple of 8.
1119  */
1120 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1121 {
1122         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1123         u32 pad_count;
1124         int i;
1125
1126         pad_count = (-ib->length_dw) & 0x7;
1127         for (i = 0; i < pad_count; i++)
1128                 if (sdma && sdma->burst_nop && (i == 0))
1129                         ib->ptr[ib->length_dw++] =
1130                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1131                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1132                 else
1133                         ib->ptr[ib->length_dw++] =
1134                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1135 }
1136
1137
1138 /**
1139  * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1140  *
1141  * @ring: amdgpu_ring pointer
1142  *
1143  * Make sure all previous operations are completed (CIK).
1144  */
1145 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1146 {
1147         uint32_t seq = ring->fence_drv.sync_seq;
1148         uint64_t addr = ring->fence_drv.gpu_addr;
1149
1150         /* wait for idle */
1151         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1152                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1153                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1154                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1155         amdgpu_ring_write(ring, addr & 0xfffffffc);
1156         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1157         amdgpu_ring_write(ring, seq); /* reference */
1158         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1159         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1160                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1161 }
1162
1163
1164 /**
1165  * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1166  *
1167  * @ring: amdgpu_ring pointer
1168  * @vmid: vmid number to use
1169  * @pd_addr: address
1170  *
1171  * Update the page table base and flush the VM TLB
1172  * using sDMA.
1173  */
1174 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1175                                          unsigned vmid, uint64_t pd_addr)
1176 {
1177         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1178 }
1179
1180 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1181                                      uint32_t reg, uint32_t val)
1182 {
1183         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1184                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1185         amdgpu_ring_write(ring, reg);
1186         amdgpu_ring_write(ring, val);
1187 }
1188
1189 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1190                                          uint32_t val, uint32_t mask)
1191 {
1192         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1193                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1194                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1195         amdgpu_ring_write(ring, reg << 2);
1196         amdgpu_ring_write(ring, 0);
1197         amdgpu_ring_write(ring, val); /* reference */
1198         amdgpu_ring_write(ring, mask); /* mask */
1199         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1200                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1201 }
1202
1203 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1204                                                    uint32_t reg0, uint32_t reg1,
1205                                                    uint32_t ref, uint32_t mask)
1206 {
1207         amdgpu_ring_emit_wreg(ring, reg0, ref);
1208         /* wait for a cycle to reset vm_inv_eng*_ack */
1209         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1210         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1211 }
1212
1213 static int sdma_v5_2_early_init(void *handle)
1214 {
1215         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1216
1217         switch (adev->asic_type) {
1218         case CHIP_SIENNA_CICHLID:
1219                 adev->sdma.num_instances = 4;
1220                 break;
1221         case CHIP_NAVY_FLOUNDER:
1222         case CHIP_DIMGREY_CAVEFISH:
1223                 adev->sdma.num_instances = 2;
1224                 break;
1225         case CHIP_VANGOGH:
1226                 adev->sdma.num_instances = 1;
1227                 break;
1228         default:
1229                 break;
1230         }
1231
1232         sdma_v5_2_set_ring_funcs(adev);
1233         sdma_v5_2_set_buffer_funcs(adev);
1234         sdma_v5_2_set_vm_pte_funcs(adev);
1235         sdma_v5_2_set_irq_funcs(adev);
1236
1237         return 0;
1238 }
1239
1240 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1241 {
1242         switch (seq_num) {
1243         case 0:
1244                 return SOC15_IH_CLIENTID_SDMA0;
1245         case 1:
1246                 return SOC15_IH_CLIENTID_SDMA1;
1247         case 2:
1248                 return SOC15_IH_CLIENTID_SDMA2;
1249         case 3:
1250                 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1251         default:
1252                 break;
1253         }
1254         return -EINVAL;
1255 }
1256
1257 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1258 {
1259         switch (seq_num) {
1260         case 0:
1261                 return SDMA0_5_0__SRCID__SDMA_TRAP;
1262         case 1:
1263                 return SDMA1_5_0__SRCID__SDMA_TRAP;
1264         case 2:
1265                 return SDMA2_5_0__SRCID__SDMA_TRAP;
1266         case 3:
1267                 return SDMA3_5_0__SRCID__SDMA_TRAP;
1268         default:
1269                 break;
1270         }
1271         return -EINVAL;
1272 }
1273
1274 static int sdma_v5_2_sw_init(void *handle)
1275 {
1276         struct amdgpu_ring *ring;
1277         int r, i;
1278         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1279
1280         /* SDMA trap event */
1281         for (i = 0; i < adev->sdma.num_instances; i++) {
1282                 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1283                                       sdma_v5_2_seq_to_trap_id(i),
1284                                       &adev->sdma.trap_irq);
1285                 if (r)
1286                         return r;
1287         }
1288
1289         r = sdma_v5_2_init_microcode(adev);
1290         if (r) {
1291                 DRM_ERROR("Failed to load sdma firmware!\n");
1292                 return r;
1293         }
1294
1295         for (i = 0; i < adev->sdma.num_instances; i++) {
1296                 ring = &adev->sdma.instance[i].ring;
1297                 ring->ring_obj = NULL;
1298                 ring->use_doorbell = true;
1299                 ring->me = i;
1300
1301                 DRM_INFO("use_doorbell being set to: [%s]\n",
1302                                 ring->use_doorbell?"true":"false");
1303
1304                 ring->doorbell_index =
1305                         (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1306
1307                 sprintf(ring->name, "sdma%d", i);
1308                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1309                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1310                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1311                 if (r)
1312                         return r;
1313         }
1314
1315         return r;
1316 }
1317
1318 static int sdma_v5_2_sw_fini(void *handle)
1319 {
1320         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1321         int i;
1322
1323         for (i = 0; i < adev->sdma.num_instances; i++)
1324                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1325
1326         sdma_v5_2_destroy_inst_ctx(adev);
1327
1328         return 0;
1329 }
1330
1331 static int sdma_v5_2_hw_init(void *handle)
1332 {
1333         int r;
1334         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1335
1336         sdma_v5_2_init_golden_registers(adev);
1337
1338         r = sdma_v5_2_start(adev);
1339
1340         return r;
1341 }
1342
1343 static int sdma_v5_2_hw_fini(void *handle)
1344 {
1345         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1346
1347         if (amdgpu_sriov_vf(adev))
1348                 return 0;
1349
1350         sdma_v5_2_ctx_switch_enable(adev, false);
1351         sdma_v5_2_enable(adev, false);
1352
1353         return 0;
1354 }
1355
1356 static int sdma_v5_2_suspend(void *handle)
1357 {
1358         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1359
1360         return sdma_v5_2_hw_fini(adev);
1361 }
1362
1363 static int sdma_v5_2_resume(void *handle)
1364 {
1365         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1366
1367         return sdma_v5_2_hw_init(adev);
1368 }
1369
1370 static bool sdma_v5_2_is_idle(void *handle)
1371 {
1372         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1373         u32 i;
1374
1375         for (i = 0; i < adev->sdma.num_instances; i++) {
1376                 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1377
1378                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1379                         return false;
1380         }
1381
1382         return true;
1383 }
1384
1385 static int sdma_v5_2_wait_for_idle(void *handle)
1386 {
1387         unsigned i;
1388         u32 sdma0, sdma1, sdma2, sdma3;
1389         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1390
1391         for (i = 0; i < adev->usec_timeout; i++) {
1392                 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1393                 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1394                 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1395                 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1396
1397                 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1398                         return 0;
1399                 udelay(1);
1400         }
1401         return -ETIMEDOUT;
1402 }
1403
1404 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1405 {
1406         int i, r = 0;
1407         struct amdgpu_device *adev = ring->adev;
1408         u32 index = 0;
1409         u64 sdma_gfx_preempt;
1410
1411         amdgpu_sdma_get_index_from_ring(ring, &index);
1412         sdma_gfx_preempt =
1413                 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1414
1415         /* assert preemption condition */
1416         amdgpu_ring_set_preempt_cond_exec(ring, false);
1417
1418         /* emit the trailing fence */
1419         ring->trail_seq += 1;
1420         amdgpu_ring_alloc(ring, 10);
1421         sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1422                                   ring->trail_seq, 0);
1423         amdgpu_ring_commit(ring);
1424
1425         /* assert IB preemption */
1426         WREG32(sdma_gfx_preempt, 1);
1427
1428         /* poll the trailing fence */
1429         for (i = 0; i < adev->usec_timeout; i++) {
1430                 if (ring->trail_seq ==
1431                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1432                         break;
1433                 udelay(1);
1434         }
1435
1436         if (i >= adev->usec_timeout) {
1437                 r = -EINVAL;
1438                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1439         }
1440
1441         /* deassert IB preemption */
1442         WREG32(sdma_gfx_preempt, 0);
1443
1444         /* deassert the preemption condition */
1445         amdgpu_ring_set_preempt_cond_exec(ring, true);
1446         return r;
1447 }
1448
1449 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1450                                         struct amdgpu_irq_src *source,
1451                                         unsigned type,
1452                                         enum amdgpu_interrupt_state state)
1453 {
1454         u32 sdma_cntl;
1455
1456         u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1457
1458         sdma_cntl = RREG32(reg_offset);
1459         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1460                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1461         WREG32(reg_offset, sdma_cntl);
1462
1463         return 0;
1464 }
1465
1466 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1467                                       struct amdgpu_irq_src *source,
1468                                       struct amdgpu_iv_entry *entry)
1469 {
1470         DRM_DEBUG("IH: SDMA trap\n");
1471         switch (entry->client_id) {
1472         case SOC15_IH_CLIENTID_SDMA0:
1473                 switch (entry->ring_id) {
1474                 case 0:
1475                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1476                         break;
1477                 case 1:
1478                         /* XXX compute */
1479                         break;
1480                 case 2:
1481                         /* XXX compute */
1482                         break;
1483                 case 3:
1484                         /* XXX page queue*/
1485                         break;
1486                 }
1487                 break;
1488         case SOC15_IH_CLIENTID_SDMA1:
1489                 switch (entry->ring_id) {
1490                 case 0:
1491                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1492                         break;
1493                 case 1:
1494                         /* XXX compute */
1495                         break;
1496                 case 2:
1497                         /* XXX compute */
1498                         break;
1499                 case 3:
1500                         /* XXX page queue*/
1501                         break;
1502                 }
1503                 break;
1504         case SOC15_IH_CLIENTID_SDMA2:
1505                 switch (entry->ring_id) {
1506                 case 0:
1507                         amdgpu_fence_process(&adev->sdma.instance[2].ring);
1508                         break;
1509                 case 1:
1510                         /* XXX compute */
1511                         break;
1512                 case 2:
1513                         /* XXX compute */
1514                         break;
1515                 case 3:
1516                         /* XXX page queue*/
1517                         break;
1518                 }
1519                 break;
1520         case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1521                 switch (entry->ring_id) {
1522                 case 0:
1523                         amdgpu_fence_process(&adev->sdma.instance[3].ring);
1524                         break;
1525                 case 1:
1526                         /* XXX compute */
1527                         break;
1528                 case 2:
1529                         /* XXX compute */
1530                         break;
1531                 case 3:
1532                         /* XXX page queue*/
1533                         break;
1534                 }
1535                 break;
1536         }
1537         return 0;
1538 }
1539
1540 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1541                                               struct amdgpu_irq_src *source,
1542                                               struct amdgpu_iv_entry *entry)
1543 {
1544         return 0;
1545 }
1546
1547 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1548                                                        bool enable)
1549 {
1550         uint32_t data, def;
1551         int i;
1552
1553         for (i = 0; i < adev->sdma.num_instances; i++) {
1554                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1555                         /* Enable sdma clock gating */
1556                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1557                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1558                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1559                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1560                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1561                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1562                                   SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1563                         if (def != data)
1564                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1565                 } else {
1566                         /* Disable sdma clock gating */
1567                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1568                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1569                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1570                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1571                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1572                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1573                                  SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1574                         if (def != data)
1575                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1576                 }
1577         }
1578 }
1579
1580 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1581                                                       bool enable)
1582 {
1583         uint32_t data, def;
1584         int i;
1585
1586         for (i = 0; i < adev->sdma.num_instances; i++) {
1587                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1588                         /* Enable sdma mem light sleep */
1589                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1590                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1591                         if (def != data)
1592                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1593
1594                 } else {
1595                         /* Disable sdma mem light sleep */
1596                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1597                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1598                         if (def != data)
1599                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1600
1601                 }
1602         }
1603 }
1604
1605 static int sdma_v5_2_set_clockgating_state(void *handle,
1606                                            enum amd_clockgating_state state)
1607 {
1608         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1609
1610         if (amdgpu_sriov_vf(adev))
1611                 return 0;
1612
1613         switch (adev->asic_type) {
1614         case CHIP_SIENNA_CICHLID:
1615         case CHIP_NAVY_FLOUNDER:
1616         case CHIP_VANGOGH:
1617         case CHIP_DIMGREY_CAVEFISH:
1618                 sdma_v5_2_update_medium_grain_clock_gating(adev,
1619                                 state == AMD_CG_STATE_GATE);
1620                 sdma_v5_2_update_medium_grain_light_sleep(adev,
1621                                 state == AMD_CG_STATE_GATE);
1622                 break;
1623         default:
1624                 break;
1625         }
1626
1627         return 0;
1628 }
1629
1630 static int sdma_v5_2_set_powergating_state(void *handle,
1631                                           enum amd_powergating_state state)
1632 {
1633         return 0;
1634 }
1635
1636 static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
1637 {
1638         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1639         int data;
1640
1641         if (amdgpu_sriov_vf(adev))
1642                 *flags = 0;
1643
1644         /* AMD_CG_SUPPORT_SDMA_LS */
1645         data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1646         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1647                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1648 }
1649
1650 const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1651         .name = "sdma_v5_2",
1652         .early_init = sdma_v5_2_early_init,
1653         .late_init = NULL,
1654         .sw_init = sdma_v5_2_sw_init,
1655         .sw_fini = sdma_v5_2_sw_fini,
1656         .hw_init = sdma_v5_2_hw_init,
1657         .hw_fini = sdma_v5_2_hw_fini,
1658         .suspend = sdma_v5_2_suspend,
1659         .resume = sdma_v5_2_resume,
1660         .is_idle = sdma_v5_2_is_idle,
1661         .wait_for_idle = sdma_v5_2_wait_for_idle,
1662         .soft_reset = sdma_v5_2_soft_reset,
1663         .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1664         .set_powergating_state = sdma_v5_2_set_powergating_state,
1665         .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1666 };
1667
1668 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1669         .type = AMDGPU_RING_TYPE_SDMA,
1670         .align_mask = 0xf,
1671         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1672         .support_64bit_ptrs = true,
1673         .vmhub = AMDGPU_GFXHUB_0,
1674         .get_rptr = sdma_v5_2_ring_get_rptr,
1675         .get_wptr = sdma_v5_2_ring_get_wptr,
1676         .set_wptr = sdma_v5_2_ring_set_wptr,
1677         .emit_frame_size =
1678                 5 + /* sdma_v5_2_ring_init_cond_exec */
1679                 6 + /* sdma_v5_2_ring_emit_hdp_flush */
1680                 3 + /* hdp_invalidate */
1681                 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1682                 /* sdma_v5_2_ring_emit_vm_flush */
1683                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1684                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1685                 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1686         .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1687         .emit_ib = sdma_v5_2_ring_emit_ib,
1688         .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,
1689         .emit_fence = sdma_v5_2_ring_emit_fence,
1690         .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1691         .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1692         .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1693         .test_ring = sdma_v5_2_ring_test_ring,
1694         .test_ib = sdma_v5_2_ring_test_ib,
1695         .insert_nop = sdma_v5_2_ring_insert_nop,
1696         .pad_ib = sdma_v5_2_ring_pad_ib,
1697         .emit_wreg = sdma_v5_2_ring_emit_wreg,
1698         .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1699         .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1700         .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1701         .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1702         .preempt_ib = sdma_v5_2_ring_preempt_ib,
1703 };
1704
1705 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1706 {
1707         int i;
1708
1709         for (i = 0; i < adev->sdma.num_instances; i++) {
1710                 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1711                 adev->sdma.instance[i].ring.me = i;
1712         }
1713 }
1714
1715 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1716         .set = sdma_v5_2_set_trap_irq_state,
1717         .process = sdma_v5_2_process_trap_irq,
1718 };
1719
1720 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1721         .process = sdma_v5_2_process_illegal_inst_irq,
1722 };
1723
1724 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1725 {
1726         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1727                                         adev->sdma.num_instances;
1728         adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1729         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1730 }
1731
1732 /**
1733  * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1734  *
1735  * @ib: indirect buffer to copy to
1736  * @src_offset: src GPU address
1737  * @dst_offset: dst GPU address
1738  * @byte_count: number of bytes to xfer
1739  * @tmz: if a secure copy should be used
1740  *
1741  * Copy GPU buffers using the DMA engine.
1742  * Used by the amdgpu ttm implementation to move pages if
1743  * registered as the asic copy callback.
1744  */
1745 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1746                                        uint64_t src_offset,
1747                                        uint64_t dst_offset,
1748                                        uint32_t byte_count,
1749                                        bool tmz)
1750 {
1751         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1752                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1753                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1754         ib->ptr[ib->length_dw++] = byte_count - 1;
1755         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1756         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1757         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1758         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1759         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1760 }
1761
1762 /**
1763  * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1764  *
1765  * @ib: indirect buffer to fill
1766  * @src_data: value to write to buffer
1767  * @dst_offset: dst GPU address
1768  * @byte_count: number of bytes to xfer
1769  *
1770  * Fill GPU buffers using the DMA engine.
1771  */
1772 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1773                                        uint32_t src_data,
1774                                        uint64_t dst_offset,
1775                                        uint32_t byte_count)
1776 {
1777         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1778         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1779         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1780         ib->ptr[ib->length_dw++] = src_data;
1781         ib->ptr[ib->length_dw++] = byte_count - 1;
1782 }
1783
1784 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1785         .copy_max_bytes = 0x400000,
1786         .copy_num_dw = 7,
1787         .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1788
1789         .fill_max_bytes = 0x400000,
1790         .fill_num_dw = 5,
1791         .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1792 };
1793
1794 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1795 {
1796         if (adev->mman.buffer_funcs == NULL) {
1797                 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1798                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1799         }
1800 }
1801
1802 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1803         .copy_pte_num_dw = 7,
1804         .copy_pte = sdma_v5_2_vm_copy_pte,
1805         .write_pte = sdma_v5_2_vm_write_pte,
1806         .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1807 };
1808
1809 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1810 {
1811         unsigned i;
1812
1813         if (adev->vm_manager.vm_pte_funcs == NULL) {
1814                 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1815                 for (i = 0; i < adev->sdma.num_instances; i++) {
1816                         adev->vm_manager.vm_pte_scheds[i] =
1817                                 &adev->sdma.instance[i].ring.sched;
1818                 }
1819                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1820         }
1821 }
1822
1823 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1824         .type = AMD_IP_BLOCK_TYPE_SDMA,
1825         .major = 5,
1826         .minor = 2,
1827         .rev = 0,
1828         .funcs = &sdma_v5_2_ip_funcs,
1829 };