drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_xcp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_trace.h"
  33
  34 #include "sdma/sdma_4_4_2_offset.h"
  35 #include "sdma/sdma_4_4_2_sh_mask.h"
  36
  37 #include "soc15_common.h"
  38 #include "soc15.h"
  39 #include "vega10_sdma_pkt_open.h"
  40
  41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
  42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
  43
  44 #include "amdgpu_ras.h"
  45
  46 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin");
  47
  48 #define mmSMNAID_AID0_MCA_SMU 0x03b30400
  49
  50 #define WREG32_SDMA(instance, offset, value) \
  51         WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value)
  52 #define RREG32_SDMA(instance, offset) \
  53         RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)))
  54
  55 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev);
  56 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev);
  57 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev);
  58 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev);
  59 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev);
  60
  61 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev,
  62                 u32 instance, u32 offset)
  63 {
  64         u32 dev_inst = GET_INST(SDMA0, instance);
  65
  66         return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset);
  67 }
  68
  69 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num)
  70 {
  71         switch (seq_num) {
  72         case 0:
  73                 return SOC15_IH_CLIENTID_SDMA0;
  74         case 1:
  75                 return SOC15_IH_CLIENTID_SDMA1;
  76         case 2:
  77                 return SOC15_IH_CLIENTID_SDMA2;
  78         case 3:
  79                 return SOC15_IH_CLIENTID_SDMA3;
  80         default:
  81                 return -EINVAL;
  82         }
  83 }
  84
  85 static int sdma_v4_4_2_irq_id_to_seq(unsigned client_id)
  86 {
  87         switch (client_id) {
  88         case SOC15_IH_CLIENTID_SDMA0:
  89                 return 0;
  90         case SOC15_IH_CLIENTID_SDMA1:
  91                 return 1;
  92         case SOC15_IH_CLIENTID_SDMA2:
  93                 return 2;
  94         case SOC15_IH_CLIENTID_SDMA3:
  95                 return 3;
  96         default:
  97                 return -EINVAL;
  98         }
  99 }
 100
 101 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev,
 102                                                    uint32_t inst_mask)
 103 {
 104         u32 val;
 105         int i;
 106
 107         for (i = 0; i < adev->sdma.num_instances; i++) {
 108                 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG);
 109                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4);
 110                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG,
 111                                     PIPE_INTERLEAVE_SIZE, 0);
 112                 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val);
 113
 114                 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ);
 115                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS,
 116                                     4);
 117                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ,
 118                                     PIPE_INTERLEAVE_SIZE, 0);
 119                 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val);
 120         }
 121 }
 122
 123 /**
 124  * sdma_v4_4_2_init_microcode - load ucode images from disk
 125  *
 126  * @adev: amdgpu_device pointer
 127  *
 128  * Use the firmware interface to load the ucode images into
 129  * the driver (not loaded into hw).
 130  * Returns 0 on success, error on failure.
 131  */
 132 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev)
 133 {
 134         int ret, i;
 135
 136         for (i = 0; i < adev->sdma.num_instances; i++) {
 137                 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) ==
 138                     IP_VERSION(4, 4, 2)) {
 139                         ret = amdgpu_sdma_init_microcode(adev, 0, true);
 140                         break;
 141                 } else {
 142                         ret = amdgpu_sdma_init_microcode(adev, i, false);
 143                         if (ret)
 144                                 return ret;
 145                 }
 146         }
 147
 148         return ret;
 149 }
 150
 151 /**
 152  * sdma_v4_4_2_ring_get_rptr - get the current read pointer
 153  *
 154  * @ring: amdgpu ring pointer
 155  *
 156  * Get the current rptr from the hardware.
 157  */
 158 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring)
 159 {
 160         u64 rptr;
 161
 162         /* XXX check if swapping is necessary on BE */
 163         rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs]));
 164
 165         DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr);
 166         return rptr >> 2;
 167 }
 168
 169 /**
 170  * sdma_v4_4_2_ring_get_wptr - get the current write pointer
 171  *
 172  * @ring: amdgpu ring pointer
 173  *
 174  * Get the current wptr from the hardware.
 175  */
 176 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring)
 177 {
 178         struct amdgpu_device *adev = ring->adev;
 179         u64 wptr;
 180
 181         if (ring->use_doorbell) {
 182                 /* XXX check if swapping is necessary on BE */
 183                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 184                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 185         } else {
 186                 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI);
 187                 wptr = wptr << 32;
 188                 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR);
 189                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
 190                                 ring->me, wptr);
 191         }
 192
 193         return wptr >> 2;
 194 }
 195
 196 /**
 197  * sdma_v4_4_2_ring_set_wptr - commit the write pointer
 198  *
 199  * @ring: amdgpu ring pointer
 200  *
 201  * Write the wptr back to the hardware.
 202  */
 203 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring)
 204 {
 205         struct amdgpu_device *adev = ring->adev;
 206
 207         DRM_DEBUG("Setting write pointer\n");
 208         if (ring->use_doorbell) {
 209                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 210
 211                 DRM_DEBUG("Using doorbell -- "
 212                                 "wptr_offs == 0x%08x "
 213                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 214                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 215                                 ring->wptr_offs,
 216                                 lower_32_bits(ring->wptr << 2),
 217                                 upper_32_bits(ring->wptr << 2));
 218                 /* XXX check if swapping is necessary on BE */
 219                 WRITE_ONCE(*wb, (ring->wptr << 2));
 220                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 221                                 ring->doorbell_index, ring->wptr << 2);
 222                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 223         } else {
 224                 DRM_DEBUG("Not using doorbell -- "
 225                                 "regSDMA%i_GFX_RB_WPTR == 0x%08x "
 226                                 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 227                                 ring->me,
 228                                 lower_32_bits(ring->wptr << 2),
 229                                 ring->me,
 230                                 upper_32_bits(ring->wptr << 2));
 231                 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR,
 232                             lower_32_bits(ring->wptr << 2));
 233                 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI,
 234                             upper_32_bits(ring->wptr << 2));
 235         }
 236 }
 237
 238 /**
 239  * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer
 240  *
 241  * @ring: amdgpu ring pointer
 242  *
 243  * Get the current wptr from the hardware.
 244  */
 245 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring)
 246 {
 247         struct amdgpu_device *adev = ring->adev;
 248         u64 wptr;
 249
 250         if (ring->use_doorbell) {
 251                 /* XXX check if swapping is necessary on BE */
 252                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 253         } else {
 254                 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI);
 255                 wptr = wptr << 32;
 256                 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR);
 257         }
 258
 259         return wptr >> 2;
 260 }
 261
 262 /**
 263  * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer
 264  *
 265  * @ring: amdgpu ring pointer
 266  *
 267  * Write the wptr back to the hardware.
 268  */
 269 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring)
 270 {
 271         struct amdgpu_device *adev = ring->adev;
 272
 273         if (ring->use_doorbell) {
 274                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 275
 276                 /* XXX check if swapping is necessary on BE */
 277                 WRITE_ONCE(*wb, (ring->wptr << 2));
 278                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 279         } else {
 280                 uint64_t wptr = ring->wptr << 2;
 281
 282                 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR,
 283                             lower_32_bits(wptr));
 284                 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI,
 285                             upper_32_bits(wptr));
 286         }
 287 }
 288
 289 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 290 {
 291         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 292         int i;
 293
 294         for (i = 0; i < count; i++)
 295                 if (sdma && sdma->burst_nop && (i == 0))
 296                         amdgpu_ring_write(ring, ring->funcs->nop |
 297                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 298                 else
 299                         amdgpu_ring_write(ring, ring->funcs->nop);
 300 }
 301
 302 /**
 303  * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine
 304  *
 305  * @ring: amdgpu ring pointer
 306  * @job: job to retrieve vmid from
 307  * @ib: IB object to schedule
 308  * @flags: unused
 309  *
 310  * Schedule an IB in the DMA ring.
 311  */
 312 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring,
 313                                    struct amdgpu_job *job,
 314                                    struct amdgpu_ib *ib,
 315                                    uint32_t flags)
 316 {
 317         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 318
 319         /* IB packet must end on a 8 DW boundary */
 320         sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 321
 322         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 323                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 324         /* base must be 32 byte aligned */
 325         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 326         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 327         amdgpu_ring_write(ring, ib->length_dw);
 328         amdgpu_ring_write(ring, 0);
 329         amdgpu_ring_write(ring, 0);
 330
 331 }
 332
 333 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring,
 334                                    int mem_space, int hdp,
 335                                    uint32_t addr0, uint32_t addr1,
 336                                    uint32_t ref, uint32_t mask,
 337                                    uint32_t inv)
 338 {
 339         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 340                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
 341                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
 342                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 343         if (mem_space) {
 344                 /* memory */
 345                 amdgpu_ring_write(ring, addr0);
 346                 amdgpu_ring_write(ring, addr1);
 347         } else {
 348                 /* registers */
 349                 amdgpu_ring_write(ring, addr0 << 2);
 350                 amdgpu_ring_write(ring, addr1 << 2);
 351         }
 352         amdgpu_ring_write(ring, ref); /* reference */
 353         amdgpu_ring_write(ring, mask); /* mask */
 354         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 355                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
 356 }
 357
 358 /**
 359  * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 360  *
 361  * @ring: amdgpu ring pointer
 362  *
 363  * Emit an hdp flush packet on the requested DMA ring.
 364  */
 365 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 366 {
 367         struct amdgpu_device *adev = ring->adev;
 368         u32 ref_and_mask = 0;
 369         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 370
 371         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 372
 373         sdma_v4_4_2_wait_reg_mem(ring, 0, 1,
 374                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
 375                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
 376                                ref_and_mask, ref_and_mask, 10);
 377 }
 378
 379 /**
 380  * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring
 381  *
 382  * @ring: amdgpu ring pointer
 383  * @addr: address
 384  * @seq: sequence number
 385  * @flags: fence related flags
 386  *
 387  * Add a DMA fence packet to the ring to write
 388  * the fence seq number and DMA trap packet to generate
 389  * an interrupt if needed.
 390  */
 391 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 392                                       unsigned flags)
 393 {
 394         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 395         /* write the fence */
 396         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 397         /* zero in first two bits */
 398         BUG_ON(addr & 0x3);
 399         amdgpu_ring_write(ring, lower_32_bits(addr));
 400         amdgpu_ring_write(ring, upper_32_bits(addr));
 401         amdgpu_ring_write(ring, lower_32_bits(seq));
 402
 403         /* optionally write high bits as well */
 404         if (write64bit) {
 405                 addr += 4;
 406                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 407                 /* zero in first two bits */
 408                 BUG_ON(addr & 0x3);
 409                 amdgpu_ring_write(ring, lower_32_bits(addr));
 410                 amdgpu_ring_write(ring, upper_32_bits(addr));
 411                 amdgpu_ring_write(ring, upper_32_bits(seq));
 412         }
 413
 414         /* generate an interrupt */
 415         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 416         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 417 }
 418
 419
 420 /**
 421  * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines
 422  *
 423  * @adev: amdgpu_device pointer
 424  * @inst_mask: mask of dma engine instances to be disabled
 425  *
 426  * Stop the gfx async dma ring buffers.
 427  */
 428 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev,
 429                                       uint32_t inst_mask)
 430 {
 431         struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
 432         u32 doorbell_offset, doorbell;
 433         u32 rb_cntl, ib_cntl;
 434         int i;
 435
 436         for_each_inst(i, inst_mask) {
 437                 sdma[i] = &adev->sdma.instance[i].ring;
 438
 439                 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
 440                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0);
 441                 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
 442                 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
 443                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0);
 444                 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
 445
 446                 if (sdma[i]->use_doorbell) {
 447                         doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
 448                         doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);
 449
 450                         doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0);
 451                         doorbell_offset = REG_SET_FIELD(doorbell_offset,
 452                                         SDMA_GFX_DOORBELL_OFFSET,
 453                                         OFFSET, 0);
 454                         WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell);
 455                         WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset);
 456                 }
 457         }
 458 }
 459
 460 /**
 461  * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines
 462  *
 463  * @adev: amdgpu_device pointer
 464  * @inst_mask: mask of dma engine instances to be disabled
 465  *
 466  * Stop the compute async dma queues.
 467  */
 468 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev,
 469                                       uint32_t inst_mask)
 470 {
 471         /* XXX todo */
 472 }
 473
 474 /**
 475  * sdma_v4_4_2_inst_page_stop - stop the page async dma engines
 476  *
 477  * @adev: amdgpu_device pointer
 478  * @inst_mask: mask of dma engine instances to be disabled
 479  *
 480  * Stop the page async dma ring buffers.
 481  */
 482 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev,
 483                                        uint32_t inst_mask)
 484 {
 485         u32 rb_cntl, ib_cntl;
 486         int i;
 487
 488         for_each_inst(i, inst_mask) {
 489                 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
 490                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
 491                                         RB_ENABLE, 0);
 492                 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
 493                 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
 494                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL,
 495                                         IB_ENABLE, 0);
 496                 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
 497         }
 498 }
 499
 500 /**
 501  * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch
 502  *
 503  * @adev: amdgpu_device pointer
 504  * @enable: enable/disable the DMA MEs context switch.
 505  * @inst_mask: mask of dma engine instances to be enabled
 506  *
 507  * Halt or unhalt the async dma engines context switch.
 508  */
 509 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev,
 510                                                bool enable, uint32_t inst_mask)
 511 {
 512         u32 f32_cntl, phase_quantum = 0;
 513         int i;
 514
 515         if (amdgpu_sdma_phase_quantum) {
 516                 unsigned value = amdgpu_sdma_phase_quantum;
 517                 unsigned unit = 0;
 518
 519                 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
 520                                 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) {
 521                         value = (value + 1) >> 1;
 522                         unit++;
 523                 }
 524                 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
 525                             SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) {
 526                         value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
 527                                  SDMA_PHASE0_QUANTUM__VALUE__SHIFT);
 528                         unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
 529                                 SDMA_PHASE0_QUANTUM__UNIT__SHIFT);
 530                         WARN_ONCE(1,
 531                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 532                                   value << unit);
 533                 }
 534                 phase_quantum =
 535                         value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT |
 536                         unit  << SDMA_PHASE0_QUANTUM__UNIT__SHIFT;
 537         }
 538
 539         for_each_inst(i, inst_mask) {
 540                 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL);
 541                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL,
 542                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 543                 if (enable && amdgpu_sdma_phase_quantum) {
 544                         WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum);
 545                         WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum);
 546                         WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum);
 547                 }
 548                 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl);
 549
 550                 /* Extend page fault timeout to avoid interrupt storm */
 551                 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080);
 552         }
 553 }
 554
 555 /**
 556  * sdma_v4_4_2_inst_enable - stop the async dma engines
 557  *
 558  * @adev: amdgpu_device pointer
 559  * @enable: enable/disable the DMA MEs.
 560  * @inst_mask: mask of dma engine instances to be enabled
 561  *
 562  * Halt or unhalt the async dma engines.
 563  */
 564 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable,
 565                                     uint32_t inst_mask)
 566 {
 567         u32 f32_cntl;
 568         int i;
 569
 570         if (!enable) {
 571                 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask);
 572                 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask);
 573                 if (adev->sdma.has_page_queue)
 574                         sdma_v4_4_2_inst_page_stop(adev, inst_mask);
 575
 576                 /* SDMA FW needs to respond to FREEZE requests during reset.
 577                  * Keep it running during reset */
 578                 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
 579                         return;
 580         }
 581
 582         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
 583                 return;
 584
 585         for_each_inst(i, inst_mask) {
 586                 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL);
 587                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1);
 588                 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl);
 589         }
 590 }
 591
 592 /*
 593  * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl
 594  */
 595 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
 596 {
 597         /* Set ring buffer size in dwords */
 598         uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
 599
 600         barrier(); /* work around https://llvm.org/pr42576 */
 601         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 602 #ifdef __BIG_ENDIAN
 603         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 604         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
 605                                 RPTR_WRITEBACK_SWAP_ENABLE, 1);
 606 #endif
 607         return rb_cntl;
 608 }
 609
 610 /**
 611  * sdma_v4_4_2_gfx_resume - setup and start the async dma engines
 612  *
 613  * @adev: amdgpu_device pointer
 614  * @i: instance to resume
 615  *
 616  * Set up the gfx DMA ring buffers and enable them.
 617  * Returns 0 for success, error for failure.
 618  */
 619 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i)
 620 {
 621         struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
 622         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 623         u32 wb_offset;
 624         u32 doorbell;
 625         u32 doorbell_offset;
 626         u64 wptr_gpu_addr;
 627
 628         wb_offset = (ring->rptr_offs * 4);
 629
 630         rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
 631         rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
 632         WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
 633
 634         /* set the wb address whether it's enabled or not */
 635         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI,
 636                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 637         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO,
 638                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 639
 640         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
 641                                 RPTR_WRITEBACK_ENABLE, 1);
 642
 643         WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8);
 644         WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
 645
 646         ring->wptr = 0;
 647
 648         /* before programing wptr to a less value, need set minor_ptr_update first */
 649         WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1);
 650
 651         /* Initialize the ring buffer's read and write pointers */
 652         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0);
 653         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0);
 654         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0);
 655         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0);
 656
 657         doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
 658         doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);
 659
 660         doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE,
 661                                  ring->use_doorbell);
 662         doorbell_offset = REG_SET_FIELD(doorbell_offset,
 663                                         SDMA_GFX_DOORBELL_OFFSET,
 664                                         OFFSET, ring->doorbell_index);
 665         WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell);
 666         WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset);
 667
 668         sdma_v4_4_2_ring_set_wptr(ring);
 669
 670         /* set minor_ptr_update to 0 after wptr programed */
 671         WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0);
 672
 673         /* setup the wptr shadow polling */
 674         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 675         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO,
 676                     lower_32_bits(wptr_gpu_addr));
 677         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI,
 678                     upper_32_bits(wptr_gpu_addr));
 679         wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL);
 680         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 681                                        SDMA_GFX_RB_WPTR_POLL_CNTL,
 682                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
 683         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
 684
 685         /* enable DMA RB */
 686         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1);
 687         WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
 688
 689         ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
 690         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1);
 691 #ifdef __BIG_ENDIAN
 692         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 693 #endif
 694         /* enable DMA IBs */
 695         WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
 696 }
 697
 698 /**
 699  * sdma_v4_4_2_page_resume - setup and start the async dma engines
 700  *
 701  * @adev: amdgpu_device pointer
 702  * @i: instance to resume
 703  *
 704  * Set up the page DMA ring buffers and enable them.
 705  * Returns 0 for success, error for failure.
 706  */
 707 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i)
 708 {
 709         struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
 710         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 711         u32 wb_offset;
 712         u32 doorbell;
 713         u32 doorbell_offset;
 714         u64 wptr_gpu_addr;
 715
 716         wb_offset = (ring->rptr_offs * 4);
 717
 718         rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
 719         rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
 720         WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
 721
 722         /* Initialize the ring buffer's read and write pointers */
 723         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0);
 724         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0);
 725         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0);
 726         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0);
 727
 728         /* set the wb address whether it's enabled or not */
 729         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI,
 730                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 731         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO,
 732                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 733
 734         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
 735                                 RPTR_WRITEBACK_ENABLE, 1);
 736
 737         WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8);
 738         WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
 739
 740         ring->wptr = 0;
 741
 742         /* before programing wptr to a less value, need set minor_ptr_update first */
 743         WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1);
 744
 745         doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL);
 746         doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET);
 747
 748         doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE,
 749                                  ring->use_doorbell);
 750         doorbell_offset = REG_SET_FIELD(doorbell_offset,
 751                                         SDMA_PAGE_DOORBELL_OFFSET,
 752                                         OFFSET, ring->doorbell_index);
 753         WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell);
 754         WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset);
 755
 756         /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */
 757         sdma_v4_4_2_page_ring_set_wptr(ring);
 758
 759         /* set minor_ptr_update to 0 after wptr programed */
 760         WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0);
 761
 762         /* setup the wptr shadow polling */
 763         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 764         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO,
 765                     lower_32_bits(wptr_gpu_addr));
 766         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI,
 767                     upper_32_bits(wptr_gpu_addr));
 768         wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL);
 769         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 770                                        SDMA_PAGE_RB_WPTR_POLL_CNTL,
 771                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
 772         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
 773
 774         /* enable DMA RB */
 775         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1);
 776         WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
 777
 778         ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
 779         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1);
 780 #ifdef __BIG_ENDIAN
 781         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
 782 #endif
 783         /* enable DMA IBs */
 784         WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
 785 }
 786
 787 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev)
 788 {
 789
 790 }
 791
 792 /**
 793  * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines
 794  *
 795  * @adev: amdgpu_device pointer
 796  * @inst_mask: mask of dma engine instances to be enabled
 797  *
 798  * Set up the compute DMA queues and enable them.
 799  * Returns 0 for success, error for failure.
 800  */
 801 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev,
 802                                        uint32_t inst_mask)
 803 {
 804         sdma_v4_4_2_init_pg(adev);
 805
 806         return 0;
 807 }
 808
 809 /**
 810  * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode
 811  *
 812  * @adev: amdgpu_device pointer
 813  * @inst_mask: mask of dma engine instances to be enabled
 814  *
 815  * Loads the sDMA0/1 ucode.
 816  * Returns 0 for success, -EINVAL if the ucode is not available.
 817  */
 818 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev,
 819                                            uint32_t inst_mask)
 820 {
 821         const struct sdma_firmware_header_v1_0 *hdr;
 822         const __le32 *fw_data;
 823         u32 fw_size;
 824         int i, j;
 825
 826         /* halt the MEs */
 827         sdma_v4_4_2_inst_enable(adev, false, inst_mask);
 828
 829         for_each_inst(i, inst_mask) {
 830                 if (!adev->sdma.instance[i].fw)
 831                         return -EINVAL;
 832
 833                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 834                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 835                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 836
 837                 fw_data = (const __le32 *)
 838                         (adev->sdma.instance[i].fw->data +
 839                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 840
 841                 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0);
 842
 843                 for (j = 0; j < fw_size; j++)
 844                         WREG32_SDMA(i, regSDMA_UCODE_DATA,
 845                                     le32_to_cpup(fw_data++));
 846
 847                 WREG32_SDMA(i, regSDMA_UCODE_ADDR,
 848                             adev->sdma.instance[i].fw_version);
 849         }
 850
 851         return 0;
 852 }
 853
 854 /**
 855  * sdma_v4_4_2_inst_start - setup and start the async dma engines
 856  *
 857  * @adev: amdgpu_device pointer
 858  * @inst_mask: mask of dma engine instances to be enabled
 859  *
 860  * Set up the DMA engines and enable them.
 861  * Returns 0 for success, error for failure.
 862  */
 863 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev,
 864                                   uint32_t inst_mask)
 865 {
 866         struct amdgpu_ring *ring;
 867         uint32_t tmp_mask;
 868         int i, r = 0;
 869
 870         if (amdgpu_sriov_vf(adev)) {
 871                 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
 872                 sdma_v4_4_2_inst_enable(adev, false, inst_mask);
 873         } else {
 874                 /* bypass sdma microcode loading on Gopher */
 875                 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP &&
 876                     adev->sdma.instance[0].fw) {
 877                         r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask);
 878                         if (r)
 879                                 return r;
 880                 }
 881
 882                 /* unhalt the MEs */
 883                 sdma_v4_4_2_inst_enable(adev, true, inst_mask);
 884                 /* enable sdma ring preemption */
 885                 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
 886         }
 887
 888         /* start the gfx rings and rlc compute queues */
 889         tmp_mask = inst_mask;
 890         for_each_inst(i, tmp_mask) {
 891                 uint32_t temp;
 892
 893                 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
 894                 sdma_v4_4_2_gfx_resume(adev, i);
 895                 if (adev->sdma.has_page_queue)
 896                         sdma_v4_4_2_page_resume(adev, i);
 897
 898                 /* set utc l1 enable flag always to 1 */
 899                 temp = RREG32_SDMA(i, regSDMA_CNTL);
 900                 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1);
 901                 /* enable context empty interrupt during initialization */
 902                 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1);
 903                 WREG32_SDMA(i, regSDMA_CNTL, temp);
 904
 905                 if (!amdgpu_sriov_vf(adev)) {
 906                         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 907                                 /* unhalt engine */
 908                                 temp = RREG32_SDMA(i, regSDMA_F32_CNTL);
 909                                 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0);
 910                                 WREG32_SDMA(i, regSDMA_F32_CNTL, temp);
 911                         }
 912                 }
 913         }
 914
 915         if (amdgpu_sriov_vf(adev)) {
 916                 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
 917                 sdma_v4_4_2_inst_enable(adev, true, inst_mask);
 918         } else {
 919                 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask);
 920                 if (r)
 921                         return r;
 922         }
 923
 924         tmp_mask = inst_mask;
 925         for_each_inst(i, tmp_mask) {
 926                 ring = &adev->sdma.instance[i].ring;
 927
 928                 r = amdgpu_ring_test_helper(ring);
 929                 if (r)
 930                         return r;
 931
 932                 if (adev->sdma.has_page_queue) {
 933                         struct amdgpu_ring *page = &adev->sdma.instance[i].page;
 934
 935                         r = amdgpu_ring_test_helper(page);
 936                         if (r)
 937                                 return r;
 938                 }
 939         }
 940
 941         return r;
 942 }
 943
 944 /**
 945  * sdma_v4_4_2_ring_test_ring - simple async dma engine test
 946  *
 947  * @ring: amdgpu_ring structure holding ring information
 948  *
 949  * Test the DMA engine by writing using it to write an
 950  * value to memory.
 951  * Returns 0 for success, error for failure.
 952  */
 953 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring)
 954 {
 955         struct amdgpu_device *adev = ring->adev;
 956         unsigned i;
 957         unsigned index;
 958         int r;
 959         u32 tmp;
 960         u64 gpu_addr;
 961
 962         r = amdgpu_device_wb_get(adev, &index);
 963         if (r)
 964                 return r;
 965
 966         gpu_addr = adev->wb.gpu_addr + (index * 4);
 967         tmp = 0xCAFEDEAD;
 968         adev->wb.wb[index] = cpu_to_le32(tmp);
 969
 970         r = amdgpu_ring_alloc(ring, 5);
 971         if (r)
 972                 goto error_free_wb;
 973
 974         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 975                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 976         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 977         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 978         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 979         amdgpu_ring_write(ring, 0xDEADBEEF);
 980         amdgpu_ring_commit(ring);
 981
 982         for (i = 0; i < adev->usec_timeout; i++) {
 983                 tmp = le32_to_cpu(adev->wb.wb[index]);
 984                 if (tmp == 0xDEADBEEF)
 985                         break;
 986                 udelay(1);
 987         }
 988
 989         if (i >= adev->usec_timeout)
 990                 r = -ETIMEDOUT;
 991
 992 error_free_wb:
 993         amdgpu_device_wb_free(adev, index);
 994         return r;
 995 }
 996
 997 /**
 998  * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine
 999  *
1000  * @ring: amdgpu_ring structure holding ring information
1001  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1002  *
1003  * Test a simple IB in the DMA ring.
1004  * Returns 0 on success, error on failure.
1005  */
1006 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1007 {
1008         struct amdgpu_device *adev = ring->adev;
1009         struct amdgpu_ib ib;
1010         struct dma_fence *f = NULL;
1011         unsigned index;
1012         long r;
1013         u32 tmp = 0;
1014         u64 gpu_addr;
1015
1016         r = amdgpu_device_wb_get(adev, &index);
1017         if (r)
1018                 return r;
1019
1020         gpu_addr = adev->wb.gpu_addr + (index * 4);
1021         tmp = 0xCAFEDEAD;
1022         adev->wb.wb[index] = cpu_to_le32(tmp);
1023         memset(&ib, 0, sizeof(ib));
1024         r = amdgpu_ib_get(adev, NULL, 256,
1025                                         AMDGPU_IB_POOL_DIRECT, &ib);
1026         if (r)
1027                 goto err0;
1028
1029         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1030                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1031         ib.ptr[1] = lower_32_bits(gpu_addr);
1032         ib.ptr[2] = upper_32_bits(gpu_addr);
1033         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1034         ib.ptr[4] = 0xDEADBEEF;
1035         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1036         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1037         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1038         ib.length_dw = 8;
1039
1040         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1041         if (r)
1042                 goto err1;
1043
1044         r = dma_fence_wait_timeout(f, false, timeout);
1045         if (r == 0) {
1046                 r = -ETIMEDOUT;
1047                 goto err1;
1048         } else if (r < 0) {
1049                 goto err1;
1050         }
1051         tmp = le32_to_cpu(adev->wb.wb[index]);
1052         if (tmp == 0xDEADBEEF)
1053                 r = 0;
1054         else
1055                 r = -EINVAL;
1056
1057 err1:
1058         amdgpu_ib_free(adev, &ib, NULL);
1059         dma_fence_put(f);
1060 err0:
1061         amdgpu_device_wb_free(adev, index);
1062         return r;
1063 }
1064
1065
1066 /**
1067  * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART
1068  *
1069  * @ib: indirect buffer to fill with commands
1070  * @pe: addr of the page entry
1071  * @src: src addr to copy from
1072  * @count: number of page entries to update
1073  *
1074  * Update PTEs by copying them from the GART using sDMA.
1075  */
1076 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib,
1077                                   uint64_t pe, uint64_t src,
1078                                   unsigned count)
1079 {
1080         unsigned bytes = count * 8;
1081
1082         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1083                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1084         ib->ptr[ib->length_dw++] = bytes - 1;
1085         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1086         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1087         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1088         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1089         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1090
1091 }
1092
1093 /**
1094  * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually
1095  *
1096  * @ib: indirect buffer to fill with commands
1097  * @pe: addr of the page entry
1098  * @value: dst addr to write into pe
1099  * @count: number of page entries to update
1100  * @incr: increase next addr by incr bytes
1101  *
1102  * Update PTEs by writing them manually using sDMA.
1103  */
1104 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1105                                    uint64_t value, unsigned count,
1106                                    uint32_t incr)
1107 {
1108         unsigned ndw = count * 2;
1109
1110         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1111                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1112         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1113         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1114         ib->ptr[ib->length_dw++] = ndw - 1;
1115         for (; ndw > 0; ndw -= 2) {
1116                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1117                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1118                 value += incr;
1119         }
1120 }
1121
1122 /**
1123  * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA
1124  *
1125  * @ib: indirect buffer to fill with commands
1126  * @pe: addr of the page entry
1127  * @addr: dst addr to write into pe
1128  * @count: number of page entries to update
1129  * @incr: increase next addr by incr bytes
1130  * @flags: access flags
1131  *
1132  * Update the page tables using sDMA.
1133  */
1134 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1135                                      uint64_t pe,
1136                                      uint64_t addr, unsigned count,
1137                                      uint32_t incr, uint64_t flags)
1138 {
1139         /* for physically contiguous pages (vram) */
1140         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1141         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1142         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1143         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1144         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1145         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1146         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1147         ib->ptr[ib->length_dw++] = incr; /* increment size */
1148         ib->ptr[ib->length_dw++] = 0;
1149         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1150 }
1151
1152 /**
1153  * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw
1154  *
1155  * @ring: amdgpu_ring structure holding ring information
1156  * @ib: indirect buffer to fill with padding
1157  */
1158 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1159 {
1160         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1161         u32 pad_count;
1162         int i;
1163
1164         pad_count = (-ib->length_dw) & 7;
1165         for (i = 0; i < pad_count; i++)
1166                 if (sdma && sdma->burst_nop && (i == 0))
1167                         ib->ptr[ib->length_dw++] =
1168                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1169                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1170                 else
1171                         ib->ptr[ib->length_dw++] =
1172                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1173 }
1174
1175
1176 /**
1177  * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline
1178  *
1179  * @ring: amdgpu_ring pointer
1180  *
1181  * Make sure all previous operations are completed (CIK).
1182  */
1183 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1184 {
1185         uint32_t seq = ring->fence_drv.sync_seq;
1186         uint64_t addr = ring->fence_drv.gpu_addr;
1187
1188         /* wait for idle */
1189         sdma_v4_4_2_wait_reg_mem(ring, 1, 0,
1190                                addr & 0xfffffffc,
1191                                upper_32_bits(addr) & 0xffffffff,
1192                                seq, 0xffffffff, 4);
1193 }
1194
1195
1196 /**
1197  * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA
1198  *
1199  * @ring: amdgpu_ring pointer
1200  * @vmid: vmid number to use
1201  * @pd_addr: address
1202  *
1203  * Update the page table base and flush the VM TLB
1204  * using sDMA.
1205  */
1206 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1207                                          unsigned vmid, uint64_t pd_addr)
1208 {
1209         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1210 }
1211
1212 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring,
1213                                      uint32_t reg, uint32_t val)
1214 {
1215         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1216                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1217         amdgpu_ring_write(ring, reg);
1218         amdgpu_ring_write(ring, val);
1219 }
1220
1221 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1222                                          uint32_t val, uint32_t mask)
1223 {
1224         sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1225 }
1226
1227 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev)
1228 {
1229         switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1230         case IP_VERSION(4, 4, 2):
1231                 return false;
1232         default:
1233                 return false;
1234         }
1235 }
1236
1237 static int sdma_v4_4_2_early_init(void *handle)
1238 {
1239         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1240         int r;
1241
1242         r = sdma_v4_4_2_init_microcode(adev);
1243         if (r)
1244                 return r;
1245
1246         /* TODO: Page queue breaks driver reload under SRIOV */
1247         if (sdma_v4_4_2_fw_support_paging_queue(adev))
1248                 adev->sdma.has_page_queue = true;
1249
1250         sdma_v4_4_2_set_ring_funcs(adev);
1251         sdma_v4_4_2_set_buffer_funcs(adev);
1252         sdma_v4_4_2_set_vm_pte_funcs(adev);
1253         sdma_v4_4_2_set_irq_funcs(adev);
1254         sdma_v4_4_2_set_ras_funcs(adev);
1255
1256         return 0;
1257 }
1258
1259 #if 0
1260 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1261                 void *err_data,
1262                 struct amdgpu_iv_entry *entry);
1263 #endif
1264
1265 static int sdma_v4_4_2_late_init(void *handle)
1266 {
1267         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1268 #if 0
1269         struct ras_ih_if ih_info = {
1270                 .cb = sdma_v4_4_2_process_ras_data_cb,
1271         };
1272 #endif
1273         if (!amdgpu_persistent_edc_harvesting_supported(adev))
1274                 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA);
1275
1276         return 0;
1277 }
1278
1279 static int sdma_v4_4_2_sw_init(void *handle)
1280 {
1281         struct amdgpu_ring *ring;
1282         int r, i;
1283         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1284         u32 aid_id;
1285
1286         /* SDMA trap event */
1287         for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1288                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1289                                       SDMA0_4_0__SRCID__SDMA_TRAP,
1290                                       &adev->sdma.trap_irq);
1291                 if (r)
1292                         return r;
1293         }
1294
1295         /* SDMA SRAM ECC event */
1296         for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1297                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1298                                       SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1299                                       &adev->sdma.ecc_irq);
1300                 if (r)
1301                         return r;
1302         }
1303
1304         /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
1305         for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1306                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1307                                       SDMA0_4_0__SRCID__SDMA_VM_HOLE,
1308                                       &adev->sdma.vm_hole_irq);
1309                 if (r)
1310                         return r;
1311
1312                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1313                                       SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
1314                                       &adev->sdma.doorbell_invalid_irq);
1315                 if (r)
1316                         return r;
1317
1318                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1319                                       SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
1320                                       &adev->sdma.pool_timeout_irq);
1321                 if (r)
1322                         return r;
1323
1324                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1325                                       SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
1326                                       &adev->sdma.srbm_write_irq);
1327                 if (r)
1328                         return r;
1329         }
1330
1331         for (i = 0; i < adev->sdma.num_instances; i++) {
1332                 ring = &adev->sdma.instance[i].ring;
1333                 ring->ring_obj = NULL;
1334                 ring->use_doorbell = true;
1335                 aid_id = adev->sdma.instance[i].aid_id;
1336
1337                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1338                                 ring->use_doorbell?"true":"false");
1339
1340                 /* doorbell size is 2 dwords, get DWORD offset */
1341                 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1342                 ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1343
1344                 sprintf(ring->name, "sdma%d.%d", aid_id,
1345                                 i % adev->sdma.num_inst_per_aid);
1346                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1347                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1348                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1349                 if (r)
1350                         return r;
1351
1352                 if (adev->sdma.has_page_queue) {
1353                         ring = &adev->sdma.instance[i].page;
1354                         ring->ring_obj = NULL;
1355                         ring->use_doorbell = true;
1356
1357                         /* doorbell index of page queue is assigned right after
1358                          * gfx queue on the same instance
1359                          */
1360                         ring->doorbell_index =
1361                                 (adev->doorbell_index.sdma_engine[i] + 1) << 1;
1362                         ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1363
1364                         sprintf(ring->name, "page%d.%d", aid_id,
1365                                         i % adev->sdma.num_inst_per_aid);
1366                         r = amdgpu_ring_init(adev, ring, 1024,
1367                                              &adev->sdma.trap_irq,
1368                                              AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1369                                              AMDGPU_RING_PRIO_DEFAULT, NULL);
1370                         if (r)
1371                                 return r;
1372                 }
1373         }
1374
1375         if (amdgpu_sdma_ras_sw_init(adev)) {
1376                 dev_err(adev->dev, "fail to initialize sdma ras block\n");
1377                 return -EINVAL;
1378         }
1379
1380         return r;
1381 }
1382
1383 static int sdma_v4_4_2_sw_fini(void *handle)
1384 {
1385         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1386         int i;
1387
1388         for (i = 0; i < adev->sdma.num_instances; i++) {
1389                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1390                 if (adev->sdma.has_page_queue)
1391                         amdgpu_ring_fini(&adev->sdma.instance[i].page);
1392         }
1393
1394         if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2))
1395                 amdgpu_sdma_destroy_inst_ctx(adev, true);
1396         else
1397                 amdgpu_sdma_destroy_inst_ctx(adev, false);
1398
1399         return 0;
1400 }
1401
1402 static int sdma_v4_4_2_hw_init(void *handle)
1403 {
1404         int r;
1405         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1406         uint32_t inst_mask;
1407
1408         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1409         if (!amdgpu_sriov_vf(adev))
1410                 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
1411
1412         r = sdma_v4_4_2_inst_start(adev, inst_mask);
1413
1414         return r;
1415 }
1416
1417 static int sdma_v4_4_2_hw_fini(void *handle)
1418 {
1419         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1420         uint32_t inst_mask;
1421         int i;
1422
1423         if (amdgpu_sriov_vf(adev))
1424                 return 0;
1425
1426         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1427         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
1428                 for (i = 0; i < adev->sdma.num_instances; i++) {
1429                         amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1430                                        AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1431                 }
1432         }
1433
1434         sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
1435         sdma_v4_4_2_inst_enable(adev, false, inst_mask);
1436
1437         return 0;
1438 }
1439
1440 static int sdma_v4_4_2_set_clockgating_state(void *handle,
1441                                              enum amd_clockgating_state state);
1442
1443 static int sdma_v4_4_2_suspend(void *handle)
1444 {
1445         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1446
1447         if (amdgpu_in_reset(adev))
1448                 sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
1449
1450         return sdma_v4_4_2_hw_fini(adev);
1451 }
1452
1453 static int sdma_v4_4_2_resume(void *handle)
1454 {
1455         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1456
1457         return sdma_v4_4_2_hw_init(adev);
1458 }
1459
1460 static bool sdma_v4_4_2_is_idle(void *handle)
1461 {
1462         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1463         u32 i;
1464
1465         for (i = 0; i < adev->sdma.num_instances; i++) {
1466                 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG);
1467
1468                 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK))
1469                         return false;
1470         }
1471
1472         return true;
1473 }
1474
1475 static int sdma_v4_4_2_wait_for_idle(void *handle)
1476 {
1477         unsigned i, j;
1478         u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
1479         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1480
1481         for (i = 0; i < adev->usec_timeout; i++) {
1482                 for (j = 0; j < adev->sdma.num_instances; j++) {
1483                         sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG);
1484                         if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK))
1485                                 break;
1486                 }
1487                 if (j == adev->sdma.num_instances)
1488                         return 0;
1489                 udelay(1);
1490         }
1491         return -ETIMEDOUT;
1492 }
1493
1494 static int sdma_v4_4_2_soft_reset(void *handle)
1495 {
1496         /* todo */
1497
1498         return 0;
1499 }
1500
1501 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev,
1502                                         struct amdgpu_irq_src *source,
1503                                         unsigned type,
1504                                         enum amdgpu_interrupt_state state)
1505 {
1506         u32 sdma_cntl;
1507
1508         sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1509         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE,
1510                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1511         WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1512
1513         return 0;
1514 }
1515
1516 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev,
1517                                       struct amdgpu_irq_src *source,
1518                                       struct amdgpu_iv_entry *entry)
1519 {
1520         uint32_t instance, i;
1521
1522         DRM_DEBUG("IH: SDMA trap\n");
1523         instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1524
1525         /* Client id gives the SDMA instance in AID. To know the exact SDMA
1526          * instance, interrupt entry gives the node id which corresponds to the AID instance.
1527          * Match node id with the AID id associated with the SDMA instance. */
1528         for (i = instance; i < adev->sdma.num_instances;
1529              i += adev->sdma.num_inst_per_aid) {
1530                 if (adev->sdma.instance[i].aid_id ==
1531                     node_id_to_phys_map[entry->node_id])
1532                         break;
1533         }
1534
1535         if (i >= adev->sdma.num_instances) {
1536                 dev_WARN_ONCE(
1537                         adev->dev, 1,
1538                         "Couldn't find the right sdma instance in trap handler");
1539                 return 0;
1540         }
1541
1542         switch (entry->ring_id) {
1543         case 0:
1544                 amdgpu_fence_process(&adev->sdma.instance[i].ring);
1545                 break;
1546         default:
1547                 break;
1548         }
1549         return 0;
1550 }
1551
1552 #if 0
1553 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1554                 void *err_data,
1555                 struct amdgpu_iv_entry *entry)
1556 {
1557         int instance;
1558
1559         /* When “Full RAS” is enabled, the per-IP interrupt sources should
1560          * be disabled and the driver should only look for the aggregated
1561          * interrupt via sync flood
1562          */
1563         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA))
1564                 goto out;
1565
1566         instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1567         if (instance < 0)
1568                 goto out;
1569
1570         amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
1571
1572 out:
1573         return AMDGPU_RAS_SUCCESS;
1574 }
1575 #endif
1576
1577 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1578                                               struct amdgpu_irq_src *source,
1579                                               struct amdgpu_iv_entry *entry)
1580 {
1581         int instance;
1582
1583         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1584
1585         instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1586         if (instance < 0)
1587                 return 0;
1588
1589         switch (entry->ring_id) {
1590         case 0:
1591                 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
1592                 break;
1593         }
1594         return 0;
1595 }
1596
1597 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev,
1598                                         struct amdgpu_irq_src *source,
1599                                         unsigned type,
1600                                         enum amdgpu_interrupt_state state)
1601 {
1602         u32 sdma_cntl;
1603
1604         sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1605         switch (state) {
1606         case AMDGPU_IRQ_STATE_DISABLE:
1607                 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL,
1608                                           DRAM_ECC_INT_ENABLE, 0);
1609                 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1610                 break;
1611         /* sdma ecc interrupt is enabled by default
1612          * driver doesn't need to do anything to
1613          * enable the interrupt */
1614         case AMDGPU_IRQ_STATE_ENABLE:
1615         default:
1616                 break;
1617         }
1618
1619         return 0;
1620 }
1621
1622 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev,
1623                                               struct amdgpu_iv_entry *entry)
1624 {
1625         int instance;
1626         struct amdgpu_task_info *task_info;
1627         u64 addr;
1628
1629         instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1630         if (instance < 0 || instance >= adev->sdma.num_instances) {
1631                 dev_err(adev->dev, "sdma instance invalid %d\n", instance);
1632                 return -EINVAL;
1633         }
1634
1635         addr = (u64)entry->src_data[0] << 12;
1636         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
1637
1638         dev_dbg_ratelimited(adev->dev,
1639                             "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n",
1640                             instance, addr, entry->src_id, entry->ring_id, entry->vmid,
1641                             entry->pasid);
1642
1643         task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid);
1644         if (task_info) {
1645                 dev_dbg_ratelimited(adev->dev, " for process %s pid %d thread %s pid %d\n",
1646                                     task_info->process_name, task_info->tgid,
1647                                     task_info->task_name, task_info->pid);
1648                 amdgpu_vm_put_task_info(task_info);
1649         }
1650
1651         return 0;
1652 }
1653
1654 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev,
1655                                               struct amdgpu_irq_src *source,
1656                                               struct amdgpu_iv_entry *entry)
1657 {
1658         dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n");
1659         sdma_v4_4_2_print_iv_entry(adev, entry);
1660         return 0;
1661 }
1662
1663 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev,
1664                                               struct amdgpu_irq_src *source,
1665                                               struct amdgpu_iv_entry *entry)
1666 {
1667
1668         dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
1669         sdma_v4_4_2_print_iv_entry(adev, entry);
1670         return 0;
1671 }
1672
1673 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev,
1674                                               struct amdgpu_irq_src *source,
1675                                               struct amdgpu_iv_entry *entry)
1676 {
1677         dev_dbg_ratelimited(adev->dev,
1678                 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
1679         sdma_v4_4_2_print_iv_entry(adev, entry);
1680         return 0;
1681 }
1682
1683 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev,
1684                                               struct amdgpu_irq_src *source,
1685                                               struct amdgpu_iv_entry *entry)
1686 {
1687         dev_dbg_ratelimited(adev->dev,
1688                 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n");
1689         sdma_v4_4_2_print_iv_entry(adev, entry);
1690         return 0;
1691 }
1692
1693 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep(
1694         struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1695 {
1696         uint32_t data, def;
1697         int i;
1698
1699         /* leave as default if it is not driver controlled */
1700         if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS))
1701                 return;
1702
1703         if (enable) {
1704                 for_each_inst(i, inst_mask) {
1705                         /* 1-not override: enable sdma mem light sleep */
1706                         def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1707                         data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1708                         if (def != data)
1709                                 WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1710                 }
1711         } else {
1712                 for_each_inst(i, inst_mask) {
1713                         /* 0-override:disable sdma mem light sleep */
1714                         def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1715                         data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1716                         if (def != data)
1717                                 WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1718                 }
1719         }
1720 }
1721
1722 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating(
1723         struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1724 {
1725         uint32_t data, def;
1726         int i;
1727
1728         /* leave as default if it is not driver controlled */
1729         if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG))
1730                 return;
1731
1732         if (enable) {
1733                 for_each_inst(i, inst_mask) {
1734                         def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
1735                         data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1736                                   SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1737                                   SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1738                                   SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1739                                   SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1740                                   SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1741                         if (def != data)
1742                                 WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
1743                 }
1744         } else {
1745                 for_each_inst(i, inst_mask) {
1746                         def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
1747                         data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1748                                  SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1749                                  SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1750                                  SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1751                                  SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1752                                  SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1753                         if (def != data)
1754                                 WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
1755                 }
1756         }
1757 }
1758
1759 static int sdma_v4_4_2_set_clockgating_state(void *handle,
1760                                           enum amd_clockgating_state state)
1761 {
1762         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1763         uint32_t inst_mask;
1764
1765         if (amdgpu_sriov_vf(adev))
1766                 return 0;
1767
1768         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1769
1770         sdma_v4_4_2_inst_update_medium_grain_clock_gating(
1771                 adev, state == AMD_CG_STATE_GATE, inst_mask);
1772         sdma_v4_4_2_inst_update_medium_grain_light_sleep(
1773                 adev, state == AMD_CG_STATE_GATE, inst_mask);
1774         return 0;
1775 }
1776
1777 static int sdma_v4_4_2_set_powergating_state(void *handle,
1778                                           enum amd_powergating_state state)
1779 {
1780         return 0;
1781 }
1782
1783 static void sdma_v4_4_2_get_clockgating_state(void *handle, u64 *flags)
1784 {
1785         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1786         int data;
1787
1788         if (amdgpu_sriov_vf(adev))
1789                 *flags = 0;
1790
1791         /* AMD_CG_SUPPORT_SDMA_MGCG */
1792         data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL));
1793         if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK))
1794                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1795
1796         /* AMD_CG_SUPPORT_SDMA_LS */
1797         data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL));
1798         if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1799                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1800 }
1801
1802 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = {
1803         .name = "sdma_v4_4_2",
1804         .early_init = sdma_v4_4_2_early_init,
1805         .late_init = sdma_v4_4_2_late_init,
1806         .sw_init = sdma_v4_4_2_sw_init,
1807         .sw_fini = sdma_v4_4_2_sw_fini,
1808         .hw_init = sdma_v4_4_2_hw_init,
1809         .hw_fini = sdma_v4_4_2_hw_fini,
1810         .suspend = sdma_v4_4_2_suspend,
1811         .resume = sdma_v4_4_2_resume,
1812         .is_idle = sdma_v4_4_2_is_idle,
1813         .wait_for_idle = sdma_v4_4_2_wait_for_idle,
1814         .soft_reset = sdma_v4_4_2_soft_reset,
1815         .set_clockgating_state = sdma_v4_4_2_set_clockgating_state,
1816         .set_powergating_state = sdma_v4_4_2_set_powergating_state,
1817         .get_clockgating_state = sdma_v4_4_2_get_clockgating_state,
1818 };
1819
1820 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {
1821         .type = AMDGPU_RING_TYPE_SDMA,
1822         .align_mask = 0xff,
1823         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1824         .support_64bit_ptrs = true,
1825         .get_rptr = sdma_v4_4_2_ring_get_rptr,
1826         .get_wptr = sdma_v4_4_2_ring_get_wptr,
1827         .set_wptr = sdma_v4_4_2_ring_set_wptr,
1828         .emit_frame_size =
1829                 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
1830                 3 + /* hdp invalidate */
1831                 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
1832                 /* sdma_v4_4_2_ring_emit_vm_flush */
1833                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1834                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1835                 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
1836         .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
1837         .emit_ib = sdma_v4_4_2_ring_emit_ib,
1838         .emit_fence = sdma_v4_4_2_ring_emit_fence,
1839         .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
1840         .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
1841         .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
1842         .test_ring = sdma_v4_4_2_ring_test_ring,
1843         .test_ib = sdma_v4_4_2_ring_test_ib,
1844         .insert_nop = sdma_v4_4_2_ring_insert_nop,
1845         .pad_ib = sdma_v4_4_2_ring_pad_ib,
1846         .emit_wreg = sdma_v4_4_2_ring_emit_wreg,
1847         .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
1848         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1849 };
1850
1851 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = {
1852         .type = AMDGPU_RING_TYPE_SDMA,
1853         .align_mask = 0xff,
1854         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1855         .support_64bit_ptrs = true,
1856         .get_rptr = sdma_v4_4_2_ring_get_rptr,
1857         .get_wptr = sdma_v4_4_2_page_ring_get_wptr,
1858         .set_wptr = sdma_v4_4_2_page_ring_set_wptr,
1859         .emit_frame_size =
1860                 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
1861                 3 + /* hdp invalidate */
1862                 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
1863                 /* sdma_v4_4_2_ring_emit_vm_flush */
1864                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1865                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1866                 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
1867         .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
1868         .emit_ib = sdma_v4_4_2_ring_emit_ib,
1869         .emit_fence = sdma_v4_4_2_ring_emit_fence,
1870         .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
1871         .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
1872         .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
1873         .test_ring = sdma_v4_4_2_ring_test_ring,
1874         .test_ib = sdma_v4_4_2_ring_test_ib,
1875         .insert_nop = sdma_v4_4_2_ring_insert_nop,
1876         .pad_ib = sdma_v4_4_2_ring_pad_ib,
1877         .emit_wreg = sdma_v4_4_2_ring_emit_wreg,
1878         .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
1879         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1880 };
1881
1882 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev)
1883 {
1884         int i, dev_inst;
1885
1886         for (i = 0; i < adev->sdma.num_instances; i++) {
1887                 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs;
1888                 adev->sdma.instance[i].ring.me = i;
1889                 if (adev->sdma.has_page_queue) {
1890                         adev->sdma.instance[i].page.funcs =
1891                                 &sdma_v4_4_2_page_ring_funcs;
1892                         adev->sdma.instance[i].page.me = i;
1893                 }
1894
1895                 dev_inst = GET_INST(SDMA0, i);
1896                 /* AID to which SDMA belongs depends on physical instance */
1897                 adev->sdma.instance[i].aid_id =
1898                         dev_inst / adev->sdma.num_inst_per_aid;
1899         }
1900 }
1901
1902 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = {
1903         .set = sdma_v4_4_2_set_trap_irq_state,
1904         .process = sdma_v4_4_2_process_trap_irq,
1905 };
1906
1907 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = {
1908         .process = sdma_v4_4_2_process_illegal_inst_irq,
1909 };
1910
1911 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = {
1912         .set = sdma_v4_4_2_set_ecc_irq_state,
1913         .process = amdgpu_sdma_process_ecc_irq,
1914 };
1915
1916 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = {
1917         .process = sdma_v4_4_2_process_vm_hole_irq,
1918 };
1919
1920 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = {
1921         .process = sdma_v4_4_2_process_doorbell_invalid_irq,
1922 };
1923
1924 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = {
1925         .process = sdma_v4_4_2_process_pool_timeout_irq,
1926 };
1927
1928 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = {
1929         .process = sdma_v4_4_2_process_srbm_write_irq,
1930 };
1931
1932 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev)
1933 {
1934         adev->sdma.trap_irq.num_types = adev->sdma.num_instances;
1935         adev->sdma.ecc_irq.num_types = adev->sdma.num_instances;
1936         adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances;
1937         adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances;
1938         adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances;
1939         adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances;
1940
1941         adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs;
1942         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs;
1943         adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs;
1944         adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs;
1945         adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs;
1946         adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs;
1947         adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs;
1948 }
1949
1950 /**
1951  * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine
1952  *
1953  * @ib: indirect buffer to copy to
1954  * @src_offset: src GPU address
1955  * @dst_offset: dst GPU address
1956  * @byte_count: number of bytes to xfer
1957  * @tmz: if a secure copy should be used
1958  *
1959  * Copy GPU buffers using the DMA engine.
1960  * Used by the amdgpu ttm implementation to move pages if
1961  * registered as the asic copy callback.
1962  */
1963 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib,
1964                                        uint64_t src_offset,
1965                                        uint64_t dst_offset,
1966                                        uint32_t byte_count,
1967                                        bool tmz)
1968 {
1969         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1970                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1971                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1972         ib->ptr[ib->length_dw++] = byte_count - 1;
1973         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1974         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1975         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1976         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1977         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1978 }
1979
1980 /**
1981  * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine
1982  *
1983  * @ib: indirect buffer to copy to
1984  * @src_data: value to write to buffer
1985  * @dst_offset: dst GPU address
1986  * @byte_count: number of bytes to xfer
1987  *
1988  * Fill GPU buffers using the DMA engine.
1989  */
1990 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib,
1991                                        uint32_t src_data,
1992                                        uint64_t dst_offset,
1993                                        uint32_t byte_count)
1994 {
1995         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1996         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1997         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1998         ib->ptr[ib->length_dw++] = src_data;
1999         ib->ptr[ib->length_dw++] = byte_count - 1;
2000 }
2001
2002 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = {
2003         .copy_max_bytes = 0x400000,
2004         .copy_num_dw = 7,
2005         .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer,
2006
2007         .fill_max_bytes = 0x400000,
2008         .fill_num_dw = 5,
2009         .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer,
2010 };
2011
2012 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev)
2013 {
2014         adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs;
2015         if (adev->sdma.has_page_queue)
2016                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2017         else
2018                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2019 }
2020
2021 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = {
2022         .copy_pte_num_dw = 7,
2023         .copy_pte = sdma_v4_4_2_vm_copy_pte,
2024
2025         .write_pte = sdma_v4_4_2_vm_write_pte,
2026         .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde,
2027 };
2028
2029 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev)
2030 {
2031         struct drm_gpu_scheduler *sched;
2032         unsigned i;
2033
2034         adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs;
2035         for (i = 0; i < adev->sdma.num_instances; i++) {
2036                 if (adev->sdma.has_page_queue)
2037                         sched = &adev->sdma.instance[i].page.sched;
2038                 else
2039                         sched = &adev->sdma.instance[i].ring.sched;
2040                 adev->vm_manager.vm_pte_scheds[i] = sched;
2041         }
2042         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2043 }
2044
2045 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = {
2046         .type = AMD_IP_BLOCK_TYPE_SDMA,
2047         .major = 4,
2048         .minor = 4,
2049         .rev = 2,
2050         .funcs = &sdma_v4_4_2_ip_funcs,
2051 };
2052
2053 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask)
2054 {
2055         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2056         int r;
2057
2058         if (!amdgpu_sriov_vf(adev))
2059                 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
2060
2061         r = sdma_v4_4_2_inst_start(adev, inst_mask);
2062
2063         return r;
2064 }
2065
2066 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask)
2067 {
2068         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2069         uint32_t tmp_mask = inst_mask;
2070         int i;
2071
2072         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2073                 for_each_inst(i, tmp_mask) {
2074                         amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
2075                                        AMDGPU_SDMA_IRQ_INSTANCE0 + i);
2076                 }
2077         }
2078
2079         sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
2080         sdma_v4_4_2_inst_enable(adev, false, inst_mask);
2081
2082         return 0;
2083 }
2084
2085 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = {
2086         .suspend = &sdma_v4_4_2_xcp_suspend,
2087         .resume = &sdma_v4_4_2_xcp_resume
2088 };
2089
2090 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = {
2091         {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI),
2092         1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"},
2093 };
2094
2095 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = {
2096         {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"},
2097         {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"},
2098         {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"},
2099         {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"},
2100         {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"},
2101         {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"},
2102         {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"},
2103         {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"},
2104         {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"},
2105         {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"},
2106         {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"},
2107         {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"},
2108         {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"},
2109         {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"},
2110         {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"},
2111         {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"},
2112         {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"},
2113         {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"},
2114         {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"},
2115         {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"},
2116         {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"},
2117         {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"},
2118         {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"},
2119         {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"},
2120 };
2121
2122 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev,
2123                                                    uint32_t sdma_inst,
2124                                                    void *ras_err_status)
2125 {
2126         struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status;
2127         uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2128         unsigned long ue_count = 0;
2129         struct amdgpu_smuio_mcm_config_info mcm_info = {
2130                 .socket_id = adev->smuio.funcs->get_socket_id(adev),
2131                 .die_id = adev->sdma.instance[sdma_inst].aid_id,
2132         };
2133
2134         /* sdma v4_4_2 doesn't support query ce counts */
2135         amdgpu_ras_inst_query_ras_error_count(adev,
2136                                         sdma_v4_2_2_ue_reg_list,
2137                                         ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
2138                                         sdma_v4_4_2_ras_memory_list,
2139                                         ARRAY_SIZE(sdma_v4_4_2_ras_memory_list),
2140                                         sdma_dev_inst,
2141                                         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
2142                                         &ue_count);
2143
2144         amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, NULL, ue_count);
2145 }
2146
2147 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev,
2148                                               void *ras_err_status)
2149 {
2150         uint32_t inst_mask;
2151         int i = 0;
2152
2153         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2154         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2155                 for_each_inst(i, inst_mask)
2156                         sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status);
2157         } else {
2158                 dev_warn(adev->dev, "SDMA RAS is not supported\n");
2159         }
2160 }
2161
2162 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev,
2163                                                    uint32_t sdma_inst)
2164 {
2165         uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2166
2167         amdgpu_ras_inst_reset_ras_error_count(adev,
2168                                         sdma_v4_2_2_ue_reg_list,
2169                                         ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
2170                                         sdma_dev_inst);
2171 }
2172
2173 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev)
2174 {
2175         uint32_t inst_mask;
2176         int i = 0;
2177
2178         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2179         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2180                 for_each_inst(i, inst_mask)
2181                         sdma_v4_4_2_inst_reset_ras_error_count(adev, i);
2182         } else {
2183                 dev_warn(adev->dev, "SDMA RAS is not supported\n");
2184         }
2185 }
2186
2187 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = {
2188         .query_ras_error_count = sdma_v4_4_2_query_ras_error_count,
2189         .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count,
2190 };
2191
2192 static int sdma_v4_4_2_aca_bank_generate_report(struct aca_handle *handle,
2193                                                 struct aca_bank *bank, enum aca_error_type type,
2194                                                 struct aca_bank_report *report, void *data)
2195 {
2196         u64 status, misc0;
2197         int ret;
2198
2199         status = bank->regs[ACA_REG_IDX_STATUS];
2200         if ((type == ACA_ERROR_TYPE_UE &&
2201              ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_FAULT) ||
2202             (type == ACA_ERROR_TYPE_CE &&
2203              ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_CE)) {
2204
2205                 ret = aca_bank_info_decode(bank, &report->info);
2206                 if (ret)
2207                         return ret;
2208
2209                 misc0 = bank->regs[ACA_REG_IDX_MISC0];
2210                 report->count[type] = ACA_REG__MISC0__ERRCNT(misc0);
2211         }
2212
2213         return 0;
2214 }
2215
2216 /* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */
2217 static int sdma_v4_4_2_err_codes[] = { 33, 34, 35, 36 };
2218
2219 static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
2220                                           enum aca_error_type type, void *data)
2221 {
2222         u32 instlo;
2223
2224         instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
2225         instlo &= GENMASK(31, 1);
2226
2227         if (instlo != mmSMNAID_AID0_MCA_SMU)
2228                 return false;
2229
2230         if (aca_bank_check_error_codes(handle->adev, bank,
2231                                        sdma_v4_4_2_err_codes,
2232                                        ARRAY_SIZE(sdma_v4_4_2_err_codes)))
2233                 return false;
2234
2235         return true;
2236 }
2237
2238 static const struct aca_bank_ops sdma_v4_4_2_aca_bank_ops = {
2239         .aca_bank_generate_report = sdma_v4_4_2_aca_bank_generate_report,
2240         .aca_bank_is_valid = sdma_v4_4_2_aca_bank_is_valid,
2241 };
2242
2243 static const struct aca_info sdma_v4_4_2_aca_info = {
2244         .hwip = ACA_HWIP_TYPE_SMU,
2245         .mask = ACA_ERROR_UE_MASK,
2246         .bank_ops = &sdma_v4_4_2_aca_bank_ops,
2247 };
2248
2249 static int sdma_v4_4_2_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
2250 {
2251         int r;
2252
2253         r = amdgpu_sdma_ras_late_init(adev, ras_block);
2254         if (r)
2255                 return r;
2256
2257         return amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__SDMA,
2258                                    &sdma_v4_4_2_aca_info, NULL);
2259 }
2260
2261 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = {
2262         .ras_block = {
2263                 .hw_ops = &sdma_v4_4_2_ras_hw_ops,
2264                 .ras_late_init = sdma_v4_4_2_ras_late_init,
2265         },
2266 };
2267
2268 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev)
2269 {
2270         adev->sdma.ras = &sdma_v4_4_2_ras;
2271 }