drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/dev_printk.h>
  24 #include <drm/drm_drv.h>
  25 #include <linux/vmalloc.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_psp.h"
  28 #include "amdgpu_ucode.h"
  29 #include "soc15_common.h"
  30 #include "psp_v13_0.h"
  31
  32 #include "mp/mp_13_0_2_offset.h"
  33 #include "mp/mp_13_0_2_sh_mask.h"
  34
  35 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
  36 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
  37 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
  38 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
  39 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
  40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
  41 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
  42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
  43 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
  44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
  45 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
  46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
  47 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
  48
  49 /* For large FW files the time to complete can be very long */
  50 #define USBC_PD_POLLING_LIMIT_S 240
  51
  52 /* Read USB-PD from LFB */
  53 #define GFX_CMD_USB_PD_USE_LFB 0x480
  54
  55 /* VBIOS gfl defines */
  56 #define MBOX_READY_MASK 0x80000000
  57 #define MBOX_STATUS_MASK 0x0000FFFF
  58 #define MBOX_COMMAND_MASK 0x00FF0000
  59 #define MBOX_READY_FLAG 0x80000000
  60 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
  61 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
  62 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
  63
  64 /* memory training timeout define */
  65 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US   3000000
  66
  67 static int psp_v13_0_init_microcode(struct psp_context *psp)
  68 {
  69         struct amdgpu_device *adev = psp->adev;
  70         const char *chip_name;
  71         char ucode_prefix[30];
  72         int err = 0;
  73
  74         switch (adev->ip_versions[MP0_HWIP][0]) {
  75         case IP_VERSION(13, 0, 2):
  76                 chip_name = "aldebaran";
  77                 break;
  78         case IP_VERSION(13, 0, 1):
  79         case IP_VERSION(13, 0, 3):
  80                 chip_name = "yellow_carp";
  81                 break;
  82         default:
  83                 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
  84                 chip_name = ucode_prefix;
  85                 break;
  86         }
  87
  88         switch (adev->ip_versions[MP0_HWIP][0]) {
  89         case IP_VERSION(13, 0, 2):
  90                 err = psp_init_sos_microcode(psp, chip_name);
  91                 if (err)
  92                         return err;
  93                 /* It's not necessary to load ras ta on Guest side */
  94                 if (!amdgpu_sriov_vf(adev)) {
  95                         err = psp_init_ta_microcode(&adev->psp, chip_name);
  96                         if (err)
  97                                 return err;
  98                 }
  99                 break;
 100         case IP_VERSION(13, 0, 1):
 101         case IP_VERSION(13, 0, 3):
 102         case IP_VERSION(13, 0, 5):
 103         case IP_VERSION(13, 0, 8):
 104                 err = psp_init_toc_microcode(psp, chip_name);
 105                 if (err)
 106                         return err;
 107                 err = psp_init_ta_microcode(psp, chip_name);
 108                 if (err)
 109                         return err;
 110                 break;
 111         case IP_VERSION(13, 0, 0):
 112         case IP_VERSION(13, 0, 7):
 113                 err = psp_init_sos_microcode(psp, chip_name);
 114                 if (err)
 115                         return err;
 116                 /* It's not necessary to load ras ta on Guest side */
 117                 err = psp_init_ta_microcode(psp, chip_name);
 118                 if (err)
 119                         return err;
 120                 break;
 121         default:
 122                 BUG();
 123         }
 124
 125         return 0;
 126 }
 127
 128 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
 129 {
 130         struct amdgpu_device *adev = psp->adev;
 131         uint32_t sol_reg;
 132
 133         sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
 134
 135         return sol_reg != 0x0;
 136 }
 137
 138 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
 139 {
 140         struct amdgpu_device *adev = psp->adev;
 141
 142         int ret;
 143         int retry_loop;
 144
 145         for (retry_loop = 0; retry_loop < 10; retry_loop++) {
 146                 /* Wait for bootloader to signify that is
 147                     ready having bit 31 of C2PMSG_35 set to 1 */
 148                 ret = psp_wait_for(psp,
 149                                    SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 150                                    0x80000000,
 151                                    0x80000000,
 152                                    false);
 153
 154                 if (ret == 0)
 155                         return 0;
 156         }
 157
 158         return ret;
 159 }
 160
 161 static int psp_v13_0_bootloader_load_component(struct psp_context       *psp,
 162                                                struct psp_bin_desc      *bin_desc,
 163                                                enum psp_bootloader_cmd  bl_cmd)
 164 {
 165         int ret;
 166         uint32_t psp_gfxdrv_command_reg = 0;
 167         struct amdgpu_device *adev = psp->adev;
 168
 169         /* Check tOS sign of life register to confirm sys driver and sOS
 170          * are already been loaded.
 171          */
 172         if (psp_v13_0_is_sos_alive(psp))
 173                 return 0;
 174
 175         ret = psp_v13_0_wait_for_bootloader(psp);
 176         if (ret)
 177                 return ret;
 178
 179         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 180
 181         /* Copy PSP KDB binary to memory */
 182         memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
 183
 184         /* Provide the PSP KDB to bootloader */
 185         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 186                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 187         psp_gfxdrv_command_reg = bl_cmd;
 188         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 189                psp_gfxdrv_command_reg);
 190
 191         ret = psp_v13_0_wait_for_bootloader(psp);
 192
 193         return ret;
 194 }
 195
 196 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
 197 {
 198         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
 199 }
 200
 201 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
 202 {
 203         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
 204 }
 205
 206 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
 207 {
 208         return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
 209 }
 210
 211 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
 212 {
 213         return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
 214 }
 215
 216 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
 217 {
 218         return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
 219 }
 220
 221 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
 222 {
 223         return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
 224 }
 225
 226 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
 227 {
 228         int ret;
 229         unsigned int psp_gfxdrv_command_reg = 0;
 230         struct amdgpu_device *adev = psp->adev;
 231
 232         /* Check sOS sign of life register to confirm sys driver and sOS
 233          * are already been loaded.
 234          */
 235         if (psp_v13_0_is_sos_alive(psp))
 236                 return 0;
 237
 238         ret = psp_v13_0_wait_for_bootloader(psp);
 239         if (ret)
 240                 return ret;
 241
 242         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 243
 244         /* Copy Secure OS binary to PSP memory */
 245         memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
 246
 247         /* Provide the PSP secure OS to bootloader */
 248         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 249                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 250         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 251         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 252                psp_gfxdrv_command_reg);
 253
 254         /* there might be handshake issue with hardware which needs delay */
 255         mdelay(20);
 256         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
 257                            RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
 258                            0, true);
 259
 260         return ret;
 261 }
 262
 263 static int psp_v13_0_ring_init(struct psp_context *psp,
 264                               enum psp_ring_type ring_type)
 265 {
 266         int ret = 0;
 267         struct psp_ring *ring;
 268         struct amdgpu_device *adev = psp->adev;
 269
 270         ring = &psp->km_ring;
 271
 272         ring->ring_type = ring_type;
 273
 274         /* allocate 4k Page of Local Frame Buffer memory for ring */
 275         ring->ring_size = 0x1000;
 276         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 277                                       AMDGPU_GEM_DOMAIN_VRAM,
 278                                       &adev->firmware.rbuf,
 279                                       &ring->ring_mem_mc_addr,
 280                                       (void **)&ring->ring_mem);
 281         if (ret) {
 282                 ring->ring_size = 0;
 283                 return ret;
 284         }
 285
 286         return 0;
 287 }
 288
 289 static int psp_v13_0_ring_stop(struct psp_context *psp,
 290                                enum psp_ring_type ring_type)
 291 {
 292         int ret = 0;
 293         struct amdgpu_device *adev = psp->adev;
 294
 295         if (amdgpu_sriov_vf(adev)) {
 296                 /* Write the ring destroy command*/
 297                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 298                              GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 299                 /* there might be handshake issue with hardware which needs delay */
 300                 mdelay(20);
 301                 /* Wait for response flag (bit 31) */
 302                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 303                                    0x80000000, 0x80000000, false);
 304         } else {
 305                 /* Write the ring destroy command*/
 306                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
 307                              GFX_CTRL_CMD_ID_DESTROY_RINGS);
 308                 /* there might be handshake issue with hardware which needs delay */
 309                 mdelay(20);
 310                 /* Wait for response flag (bit 31) */
 311                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 312                                    0x80000000, 0x80000000, false);
 313         }
 314
 315         return ret;
 316 }
 317
 318 static int psp_v13_0_ring_create(struct psp_context *psp,
 319                                  enum psp_ring_type ring_type)
 320 {
 321         int ret = 0;
 322         unsigned int psp_ring_reg = 0;
 323         struct psp_ring *ring = &psp->km_ring;
 324         struct amdgpu_device *adev = psp->adev;
 325
 326         if (amdgpu_sriov_vf(adev)) {
 327                 ret = psp_v13_0_ring_stop(psp, ring_type);
 328                 if (ret) {
 329                         DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
 330                         return ret;
 331                 }
 332
 333                 /* Write low address of the ring to C2PMSG_102 */
 334                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 335                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
 336                 /* Write high address of the ring to C2PMSG_103 */
 337                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 338                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
 339
 340                 /* Write the ring initialization command to C2PMSG_101 */
 341                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 342                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 343
 344                 /* there might be handshake issue with hardware which needs delay */
 345                 mdelay(20);
 346
 347                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 348                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 349                                    0x80000000, 0x8000FFFF, false);
 350
 351         } else {
 352                 /* Wait for sOS ready for ring creation */
 353                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 354                                    0x80000000, 0x80000000, false);
 355                 if (ret) {
 356                         DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
 357                         return ret;
 358                 }
 359
 360                 /* Write low address of the ring to C2PMSG_69 */
 361                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 362                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
 363                 /* Write high address of the ring to C2PMSG_70 */
 364                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 365                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
 366                 /* Write size of ring to C2PMSG_71 */
 367                 psp_ring_reg = ring->ring_size;
 368                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
 369                 /* Write the ring initialization command to C2PMSG_64 */
 370                 psp_ring_reg = ring_type;
 371                 psp_ring_reg = psp_ring_reg << 16;
 372                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
 373
 374                 /* there might be handshake issue with hardware which needs delay */
 375                 mdelay(20);
 376
 377                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 378                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 379                                    0x80000000, 0x8000FFFF, false);
 380         }
 381
 382         return ret;
 383 }
 384
 385 static int psp_v13_0_ring_destroy(struct psp_context *psp,
 386                                   enum psp_ring_type ring_type)
 387 {
 388         int ret = 0;
 389         struct psp_ring *ring = &psp->km_ring;
 390         struct amdgpu_device *adev = psp->adev;
 391
 392         ret = psp_v13_0_ring_stop(psp, ring_type);
 393         if (ret)
 394                 DRM_ERROR("Fail to stop psp ring\n");
 395
 396         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 397                               &ring->ring_mem_mc_addr,
 398                               (void **)&ring->ring_mem);
 399
 400         return ret;
 401 }
 402
 403 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
 404 {
 405         uint32_t data;
 406         struct amdgpu_device *adev = psp->adev;
 407
 408         if (amdgpu_sriov_vf(adev))
 409                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
 410         else
 411                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
 412
 413         return data;
 414 }
 415
 416 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
 417 {
 418         struct amdgpu_device *adev = psp->adev;
 419
 420         if (amdgpu_sriov_vf(adev)) {
 421                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
 422                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 423                              GFX_CTRL_CMD_ID_CONSUME_CMD);
 424         } else
 425                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
 426 }
 427
 428 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
 429 {
 430         int ret;
 431         int i;
 432         uint32_t data_32;
 433         int max_wait;
 434         struct amdgpu_device *adev = psp->adev;
 435
 436         data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
 437         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
 438         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
 439
 440         max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
 441         for (i = 0; i < max_wait; i++) {
 442                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 443                                    0x80000000, 0x80000000, false);
 444                 if (ret == 0)
 445                         break;
 446         }
 447         if (i < max_wait)
 448                 ret = 0;
 449         else
 450                 ret = -ETIME;
 451
 452         dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
 453                   (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
 454                   (ret == 0) ? "succeed" : "failed",
 455                   i, adev->usec_timeout/1000);
 456         return ret;
 457 }
 458
 459
 460 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
 461 {
 462         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 463         uint32_t *pcache = (uint32_t *)ctx->sys_cache;
 464         struct amdgpu_device *adev = psp->adev;
 465         uint32_t p2c_header[4];
 466         uint32_t sz;
 467         void *buf;
 468         int ret, idx;
 469
 470         if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
 471                 dev_dbg(adev->dev, "Memory training is not supported.\n");
 472                 return 0;
 473         } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
 474                 dev_err(adev->dev, "Memory training initialization failure.\n");
 475                 return -EINVAL;
 476         }
 477
 478         if (psp_v13_0_is_sos_alive(psp)) {
 479                 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
 480                 return 0;
 481         }
 482
 483         amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
 484         dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
 485                   pcache[0], pcache[1], pcache[2], pcache[3],
 486                   p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
 487
 488         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 489                 dev_dbg(adev->dev, "Short training depends on restore.\n");
 490                 ops |= PSP_MEM_TRAIN_RESTORE;
 491         }
 492
 493         if ((ops & PSP_MEM_TRAIN_RESTORE) &&
 494             pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 495                 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
 496                 ops |= PSP_MEM_TRAIN_SAVE;
 497         }
 498
 499         if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 500             !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 501               pcache[3] == p2c_header[3])) {
 502                 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
 503                 ops |= PSP_MEM_TRAIN_SAVE;
 504         }
 505
 506         if ((ops & PSP_MEM_TRAIN_SAVE) &&
 507             p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 508                 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
 509                 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
 510         }
 511
 512         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 513                 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
 514                 ops |= PSP_MEM_TRAIN_SAVE;
 515         }
 516
 517         dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
 518
 519         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 520                 /*
 521                  * Long training will encroach a certain amount on the bottom of VRAM;
 522                  * save the content from the bottom of VRAM to system memory
 523                  * before training, and restore it after training to avoid
 524                  * VRAM corruption.
 525                  */
 526                 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
 527
 528                 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
 529                         dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
 530                                   adev->gmc.visible_vram_size,
 531                                   adev->mman.aper_base_kaddr);
 532                         return -EINVAL;
 533                 }
 534
 535                 buf = vmalloc(sz);
 536                 if (!buf) {
 537                         dev_err(adev->dev, "failed to allocate system memory.\n");
 538                         return -ENOMEM;
 539                 }
 540
 541                 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 542                         memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
 543                         ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
 544                         if (ret) {
 545                                 DRM_ERROR("Send long training msg failed.\n");
 546                                 vfree(buf);
 547                                 drm_dev_exit(idx);
 548                                 return ret;
 549                         }
 550
 551                         memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
 552                         adev->hdp.funcs->flush_hdp(adev, NULL);
 553                         vfree(buf);
 554                         drm_dev_exit(idx);
 555                 } else {
 556                         vfree(buf);
 557                         return -ENODEV;
 558                 }
 559         }
 560
 561         if (ops & PSP_MEM_TRAIN_SAVE) {
 562                 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
 563         }
 564
 565         if (ops & PSP_MEM_TRAIN_RESTORE) {
 566                 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
 567         }
 568
 569         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 570                 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
 571                                                          PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
 572                 if (ret) {
 573                         dev_err(adev->dev, "send training msg failed.\n");
 574                         return ret;
 575                 }
 576         }
 577         ctx->training_cnt++;
 578         return 0;
 579 }
 580
 581 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
 582 {
 583         struct amdgpu_device *adev = psp->adev;
 584         uint32_t reg_status;
 585         int ret, i = 0;
 586
 587         /*
 588          * LFB address which is aligned to 1MB address and has to be
 589          * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
 590          * register
 591          */
 592         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
 593
 594         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 595                              0x80000000, 0x80000000, false);
 596         if (ret)
 597                 return ret;
 598
 599         /* Fireup interrupt so PSP can pick up the address */
 600         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
 601
 602         /* FW load takes very long time */
 603         do {
 604                 msleep(1000);
 605                 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
 606
 607                 if (reg_status & 0x80000000)
 608                         goto done;
 609
 610         } while (++i < USBC_PD_POLLING_LIMIT_S);
 611
 612         return -ETIME;
 613 done:
 614
 615         if ((reg_status & 0xFFFF) != 0) {
 616                 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
 617                                 reg_status & 0xFFFF);
 618                 return -EIO;
 619         }
 620
 621         return 0;
 622 }
 623
 624 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
 625 {
 626         struct amdgpu_device *adev = psp->adev;
 627         int ret;
 628
 629         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 630
 631         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 632                                      0x80000000, 0x80000000, false);
 633         if (!ret)
 634                 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
 635
 636         return ret;
 637 }
 638
 639 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
 640 {
 641         uint32_t reg_status = 0, reg_val = 0;
 642         struct amdgpu_device *adev = psp->adev;
 643         int ret;
 644
 645         /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
 646         reg_val |= (cmd << 16);
 647         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115,  reg_val);
 648
 649         /* Ring the doorbell */
 650         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
 651
 652         if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
 653                 return 0;
 654
 655         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 656                                 MBOX_READY_FLAG, MBOX_READY_MASK, false);
 657         if (ret) {
 658                 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
 659                 return ret;
 660         }
 661
 662         reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 663         if ((reg_status & 0xFFFF) != 0) {
 664                 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
 665                                 cmd, reg_status & 0xFFFF);
 666                 return -EIO;
 667         }
 668
 669         return 0;
 670 }
 671
 672 static int psp_v13_0_update_spirom(struct psp_context *psp,
 673                                    uint64_t fw_pri_mc_addr)
 674 {
 675         struct amdgpu_device *adev = psp->adev;
 676         int ret;
 677
 678         /* Confirm PSP is ready to start */
 679         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 680                            MBOX_READY_FLAG, MBOX_READY_MASK, false);
 681         if (ret) {
 682                 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
 683                 return ret;
 684         }
 685
 686         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
 687
 688         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
 689         if (ret)
 690                 return ret;
 691
 692         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
 693
 694         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
 695         if (ret)
 696                 return ret;
 697
 698         psp->vbflash_done = true;
 699
 700         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
 701         if (ret)
 702                 return ret;
 703
 704         return 0;
 705 }
 706
 707 static int psp_v13_0_vbflash_status(struct psp_context *psp)
 708 {
 709         struct amdgpu_device *adev = psp->adev;
 710
 711         return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 712 }
 713
 714 static const struct psp_funcs psp_v13_0_funcs = {
 715         .init_microcode = psp_v13_0_init_microcode,
 716         .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
 717         .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
 718         .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
 719         .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
 720         .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
 721         .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
 722         .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
 723         .ring_init = psp_v13_0_ring_init,
 724         .ring_create = psp_v13_0_ring_create,
 725         .ring_stop = psp_v13_0_ring_stop,
 726         .ring_destroy = psp_v13_0_ring_destroy,
 727         .ring_get_wptr = psp_v13_0_ring_get_wptr,
 728         .ring_set_wptr = psp_v13_0_ring_set_wptr,
 729         .mem_training = psp_v13_0_memory_training,
 730         .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
 731         .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
 732         .update_spirom = psp_v13_0_update_spirom,
 733         .vbflash_stat = psp_v13_0_vbflash_status
 734 };
 735
 736 void psp_v13_0_set_psp_funcs(struct psp_context *psp)
 737 {
 738         psp->funcs = &psp_v13_0_funcs;
 739 }