drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "mmhub_v3_0_2.h"
  26
  27 #include "mmhub/mmhub_3_0_2_offset.h"
  28 #include "mmhub/mmhub_3_0_2_sh_mask.h"
  29 #include "navi10_enum.h"
  30
  31 #include "soc15_common.h"
  32
  33 #define regMMVM_L2_CNTL3_DEFAULT                                0x80100007
  34 #define regMMVM_L2_CNTL4_DEFAULT                                0x000000c1
  35 #define regMMVM_L2_CNTL5_DEFAULT                                0x00003fe0
  36
  37 static const char *mmhub_client_ids_v3_0_2[][2] = {
  38         [0][0] = "VMC",
  39         [4][0] = "DCEDMC",
  40         [5][0] = "DCEVGA",
  41         [6][0] = "MP0",
  42         [7][0] = "MP1",
  43         [8][0] = "MPIO",
  44         [16][0] = "HDP",
  45         [17][0] = "LSDMA",
  46         [18][0] = "JPEG",
  47         [19][0] = "VCNU0",
  48         [21][0] = "VSCH",
  49         [22][0] = "VCNU1",
  50         [23][0] = "VCN1",
  51         [32+20][0] = "VCN0",
  52         [2][1] = "DBGUNBIO",
  53         [3][1] = "DCEDWB",
  54         [4][1] = "DCEDMC",
  55         [5][1] = "DCEVGA",
  56         [6][1] = "MP0",
  57         [7][1] = "MP1",
  58         [8][1] = "MPIO",
  59         [10][1] = "DBGU0",
  60         [11][1] = "DBGU1",
  61         [12][1] = "DBGU2",
  62         [13][1] = "DBGU3",
  63         [14][1] = "XDP",
  64         [15][1] = "OSSSYS",
  65         [16][1] = "HDP",
  66         [17][1] = "LSDMA",
  67         [18][1] = "JPEG",
  68         [19][1] = "VCNU0",
  69         [20][1] = "VCN0",
  70         [21][1] = "VSCH",
  71         [22][1] = "VCNU1",
  72         [23][1] = "VCN1",
  73 };
  74
  75 static uint32_t mmhub_v3_0_2_get_invalidate_req(unsigned int vmid,
  76                                               uint32_t flush_type)
  77 {
  78         u32 req = 0;
  79
  80         /* invalidate using legacy mode on vmid*/
  81         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
  82                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
  83         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
  84         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
  85         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
  86         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
  87         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
  88         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
  89         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
  90                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
  91
  92         return req;
  93 }
  94
  95 static void
  96 mmhub_v3_0_2_print_l2_protection_fault_status(struct amdgpu_device *adev,
  97                                              uint32_t status)
  98 {
  99         uint32_t cid, rw;
 100         const char *mmhub_cid = NULL;
 101
 102         cid = REG_GET_FIELD(status,
 103                             MMVM_L2_PROTECTION_FAULT_STATUS, CID);
 104         rw = REG_GET_FIELD(status,
 105                            MMVM_L2_PROTECTION_FAULT_STATUS, RW);
 106
 107         dev_err(adev->dev,
 108                 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 109                 status);
 110
 111         mmhub_cid = mmhub_client_ids_v3_0_2[cid][rw];
 112         dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 113                 mmhub_cid ? mmhub_cid : "unknown", cid);
 114         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 115                 REG_GET_FIELD(status,
 116                 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 117         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 118                 REG_GET_FIELD(status,
 119                 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 120         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 121                 REG_GET_FIELD(status,
 122                 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 123         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 124                 REG_GET_FIELD(status,
 125                 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 126         dev_err(adev->dev, "\t RW: 0x%x\n", rw);
 127 }
 128
 129 static void mmhub_v3_0_2_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
 130                                 uint64_t page_table_base)
 131 {
 132         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
 133
 134         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
 135                             hub->ctx_addr_distance * vmid,
 136                             lower_32_bits(page_table_base));
 137
 138         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
 139                             hub->ctx_addr_distance * vmid,
 140                             upper_32_bits(page_table_base));
 141 }
 142
 143 static void mmhub_v3_0_2_init_gart_aperture_regs(struct amdgpu_device *adev)
 144 {
 145         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
 146
 147         mmhub_v3_0_2_setup_vm_pt_regs(adev, 0, pt_base);
 148
 149         WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
 150                      (u32)(adev->gmc.gart_start >> 12));
 151         WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
 152                      (u32)(adev->gmc.gart_start >> 44));
 153
 154         WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
 155                      (u32)(adev->gmc.gart_end >> 12));
 156         WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 157                      (u32)(adev->gmc.gart_end >> 44));
 158 }
 159
 160 static void mmhub_v3_0_2_init_system_aperture_regs(struct amdgpu_device *adev)
 161 {
 162         uint64_t value;
 163         uint32_t tmp;
 164
 165         /* Program the AGP BAR */
 166         WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
 167         WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
 168         WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 169
 170         if (!amdgpu_sriov_vf(adev)) {
 171                 /*
 172                  * the new L1 policy will block SRIOV guest from writing
 173                  * these regs, and they will be programed at host.
 174                  * so skip programing these regs.
 175                  */
 176                 /* Program the system aperture low logical page number. */
 177                 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 178                              min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 179                 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 180                              max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 181         }
 182
 183         /* Set default page address. */
 184         value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start +
 185                 adev->vm_manager.vram_base_offset;
 186         WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 187                      (u32)(value >> 12));
 188         WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 189                      (u32)(value >> 44));
 190
 191         /* Program "protection fault". */
 192         WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 193                      (u32)(adev->dummy_page_addr >> 12));
 194         WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 195                      (u32)((u64)adev->dummy_page_addr >> 44));
 196
 197         tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
 198         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
 199                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 200         WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 201 }
 202
 203 static void mmhub_v3_0_2_init_tlb_regs(struct amdgpu_device *adev)
 204 {
 205         uint32_t tmp;
 206
 207         /* Setup TLB control */
 208         tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
 209
 210         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 211         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 212         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 213                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 214         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 215                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 216         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 217         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 218                             MTYPE, MTYPE_UC); /* UC, uncached */
 219
 220         WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
 221 }
 222
 223 static void mmhub_v3_0_2_init_cache_regs(struct amdgpu_device *adev)
 224 {
 225         uint32_t tmp;
 226
 227         /* These registers are not accessible to VF-SRIOV.
 228          * The PF will program them instead.
 229          */
 230         if (amdgpu_sriov_vf(adev))
 231                 return;
 232
 233         /* Setup L2 cache */
 234         tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
 235         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
 236         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
 237         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
 238                             ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 239         /* XXX for emulation, Refer to closed source code.*/
 240         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 241                             0);
 242         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 243         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 244         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 245         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
 246
 247         tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
 248         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 249         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 250         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
 251
 252         tmp = regMMVM_L2_CNTL3_DEFAULT;
 253         if (adev->gmc.translate_further) {
 254                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
 255                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
 256                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 257         } else {
 258                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
 259                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
 260                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 261         }
 262         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
 263
 264         tmp = regMMVM_L2_CNTL4_DEFAULT;
 265         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 266         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 267         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
 268
 269         tmp = regMMVM_L2_CNTL5_DEFAULT;
 270         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
 271         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
 272 }
 273
 274 static void mmhub_v3_0_2_enable_system_domain(struct amdgpu_device *adev)
 275 {
 276         uint32_t tmp;
 277
 278         tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
 279         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 280         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 281         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
 282                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 283         WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
 284 }
 285
 286 static void mmhub_v3_0_2_disable_identity_aperture(struct amdgpu_device *adev)
 287 {
 288         /* These registers are not accessible to VF-SRIOV.
 289          * The PF will program them instead.
 290          */
 291         if (amdgpu_sriov_vf(adev))
 292                 return;
 293
 294         WREG32_SOC15(MMHUB, 0,
 295                      regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 296                      0xFFFFFFFF);
 297         WREG32_SOC15(MMHUB, 0,
 298                      regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 299                      0x0000000F);
 300
 301         WREG32_SOC15(MMHUB, 0,
 302                      regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
 303         WREG32_SOC15(MMHUB, 0,
 304                      regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
 305
 306         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 307                      0);
 308         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 309                      0);
 310 }
 311
 312 static void mmhub_v3_0_2_setup_vmid_config(struct amdgpu_device *adev)
 313 {
 314         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
 315         int i;
 316         uint32_t tmp;
 317
 318         for (i = 0; i <= 14; i++) {
 319                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
 320                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 321                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 322                                     adev->vm_manager.num_level);
 323                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 324                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 325                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 326                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 327                                     1);
 328                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 329                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 330                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 331                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 332                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 333                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 334                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 335                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 336                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 337                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 338                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 339                                     PAGE_TABLE_BLOCK_SIZE,
 340                                     adev->vm_manager.block_size - 9);
 341                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 342                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 343                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 344                                     !amdgpu_noretry);
 345                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,
 346                                     i * hub->ctx_distance, tmp);
 347                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 348                                     i * hub->ctx_addr_distance, 0);
 349                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 350                                     i * hub->ctx_addr_distance, 0);
 351                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 352                                     i * hub->ctx_addr_distance,
 353                                     lower_32_bits(adev->vm_manager.max_pfn - 1));
 354                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 355                                     i * hub->ctx_addr_distance,
 356                                     upper_32_bits(adev->vm_manager.max_pfn - 1));
 357         }
 358
 359         hub->vm_cntx_cntl = tmp;
 360 }
 361
 362 static void mmhub_v3_0_2_program_invalidation(struct amdgpu_device *adev)
 363 {
 364         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
 365         unsigned i;
 366
 367         for (i = 0; i < 18; ++i) {
 368                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 369                                     i * hub->eng_addr_distance, 0xffffffff);
 370                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 371                                     i * hub->eng_addr_distance, 0x1f);
 372         }
 373 }
 374
 375 static int mmhub_v3_0_2_gart_enable(struct amdgpu_device *adev)
 376 {
 377         /* GART Enable. */
 378         mmhub_v3_0_2_init_gart_aperture_regs(adev);
 379         mmhub_v3_0_2_init_system_aperture_regs(adev);
 380         mmhub_v3_0_2_init_tlb_regs(adev);
 381         mmhub_v3_0_2_init_cache_regs(adev);
 382
 383         mmhub_v3_0_2_enable_system_domain(adev);
 384         mmhub_v3_0_2_disable_identity_aperture(adev);
 385         mmhub_v3_0_2_setup_vmid_config(adev);
 386         mmhub_v3_0_2_program_invalidation(adev);
 387
 388         return 0;
 389 }
 390
 391 static void mmhub_v3_0_2_gart_disable(struct amdgpu_device *adev)
 392 {
 393         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
 394         u32 tmp;
 395         u32 i;
 396
 397         /* Disable all tables */
 398         for (i = 0; i < 16; i++)
 399                 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL,
 400                                     i * hub->ctx_distance, 0);
 401
 402         /* Setup TLB control */
 403         tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
 404         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 405         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 406                             ENABLE_ADVANCED_DRIVER_MODEL, 0);
 407         WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
 408
 409         /* Setup L2 cache */
 410         tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
 411         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
 412         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
 413         WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0);
 414 }
 415
 416 /**
 417  * mmhub_v3_0_2_set_fault_enable_default - update GART/VM fault handling
 418  *
 419  * @adev: amdgpu_device pointer
 420  * @value: true redirects VM faults to the default page
 421  */
 422 static void mmhub_v3_0_2_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 423 {
 424         u32 tmp;
 425
 426         /* These registers are not accessible to VF-SRIOV.
 427          * The PF will program them instead.
 428          */
 429         if (amdgpu_sriov_vf(adev))
 430                 return;
 431
 432         tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
 433         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 434                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 435         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 436                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 437         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 438                             PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 439         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 440                             PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 441         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 442                             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 443                             value);
 444         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 445                             NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 446         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 447                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 448         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 449                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 450         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 451                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 452         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 453                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 454         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 455                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 456         if (!value) {
 457                 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 458                                 CRASH_ON_NO_RETRY_FAULT, 1);
 459                 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 460                                 CRASH_ON_RETRY_FAULT, 1);
 461         }
 462         WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
 463 }
 464
 465 static const struct amdgpu_vmhub_funcs mmhub_v3_0_2_vmhub_funcs = {
 466         .print_l2_protection_fault_status = mmhub_v3_0_2_print_l2_protection_fault_status,
 467         .get_invalidate_req = mmhub_v3_0_2_get_invalidate_req,
 468 };
 469
 470 static void mmhub_v3_0_2_init(struct amdgpu_device *adev)
 471 {
 472         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];
 473
 474         hub->ctx0_ptb_addr_lo32 =
 475                 SOC15_REG_OFFSET(MMHUB, 0,
 476                                  regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 477         hub->ctx0_ptb_addr_hi32 =
 478                 SOC15_REG_OFFSET(MMHUB, 0,
 479                                  regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 480         hub->vm_inv_eng0_sem =
 481                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
 482         hub->vm_inv_eng0_req =
 483                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
 484         hub->vm_inv_eng0_ack =
 485                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
 486         hub->vm_context0_cntl =
 487                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
 488         hub->vm_l2_pro_fault_status =
 489                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS);
 490         hub->vm_l2_pro_fault_cntl =
 491                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
 492
 493         hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL;
 494         hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 495                 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 496         hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ -
 497                 regMMVM_INVALIDATE_ENG0_REQ;
 498         hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 499                 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 500
 501         hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 502                 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 503                 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 504                 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 505                 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 506                 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 507                 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 508
 509         hub->vm_l2_bank_select_reserved_cid2 =
 510                 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2);
 511
 512         hub->vmhub_funcs = &mmhub_v3_0_2_vmhub_funcs;
 513 }
 514
 515 static u64 mmhub_v3_0_2_get_fb_location(struct amdgpu_device *adev)
 516 {
 517         u64 base;
 518
 519         base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);
 520         base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
 521         base <<= 24;
 522
 523         return base;
 524 }
 525
 526 static u64 mmhub_v3_0_2_get_mc_fb_offset(struct amdgpu_device *adev)
 527 {
 528         return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;
 529 }
 530
 531 static void mmhub_v3_0_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 532                                                         bool enable)
 533 {
 534         //TODO
 535 }
 536
 537 static void mmhub_v3_0_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 538                                                        bool enable)
 539 {
 540         //TODO
 541 }
 542
 543 static int mmhub_v3_0_2_set_clockgating(struct amdgpu_device *adev,
 544                                enum amd_clockgating_state state)
 545 {
 546         if (amdgpu_sriov_vf(adev))
 547                 return 0;
 548
 549         mmhub_v3_0_2_update_medium_grain_clock_gating(adev,
 550                         state == AMD_CG_STATE_GATE);
 551         mmhub_v3_0_2_update_medium_grain_light_sleep(adev,
 552                         state == AMD_CG_STATE_GATE);
 553         return 0;
 554 }
 555
 556 static void mmhub_v3_0_2_get_clockgating(struct amdgpu_device *adev, u64 *flags)
 557 {
 558         //TODO
 559 }
 560
 561 const struct amdgpu_mmhub_funcs mmhub_v3_0_2_funcs = {
 562         .init = mmhub_v3_0_2_init,
 563         .get_fb_location = mmhub_v3_0_2_get_fb_location,
 564         .get_mc_fb_offset = mmhub_v3_0_2_get_mc_fb_offset,
 565         .gart_enable = mmhub_v3_0_2_gart_enable,
 566         .set_fault_enable_default = mmhub_v3_0_2_set_fault_enable_default,
 567         .gart_disable = mmhub_v3_0_2_gart_disable,
 568         .set_clockgating = mmhub_v3_0_2_set_clockgating,
 569         .get_clockgating = mmhub_v3_0_2_get_clockgating,
 570         .setup_vm_pt_regs = mmhub_v3_0_2_setup_vm_pt_regs,
 571 };