2 * Copyright 2023 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/pci.h>
27 #include "amdgpu_ih.h"
29 #include "oss/osssys_7_0_0_offset.h"
30 #include "oss/osssys_7_0_0_sh_mask.h"
32 #include "soc15_common.h"
35 #define MAX_REARM_RETRY 10
37 static void ih_v7_0_set_interrupt_funcs(struct amdgpu_device *adev);
40 * ih_v7_0_init_register_offset - Initialize register offset for ih rings
42 * @adev: amdgpu_device pointer
44 * Initialize register offset ih rings (IH_V7_0).
46 static void ih_v7_0_init_register_offset(struct amdgpu_device *adev)
48 struct amdgpu_ih_regs *ih_regs;
50 /* ih ring 2 is removed
51 * ih ring and ih ring 1 are available */
52 if (adev->irq.ih.ring_size) {
53 ih_regs = &adev->irq.ih.ih_regs;
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE);
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI);
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL);
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR);
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR);
59 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR);
60 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_LO);
61 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_HI);
62 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
65 if (adev->irq.ih1.ring_size) {
66 ih_regs = &adev->irq.ih1.ih_regs;
67 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_RING1);
68 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI_RING1);
69 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1);
70 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1);
71 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR_RING1);
72 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR_RING1);
73 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
78 * force_update_wptr_for_self_int - Force update the wptr for self interrupt
80 * @adev: amdgpu_device pointer
81 * @threshold: threshold to trigger the wptr reporting
82 * @timeout: timeout to trigger the wptr reporting
83 * @enabled: Enable/disable timeout flush mechanism
85 * threshold input range: 0 ~ 15, default 0,
86 * real_threshold = 2^threshold
87 * timeout input range: 0 ~ 20, default 8,
88 * real_timeout = (2^timeout) * 1024 / (socclk_freq)
90 * Force update wptr for self interrupt ( >= SIENNA_CICHLID).
93 force_update_wptr_for_self_int(struct amdgpu_device *adev,
94 u32 threshold, u32 timeout, bool enabled)
96 u32 ih_cntl, ih_rb_cntl;
98 ih_cntl = RREG32_SOC15(OSSSYS, 0, regIH_CNTL2);
99 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1);
101 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,
102 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout);
103 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,
104 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled);
105 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
106 RB_USED_INT_THRESHOLD, threshold);
108 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
109 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl))
112 WREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1, ih_rb_cntl);
115 WREG32_SOC15(OSSSYS, 0, regIH_CNTL2, ih_cntl);
119 * ih_v7_0_toggle_ring_interrupts - toggle the interrupt ring buffer
121 * @adev: amdgpu_device pointer
122 * @ih: amdgpu_ih_ring pointet
123 * @enable: true - enable the interrupts, false - disable the interrupts
125 * Toggle the interrupt ring buffer (IH_V7_0)
127 static int ih_v7_0_toggle_ring_interrupts(struct amdgpu_device *adev,
128 struct amdgpu_ih_ring *ih,
131 struct amdgpu_ih_regs *ih_regs;
134 ih_regs = &ih->ih_regs;
136 tmp = RREG32(ih_regs->ih_rb_cntl);
137 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
138 /* enable_intr field is only valid in ring0 */
139 if (ih == &adev->irq.ih)
140 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
142 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
143 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
146 WREG32(ih_regs->ih_rb_cntl, tmp);
152 /* set rptr, wptr to 0 */
153 WREG32(ih_regs->ih_rb_rptr, 0);
154 WREG32(ih_regs->ih_rb_wptr, 0);
163 * ih_v7_0_toggle_interrupts - Toggle all the available interrupt ring buffers
165 * @adev: amdgpu_device pointer
166 * @enable: enable or disable interrupt ring buffers
168 * Toggle all the available interrupt ring buffers (IH_V7_0).
170 static int ih_v7_0_toggle_interrupts(struct amdgpu_device *adev, bool enable)
172 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1};
176 for (i = 0; i < ARRAY_SIZE(ih); i++) {
177 if (ih[i]->ring_size) {
178 r = ih_v7_0_toggle_ring_interrupts(adev, ih[i], enable);
187 static uint32_t ih_v7_0_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
189 int rb_bufsz = order_base_2(ih->ring_size / 4);
191 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
192 MC_SPACE, ih->use_bus_addr ? 2 : 4);
193 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
194 WPTR_OVERFLOW_CLEAR, 1);
195 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
196 WPTR_OVERFLOW_ENABLE, 1);
197 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
198 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
199 * value is written to memory
201 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
202 WPTR_WRITEBACK_ENABLE, 1);
203 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
204 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
205 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
210 static uint32_t ih_v7_0_doorbell_rptr(struct amdgpu_ih_ring *ih)
212 u32 ih_doorbell_rtpr = 0;
214 if (ih->use_doorbell) {
215 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
216 IH_DOORBELL_RPTR, OFFSET,
218 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
222 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
226 return ih_doorbell_rtpr;
230 * ih_v7_0_enable_ring - enable an ih ring buffer
232 * @adev: amdgpu_device pointer
233 * @ih: amdgpu_ih_ring pointer
235 * Enable an ih ring buffer (IH_V7_0)
237 static int ih_v7_0_enable_ring(struct amdgpu_device *adev,
238 struct amdgpu_ih_ring *ih)
240 struct amdgpu_ih_regs *ih_regs;
243 ih_regs = &ih->ih_regs;
245 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
246 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
247 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
249 tmp = RREG32(ih_regs->ih_rb_cntl);
250 tmp = ih_v7_0_rb_cntl(ih, tmp);
251 if (ih == &adev->irq.ih)
252 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
253 if (ih == &adev->irq.ih1) {
254 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
255 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
258 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
259 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
260 DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
264 WREG32(ih_regs->ih_rb_cntl, tmp);
267 if (ih == &adev->irq.ih) {
268 /* set the ih ring 0 writeback address whether it's enabled or not */
269 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
270 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
273 /* set rptr, wptr to 0 */
274 WREG32(ih_regs->ih_rb_wptr, 0);
275 WREG32(ih_regs->ih_rb_rptr, 0);
277 WREG32(ih_regs->ih_doorbell_rptr, ih_v7_0_doorbell_rptr(ih));
283 * ih_v7_0_irq_init - init and enable the interrupt ring
285 * @adev: amdgpu_device pointer
287 * Allocate a ring buffer for the interrupt controller,
288 * enable the RLC, disable interrupts, enable the IH
289 * ring buffer and enable it.
290 * Called at device load and reume.
291 * Returns 0 for success, errors for failure.
293 static int ih_v7_0_irq_init(struct amdgpu_device *adev)
295 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1};
302 ret = ih_v7_0_toggle_interrupts(adev, false);
306 adev->nbio.funcs->ih_control(adev);
308 if (unlikely((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) ||
309 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO))) {
310 if (ih[0]->use_bus_addr) {
311 ih_chicken = RREG32_SOC15(OSSSYS, 0, regIH_CHICKEN);
312 ih_chicken = REG_SET_FIELD(ih_chicken,
313 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
314 WREG32_SOC15(OSSSYS, 0, regIH_CHICKEN, ih_chicken);
318 for (i = 0; i < ARRAY_SIZE(ih); i++) {
319 if (ih[i]->ring_size) {
320 ret = ih_v7_0_enable_ring(adev, ih[i]);
326 /* update doorbell range for ih ring 0 */
327 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell,
328 ih[0]->doorbell_index);
330 tmp = RREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL);
331 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
332 CLIENT18_IS_STORM_CLIENT, 1);
333 WREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL, tmp);
335 tmp = RREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL);
336 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
337 WREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL, tmp);
339 /* GC/MMHUB UTCL2 page fault interrupts are configured as
340 * MSI storm capable interrupts by deafult. The delay is
341 * used to avoid ISR being called too frequently
342 * when page fault happens on several continuous page
343 * and thus avoid MSI storm */
344 tmp = RREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL);
345 tmp = REG_SET_FIELD(tmp, IH_MSI_STORM_CTRL,
347 WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);
349 pci_set_master(adev->pdev);
351 /* enable interrupts */
352 ret = ih_v7_0_toggle_interrupts(adev, true);
355 /* enable wptr force update for self int */
356 force_update_wptr_for_self_int(adev, 0, 8, true);
358 if (adev->irq.ih_soft.ring_size)
359 adev->irq.ih_soft.enabled = true;
365 * ih_v7_0_irq_disable - disable interrupts
367 * @adev: amdgpu_device pointer
369 * Disable interrupts on the hw.
371 static void ih_v7_0_irq_disable(struct amdgpu_device *adev)
373 force_update_wptr_for_self_int(adev, 0, 8, false);
374 ih_v7_0_toggle_interrupts(adev, false);
376 /* Wait and acknowledge irq */
381 * ih_v7_0_get_wptr() - get the IH ring buffer wptr
383 * @adev: amdgpu_device pointer
384 * @ih: IH ring buffer to fetch wptr
386 * Get the IH ring buffer wptr from either the register
387 * or the writeback memory buffer. Also check for
388 * ring buffer overflow and deal with it.
389 * Returns the value of the wptr.
391 static u32 ih_v7_0_get_wptr(struct amdgpu_device *adev,
392 struct amdgpu_ih_ring *ih)
395 struct amdgpu_ih_regs *ih_regs;
397 wptr = le32_to_cpu(*ih->wptr_cpu);
398 ih_regs = &ih->ih_regs;
400 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
403 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
404 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
406 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
408 /* When a ring buffer overflow happen start parsing interrupt
409 * from the last not overwritten vector (wptr + 32). Hopefully
410 * this should allow us to catch up.
412 tmp = (wptr + 32) & ih->ptr_mask;
413 dev_warn(adev->dev, "IH ring buffer overflow "
414 "(0x%08X, 0x%08X, 0x%08X)\n",
415 wptr, ih->rptr, tmp);
418 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
419 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
420 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
422 return (wptr & ih->ptr_mask);
426 * ih_v7_0_irq_rearm - rearm IRQ if lost
428 * @adev: amdgpu_device pointer
429 * @ih: IH ring to match
432 static void ih_v7_0_irq_rearm(struct amdgpu_device *adev,
433 struct amdgpu_ih_ring *ih)
437 struct amdgpu_ih_regs *ih_regs;
439 ih_regs = &ih->ih_regs;
441 /* Rearm IRQ / re-write doorbell if doorbell write is lost */
442 for (i = 0; i < MAX_REARM_RETRY; i++) {
443 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
444 if ((v < ih->ring_size) && (v != ih->rptr))
445 WDOORBELL32(ih->doorbell_index, ih->rptr);
452 * ih_v7_0_set_rptr - set the IH ring buffer rptr
454 * @adev: amdgpu_device pointer
455 * @ih: IH ring buffer to set rptr
457 static void ih_v7_0_set_rptr(struct amdgpu_device *adev,
458 struct amdgpu_ih_ring *ih)
460 struct amdgpu_ih_regs *ih_regs;
462 if (ih->use_doorbell) {
463 /* XXX check if swapping is necessary on BE */
464 *ih->rptr_cpu = ih->rptr;
465 WDOORBELL32(ih->doorbell_index, ih->rptr);
467 if (amdgpu_sriov_vf(adev))
468 ih_v7_0_irq_rearm(adev, ih);
470 ih_regs = &ih->ih_regs;
471 WREG32(ih_regs->ih_rb_rptr, ih->rptr);
476 * ih_v7_0_self_irq - dispatch work for ring 1
478 * @adev: amdgpu_device pointer
479 * @source: irq source
480 * @entry: IV with WPTR update
482 * Update the WPTR from the IV and schedule work to handle the entries.
484 static int ih_v7_0_self_irq(struct amdgpu_device *adev,
485 struct amdgpu_irq_src *source,
486 struct amdgpu_iv_entry *entry)
488 uint32_t wptr = cpu_to_le32(entry->src_data[0]);
490 switch (entry->ring_id) {
492 *adev->irq.ih1.wptr_cpu = wptr;
493 schedule_work(&adev->irq.ih1_work);
500 static const struct amdgpu_irq_src_funcs ih_v7_0_self_irq_funcs = {
501 .process = ih_v7_0_self_irq,
504 static void ih_v7_0_set_self_irq_funcs(struct amdgpu_device *adev)
506 adev->irq.self_irq.num_types = 0;
507 adev->irq.self_irq.funcs = &ih_v7_0_self_irq_funcs;
510 static int ih_v7_0_early_init(void *handle)
512 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
514 ih_v7_0_set_interrupt_funcs(adev);
515 ih_v7_0_set_self_irq_funcs(adev);
519 static int ih_v7_0_sw_init(void *handle)
522 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
525 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_IH, 0,
526 &adev->irq.self_irq);
531 /* use gpu virtual address for ih ring
532 * until ih_checken is programmed to allow
533 * use bus address for ih ring by psp bl */
535 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true;
536 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr);
540 adev->irq.ih.use_doorbell = true;
541 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
543 adev->irq.ih1.ring_size = 0;
544 adev->irq.ih2.ring_size = 0;
546 /* initialize ih control register offset */
547 ih_v7_0_init_register_offset(adev);
549 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true);
553 r = amdgpu_irq_init(adev);
558 static int ih_v7_0_sw_fini(void *handle)
560 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
562 amdgpu_irq_fini_sw(adev);
567 static int ih_v7_0_hw_init(void *handle)
570 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
572 r = ih_v7_0_irq_init(adev);
579 static int ih_v7_0_hw_fini(void *handle)
581 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
583 ih_v7_0_irq_disable(adev);
588 static int ih_v7_0_suspend(void *handle)
590 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
592 return ih_v7_0_hw_fini(adev);
595 static int ih_v7_0_resume(void *handle)
597 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
599 return ih_v7_0_hw_init(adev);
602 static bool ih_v7_0_is_idle(void *handle)
608 static int ih_v7_0_wait_for_idle(void *handle)
614 static int ih_v7_0_soft_reset(void *handle)
620 static void ih_v7_0_update_clockgating_state(struct amdgpu_device *adev,
623 uint32_t data, def, field_val;
625 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
626 def = data = RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL);
627 field_val = enable ? 0 : 1;
628 data = REG_SET_FIELD(data, IH_CLK_CTRL,
629 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
630 data = REG_SET_FIELD(data, IH_CLK_CTRL,
631 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
632 data = REG_SET_FIELD(data, IH_CLK_CTRL,
633 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
634 data = REG_SET_FIELD(data, IH_CLK_CTRL,
635 DYN_CLK_SOFT_OVERRIDE, field_val);
636 data = REG_SET_FIELD(data, IH_CLK_CTRL,
637 REG_CLK_SOFT_OVERRIDE, field_val);
639 WREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL, data);
645 static int ih_v7_0_set_clockgating_state(void *handle,
646 enum amd_clockgating_state state)
648 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
650 ih_v7_0_update_clockgating_state(adev,
651 state == AMD_CG_STATE_GATE);
655 static void ih_v7_0_update_ih_mem_power_gating(struct amdgpu_device *adev,
658 uint32_t ih_mem_pwr_cntl;
660 /* Disable ih sram power cntl before switch powergating mode */
661 ih_mem_pwr_cntl = RREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL);
662 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
663 IH_BUFFER_MEM_POWER_CTRL_EN, 0);
664 WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
666 /* It is recommended to set mem powergating mode to DS mode */
669 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
670 IH_BUFFER_MEM_POWER_LS_EN, 0);
671 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
672 IH_BUFFER_MEM_POWER_DS_EN, 1);
673 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
674 IH_BUFFER_MEM_POWER_SD_EN, 0);
675 /* cam mem power mode */
676 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
677 IH_RETRY_INT_CAM_MEM_POWER_LS_EN, 0);
678 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
679 IH_RETRY_INT_CAM_MEM_POWER_DS_EN, 1);
680 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
681 IH_RETRY_INT_CAM_MEM_POWER_SD_EN, 0);
682 /* re-enable power cntl */
683 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
684 IH_BUFFER_MEM_POWER_CTRL_EN, 1);
687 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
688 IH_BUFFER_MEM_POWER_LS_EN, 0);
689 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
690 IH_BUFFER_MEM_POWER_DS_EN, 0);
691 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
692 IH_BUFFER_MEM_POWER_SD_EN, 0);
693 /* cam mem power mode */
694 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
695 IH_RETRY_INT_CAM_MEM_POWER_LS_EN, 0);
696 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
697 IH_RETRY_INT_CAM_MEM_POWER_DS_EN, 0);
698 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
699 IH_RETRY_INT_CAM_MEM_POWER_SD_EN, 0);
700 /* re-enable power cntl*/
701 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
702 IH_BUFFER_MEM_POWER_CTRL_EN, 1);
705 WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
708 static int ih_v7_0_set_powergating_state(void *handle,
709 enum amd_powergating_state state)
711 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
712 bool enable = (state == AMD_PG_STATE_GATE);
714 if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
715 ih_v7_0_update_ih_mem_power_gating(adev, enable);
720 static void ih_v7_0_get_clockgating_state(void *handle, u64 *flags)
722 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
724 if (!RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL))
725 *flags |= AMD_CG_SUPPORT_IH_CG;
730 static const struct amd_ip_funcs ih_v7_0_ip_funcs = {
732 .early_init = ih_v7_0_early_init,
734 .sw_init = ih_v7_0_sw_init,
735 .sw_fini = ih_v7_0_sw_fini,
736 .hw_init = ih_v7_0_hw_init,
737 .hw_fini = ih_v7_0_hw_fini,
738 .suspend = ih_v7_0_suspend,
739 .resume = ih_v7_0_resume,
740 .is_idle = ih_v7_0_is_idle,
741 .wait_for_idle = ih_v7_0_wait_for_idle,
742 .soft_reset = ih_v7_0_soft_reset,
743 .set_clockgating_state = ih_v7_0_set_clockgating_state,
744 .set_powergating_state = ih_v7_0_set_powergating_state,
745 .get_clockgating_state = ih_v7_0_get_clockgating_state,
748 static const struct amdgpu_ih_funcs ih_v7_0_funcs = {
749 .get_wptr = ih_v7_0_get_wptr,
750 .decode_iv = amdgpu_ih_decode_iv_helper,
751 .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
752 .set_rptr = ih_v7_0_set_rptr
755 static void ih_v7_0_set_interrupt_funcs(struct amdgpu_device *adev)
757 adev->irq.ih_funcs = &ih_v7_0_funcs;
760 const struct amdgpu_ip_block_version ih_v7_0_ip_block =
762 .type = AMD_IP_BLOCK_TYPE_IH,
766 .funcs = &ih_v7_0_ip_funcs,