drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/drm_cache.h>
  29 #include "amdgpu.h"
  30 #include "cikd.h"
  31 #include "cik.h"
  32 #include "gmc_v7_0.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_amdkfd.h"
  35 #include "amdgpu_gem.h"
  36
  37 #include "bif/bif_4_1_d.h"
  38 #include "bif/bif_4_1_sh_mask.h"
  39
  40 #include "gmc/gmc_7_1_d.h"
  41 #include "gmc/gmc_7_1_sh_mask.h"
  42
  43 #include "oss/oss_2_0_d.h"
  44 #include "oss/oss_2_0_sh_mask.h"
  45
  46 #include "dce/dce_8_0_d.h"
  47 #include "dce/dce_8_0_sh_mask.h"
  48
  49 #include "amdgpu_atombios.h"
  50
  51 #include "ivsrcid/ivsrcid_vislands30.h"
  52
  53 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev);
  54 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  55 static int gmc_v7_0_wait_for_idle(void *handle);
  56
  57 MODULE_FIRMWARE("amdgpu/bonaire_mc.bin");
  58 MODULE_FIRMWARE("amdgpu/hawaii_mc.bin");
  59 MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
  60
  61 static const u32 golden_settings_iceland_a11[] =
  62 {
  63         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  64         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  65         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  66         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  67 };
  68
  69 static const u32 iceland_mgcg_cgcg_init[] =
  70 {
  71         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  72 };
  73
  74 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
  75 {
  76         switch (adev->asic_type) {
  77         case CHIP_TOPAZ:
  78                 amdgpu_device_program_register_sequence(adev,
  79                                                         iceland_mgcg_cgcg_init,
  80                                                         ARRAY_SIZE(iceland_mgcg_cgcg_init));
  81                 amdgpu_device_program_register_sequence(adev,
  82                                                         golden_settings_iceland_a11,
  83                                                         ARRAY_SIZE(golden_settings_iceland_a11));
  84                 break;
  85         default:
  86                 break;
  87         }
  88 }
  89
  90 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev)
  91 {
  92         u32 blackout;
  93
  94         gmc_v7_0_wait_for_idle((void *)adev);
  95
  96         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
  97         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
  98                 /* Block CPU access */
  99                 WREG32(mmBIF_FB_EN, 0);
 100                 /* blackout the MC */
 101                 blackout = REG_SET_FIELD(blackout,
 102                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 103                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
 104         }
 105         /* wait for the MC to settle */
 106         udelay(100);
 107 }
 108
 109 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev)
 110 {
 111         u32 tmp;
 112
 113         /* unblackout the MC */
 114         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 115         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 116         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 117         /* allow CPU access */
 118         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 119         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 120         WREG32(mmBIF_FB_EN, tmp);
 121 }
 122
 123 /**
 124  * gmc_v7_0_init_microcode - load ucode images from disk
 125  *
 126  * @adev: amdgpu_device pointer
 127  *
 128  * Use the firmware interface to load the ucode images into
 129  * the driver (not loaded into hw).
 130  * Returns 0 on success, error on failure.
 131  */
 132 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
 133 {
 134         const char *chip_name;
 135         char fw_name[30];
 136         int err;
 137
 138         DRM_DEBUG("\n");
 139
 140         switch (adev->asic_type) {
 141         case CHIP_BONAIRE:
 142                 chip_name = "bonaire";
 143                 break;
 144         case CHIP_HAWAII:
 145                 chip_name = "hawaii";
 146                 break;
 147         case CHIP_TOPAZ:
 148                 chip_name = "topaz";
 149                 break;
 150         case CHIP_KAVERI:
 151         case CHIP_KABINI:
 152         case CHIP_MULLINS:
 153                 return 0;
 154         default: BUG();
 155         }
 156
 157         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 158
 159         err = amdgpu_ucode_request(adev, &adev->gmc.fw, fw_name);
 160         if (err) {
 161                 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name);
 162                 amdgpu_ucode_release(&adev->gmc.fw);
 163         }
 164         return err;
 165 }
 166
 167 /**
 168  * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
 169  *
 170  * @adev: amdgpu_device pointer
 171  *
 172  * Load the GDDR MC ucode into the hw (CIK).
 173  * Returns 0 on success, error on failure.
 174  */
 175 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
 176 {
 177         const struct mc_firmware_header_v1_0 *hdr;
 178         const __le32 *fw_data = NULL;
 179         const __le32 *io_mc_regs = NULL;
 180         u32 running;
 181         int i, ucode_size, regs_size;
 182
 183         if (!adev->gmc.fw)
 184                 return -EINVAL;
 185
 186         hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
 187         amdgpu_ucode_print_mc_hdr(&hdr->header);
 188
 189         adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 190         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 191         io_mc_regs = (const __le32 *)
 192                 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 193         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 194         fw_data = (const __le32 *)
 195                 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 196
 197         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 198
 199         if (running == 0) {
 200                 /* reset the engine and set to writable */
 201                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 202                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 203
 204                 /* load mc io regs */
 205                 for (i = 0; i < regs_size; i++) {
 206                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 207                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 208                 }
 209                 /* load the MC ucode */
 210                 for (i = 0; i < ucode_size; i++)
 211                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 212
 213                 /* put the engine back into the active state */
 214                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 215                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 216                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 217
 218                 /* wait for training to complete */
 219                 for (i = 0; i < adev->usec_timeout; i++) {
 220                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 221                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 222                                 break;
 223                         udelay(1);
 224                 }
 225                 for (i = 0; i < adev->usec_timeout; i++) {
 226                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 227                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 228                                 break;
 229                         udelay(1);
 230                 }
 231         }
 232
 233         return 0;
 234 }
 235
 236 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
 237                                        struct amdgpu_gmc *mc)
 238 {
 239         u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 240         base <<= 24;
 241
 242         amdgpu_gmc_vram_location(adev, mc, base);
 243         amdgpu_gmc_gart_location(adev, mc);
 244 }
 245
 246 /**
 247  * gmc_v7_0_mc_program - program the GPU memory controller
 248  *
 249  * @adev: amdgpu_device pointer
 250  *
 251  * Set the location of vram, gart, and AGP in the GPU's
 252  * physical address space (CIK).
 253  */
 254 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
 255 {
 256         u32 tmp;
 257         int i, j;
 258
 259         /* Initialize HDP */
 260         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 261                 WREG32((0xb05 + j), 0x00000000);
 262                 WREG32((0xb06 + j), 0x00000000);
 263                 WREG32((0xb07 + j), 0x00000000);
 264                 WREG32((0xb08 + j), 0x00000000);
 265                 WREG32((0xb09 + j), 0x00000000);
 266         }
 267         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 268
 269         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 270                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 271         }
 272         if (adev->mode_info.num_crtc) {
 273                 /* Lockout access through VGA aperture*/
 274                 tmp = RREG32(mmVGA_HDP_CONTROL);
 275                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 276                 WREG32(mmVGA_HDP_CONTROL, tmp);
 277
 278                 /* disable VGA render */
 279                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 280                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 281                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 282         }
 283         /* Update configuration */
 284         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 285                adev->gmc.vram_start >> 12);
 286         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 287                adev->gmc.vram_end >> 12);
 288         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 289                adev->mem_scratch.gpu_addr >> 12);
 290         WREG32(mmMC_VM_AGP_BASE, 0);
 291         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 292         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 293         if (gmc_v7_0_wait_for_idle((void *)adev)) {
 294                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 295         }
 296
 297         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 298
 299         tmp = RREG32(mmHDP_MISC_CNTL);
 300         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 301         WREG32(mmHDP_MISC_CNTL, tmp);
 302
 303         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 304         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 305 }
 306
 307 /**
 308  * gmc_v7_0_mc_init - initialize the memory controller driver params
 309  *
 310  * @adev: amdgpu_device pointer
 311  *
 312  * Look up the amount of vram, vram width, and decide how to place
 313  * vram and gart within the GPU's physical address space (CIK).
 314  * Returns 0 for success.
 315  */
 316 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
 317 {
 318         int r;
 319
 320         adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
 321         if (!adev->gmc.vram_width) {
 322                 u32 tmp;
 323                 int chansize, numchan;
 324
 325                 /* Get VRAM informations */
 326                 tmp = RREG32(mmMC_ARB_RAMCFG);
 327                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 328                         chansize = 64;
 329                 } else {
 330                         chansize = 32;
 331                 }
 332                 tmp = RREG32(mmMC_SHARED_CHMAP);
 333                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 334                 case 0:
 335                 default:
 336                         numchan = 1;
 337                         break;
 338                 case 1:
 339                         numchan = 2;
 340                         break;
 341                 case 2:
 342                         numchan = 4;
 343                         break;
 344                 case 3:
 345                         numchan = 8;
 346                         break;
 347                 case 4:
 348                         numchan = 3;
 349                         break;
 350                 case 5:
 351                         numchan = 6;
 352                         break;
 353                 case 6:
 354                         numchan = 10;
 355                         break;
 356                 case 7:
 357                         numchan = 12;
 358                         break;
 359                 case 8:
 360                         numchan = 16;
 361                         break;
 362                 }
 363                 adev->gmc.vram_width = numchan * chansize;
 364         }
 365         /* size in MB on si */
 366         adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 367         adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 368
 369         if (!(adev->flags & AMD_IS_APU)) {
 370                 r = amdgpu_device_resize_fb_bar(adev);
 371                 if (r)
 372                         return r;
 373         }
 374         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
 375         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 376
 377 #ifdef CONFIG_X86_64
 378         if ((adev->flags & AMD_IS_APU) &&
 379             adev->gmc.real_vram_size > adev->gmc.aper_size &&
 380             !amdgpu_passthrough(adev)) {
 381                 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 382                 adev->gmc.aper_size = adev->gmc.real_vram_size;
 383         }
 384 #endif
 385
 386         adev->gmc.visible_vram_size = adev->gmc.aper_size;
 387
 388         /* set the gart size */
 389         if (amdgpu_gart_size == -1) {
 390                 switch (adev->asic_type) {
 391                 case CHIP_TOPAZ:     /* no MM engines */
 392                 default:
 393                         adev->gmc.gart_size = 256ULL << 20;
 394                         break;
 395 #ifdef CONFIG_DRM_AMDGPU_CIK
 396                 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
 397                 case CHIP_HAWAII:  /* UVD, VCE do not support GPUVM */
 398                 case CHIP_KAVERI:  /* UVD, VCE do not support GPUVM */
 399                 case CHIP_KABINI:  /* UVD, VCE do not support GPUVM */
 400                 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
 401                         adev->gmc.gart_size = 1024ULL << 20;
 402                         break;
 403 #endif
 404                 }
 405         } else {
 406                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
 407         }
 408
 409         adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
 410         gmc_v7_0_vram_gtt_location(adev, &adev->gmc);
 411
 412         return 0;
 413 }
 414
 415 /**
 416  * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid
 417  *
 418  * @adev: amdgpu_device pointer
 419  * @pasid: pasid to be flush
 420  * @flush_type: type of flush
 421  * @all_hub: flush all hubs
 422  * @inst: is used to select which instance of KIQ to use for the invalidation
 423  *
 424  * Flush the TLB for the requested pasid.
 425  */
 426 static int gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 427                                         uint16_t pasid, uint32_t flush_type,
 428                                         bool all_hub, uint32_t inst)
 429 {
 430         int vmid;
 431         unsigned int tmp;
 432
 433         if (amdgpu_in_reset(adev))
 434                 return -EIO;
 435
 436         for (vmid = 1; vmid < 16; vmid++) {
 437
 438                 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
 439                 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
 440                         (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
 441                         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 442                         RREG32(mmVM_INVALIDATE_RESPONSE);
 443                         break;
 444                 }
 445         }
 446
 447         return 0;
 448 }
 449
 450 /*
 451  * GART
 452  * VMID 0 is the physical GPU addresses as used by the kernel.
 453  * VMIDs 1-15 are used for userspace clients and are handled
 454  * by the amdgpu vm/hsa code.
 455  */
 456
 457 /**
 458  * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback
 459  *
 460  * @adev: amdgpu_device pointer
 461  * @vmid: vm instance to flush
 462  * @vmhub: which hub to flush
 463  * @flush_type: type of flush
 464  * *
 465  * Flush the TLB for the requested page table (CIK).
 466  */
 467 static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 468                                         uint32_t vmhub, uint32_t flush_type)
 469 {
 470         /* bits 0-15 are the VM contexts0-15 */
 471         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 472 }
 473
 474 static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 475                                             unsigned vmid, uint64_t pd_addr)
 476 {
 477         uint32_t reg;
 478
 479         if (vmid < 8)
 480                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
 481         else
 482                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
 483         amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
 484
 485         /* bits 0-15 are the VM contexts0-15 */
 486         amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
 487
 488         return pd_addr;
 489 }
 490
 491 static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 492                                         unsigned pasid)
 493 {
 494         amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
 495 }
 496
 497 static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level,
 498                                 uint64_t *addr, uint64_t *flags)
 499 {
 500         BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
 501 }
 502
 503 static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev,
 504                                 struct amdgpu_bo_va_mapping *mapping,
 505                                 uint64_t *flags)
 506 {
 507         *flags &= ~AMDGPU_PTE_EXECUTABLE;
 508         *flags &= ~AMDGPU_PTE_PRT;
 509 }
 510
 511 /**
 512  * gmc_v7_0_set_fault_enable_default - update VM fault handling
 513  *
 514  * @adev: amdgpu_device pointer
 515  * @value: true redirects VM faults to the default page
 516  */
 517 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
 518                                               bool value)
 519 {
 520         u32 tmp;
 521
 522         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 523         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 524                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 525         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 526                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 527         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 528                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 529         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 530                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 531         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 532                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 533         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 534                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 535         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 536 }
 537
 538 /**
 539  * gmc_v7_0_set_prt - set PRT VM fault
 540  *
 541  * @adev: amdgpu_device pointer
 542  * @enable: enable/disable VM fault handling for PRT
 543  */
 544 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
 545 {
 546         uint32_t tmp;
 547
 548         if (enable && !adev->gmc.prt_warning) {
 549                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 550                 adev->gmc.prt_warning = true;
 551         }
 552
 553         tmp = RREG32(mmVM_PRT_CNTL);
 554         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 555                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 556         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 557                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 558         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 559                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 560         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 561                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 562         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 563                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 564         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 565                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 566         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 567                             MASK_PDE0_FAULT, enable);
 568         WREG32(mmVM_PRT_CNTL, tmp);
 569
 570         if (enable) {
 571                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 572                 uint32_t high = adev->vm_manager.max_pfn -
 573                         (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
 574
 575                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 576                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 577                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 578                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 579                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 580                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 581                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 582                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 583         } else {
 584                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 585                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 586                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 587                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 588                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 589                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 590                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 591                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 592         }
 593 }
 594
 595 /**
 596  * gmc_v7_0_gart_enable - gart enable
 597  *
 598  * @adev: amdgpu_device pointer
 599  *
 600  * This sets up the TLBs, programs the page tables for VMID0,
 601  * sets up the hw for VMIDs 1-15 which are allocated on
 602  * demand, and sets up the global locations for the LDS, GDS,
 603  * and GPUVM for FSA64 clients (CIK).
 604  * Returns 0 for success, errors for failure.
 605  */
 606 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 607 {
 608         uint64_t table_addr;
 609         u32 tmp, field;
 610         int i;
 611
 612         if (adev->gart.bo == NULL) {
 613                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 614                 return -EINVAL;
 615         }
 616         amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
 617         table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 618
 619         /* Setup TLB control */
 620         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 621         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 622         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 623         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 624         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 625         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 626         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 627         /* Setup L2 cache */
 628         tmp = RREG32(mmVM_L2_CNTL);
 629         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 630         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 631         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 632         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 633         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 634         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 635         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 636         WREG32(mmVM_L2_CNTL, tmp);
 637         tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 638         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 639         WREG32(mmVM_L2_CNTL2, tmp);
 640
 641         field = adev->vm_manager.fragment_size;
 642         tmp = RREG32(mmVM_L2_CNTL3);
 643         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 644         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
 645         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
 646         WREG32(mmVM_L2_CNTL3, tmp);
 647         /* setup context0 */
 648         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
 649         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
 650         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
 651         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 652                         (u32)(adev->dummy_page_addr >> 12));
 653         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 654         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 655         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 656         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 657         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 658         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 659
 660         WREG32(0x575, 0);
 661         WREG32(0x576, 0);
 662         WREG32(0x577, 0);
 663
 664         /* empty context1-15 */
 665         /* FIXME start with 4G, once using 2 level pt switch to full
 666          * vm size space
 667          */
 668         /* set vm size, must be a multiple of 4 */
 669         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 670         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 671         for (i = 1; i < AMDGPU_NUM_VMID; i++) {
 672                 if (i < 8)
 673                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 674                                table_addr >> 12);
 675                 else
 676                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 677                                table_addr >> 12);
 678         }
 679
 680         /* enable context1-15 */
 681         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 682                (u32)(adev->dummy_page_addr >> 12));
 683         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 684         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 685         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 686         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 687         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 688                             adev->vm_manager.block_size - 9);
 689         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 690         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 691                 gmc_v7_0_set_fault_enable_default(adev, false);
 692         else
 693                 gmc_v7_0_set_fault_enable_default(adev, true);
 694
 695         if (adev->asic_type == CHIP_KAVERI) {
 696                 tmp = RREG32(mmCHUB_CONTROL);
 697                 tmp &= ~BYPASS_VM;
 698                 WREG32(mmCHUB_CONTROL, tmp);
 699         }
 700
 701         gmc_v7_0_flush_gpu_tlb(adev, 0, 0, 0);
 702         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 703                  (unsigned)(adev->gmc.gart_size >> 20),
 704                  (unsigned long long)table_addr);
 705         return 0;
 706 }
 707
 708 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
 709 {
 710         int r;
 711
 712         if (adev->gart.bo) {
 713                 WARN(1, "R600 PCIE GART already initialized\n");
 714                 return 0;
 715         }
 716         /* Initialize common gart structure */
 717         r = amdgpu_gart_init(adev);
 718         if (r)
 719                 return r;
 720         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 721         adev->gart.gart_pte_flags = 0;
 722         return amdgpu_gart_table_vram_alloc(adev);
 723 }
 724
 725 /**
 726  * gmc_v7_0_gart_disable - gart disable
 727  *
 728  * @adev: amdgpu_device pointer
 729  *
 730  * This disables all VM page table (CIK).
 731  */
 732 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
 733 {
 734         u32 tmp;
 735
 736         /* Disable all tables */
 737         WREG32(mmVM_CONTEXT0_CNTL, 0);
 738         WREG32(mmVM_CONTEXT1_CNTL, 0);
 739         /* Setup TLB control */
 740         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 741         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 742         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 743         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 744         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 745         /* Setup L2 cache */
 746         tmp = RREG32(mmVM_L2_CNTL);
 747         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 748         WREG32(mmVM_L2_CNTL, tmp);
 749         WREG32(mmVM_L2_CNTL2, 0);
 750 }
 751
 752 /**
 753  * gmc_v7_0_vm_decode_fault - print human readable fault info
 754  *
 755  * @adev: amdgpu_device pointer
 756  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 757  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 758  * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value
 759  * @pasid: debug logging only - no functional use
 760  *
 761  * Print human readable fault information (CIK).
 762  */
 763 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
 764                                      u32 addr, u32 mc_client, unsigned pasid)
 765 {
 766         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 767         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 768                                         PROTECTIONS);
 769         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 770                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 771         u32 mc_id;
 772
 773         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 774                               MEMORY_CLIENT_ID);
 775
 776         dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 777                protections, vmid, pasid, addr,
 778                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 779                              MEMORY_CLIENT_RW) ?
 780                "write" : "read", block, mc_client, mc_id);
 781 }
 782
 783
 784 static const u32 mc_cg_registers[] = {
 785         mmMC_HUB_MISC_HUB_CG,
 786         mmMC_HUB_MISC_SIP_CG,
 787         mmMC_HUB_MISC_VM_CG,
 788         mmMC_XPB_CLK_GAT,
 789         mmATC_MISC_CG,
 790         mmMC_CITF_MISC_WR_CG,
 791         mmMC_CITF_MISC_RD_CG,
 792         mmMC_CITF_MISC_VM_CG,
 793         mmVM_L2_CG,
 794 };
 795
 796 static const u32 mc_cg_ls_en[] = {
 797         MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
 798         MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
 799         MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 800         MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
 801         ATC_MISC_CG__MEM_LS_ENABLE_MASK,
 802         MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
 803         MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
 804         MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
 805         VM_L2_CG__MEM_LS_ENABLE_MASK,
 806 };
 807
 808 static const u32 mc_cg_en[] = {
 809         MC_HUB_MISC_HUB_CG__ENABLE_MASK,
 810         MC_HUB_MISC_SIP_CG__ENABLE_MASK,
 811         MC_HUB_MISC_VM_CG__ENABLE_MASK,
 812         MC_XPB_CLK_GAT__ENABLE_MASK,
 813         ATC_MISC_CG__ENABLE_MASK,
 814         MC_CITF_MISC_WR_CG__ENABLE_MASK,
 815         MC_CITF_MISC_RD_CG__ENABLE_MASK,
 816         MC_CITF_MISC_VM_CG__ENABLE_MASK,
 817         VM_L2_CG__ENABLE_MASK,
 818 };
 819
 820 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
 821                                   bool enable)
 822 {
 823         int i;
 824         u32 orig, data;
 825
 826         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 827                 orig = data = RREG32(mc_cg_registers[i]);
 828                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 829                         data |= mc_cg_ls_en[i];
 830                 else
 831                         data &= ~mc_cg_ls_en[i];
 832                 if (data != orig)
 833                         WREG32(mc_cg_registers[i], data);
 834         }
 835 }
 836
 837 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
 838                                     bool enable)
 839 {
 840         int i;
 841         u32 orig, data;
 842
 843         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
 844                 orig = data = RREG32(mc_cg_registers[i]);
 845                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 846                         data |= mc_cg_en[i];
 847                 else
 848                         data &= ~mc_cg_en[i];
 849                 if (data != orig)
 850                         WREG32(mc_cg_registers[i], data);
 851         }
 852 }
 853
 854 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
 855                                      bool enable)
 856 {
 857         u32 orig, data;
 858
 859         orig = data = RREG32_PCIE(ixPCIE_CNTL2);
 860
 861         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 862                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
 863                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
 864                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
 865                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
 866         } else {
 867                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
 868                 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
 869                 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
 870                 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
 871         }
 872
 873         if (orig != data)
 874                 WREG32_PCIE(ixPCIE_CNTL2, data);
 875 }
 876
 877 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
 878                                      bool enable)
 879 {
 880         u32 orig, data;
 881
 882         orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
 883
 884         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
 885                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
 886         else
 887                 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
 888
 889         if (orig != data)
 890                 WREG32(mmHDP_HOST_PATH_CNTL, data);
 891 }
 892
 893 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
 894                                    bool enable)
 895 {
 896         u32 orig, data;
 897
 898         orig = data = RREG32(mmHDP_MEM_POWER_LS);
 899
 900         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 901                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
 902         else
 903                 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
 904
 905         if (orig != data)
 906                 WREG32(mmHDP_MEM_POWER_LS, data);
 907 }
 908
 909 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
 910 {
 911         switch (mc_seq_vram_type) {
 912         case MC_SEQ_MISC0__MT__GDDR1:
 913                 return AMDGPU_VRAM_TYPE_GDDR1;
 914         case MC_SEQ_MISC0__MT__DDR2:
 915                 return AMDGPU_VRAM_TYPE_DDR2;
 916         case MC_SEQ_MISC0__MT__GDDR3:
 917                 return AMDGPU_VRAM_TYPE_GDDR3;
 918         case MC_SEQ_MISC0__MT__GDDR4:
 919                 return AMDGPU_VRAM_TYPE_GDDR4;
 920         case MC_SEQ_MISC0__MT__GDDR5:
 921                 return AMDGPU_VRAM_TYPE_GDDR5;
 922         case MC_SEQ_MISC0__MT__HBM:
 923                 return AMDGPU_VRAM_TYPE_HBM;
 924         case MC_SEQ_MISC0__MT__DDR3:
 925                 return AMDGPU_VRAM_TYPE_DDR3;
 926         default:
 927                 return AMDGPU_VRAM_TYPE_UNKNOWN;
 928         }
 929 }
 930
 931 static int gmc_v7_0_early_init(void *handle)
 932 {
 933         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 934
 935         gmc_v7_0_set_gmc_funcs(adev);
 936         gmc_v7_0_set_irq_funcs(adev);
 937
 938         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 939         adev->gmc.shared_aperture_end =
 940                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 941         adev->gmc.private_aperture_start =
 942                 adev->gmc.shared_aperture_end + 1;
 943         adev->gmc.private_aperture_end =
 944                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 945
 946         return 0;
 947 }
 948
 949 static int gmc_v7_0_late_init(void *handle)
 950 {
 951         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 952
 953         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
 954                 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 955         else
 956                 return 0;
 957 }
 958
 959 static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev)
 960 {
 961         u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
 962         unsigned size;
 963
 964         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
 965                 size = AMDGPU_VBIOS_VGA_ALLOCATION;
 966         } else {
 967                 u32 viewport = RREG32(mmVIEWPORT_SIZE);
 968                 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
 969                         REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
 970                         4);
 971         }
 972
 973         return size;
 974 }
 975
 976 static int gmc_v7_0_sw_init(void *handle)
 977 {
 978         int r;
 979         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 980
 981         set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
 982
 983         if (adev->flags & AMD_IS_APU) {
 984                 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 985         } else {
 986                 u32 tmp = RREG32(mmMC_SEQ_MISC0);
 987                 tmp &= MC_SEQ_MISC0__MT__MASK;
 988                 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);
 989         }
 990
 991         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
 992         if (r)
 993                 return r;
 994
 995         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
 996         if (r)
 997                 return r;
 998
 999         /* Adjust VM size here.
1000          * Currently set to 4GB ((1 << 20) 4k pages).
1001          * Max GPUVM size for cayman and SI is 40 bits.
1002          */
1003         amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1004
1005         /* Set the internal MC address mask
1006          * This is the max address of the GPU's
1007          * internal address space.
1008          */
1009         adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1010
1011         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
1012         if (r) {
1013                 pr_warn("No suitable DMA available\n");
1014                 return r;
1015         }
1016         adev->need_swiotlb = drm_need_swiotlb(40);
1017
1018         r = gmc_v7_0_init_microcode(adev);
1019         if (r) {
1020                 DRM_ERROR("Failed to load mc firmware!\n");
1021                 return r;
1022         }
1023
1024         r = gmc_v7_0_mc_init(adev);
1025         if (r)
1026                 return r;
1027
1028         amdgpu_gmc_get_vbios_allocations(adev);
1029
1030         /* Memory manager */
1031         r = amdgpu_bo_init(adev);
1032         if (r)
1033                 return r;
1034
1035         r = gmc_v7_0_gart_init(adev);
1036         if (r)
1037                 return r;
1038
1039         /*
1040          * number of VMs
1041          * VMID 0 is reserved for System
1042          * amdgpu graphics/compute will use VMIDs 1-7
1043          * amdkfd will use VMIDs 8-15
1044          */
1045         adev->vm_manager.first_kfd_vmid = 8;
1046         amdgpu_vm_manager_init(adev);
1047
1048         /* base offset of vram pages */
1049         if (adev->flags & AMD_IS_APU) {
1050                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1051
1052                 tmp <<= 22;
1053                 adev->vm_manager.vram_base_offset = tmp;
1054         } else {
1055                 adev->vm_manager.vram_base_offset = 0;
1056         }
1057
1058         adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1059                                         GFP_KERNEL);
1060         if (!adev->gmc.vm_fault_info)
1061                 return -ENOMEM;
1062         atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1063
1064         return 0;
1065 }
1066
1067 static int gmc_v7_0_sw_fini(void *handle)
1068 {
1069         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1070
1071         amdgpu_gem_force_release(adev);
1072         amdgpu_vm_manager_fini(adev);
1073         kfree(adev->gmc.vm_fault_info);
1074         amdgpu_gart_table_vram_free(adev);
1075         amdgpu_bo_fini(adev);
1076         amdgpu_ucode_release(&adev->gmc.fw);
1077
1078         return 0;
1079 }
1080
1081 static int gmc_v7_0_hw_init(void *handle)
1082 {
1083         int r;
1084         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1085
1086         gmc_v7_0_init_golden_registers(adev);
1087
1088         gmc_v7_0_mc_program(adev);
1089
1090         if (!(adev->flags & AMD_IS_APU)) {
1091                 r = gmc_v7_0_mc_load_microcode(adev);
1092                 if (r) {
1093                         DRM_ERROR("Failed to load MC firmware!\n");
1094                         return r;
1095                 }
1096         }
1097
1098         r = gmc_v7_0_gart_enable(adev);
1099         if (r)
1100                 return r;
1101
1102         if (amdgpu_emu_mode == 1)
1103                 return amdgpu_gmc_vram_checking(adev);
1104         else
1105                 return r;
1106 }
1107
1108 static int gmc_v7_0_hw_fini(void *handle)
1109 {
1110         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1111
1112         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1113         gmc_v7_0_gart_disable(adev);
1114
1115         return 0;
1116 }
1117
1118 static int gmc_v7_0_suspend(void *handle)
1119 {
1120         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1121
1122         gmc_v7_0_hw_fini(adev);
1123
1124         return 0;
1125 }
1126
1127 static int gmc_v7_0_resume(void *handle)
1128 {
1129         int r;
1130         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1131
1132         r = gmc_v7_0_hw_init(adev);
1133         if (r)
1134                 return r;
1135
1136         amdgpu_vmid_reset_all(adev);
1137
1138         return 0;
1139 }
1140
1141 static bool gmc_v7_0_is_idle(void *handle)
1142 {
1143         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1144         u32 tmp = RREG32(mmSRBM_STATUS);
1145
1146         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1147                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1148                 return false;
1149
1150         return true;
1151 }
1152
1153 static int gmc_v7_0_wait_for_idle(void *handle)
1154 {
1155         unsigned i;
1156         u32 tmp;
1157         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1158
1159         for (i = 0; i < adev->usec_timeout; i++) {
1160                 /* read MC_STATUS */
1161                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1162                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1163                                                SRBM_STATUS__MCC_BUSY_MASK |
1164                                                SRBM_STATUS__MCD_BUSY_MASK |
1165                                                SRBM_STATUS__VMC_BUSY_MASK);
1166                 if (!tmp)
1167                         return 0;
1168                 udelay(1);
1169         }
1170         return -ETIMEDOUT;
1171
1172 }
1173
1174 static int gmc_v7_0_soft_reset(void *handle)
1175 {
1176         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1177         u32 srbm_soft_reset = 0;
1178         u32 tmp = RREG32(mmSRBM_STATUS);
1179
1180         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1181                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1182                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1183
1184         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1185                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1186                 if (!(adev->flags & AMD_IS_APU))
1187                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1188                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1189         }
1190
1191         if (srbm_soft_reset) {
1192                 gmc_v7_0_mc_stop(adev);
1193                 if (gmc_v7_0_wait_for_idle((void *)adev)) {
1194                         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1195                 }
1196
1197
1198                 tmp = RREG32(mmSRBM_SOFT_RESET);
1199                 tmp |= srbm_soft_reset;
1200                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1201                 WREG32(mmSRBM_SOFT_RESET, tmp);
1202                 tmp = RREG32(mmSRBM_SOFT_RESET);
1203
1204                 udelay(50);
1205
1206                 tmp &= ~srbm_soft_reset;
1207                 WREG32(mmSRBM_SOFT_RESET, tmp);
1208                 tmp = RREG32(mmSRBM_SOFT_RESET);
1209
1210                 /* Wait a little for things to settle down */
1211                 udelay(50);
1212
1213                 gmc_v7_0_mc_resume(adev);
1214                 udelay(50);
1215         }
1216
1217         return 0;
1218 }
1219
1220 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1221                                              struct amdgpu_irq_src *src,
1222                                              unsigned type,
1223                                              enum amdgpu_interrupt_state state)
1224 {
1225         u32 tmp;
1226         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1227                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1228                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1229                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1230                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1231                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1232
1233         switch (state) {
1234         case AMDGPU_IRQ_STATE_DISABLE:
1235                 /* system context */
1236                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1237                 tmp &= ~bits;
1238                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1239                 /* VMs */
1240                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1241                 tmp &= ~bits;
1242                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1243                 break;
1244         case AMDGPU_IRQ_STATE_ENABLE:
1245                 /* system context */
1246                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1247                 tmp |= bits;
1248                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1249                 /* VMs */
1250                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1251                 tmp |= bits;
1252                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1253                 break;
1254         default:
1255                 break;
1256         }
1257
1258         return 0;
1259 }
1260
1261 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1262                                       struct amdgpu_irq_src *source,
1263                                       struct amdgpu_iv_entry *entry)
1264 {
1265         u32 addr, status, mc_client, vmid;
1266
1267         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1268         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1269         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1270         /* reset addr and status */
1271         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1272
1273         if (!addr && !status)
1274                 return 0;
1275
1276         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1277                 gmc_v7_0_set_fault_enable_default(adev, false);
1278
1279         if (printk_ratelimit()) {
1280                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1281                         entry->src_id, entry->src_data[0]);
1282                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1283                         addr);
1284                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1285                         status);
1286                 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client,
1287                                          entry->pasid);
1288         }
1289
1290         vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1291                              VMID);
1292         if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1293                 && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1294                 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1295                 u32 protections = REG_GET_FIELD(status,
1296                                         VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1297                                         PROTECTIONS);
1298
1299                 info->vmid = vmid;
1300                 info->mc_id = REG_GET_FIELD(status,
1301                                             VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1302                                             MEMORY_CLIENT_ID);
1303                 info->status = status;
1304                 info->page_addr = addr;
1305                 info->prot_valid = protections & 0x7 ? true : false;
1306                 info->prot_read = protections & 0x8 ? true : false;
1307                 info->prot_write = protections & 0x10 ? true : false;
1308                 info->prot_exec = protections & 0x20 ? true : false;
1309                 mb();
1310                 atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1311         }
1312
1313         return 0;
1314 }
1315
1316 static int gmc_v7_0_set_clockgating_state(void *handle,
1317                                           enum amd_clockgating_state state)
1318 {
1319         bool gate = false;
1320         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1321
1322         if (state == AMD_CG_STATE_GATE)
1323                 gate = true;
1324
1325         if (!(adev->flags & AMD_IS_APU)) {
1326                 gmc_v7_0_enable_mc_mgcg(adev, gate);
1327                 gmc_v7_0_enable_mc_ls(adev, gate);
1328         }
1329         gmc_v7_0_enable_bif_mgls(adev, gate);
1330         gmc_v7_0_enable_hdp_mgcg(adev, gate);
1331         gmc_v7_0_enable_hdp_ls(adev, gate);
1332
1333         return 0;
1334 }
1335
1336 static int gmc_v7_0_set_powergating_state(void *handle,
1337                                           enum amd_powergating_state state)
1338 {
1339         return 0;
1340 }
1341
1342 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1343         .name = "gmc_v7_0",
1344         .early_init = gmc_v7_0_early_init,
1345         .late_init = gmc_v7_0_late_init,
1346         .sw_init = gmc_v7_0_sw_init,
1347         .sw_fini = gmc_v7_0_sw_fini,
1348         .hw_init = gmc_v7_0_hw_init,
1349         .hw_fini = gmc_v7_0_hw_fini,
1350         .suspend = gmc_v7_0_suspend,
1351         .resume = gmc_v7_0_resume,
1352         .is_idle = gmc_v7_0_is_idle,
1353         .wait_for_idle = gmc_v7_0_wait_for_idle,
1354         .soft_reset = gmc_v7_0_soft_reset,
1355         .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1356         .set_powergating_state = gmc_v7_0_set_powergating_state,
1357 };
1358
1359 static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
1360         .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
1361         .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid,
1362         .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
1363         .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,
1364         .set_prt = gmc_v7_0_set_prt,
1365         .get_vm_pde = gmc_v7_0_get_vm_pde,
1366         .get_vm_pte = gmc_v7_0_get_vm_pte,
1367         .get_vbios_fb_size = gmc_v7_0_get_vbios_fb_size,
1368 };
1369
1370 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1371         .set = gmc_v7_0_vm_fault_interrupt_state,
1372         .process = gmc_v7_0_process_interrupt,
1373 };
1374
1375 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev)
1376 {
1377         adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs;
1378 }
1379
1380 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1381 {
1382         adev->gmc.vm_fault.num_types = 1;
1383         adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1384 }
1385
1386 const struct amdgpu_ip_block_version gmc_v7_0_ip_block =
1387 {
1388         .type = AMD_IP_BLOCK_TYPE_GMC,
1389         .major = 7,
1390         .minor = 0,
1391         .rev = 0,
1392         .funcs = &gmc_v7_0_ip_funcs,
1393 };
1394
1395 const struct amdgpu_ip_block_version gmc_v7_4_ip_block =
1396 {
1397         .type = AMD_IP_BLOCK_TYPE_GMC,
1398         .major = 7,
1399         .minor = 4,
1400         .rev = 0,
1401         .funcs = &gmc_v7_0_ip_funcs,
1402 };