drivers/gpu/drm/amd/amdgpu/dce_virtual.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "atom.h"
  28 #include "amdgpu_pll.h"
  29 #include "amdgpu_connectors.h"
  30 #ifdef CONFIG_DRM_AMDGPU_SI
  31 #include "dce_v6_0.h"
  32 #endif
  33 #ifdef CONFIG_DRM_AMDGPU_CIK
  34 #include "dce_v8_0.h"
  35 #endif
  36 #include "dce_v10_0.h"
  37 #include "dce_v11_0.h"
  38 #include "dce_virtual.h"
  39
  40 #define DCE_VIRTUAL_VBLANK_PERIOD 16666666
  41
  42
  43 static void dce_virtual_set_display_funcs(struct amdgpu_device *adev);
  44 static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev);
  45 static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
  46                                               int index);
  47
  48 /**
  49  * dce_virtual_vblank_wait - vblank wait asic callback.
  50  *
  51  * @adev: amdgpu_device pointer
  52  * @crtc: crtc to wait for vblank on
  53  *
  54  * Wait for vblank on the requested crtc (evergreen+).
  55  */
  56 static void dce_virtual_vblank_wait(struct amdgpu_device *adev, int crtc)
  57 {
  58         return;
  59 }
  60
  61 static u32 dce_virtual_vblank_get_counter(struct amdgpu_device *adev, int crtc)
  62 {
  63         return 0;
  64 }
  65
  66 static void dce_virtual_page_flip(struct amdgpu_device *adev,
  67                               int crtc_id, u64 crtc_base, bool async)
  68 {
  69         return;
  70 }
  71
  72 static int dce_virtual_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
  73                                         u32 *vbl, u32 *position)
  74 {
  75         *vbl = 0;
  76         *position = 0;
  77
  78         return -EINVAL;
  79 }
  80
  81 static bool dce_virtual_hpd_sense(struct amdgpu_device *adev,
  82                                enum amdgpu_hpd_id hpd)
  83 {
  84         return true;
  85 }
  86
  87 static void dce_virtual_hpd_set_polarity(struct amdgpu_device *adev,
  88                                       enum amdgpu_hpd_id hpd)
  89 {
  90         return;
  91 }
  92
  93 static u32 dce_virtual_hpd_get_gpio_reg(struct amdgpu_device *adev)
  94 {
  95         return 0;
  96 }
  97
  98 static bool dce_virtual_is_display_hung(struct amdgpu_device *adev)
  99 {
 100         return false;
 101 }
 102
 103 static void dce_virtual_stop_mc_access(struct amdgpu_device *adev,
 104                               struct amdgpu_mode_mc_save *save)
 105 {
 106         switch (adev->asic_type) {
 107 #ifdef CONFIG_DRM_AMDGPU_SI
 108         case CHIP_TAHITI:
 109         case CHIP_PITCAIRN:
 110         case CHIP_VERDE:
 111         case CHIP_OLAND:
 112                 dce_v6_0_disable_dce(adev);
 113                 break;
 114 #endif
 115 #ifdef CONFIG_DRM_AMDGPU_CIK
 116         case CHIP_BONAIRE:
 117         case CHIP_HAWAII:
 118         case CHIP_KAVERI:
 119         case CHIP_KABINI:
 120         case CHIP_MULLINS:
 121                 dce_v8_0_disable_dce(adev);
 122                 break;
 123 #endif
 124         case CHIP_FIJI:
 125         case CHIP_TONGA:
 126                 dce_v10_0_disable_dce(adev);
 127                 break;
 128         case CHIP_CARRIZO:
 129         case CHIP_STONEY:
 130         case CHIP_POLARIS11:
 131         case CHIP_POLARIS10:
 132                 dce_v11_0_disable_dce(adev);
 133                 break;
 134         case CHIP_TOPAZ:
 135 #ifdef CONFIG_DRM_AMDGPU_SI
 136         case CHIP_HAINAN:
 137 #endif
 138                 /* no DCE */
 139                 return;
 140         default:
 141                 DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", adev->asic_type);
 142         }
 143
 144         return;
 145 }
 146 static void dce_virtual_resume_mc_access(struct amdgpu_device *adev,
 147                                 struct amdgpu_mode_mc_save *save)
 148 {
 149         return;
 150 }
 151
 152 static void dce_virtual_set_vga_render_state(struct amdgpu_device *adev,
 153                                     bool render)
 154 {
 155         return;
 156 }
 157
 158 /**
 159  * dce_virtual_bandwidth_update - program display watermarks
 160  *
 161  * @adev: amdgpu_device pointer
 162  *
 163  * Calculate and program the display watermarks and line
 164  * buffer allocation (CIK).
 165  */
 166 static void dce_virtual_bandwidth_update(struct amdgpu_device *adev)
 167 {
 168         return;
 169 }
 170
 171 static int dce_virtual_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
 172                                       u16 *green, u16 *blue, uint32_t size)
 173 {
 174         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 175         int i;
 176
 177         /* userspace palettes are always correct as is */
 178         for (i = 0; i < size; i++) {
 179                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
 180                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
 181                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
 182         }
 183
 184         return 0;
 185 }
 186
 187 static void dce_virtual_crtc_destroy(struct drm_crtc *crtc)
 188 {
 189         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 190
 191         drm_crtc_cleanup(crtc);
 192         kfree(amdgpu_crtc);
 193 }
 194
 195 static const struct drm_crtc_funcs dce_virtual_crtc_funcs = {
 196         .cursor_set2 = NULL,
 197         .cursor_move = NULL,
 198         .gamma_set = dce_virtual_crtc_gamma_set,
 199         .set_config = amdgpu_crtc_set_config,
 200         .destroy = dce_virtual_crtc_destroy,
 201         .page_flip_target = amdgpu_crtc_page_flip_target,
 202 };
 203
 204 static void dce_virtual_crtc_dpms(struct drm_crtc *crtc, int mode)
 205 {
 206         struct drm_device *dev = crtc->dev;
 207         struct amdgpu_device *adev = dev->dev_private;
 208         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 209         unsigned type;
 210
 211         switch (mode) {
 212         case DRM_MODE_DPMS_ON:
 213                 amdgpu_crtc->enabled = true;
 214                 /* Make sure VBLANK interrupts are still enabled */
 215                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
 216                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
 217                 drm_vblank_on(dev, amdgpu_crtc->crtc_id);
 218                 break;
 219         case DRM_MODE_DPMS_STANDBY:
 220         case DRM_MODE_DPMS_SUSPEND:
 221         case DRM_MODE_DPMS_OFF:
 222                 drm_vblank_off(dev, amdgpu_crtc->crtc_id);
 223                 amdgpu_crtc->enabled = false;
 224                 break;
 225         }
 226 }
 227
 228
 229 static void dce_virtual_crtc_prepare(struct drm_crtc *crtc)
 230 {
 231         dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 232 }
 233
 234 static void dce_virtual_crtc_commit(struct drm_crtc *crtc)
 235 {
 236         dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 237 }
 238
 239 static void dce_virtual_crtc_disable(struct drm_crtc *crtc)
 240 {
 241         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 242
 243         dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 244         if (crtc->primary->fb) {
 245                 int r;
 246                 struct amdgpu_framebuffer *amdgpu_fb;
 247                 struct amdgpu_bo *abo;
 248
 249                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
 250                 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
 251                 r = amdgpu_bo_reserve(abo, false);
 252                 if (unlikely(r))
 253                         DRM_ERROR("failed to reserve abo before unpin\n");
 254                 else {
 255                         amdgpu_bo_unpin(abo);
 256                         amdgpu_bo_unreserve(abo);
 257                 }
 258         }
 259
 260         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
 261         amdgpu_crtc->encoder = NULL;
 262         amdgpu_crtc->connector = NULL;
 263 }
 264
 265 static int dce_virtual_crtc_mode_set(struct drm_crtc *crtc,
 266                                   struct drm_display_mode *mode,
 267                                   struct drm_display_mode *adjusted_mode,
 268                                   int x, int y, struct drm_framebuffer *old_fb)
 269 {
 270         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 271
 272         /* update the hw version fpr dpm */
 273         amdgpu_crtc->hw_mode = *adjusted_mode;
 274
 275         return 0;
 276 }
 277
 278 static bool dce_virtual_crtc_mode_fixup(struct drm_crtc *crtc,
 279                                      const struct drm_display_mode *mode,
 280                                      struct drm_display_mode *adjusted_mode)
 281 {
 282         return true;
 283 }
 284
 285
 286 static int dce_virtual_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 287                                   struct drm_framebuffer *old_fb)
 288 {
 289         return 0;
 290 }
 291
 292 static void dce_virtual_crtc_load_lut(struct drm_crtc *crtc)
 293 {
 294         return;
 295 }
 296
 297 static int dce_virtual_crtc_set_base_atomic(struct drm_crtc *crtc,
 298                                          struct drm_framebuffer *fb,
 299                                          int x, int y, enum mode_set_atomic state)
 300 {
 301         return 0;
 302 }
 303
 304 static const struct drm_crtc_helper_funcs dce_virtual_crtc_helper_funcs = {
 305         .dpms = dce_virtual_crtc_dpms,
 306         .mode_fixup = dce_virtual_crtc_mode_fixup,
 307         .mode_set = dce_virtual_crtc_mode_set,
 308         .mode_set_base = dce_virtual_crtc_set_base,
 309         .mode_set_base_atomic = dce_virtual_crtc_set_base_atomic,
 310         .prepare = dce_virtual_crtc_prepare,
 311         .commit = dce_virtual_crtc_commit,
 312         .load_lut = dce_virtual_crtc_load_lut,
 313         .disable = dce_virtual_crtc_disable,
 314 };
 315
 316 static int dce_virtual_crtc_init(struct amdgpu_device *adev, int index)
 317 {
 318         struct amdgpu_crtc *amdgpu_crtc;
 319         int i;
 320
 321         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
 322                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 323         if (amdgpu_crtc == NULL)
 324                 return -ENOMEM;
 325
 326         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_virtual_crtc_funcs);
 327
 328         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
 329         amdgpu_crtc->crtc_id = index;
 330         adev->mode_info.crtcs[index] = amdgpu_crtc;
 331
 332         for (i = 0; i < 256; i++) {
 333                 amdgpu_crtc->lut_r[i] = i << 2;
 334                 amdgpu_crtc->lut_g[i] = i << 2;
 335                 amdgpu_crtc->lut_b[i] = i << 2;
 336         }
 337
 338         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
 339         amdgpu_crtc->encoder = NULL;
 340         amdgpu_crtc->connector = NULL;
 341         amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
 342         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_virtual_crtc_helper_funcs);
 343
 344         return 0;
 345 }
 346
 347 static int dce_virtual_early_init(void *handle)
 348 {
 349         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 350
 351         dce_virtual_set_display_funcs(adev);
 352         dce_virtual_set_irq_funcs(adev);
 353
 354         adev->mode_info.num_hpd = 1;
 355         adev->mode_info.num_dig = 1;
 356         return 0;
 357 }
 358
 359 static struct drm_encoder *
 360 dce_virtual_encoder(struct drm_connector *connector)
 361 {
 362         int enc_id = connector->encoder_ids[0];
 363         struct drm_encoder *encoder;
 364         int i;
 365
 366         for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
 367                 if (connector->encoder_ids[i] == 0)
 368                         break;
 369
 370                 encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
 371                 if (!encoder)
 372                         continue;
 373
 374                 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
 375                         return encoder;
 376         }
 377
 378         /* pick the first one */
 379         if (enc_id)
 380                 return drm_encoder_find(connector->dev, enc_id);
 381         return NULL;
 382 }
 383
 384 static int dce_virtual_get_modes(struct drm_connector *connector)
 385 {
 386         struct drm_device *dev = connector->dev;
 387         struct drm_display_mode *mode = NULL;
 388         unsigned i;
 389         static const struct mode_size {
 390                 int w;
 391                 int h;
 392         } common_modes[17] = {
 393                 { 640,  480},
 394                 { 720,  480},
 395                 { 800,  600},
 396                 { 848,  480},
 397                 {1024,  768},
 398                 {1152,  768},
 399                 {1280,  720},
 400                 {1280,  800},
 401                 {1280,  854},
 402                 {1280,  960},
 403                 {1280, 1024},
 404                 {1440,  900},
 405                 {1400, 1050},
 406                 {1680, 1050},
 407                 {1600, 1200},
 408                 {1920, 1080},
 409                 {1920, 1200}
 410         };
 411
 412         for (i = 0; i < 17; i++) {
 413                 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 414                 drm_mode_probed_add(connector, mode);
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int dce_virtual_mode_valid(struct drm_connector *connector,
 421                                   struct drm_display_mode *mode)
 422 {
 423         return MODE_OK;
 424 }
 425
 426 static int
 427 dce_virtual_dpms(struct drm_connector *connector, int mode)
 428 {
 429         return 0;
 430 }
 431
 432 static enum drm_connector_status
 433 dce_virtual_detect(struct drm_connector *connector, bool force)
 434 {
 435         return connector_status_connected;
 436 }
 437
 438 static int
 439 dce_virtual_set_property(struct drm_connector *connector,
 440                          struct drm_property *property,
 441                          uint64_t val)
 442 {
 443         return 0;
 444 }
 445
 446 static void dce_virtual_destroy(struct drm_connector *connector)
 447 {
 448         drm_connector_unregister(connector);
 449         drm_connector_cleanup(connector);
 450         kfree(connector);
 451 }
 452
 453 static void dce_virtual_force(struct drm_connector *connector)
 454 {
 455         return;
 456 }
 457
 458 static const struct drm_connector_helper_funcs dce_virtual_connector_helper_funcs = {
 459         .get_modes = dce_virtual_get_modes,
 460         .mode_valid = dce_virtual_mode_valid,
 461         .best_encoder = dce_virtual_encoder,
 462 };
 463
 464 static const struct drm_connector_funcs dce_virtual_connector_funcs = {
 465         .dpms = dce_virtual_dpms,
 466         .detect = dce_virtual_detect,
 467         .fill_modes = drm_helper_probe_single_connector_modes,
 468         .set_property = dce_virtual_set_property,
 469         .destroy = dce_virtual_destroy,
 470         .force = dce_virtual_force,
 471 };
 472
 473 static int dce_virtual_sw_init(void *handle)
 474 {
 475         int r, i;
 476         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 477
 478         r = amdgpu_irq_add_id(adev, 229, &adev->crtc_irq);
 479         if (r)
 480                 return r;
 481
 482         adev->ddev->max_vblank_count = 0;
 483
 484         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
 485
 486         adev->ddev->mode_config.max_width = 16384;
 487         adev->ddev->mode_config.max_height = 16384;
 488
 489         adev->ddev->mode_config.preferred_depth = 24;
 490         adev->ddev->mode_config.prefer_shadow = 1;
 491
 492         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
 493
 494         r = amdgpu_modeset_create_props(adev);
 495         if (r)
 496                 return r;
 497
 498         adev->ddev->mode_config.max_width = 16384;
 499         adev->ddev->mode_config.max_height = 16384;
 500
 501         /* allocate crtcs, encoders, connectors */
 502         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 503                 r = dce_virtual_crtc_init(adev, i);
 504                 if (r)
 505                         return r;
 506                 r = dce_virtual_connector_encoder_init(adev, i);
 507                 if (r)
 508                         return r;
 509         }
 510
 511         drm_kms_helper_poll_init(adev->ddev);
 512
 513         adev->mode_info.mode_config_initialized = true;
 514         return 0;
 515 }
 516
 517 static int dce_virtual_sw_fini(void *handle)
 518 {
 519         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 520
 521         kfree(adev->mode_info.bios_hardcoded_edid);
 522
 523         drm_kms_helper_poll_fini(adev->ddev);
 524
 525         drm_mode_config_cleanup(adev->ddev);
 526         adev->mode_info.mode_config_initialized = false;
 527         return 0;
 528 }
 529
 530 static int dce_virtual_hw_init(void *handle)
 531 {
 532         return 0;
 533 }
 534
 535 static int dce_virtual_hw_fini(void *handle)
 536 {
 537         return 0;
 538 }
 539
 540 static int dce_virtual_suspend(void *handle)
 541 {
 542         return dce_virtual_hw_fini(handle);
 543 }
 544
 545 static int dce_virtual_resume(void *handle)
 546 {
 547         return dce_virtual_hw_init(handle);
 548 }
 549
 550 static bool dce_virtual_is_idle(void *handle)
 551 {
 552         return true;
 553 }
 554
 555 static int dce_virtual_wait_for_idle(void *handle)
 556 {
 557         return 0;
 558 }
 559
 560 static int dce_virtual_soft_reset(void *handle)
 561 {
 562         return 0;
 563 }
 564
 565 static int dce_virtual_set_clockgating_state(void *handle,
 566                                           enum amd_clockgating_state state)
 567 {
 568         return 0;
 569 }
 570
 571 static int dce_virtual_set_powergating_state(void *handle,
 572                                           enum amd_powergating_state state)
 573 {
 574         return 0;
 575 }
 576
 577 static const struct amd_ip_funcs dce_virtual_ip_funcs = {
 578         .name = "dce_virtual",
 579         .early_init = dce_virtual_early_init,
 580         .late_init = NULL,
 581         .sw_init = dce_virtual_sw_init,
 582         .sw_fini = dce_virtual_sw_fini,
 583         .hw_init = dce_virtual_hw_init,
 584         .hw_fini = dce_virtual_hw_fini,
 585         .suspend = dce_virtual_suspend,
 586         .resume = dce_virtual_resume,
 587         .is_idle = dce_virtual_is_idle,
 588         .wait_for_idle = dce_virtual_wait_for_idle,
 589         .soft_reset = dce_virtual_soft_reset,
 590         .set_clockgating_state = dce_virtual_set_clockgating_state,
 591         .set_powergating_state = dce_virtual_set_powergating_state,
 592 };
 593
 594 /* these are handled by the primary encoders */
 595 static void dce_virtual_encoder_prepare(struct drm_encoder *encoder)
 596 {
 597         return;
 598 }
 599
 600 static void dce_virtual_encoder_commit(struct drm_encoder *encoder)
 601 {
 602         return;
 603 }
 604
 605 static void
 606 dce_virtual_encoder_mode_set(struct drm_encoder *encoder,
 607                              struct drm_display_mode *mode,
 608                              struct drm_display_mode *adjusted_mode)
 609 {
 610         return;
 611 }
 612
 613 static void dce_virtual_encoder_disable(struct drm_encoder *encoder)
 614 {
 615         return;
 616 }
 617
 618 static void
 619 dce_virtual_encoder_dpms(struct drm_encoder *encoder, int mode)
 620 {
 621         return;
 622 }
 623
 624 static bool dce_virtual_encoder_mode_fixup(struct drm_encoder *encoder,
 625                                     const struct drm_display_mode *mode,
 626                                     struct drm_display_mode *adjusted_mode)
 627 {
 628         return true;
 629 }
 630
 631 static const struct drm_encoder_helper_funcs dce_virtual_encoder_helper_funcs = {
 632         .dpms = dce_virtual_encoder_dpms,
 633         .mode_fixup = dce_virtual_encoder_mode_fixup,
 634         .prepare = dce_virtual_encoder_prepare,
 635         .mode_set = dce_virtual_encoder_mode_set,
 636         .commit = dce_virtual_encoder_commit,
 637         .disable = dce_virtual_encoder_disable,
 638 };
 639
 640 static void dce_virtual_encoder_destroy(struct drm_encoder *encoder)
 641 {
 642         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 643
 644         kfree(amdgpu_encoder->enc_priv);
 645         drm_encoder_cleanup(encoder);
 646         kfree(amdgpu_encoder);
 647 }
 648
 649 static const struct drm_encoder_funcs dce_virtual_encoder_funcs = {
 650         .destroy = dce_virtual_encoder_destroy,
 651 };
 652
 653 static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
 654                                               int index)
 655 {
 656         struct drm_encoder *encoder;
 657         struct drm_connector *connector;
 658
 659         /* add a new encoder */
 660         encoder = kzalloc(sizeof(struct drm_encoder), GFP_KERNEL);
 661         if (!encoder)
 662                 return -ENOMEM;
 663         encoder->possible_crtcs = 1 << index;
 664         drm_encoder_init(adev->ddev, encoder, &dce_virtual_encoder_funcs,
 665                          DRM_MODE_ENCODER_VIRTUAL, NULL);
 666         drm_encoder_helper_add(encoder, &dce_virtual_encoder_helper_funcs);
 667
 668         connector = kzalloc(sizeof(struct drm_connector), GFP_KERNEL);
 669         if (!connector) {
 670                 kfree(encoder);
 671                 return -ENOMEM;
 672         }
 673
 674         /* add a new connector */
 675         drm_connector_init(adev->ddev, connector, &dce_virtual_connector_funcs,
 676                            DRM_MODE_CONNECTOR_VIRTUAL);
 677         drm_connector_helper_add(connector, &dce_virtual_connector_helper_funcs);
 678         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
 679         connector->interlace_allowed = false;
 680         connector->doublescan_allowed = false;
 681         drm_connector_register(connector);
 682
 683         /* link them */
 684         drm_mode_connector_attach_encoder(connector, encoder);
 685
 686         return 0;
 687 }
 688
 689 static const struct amdgpu_display_funcs dce_virtual_display_funcs = {
 690         .set_vga_render_state = &dce_virtual_set_vga_render_state,
 691         .bandwidth_update = &dce_virtual_bandwidth_update,
 692         .vblank_get_counter = &dce_virtual_vblank_get_counter,
 693         .vblank_wait = &dce_virtual_vblank_wait,
 694         .is_display_hung = &dce_virtual_is_display_hung,
 695         .backlight_set_level = NULL,
 696         .backlight_get_level = NULL,
 697         .hpd_sense = &dce_virtual_hpd_sense,
 698         .hpd_set_polarity = &dce_virtual_hpd_set_polarity,
 699         .hpd_get_gpio_reg = &dce_virtual_hpd_get_gpio_reg,
 700         .page_flip = &dce_virtual_page_flip,
 701         .page_flip_get_scanoutpos = &dce_virtual_crtc_get_scanoutpos,
 702         .add_encoder = NULL,
 703         .add_connector = NULL,
 704         .stop_mc_access = &dce_virtual_stop_mc_access,
 705         .resume_mc_access = &dce_virtual_resume_mc_access,
 706 };
 707
 708 static void dce_virtual_set_display_funcs(struct amdgpu_device *adev)
 709 {
 710         if (adev->mode_info.funcs == NULL)
 711                 adev->mode_info.funcs = &dce_virtual_display_funcs;
 712 }
 713
 714 static int dce_virtual_pageflip(struct amdgpu_device *adev,
 715                                 unsigned crtc_id)
 716 {
 717         unsigned long flags;
 718         struct amdgpu_crtc *amdgpu_crtc;
 719         struct amdgpu_flip_work *works;
 720
 721         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 722
 723         if (crtc_id >= adev->mode_info.num_crtc) {
 724                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
 725                 return -EINVAL;
 726         }
 727
 728         /* IRQ could occur when in initial stage */
 729         if (amdgpu_crtc == NULL)
 730                 return 0;
 731
 732         spin_lock_irqsave(&adev->ddev->event_lock, flags);
 733         works = amdgpu_crtc->pflip_works;
 734         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
 735                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
 736                         "AMDGPU_FLIP_SUBMITTED(%d)\n",
 737                         amdgpu_crtc->pflip_status,
 738                         AMDGPU_FLIP_SUBMITTED);
 739                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 740                 return 0;
 741         }
 742
 743         /* page flip completed. clean up */
 744         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 745         amdgpu_crtc->pflip_works = NULL;
 746
 747         /* wakeup usersapce */
 748         if (works->event)
 749                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
 750
 751         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 752
 753         drm_crtc_vblank_put(&amdgpu_crtc->base);
 754         schedule_work(&works->unpin_work);
 755
 756         return 0;
 757 }
 758
 759 static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer *vblank_timer)
 760 {
 761         struct amdgpu_crtc *amdgpu_crtc = container_of(vblank_timer,
 762                                                        struct amdgpu_crtc, vblank_timer);
 763         struct drm_device *ddev = amdgpu_crtc->base.dev;
 764         struct amdgpu_device *adev = ddev->dev_private;
 765
 766         drm_handle_vblank(ddev, amdgpu_crtc->crtc_id);
 767         dce_virtual_pageflip(adev, amdgpu_crtc->crtc_id);
 768         hrtimer_start(vblank_timer, ktime_set(0, DCE_VIRTUAL_VBLANK_PERIOD),
 769                       HRTIMER_MODE_REL);
 770
 771         return HRTIMER_NORESTART;
 772 }
 773
 774 static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
 775                                                         int crtc,
 776                                                         enum amdgpu_interrupt_state state)
 777 {
 778         if (crtc >= adev->mode_info.num_crtc) {
 779                 DRM_DEBUG("invalid crtc %d\n", crtc);
 780                 return;
 781         }
 782
 783         if (state && !adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
 784                 DRM_DEBUG("Enable software vsync timer\n");
 785                 hrtimer_init(&adev->mode_info.crtcs[crtc]->vblank_timer,
 786                              CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 787                 hrtimer_set_expires(&adev->mode_info.crtcs[crtc]->vblank_timer,
 788                                     ktime_set(0, DCE_VIRTUAL_VBLANK_PERIOD));
 789                 adev->mode_info.crtcs[crtc]->vblank_timer.function =
 790                         dce_virtual_vblank_timer_handle;
 791                 hrtimer_start(&adev->mode_info.crtcs[crtc]->vblank_timer,
 792                               ktime_set(0, DCE_VIRTUAL_VBLANK_PERIOD), HRTIMER_MODE_REL);
 793         } else if (!state && adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
 794                 DRM_DEBUG("Disable software vsync timer\n");
 795                 hrtimer_cancel(&adev->mode_info.crtcs[crtc]->vblank_timer);
 796         }
 797
 798         adev->mode_info.crtcs[crtc]->vsync_timer_enabled = state;
 799         DRM_DEBUG("[FM]set crtc %d vblank interrupt state %d\n", crtc, state);
 800 }
 801
 802
 803 static int dce_virtual_set_crtc_irq_state(struct amdgpu_device *adev,
 804                                           struct amdgpu_irq_src *source,
 805                                           unsigned type,
 806                                           enum amdgpu_interrupt_state state)
 807 {
 808         if (type > AMDGPU_CRTC_IRQ_VBLANK6)
 809                 return -EINVAL;
 810
 811         dce_virtual_set_crtc_vblank_interrupt_state(adev, type, state);
 812
 813         return 0;
 814 }
 815
 816 static const struct amdgpu_irq_src_funcs dce_virtual_crtc_irq_funcs = {
 817         .set = dce_virtual_set_crtc_irq_state,
 818         .process = NULL,
 819 };
 820
 821 static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev)
 822 {
 823         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
 824         adev->crtc_irq.funcs = &dce_virtual_crtc_irq_funcs;
 825 }
 826
 827 const struct amdgpu_ip_block_version dce_virtual_ip_block =
 828 {
 829         .type = AMD_IP_BLOCK_TYPE_DCE,
 830         .major = 1,
 831         .minor = 0,
 832         .rev = 0,
 833         .funcs = &dce_virtual_ip_funcs,
 834 };