drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drm_fb_helper.h>
  25 #include <drm/drm_fourcc.h>
  26 #include <drm/drm_vblank.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_pm.h"
  30 #include "amdgpu_i2c.h"
  31 #include "vid.h"
  32 #include "atom.h"
  33 #include "amdgpu_atombios.h"
  34 #include "atombios_crtc.h"
  35 #include "atombios_encoders.h"
  36 #include "amdgpu_pll.h"
  37 #include "amdgpu_connectors.h"
  38 #include "amdgpu_display.h"
  39 #include "dce_v11_0.h"
  40
  41 #include "dce/dce_11_0_d.h"
  42 #include "dce/dce_11_0_sh_mask.h"
  43 #include "dce/dce_11_0_enum.h"
  44 #include "oss/oss_3_0_d.h"
  45 #include "oss/oss_3_0_sh_mask.h"
  46 #include "gmc/gmc_8_1_d.h"
  47 #include "gmc/gmc_8_1_sh_mask.h"
  48
  49 #include "ivsrcid/ivsrcid_vislands30.h"
  50
  51 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
  52 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
  53
  54 static const u32 crtc_offsets[] =
  55 {
  56         CRTC0_REGISTER_OFFSET,
  57         CRTC1_REGISTER_OFFSET,
  58         CRTC2_REGISTER_OFFSET,
  59         CRTC3_REGISTER_OFFSET,
  60         CRTC4_REGISTER_OFFSET,
  61         CRTC5_REGISTER_OFFSET,
  62         CRTC6_REGISTER_OFFSET
  63 };
  64
  65 static const u32 hpd_offsets[] =
  66 {
  67         HPD0_REGISTER_OFFSET,
  68         HPD1_REGISTER_OFFSET,
  69         HPD2_REGISTER_OFFSET,
  70         HPD3_REGISTER_OFFSET,
  71         HPD4_REGISTER_OFFSET,
  72         HPD5_REGISTER_OFFSET
  73 };
  74
  75 static const uint32_t dig_offsets[] = {
  76         DIG0_REGISTER_OFFSET,
  77         DIG1_REGISTER_OFFSET,
  78         DIG2_REGISTER_OFFSET,
  79         DIG3_REGISTER_OFFSET,
  80         DIG4_REGISTER_OFFSET,
  81         DIG5_REGISTER_OFFSET,
  82         DIG6_REGISTER_OFFSET,
  83         DIG7_REGISTER_OFFSET,
  84         DIG8_REGISTER_OFFSET
  85 };
  86
  87 static const struct {
  88         uint32_t        reg;
  89         uint32_t        vblank;
  90         uint32_t        vline;
  91         uint32_t        hpd;
  92
  93 } interrupt_status_offsets[] = { {
  94         .reg = mmDISP_INTERRUPT_STATUS,
  95         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  96         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  97         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  98 }, {
  99         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
 100         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
 101         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
 102         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
 103 }, {
 104         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
 105         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
 106         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
 107         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
 108 }, {
 109         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
 110         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
 111         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
 112         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
 113 }, {
 114         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
 115         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
 116         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
 117         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 118 }, {
 119         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 120         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 121         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 122         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 123 } };
 124
 125 static const u32 cz_golden_settings_a11[] =
 126 {
 127         mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
 128         mmFBC_MISC, 0x1f311fff, 0x14300000,
 129 };
 130
 131 static const u32 cz_mgcg_cgcg_init[] =
 132 {
 133         mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
 134         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 135 };
 136
 137 static const u32 stoney_golden_settings_a11[] =
 138 {
 139         mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
 140         mmFBC_MISC, 0x1f311fff, 0x14302000,
 141 };
 142
 143 static const u32 polaris11_golden_settings_a11[] =
 144 {
 145         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 146         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 147         mmFBC_DEBUG1, 0xffffffff, 0x00000008,
 148         mmFBC_MISC, 0x9f313fff, 0x14302008,
 149         mmHDMI_CONTROL, 0x313f031f, 0x00000011,
 150 };
 151
 152 static const u32 polaris10_golden_settings_a11[] =
 153 {
 154         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 155         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
 156         mmFBC_MISC, 0x9f313fff, 0x14302008,
 157         mmHDMI_CONTROL, 0x313f031f, 0x00000011,
 158 };
 159
 160 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
 161 {
 162         switch (adev->asic_type) {
 163         case CHIP_CARRIZO:
 164                 amdgpu_device_program_register_sequence(adev,
 165                                                         cz_mgcg_cgcg_init,
 166                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 167                 amdgpu_device_program_register_sequence(adev,
 168                                                         cz_golden_settings_a11,
 169                                                         ARRAY_SIZE(cz_golden_settings_a11));
 170                 break;
 171         case CHIP_STONEY:
 172                 amdgpu_device_program_register_sequence(adev,
 173                                                         stoney_golden_settings_a11,
 174                                                         ARRAY_SIZE(stoney_golden_settings_a11));
 175                 break;
 176         case CHIP_POLARIS11:
 177         case CHIP_POLARIS12:
 178                 amdgpu_device_program_register_sequence(adev,
 179                                                         polaris11_golden_settings_a11,
 180                                                         ARRAY_SIZE(polaris11_golden_settings_a11));
 181                 break;
 182         case CHIP_POLARIS10:
 183         case CHIP_VEGAM:
 184                 amdgpu_device_program_register_sequence(adev,
 185                                                         polaris10_golden_settings_a11,
 186                                                         ARRAY_SIZE(polaris10_golden_settings_a11));
 187                 break;
 188         default:
 189                 break;
 190         }
 191 }
 192
 193 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
 194                                      u32 block_offset, u32 reg)
 195 {
 196         unsigned long flags;
 197         u32 r;
 198
 199         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 200         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 201         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 202         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 203
 204         return r;
 205 }
 206
 207 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
 208                                       u32 block_offset, u32 reg, u32 v)
 209 {
 210         unsigned long flags;
 211
 212         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 213         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 214         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 215         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 216 }
 217
 218 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 219 {
 220         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
 221                 return 0;
 222         else
 223                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 224 }
 225
 226 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 227 {
 228         unsigned i;
 229
 230         /* Enable pflip interrupts */
 231         for (i = 0; i < adev->mode_info.num_crtc; i++)
 232                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 233 }
 234
 235 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 236 {
 237         unsigned i;
 238
 239         /* Disable pflip interrupts */
 240         for (i = 0; i < adev->mode_info.num_crtc; i++)
 241                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 242 }
 243
 244 /**
 245  * dce_v11_0_page_flip - pageflip callback.
 246  *
 247  * @adev: amdgpu_device pointer
 248  * @crtc_id: crtc to cleanup pageflip on
 249  * @crtc_base: new address of the crtc (GPU MC address)
 250  * @async: asynchronous flip
 251  *
 252  * Triggers the actual pageflip by updating the primary
 253  * surface base address.
 254  */
 255 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
 256                                 int crtc_id, u64 crtc_base, bool async)
 257 {
 258         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 259         struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
 260         u32 tmp;
 261
 262         /* flip immediate for async, default is vsync */
 263         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
 264         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
 265                             GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
 266         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 267         /* update pitch */
 268         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
 269                fb->pitches[0] / fb->format->cpp[0]);
 270         /* update the scanout addresses */
 271         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 272                upper_32_bits(crtc_base));
 273         /* writing to the low address triggers the update */
 274         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 275                lower_32_bits(crtc_base));
 276         /* post the write */
 277         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 278 }
 279
 280 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 281                                         u32 *vbl, u32 *position)
 282 {
 283         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 284                 return -EINVAL;
 285
 286         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 287         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 288
 289         return 0;
 290 }
 291
 292 /**
 293  * dce_v11_0_hpd_sense - hpd sense callback.
 294  *
 295  * @adev: amdgpu_device pointer
 296  * @hpd: hpd (hotplug detect) pin
 297  *
 298  * Checks if a digital monitor is connected (evergreen+).
 299  * Returns true if connected, false if not connected.
 300  */
 301 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
 302                                enum amdgpu_hpd_id hpd)
 303 {
 304         bool connected = false;
 305
 306         if (hpd >= adev->mode_info.num_hpd)
 307                 return connected;
 308
 309         if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
 310             DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
 311                 connected = true;
 312
 313         return connected;
 314 }
 315
 316 /**
 317  * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
 318  *
 319  * @adev: amdgpu_device pointer
 320  * @hpd: hpd (hotplug detect) pin
 321  *
 322  * Set the polarity of the hpd pin (evergreen+).
 323  */
 324 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
 325                                       enum amdgpu_hpd_id hpd)
 326 {
 327         u32 tmp;
 328         bool connected = dce_v11_0_hpd_sense(adev, hpd);
 329
 330         if (hpd >= adev->mode_info.num_hpd)
 331                 return;
 332
 333         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
 334         if (connected)
 335                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
 336         else
 337                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
 338         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
 339 }
 340
 341 /**
 342  * dce_v11_0_hpd_init - hpd setup callback.
 343  *
 344  * @adev: amdgpu_device pointer
 345  *
 346  * Setup the hpd pins used by the card (evergreen+).
 347  * Enable the pin, set the polarity, and enable the hpd interrupts.
 348  */
 349 static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
 350 {
 351         struct drm_device *dev = adev_to_drm(adev);
 352         struct drm_connector *connector;
 353         struct drm_connector_list_iter iter;
 354         u32 tmp;
 355
 356         drm_connector_list_iter_begin(dev, &iter);
 357         drm_for_each_connector_iter(connector, &iter) {
 358                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 359
 360                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 361                         continue;
 362
 363                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 364                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 365                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 366                          * aux dp channel on imac and help (but not completely fix)
 367                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 368                          * also avoid interrupt storms during dpms.
 369                          */
 370                         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 371                         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
 372                         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 373                         continue;
 374                 }
 375
 376                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 377                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
 378                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 379
 380                 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 381                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 382                                     DC_HPD_CONNECT_INT_DELAY,
 383                                     AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
 384                 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
 385                                     DC_HPD_DISCONNECT_INT_DELAY,
 386                                     AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
 387                 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 388
 389                 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 390                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 391         }
 392         drm_connector_list_iter_end(&iter);
 393 }
 394
 395 /**
 396  * dce_v11_0_hpd_fini - hpd tear down callback.
 397  *
 398  * @adev: amdgpu_device pointer
 399  *
 400  * Tear down the hpd pins used by the card (evergreen+).
 401  * Disable the hpd interrupts.
 402  */
 403 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
 404 {
 405         struct drm_device *dev = adev_to_drm(adev);
 406         struct drm_connector *connector;
 407         struct drm_connector_list_iter iter;
 408         u32 tmp;
 409
 410         drm_connector_list_iter_begin(dev, &iter);
 411         drm_for_each_connector_iter(connector, &iter) {
 412                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 413
 414                 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
 415                         continue;
 416
 417                 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 418                 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
 419                 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 420
 421                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 422         }
 423         drm_connector_list_iter_end(&iter);
 424 }
 425
 426 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 427 {
 428         return mmDC_GPIO_HPD_A;
 429 }
 430
 431 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
 432 {
 433         u32 crtc_hung = 0;
 434         u32 crtc_status[6];
 435         u32 i, j, tmp;
 436
 437         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 438                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 439                 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
 440                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 441                         crtc_hung |= (1 << i);
 442                 }
 443         }
 444
 445         for (j = 0; j < 10; j++) {
 446                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 447                         if (crtc_hung & (1 << i)) {
 448                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 449                                 if (tmp != crtc_status[i])
 450                                         crtc_hung &= ~(1 << i);
 451                         }
 452                 }
 453                 if (crtc_hung == 0)
 454                         return false;
 455                 udelay(100);
 456         }
 457
 458         return true;
 459 }
 460
 461 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
 462                                            bool render)
 463 {
 464         u32 tmp;
 465
 466         /* Lockout access through VGA aperture*/
 467         tmp = RREG32(mmVGA_HDP_CONTROL);
 468         if (render)
 469                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 470         else
 471                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 472         WREG32(mmVGA_HDP_CONTROL, tmp);
 473
 474         /* disable VGA render */
 475         tmp = RREG32(mmVGA_RENDER_CONTROL);
 476         if (render)
 477                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 478         else
 479                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 480         WREG32(mmVGA_RENDER_CONTROL, tmp);
 481 }
 482
 483 static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
 484 {
 485         int num_crtc = 0;
 486
 487         switch (adev->asic_type) {
 488         case CHIP_CARRIZO:
 489                 num_crtc = 3;
 490                 break;
 491         case CHIP_STONEY:
 492                 num_crtc = 2;
 493                 break;
 494         case CHIP_POLARIS10:
 495         case CHIP_VEGAM:
 496                 num_crtc = 6;
 497                 break;
 498         case CHIP_POLARIS11:
 499         case CHIP_POLARIS12:
 500                 num_crtc = 5;
 501                 break;
 502         default:
 503                 num_crtc = 0;
 504         }
 505         return num_crtc;
 506 }
 507
 508 void dce_v11_0_disable_dce(struct amdgpu_device *adev)
 509 {
 510         /*Disable VGA render and enabled crtc, if has DCE engine*/
 511         if (amdgpu_atombios_has_dce_engine_info(adev)) {
 512                 u32 tmp;
 513                 int crtc_enabled, i;
 514
 515                 dce_v11_0_set_vga_render_state(adev, false);
 516
 517                 /*Disable crtc*/
 518                 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
 519                         crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 520                                                                          CRTC_CONTROL, CRTC_MASTER_EN);
 521                         if (crtc_enabled) {
 522                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 523                                 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 524                                 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 525                                 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 526                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 527                         }
 528                 }
 529         }
 530 }
 531
 532 static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
 533 {
 534         struct drm_device *dev = encoder->dev;
 535         struct amdgpu_device *adev = drm_to_adev(dev);
 536         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 537         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 538         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 539         int bpc = 0;
 540         u32 tmp = 0;
 541         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 542
 543         if (connector) {
 544                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 545                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 546                 dither = amdgpu_connector->dither;
 547         }
 548
 549         /* LVDS/eDP FMT is set up by atom */
 550         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 551                 return;
 552
 553         /* not needed for analog */
 554         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 555             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 556                 return;
 557
 558         if (bpc == 0)
 559                 return;
 560
 561         switch (bpc) {
 562         case 6:
 563                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 564                         /* XXX sort out optimal dither settings */
 565                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 566                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 567                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 568                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
 569                 } else {
 570                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 571                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
 572                 }
 573                 break;
 574         case 8:
 575                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 576                         /* XXX sort out optimal dither settings */
 577                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 578                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 579                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 580                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 581                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
 582                 } else {
 583                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 584                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
 585                 }
 586                 break;
 587         case 10:
 588                 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
 589                         /* XXX sort out optimal dither settings */
 590                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
 591                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
 592                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
 593                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
 594                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
 595                 } else {
 596                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
 597                         tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
 598                 }
 599                 break;
 600         default:
 601                 /* not needed */
 602                 break;
 603         }
 604
 605         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 606 }
 607
 608
 609 /* display watermark setup */
 610 /**
 611  * dce_v11_0_line_buffer_adjust - Set up the line buffer
 612  *
 613  * @adev: amdgpu_device pointer
 614  * @amdgpu_crtc: the selected display controller
 615  * @mode: the current display mode on the selected display
 616  * controller
 617  *
 618  * Setup up the line buffer allocation for
 619  * the selected display controller (CIK).
 620  * Returns the line buffer size in pixels.
 621  */
 622 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
 623                                        struct amdgpu_crtc *amdgpu_crtc,
 624                                        struct drm_display_mode *mode)
 625 {
 626         u32 tmp, buffer_alloc, i, mem_cfg;
 627         u32 pipe_offset = amdgpu_crtc->crtc_id;
 628         /*
 629          * Line Buffer Setup
 630          * There are 6 line buffers, one for each display controllers.
 631          * There are 3 partitions per LB. Select the number of partitions
 632          * to enable based on the display width.  For display widths larger
 633          * than 4096, you need use to use 2 display controllers and combine
 634          * them using the stereo blender.
 635          */
 636         if (amdgpu_crtc->base.enabled && mode) {
 637                 if (mode->crtc_hdisplay < 1920) {
 638                         mem_cfg = 1;
 639                         buffer_alloc = 2;
 640                 } else if (mode->crtc_hdisplay < 2560) {
 641                         mem_cfg = 2;
 642                         buffer_alloc = 2;
 643                 } else if (mode->crtc_hdisplay < 4096) {
 644                         mem_cfg = 0;
 645                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 646                 } else {
 647                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 648                         mem_cfg = 0;
 649                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 650                 }
 651         } else {
 652                 mem_cfg = 1;
 653                 buffer_alloc = 0;
 654         }
 655
 656         tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
 657         tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
 658         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
 659
 660         tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 661         tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
 662         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
 663
 664         for (i = 0; i < adev->usec_timeout; i++) {
 665                 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
 666                 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
 667                         break;
 668                 udelay(1);
 669         }
 670
 671         if (amdgpu_crtc->base.enabled && mode) {
 672                 switch (mem_cfg) {
 673                 case 0:
 674                 default:
 675                         return 4096 * 2;
 676                 case 1:
 677                         return 1920 * 2;
 678                 case 2:
 679                         return 2560 * 2;
 680                 }
 681         }
 682
 683         /* controller not enabled, so no lb used */
 684         return 0;
 685 }
 686
 687 /**
 688  * cik_get_number_of_dram_channels - get the number of dram channels
 689  *
 690  * @adev: amdgpu_device pointer
 691  *
 692  * Look up the number of video ram channels (CIK).
 693  * Used for display watermark bandwidth calculations
 694  * Returns the number of dram channels
 695  */
 696 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 697 {
 698         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 699
 700         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 701         case 0:
 702         default:
 703                 return 1;
 704         case 1:
 705                 return 2;
 706         case 2:
 707                 return 4;
 708         case 3:
 709                 return 8;
 710         case 4:
 711                 return 3;
 712         case 5:
 713                 return 6;
 714         case 6:
 715                 return 10;
 716         case 7:
 717                 return 12;
 718         case 8:
 719                 return 16;
 720         }
 721 }
 722
 723 struct dce10_wm_params {
 724         u32 dram_channels; /* number of dram channels */
 725         u32 yclk;          /* bandwidth per dram data pin in kHz */
 726         u32 sclk;          /* engine clock in kHz */
 727         u32 disp_clk;      /* display clock in kHz */
 728         u32 src_width;     /* viewport width */
 729         u32 active_time;   /* active display time in ns */
 730         u32 blank_time;    /* blank time in ns */
 731         bool interlaced;    /* mode is interlaced */
 732         fixed20_12 vsc;    /* vertical scale ratio */
 733         u32 num_heads;     /* number of active crtcs */
 734         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 735         u32 lb_size;       /* line buffer allocated to pipe */
 736         u32 vtaps;         /* vertical scaler taps */
 737 };
 738
 739 /**
 740  * dce_v11_0_dram_bandwidth - get the dram bandwidth
 741  *
 742  * @wm: watermark calculation data
 743  *
 744  * Calculate the raw dram bandwidth (CIK).
 745  * Used for display watermark bandwidth calculations
 746  * Returns the dram bandwidth in MBytes/s
 747  */
 748 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
 749 {
 750         /* Calculate raw DRAM Bandwidth */
 751         fixed20_12 dram_efficiency; /* 0.7 */
 752         fixed20_12 yclk, dram_channels, bandwidth;
 753         fixed20_12 a;
 754
 755         a.full = dfixed_const(1000);
 756         yclk.full = dfixed_const(wm->yclk);
 757         yclk.full = dfixed_div(yclk, a);
 758         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 759         a.full = dfixed_const(10);
 760         dram_efficiency.full = dfixed_const(7);
 761         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 762         bandwidth.full = dfixed_mul(dram_channels, yclk);
 763         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 764
 765         return dfixed_trunc(bandwidth);
 766 }
 767
 768 /**
 769  * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
 770  *
 771  * @wm: watermark calculation data
 772  *
 773  * Calculate the dram bandwidth used for display (CIK).
 774  * Used for display watermark bandwidth calculations
 775  * Returns the dram bandwidth for display in MBytes/s
 776  */
 777 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 778 {
 779         /* Calculate DRAM Bandwidth and the part allocated to display. */
 780         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 781         fixed20_12 yclk, dram_channels, bandwidth;
 782         fixed20_12 a;
 783
 784         a.full = dfixed_const(1000);
 785         yclk.full = dfixed_const(wm->yclk);
 786         yclk.full = dfixed_div(yclk, a);
 787         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 788         a.full = dfixed_const(10);
 789         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 790         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 791         bandwidth.full = dfixed_mul(dram_channels, yclk);
 792         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 793
 794         return dfixed_trunc(bandwidth);
 795 }
 796
 797 /**
 798  * dce_v11_0_data_return_bandwidth - get the data return bandwidth
 799  *
 800  * @wm: watermark calculation data
 801  *
 802  * Calculate the data return bandwidth used for display (CIK).
 803  * Used for display watermark bandwidth calculations
 804  * Returns the data return bandwidth in MBytes/s
 805  */
 806 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
 807 {
 808         /* Calculate the display Data return Bandwidth */
 809         fixed20_12 return_efficiency; /* 0.8 */
 810         fixed20_12 sclk, bandwidth;
 811         fixed20_12 a;
 812
 813         a.full = dfixed_const(1000);
 814         sclk.full = dfixed_const(wm->sclk);
 815         sclk.full = dfixed_div(sclk, a);
 816         a.full = dfixed_const(10);
 817         return_efficiency.full = dfixed_const(8);
 818         return_efficiency.full = dfixed_div(return_efficiency, a);
 819         a.full = dfixed_const(32);
 820         bandwidth.full = dfixed_mul(a, sclk);
 821         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 822
 823         return dfixed_trunc(bandwidth);
 824 }
 825
 826 /**
 827  * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
 828  *
 829  * @wm: watermark calculation data
 830  *
 831  * Calculate the dmif bandwidth used for display (CIK).
 832  * Used for display watermark bandwidth calculations
 833  * Returns the dmif bandwidth in MBytes/s
 834  */
 835 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
 836 {
 837         /* Calculate the DMIF Request Bandwidth */
 838         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 839         fixed20_12 disp_clk, bandwidth;
 840         fixed20_12 a, b;
 841
 842         a.full = dfixed_const(1000);
 843         disp_clk.full = dfixed_const(wm->disp_clk);
 844         disp_clk.full = dfixed_div(disp_clk, a);
 845         a.full = dfixed_const(32);
 846         b.full = dfixed_mul(a, disp_clk);
 847
 848         a.full = dfixed_const(10);
 849         disp_clk_request_efficiency.full = dfixed_const(8);
 850         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 851
 852         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
 853
 854         return dfixed_trunc(bandwidth);
 855 }
 856
 857 /**
 858  * dce_v11_0_available_bandwidth - get the min available bandwidth
 859  *
 860  * @wm: watermark calculation data
 861  *
 862  * Calculate the min available bandwidth used for display (CIK).
 863  * Used for display watermark bandwidth calculations
 864  * Returns the min available bandwidth in MBytes/s
 865  */
 866 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
 867 {
 868         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 869         u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
 870         u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
 871         u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
 872
 873         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 874 }
 875
 876 /**
 877  * dce_v11_0_average_bandwidth - get the average available bandwidth
 878  *
 879  * @wm: watermark calculation data
 880  *
 881  * Calculate the average available bandwidth used for display (CIK).
 882  * Used for display watermark bandwidth calculations
 883  * Returns the average available bandwidth in MBytes/s
 884  */
 885 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
 886 {
 887         /* Calculate the display mode Average Bandwidth
 888          * DisplayMode should contain the source and destination dimensions,
 889          * timing, etc.
 890          */
 891         fixed20_12 bpp;
 892         fixed20_12 line_time;
 893         fixed20_12 src_width;
 894         fixed20_12 bandwidth;
 895         fixed20_12 a;
 896
 897         a.full = dfixed_const(1000);
 898         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 899         line_time.full = dfixed_div(line_time, a);
 900         bpp.full = dfixed_const(wm->bytes_per_pixel);
 901         src_width.full = dfixed_const(wm->src_width);
 902         bandwidth.full = dfixed_mul(src_width, bpp);
 903         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 904         bandwidth.full = dfixed_div(bandwidth, line_time);
 905
 906         return dfixed_trunc(bandwidth);
 907 }
 908
 909 /**
 910  * dce_v11_0_latency_watermark - get the latency watermark
 911  *
 912  * @wm: watermark calculation data
 913  *
 914  * Calculate the latency watermark (CIK).
 915  * Used for display watermark bandwidth calculations
 916  * Returns the latency watermark in ns
 917  */
 918 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
 919 {
 920         /* First calculate the latency in ns */
 921         u32 mc_latency = 2000; /* 2000 ns. */
 922         u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
 923         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 924         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 925         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 926         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 927                 (wm->num_heads * cursor_line_pair_return_time);
 928         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 929         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 930         u32 tmp, dmif_size = 12288;
 931         fixed20_12 a, b, c;
 932
 933         if (wm->num_heads == 0)
 934                 return 0;
 935
 936         a.full = dfixed_const(2);
 937         b.full = dfixed_const(1);
 938         if ((wm->vsc.full > a.full) ||
 939             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 940             (wm->vtaps >= 5) ||
 941             ((wm->vsc.full >= a.full) && wm->interlaced))
 942                 max_src_lines_per_dst_line = 4;
 943         else
 944                 max_src_lines_per_dst_line = 2;
 945
 946         a.full = dfixed_const(available_bandwidth);
 947         b.full = dfixed_const(wm->num_heads);
 948         a.full = dfixed_div(a, b);
 949         tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
 950         tmp = min(dfixed_trunc(a), tmp);
 951
 952         lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
 953
 954         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 955         b.full = dfixed_const(1000);
 956         c.full = dfixed_const(lb_fill_bw);
 957         b.full = dfixed_div(c, b);
 958         a.full = dfixed_div(a, b);
 959         line_fill_time = dfixed_trunc(a);
 960
 961         if (line_fill_time < wm->active_time)
 962                 return latency;
 963         else
 964                 return latency + (line_fill_time - wm->active_time);
 965
 966 }
 967
 968 /**
 969  * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
 970  * average and available dram bandwidth
 971  *
 972  * @wm: watermark calculation data
 973  *
 974  * Check if the display average bandwidth fits in the display
 975  * dram bandwidth (CIK).
 976  * Used for display watermark bandwidth calculations
 977  * Returns true if the display fits, false if not.
 978  */
 979 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
 980 {
 981         if (dce_v11_0_average_bandwidth(wm) <=
 982             (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
 983                 return true;
 984         else
 985                 return false;
 986 }
 987
 988 /**
 989  * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
 990  * average and available bandwidth
 991  *
 992  * @wm: watermark calculation data
 993  *
 994  * Check if the display average bandwidth fits in the display
 995  * available bandwidth (CIK).
 996  * Used for display watermark bandwidth calculations
 997  * Returns true if the display fits, false if not.
 998  */
 999 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
1000 {
1001         if (dce_v11_0_average_bandwidth(wm) <=
1002             (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1003                 return true;
1004         else
1005                 return false;
1006 }
1007
1008 /**
1009  * dce_v11_0_check_latency_hiding - check latency hiding
1010  *
1011  * @wm: watermark calculation data
1012  *
1013  * Check latency hiding (CIK).
1014  * Used for display watermark bandwidth calculations
1015  * Returns true if the display fits, false if not.
1016  */
1017 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1018 {
1019         u32 lb_partitions = wm->lb_size / wm->src_width;
1020         u32 line_time = wm->active_time + wm->blank_time;
1021         u32 latency_tolerant_lines;
1022         u32 latency_hiding;
1023         fixed20_12 a;
1024
1025         a.full = dfixed_const(1);
1026         if (wm->vsc.full > a.full)
1027                 latency_tolerant_lines = 1;
1028         else {
1029                 if (lb_partitions <= (wm->vtaps + 1))
1030                         latency_tolerant_lines = 1;
1031                 else
1032                         latency_tolerant_lines = 2;
1033         }
1034
1035         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1036
1037         if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1038                 return true;
1039         else
1040                 return false;
1041 }
1042
1043 /**
1044  * dce_v11_0_program_watermarks - program display watermarks
1045  *
1046  * @adev: amdgpu_device pointer
1047  * @amdgpu_crtc: the selected display controller
1048  * @lb_size: line buffer size
1049  * @num_heads: number of display controllers in use
1050  *
1051  * Calculate and program the display watermarks for the
1052  * selected display controller (CIK).
1053  */
1054 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1055                                         struct amdgpu_crtc *amdgpu_crtc,
1056                                         u32 lb_size, u32 num_heads)
1057 {
1058         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1059         struct dce10_wm_params wm_low, wm_high;
1060         u32 active_time;
1061         u32 line_time = 0;
1062         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1063         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1064
1065         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1066                 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1067                                             (u32)mode->clock);
1068                 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1069                                           (u32)mode->clock);
1070                 line_time = min(line_time, (u32)65535);
1071
1072                 /* watermark for high clocks */
1073                 if (adev->pm.dpm_enabled) {
1074                         wm_high.yclk =
1075                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1076                         wm_high.sclk =
1077                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1078                 } else {
1079                         wm_high.yclk = adev->pm.current_mclk * 10;
1080                         wm_high.sclk = adev->pm.current_sclk * 10;
1081                 }
1082
1083                 wm_high.disp_clk = mode->clock;
1084                 wm_high.src_width = mode->crtc_hdisplay;
1085                 wm_high.active_time = active_time;
1086                 wm_high.blank_time = line_time - wm_high.active_time;
1087                 wm_high.interlaced = false;
1088                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1089                         wm_high.interlaced = true;
1090                 wm_high.vsc = amdgpu_crtc->vsc;
1091                 wm_high.vtaps = 1;
1092                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1093                         wm_high.vtaps = 2;
1094                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1095                 wm_high.lb_size = lb_size;
1096                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1097                 wm_high.num_heads = num_heads;
1098
1099                 /* set for high clocks */
1100                 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1101
1102                 /* possibly force display priority to high */
1103                 /* should really do this at mode validation time... */
1104                 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1105                     !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1106                     !dce_v11_0_check_latency_hiding(&wm_high) ||
1107                     (adev->mode_info.disp_priority == 2)) {
1108                         DRM_DEBUG_KMS("force priority to high\n");
1109                 }
1110
1111                 /* watermark for low clocks */
1112                 if (adev->pm.dpm_enabled) {
1113                         wm_low.yclk =
1114                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1115                         wm_low.sclk =
1116                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1117                 } else {
1118                         wm_low.yclk = adev->pm.current_mclk * 10;
1119                         wm_low.sclk = adev->pm.current_sclk * 10;
1120                 }
1121
1122                 wm_low.disp_clk = mode->clock;
1123                 wm_low.src_width = mode->crtc_hdisplay;
1124                 wm_low.active_time = active_time;
1125                 wm_low.blank_time = line_time - wm_low.active_time;
1126                 wm_low.interlaced = false;
1127                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1128                         wm_low.interlaced = true;
1129                 wm_low.vsc = amdgpu_crtc->vsc;
1130                 wm_low.vtaps = 1;
1131                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1132                         wm_low.vtaps = 2;
1133                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1134                 wm_low.lb_size = lb_size;
1135                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1136                 wm_low.num_heads = num_heads;
1137
1138                 /* set for low clocks */
1139                 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1140
1141                 /* possibly force display priority to high */
1142                 /* should really do this at mode validation time... */
1143                 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1144                     !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1145                     !dce_v11_0_check_latency_hiding(&wm_low) ||
1146                     (adev->mode_info.disp_priority == 2)) {
1147                         DRM_DEBUG_KMS("force priority to high\n");
1148                 }
1149                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1150         }
1151
1152         /* select wm A */
1153         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1154         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1155         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1156         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1157         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1158         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1159         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1160         /* select wm B */
1161         tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1162         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1163         tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1164         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1165         tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1166         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1167         /* restore original selection */
1168         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1169
1170         /* save values for DPM */
1171         amdgpu_crtc->line_time = line_time;
1172         amdgpu_crtc->wm_high = latency_watermark_a;
1173         amdgpu_crtc->wm_low = latency_watermark_b;
1174         /* Save number of lines the linebuffer leads before the scanout */
1175         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1176 }
1177
1178 /**
1179  * dce_v11_0_bandwidth_update - program display watermarks
1180  *
1181  * @adev: amdgpu_device pointer
1182  *
1183  * Calculate and program the display watermarks and line
1184  * buffer allocation (CIK).
1185  */
1186 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1187 {
1188         struct drm_display_mode *mode = NULL;
1189         u32 num_heads = 0, lb_size;
1190         int i;
1191
1192         amdgpu_display_update_priority(adev);
1193
1194         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1195                 if (adev->mode_info.crtcs[i]->base.enabled)
1196                         num_heads++;
1197         }
1198         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1199                 mode = &adev->mode_info.crtcs[i]->base.mode;
1200                 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1201                 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1202                                             lb_size, num_heads);
1203         }
1204 }
1205
1206 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1207 {
1208         int i;
1209         u32 offset, tmp;
1210
1211         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1212                 offset = adev->mode_info.audio.pin[i].offset;
1213                 tmp = RREG32_AUDIO_ENDPT(offset,
1214                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1215                 if (((tmp &
1216                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1217                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1218                         adev->mode_info.audio.pin[i].connected = false;
1219                 else
1220                         adev->mode_info.audio.pin[i].connected = true;
1221         }
1222 }
1223
1224 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1225 {
1226         int i;
1227
1228         dce_v11_0_audio_get_connected_pins(adev);
1229
1230         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1231                 if (adev->mode_info.audio.pin[i].connected)
1232                         return &adev->mode_info.audio.pin[i];
1233         }
1234         DRM_ERROR("No connected audio pins found!\n");
1235         return NULL;
1236 }
1237
1238 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1239 {
1240         struct amdgpu_device *adev = drm_to_adev(encoder->dev);
1241         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1242         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1243         u32 tmp;
1244
1245         if (!dig || !dig->afmt || !dig->afmt->pin)
1246                 return;
1247
1248         tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1249         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1250         WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1251 }
1252
1253 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1254                                                 struct drm_display_mode *mode)
1255 {
1256         struct drm_device *dev = encoder->dev;
1257         struct amdgpu_device *adev = drm_to_adev(dev);
1258         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1259         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1260         struct drm_connector *connector;
1261         struct drm_connector_list_iter iter;
1262         struct amdgpu_connector *amdgpu_connector = NULL;
1263         u32 tmp;
1264         int interlace = 0;
1265
1266         if (!dig || !dig->afmt || !dig->afmt->pin)
1267                 return;
1268
1269         drm_connector_list_iter_begin(dev, &iter);
1270         drm_for_each_connector_iter(connector, &iter) {
1271                 if (connector->encoder == encoder) {
1272                         amdgpu_connector = to_amdgpu_connector(connector);
1273                         break;
1274                 }
1275         }
1276         drm_connector_list_iter_end(&iter);
1277
1278         if (!amdgpu_connector) {
1279                 DRM_ERROR("Couldn't find encoder's connector\n");
1280                 return;
1281         }
1282
1283         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1284                 interlace = 1;
1285         if (connector->latency_present[interlace]) {
1286                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1287                                     VIDEO_LIPSYNC, connector->video_latency[interlace]);
1288                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1289                                     AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1290         } else {
1291                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1292                                     VIDEO_LIPSYNC, 0);
1293                 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1294                                     AUDIO_LIPSYNC, 0);
1295         }
1296         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1297                            ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1298 }
1299
1300 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1301 {
1302         struct drm_device *dev = encoder->dev;
1303         struct amdgpu_device *adev = drm_to_adev(dev);
1304         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1305         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1306         struct drm_connector *connector;
1307         struct drm_connector_list_iter iter;
1308         struct amdgpu_connector *amdgpu_connector = NULL;
1309         u32 tmp;
1310         u8 *sadb = NULL;
1311         int sad_count;
1312
1313         if (!dig || !dig->afmt || !dig->afmt->pin)
1314                 return;
1315
1316         drm_connector_list_iter_begin(dev, &iter);
1317         drm_for_each_connector_iter(connector, &iter) {
1318                 if (connector->encoder == encoder) {
1319                         amdgpu_connector = to_amdgpu_connector(connector);
1320                         break;
1321                 }
1322         }
1323         drm_connector_list_iter_end(&iter);
1324
1325         if (!amdgpu_connector) {
1326                 DRM_ERROR("Couldn't find encoder's connector\n");
1327                 return;
1328         }
1329
1330         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1331         if (sad_count < 0) {
1332                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1333                 sad_count = 0;
1334         }
1335
1336         /* program the speaker allocation */
1337         tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1338                                  ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1339         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1340                             DP_CONNECTION, 0);
1341         /* set HDMI mode */
1342         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1343                             HDMI_CONNECTION, 1);
1344         if (sad_count)
1345                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1346                                     SPEAKER_ALLOCATION, sadb[0]);
1347         else
1348                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1349                                     SPEAKER_ALLOCATION, 5); /* stereo */
1350         WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1351                            ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1352
1353         kfree(sadb);
1354 }
1355
1356 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1357 {
1358         struct drm_device *dev = encoder->dev;
1359         struct amdgpu_device *adev = drm_to_adev(dev);
1360         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1361         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1362         struct drm_connector *connector;
1363         struct drm_connector_list_iter iter;
1364         struct amdgpu_connector *amdgpu_connector = NULL;
1365         struct cea_sad *sads;
1366         int i, sad_count;
1367
1368         static const u16 eld_reg_to_type[][2] = {
1369                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1370                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1371                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1372                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1373                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1374                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1375                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1376                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1377                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1378                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1379                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1380                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1381         };
1382
1383         if (!dig || !dig->afmt || !dig->afmt->pin)
1384                 return;
1385
1386         drm_connector_list_iter_begin(dev, &iter);
1387         drm_for_each_connector_iter(connector, &iter) {
1388                 if (connector->encoder == encoder) {
1389                         amdgpu_connector = to_amdgpu_connector(connector);
1390                         break;
1391                 }
1392         }
1393         drm_connector_list_iter_end(&iter);
1394
1395         if (!amdgpu_connector) {
1396                 DRM_ERROR("Couldn't find encoder's connector\n");
1397                 return;
1398         }
1399
1400         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1401         if (sad_count < 0)
1402                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1403         if (sad_count <= 0)
1404                 return;
1405         BUG_ON(!sads);
1406
1407         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1408                 u32 tmp = 0;
1409                 u8 stereo_freqs = 0;
1410                 int max_channels = -1;
1411                 int j;
1412
1413                 for (j = 0; j < sad_count; j++) {
1414                         struct cea_sad *sad = &sads[j];
1415
1416                         if (sad->format == eld_reg_to_type[i][1]) {
1417                                 if (sad->channels > max_channels) {
1418                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1419                                                             MAX_CHANNELS, sad->channels);
1420                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1421                                                             DESCRIPTOR_BYTE_2, sad->byte2);
1422                                         tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1423                                                             SUPPORTED_FREQUENCIES, sad->freq);
1424                                         max_channels = sad->channels;
1425                                 }
1426
1427                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1428                                         stereo_freqs |= sad->freq;
1429                                 else
1430                                         break;
1431                         }
1432                 }
1433
1434                 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1435                                     SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1436                 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1437         }
1438
1439         kfree(sads);
1440 }
1441
1442 static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1443                                   struct amdgpu_audio_pin *pin,
1444                                   bool enable)
1445 {
1446         if (!pin)
1447                 return;
1448
1449         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1450                            enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1451 }
1452
1453 static const u32 pin_offsets[] =
1454 {
1455         AUD0_REGISTER_OFFSET,
1456         AUD1_REGISTER_OFFSET,
1457         AUD2_REGISTER_OFFSET,
1458         AUD3_REGISTER_OFFSET,
1459         AUD4_REGISTER_OFFSET,
1460         AUD5_REGISTER_OFFSET,
1461         AUD6_REGISTER_OFFSET,
1462         AUD7_REGISTER_OFFSET,
1463 };
1464
1465 static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1466 {
1467         int i;
1468
1469         if (!amdgpu_audio)
1470                 return 0;
1471
1472         adev->mode_info.audio.enabled = true;
1473
1474         switch (adev->asic_type) {
1475         case CHIP_CARRIZO:
1476         case CHIP_STONEY:
1477                 adev->mode_info.audio.num_pins = 7;
1478                 break;
1479         case CHIP_POLARIS10:
1480         case CHIP_VEGAM:
1481                 adev->mode_info.audio.num_pins = 8;
1482                 break;
1483         case CHIP_POLARIS11:
1484         case CHIP_POLARIS12:
1485                 adev->mode_info.audio.num_pins = 6;
1486                 break;
1487         default:
1488                 return -EINVAL;
1489         }
1490
1491         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1492                 adev->mode_info.audio.pin[i].channels = -1;
1493                 adev->mode_info.audio.pin[i].rate = -1;
1494                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1495                 adev->mode_info.audio.pin[i].status_bits = 0;
1496                 adev->mode_info.audio.pin[i].category_code = 0;
1497                 adev->mode_info.audio.pin[i].connected = false;
1498                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1499                 adev->mode_info.audio.pin[i].id = i;
1500                 /* disable audio.  it will be set up later */
1501                 /* XXX remove once we switch to ip funcs */
1502                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1503         }
1504
1505         return 0;
1506 }
1507
1508 static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1509 {
1510         int i;
1511
1512         if (!amdgpu_audio)
1513                 return;
1514
1515         if (!adev->mode_info.audio.enabled)
1516                 return;
1517
1518         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1519                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1520
1521         adev->mode_info.audio.enabled = false;
1522 }
1523
1524 /*
1525  * update the N and CTS parameters for a given pixel clock rate
1526  */
1527 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1528 {
1529         struct drm_device *dev = encoder->dev;
1530         struct amdgpu_device *adev = drm_to_adev(dev);
1531         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1532         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1533         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1534         u32 tmp;
1535
1536         tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1537         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1538         WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1539         tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1540         tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1541         WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1542
1543         tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1544         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1545         WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1546         tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1547         tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1548         WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1549
1550         tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1551         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1552         WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1553         tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1554         tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1555         WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1556
1557 }
1558
1559 /*
1560  * build a HDMI Video Info Frame
1561  */
1562 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1563                                                void *buffer, size_t size)
1564 {
1565         struct drm_device *dev = encoder->dev;
1566         struct amdgpu_device *adev = drm_to_adev(dev);
1567         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1568         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1569         uint8_t *frame = buffer + 3;
1570         uint8_t *header = buffer;
1571
1572         WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1573                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1574         WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1575                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1576         WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1577                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1578         WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1579                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1580 }
1581
1582 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1583 {
1584         struct drm_device *dev = encoder->dev;
1585         struct amdgpu_device *adev = drm_to_adev(dev);
1586         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1587         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1588         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1589         u32 dto_phase = 24 * 1000;
1590         u32 dto_modulo = clock;
1591         u32 tmp;
1592
1593         if (!dig || !dig->afmt)
1594                 return;
1595
1596         /* XXX two dtos; generally use dto0 for hdmi */
1597         /* Express [24MHz / target pixel clock] as an exact rational
1598          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1599          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1600          */
1601         tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1602         tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1603                             amdgpu_crtc->crtc_id);
1604         WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1605         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1606         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1607 }
1608
1609 /*
1610  * update the info frames with the data from the current display mode
1611  */
1612 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1613                                   struct drm_display_mode *mode)
1614 {
1615         struct drm_device *dev = encoder->dev;
1616         struct amdgpu_device *adev = drm_to_adev(dev);
1617         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1618         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1619         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1620         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1621         struct hdmi_avi_infoframe frame;
1622         ssize_t err;
1623         u32 tmp;
1624         int bpc = 8;
1625
1626         if (!dig || !dig->afmt)
1627                 return;
1628
1629         /* Silent, r600_hdmi_enable will raise WARN for us */
1630         if (!dig->afmt->enabled)
1631                 return;
1632
1633         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1634         if (encoder->crtc) {
1635                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1636                 bpc = amdgpu_crtc->bpc;
1637         }
1638
1639         /* disable audio prior to setting up hw */
1640         dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1641         dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1642
1643         dce_v11_0_audio_set_dto(encoder, mode->clock);
1644
1645         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1646         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1647         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1648
1649         WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1650
1651         tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1652         switch (bpc) {
1653         case 0:
1654         case 6:
1655         case 8:
1656         case 16:
1657         default:
1658                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1659                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1660                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1661                           connector->name, bpc);
1662                 break;
1663         case 10:
1664                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1665                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1666                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1667                           connector->name);
1668                 break;
1669         case 12:
1670                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1671                 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1672                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1673                           connector->name);
1674                 break;
1675         }
1676         WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1677
1678         tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1679         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1680         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1681         tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1682         WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1683
1684         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1685         /* enable audio info frames (frames won't be set until audio is enabled) */
1686         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1687         /* required for audio info values to be updated */
1688         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1689         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1690
1691         tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1692         /* required for audio info values to be updated */
1693         tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1694         WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1695
1696         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1697         /* anything other than 0 */
1698         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1699         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1700
1701         WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1702
1703         tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1704         /* set the default audio delay */
1705         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1706         /* should be suffient for all audio modes and small enough for all hblanks */
1707         tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1708         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1709
1710         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1711         /* allow 60958 channel status fields to be updated */
1712         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1713         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1714
1715         tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1716         if (bpc > 8)
1717                 /* clear SW CTS value */
1718                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1719         else
1720                 /* select SW CTS value */
1721                 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1722         /* allow hw to sent ACR packets when required */
1723         tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1724         WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1725
1726         dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1727
1728         tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1729         tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1730         WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1731
1732         tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1733         tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1734         WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1735
1736         tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1737         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1738         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1739         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1740         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1741         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1742         tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1743         WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1744
1745         dce_v11_0_audio_write_speaker_allocation(encoder);
1746
1747         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1748                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1749
1750         dce_v11_0_afmt_audio_select_pin(encoder);
1751         dce_v11_0_audio_write_sad_regs(encoder);
1752         dce_v11_0_audio_write_latency_fields(encoder, mode);
1753
1754         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1755         if (err < 0) {
1756                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1757                 return;
1758         }
1759
1760         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1761         if (err < 0) {
1762                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1763                 return;
1764         }
1765
1766         dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1767
1768         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1769         /* enable AVI info frames */
1770         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1771         /* required for audio info values to be updated */
1772         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1773         WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1774
1775         tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1776         tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1777         WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1778
1779         tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1780         /* send audio packets */
1781         tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1782         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1783
1784         WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1785         WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1786         WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1787         WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1788
1789         /* enable audio after to setting up hw */
1790         dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1791 }
1792
1793 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1794 {
1795         struct drm_device *dev = encoder->dev;
1796         struct amdgpu_device *adev = drm_to_adev(dev);
1797         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1798         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1799
1800         if (!dig || !dig->afmt)
1801                 return;
1802
1803         /* Silent, r600_hdmi_enable will raise WARN for us */
1804         if (enable && dig->afmt->enabled)
1805                 return;
1806         if (!enable && !dig->afmt->enabled)
1807                 return;
1808
1809         if (!enable && dig->afmt->pin) {
1810                 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1811                 dig->afmt->pin = NULL;
1812         }
1813
1814         dig->afmt->enabled = enable;
1815
1816         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1817                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1818 }
1819
1820 static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1821 {
1822         int i;
1823
1824         for (i = 0; i < adev->mode_info.num_dig; i++)
1825                 adev->mode_info.afmt[i] = NULL;
1826
1827         /* DCE11 has audio blocks tied to DIG encoders */
1828         for (i = 0; i < adev->mode_info.num_dig; i++) {
1829                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1830                 if (adev->mode_info.afmt[i]) {
1831                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1832                         adev->mode_info.afmt[i]->id = i;
1833                 } else {
1834                         int j;
1835                         for (j = 0; j < i; j++) {
1836                                 kfree(adev->mode_info.afmt[j]);
1837                                 adev->mode_info.afmt[j] = NULL;
1838                         }
1839                         return -ENOMEM;
1840                 }
1841         }
1842         return 0;
1843 }
1844
1845 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1846 {
1847         int i;
1848
1849         for (i = 0; i < adev->mode_info.num_dig; i++) {
1850                 kfree(adev->mode_info.afmt[i]);
1851                 adev->mode_info.afmt[i] = NULL;
1852         }
1853 }
1854
1855 static const u32 vga_control_regs[6] =
1856 {
1857         mmD1VGA_CONTROL,
1858         mmD2VGA_CONTROL,
1859         mmD3VGA_CONTROL,
1860         mmD4VGA_CONTROL,
1861         mmD5VGA_CONTROL,
1862         mmD6VGA_CONTROL,
1863 };
1864
1865 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1866 {
1867         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1868         struct drm_device *dev = crtc->dev;
1869         struct amdgpu_device *adev = drm_to_adev(dev);
1870         u32 vga_control;
1871
1872         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1873         if (enable)
1874                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1875         else
1876                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1877 }
1878
1879 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
1880 {
1881         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1882         struct drm_device *dev = crtc->dev;
1883         struct amdgpu_device *adev = drm_to_adev(dev);
1884
1885         if (enable)
1886                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1887         else
1888                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1889 }
1890
1891 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
1892                                      struct drm_framebuffer *fb,
1893                                      int x, int y, int atomic)
1894 {
1895         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1896         struct drm_device *dev = crtc->dev;
1897         struct amdgpu_device *adev = drm_to_adev(dev);
1898         struct drm_framebuffer *target_fb;
1899         struct drm_gem_object *obj;
1900         struct amdgpu_bo *abo;
1901         uint64_t fb_location, tiling_flags;
1902         uint32_t fb_format, fb_pitch_pixels;
1903         u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1904         u32 pipe_config;
1905         u32 tmp, viewport_w, viewport_h;
1906         int r;
1907         bool bypass_lut = false;
1908
1909         /* no fb bound */
1910         if (!atomic && !crtc->primary->fb) {
1911                 DRM_DEBUG_KMS("No FB bound\n");
1912                 return 0;
1913         }
1914
1915         if (atomic)
1916                 target_fb = fb;
1917         else
1918                 target_fb = crtc->primary->fb;
1919
1920         /* If atomic, assume fb object is pinned & idle & fenced and
1921          * just update base pointers
1922          */
1923         obj = target_fb->obj[0];
1924         abo = gem_to_amdgpu_bo(obj);
1925         r = amdgpu_bo_reserve(abo, false);
1926         if (unlikely(r != 0))
1927                 return r;
1928
1929         if (!atomic) {
1930                 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1931                 if (unlikely(r != 0)) {
1932                         amdgpu_bo_unreserve(abo);
1933                         return -EINVAL;
1934                 }
1935         }
1936         fb_location = amdgpu_bo_gpu_offset(abo);
1937
1938         amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1939         amdgpu_bo_unreserve(abo);
1940
1941         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1942
1943         switch (target_fb->format->format) {
1944         case DRM_FORMAT_C8:
1945                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1946                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1947                 break;
1948         case DRM_FORMAT_XRGB4444:
1949         case DRM_FORMAT_ARGB4444:
1950                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1951                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1952 #ifdef __BIG_ENDIAN
1953                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1954                                         ENDIAN_8IN16);
1955 #endif
1956                 break;
1957         case DRM_FORMAT_XRGB1555:
1958         case DRM_FORMAT_ARGB1555:
1959                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1960                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1961 #ifdef __BIG_ENDIAN
1962                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1963                                         ENDIAN_8IN16);
1964 #endif
1965                 break;
1966         case DRM_FORMAT_BGRX5551:
1967         case DRM_FORMAT_BGRA5551:
1968                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1969                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1970 #ifdef __BIG_ENDIAN
1971                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1972                                         ENDIAN_8IN16);
1973 #endif
1974                 break;
1975         case DRM_FORMAT_RGB565:
1976                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1977                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1978 #ifdef __BIG_ENDIAN
1979                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1980                                         ENDIAN_8IN16);
1981 #endif
1982                 break;
1983         case DRM_FORMAT_XRGB8888:
1984         case DRM_FORMAT_ARGB8888:
1985                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1986                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1987 #ifdef __BIG_ENDIAN
1988                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1989                                         ENDIAN_8IN32);
1990 #endif
1991                 break;
1992         case DRM_FORMAT_XRGB2101010:
1993         case DRM_FORMAT_ARGB2101010:
1994                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1995                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1996 #ifdef __BIG_ENDIAN
1997                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1998                                         ENDIAN_8IN32);
1999 #endif
2000                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2001                 bypass_lut = true;
2002                 break;
2003         case DRM_FORMAT_BGRX1010102:
2004         case DRM_FORMAT_BGRA1010102:
2005                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2006                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2007 #ifdef __BIG_ENDIAN
2008                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2009                                         ENDIAN_8IN32);
2010 #endif
2011                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2012                 bypass_lut = true;
2013                 break;
2014         case DRM_FORMAT_XBGR8888:
2015         case DRM_FORMAT_ABGR8888:
2016                 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2017                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2018                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
2019                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
2020 #ifdef __BIG_ENDIAN
2021                 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2022                                         ENDIAN_8IN32);
2023 #endif
2024                 break;
2025         default:
2026                 DRM_ERROR("Unsupported screen format %p4cc\n",
2027                           &target_fb->format->format);
2028                 return -EINVAL;
2029         }
2030
2031         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2032                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2033
2034                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2035                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2036                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2037                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2038                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2039
2040                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2041                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2042                                           ARRAY_2D_TILED_THIN1);
2043                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2044                                           tile_split);
2045                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2046                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2047                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2048                                           mtaspect);
2049                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2050                                           ADDR_SURF_MICRO_TILING_DISPLAY);
2051         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2052                 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2053                                           ARRAY_1D_TILED_THIN1);
2054         }
2055
2056         fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2057                                   pipe_config);
2058
2059         dce_v11_0_vga_enable(crtc, false);
2060
2061         /* Make sure surface address is updated at vertical blank rather than
2062          * horizontal blank
2063          */
2064         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2065         tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2066                             GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2067         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2068
2069         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2070                upper_32_bits(fb_location));
2071         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2072                upper_32_bits(fb_location));
2073         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2074                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2075         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2076                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2077         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2078         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2079
2080         /*
2081          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2082          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2083          * retain the full precision throughout the pipeline.
2084          */
2085         tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2086         if (bypass_lut)
2087                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2088         else
2089                 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2090         WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2091
2092         if (bypass_lut)
2093                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2094
2095         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2096         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2097         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2098         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2099         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2100         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2101
2102         fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2103         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2104
2105         dce_v11_0_grph_enable(crtc, true);
2106
2107         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2108                target_fb->height);
2109
2110         x &= ~3;
2111         y &= ~1;
2112         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2113                (x << 16) | y);
2114         viewport_w = crtc->mode.hdisplay;
2115         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2116         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2117                (viewport_w << 16) | viewport_h);
2118
2119         /* set pageflip to happen anywhere in vblank interval */
2120         WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2121
2122         if (!atomic && fb && fb != crtc->primary->fb) {
2123                 abo = gem_to_amdgpu_bo(fb->obj[0]);
2124                 r = amdgpu_bo_reserve(abo, true);
2125                 if (unlikely(r != 0))
2126                         return r;
2127                 amdgpu_bo_unpin(abo);
2128                 amdgpu_bo_unreserve(abo);
2129         }
2130
2131         /* Bytes per pixel may have changed */
2132         dce_v11_0_bandwidth_update(adev);
2133
2134         return 0;
2135 }
2136
2137 static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2138                                      struct drm_display_mode *mode)
2139 {
2140         struct drm_device *dev = crtc->dev;
2141         struct amdgpu_device *adev = drm_to_adev(dev);
2142         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2143         u32 tmp;
2144
2145         tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2146         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2147                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2148         else
2149                 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2150         WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2151 }
2152
2153 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2154 {
2155         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2156         struct drm_device *dev = crtc->dev;
2157         struct amdgpu_device *adev = drm_to_adev(dev);
2158         u16 *r, *g, *b;
2159         int i;
2160         u32 tmp;
2161
2162         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2163
2164         tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2165         tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2166         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2167
2168         tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2169         tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2170         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2171
2172         tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2173         tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2174         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2175
2176         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2177
2178         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2179         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2180         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2181
2182         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2183         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2184         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2185
2186         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2187         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2188
2189         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2190         r = crtc->gamma_store;
2191         g = r + crtc->gamma_size;
2192         b = g + crtc->gamma_size;
2193         for (i = 0; i < 256; i++) {
2194                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2195                        ((*r++ & 0xffc0) << 14) |
2196                        ((*g++ & 0xffc0) << 4) |
2197                        (*b++ >> 6));
2198         }
2199
2200         tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2201         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2202         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2203         tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2204         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2205
2206         tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2207         tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2208         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2209
2210         tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2211         tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2212         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2213
2214         tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2215         tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2216         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2217
2218         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2219         WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2220         /* XXX this only needs to be programmed once per crtc at startup,
2221          * not sure where the best place for it is
2222          */
2223         tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2224         tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2225         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2226 }
2227
2228 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2229 {
2230         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2231         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2232
2233         switch (amdgpu_encoder->encoder_id) {
2234         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2235                 if (dig->linkb)
2236                         return 1;
2237                 else
2238                         return 0;
2239         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2240                 if (dig->linkb)
2241                         return 3;
2242                 else
2243                         return 2;
2244         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2245                 if (dig->linkb)
2246                         return 5;
2247                 else
2248                         return 4;
2249         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2250                 return 6;
2251         default:
2252                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2253                 return 0;
2254         }
2255 }
2256
2257 /**
2258  * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2259  *
2260  * @crtc: drm crtc
2261  *
2262  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2263  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2264  * monitors a dedicated PPLL must be used.  If a particular board has
2265  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2266  * as there is no need to program the PLL itself.  If we are not able to
2267  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2268  * avoid messing up an existing monitor.
2269  *
2270  * Asic specific PLL information
2271  *
2272  * DCE 10.x
2273  * Tonga
2274  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2275  * CI
2276  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2277  *
2278  */
2279 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2280 {
2281         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2282         struct drm_device *dev = crtc->dev;
2283         struct amdgpu_device *adev = drm_to_adev(dev);
2284         u32 pll_in_use;
2285         int pll;
2286
2287         if ((adev->asic_type == CHIP_POLARIS10) ||
2288             (adev->asic_type == CHIP_POLARIS11) ||
2289             (adev->asic_type == CHIP_POLARIS12) ||
2290             (adev->asic_type == CHIP_VEGAM)) {
2291                 struct amdgpu_encoder *amdgpu_encoder =
2292                         to_amdgpu_encoder(amdgpu_crtc->encoder);
2293                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2294
2295                 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2296                         return ATOM_DP_DTO;
2297
2298                 switch (amdgpu_encoder->encoder_id) {
2299                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2300                         if (dig->linkb)
2301                                 return ATOM_COMBOPHY_PLL1;
2302                         else
2303                                 return ATOM_COMBOPHY_PLL0;
2304                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2305                         if (dig->linkb)
2306                                 return ATOM_COMBOPHY_PLL3;
2307                         else
2308                                 return ATOM_COMBOPHY_PLL2;
2309                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2310                         if (dig->linkb)
2311                                 return ATOM_COMBOPHY_PLL5;
2312                         else
2313                                 return ATOM_COMBOPHY_PLL4;
2314                 default:
2315                         DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2316                         return ATOM_PPLL_INVALID;
2317                 }
2318         }
2319
2320         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2321                 if (adev->clock.dp_extclk)
2322                         /* skip PPLL programming if using ext clock */
2323                         return ATOM_PPLL_INVALID;
2324                 else {
2325                         /* use the same PPLL for all DP monitors */
2326                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2327                         if (pll != ATOM_PPLL_INVALID)
2328                                 return pll;
2329                 }
2330         } else {
2331                 /* use the same PPLL for all monitors with the same clock */
2332                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2333                 if (pll != ATOM_PPLL_INVALID)
2334                         return pll;
2335         }
2336
2337         /* XXX need to determine what plls are available on each DCE11 part */
2338         pll_in_use = amdgpu_pll_get_use_mask(crtc);
2339         if (adev->flags & AMD_IS_APU) {
2340                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2341                         return ATOM_PPLL1;
2342                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2343                         return ATOM_PPLL0;
2344                 DRM_ERROR("unable to allocate a PPLL\n");
2345                 return ATOM_PPLL_INVALID;
2346         } else {
2347                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2348                         return ATOM_PPLL2;
2349                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2350                         return ATOM_PPLL1;
2351                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2352                         return ATOM_PPLL0;
2353                 DRM_ERROR("unable to allocate a PPLL\n");
2354                 return ATOM_PPLL_INVALID;
2355         }
2356         return ATOM_PPLL_INVALID;
2357 }
2358
2359 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2360 {
2361         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2362         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2363         uint32_t cur_lock;
2364
2365         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2366         if (lock)
2367                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2368         else
2369                 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2370         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2371 }
2372
2373 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2374 {
2375         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2376         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2377         u32 tmp;
2378
2379         tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2380         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2381         WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2382 }
2383
2384 static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2385 {
2386         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2387         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2388         u32 tmp;
2389
2390         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2391                upper_32_bits(amdgpu_crtc->cursor_addr));
2392         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2393                lower_32_bits(amdgpu_crtc->cursor_addr));
2394
2395         tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2396         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2397         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2398         WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2399 }
2400
2401 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2402                                         int x, int y)
2403 {
2404         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2405         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2406         int xorigin = 0, yorigin = 0;
2407
2408         amdgpu_crtc->cursor_x = x;
2409         amdgpu_crtc->cursor_y = y;
2410
2411         /* avivo cursor are offset into the total surface */
2412         x += crtc->x;
2413         y += crtc->y;
2414         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2415
2416         if (x < 0) {
2417                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2418                 x = 0;
2419         }
2420         if (y < 0) {
2421                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2422                 y = 0;
2423         }
2424
2425         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2426         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2427         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2428                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2429
2430         return 0;
2431 }
2432
2433 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2434                                       int x, int y)
2435 {
2436         int ret;
2437
2438         dce_v11_0_lock_cursor(crtc, true);
2439         ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2440         dce_v11_0_lock_cursor(crtc, false);
2441
2442         return ret;
2443 }
2444
2445 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2446                                       struct drm_file *file_priv,
2447                                       uint32_t handle,
2448                                       uint32_t width,
2449                                       uint32_t height,
2450                                       int32_t hot_x,
2451                                       int32_t hot_y)
2452 {
2453         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2454         struct drm_gem_object *obj;
2455         struct amdgpu_bo *aobj;
2456         int ret;
2457
2458         if (!handle) {
2459                 /* turn off cursor */
2460                 dce_v11_0_hide_cursor(crtc);
2461                 obj = NULL;
2462                 goto unpin;
2463         }
2464
2465         if ((width > amdgpu_crtc->max_cursor_width) ||
2466             (height > amdgpu_crtc->max_cursor_height)) {
2467                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2468                 return -EINVAL;
2469         }
2470
2471         obj = drm_gem_object_lookup(file_priv, handle);
2472         if (!obj) {
2473                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2474                 return -ENOENT;
2475         }
2476
2477         aobj = gem_to_amdgpu_bo(obj);
2478         ret = amdgpu_bo_reserve(aobj, false);
2479         if (ret != 0) {
2480                 drm_gem_object_put(obj);
2481                 return ret;
2482         }
2483
2484         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2485         amdgpu_bo_unreserve(aobj);
2486         if (ret) {
2487                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2488                 drm_gem_object_put(obj);
2489                 return ret;
2490         }
2491         amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2492
2493         dce_v11_0_lock_cursor(crtc, true);
2494
2495         if (width != amdgpu_crtc->cursor_width ||
2496             height != amdgpu_crtc->cursor_height ||
2497             hot_x != amdgpu_crtc->cursor_hot_x ||
2498             hot_y != amdgpu_crtc->cursor_hot_y) {
2499                 int x, y;
2500
2501                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2502                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2503
2504                 dce_v11_0_cursor_move_locked(crtc, x, y);
2505
2506                 amdgpu_crtc->cursor_width = width;
2507                 amdgpu_crtc->cursor_height = height;
2508                 amdgpu_crtc->cursor_hot_x = hot_x;
2509                 amdgpu_crtc->cursor_hot_y = hot_y;
2510         }
2511
2512         dce_v11_0_show_cursor(crtc);
2513         dce_v11_0_lock_cursor(crtc, false);
2514
2515 unpin:
2516         if (amdgpu_crtc->cursor_bo) {
2517                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2518                 ret = amdgpu_bo_reserve(aobj, true);
2519                 if (likely(ret == 0)) {
2520                         amdgpu_bo_unpin(aobj);
2521                         amdgpu_bo_unreserve(aobj);
2522                 }
2523                 drm_gem_object_put(amdgpu_crtc->cursor_bo);
2524         }
2525
2526         amdgpu_crtc->cursor_bo = obj;
2527         return 0;
2528 }
2529
2530 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2531 {
2532         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2533
2534         if (amdgpu_crtc->cursor_bo) {
2535                 dce_v11_0_lock_cursor(crtc, true);
2536
2537                 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2538                                              amdgpu_crtc->cursor_y);
2539
2540                 dce_v11_0_show_cursor(crtc);
2541
2542                 dce_v11_0_lock_cursor(crtc, false);
2543         }
2544 }
2545
2546 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2547                                     u16 *blue, uint32_t size,
2548                                     struct drm_modeset_acquire_ctx *ctx)
2549 {
2550         dce_v11_0_crtc_load_lut(crtc);
2551
2552         return 0;
2553 }
2554
2555 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2556 {
2557         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2558
2559         drm_crtc_cleanup(crtc);
2560         kfree(amdgpu_crtc);
2561 }
2562
2563 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2564         .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2565         .cursor_move = dce_v11_0_crtc_cursor_move,
2566         .gamma_set = dce_v11_0_crtc_gamma_set,
2567         .set_config = amdgpu_display_crtc_set_config,
2568         .destroy = dce_v11_0_crtc_destroy,
2569         .page_flip_target = amdgpu_display_crtc_page_flip_target,
2570         .get_vblank_counter = amdgpu_get_vblank_counter_kms,
2571         .enable_vblank = amdgpu_enable_vblank_kms,
2572         .disable_vblank = amdgpu_disable_vblank_kms,
2573         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2574 };
2575
2576 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2577 {
2578         struct drm_device *dev = crtc->dev;
2579         struct amdgpu_device *adev = drm_to_adev(dev);
2580         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2581         unsigned type;
2582
2583         switch (mode) {
2584         case DRM_MODE_DPMS_ON:
2585                 amdgpu_crtc->enabled = true;
2586                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2587                 dce_v11_0_vga_enable(crtc, true);
2588                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2589                 dce_v11_0_vga_enable(crtc, false);
2590                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2591                 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2592                                                 amdgpu_crtc->crtc_id);
2593                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2594                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2595                 drm_crtc_vblank_on(crtc);
2596                 dce_v11_0_crtc_load_lut(crtc);
2597                 break;
2598         case DRM_MODE_DPMS_STANDBY:
2599         case DRM_MODE_DPMS_SUSPEND:
2600         case DRM_MODE_DPMS_OFF:
2601                 drm_crtc_vblank_off(crtc);
2602                 if (amdgpu_crtc->enabled) {
2603                         dce_v11_0_vga_enable(crtc, true);
2604                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2605                         dce_v11_0_vga_enable(crtc, false);
2606                 }
2607                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2608                 amdgpu_crtc->enabled = false;
2609                 break;
2610         }
2611         /* adjust pm to dpms */
2612         amdgpu_dpm_compute_clocks(adev);
2613 }
2614
2615 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2616 {
2617         /* disable crtc pair power gating before programming */
2618         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2619         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2620         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2621 }
2622
2623 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2624 {
2625         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2626         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2627 }
2628
2629 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2630 {
2631         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2632         struct drm_device *dev = crtc->dev;
2633         struct amdgpu_device *adev = drm_to_adev(dev);
2634         struct amdgpu_atom_ss ss;
2635         int i;
2636
2637         dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2638         if (crtc->primary->fb) {
2639                 int r;
2640                 struct amdgpu_bo *abo;
2641
2642                 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2643                 r = amdgpu_bo_reserve(abo, true);
2644                 if (unlikely(r))
2645                         DRM_ERROR("failed to reserve abo before unpin\n");
2646                 else {
2647                         amdgpu_bo_unpin(abo);
2648                         amdgpu_bo_unreserve(abo);
2649                 }
2650         }
2651         /* disable the GRPH */
2652         dce_v11_0_grph_enable(crtc, false);
2653
2654         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2655
2656         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2657                 if (adev->mode_info.crtcs[i] &&
2658                     adev->mode_info.crtcs[i]->enabled &&
2659                     i != amdgpu_crtc->crtc_id &&
2660                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2661                         /* one other crtc is using this pll don't turn
2662                          * off the pll
2663                          */
2664                         goto done;
2665                 }
2666         }
2667
2668         switch (amdgpu_crtc->pll_id) {
2669         case ATOM_PPLL0:
2670         case ATOM_PPLL1:
2671         case ATOM_PPLL2:
2672                 /* disable the ppll */
2673                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2674                                                  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2675                 break;
2676         case ATOM_COMBOPHY_PLL0:
2677         case ATOM_COMBOPHY_PLL1:
2678         case ATOM_COMBOPHY_PLL2:
2679         case ATOM_COMBOPHY_PLL3:
2680         case ATOM_COMBOPHY_PLL4:
2681         case ATOM_COMBOPHY_PLL5:
2682                 /* disable the ppll */
2683                 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2684                                                  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2685                 break;
2686         default:
2687                 break;
2688         }
2689 done:
2690         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2691         amdgpu_crtc->adjusted_clock = 0;
2692         amdgpu_crtc->encoder = NULL;
2693         amdgpu_crtc->connector = NULL;
2694 }
2695
2696 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2697                                   struct drm_display_mode *mode,
2698                                   struct drm_display_mode *adjusted_mode,
2699                                   int x, int y, struct drm_framebuffer *old_fb)
2700 {
2701         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2702         struct drm_device *dev = crtc->dev;
2703         struct amdgpu_device *adev = drm_to_adev(dev);
2704
2705         if (!amdgpu_crtc->adjusted_clock)
2706                 return -EINVAL;
2707
2708         if ((adev->asic_type == CHIP_POLARIS10) ||
2709             (adev->asic_type == CHIP_POLARIS11) ||
2710             (adev->asic_type == CHIP_POLARIS12) ||
2711             (adev->asic_type == CHIP_VEGAM)) {
2712                 struct amdgpu_encoder *amdgpu_encoder =
2713                         to_amdgpu_encoder(amdgpu_crtc->encoder);
2714                 int encoder_mode =
2715                         amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2716
2717                 /* SetPixelClock calculates the plls and ss values now */
2718                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2719                                                  amdgpu_crtc->pll_id,
2720                                                  encoder_mode, amdgpu_encoder->encoder_id,
2721                                                  adjusted_mode->clock, 0, 0, 0, 0,
2722                                                  amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2723         } else {
2724                 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2725         }
2726         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2727         dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2728         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2729         amdgpu_atombios_crtc_scaler_setup(crtc);
2730         dce_v11_0_cursor_reset(crtc);
2731         /* update the hw version fpr dpm */
2732         amdgpu_crtc->hw_mode = *adjusted_mode;
2733
2734         return 0;
2735 }
2736
2737 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2738                                      const struct drm_display_mode *mode,
2739                                      struct drm_display_mode *adjusted_mode)
2740 {
2741         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2742         struct drm_device *dev = crtc->dev;
2743         struct drm_encoder *encoder;
2744
2745         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2746         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2747                 if (encoder->crtc == crtc) {
2748                         amdgpu_crtc->encoder = encoder;
2749                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2750                         break;
2751                 }
2752         }
2753         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2754                 amdgpu_crtc->encoder = NULL;
2755                 amdgpu_crtc->connector = NULL;
2756                 return false;
2757         }
2758         if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2759                 return false;
2760         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2761                 return false;
2762         /* pick pll */
2763         amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2764         /* if we can't get a PPLL for a non-DP encoder, fail */
2765         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2766             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2767                 return false;
2768
2769         return true;
2770 }
2771
2772 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2773                                   struct drm_framebuffer *old_fb)
2774 {
2775         return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2776 }
2777
2778 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2779                                          struct drm_framebuffer *fb,
2780                                          int x, int y, enum mode_set_atomic state)
2781 {
2782         return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2783 }
2784
2785 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2786         .dpms = dce_v11_0_crtc_dpms,
2787         .mode_fixup = dce_v11_0_crtc_mode_fixup,
2788         .mode_set = dce_v11_0_crtc_mode_set,
2789         .mode_set_base = dce_v11_0_crtc_set_base,
2790         .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2791         .prepare = dce_v11_0_crtc_prepare,
2792         .commit = dce_v11_0_crtc_commit,
2793         .disable = dce_v11_0_crtc_disable,
2794         .get_scanout_position = amdgpu_crtc_get_scanout_position,
2795 };
2796
2797 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2798 {
2799         struct amdgpu_crtc *amdgpu_crtc;
2800
2801         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2802                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2803         if (amdgpu_crtc == NULL)
2804                 return -ENOMEM;
2805
2806         drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2807
2808         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2809         amdgpu_crtc->crtc_id = index;
2810         adev->mode_info.crtcs[index] = amdgpu_crtc;
2811
2812         amdgpu_crtc->max_cursor_width = 128;
2813         amdgpu_crtc->max_cursor_height = 128;
2814         adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2815         adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2816
2817         switch (amdgpu_crtc->crtc_id) {
2818         case 0:
2819         default:
2820                 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2821                 break;
2822         case 1:
2823                 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2824                 break;
2825         case 2:
2826                 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2827                 break;
2828         case 3:
2829                 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2830                 break;
2831         case 4:
2832                 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2833                 break;
2834         case 5:
2835                 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2836                 break;
2837         }
2838
2839         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2840         amdgpu_crtc->adjusted_clock = 0;
2841         amdgpu_crtc->encoder = NULL;
2842         amdgpu_crtc->connector = NULL;
2843         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2844
2845         return 0;
2846 }
2847
2848 static int dce_v11_0_early_init(void *handle)
2849 {
2850         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2851
2852         adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2853         adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2854
2855         dce_v11_0_set_display_funcs(adev);
2856
2857         adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
2858
2859         switch (adev->asic_type) {
2860         case CHIP_CARRIZO:
2861                 adev->mode_info.num_hpd = 6;
2862                 adev->mode_info.num_dig = 9;
2863                 break;
2864         case CHIP_STONEY:
2865                 adev->mode_info.num_hpd = 6;
2866                 adev->mode_info.num_dig = 9;
2867                 break;
2868         case CHIP_POLARIS10:
2869         case CHIP_VEGAM:
2870                 adev->mode_info.num_hpd = 6;
2871                 adev->mode_info.num_dig = 6;
2872                 break;
2873         case CHIP_POLARIS11:
2874         case CHIP_POLARIS12:
2875                 adev->mode_info.num_hpd = 5;
2876                 adev->mode_info.num_dig = 5;
2877                 break;
2878         default:
2879                 /* FIXME: not supported yet */
2880                 return -EINVAL;
2881         }
2882
2883         dce_v11_0_set_irq_funcs(adev);
2884
2885         return 0;
2886 }
2887
2888 static int dce_v11_0_sw_init(void *handle)
2889 {
2890         int r, i;
2891         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2892
2893         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2894                 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2895                 if (r)
2896                         return r;
2897         }
2898
2899         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2900                 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2901                 if (r)
2902                         return r;
2903         }
2904
2905         /* HPD hotplug */
2906         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2907         if (r)
2908                 return r;
2909
2910         adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2911
2912         adev_to_drm(adev)->mode_config.async_page_flip = true;
2913
2914         adev_to_drm(adev)->mode_config.max_width = 16384;
2915         adev_to_drm(adev)->mode_config.max_height = 16384;
2916
2917         adev_to_drm(adev)->mode_config.preferred_depth = 24;
2918         adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2919
2920         adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
2921
2922         r = amdgpu_display_modeset_create_props(adev);
2923         if (r)
2924                 return r;
2925
2926         adev_to_drm(adev)->mode_config.max_width = 16384;
2927         adev_to_drm(adev)->mode_config.max_height = 16384;
2928
2929
2930         /* allocate crtcs */
2931         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2932                 r = dce_v11_0_crtc_init(adev, i);
2933                 if (r)
2934                         return r;
2935         }
2936
2937         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2938                 amdgpu_display_print_display_setup(adev_to_drm(adev));
2939         else
2940                 return -EINVAL;
2941
2942         /* setup afmt */
2943         r = dce_v11_0_afmt_init(adev);
2944         if (r)
2945                 return r;
2946
2947         r = dce_v11_0_audio_init(adev);
2948         if (r)
2949                 return r;
2950
2951         /* Disable vblank IRQs aggressively for power-saving */
2952         /* XXX: can this be enabled for DC? */
2953         adev_to_drm(adev)->vblank_disable_immediate = true;
2954
2955         r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
2956         if (r)
2957                 return r;
2958
2959         INIT_DELAYED_WORK(&adev->hotplug_work,
2960                   amdgpu_display_hotplug_work_func);
2961
2962         drm_kms_helper_poll_init(adev_to_drm(adev));
2963
2964         adev->mode_info.mode_config_initialized = true;
2965         return 0;
2966 }
2967
2968 static int dce_v11_0_sw_fini(void *handle)
2969 {
2970         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2971
2972         kfree(adev->mode_info.bios_hardcoded_edid);
2973
2974         drm_kms_helper_poll_fini(adev_to_drm(adev));
2975
2976         dce_v11_0_audio_fini(adev);
2977
2978         dce_v11_0_afmt_fini(adev);
2979
2980         drm_mode_config_cleanup(adev_to_drm(adev));
2981         adev->mode_info.mode_config_initialized = false;
2982
2983         return 0;
2984 }
2985
2986 static int dce_v11_0_hw_init(void *handle)
2987 {
2988         int i;
2989         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2990
2991         dce_v11_0_init_golden_registers(adev);
2992
2993         /* disable vga render */
2994         dce_v11_0_set_vga_render_state(adev, false);
2995         /* init dig PHYs, disp eng pll */
2996         amdgpu_atombios_crtc_powergate_init(adev);
2997         amdgpu_atombios_encoder_init_dig(adev);
2998         if ((adev->asic_type == CHIP_POLARIS10) ||
2999             (adev->asic_type == CHIP_POLARIS11) ||
3000             (adev->asic_type == CHIP_POLARIS12) ||
3001             (adev->asic_type == CHIP_VEGAM)) {
3002                 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
3003                                                    DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
3004                 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
3005                                                    DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
3006         } else {
3007                 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3008         }
3009
3010         /* initialize hpd */
3011         dce_v11_0_hpd_init(adev);
3012
3013         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3014                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3015         }
3016
3017         dce_v11_0_pageflip_interrupt_init(adev);
3018
3019         return 0;
3020 }
3021
3022 static int dce_v11_0_hw_fini(void *handle)
3023 {
3024         int i;
3025         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3026
3027         dce_v11_0_hpd_fini(adev);
3028
3029         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3030                 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3031         }
3032
3033         dce_v11_0_pageflip_interrupt_fini(adev);
3034
3035         flush_delayed_work(&adev->hotplug_work);
3036
3037         return 0;
3038 }
3039
3040 static int dce_v11_0_suspend(void *handle)
3041 {
3042         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3043         int r;
3044
3045         r = amdgpu_display_suspend_helper(adev);
3046         if (r)
3047                 return r;
3048
3049         adev->mode_info.bl_level =
3050                 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
3051
3052         return dce_v11_0_hw_fini(handle);
3053 }
3054
3055 static int dce_v11_0_resume(void *handle)
3056 {
3057         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3058         int ret;
3059
3060         amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
3061                                                            adev->mode_info.bl_level);
3062
3063         ret = dce_v11_0_hw_init(handle);
3064
3065         /* turn on the BL */
3066         if (adev->mode_info.bl_encoder) {
3067                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3068                                                                   adev->mode_info.bl_encoder);
3069                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3070                                                     bl_level);
3071         }
3072         if (ret)
3073                 return ret;
3074
3075         return amdgpu_display_resume_helper(adev);
3076 }
3077
3078 static bool dce_v11_0_is_idle(void *handle)
3079 {
3080         return true;
3081 }
3082
3083 static int dce_v11_0_wait_for_idle(void *handle)
3084 {
3085         return 0;
3086 }
3087
3088 static int dce_v11_0_soft_reset(void *handle)
3089 {
3090         u32 srbm_soft_reset = 0, tmp;
3091         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3092
3093         if (dce_v11_0_is_display_hung(adev))
3094                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3095
3096         if (srbm_soft_reset) {
3097                 tmp = RREG32(mmSRBM_SOFT_RESET);
3098                 tmp |= srbm_soft_reset;
3099                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3100                 WREG32(mmSRBM_SOFT_RESET, tmp);
3101                 tmp = RREG32(mmSRBM_SOFT_RESET);
3102
3103                 udelay(50);
3104
3105                 tmp &= ~srbm_soft_reset;
3106                 WREG32(mmSRBM_SOFT_RESET, tmp);
3107                 tmp = RREG32(mmSRBM_SOFT_RESET);
3108
3109                 /* Wait a little for things to settle down */
3110                 udelay(50);
3111         }
3112         return 0;
3113 }
3114
3115 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3116                                                      int crtc,
3117                                                      enum amdgpu_interrupt_state state)
3118 {
3119         u32 lb_interrupt_mask;
3120
3121         if (crtc >= adev->mode_info.num_crtc) {
3122                 DRM_DEBUG("invalid crtc %d\n", crtc);
3123                 return;
3124         }
3125
3126         switch (state) {
3127         case AMDGPU_IRQ_STATE_DISABLE:
3128                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3129                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3130                                                   VBLANK_INTERRUPT_MASK, 0);
3131                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3132                 break;
3133         case AMDGPU_IRQ_STATE_ENABLE:
3134                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3135                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3136                                                   VBLANK_INTERRUPT_MASK, 1);
3137                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3138                 break;
3139         default:
3140                 break;
3141         }
3142 }
3143
3144 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3145                                                     int crtc,
3146                                                     enum amdgpu_interrupt_state state)
3147 {
3148         u32 lb_interrupt_mask;
3149
3150         if (crtc >= adev->mode_info.num_crtc) {
3151                 DRM_DEBUG("invalid crtc %d\n", crtc);
3152                 return;
3153         }
3154
3155         switch (state) {
3156         case AMDGPU_IRQ_STATE_DISABLE:
3157                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3158                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3159                                                   VLINE_INTERRUPT_MASK, 0);
3160                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3161                 break;
3162         case AMDGPU_IRQ_STATE_ENABLE:
3163                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3164                 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3165                                                   VLINE_INTERRUPT_MASK, 1);
3166                 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3167                 break;
3168         default:
3169                 break;
3170         }
3171 }
3172
3173 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3174                                         struct amdgpu_irq_src *source,
3175                                         unsigned hpd,
3176                                         enum amdgpu_interrupt_state state)
3177 {
3178         u32 tmp;
3179
3180         if (hpd >= adev->mode_info.num_hpd) {
3181                 DRM_DEBUG("invalid hdp %d\n", hpd);
3182                 return 0;
3183         }
3184
3185         switch (state) {
3186         case AMDGPU_IRQ_STATE_DISABLE:
3187                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3188                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3189                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3190                 break;
3191         case AMDGPU_IRQ_STATE_ENABLE:
3192                 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3193                 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3194                 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3195                 break;
3196         default:
3197                 break;
3198         }
3199
3200         return 0;
3201 }
3202
3203 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3204                                         struct amdgpu_irq_src *source,
3205                                         unsigned type,
3206                                         enum amdgpu_interrupt_state state)
3207 {
3208         switch (type) {
3209         case AMDGPU_CRTC_IRQ_VBLANK1:
3210                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3211                 break;
3212         case AMDGPU_CRTC_IRQ_VBLANK2:
3213                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3214                 break;
3215         case AMDGPU_CRTC_IRQ_VBLANK3:
3216                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3217                 break;
3218         case AMDGPU_CRTC_IRQ_VBLANK4:
3219                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3220                 break;
3221         case AMDGPU_CRTC_IRQ_VBLANK5:
3222                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3223                 break;
3224         case AMDGPU_CRTC_IRQ_VBLANK6:
3225                 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3226                 break;
3227         case AMDGPU_CRTC_IRQ_VLINE1:
3228                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3229                 break;
3230         case AMDGPU_CRTC_IRQ_VLINE2:
3231                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3232                 break;
3233         case AMDGPU_CRTC_IRQ_VLINE3:
3234                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3235                 break;
3236         case AMDGPU_CRTC_IRQ_VLINE4:
3237                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3238                 break;
3239         case AMDGPU_CRTC_IRQ_VLINE5:
3240                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3241                 break;
3242          case AMDGPU_CRTC_IRQ_VLINE6:
3243                 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3244                 break;
3245         default:
3246                 break;
3247         }
3248         return 0;
3249 }
3250
3251 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3252                                             struct amdgpu_irq_src *src,
3253                                             unsigned type,
3254                                             enum amdgpu_interrupt_state state)
3255 {
3256         u32 reg;
3257
3258         if (type >= adev->mode_info.num_crtc) {
3259                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3260                 return -EINVAL;
3261         }
3262
3263         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3264         if (state == AMDGPU_IRQ_STATE_DISABLE)
3265                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3266                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3267         else
3268                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3269                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3270
3271         return 0;
3272 }
3273
3274 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3275                                   struct amdgpu_irq_src *source,
3276                                   struct amdgpu_iv_entry *entry)
3277 {
3278         unsigned long flags;
3279         unsigned crtc_id;
3280         struct amdgpu_crtc *amdgpu_crtc;
3281         struct amdgpu_flip_work *works;
3282
3283         crtc_id = (entry->src_id - 8) >> 1;
3284         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3285
3286         if (crtc_id >= adev->mode_info.num_crtc) {
3287                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3288                 return -EINVAL;
3289         }
3290
3291         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3292             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3293                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3294                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3295
3296         /* IRQ could occur when in initial stage */
3297         if(amdgpu_crtc == NULL)
3298                 return 0;
3299
3300         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
3301         works = amdgpu_crtc->pflip_works;
3302         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3303                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3304                                                  "AMDGPU_FLIP_SUBMITTED(%d)\n",
3305                                                  amdgpu_crtc->pflip_status,
3306                                                  AMDGPU_FLIP_SUBMITTED);
3307                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3308                 return 0;
3309         }
3310
3311         /* page flip completed. clean up */
3312         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3313         amdgpu_crtc->pflip_works = NULL;
3314
3315         /* wakeup usersapce */
3316         if(works->event)
3317                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3318
3319         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3320
3321         drm_crtc_vblank_put(&amdgpu_crtc->base);
3322         schedule_work(&works->unpin_work);
3323
3324         return 0;
3325 }
3326
3327 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3328                                   int hpd)
3329 {
3330         u32 tmp;
3331
3332         if (hpd >= adev->mode_info.num_hpd) {
3333                 DRM_DEBUG("invalid hdp %d\n", hpd);
3334                 return;
3335         }
3336
3337         tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3338         tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3339         WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3340 }
3341
3342 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3343                                           int crtc)
3344 {
3345         u32 tmp;
3346
3347         if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3348                 DRM_DEBUG("invalid crtc %d\n", crtc);
3349                 return;
3350         }
3351
3352         tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3353         tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3354         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3355 }
3356
3357 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3358                                          int crtc)
3359 {
3360         u32 tmp;
3361
3362         if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3363                 DRM_DEBUG("invalid crtc %d\n", crtc);
3364                 return;
3365         }
3366
3367         tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3368         tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3369         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3370 }
3371
3372 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3373                                 struct amdgpu_irq_src *source,
3374                                 struct amdgpu_iv_entry *entry)
3375 {
3376         unsigned crtc = entry->src_id - 1;
3377         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3378         unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3379                                                                     crtc);
3380
3381         switch (entry->src_data[0]) {
3382         case 0: /* vblank */
3383                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3384                         dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3385                 else
3386                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3387
3388                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3389                         drm_handle_vblank(adev_to_drm(adev), crtc);
3390                 }
3391                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3392
3393                 break;
3394         case 1: /* vline */
3395                 if (disp_int & interrupt_status_offsets[crtc].vline)
3396                         dce_v11_0_crtc_vline_int_ack(adev, crtc);
3397                 else
3398                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3399
3400                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3401
3402                 break;
3403         default:
3404                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3405                 break;
3406         }
3407
3408         return 0;
3409 }
3410
3411 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3412                              struct amdgpu_irq_src *source,
3413                              struct amdgpu_iv_entry *entry)
3414 {
3415         uint32_t disp_int, mask;
3416         unsigned hpd;
3417
3418         if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3419                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3420                 return 0;
3421         }
3422
3423         hpd = entry->src_data[0];
3424         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3425         mask = interrupt_status_offsets[hpd].hpd;
3426
3427         if (disp_int & mask) {
3428                 dce_v11_0_hpd_int_ack(adev, hpd);
3429                 schedule_delayed_work(&adev->hotplug_work, 0);
3430                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3431         }
3432
3433         return 0;
3434 }
3435
3436 static int dce_v11_0_set_clockgating_state(void *handle,
3437                                           enum amd_clockgating_state state)
3438 {
3439         return 0;
3440 }
3441
3442 static int dce_v11_0_set_powergating_state(void *handle,
3443                                           enum amd_powergating_state state)
3444 {
3445         return 0;
3446 }
3447
3448 static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3449         .name = "dce_v11_0",
3450         .early_init = dce_v11_0_early_init,
3451         .late_init = NULL,
3452         .sw_init = dce_v11_0_sw_init,
3453         .sw_fini = dce_v11_0_sw_fini,
3454         .hw_init = dce_v11_0_hw_init,
3455         .hw_fini = dce_v11_0_hw_fini,
3456         .suspend = dce_v11_0_suspend,
3457         .resume = dce_v11_0_resume,
3458         .is_idle = dce_v11_0_is_idle,
3459         .wait_for_idle = dce_v11_0_wait_for_idle,
3460         .soft_reset = dce_v11_0_soft_reset,
3461         .set_clockgating_state = dce_v11_0_set_clockgating_state,
3462         .set_powergating_state = dce_v11_0_set_powergating_state,
3463 };
3464
3465 static void
3466 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3467                           struct drm_display_mode *mode,
3468                           struct drm_display_mode *adjusted_mode)
3469 {
3470         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3471
3472         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3473
3474         /* need to call this here rather than in prepare() since we need some crtc info */
3475         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3476
3477         /* set scaler clears this on some chips */
3478         dce_v11_0_set_interleave(encoder->crtc, mode);
3479
3480         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3481                 dce_v11_0_afmt_enable(encoder, true);
3482                 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3483         }
3484 }
3485
3486 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3487 {
3488         struct amdgpu_device *adev = drm_to_adev(encoder->dev);
3489         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3490         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3491
3492         if ((amdgpu_encoder->active_device &
3493              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3494             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3495              ENCODER_OBJECT_ID_NONE)) {
3496                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3497                 if (dig) {
3498                         dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3499                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3500                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3501                 }
3502         }
3503
3504         amdgpu_atombios_scratch_regs_lock(adev, true);
3505
3506         if (connector) {
3507                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3508
3509                 /* select the clock/data port if it uses a router */
3510                 if (amdgpu_connector->router.cd_valid)
3511                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3512
3513                 /* turn eDP panel on for mode set */
3514                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3515                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3516                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3517         }
3518
3519         /* this is needed for the pll/ss setup to work correctly in some cases */
3520         amdgpu_atombios_encoder_set_crtc_source(encoder);
3521         /* set up the FMT blocks */
3522         dce_v11_0_program_fmt(encoder);
3523 }
3524
3525 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3526 {
3527         struct drm_device *dev = encoder->dev;
3528         struct amdgpu_device *adev = drm_to_adev(dev);
3529
3530         /* need to call this here as we need the crtc set up */
3531         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3532         amdgpu_atombios_scratch_regs_lock(adev, false);
3533 }
3534
3535 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3536 {
3537         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3538         struct amdgpu_encoder_atom_dig *dig;
3539
3540         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3541
3542         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3543                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3544                         dce_v11_0_afmt_enable(encoder, false);
3545                 dig = amdgpu_encoder->enc_priv;
3546                 dig->dig_encoder = -1;
3547         }
3548         amdgpu_encoder->active_device = 0;
3549 }
3550
3551 /* these are handled by the primary encoders */
3552 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3553 {
3554
3555 }
3556
3557 static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3558 {
3559
3560 }
3561
3562 static void
3563 dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3564                       struct drm_display_mode *mode,
3565                       struct drm_display_mode *adjusted_mode)
3566 {
3567
3568 }
3569
3570 static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3571 {
3572
3573 }
3574
3575 static void
3576 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3577 {
3578
3579 }
3580
3581 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3582         .dpms = dce_v11_0_ext_dpms,
3583         .prepare = dce_v11_0_ext_prepare,
3584         .mode_set = dce_v11_0_ext_mode_set,
3585         .commit = dce_v11_0_ext_commit,
3586         .disable = dce_v11_0_ext_disable,
3587         /* no detect for TMDS/LVDS yet */
3588 };
3589
3590 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3591         .dpms = amdgpu_atombios_encoder_dpms,
3592         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3593         .prepare = dce_v11_0_encoder_prepare,
3594         .mode_set = dce_v11_0_encoder_mode_set,
3595         .commit = dce_v11_0_encoder_commit,
3596         .disable = dce_v11_0_encoder_disable,
3597         .detect = amdgpu_atombios_encoder_dig_detect,
3598 };
3599
3600 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3601         .dpms = amdgpu_atombios_encoder_dpms,
3602         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3603         .prepare = dce_v11_0_encoder_prepare,
3604         .mode_set = dce_v11_0_encoder_mode_set,
3605         .commit = dce_v11_0_encoder_commit,
3606         .detect = amdgpu_atombios_encoder_dac_detect,
3607 };
3608
3609 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3610 {
3611         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3612         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3613                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3614         kfree(amdgpu_encoder->enc_priv);
3615         drm_encoder_cleanup(encoder);
3616         kfree(amdgpu_encoder);
3617 }
3618
3619 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3620         .destroy = dce_v11_0_encoder_destroy,
3621 };
3622
3623 static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3624                                  uint32_t encoder_enum,
3625                                  uint32_t supported_device,
3626                                  u16 caps)
3627 {
3628         struct drm_device *dev = adev_to_drm(adev);
3629         struct drm_encoder *encoder;
3630         struct amdgpu_encoder *amdgpu_encoder;
3631
3632         /* see if we already added it */
3633         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3634                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3635                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3636                         amdgpu_encoder->devices |= supported_device;
3637                         return;
3638                 }
3639
3640         }
3641
3642         /* add a new one */
3643         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3644         if (!amdgpu_encoder)
3645                 return;
3646
3647         encoder = &amdgpu_encoder->base;
3648         switch (adev->mode_info.num_crtc) {
3649         case 1:
3650                 encoder->possible_crtcs = 0x1;
3651                 break;
3652         case 2:
3653         default:
3654                 encoder->possible_crtcs = 0x3;
3655                 break;
3656         case 3:
3657                 encoder->possible_crtcs = 0x7;
3658                 break;
3659         case 4:
3660                 encoder->possible_crtcs = 0xf;
3661                 break;
3662         case 5:
3663                 encoder->possible_crtcs = 0x1f;
3664                 break;
3665         case 6:
3666                 encoder->possible_crtcs = 0x3f;
3667                 break;
3668         }
3669
3670         amdgpu_encoder->enc_priv = NULL;
3671
3672         amdgpu_encoder->encoder_enum = encoder_enum;
3673         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3674         amdgpu_encoder->devices = supported_device;
3675         amdgpu_encoder->rmx_type = RMX_OFF;
3676         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3677         amdgpu_encoder->is_ext_encoder = false;
3678         amdgpu_encoder->caps = caps;
3679
3680         switch (amdgpu_encoder->encoder_id) {
3681         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3682         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3683                 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3684                                  DRM_MODE_ENCODER_DAC, NULL);
3685                 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3686                 break;
3687         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3688         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3689         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3690         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3691         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3692                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3693                         amdgpu_encoder->rmx_type = RMX_FULL;
3694                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3695                                          DRM_MODE_ENCODER_LVDS, NULL);
3696                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3697                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3698                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3699                                          DRM_MODE_ENCODER_DAC, NULL);
3700                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3701                 } else {
3702                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3703                                          DRM_MODE_ENCODER_TMDS, NULL);
3704                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3705                 }
3706                 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3707                 break;
3708         case ENCODER_OBJECT_ID_SI170B:
3709         case ENCODER_OBJECT_ID_CH7303:
3710         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3711         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3712         case ENCODER_OBJECT_ID_TITFP513:
3713         case ENCODER_OBJECT_ID_VT1623:
3714         case ENCODER_OBJECT_ID_HDMI_SI1930:
3715         case ENCODER_OBJECT_ID_TRAVIS:
3716         case ENCODER_OBJECT_ID_NUTMEG:
3717                 /* these are handled by the primary encoders */
3718                 amdgpu_encoder->is_ext_encoder = true;
3719                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3720                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3721                                          DRM_MODE_ENCODER_LVDS, NULL);
3722                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3723                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3724                                          DRM_MODE_ENCODER_DAC, NULL);
3725                 else
3726                         drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3727                                          DRM_MODE_ENCODER_TMDS, NULL);
3728                 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3729                 break;
3730         }
3731 }
3732
3733 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3734         .bandwidth_update = &dce_v11_0_bandwidth_update,
3735         .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3736         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3737         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3738         .hpd_sense = &dce_v11_0_hpd_sense,
3739         .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3740         .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3741         .page_flip = &dce_v11_0_page_flip,
3742         .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3743         .add_encoder = &dce_v11_0_encoder_add,
3744         .add_connector = &amdgpu_connector_add,
3745 };
3746
3747 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3748 {
3749         adev->mode_info.funcs = &dce_v11_0_display_funcs;
3750 }
3751
3752 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3753         .set = dce_v11_0_set_crtc_irq_state,
3754         .process = dce_v11_0_crtc_irq,
3755 };
3756
3757 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3758         .set = dce_v11_0_set_pageflip_irq_state,
3759         .process = dce_v11_0_pageflip_irq,
3760 };
3761
3762 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3763         .set = dce_v11_0_set_hpd_irq_state,
3764         .process = dce_v11_0_hpd_irq,
3765 };
3766
3767 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3768 {
3769         if (adev->mode_info.num_crtc > 0)
3770                 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3771         else
3772                 adev->crtc_irq.num_types = 0;
3773         adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3774
3775         adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3776         adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3777
3778         adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3779         adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3780 }
3781
3782 const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3783 {
3784         .type = AMD_IP_BLOCK_TYPE_DCE,
3785         .major = 11,
3786         .minor = 0,
3787         .rev = 0,
3788         .funcs = &dce_v11_0_ip_funcs,
3789 };
3790
3791 const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3792 {
3793         .type = AMD_IP_BLOCK_TYPE_DCE,
3794         .major = 11,
3795         .minor = 2,
3796         .rev = 0,
3797         .funcs = &dce_v11_0_ip_funcs,
3798 };