drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/sched/mm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swap.h>
  42 #include <linux/swiotlb.h>
  43 #include <linux/dma-buf.h>
  44 #include <linux/sizes.h>
  45
  46 #include <drm/ttm/ttm_bo_api.h>
  47 #include <drm/ttm/ttm_bo_driver.h>
  48 #include <drm/ttm/ttm_placement.h>
  49 #include <drm/ttm/ttm_module.h>
  50 #include <drm/ttm/ttm_page_alloc.h>
  51
  52 #include <drm/drm_debugfs.h>
  53 #include <drm/amdgpu_drm.h>
  54
  55 #include "amdgpu.h"
  56 #include "amdgpu_object.h"
  57 #include "amdgpu_trace.h"
  58 #include "amdgpu_amdkfd.h"
  59 #include "amdgpu_sdma.h"
  60 #include "amdgpu_ras.h"
  61 #include "amdgpu_atomfirmware.h"
  62 #include "bif/bif_4_1_d.h"
  63
  64 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  65
  66 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
  67                                    struct ttm_tt *ttm,
  68                                    struct ttm_resource *bo_mem);
  69 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
  70                                       struct ttm_tt *ttm);
  71
  72 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  73                                     unsigned int type,
  74                                     uint64_t size)
  75 {
  76         return ttm_range_man_init(&adev->mman.bdev, type,
  77                                   false, size >> PAGE_SHIFT);
  78 }
  79
  80 /**
  81  * amdgpu_evict_flags - Compute placement flags
  82  *
  83  * @bo: The buffer object to evict
  84  * @placement: Possible destination(s) for evicted BO
  85  *
  86  * Fill in placement data when ttm_bo_evict() is called
  87  */
  88 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  89                                 struct ttm_placement *placement)
  90 {
  91         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  92         struct amdgpu_bo *abo;
  93         static const struct ttm_place placements = {
  94                 .fpfn = 0,
  95                 .lpfn = 0,
  96                 .mem_type = TTM_PL_SYSTEM,
  97                 .flags = 0
  98         };
  99
 100         /* Don't handle scatter gather BOs */
 101         if (bo->type == ttm_bo_type_sg) {
 102                 placement->num_placement = 0;
 103                 placement->num_busy_placement = 0;
 104                 return;
 105         }
 106
 107         /* Object isn't an AMDGPU object so ignore */
 108         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 109                 placement->placement = &placements;
 110                 placement->busy_placement = &placements;
 111                 placement->num_placement = 1;
 112                 placement->num_busy_placement = 1;
 113                 return;
 114         }
 115
 116         abo = ttm_to_amdgpu_bo(bo);
 117         switch (bo->mem.mem_type) {
 118         case AMDGPU_PL_GDS:
 119         case AMDGPU_PL_GWS:
 120         case AMDGPU_PL_OA:
 121                 placement->num_placement = 0;
 122                 placement->num_busy_placement = 0;
 123                 return;
 124
 125         case TTM_PL_VRAM:
 126                 if (!adev->mman.buffer_funcs_enabled) {
 127                         /* Move to system memory */
 128                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 129                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 130                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 131                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 132
 133                         /* Try evicting to the CPU inaccessible part of VRAM
 134                          * first, but only set GTT as busy placement, so this
 135                          * BO will be evicted to GTT rather than causing other
 136                          * BOs to be evicted from VRAM
 137                          */
 138                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 139                                                          AMDGPU_GEM_DOMAIN_GTT);
 140                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 141                         abo->placements[0].lpfn = 0;
 142                         abo->placement.busy_placement = &abo->placements[1];
 143                         abo->placement.num_busy_placement = 1;
 144                 } else {
 145                         /* Move to GTT memory */
 146                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 147                 }
 148                 break;
 149         case TTM_PL_TT:
 150         default:
 151                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 152                 break;
 153         }
 154         *placement = abo->placement;
 155 }
 156
 157 /**
 158  * amdgpu_verify_access - Verify access for a mmap call
 159  *
 160  * @bo: The buffer object to map
 161  * @filp: The file pointer from the process performing the mmap
 162  *
 163  * This is called by ttm_bo_mmap() to verify whether a process
 164  * has the right to mmap a BO to their process space.
 165  */
 166 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 167 {
 168         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 169
 170         /*
 171          * Don't verify access for KFD BOs. They don't have a GEM
 172          * object associated with them.
 173          */
 174         if (abo->kfd_bo)
 175                 return 0;
 176
 177         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 178                 return -EPERM;
 179         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 180                                           filp->private_data);
 181 }
 182
 183 /**
 184  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 185  *
 186  * @bo: The bo to assign the memory to.
 187  * @mm_node: Memory manager node for drm allocator.
 188  * @mem: The region where the bo resides.
 189  *
 190  */
 191 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 192                                     struct drm_mm_node *mm_node,
 193                                     struct ttm_resource *mem)
 194 {
 195         uint64_t addr = 0;
 196
 197         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 198                 addr = mm_node->start << PAGE_SHIFT;
 199                 addr += amdgpu_ttm_domain_start(amdgpu_ttm_adev(bo->bdev),
 200                                                 mem->mem_type);
 201         }
 202         return addr;
 203 }
 204
 205 /**
 206  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 207  * @offset. It also modifies the offset to be within the drm_mm_node returned
 208  *
 209  * @mem: The region where the bo resides.
 210  * @offset: The offset that drm_mm_node is used for finding.
 211  *
 212  */
 213 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_resource *mem,
 214                                                uint64_t *offset)
 215 {
 216         struct drm_mm_node *mm_node = mem->mm_node;
 217
 218         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 219                 *offset -= (mm_node->size << PAGE_SHIFT);
 220                 ++mm_node;
 221         }
 222         return mm_node;
 223 }
 224
 225 /**
 226  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 227  * @bo: buffer object to map
 228  * @mem: memory object to map
 229  * @mm_node: drm_mm node object to map
 230  * @num_pages: number of pages to map
 231  * @offset: offset into @mm_node where to start
 232  * @window: which GART window to use
 233  * @ring: DMA ring to use for the copy
 234  * @tmz: if we should setup a TMZ enabled mapping
 235  * @addr: resulting address inside the MC address space
 236  *
 237  * Setup one of the GART windows to access a specific piece of memory or return
 238  * the physical address for local memory.
 239  */
 240 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 241                                  struct ttm_resource *mem,
 242                                  struct drm_mm_node *mm_node,
 243                                  unsigned num_pages, uint64_t offset,
 244                                  unsigned window, struct amdgpu_ring *ring,
 245                                  bool tmz, uint64_t *addr)
 246 {
 247         struct amdgpu_device *adev = ring->adev;
 248         struct amdgpu_job *job;
 249         unsigned num_dw, num_bytes;
 250         struct dma_fence *fence;
 251         uint64_t src_addr, dst_addr;
 252         void *cpu_addr;
 253         uint64_t flags;
 254         unsigned int i;
 255         int r;
 256
 257         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 258                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 259
 260         /* Map only what can't be accessed directly */
 261         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 262                 *addr = amdgpu_mm_node_addr(bo, mm_node, mem) + offset;
 263                 return 0;
 264         }
 265
 266         *addr = adev->gmc.gart_start;
 267         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 268                 AMDGPU_GPU_PAGE_SIZE;
 269         *addr += offset & ~PAGE_MASK;
 270
 271         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 272         num_bytes = num_pages * 8;
 273
 274         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 275                                      AMDGPU_IB_POOL_DELAYED, &job);
 276         if (r)
 277                 return r;
 278
 279         src_addr = num_dw * 4;
 280         src_addr += job->ibs[0].gpu_addr;
 281
 282         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 283         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 284         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 285                                 dst_addr, num_bytes, false);
 286
 287         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 288         WARN_ON(job->ibs[0].length_dw > num_dw);
 289
 290         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 291         if (tmz)
 292                 flags |= AMDGPU_PTE_TMZ;
 293
 294         cpu_addr = &job->ibs[0].ptr[num_dw];
 295
 296         if (mem->mem_type == TTM_PL_TT) {
 297                 struct ttm_dma_tt *dma;
 298                 dma_addr_t *dma_address;
 299
 300                 dma = container_of(bo->ttm, struct ttm_dma_tt, ttm);
 301                 dma_address = &dma->dma_address[offset >> PAGE_SHIFT];
 302                 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
 303                                     cpu_addr);
 304                 if (r)
 305                         goto error_free;
 306         } else {
 307                 dma_addr_t dma_address;
 308
 309                 dma_address = (mm_node->start << PAGE_SHIFT) + offset;
 310                 dma_address += adev->vm_manager.vram_base_offset;
 311
 312                 for (i = 0; i < num_pages; ++i) {
 313                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 314                                             &dma_address, flags, cpu_addr);
 315                         if (r)
 316                                 goto error_free;
 317
 318                         dma_address += PAGE_SIZE;
 319                 }
 320         }
 321
 322         r = amdgpu_job_submit(job, &adev->mman.entity,
 323                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 324         if (r)
 325                 goto error_free;
 326
 327         dma_fence_put(fence);
 328
 329         return r;
 330
 331 error_free:
 332         amdgpu_job_free(job);
 333         return r;
 334 }
 335
 336 /**
 337  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 338  * @adev: amdgpu device
 339  * @src: buffer/address where to read from
 340  * @dst: buffer/address where to write to
 341  * @size: number of bytes to copy
 342  * @tmz: if a secure copy should be used
 343  * @resv: resv object to sync to
 344  * @f: Returns the last fence if multiple jobs are submitted.
 345  *
 346  * The function copies @size bytes from {src->mem + src->offset} to
 347  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 348  * move and different for a BO to BO copy.
 349  *
 350  */
 351 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 352                                const struct amdgpu_copy_mem *src,
 353                                const struct amdgpu_copy_mem *dst,
 354                                uint64_t size, bool tmz,
 355                                struct dma_resv *resv,
 356                                struct dma_fence **f)
 357 {
 358         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 359                                         AMDGPU_GPU_PAGE_SIZE);
 360
 361         uint64_t src_node_size, dst_node_size, src_offset, dst_offset;
 362         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 363         struct drm_mm_node *src_mm, *dst_mm;
 364         struct dma_fence *fence = NULL;
 365         int r = 0;
 366
 367         if (!adev->mman.buffer_funcs_enabled) {
 368                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 369                 return -EINVAL;
 370         }
 371
 372         src_offset = src->offset;
 373         if (src->mem->mm_node) {
 374                 src_mm = amdgpu_find_mm_node(src->mem, &src_offset);
 375                 src_node_size = (src_mm->size << PAGE_SHIFT) - src_offset;
 376         } else {
 377                 src_mm = NULL;
 378                 src_node_size = ULLONG_MAX;
 379         }
 380
 381         dst_offset = dst->offset;
 382         if (dst->mem->mm_node) {
 383                 dst_mm = amdgpu_find_mm_node(dst->mem, &dst_offset);
 384                 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst_offset;
 385         } else {
 386                 dst_mm = NULL;
 387                 dst_node_size = ULLONG_MAX;
 388         }
 389
 390         mutex_lock(&adev->mman.gtt_window_lock);
 391
 392         while (size) {
 393                 uint32_t src_page_offset = src_offset & ~PAGE_MASK;
 394                 uint32_t dst_page_offset = dst_offset & ~PAGE_MASK;
 395                 struct dma_fence *next;
 396                 uint32_t cur_size;
 397                 uint64_t from, to;
 398
 399                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 400                  * begins at an offset, then adjust the size accordingly
 401                  */
 402                 cur_size = max(src_page_offset, dst_page_offset);
 403                 cur_size = min(min3(src_node_size, dst_node_size, size),
 404                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 405
 406                 /* Map src to window 0 and dst to window 1. */
 407                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, src_mm,
 408                                           PFN_UP(cur_size + src_page_offset),
 409                                           src_offset, 0, ring, tmz, &from);
 410                 if (r)
 411                         goto error;
 412
 413                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, dst_mm,
 414                                           PFN_UP(cur_size + dst_page_offset),
 415                                           dst_offset, 1, ring, tmz, &to);
 416                 if (r)
 417                         goto error;
 418
 419                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 420                                        resv, &next, false, true, tmz);
 421                 if (r)
 422                         goto error;
 423
 424                 dma_fence_put(fence);
 425                 fence = next;
 426
 427                 size -= cur_size;
 428                 if (!size)
 429                         break;
 430
 431                 src_node_size -= cur_size;
 432                 if (!src_node_size) {
 433                         ++src_mm;
 434                         src_node_size = src_mm->size << PAGE_SHIFT;
 435                         src_offset = 0;
 436                 } else {
 437                         src_offset += cur_size;
 438                 }
 439
 440                 dst_node_size -= cur_size;
 441                 if (!dst_node_size) {
 442                         ++dst_mm;
 443                         dst_node_size = dst_mm->size << PAGE_SHIFT;
 444                         dst_offset = 0;
 445                 } else {
 446                         dst_offset += cur_size;
 447                 }
 448         }
 449 error:
 450         mutex_unlock(&adev->mman.gtt_window_lock);
 451         if (f)
 452                 *f = dma_fence_get(fence);
 453         dma_fence_put(fence);
 454         return r;
 455 }
 456
 457 /**
 458  * amdgpu_move_blit - Copy an entire buffer to another buffer
 459  *
 460  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 461  * help move buffers to and from VRAM.
 462  */
 463 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 464                             bool evict,
 465                             struct ttm_resource *new_mem,
 466                             struct ttm_resource *old_mem)
 467 {
 468         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 469         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 470         struct amdgpu_copy_mem src, dst;
 471         struct dma_fence *fence = NULL;
 472         int r;
 473
 474         src.bo = bo;
 475         dst.bo = bo;
 476         src.mem = old_mem;
 477         dst.mem = new_mem;
 478         src.offset = 0;
 479         dst.offset = 0;
 480
 481         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 482                                        new_mem->num_pages << PAGE_SHIFT,
 483                                        amdgpu_bo_encrypted(abo),
 484                                        bo->base.resv, &fence);
 485         if (r)
 486                 goto error;
 487
 488         /* clear the space being freed */
 489         if (old_mem->mem_type == TTM_PL_VRAM &&
 490             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 491                 struct dma_fence *wipe_fence = NULL;
 492
 493                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 494                                        NULL, &wipe_fence);
 495                 if (r) {
 496                         goto error;
 497                 } else if (wipe_fence) {
 498                         dma_fence_put(fence);
 499                         fence = wipe_fence;
 500                 }
 501         }
 502
 503         /* Always block for VM page tables before committing the new location */
 504         if (bo->type == ttm_bo_type_kernel)
 505                 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 506         else
 507                 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 508         dma_fence_put(fence);
 509         return r;
 510
 511 error:
 512         if (fence)
 513                 dma_fence_wait(fence, false);
 514         dma_fence_put(fence);
 515         return r;
 516 }
 517
 518 /**
 519  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 520  *
 521  * Called by amdgpu_bo_move().
 522  */
 523 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 524                                 struct ttm_operation_ctx *ctx,
 525                                 struct ttm_resource *new_mem)
 526 {
 527         struct ttm_resource *old_mem = &bo->mem;
 528         struct ttm_resource tmp_mem;
 529         struct ttm_place placements;
 530         struct ttm_placement placement;
 531         int r;
 532
 533         /* create space/pages for new_mem in GTT space */
 534         tmp_mem = *new_mem;
 535         tmp_mem.mm_node = NULL;
 536         placement.num_placement = 1;
 537         placement.placement = &placements;
 538         placement.num_busy_placement = 1;
 539         placement.busy_placement = &placements;
 540         placements.fpfn = 0;
 541         placements.lpfn = 0;
 542         placements.mem_type = TTM_PL_TT;
 543         placements.flags = 0;
 544         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 545         if (unlikely(r)) {
 546                 pr_err("Failed to find GTT space for blit from VRAM\n");
 547                 return r;
 548         }
 549
 550         r = ttm_tt_populate(bo->bdev, bo->ttm, ctx);
 551         if (unlikely(r))
 552                 goto out_cleanup;
 553
 554         /* Bind the memory to the GTT space */
 555         r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, &tmp_mem);
 556         if (unlikely(r)) {
 557                 goto out_cleanup;
 558         }
 559
 560         /* blit VRAM to GTT */
 561         r = amdgpu_move_blit(bo, evict, &tmp_mem, old_mem);
 562         if (unlikely(r)) {
 563                 goto out_cleanup;
 564         }
 565
 566         r = ttm_bo_wait_ctx(bo, ctx);
 567         if (unlikely(r))
 568                 goto out_cleanup;
 569
 570         amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 571         ttm_resource_free(bo, &bo->mem);
 572         ttm_bo_assign_mem(bo, new_mem);
 573 out_cleanup:
 574         ttm_resource_free(bo, &tmp_mem);
 575         return r;
 576 }
 577
 578 /**
 579  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 580  *
 581  * Called by amdgpu_bo_move().
 582  */
 583 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 584                                 struct ttm_operation_ctx *ctx,
 585                                 struct ttm_resource *new_mem)
 586 {
 587         struct ttm_resource *old_mem = &bo->mem;
 588         struct ttm_resource tmp_mem;
 589         struct ttm_placement placement;
 590         struct ttm_place placements;
 591         int r;
 592
 593         /* make space in GTT for old_mem buffer */
 594         tmp_mem = *new_mem;
 595         tmp_mem.mm_node = NULL;
 596         placement.num_placement = 1;
 597         placement.placement = &placements;
 598         placement.num_busy_placement = 1;
 599         placement.busy_placement = &placements;
 600         placements.fpfn = 0;
 601         placements.lpfn = 0;
 602         placements.mem_type = TTM_PL_TT;
 603         placements.flags = 0;
 604         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 605         if (unlikely(r)) {
 606                 pr_err("Failed to find GTT space for blit to VRAM\n");
 607                 return r;
 608         }
 609
 610         /* move/bind old memory to GTT space */
 611         r = ttm_tt_populate(bo->bdev, bo->ttm, ctx);
 612         if (unlikely(r))
 613                 return r;
 614
 615         r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, &tmp_mem);
 616         if (unlikely(r)) {
 617                 goto out_cleanup;
 618         }
 619
 620         ttm_bo_assign_mem(bo, &tmp_mem);
 621         /* copy to VRAM */
 622         r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 623         if (unlikely(r)) {
 624                 goto out_cleanup;
 625         }
 626 out_cleanup:
 627         ttm_resource_free(bo, &tmp_mem);
 628         return r;
 629 }
 630
 631 /**
 632  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 633  *
 634  * Called by amdgpu_bo_move()
 635  */
 636 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 637                                struct ttm_resource *mem)
 638 {
 639         struct drm_mm_node *nodes = mem->mm_node;
 640
 641         if (mem->mem_type == TTM_PL_SYSTEM ||
 642             mem->mem_type == TTM_PL_TT)
 643                 return true;
 644         if (mem->mem_type != TTM_PL_VRAM)
 645                 return false;
 646
 647         /* ttm_resource_ioremap only supports contiguous memory */
 648         if (nodes->size != mem->num_pages)
 649                 return false;
 650
 651         return ((nodes->start + nodes->size) << PAGE_SHIFT)
 652                 <= adev->gmc.visible_vram_size;
 653 }
 654
 655 /**
 656  * amdgpu_bo_move - Move a buffer object to a new memory location
 657  *
 658  * Called by ttm_bo_handle_move_mem()
 659  */
 660 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 661                           struct ttm_operation_ctx *ctx,
 662                           struct ttm_resource *new_mem)
 663 {
 664         struct amdgpu_device *adev;
 665         struct amdgpu_bo *abo;
 666         struct ttm_resource *old_mem = &bo->mem;
 667         int r;
 668
 669         if (new_mem->mem_type == TTM_PL_TT) {
 670                 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 671                 if (r)
 672                         return r;
 673         }
 674
 675         amdgpu_bo_move_notify(bo, evict, new_mem);
 676
 677         /* Can't move a pinned BO */
 678         abo = ttm_to_amdgpu_bo(bo);
 679         if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
 680                 return -EINVAL;
 681
 682         adev = amdgpu_ttm_adev(bo->bdev);
 683
 684         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 685                 ttm_bo_move_null(bo, new_mem);
 686                 return 0;
 687         }
 688         if (old_mem->mem_type == TTM_PL_SYSTEM &&
 689             new_mem->mem_type == TTM_PL_TT) {
 690                 ttm_bo_move_null(bo, new_mem);
 691                 return 0;
 692         }
 693
 694         if (old_mem->mem_type == TTM_PL_TT &&
 695             new_mem->mem_type == TTM_PL_SYSTEM) {
 696                 r = ttm_bo_wait_ctx(bo, ctx);
 697                 if (r)
 698                         goto fail;
 699
 700                 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 701                 ttm_resource_free(bo, &bo->mem);
 702                 ttm_bo_assign_mem(bo, new_mem);
 703                 return 0;
 704         }
 705
 706         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 707             old_mem->mem_type == AMDGPU_PL_GWS ||
 708             old_mem->mem_type == AMDGPU_PL_OA ||
 709             new_mem->mem_type == AMDGPU_PL_GDS ||
 710             new_mem->mem_type == AMDGPU_PL_GWS ||
 711             new_mem->mem_type == AMDGPU_PL_OA) {
 712                 /* Nothing to save here */
 713                 ttm_bo_move_null(bo, new_mem);
 714                 return 0;
 715         }
 716
 717         if (!adev->mman.buffer_funcs_enabled) {
 718                 r = -ENODEV;
 719                 goto memcpy;
 720         }
 721
 722         if (old_mem->mem_type == TTM_PL_VRAM &&
 723             new_mem->mem_type == TTM_PL_SYSTEM) {
 724                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 725         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 726                    new_mem->mem_type == TTM_PL_VRAM) {
 727                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 728         } else {
 729                 r = amdgpu_move_blit(bo, evict,
 730                                      new_mem, old_mem);
 731         }
 732
 733         if (r) {
 734 memcpy:
 735                 /* Check that all memory is CPU accessible */
 736                 if (!amdgpu_mem_visible(adev, old_mem) ||
 737                     !amdgpu_mem_visible(adev, new_mem)) {
 738                         pr_err("Move buffer fallback to memcpy unavailable\n");
 739                         goto fail;
 740                 }
 741
 742                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 743                 if (r)
 744                         goto fail;
 745         }
 746
 747         if (bo->type == ttm_bo_type_device &&
 748             new_mem->mem_type == TTM_PL_VRAM &&
 749             old_mem->mem_type != TTM_PL_VRAM) {
 750                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 751                  * accesses the BO after it's moved.
 752                  */
 753                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 754         }
 755
 756         /* update statistics */
 757         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 758         return 0;
 759 fail:
 760         swap(*new_mem, bo->mem);
 761         amdgpu_bo_move_notify(bo, false, new_mem);
 762         swap(*new_mem, bo->mem);
 763         return r;
 764 }
 765
 766 /**
 767  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 768  *
 769  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 770  */
 771 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_resource *mem)
 772 {
 773         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 774         struct drm_mm_node *mm_node = mem->mm_node;
 775         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 776
 777         switch (mem->mem_type) {
 778         case TTM_PL_SYSTEM:
 779                 /* system memory */
 780                 return 0;
 781         case TTM_PL_TT:
 782                 break;
 783         case TTM_PL_VRAM:
 784                 mem->bus.offset = mem->start << PAGE_SHIFT;
 785                 /* check if it's visible */
 786                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 787                         return -EINVAL;
 788                 /* Only physically contiguous buffers apply. In a contiguous
 789                  * buffer, size of the first mm_node would match the number of
 790                  * pages in ttm_resource.
 791                  */
 792                 if (adev->mman.aper_base_kaddr &&
 793                     (mm_node->size == mem->num_pages))
 794                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 795                                         mem->bus.offset;
 796
 797                 mem->bus.offset += adev->gmc.aper_base;
 798                 mem->bus.is_iomem = true;
 799                 mem->bus.caching = ttm_write_combined;
 800                 break;
 801         default:
 802                 return -EINVAL;
 803         }
 804         return 0;
 805 }
 806
 807 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 808                                            unsigned long page_offset)
 809 {
 810         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 811         uint64_t offset = (page_offset << PAGE_SHIFT);
 812         struct drm_mm_node *mm;
 813
 814         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 815         offset += adev->gmc.aper_base;
 816         return mm->start + (offset >> PAGE_SHIFT);
 817 }
 818
 819 /**
 820  * amdgpu_ttm_domain_start - Returns GPU start address
 821  * @adev: amdgpu device object
 822  * @type: type of the memory
 823  *
 824  * Returns:
 825  * GPU start address of a memory domain
 826  */
 827
 828 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 829 {
 830         switch (type) {
 831         case TTM_PL_TT:
 832                 return adev->gmc.gart_start;
 833         case TTM_PL_VRAM:
 834                 return adev->gmc.vram_start;
 835         }
 836
 837         return 0;
 838 }
 839
 840 /*
 841  * TTM backend functions.
 842  */
 843 struct amdgpu_ttm_tt {
 844         struct ttm_dma_tt       ttm;
 845         struct drm_gem_object   *gobj;
 846         u64                     offset;
 847         uint64_t                userptr;
 848         struct task_struct      *usertask;
 849         uint32_t                userflags;
 850         bool                    bound;
 851 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 852         struct hmm_range        *range;
 853 #endif
 854 };
 855
 856 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 857 /**
 858  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 859  * memory and start HMM tracking CPU page table update
 860  *
 861  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 862  * once afterwards to stop HMM tracking
 863  */
 864 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 865 {
 866         struct ttm_tt *ttm = bo->tbo.ttm;
 867         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 868         unsigned long start = gtt->userptr;
 869         struct vm_area_struct *vma;
 870         struct hmm_range *range;
 871         unsigned long timeout;
 872         struct mm_struct *mm;
 873         unsigned long i;
 874         int r = 0;
 875
 876         mm = bo->notifier.mm;
 877         if (unlikely(!mm)) {
 878                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 879                 return -EFAULT;
 880         }
 881
 882         /* Another get_user_pages is running at the same time?? */
 883         if (WARN_ON(gtt->range))
 884                 return -EFAULT;
 885
 886         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 887                 return -ESRCH;
 888
 889         range = kzalloc(sizeof(*range), GFP_KERNEL);
 890         if (unlikely(!range)) {
 891                 r = -ENOMEM;
 892                 goto out;
 893         }
 894         range->notifier = &bo->notifier;
 895         range->start = bo->notifier.interval_tree.start;
 896         range->end = bo->notifier.interval_tree.last + 1;
 897         range->default_flags = HMM_PFN_REQ_FAULT;
 898         if (!amdgpu_ttm_tt_is_readonly(ttm))
 899                 range->default_flags |= HMM_PFN_REQ_WRITE;
 900
 901         range->hmm_pfns = kvmalloc_array(ttm->num_pages,
 902                                          sizeof(*range->hmm_pfns), GFP_KERNEL);
 903         if (unlikely(!range->hmm_pfns)) {
 904                 r = -ENOMEM;
 905                 goto out_free_ranges;
 906         }
 907
 908         mmap_read_lock(mm);
 909         vma = find_vma(mm, start);
 910         if (unlikely(!vma || start < vma->vm_start)) {
 911                 r = -EFAULT;
 912                 goto out_unlock;
 913         }
 914         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 915                 vma->vm_file)) {
 916                 r = -EPERM;
 917                 goto out_unlock;
 918         }
 919         mmap_read_unlock(mm);
 920         timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
 921
 922 retry:
 923         range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
 924
 925         mmap_read_lock(mm);
 926         r = hmm_range_fault(range);
 927         mmap_read_unlock(mm);
 928         if (unlikely(r)) {
 929                 /*
 930                  * FIXME: This timeout should encompass the retry from
 931                  * mmu_interval_read_retry() as well.
 932                  */
 933                 if (r == -EBUSY && !time_after(jiffies, timeout))
 934                         goto retry;
 935                 goto out_free_pfns;
 936         }
 937
 938         /*
 939          * Due to default_flags, all pages are HMM_PFN_VALID or
 940          * hmm_range_fault() fails. FIXME: The pages cannot be touched outside
 941          * the notifier_lock, and mmu_interval_read_retry() must be done first.
 942          */
 943         for (i = 0; i < ttm->num_pages; i++)
 944                 pages[i] = hmm_pfn_to_page(range->hmm_pfns[i]);
 945
 946         gtt->range = range;
 947         mmput(mm);
 948
 949         return 0;
 950
 951 out_unlock:
 952         mmap_read_unlock(mm);
 953 out_free_pfns:
 954         kvfree(range->hmm_pfns);
 955 out_free_ranges:
 956         kfree(range);
 957 out:
 958         mmput(mm);
 959         return r;
 960 }
 961
 962 /**
 963  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 964  * Check if the pages backing this ttm range have been invalidated
 965  *
 966  * Returns: true if pages are still valid
 967  */
 968 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 969 {
 970         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 971         bool r = false;
 972
 973         if (!gtt || !gtt->userptr)
 974                 return false;
 975
 976         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
 977                 gtt->userptr, ttm->num_pages);
 978
 979         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
 980                 "No user pages to check\n");
 981
 982         if (gtt->range) {
 983                 /*
 984                  * FIXME: Must always hold notifier_lock for this, and must
 985                  * not ignore the return code.
 986                  */
 987                 r = mmu_interval_read_retry(gtt->range->notifier,
 988                                          gtt->range->notifier_seq);
 989                 kvfree(gtt->range->hmm_pfns);
 990                 kfree(gtt->range);
 991                 gtt->range = NULL;
 992         }
 993
 994         return !r;
 995 }
 996 #endif
 997
 998 /**
 999  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
1000  *
1001  * Called by amdgpu_cs_list_validate(). This creates the page list
1002  * that backs user memory and will ultimately be mapped into the device
1003  * address space.
1004  */
1005 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
1006 {
1007         unsigned long i;
1008
1009         for (i = 0; i < ttm->num_pages; ++i)
1010                 ttm->pages[i] = pages ? pages[i] : NULL;
1011 }
1012
1013 /**
1014  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
1015  *
1016  * Called by amdgpu_ttm_backend_bind()
1017  **/
1018 static int amdgpu_ttm_tt_pin_userptr(struct ttm_bo_device *bdev,
1019                                      struct ttm_tt *ttm)
1020 {
1021         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1022         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1023         int r;
1024
1025         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1026         enum dma_data_direction direction = write ?
1027                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1028
1029         /* Allocate an SG array and squash pages into it */
1030         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
1031                                       ttm->num_pages << PAGE_SHIFT,
1032                                       GFP_KERNEL);
1033         if (r)
1034                 goto release_sg;
1035
1036         /* Map SG to device */
1037         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
1038         if (r)
1039                 goto release_sg;
1040
1041         /* convert SG to linear array of pages and dma addresses */
1042         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1043                                          gtt->ttm.dma_address, ttm->num_pages);
1044
1045         return 0;
1046
1047 release_sg:
1048         kfree(ttm->sg);
1049         return r;
1050 }
1051
1052 /**
1053  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
1054  */
1055 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_bo_device *bdev,
1056                                         struct ttm_tt *ttm)
1057 {
1058         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1059         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1060
1061         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1062         enum dma_data_direction direction = write ?
1063                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1064
1065         /* double check that we don't free the table twice */
1066         if (!ttm->sg->sgl)
1067                 return;
1068
1069         /* unmap the pages mapped to the device */
1070         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
1071         sg_free_table(ttm->sg);
1072
1073 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1074         if (gtt->range) {
1075                 unsigned long i;
1076
1077                 for (i = 0; i < ttm->num_pages; i++) {
1078                         if (ttm->pages[i] !=
1079                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
1080                                 break;
1081                 }
1082
1083                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1084         }
1085 #endif
1086 }
1087
1088 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1089                                 struct ttm_buffer_object *tbo,
1090                                 uint64_t flags)
1091 {
1092         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1093         struct ttm_tt *ttm = tbo->ttm;
1094         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1095         int r;
1096
1097         if (amdgpu_bo_encrypted(abo))
1098                 flags |= AMDGPU_PTE_TMZ;
1099
1100         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
1101                 uint64_t page_idx = 1;
1102
1103                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1104                                 ttm->pages, gtt->ttm.dma_address, flags);
1105                 if (r)
1106                         goto gart_bind_fail;
1107
1108                 /* The memory type of the first page defaults to UC. Now
1109                  * modify the memory type to NC from the second page of
1110                  * the BO onward.
1111                  */
1112                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1113                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1114
1115                 r = amdgpu_gart_bind(adev,
1116                                 gtt->offset + (page_idx << PAGE_SHIFT),
1117                                 ttm->num_pages - page_idx,
1118                                 &ttm->pages[page_idx],
1119                                 &(gtt->ttm.dma_address[page_idx]), flags);
1120         } else {
1121                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1122                                      ttm->pages, gtt->ttm.dma_address, flags);
1123         }
1124
1125 gart_bind_fail:
1126         if (r)
1127                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1128                           ttm->num_pages, gtt->offset);
1129
1130         return r;
1131 }
1132
1133 /**
1134  * amdgpu_ttm_backend_bind - Bind GTT memory
1135  *
1136  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1137  * This handles binding GTT memory to the device address space.
1138  */
1139 static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
1140                                    struct ttm_tt *ttm,
1141                                    struct ttm_resource *bo_mem)
1142 {
1143         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1144         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1145         uint64_t flags;
1146         int r = 0;
1147
1148         if (!bo_mem)
1149                 return -EINVAL;
1150
1151         if (gtt->bound)
1152                 return 0;
1153
1154         if (gtt->userptr) {
1155                 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
1156                 if (r) {
1157                         DRM_ERROR("failed to pin userptr\n");
1158                         return r;
1159                 }
1160         }
1161         if (!ttm->num_pages) {
1162                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1163                      ttm->num_pages, bo_mem, ttm);
1164         }
1165
1166         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1167             bo_mem->mem_type == AMDGPU_PL_GWS ||
1168             bo_mem->mem_type == AMDGPU_PL_OA)
1169                 return -EINVAL;
1170
1171         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1172                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1173                 return 0;
1174         }
1175
1176         /* compute PTE flags relevant to this BO memory */
1177         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1178
1179         /* bind pages into GART page tables */
1180         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1181         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1182                 ttm->pages, gtt->ttm.dma_address, flags);
1183
1184         if (r)
1185                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1186                           ttm->num_pages, gtt->offset);
1187         gtt->bound = true;
1188         return r;
1189 }
1190
1191 /**
1192  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1193  */
1194 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1195 {
1196         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1197         struct ttm_operation_ctx ctx = { false, false };
1198         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1199         struct ttm_resource tmp;
1200         struct ttm_placement placement;
1201         struct ttm_place placements;
1202         uint64_t addr, flags;
1203         int r;
1204
1205         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1206                 return 0;
1207
1208         addr = amdgpu_gmc_agp_addr(bo);
1209         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1210                 bo->mem.start = addr >> PAGE_SHIFT;
1211         } else {
1212
1213                 /* allocate GART space */
1214                 tmp = bo->mem;
1215                 tmp.mm_node = NULL;
1216                 placement.num_placement = 1;
1217                 placement.placement = &placements;
1218                 placement.num_busy_placement = 1;
1219                 placement.busy_placement = &placements;
1220                 placements.fpfn = 0;
1221                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1222                 placements.mem_type = TTM_PL_TT;
1223                 placements.flags = bo->mem.placement;
1224
1225                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1226                 if (unlikely(r))
1227                         return r;
1228
1229                 /* compute PTE flags for this buffer object */
1230                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1231
1232                 /* Bind pages */
1233                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1234                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1235                 if (unlikely(r)) {
1236                         ttm_resource_free(bo, &tmp);
1237                         return r;
1238                 }
1239
1240                 ttm_resource_free(bo, &bo->mem);
1241                 bo->mem = tmp;
1242         }
1243
1244         return 0;
1245 }
1246
1247 /**
1248  * amdgpu_ttm_recover_gart - Rebind GTT pages
1249  *
1250  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1251  * rebind GTT pages during a GPU reset.
1252  */
1253 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1254 {
1255         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1256         uint64_t flags;
1257         int r;
1258
1259         if (!tbo->ttm)
1260                 return 0;
1261
1262         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1263         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1264
1265         return r;
1266 }
1267
1268 /**
1269  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1270  *
1271  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1272  * ttm_tt_destroy().
1273  */
1274 static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
1275                                       struct ttm_tt *ttm)
1276 {
1277         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1278         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1279         int r;
1280
1281         if (!gtt->bound)
1282                 return;
1283
1284         /* if the pages have userptr pinning then clear that first */
1285         if (gtt->userptr)
1286                 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1287
1288         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1289                 return;
1290
1291         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1292         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1293         if (r)
1294                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1295                           gtt->ttm.ttm.num_pages, gtt->offset);
1296         gtt->bound = false;
1297 }
1298
1299 static void amdgpu_ttm_backend_destroy(struct ttm_bo_device *bdev,
1300                                        struct ttm_tt *ttm)
1301 {
1302         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1303
1304         amdgpu_ttm_backend_unbind(bdev, ttm);
1305         ttm_tt_destroy_common(bdev, ttm);
1306         if (gtt->usertask)
1307                 put_task_struct(gtt->usertask);
1308
1309         ttm_dma_tt_fini(&gtt->ttm);
1310         kfree(gtt);
1311 }
1312
1313 /**
1314  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1315  *
1316  * @bo: The buffer object to create a GTT ttm_tt object around
1317  *
1318  * Called by ttm_tt_create().
1319  */
1320 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1321                                            uint32_t page_flags)
1322 {
1323         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1324         struct amdgpu_ttm_tt *gtt;
1325         enum ttm_caching caching;
1326
1327         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1328         if (gtt == NULL) {
1329                 return NULL;
1330         }
1331         gtt->gobj = &bo->base;
1332
1333         if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1334                 caching = ttm_write_combined;
1335         else
1336                 caching = ttm_cached;
1337
1338         /* allocate space for the uninitialized page entries */
1339         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1340                 kfree(gtt);
1341                 return NULL;
1342         }
1343         return &gtt->ttm.ttm;
1344 }
1345
1346 /**
1347  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1348  *
1349  * Map the pages of a ttm_tt object to an address space visible
1350  * to the underlying device.
1351  */
1352 static int amdgpu_ttm_tt_populate(struct ttm_bo_device *bdev,
1353                                   struct ttm_tt *ttm,
1354                                   struct ttm_operation_ctx *ctx)
1355 {
1356         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1357         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1358
1359         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1360         if (gtt && gtt->userptr) {
1361                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1362                 if (!ttm->sg)
1363                         return -ENOMEM;
1364
1365                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1366                 ttm_tt_set_populated(ttm);
1367                 return 0;
1368         }
1369
1370         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1371                 if (!ttm->sg) {
1372                         struct dma_buf_attachment *attach;
1373                         struct sg_table *sgt;
1374
1375                         attach = gtt->gobj->import_attach;
1376                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1377                         if (IS_ERR(sgt))
1378                                 return PTR_ERR(sgt);
1379
1380                         ttm->sg = sgt;
1381                 }
1382
1383                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1384                                                  gtt->ttm.dma_address,
1385                                                  ttm->num_pages);
1386                 ttm_tt_set_populated(ttm);
1387                 return 0;
1388         }
1389
1390 #ifdef CONFIG_SWIOTLB
1391         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1392                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1393         }
1394 #endif
1395
1396         /* fall back to generic helper to populate the page array
1397          * and map them to the device */
1398         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1399 }
1400
1401 /**
1402  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1403  *
1404  * Unmaps pages of a ttm_tt object from the device address space and
1405  * unpopulates the page array backing it.
1406  */
1407 static void amdgpu_ttm_tt_unpopulate(struct ttm_bo_device *bdev, struct ttm_tt *ttm)
1408 {
1409         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1410         struct amdgpu_device *adev;
1411
1412         if (gtt && gtt->userptr) {
1413                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1414                 kfree(ttm->sg);
1415                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1416                 return;
1417         }
1418
1419         if (ttm->sg && gtt->gobj->import_attach) {
1420                 struct dma_buf_attachment *attach;
1421
1422                 attach = gtt->gobj->import_attach;
1423                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1424                 ttm->sg = NULL;
1425                 return;
1426         }
1427
1428         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1429                 return;
1430
1431         adev = amdgpu_ttm_adev(bdev);
1432
1433 #ifdef CONFIG_SWIOTLB
1434         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1435                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1436                 return;
1437         }
1438 #endif
1439
1440         /* fall back to generic helper to unmap and unpopulate array */
1441         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1442 }
1443
1444 /**
1445  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1446  * task
1447  *
1448  * @bo: The ttm_buffer_object to bind this userptr to
1449  * @addr:  The address in the current tasks VM space to use
1450  * @flags: Requirements of userptr object.
1451  *
1452  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1453  * to current task
1454  */
1455 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1456                               uint64_t addr, uint32_t flags)
1457 {
1458         struct amdgpu_ttm_tt *gtt;
1459
1460         if (!bo->ttm) {
1461                 /* TODO: We want a separate TTM object type for userptrs */
1462                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1463                 if (bo->ttm == NULL)
1464                         return -ENOMEM;
1465         }
1466
1467         gtt = (void*)bo->ttm;
1468         gtt->userptr = addr;
1469         gtt->userflags = flags;
1470
1471         if (gtt->usertask)
1472                 put_task_struct(gtt->usertask);
1473         gtt->usertask = current->group_leader;
1474         get_task_struct(gtt->usertask);
1475
1476         return 0;
1477 }
1478
1479 /**
1480  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1481  */
1482 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1483 {
1484         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1485
1486         if (gtt == NULL)
1487                 return NULL;
1488
1489         if (gtt->usertask == NULL)
1490                 return NULL;
1491
1492         return gtt->usertask->mm;
1493 }
1494
1495 /**
1496  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1497  * address range for the current task.
1498  *
1499  */
1500 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1501                                   unsigned long end)
1502 {
1503         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1504         unsigned long size;
1505
1506         if (gtt == NULL || !gtt->userptr)
1507                 return false;
1508
1509         /* Return false if no part of the ttm_tt object lies within
1510          * the range
1511          */
1512         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1513         if (gtt->userptr > end || gtt->userptr + size <= start)
1514                 return false;
1515
1516         return true;
1517 }
1518
1519 /**
1520  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1521  */
1522 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1523 {
1524         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1525
1526         if (gtt == NULL || !gtt->userptr)
1527                 return false;
1528
1529         return true;
1530 }
1531
1532 /**
1533  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1534  */
1535 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1536 {
1537         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1538
1539         if (gtt == NULL)
1540                 return false;
1541
1542         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1543 }
1544
1545 /**
1546  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1547  *
1548  * @ttm: The ttm_tt object to compute the flags for
1549  * @mem: The memory registry backing this ttm_tt object
1550  *
1551  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1552  */
1553 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1554 {
1555         uint64_t flags = 0;
1556
1557         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1558                 flags |= AMDGPU_PTE_VALID;
1559
1560         if (mem && mem->mem_type == TTM_PL_TT) {
1561                 flags |= AMDGPU_PTE_SYSTEM;
1562
1563                 if (ttm->caching == ttm_cached)
1564                         flags |= AMDGPU_PTE_SNOOPED;
1565         }
1566
1567         return flags;
1568 }
1569
1570 /**
1571  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1572  *
1573  * @ttm: The ttm_tt object to compute the flags for
1574  * @mem: The memory registry backing this ttm_tt object
1575
1576  * Figure out the flags to use for a VM PTE (Page Table Entry).
1577  */
1578 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1579                                  struct ttm_resource *mem)
1580 {
1581         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1582
1583         flags |= adev->gart.gart_pte_flags;
1584         flags |= AMDGPU_PTE_READABLE;
1585
1586         if (!amdgpu_ttm_tt_is_readonly(ttm))
1587                 flags |= AMDGPU_PTE_WRITEABLE;
1588
1589         return flags;
1590 }
1591
1592 /**
1593  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1594  * object.
1595  *
1596  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1597  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1598  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1599  * used to clean out a memory space.
1600  */
1601 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1602                                             const struct ttm_place *place)
1603 {
1604         unsigned long num_pages = bo->mem.num_pages;
1605         struct drm_mm_node *node = bo->mem.mm_node;
1606         struct dma_resv_list *flist;
1607         struct dma_fence *f;
1608         int i;
1609
1610         if (bo->type == ttm_bo_type_kernel &&
1611             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1612                 return false;
1613
1614         /* If bo is a KFD BO, check if the bo belongs to the current process.
1615          * If true, then return false as any KFD process needs all its BOs to
1616          * be resident to run successfully
1617          */
1618         flist = dma_resv_get_list(bo->base.resv);
1619         if (flist) {
1620                 for (i = 0; i < flist->shared_count; ++i) {
1621                         f = rcu_dereference_protected(flist->shared[i],
1622                                 dma_resv_held(bo->base.resv));
1623                         if (amdkfd_fence_check_mm(f, current->mm))
1624                                 return false;
1625                 }
1626         }
1627
1628         switch (bo->mem.mem_type) {
1629         case TTM_PL_TT:
1630                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1631                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1632                         return false;
1633                 return true;
1634
1635         case TTM_PL_VRAM:
1636                 /* Check each drm MM node individually */
1637                 while (num_pages) {
1638                         if (place->fpfn < (node->start + node->size) &&
1639                             !(place->lpfn && place->lpfn <= node->start))
1640                                 return true;
1641
1642                         num_pages -= node->size;
1643                         ++node;
1644                 }
1645                 return false;
1646
1647         default:
1648                 break;
1649         }
1650
1651         return ttm_bo_eviction_valuable(bo, place);
1652 }
1653
1654 /**
1655  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1656  *
1657  * @bo:  The buffer object to read/write
1658  * @offset:  Offset into buffer object
1659  * @buf:  Secondary buffer to write/read from
1660  * @len: Length in bytes of access
1661  * @write:  true if writing
1662  *
1663  * This is used to access VRAM that backs a buffer object via MMIO
1664  * access for debugging purposes.
1665  */
1666 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1667                                     unsigned long offset,
1668                                     void *buf, int len, int write)
1669 {
1670         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1671         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1672         struct drm_mm_node *nodes;
1673         uint32_t value = 0;
1674         int ret = 0;
1675         uint64_t pos;
1676         unsigned long flags;
1677
1678         if (bo->mem.mem_type != TTM_PL_VRAM)
1679                 return -EIO;
1680
1681         pos = offset;
1682         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &pos);
1683         pos += (nodes->start << PAGE_SHIFT);
1684
1685         while (len && pos < adev->gmc.mc_vram_size) {
1686                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1687                 uint64_t bytes = 4 - (pos & 3);
1688                 uint32_t shift = (pos & 3) * 8;
1689                 uint32_t mask = 0xffffffff << shift;
1690
1691                 if (len < bytes) {
1692                         mask &= 0xffffffff >> (bytes - len) * 8;
1693                         bytes = len;
1694                 }
1695
1696                 if (mask != 0xffffffff) {
1697                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1698                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1699                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1700                         if (!write || mask != 0xffffffff)
1701                                 value = RREG32_NO_KIQ(mmMM_DATA);
1702                         if (write) {
1703                                 value &= ~mask;
1704                                 value |= (*(uint32_t *)buf << shift) & mask;
1705                                 WREG32_NO_KIQ(mmMM_DATA, value);
1706                         }
1707                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1708                         if (!write) {
1709                                 value = (value & mask) >> shift;
1710                                 memcpy(buf, &value, bytes);
1711                         }
1712                 } else {
1713                         bytes = (nodes->start + nodes->size) << PAGE_SHIFT;
1714                         bytes = min(bytes - pos, (uint64_t)len & ~0x3ull);
1715
1716                         amdgpu_device_vram_access(adev, pos, (uint32_t *)buf,
1717                                                   bytes, write);
1718                 }
1719
1720                 ret += bytes;
1721                 buf = (uint8_t *)buf + bytes;
1722                 pos += bytes;
1723                 len -= bytes;
1724                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1725                         ++nodes;
1726                         pos = (nodes->start << PAGE_SHIFT);
1727                 }
1728         }
1729
1730         return ret;
1731 }
1732
1733 static struct ttm_bo_driver amdgpu_bo_driver = {
1734         .ttm_tt_create = &amdgpu_ttm_tt_create,
1735         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1736         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1737         .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1738         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1739         .evict_flags = &amdgpu_evict_flags,
1740         .move = &amdgpu_bo_move,
1741         .verify_access = &amdgpu_verify_access,
1742         .move_notify = &amdgpu_bo_move_notify,
1743         .release_notify = &amdgpu_bo_release_notify,
1744         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1745         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1746         .access_memory = &amdgpu_ttm_access_memory,
1747         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1748 };
1749
1750 /*
1751  * Firmware Reservation functions
1752  */
1753 /**
1754  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1755  *
1756  * @adev: amdgpu_device pointer
1757  *
1758  * free fw reserved vram if it has been reserved.
1759  */
1760 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1761 {
1762         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1763                 NULL, &adev->mman.fw_vram_usage_va);
1764 }
1765
1766 /**
1767  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1768  *
1769  * @adev: amdgpu_device pointer
1770  *
1771  * create bo vram reservation from fw.
1772  */
1773 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1774 {
1775         uint64_t vram_size = adev->gmc.visible_vram_size;
1776
1777         adev->mman.fw_vram_usage_va = NULL;
1778         adev->mman.fw_vram_usage_reserved_bo = NULL;
1779
1780         if (adev->mman.fw_vram_usage_size == 0 ||
1781             adev->mman.fw_vram_usage_size > vram_size)
1782                 return 0;
1783
1784         return amdgpu_bo_create_kernel_at(adev,
1785                                           adev->mman.fw_vram_usage_start_offset,
1786                                           adev->mman.fw_vram_usage_size,
1787                                           AMDGPU_GEM_DOMAIN_VRAM,
1788                                           &adev->mman.fw_vram_usage_reserved_bo,
1789                                           &adev->mman.fw_vram_usage_va);
1790 }
1791
1792 /*
1793  * Memoy training reservation functions
1794  */
1795
1796 /**
1797  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1798  *
1799  * @adev: amdgpu_device pointer
1800  *
1801  * free memory training reserved vram if it has been reserved.
1802  */
1803 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1804 {
1805         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1806
1807         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1808         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1809         ctx->c2p_bo = NULL;
1810
1811         return 0;
1812 }
1813
1814 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1815 {
1816         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1817
1818         memset(ctx, 0, sizeof(*ctx));
1819
1820         ctx->c2p_train_data_offset =
1821                 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1822         ctx->p2c_train_data_offset =
1823                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1824         ctx->train_data_size =
1825                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1826
1827         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1828                         ctx->train_data_size,
1829                         ctx->p2c_train_data_offset,
1830                         ctx->c2p_train_data_offset);
1831 }
1832
1833 /*
1834  * reserve TMR memory at the top of VRAM which holds
1835  * IP Discovery data and is protected by PSP.
1836  */
1837 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1838 {
1839         int ret;
1840         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1841         bool mem_train_support = false;
1842
1843         if (!amdgpu_sriov_vf(adev)) {
1844                 ret = amdgpu_mem_train_support(adev);
1845                 if (ret == 1)
1846                         mem_train_support = true;
1847                 else if (ret == -1)
1848                         return -EINVAL;
1849                 else
1850                         DRM_DEBUG("memory training does not support!\n");
1851         }
1852
1853         /*
1854          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1855          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1856          *
1857          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1858          * discovery data and G6 memory training data respectively
1859          */
1860         adev->mman.discovery_tmr_size =
1861                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1862         if (!adev->mman.discovery_tmr_size)
1863                 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1864
1865         if (mem_train_support) {
1866                 /* reserve vram for mem train according to TMR location */
1867                 amdgpu_ttm_training_data_block_init(adev);
1868                 ret = amdgpu_bo_create_kernel_at(adev,
1869                                          ctx->c2p_train_data_offset,
1870                                          ctx->train_data_size,
1871                                          AMDGPU_GEM_DOMAIN_VRAM,
1872                                          &ctx->c2p_bo,
1873                                          NULL);
1874                 if (ret) {
1875                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1876                         amdgpu_ttm_training_reserve_vram_fini(adev);
1877                         return ret;
1878                 }
1879                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1880         }
1881
1882         ret = amdgpu_bo_create_kernel_at(adev,
1883                                 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1884                                 adev->mman.discovery_tmr_size,
1885                                 AMDGPU_GEM_DOMAIN_VRAM,
1886                                 &adev->mman.discovery_memory,
1887                                 NULL);
1888         if (ret) {
1889                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1890                 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1891                 return ret;
1892         }
1893
1894         return 0;
1895 }
1896
1897 /**
1898  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1899  * gtt/vram related fields.
1900  *
1901  * This initializes all of the memory space pools that the TTM layer
1902  * will need such as the GTT space (system memory mapped to the device),
1903  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1904  * can be mapped per VMID.
1905  */
1906 int amdgpu_ttm_init(struct amdgpu_device *adev)
1907 {
1908         uint64_t gtt_size;
1909         int r;
1910         u64 vis_vram_limit;
1911
1912         mutex_init(&adev->mman.gtt_window_lock);
1913
1914         /* No others user of address space so set it to 0 */
1915         r = ttm_bo_device_init(&adev->mman.bdev,
1916                                &amdgpu_bo_driver,
1917                                adev_to_drm(adev)->anon_inode->i_mapping,
1918                                adev_to_drm(adev)->vma_offset_manager,
1919                                dma_addressing_limited(adev->dev));
1920         if (r) {
1921                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1922                 return r;
1923         }
1924         adev->mman.initialized = true;
1925
1926         /* We opt to avoid OOM on system pages allocations */
1927         adev->mman.bdev.no_retry = true;
1928
1929         /* Initialize VRAM pool with all of VRAM divided into pages */
1930         r = amdgpu_vram_mgr_init(adev);
1931         if (r) {
1932                 DRM_ERROR("Failed initializing VRAM heap.\n");
1933                 return r;
1934         }
1935
1936         /* Reduce size of CPU-visible VRAM if requested */
1937         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1938         if (amdgpu_vis_vram_limit > 0 &&
1939             vis_vram_limit <= adev->gmc.visible_vram_size)
1940                 adev->gmc.visible_vram_size = vis_vram_limit;
1941
1942         /* Change the size here instead of the init above so only lpfn is affected */
1943         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1944 #ifdef CONFIG_64BIT
1945         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1946                                                 adev->gmc.visible_vram_size);
1947 #endif
1948
1949         /*
1950          *The reserved vram for firmware must be pinned to the specified
1951          *place on the VRAM, so reserve it early.
1952          */
1953         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1954         if (r) {
1955                 return r;
1956         }
1957
1958         /*
1959          * only NAVI10 and onwards ASIC support for IP discovery.
1960          * If IP discovery enabled, a block of memory should be
1961          * reserved for IP discovey.
1962          */
1963         if (adev->mman.discovery_bin) {
1964                 r = amdgpu_ttm_reserve_tmr(adev);
1965                 if (r)
1966                         return r;
1967         }
1968
1969         /* allocate memory as required for VGA
1970          * This is used for VGA emulation and pre-OS scanout buffers to
1971          * avoid display artifacts while transitioning between pre-OS
1972          * and driver.  */
1973         r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1974                                        AMDGPU_GEM_DOMAIN_VRAM,
1975                                        &adev->mman.stolen_vga_memory,
1976                                        NULL);
1977         if (r)
1978                 return r;
1979         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1980                                        adev->mman.stolen_extended_size,
1981                                        AMDGPU_GEM_DOMAIN_VRAM,
1982                                        &adev->mman.stolen_extended_memory,
1983                                        NULL);
1984         if (r)
1985                 return r;
1986
1987         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1988                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1989
1990         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1991          * or whatever the user passed on module init */
1992         if (amdgpu_gtt_size == -1) {
1993                 struct sysinfo si;
1994
1995                 si_meminfo(&si);
1996                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1997                                adev->gmc.mc_vram_size),
1998                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1999         }
2000         else
2001                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
2002
2003         /* Initialize GTT memory pool */
2004         r = amdgpu_gtt_mgr_init(adev, gtt_size);
2005         if (r) {
2006                 DRM_ERROR("Failed initializing GTT heap.\n");
2007                 return r;
2008         }
2009         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
2010                  (unsigned)(gtt_size / (1024 * 1024)));
2011
2012         /* Initialize various on-chip memory pools */
2013         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
2014         if (r) {
2015                 DRM_ERROR("Failed initializing GDS heap.\n");
2016                 return r;
2017         }
2018
2019         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
2020         if (r) {
2021                 DRM_ERROR("Failed initializing gws heap.\n");
2022                 return r;
2023         }
2024
2025         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
2026         if (r) {
2027                 DRM_ERROR("Failed initializing oa heap.\n");
2028                 return r;
2029         }
2030
2031         return 0;
2032 }
2033
2034 /**
2035  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
2036  */
2037 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
2038 {
2039         /* return the VGA stolen memory (if any) back to VRAM */
2040         if (!adev->mman.keep_stolen_vga_memory)
2041                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2042         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
2043 }
2044
2045 /**
2046  * amdgpu_ttm_fini - De-initialize the TTM memory pools
2047  */
2048 void amdgpu_ttm_fini(struct amdgpu_device *adev)
2049 {
2050         if (!adev->mman.initialized)
2051                 return;
2052
2053         amdgpu_ttm_training_reserve_vram_fini(adev);
2054         /* return the stolen vga memory back to VRAM */
2055         if (adev->mman.keep_stolen_vga_memory)
2056                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2057         /* return the IP Discovery TMR memory back to VRAM */
2058         amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
2059         amdgpu_ttm_fw_reserve_vram_fini(adev);
2060
2061         if (adev->mman.aper_base_kaddr)
2062                 iounmap(adev->mman.aper_base_kaddr);
2063         adev->mman.aper_base_kaddr = NULL;
2064
2065         amdgpu_vram_mgr_fini(adev);
2066         amdgpu_gtt_mgr_fini(adev);
2067         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
2068         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
2069         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
2070         ttm_bo_device_release(&adev->mman.bdev);
2071         adev->mman.initialized = false;
2072         DRM_INFO("amdgpu: ttm finalized\n");
2073 }
2074
2075 /**
2076  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2077  *
2078  * @adev: amdgpu_device pointer
2079  * @enable: true when we can use buffer functions.
2080  *
2081  * Enable/disable use of buffer functions during suspend/resume. This should
2082  * only be called at bootup or when userspace isn't running.
2083  */
2084 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2085 {
2086         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
2087         uint64_t size;
2088         int r;
2089
2090         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
2091             adev->mman.buffer_funcs_enabled == enable)
2092                 return;
2093
2094         if (enable) {
2095                 struct amdgpu_ring *ring;
2096                 struct drm_gpu_scheduler *sched;
2097
2098                 ring = adev->mman.buffer_funcs_ring;
2099                 sched = &ring->sched;
2100                 r = drm_sched_entity_init(&adev->mman.entity,
2101                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
2102                                           1, NULL);
2103                 if (r) {
2104                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2105                                   r);
2106                         return;
2107                 }
2108         } else {
2109                 drm_sched_entity_destroy(&adev->mman.entity);
2110                 dma_fence_put(man->move);
2111                 man->move = NULL;
2112         }
2113
2114         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2115         if (enable)
2116                 size = adev->gmc.real_vram_size;
2117         else
2118                 size = adev->gmc.visible_vram_size;
2119         man->size = size >> PAGE_SHIFT;
2120         adev->mman.buffer_funcs_enabled = enable;
2121 }
2122
2123 static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf)
2124 {
2125         struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
2126         vm_fault_t ret;
2127
2128         ret = ttm_bo_vm_reserve(bo, vmf);
2129         if (ret)
2130                 return ret;
2131
2132         ret = amdgpu_bo_fault_reserve_notify(bo);
2133         if (ret)
2134                 goto unlock;
2135
2136         ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
2137                                        TTM_BO_VM_NUM_PREFAULT, 1);
2138         if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
2139                 return ret;
2140
2141 unlock:
2142         dma_resv_unlock(bo->base.resv);
2143         return ret;
2144 }
2145
2146 static struct vm_operations_struct amdgpu_ttm_vm_ops = {
2147         .fault = amdgpu_ttm_fault,
2148         .open = ttm_bo_vm_open,
2149         .close = ttm_bo_vm_close,
2150         .access = ttm_bo_vm_access
2151 };
2152
2153 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2154 {
2155         struct drm_file *file_priv = filp->private_data;
2156         struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);
2157         int r;
2158
2159         r = ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2160         if (unlikely(r != 0))
2161                 return r;
2162
2163         vma->vm_ops = &amdgpu_ttm_vm_ops;
2164         return 0;
2165 }
2166
2167 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2168                        uint64_t dst_offset, uint32_t byte_count,
2169                        struct dma_resv *resv,
2170                        struct dma_fence **fence, bool direct_submit,
2171                        bool vm_needs_flush, bool tmz)
2172 {
2173         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
2174                 AMDGPU_IB_POOL_DELAYED;
2175         struct amdgpu_device *adev = ring->adev;
2176         struct amdgpu_job *job;
2177
2178         uint32_t max_bytes;
2179         unsigned num_loops, num_dw;
2180         unsigned i;
2181         int r;
2182
2183         if (direct_submit && !ring->sched.ready) {
2184                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2185                 return -EINVAL;
2186         }
2187
2188         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2189         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2190         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2191
2192         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2193         if (r)
2194                 return r;
2195
2196         if (vm_needs_flush) {
2197                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2198                 job->vm_needs_flush = true;
2199         }
2200         if (resv) {
2201                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2202                                      AMDGPU_SYNC_ALWAYS,
2203                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2204                 if (r) {
2205                         DRM_ERROR("sync failed (%d).\n", r);
2206                         goto error_free;
2207                 }
2208         }
2209
2210         for (i = 0; i < num_loops; i++) {
2211                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2212
2213                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2214                                         dst_offset, cur_size_in_bytes, tmz);
2215
2216                 src_offset += cur_size_in_bytes;
2217                 dst_offset += cur_size_in_bytes;
2218                 byte_count -= cur_size_in_bytes;
2219         }
2220
2221         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2222         WARN_ON(job->ibs[0].length_dw > num_dw);
2223         if (direct_submit)
2224                 r = amdgpu_job_submit_direct(job, ring, fence);
2225         else
2226                 r = amdgpu_job_submit(job, &adev->mman.entity,
2227                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2228         if (r)
2229                 goto error_free;
2230
2231         return r;
2232
2233 error_free:
2234         amdgpu_job_free(job);
2235         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2236         return r;
2237 }
2238
2239 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2240                        uint32_t src_data,
2241                        struct dma_resv *resv,
2242                        struct dma_fence **fence)
2243 {
2244         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2245         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2246         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2247
2248         struct drm_mm_node *mm_node;
2249         unsigned long num_pages;
2250         unsigned int num_loops, num_dw;
2251
2252         struct amdgpu_job *job;
2253         int r;
2254
2255         if (!adev->mman.buffer_funcs_enabled) {
2256                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2257                 return -EINVAL;
2258         }
2259
2260         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2261                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2262                 if (r)
2263                         return r;
2264         }
2265
2266         num_pages = bo->tbo.num_pages;
2267         mm_node = bo->tbo.mem.mm_node;
2268         num_loops = 0;
2269         while (num_pages) {
2270                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2271
2272                 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2273                 num_pages -= mm_node->size;
2274                 ++mm_node;
2275         }
2276         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2277
2278         /* for IB padding */
2279         num_dw += 64;
2280
2281         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2282                                      &job);
2283         if (r)
2284                 return r;
2285
2286         if (resv) {
2287                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2288                                      AMDGPU_SYNC_ALWAYS,
2289                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2290                 if (r) {
2291                         DRM_ERROR("sync failed (%d).\n", r);
2292                         goto error_free;
2293                 }
2294         }
2295
2296         num_pages = bo->tbo.num_pages;
2297         mm_node = bo->tbo.mem.mm_node;
2298
2299         while (num_pages) {
2300                 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2301                 uint64_t dst_addr;
2302
2303                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2304                 while (byte_count) {
2305                         uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2306                                                            max_bytes);
2307
2308                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2309                                                 dst_addr, cur_size_in_bytes);
2310
2311                         dst_addr += cur_size_in_bytes;
2312                         byte_count -= cur_size_in_bytes;
2313                 }
2314
2315                 num_pages -= mm_node->size;
2316                 ++mm_node;
2317         }
2318
2319         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2320         WARN_ON(job->ibs[0].length_dw > num_dw);
2321         r = amdgpu_job_submit(job, &adev->mman.entity,
2322                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2323         if (r)
2324                 goto error_free;
2325
2326         return 0;
2327
2328 error_free:
2329         amdgpu_job_free(job);
2330         return r;
2331 }
2332
2333 #if defined(CONFIG_DEBUG_FS)
2334
2335 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2336 {
2337         struct drm_info_node *node = (struct drm_info_node *)m->private;
2338         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2339         struct drm_device *dev = node->minor->dev;
2340         struct amdgpu_device *adev = drm_to_adev(dev);
2341         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl);
2342         struct drm_printer p = drm_seq_file_printer(m);
2343
2344         man->func->debug(man, &p);
2345         return 0;
2346 }
2347
2348 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2349         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2350         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2351         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2352         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2353         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2354         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2355 #ifdef CONFIG_SWIOTLB
2356         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2357 #endif
2358 };
2359
2360 /**
2361  * amdgpu_ttm_vram_read - Linear read access to VRAM
2362  *
2363  * Accesses VRAM via MMIO for debugging purposes.
2364  */
2365 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2366                                     size_t size, loff_t *pos)
2367 {
2368         struct amdgpu_device *adev = file_inode(f)->i_private;
2369         ssize_t result = 0;
2370
2371         if (size & 0x3 || *pos & 0x3)
2372                 return -EINVAL;
2373
2374         if (*pos >= adev->gmc.mc_vram_size)
2375                 return -ENXIO;
2376
2377         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2378         while (size) {
2379                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2380                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2381
2382                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2383                 if (copy_to_user(buf, value, bytes))
2384                         return -EFAULT;
2385
2386                 result += bytes;
2387                 buf += bytes;
2388                 *pos += bytes;
2389                 size -= bytes;
2390         }
2391
2392         return result;
2393 }
2394
2395 /**
2396  * amdgpu_ttm_vram_write - Linear write access to VRAM
2397  *
2398  * Accesses VRAM via MMIO for debugging purposes.
2399  */
2400 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2401                                     size_t size, loff_t *pos)
2402 {
2403         struct amdgpu_device *adev = file_inode(f)->i_private;
2404         ssize_t result = 0;
2405         int r;
2406
2407         if (size & 0x3 || *pos & 0x3)
2408                 return -EINVAL;
2409
2410         if (*pos >= adev->gmc.mc_vram_size)
2411                 return -ENXIO;
2412
2413         while (size) {
2414                 unsigned long flags;
2415                 uint32_t value;
2416
2417                 if (*pos >= adev->gmc.mc_vram_size)
2418                         return result;
2419
2420                 r = get_user(value, (uint32_t *)buf);
2421                 if (r)
2422                         return r;
2423
2424                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2425                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2426                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2427                 WREG32_NO_KIQ(mmMM_DATA, value);
2428                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2429
2430                 result += 4;
2431                 buf += 4;
2432                 *pos += 4;
2433                 size -= 4;
2434         }
2435
2436         return result;
2437 }
2438
2439 static const struct file_operations amdgpu_ttm_vram_fops = {
2440         .owner = THIS_MODULE,
2441         .read = amdgpu_ttm_vram_read,
2442         .write = amdgpu_ttm_vram_write,
2443         .llseek = default_llseek,
2444 };
2445
2446 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2447
2448 /**
2449  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2450  */
2451 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2452                                    size_t size, loff_t *pos)
2453 {
2454         struct amdgpu_device *adev = file_inode(f)->i_private;
2455         ssize_t result = 0;
2456         int r;
2457
2458         while (size) {
2459                 loff_t p = *pos / PAGE_SIZE;
2460                 unsigned off = *pos & ~PAGE_MASK;
2461                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2462                 struct page *page;
2463                 void *ptr;
2464
2465                 if (p >= adev->gart.num_cpu_pages)
2466                         return result;
2467
2468                 page = adev->gart.pages[p];
2469                 if (page) {
2470                         ptr = kmap(page);
2471                         ptr += off;
2472
2473                         r = copy_to_user(buf, ptr, cur_size);
2474                         kunmap(adev->gart.pages[p]);
2475                 } else
2476                         r = clear_user(buf, cur_size);
2477
2478                 if (r)
2479                         return -EFAULT;
2480
2481                 result += cur_size;
2482                 buf += cur_size;
2483                 *pos += cur_size;
2484                 size -= cur_size;
2485         }
2486
2487         return result;
2488 }
2489
2490 static const struct file_operations amdgpu_ttm_gtt_fops = {
2491         .owner = THIS_MODULE,
2492         .read = amdgpu_ttm_gtt_read,
2493         .llseek = default_llseek
2494 };
2495
2496 #endif
2497
2498 /**
2499  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2500  *
2501  * This function is used to read memory that has been mapped to the
2502  * GPU and the known addresses are not physical addresses but instead
2503  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2504  */
2505 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2506                                  size_t size, loff_t *pos)
2507 {
2508         struct amdgpu_device *adev = file_inode(f)->i_private;
2509         struct iommu_domain *dom;
2510         ssize_t result = 0;
2511         int r;
2512
2513         /* retrieve the IOMMU domain if any for this device */
2514         dom = iommu_get_domain_for_dev(adev->dev);
2515
2516         while (size) {
2517                 phys_addr_t addr = *pos & PAGE_MASK;
2518                 loff_t off = *pos & ~PAGE_MASK;
2519                 size_t bytes = PAGE_SIZE - off;
2520                 unsigned long pfn;
2521                 struct page *p;
2522                 void *ptr;
2523
2524                 bytes = bytes < size ? bytes : size;
2525
2526                 /* Translate the bus address to a physical address.  If
2527                  * the domain is NULL it means there is no IOMMU active
2528                  * and the address translation is the identity
2529                  */
2530                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2531
2532                 pfn = addr >> PAGE_SHIFT;
2533                 if (!pfn_valid(pfn))
2534                         return -EPERM;
2535
2536                 p = pfn_to_page(pfn);
2537                 if (p->mapping != adev->mman.bdev.dev_mapping)
2538                         return -EPERM;
2539
2540                 ptr = kmap(p);
2541                 r = copy_to_user(buf, ptr + off, bytes);
2542                 kunmap(p);
2543                 if (r)
2544                         return -EFAULT;
2545
2546                 size -= bytes;
2547                 *pos += bytes;
2548                 result += bytes;
2549         }
2550
2551         return result;
2552 }
2553
2554 /**
2555  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2556  *
2557  * This function is used to write memory that has been mapped to the
2558  * GPU and the known addresses are not physical addresses but instead
2559  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2560  */
2561 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2562                                  size_t size, loff_t *pos)
2563 {
2564         struct amdgpu_device *adev = file_inode(f)->i_private;
2565         struct iommu_domain *dom;
2566         ssize_t result = 0;
2567         int r;
2568
2569         dom = iommu_get_domain_for_dev(adev->dev);
2570
2571         while (size) {
2572                 phys_addr_t addr = *pos & PAGE_MASK;
2573                 loff_t off = *pos & ~PAGE_MASK;
2574                 size_t bytes = PAGE_SIZE - off;
2575                 unsigned long pfn;
2576                 struct page *p;
2577                 void *ptr;
2578
2579                 bytes = bytes < size ? bytes : size;
2580
2581                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2582
2583                 pfn = addr >> PAGE_SHIFT;
2584                 if (!pfn_valid(pfn))
2585                         return -EPERM;
2586
2587                 p = pfn_to_page(pfn);
2588                 if (p->mapping != adev->mman.bdev.dev_mapping)
2589                         return -EPERM;
2590
2591                 ptr = kmap(p);
2592                 r = copy_from_user(ptr + off, buf, bytes);
2593                 kunmap(p);
2594                 if (r)
2595                         return -EFAULT;
2596
2597                 size -= bytes;
2598                 *pos += bytes;
2599                 result += bytes;
2600         }
2601
2602         return result;
2603 }
2604
2605 static const struct file_operations amdgpu_ttm_iomem_fops = {
2606         .owner = THIS_MODULE,
2607         .read = amdgpu_iomem_read,
2608         .write = amdgpu_iomem_write,
2609         .llseek = default_llseek
2610 };
2611
2612 static const struct {
2613         char *name;
2614         const struct file_operations *fops;
2615         int domain;
2616 } ttm_debugfs_entries[] = {
2617         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2618 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2619         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2620 #endif
2621         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2622 };
2623
2624 #endif
2625
2626 int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2627 {
2628 #if defined(CONFIG_DEBUG_FS)
2629         unsigned count;
2630
2631         struct drm_minor *minor = adev_to_drm(adev)->primary;
2632         struct dentry *ent, *root = minor->debugfs_root;
2633
2634         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2635                 ent = debugfs_create_file(
2636                                 ttm_debugfs_entries[count].name,
2637                                 S_IFREG | S_IRUGO, root,
2638                                 adev,
2639                                 ttm_debugfs_entries[count].fops);
2640                 if (IS_ERR(ent))
2641                         return PTR_ERR(ent);
2642                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2643                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2644                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2645                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2646                 adev->mman.debugfs_entries[count] = ent;
2647         }
2648
2649         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2650
2651 #ifdef CONFIG_SWIOTLB
2652         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2653                 --count;
2654 #endif
2655
2656         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2657 #else
2658         return 0;
2659 #endif
2660 }