drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  *          Christian König
  28  */
  29 #include <linux/seq_file.h>
  30 #include <linux/slab.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/debugfs.h>
  33
  34 #include <drm/amdgpu_drm.h>
  35 #include "amdgpu.h"
  36 #include "atom.h"
  37
  38 /*
  39  * Rings
  40  * Most engines on the GPU are fed via ring buffers.  Ring
  41  * buffers are areas of GPU accessible memory that the host
  42  * writes commands into and the GPU reads commands out of.
  43  * There is a rptr (read pointer) that determines where the
  44  * GPU is currently reading, and a wptr (write pointer)
  45  * which determines where the host has written.  When the
  46  * pointers are equal, the ring is idle.  When the host
  47  * writes commands to the ring buffer, it increments the
  48  * wptr.  The GPU then starts fetching commands and executes
  49  * them until the pointers are equal again.
  50  */
  51
  52 /**
  53  * amdgpu_ring_alloc - allocate space on the ring buffer
  54  *
  55  * @ring: amdgpu_ring structure holding ring information
  56  * @ndw: number of dwords to allocate in the ring buffer
  57  *
  58  * Allocate @ndw dwords in the ring buffer (all asics).
  59  * Returns 0 on success, error on failure.
  60  */
  61 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
  62 {
  63         /* Align requested size with padding so unlock_commit can
  64          * pad safely */
  65         ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
  66
  67         /* Make sure we aren't trying to allocate more space
  68          * than the maximum for one submission
  69          */
  70         if (WARN_ON_ONCE(ndw > ring->max_dw))
  71                 return -ENOMEM;
  72
  73         ring->count_dw = ndw;
  74         ring->wptr_old = ring->wptr;
  75
  76         if (ring->funcs->begin_use)
  77                 ring->funcs->begin_use(ring);
  78
  79         return 0;
  80 }
  81
  82 /** amdgpu_ring_insert_nop - insert NOP packets
  83  *
  84  * @ring: amdgpu_ring structure holding ring information
  85  * @count: the number of NOP packets to insert
  86  *
  87  * This is the generic insert_nop function for rings except SDMA
  88  */
  89 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
  90 {
  91         int i;
  92
  93         for (i = 0; i < count; i++)
  94                 amdgpu_ring_write(ring, ring->funcs->nop);
  95 }
  96
  97 /**
  98  * amdgpu_ring_generic_pad_ib - pad IB with NOP packets
  99  *
 100  * @ring: amdgpu_ring structure holding ring information
 101  * @ib: IB to add NOP packets to
 102  *
 103  * This is the generic pad_ib function for rings except SDMA
 104  */
 105 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 106 {
 107         while (ib->length_dw & ring->funcs->align_mask)
 108                 ib->ptr[ib->length_dw++] = ring->funcs->nop;
 109 }
 110
 111 /**
 112  * amdgpu_ring_commit - tell the GPU to execute the new
 113  * commands on the ring buffer
 114  *
 115  * @ring: amdgpu_ring structure holding ring information
 116  *
 117  * Update the wptr (write pointer) to tell the GPU to
 118  * execute new commands on the ring buffer (all asics).
 119  */
 120 void amdgpu_ring_commit(struct amdgpu_ring *ring)
 121 {
 122         uint32_t count;
 123
 124         /* We pad to match fetch size */
 125         count = ring->funcs->align_mask + 1 -
 126                 (ring->wptr & ring->funcs->align_mask);
 127         count %= ring->funcs->align_mask + 1;
 128         ring->funcs->insert_nop(ring, count);
 129
 130         mb();
 131         amdgpu_ring_set_wptr(ring);
 132
 133         if (ring->funcs->end_use)
 134                 ring->funcs->end_use(ring);
 135 }
 136
 137 /**
 138  * amdgpu_ring_undo - reset the wptr
 139  *
 140  * @ring: amdgpu_ring structure holding ring information
 141  *
 142  * Reset the driver's copy of the wptr (all asics).
 143  */
 144 void amdgpu_ring_undo(struct amdgpu_ring *ring)
 145 {
 146         ring->wptr = ring->wptr_old;
 147
 148         if (ring->funcs->end_use)
 149                 ring->funcs->end_use(ring);
 150 }
 151
 152 /**
 153  * amdgpu_ring_init - init driver ring struct.
 154  *
 155  * @adev: amdgpu_device pointer
 156  * @ring: amdgpu_ring structure holding ring information
 157  * @max_dw: maximum number of dw for ring alloc
 158  * @irq_src: interrupt source to use for this ring
 159  * @irq_type: interrupt type to use for this ring
 160  * @hw_prio: ring priority (NORMAL/HIGH)
 161  *
 162  * Initialize the driver information for the selected ring (all asics).
 163  * Returns 0 on success, error on failure.
 164  */
 165 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
 166                      unsigned int max_dw, struct amdgpu_irq_src *irq_src,
 167                      unsigned int irq_type, unsigned int hw_prio)
 168 {
 169         int r;
 170         int sched_hw_submission = amdgpu_sched_hw_submission;
 171         u32 *num_sched;
 172         u32 hw_ip;
 173
 174         /* Set the hw submission limit higher for KIQ because
 175          * it's used for a number of gfx/compute tasks by both
 176          * KFD and KGD which may have outstanding fences and
 177          * it doesn't really use the gpu scheduler anyway;
 178          * KIQ tasks get submitted directly to the ring.
 179          */
 180         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
 181                 sched_hw_submission = max(sched_hw_submission, 256);
 182         else if (ring == &adev->sdma.instance[0].page)
 183                 sched_hw_submission = 256;
 184
 185         if (ring->adev == NULL) {
 186                 if (adev->num_rings >= AMDGPU_MAX_RINGS)
 187                         return -EINVAL;
 188
 189                 ring->adev = adev;
 190                 ring->idx = adev->num_rings++;
 191                 adev->rings[ring->idx] = ring;
 192                 r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission);
 193                 if (r)
 194                         return r;
 195         }
 196
 197         r = amdgpu_device_wb_get(adev, &ring->rptr_offs);
 198         if (r) {
 199                 dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
 200                 return r;
 201         }
 202
 203         r = amdgpu_device_wb_get(adev, &ring->wptr_offs);
 204         if (r) {
 205                 dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
 206                 return r;
 207         }
 208
 209         r = amdgpu_device_wb_get(adev, &ring->fence_offs);
 210         if (r) {
 211                 dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
 212                 return r;
 213         }
 214
 215         r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs);
 216         if (r) {
 217                 dev_err(adev->dev,
 218                         "(%d) ring trail_fence_offs wb alloc failed\n", r);
 219                 return r;
 220         }
 221         ring->trail_fence_gpu_addr =
 222                 adev->wb.gpu_addr + (ring->trail_fence_offs * 4);
 223         ring->trail_fence_cpu_addr = &adev->wb.wb[ring->trail_fence_offs];
 224
 225         r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs);
 226         if (r) {
 227                 dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
 228                 return r;
 229         }
 230         ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
 231         ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
 232         /* always set cond_exec_polling to CONTINUE */
 233         *ring->cond_exe_cpu_addr = 1;
 234
 235         r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
 236         if (r) {
 237                 dev_err(adev->dev, "failed initializing fences (%d).\n", r);
 238                 return r;
 239         }
 240
 241         ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
 242
 243         ring->buf_mask = (ring->ring_size / 4) - 1;
 244         ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
 245                 0xffffffffffffffff : ring->buf_mask;
 246         /* Allocate ring buffer */
 247         if (ring->ring_obj == NULL) {
 248                 r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE,
 249                                             AMDGPU_GEM_DOMAIN_GTT,
 250                                             &ring->ring_obj,
 251                                             &ring->gpu_addr,
 252                                             (void **)&ring->ring);
 253                 if (r) {
 254                         dev_err(adev->dev, "(%d) ring create failed\n", r);
 255                         return r;
 256                 }
 257                 amdgpu_ring_clear_ring(ring);
 258         }
 259
 260         ring->max_dw = max_dw;
 261         ring->hw_prio = hw_prio;
 262
 263         if (!ring->no_scheduler) {
 264                 hw_ip = ring->funcs->type;
 265                 num_sched = &adev->gpu_sched[hw_ip][hw_prio].num_scheds;
 266                 adev->gpu_sched[hw_ip][hw_prio].sched[(*num_sched)++] =
 267                         &ring->sched;
 268         }
 269
 270         return 0;
 271 }
 272
 273 /**
 274  * amdgpu_ring_fini - tear down the driver ring struct.
 275  *
 276  * @ring: amdgpu_ring structure holding ring information
 277  *
 278  * Tear down the driver information for the selected ring (all asics).
 279  */
 280 void amdgpu_ring_fini(struct amdgpu_ring *ring)
 281 {
 282
 283         /* Not to finish a ring which is not initialized */
 284         if (!(ring->adev) || !(ring->adev->rings[ring->idx]))
 285                 return;
 286
 287         ring->sched.ready = false;
 288
 289         amdgpu_device_wb_free(ring->adev, ring->rptr_offs);
 290         amdgpu_device_wb_free(ring->adev, ring->wptr_offs);
 291
 292         amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs);
 293         amdgpu_device_wb_free(ring->adev, ring->fence_offs);
 294
 295         amdgpu_bo_free_kernel(&ring->ring_obj,
 296                               &ring->gpu_addr,
 297                               (void **)&ring->ring);
 298
 299         dma_fence_put(ring->vmid_wait);
 300         ring->vmid_wait = NULL;
 301         ring->me = 0;
 302
 303         ring->adev->rings[ring->idx] = NULL;
 304 }
 305
 306 /**
 307  * amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper
 308  *
 309  * @ring: ring to write to
 310  * @reg0: register to write
 311  * @reg1: register to wait on
 312  * @ref: reference value to write/wait on
 313  * @mask: mask to wait on
 314  *
 315  * Helper for rings that don't support write and wait in a
 316  * single oneshot packet.
 317  */
 318 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
 319                                                 uint32_t reg0, uint32_t reg1,
 320                                                 uint32_t ref, uint32_t mask)
 321 {
 322         amdgpu_ring_emit_wreg(ring, reg0, ref);
 323         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
 324 }
 325
 326 /**
 327  * amdgpu_ring_soft_recovery - try to soft recover a ring lockup
 328  *
 329  * @ring: ring to try the recovery on
 330  * @vmid: VMID we try to get going again
 331  * @fence: timedout fence
 332  *
 333  * Tries to get a ring proceeding again when it is stuck.
 334  */
 335 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
 336                                struct dma_fence *fence)
 337 {
 338         ktime_t deadline = ktime_add_us(ktime_get(), 10000);
 339
 340         if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence)
 341                 return false;
 342
 343         atomic_inc(&ring->adev->gpu_reset_counter);
 344         while (!dma_fence_is_signaled(fence) &&
 345                ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0)
 346                 ring->funcs->soft_recovery(ring, vmid);
 347
 348         return dma_fence_is_signaled(fence);
 349 }
 350
 351 /*
 352  * Debugfs info
 353  */
 354 #if defined(CONFIG_DEBUG_FS)
 355
 356 /* Layout of file is 12 bytes consisting of
 357  * - rptr
 358  * - wptr
 359  * - driver's copy of wptr
 360  *
 361  * followed by n-words of ring data
 362  */
 363 static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
 364                                         size_t size, loff_t *pos)
 365 {
 366         struct amdgpu_ring *ring = file_inode(f)->i_private;
 367         int r, i;
 368         uint32_t value, result, early[3];
 369
 370         if (*pos & 3 || size & 3)
 371                 return -EINVAL;
 372
 373         result = 0;
 374
 375         if (*pos < 12) {
 376                 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
 377                 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
 378                 early[2] = ring->wptr & ring->buf_mask;
 379                 for (i = *pos / 4; i < 3 && size; i++) {
 380                         r = put_user(early[i], (uint32_t *)buf);
 381                         if (r)
 382                                 return r;
 383                         buf += 4;
 384                         result += 4;
 385                         size -= 4;
 386                         *pos += 4;
 387                 }
 388         }
 389
 390         while (size) {
 391                 if (*pos >= (ring->ring_size + 12))
 392                         return result;
 393
 394                 value = ring->ring[(*pos - 12)/4];
 395                 r = put_user(value, (uint32_t *)buf);
 396                 if (r)
 397                         return r;
 398                 buf += 4;
 399                 result += 4;
 400                 size -= 4;
 401                 *pos += 4;
 402         }
 403
 404         return result;
 405 }
 406
 407 static const struct file_operations amdgpu_debugfs_ring_fops = {
 408         .owner = THIS_MODULE,
 409         .read = amdgpu_debugfs_ring_read,
 410         .llseek = default_llseek
 411 };
 412
 413 #endif
 414
 415 int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
 416                              struct amdgpu_ring *ring)
 417 {
 418 #if defined(CONFIG_DEBUG_FS)
 419         struct drm_minor *minor = adev_to_drm(adev)->primary;
 420         struct dentry *ent, *root = minor->debugfs_root;
 421         char name[32];
 422
 423         sprintf(name, "amdgpu_ring_%s", ring->name);
 424
 425         ent = debugfs_create_file(name,
 426                                   S_IFREG | S_IRUGO, root,
 427                                   ring, &amdgpu_debugfs_ring_fops);
 428         if (!ent)
 429                 return -ENOMEM;
 430
 431         i_size_write(ent->d_inode, ring->ring_size + 12);
 432         ring->ent = ent;
 433 #endif
 434         return 0;
 435 }
 436
 437 /**
 438  * amdgpu_ring_test_helper - tests ring and set sched readiness status
 439  *
 440  * @ring: ring to try the recovery on
 441  *
 442  * Tests ring and set sched readiness status
 443  *
 444  * Returns 0 on success, error on failure.
 445  */
 446 int amdgpu_ring_test_helper(struct amdgpu_ring *ring)
 447 {
 448         struct amdgpu_device *adev = ring->adev;
 449         int r;
 450
 451         r = amdgpu_ring_test_ring(ring);
 452         if (r)
 453                 DRM_DEV_ERROR(adev->dev, "ring %s test failed (%d)\n",
 454                               ring->name, r);
 455         else
 456                 DRM_DEV_DEBUG(adev->dev, "ring test on %s succeeded\n",
 457                               ring->name);
 458
 459         ring->sched.ready = !r;
 460         return r;
 461 }