2 * Copyright 2021 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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24 #include "amdgpu_reset.h"
25 #include "aldebaran.h"
26 #include "sienna_cichlid.h"
27 #include "smu_v13_0_10.h"
29 int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
30 struct amdgpu_reset_handler *handler)
32 /* TODO: Check if handler exists? */
33 list_add_tail(&handler->handler_list, &reset_ctl->reset_handlers);
37 int amdgpu_reset_init(struct amdgpu_device *adev)
41 switch (adev->ip_versions[MP1_HWIP][0]) {
42 case IP_VERSION(13, 0, 2):
43 case IP_VERSION(13, 0, 6):
44 ret = aldebaran_reset_init(adev);
46 case IP_VERSION(11, 0, 7):
47 ret = sienna_cichlid_reset_init(adev);
49 case IP_VERSION(13, 0, 10):
50 ret = smu_v13_0_10_reset_init(adev);
59 int amdgpu_reset_fini(struct amdgpu_device *adev)
63 switch (adev->ip_versions[MP1_HWIP][0]) {
64 case IP_VERSION(13, 0, 2):
65 case IP_VERSION(13, 0, 6):
66 ret = aldebaran_reset_fini(adev);
68 case IP_VERSION(11, 0, 7):
69 ret = sienna_cichlid_reset_fini(adev);
71 case IP_VERSION(13, 0, 10):
72 ret = smu_v13_0_10_reset_fini(adev);
81 int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
82 struct amdgpu_reset_context *reset_context)
84 struct amdgpu_reset_handler *reset_handler = NULL;
86 if (adev->reset_cntl && adev->reset_cntl->get_reset_handler)
87 reset_handler = adev->reset_cntl->get_reset_handler(
88 adev->reset_cntl, reset_context);
92 return reset_handler->prepare_hwcontext(adev->reset_cntl,
96 int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
97 struct amdgpu_reset_context *reset_context)
100 struct amdgpu_reset_handler *reset_handler = NULL;
102 if (adev->reset_cntl)
103 reset_handler = adev->reset_cntl->get_reset_handler(
104 adev->reset_cntl, reset_context);
108 ret = reset_handler->perform_reset(adev->reset_cntl, reset_context);
112 return reset_handler->restore_hwcontext(adev->reset_cntl,
117 void amdgpu_reset_destroy_reset_domain(struct kref *ref)
119 struct amdgpu_reset_domain *reset_domain = container_of(ref,
120 struct amdgpu_reset_domain,
122 if (reset_domain->wq)
123 destroy_workqueue(reset_domain->wq);
125 kvfree(reset_domain);
128 struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type,
131 struct amdgpu_reset_domain *reset_domain;
133 reset_domain = kvzalloc(sizeof(struct amdgpu_reset_domain), GFP_KERNEL);
135 DRM_ERROR("Failed to allocate amdgpu_reset_domain!");
139 reset_domain->type = type;
140 kref_init(&reset_domain->refcount);
142 reset_domain->wq = create_singlethread_workqueue(wq_name);
143 if (!reset_domain->wq) {
144 DRM_ERROR("Failed to allocate wq for amdgpu_reset_domain!");
145 amdgpu_reset_put_reset_domain(reset_domain);
150 atomic_set(&reset_domain->in_gpu_reset, 0);
151 atomic_set(&reset_domain->reset_res, 0);
152 init_rwsem(&reset_domain->sem);
157 void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain)
159 atomic_set(&reset_domain->in_gpu_reset, 1);
160 down_write(&reset_domain->sem);
164 void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain)
166 atomic_set(&reset_domain->in_gpu_reset, 0);
167 up_write(&reset_domain->sem);