drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30 #include <linux/pm_runtime.h>
  31
  32 #include "amdgpu.h"
  33 #include "amdgpu_ras.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_xgmi.h"
  36 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  37 #include "atom.h"
  38 #ifdef CONFIG_X86_MCE_AMD
  39 #include <asm/mce.h>
  40
  41 static bool notifier_registered;
  42 #endif
  43 static const char *RAS_FS_NAME = "ras";
  44
  45 const char *ras_error_string[] = {
  46         "none",
  47         "parity",
  48         "single_correctable",
  49         "multi_uncorrectable",
  50         "poison",
  51 };
  52
  53 const char *ras_block_string[] = {
  54         "umc",
  55         "sdma",
  56         "gfx",
  57         "mmhub",
  58         "athub",
  59         "pcie_bif",
  60         "hdp",
  61         "xgmi_wafl",
  62         "df",
  63         "smn",
  64         "sem",
  65         "mp0",
  66         "mp1",
  67         "fuse",
  68         "mca",
  69 };
  70
  71 const char *ras_mca_block_string[] = {
  72         "mca_mp0",
  73         "mca_mp1",
  74         "mca_mpio",
  75         "mca_iohc",
  76 };
  77
  78 struct amdgpu_ras_block_list {
  79         /* ras block link */
  80         struct list_head node;
  81
  82         struct amdgpu_ras_block_object *ras_obj;
  83 };
  84
  85 const char *get_ras_block_str(struct ras_common_if *ras_block)
  86 {
  87         if (!ras_block)
  88                 return "NULL";
  89
  90         if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)
  91                 return "OUT OF RANGE";
  92
  93         if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
  94                 return ras_mca_block_string[ras_block->sub_block_index];
  95
  96         return ras_block_string[ras_block->block];
  97 }
  98
  99 #define ras_block_str(_BLOCK_) \
 100         (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
 101
 102 #define ras_err_str(i) (ras_error_string[ffs(i)])
 103
 104 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
 105
 106 /* inject address is 52 bits */
 107 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
 108
 109 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */
 110 #define RAS_BAD_PAGE_COVER              (100 * 1024 * 1024ULL)
 111
 112 enum amdgpu_ras_retire_page_reservation {
 113         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
 114         AMDGPU_RAS_RETIRE_PAGE_PENDING,
 115         AMDGPU_RAS_RETIRE_PAGE_FAULT,
 116 };
 117
 118 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
 119
 120 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
 121                                 uint64_t addr);
 122 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
 123                                 uint64_t addr);
 124 #ifdef CONFIG_X86_MCE_AMD
 125 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
 126 struct mce_notifier_adev_list {
 127         struct amdgpu_device *devs[MAX_GPU_INSTANCE];
 128         int num_gpu;
 129 };
 130 static struct mce_notifier_adev_list mce_adev_list;
 131 #endif
 132
 133 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
 134 {
 135         if (adev && amdgpu_ras_get_context(adev))
 136                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
 137 }
 138
 139 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
 140 {
 141         if (adev && amdgpu_ras_get_context(adev))
 142                 return amdgpu_ras_get_context(adev)->error_query_ready;
 143
 144         return false;
 145 }
 146
 147 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 148 {
 149         struct ras_err_data err_data = {0, 0, 0, NULL};
 150         struct eeprom_table_record err_rec;
 151
 152         if ((address >= adev->gmc.mc_vram_size) ||
 153             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 154                 dev_warn(adev->dev,
 155                          "RAS WARN: input address 0x%llx is invalid.\n",
 156                          address);
 157                 return -EINVAL;
 158         }
 159
 160         if (amdgpu_ras_check_bad_page(adev, address)) {
 161                 dev_warn(adev->dev,
 162                          "RAS WARN: 0x%llx has already been marked as bad page!\n",
 163                          address);
 164                 return 0;
 165         }
 166
 167         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 168         err_data.err_addr = &err_rec;
 169         amdgpu_umc_fill_error_record(&err_data, address,
 170                         (address >> AMDGPU_GPU_PAGE_SHIFT), 0, 0);
 171
 172         if (amdgpu_bad_page_threshold != 0) {
 173                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 174                                          err_data.err_addr_cnt);
 175                 amdgpu_ras_save_bad_pages(adev);
 176         }
 177
 178         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 179         dev_warn(adev->dev, "Clear EEPROM:\n");
 180         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 181
 182         return 0;
 183 }
 184
 185 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 186                                         size_t size, loff_t *pos)
 187 {
 188         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 189         struct ras_query_if info = {
 190                 .head = obj->head,
 191         };
 192         ssize_t s;
 193         char val[128];
 194
 195         if (amdgpu_ras_query_error_status(obj->adev, &info))
 196                 return -EINVAL;
 197
 198         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 199                         "ue", info.ue_count,
 200                         "ce", info.ce_count);
 201         if (*pos >= s)
 202                 return 0;
 203
 204         s -= *pos;
 205         s = min_t(u64, s, size);
 206
 207
 208         if (copy_to_user(buf, &val[*pos], s))
 209                 return -EINVAL;
 210
 211         *pos += s;
 212
 213         return s;
 214 }
 215
 216 static const struct file_operations amdgpu_ras_debugfs_ops = {
 217         .owner = THIS_MODULE,
 218         .read = amdgpu_ras_debugfs_read,
 219         .write = NULL,
 220         .llseek = default_llseek
 221 };
 222
 223 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 224 {
 225         int i;
 226
 227         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 228                 *block_id = i;
 229                 if (strcmp(name, ras_block_string[i]) == 0)
 230                         return 0;
 231         }
 232         return -EINVAL;
 233 }
 234
 235 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 236                 const char __user *buf, size_t size,
 237                 loff_t *pos, struct ras_debug_if *data)
 238 {
 239         ssize_t s = min_t(u64, 64, size);
 240         char str[65];
 241         char block_name[33];
 242         char err[9] = "ue";
 243         int op = -1;
 244         int block_id;
 245         uint32_t sub_block;
 246         u64 address, value;
 247
 248         if (*pos)
 249                 return -EINVAL;
 250         *pos = size;
 251
 252         memset(str, 0, sizeof(str));
 253         memset(data, 0, sizeof(*data));
 254
 255         if (copy_from_user(str, buf, s))
 256                 return -EINVAL;
 257
 258         if (sscanf(str, "disable %32s", block_name) == 1)
 259                 op = 0;
 260         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 261                 op = 1;
 262         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 263                 op = 2;
 264         else if (strstr(str, "retire_page") != NULL)
 265                 op = 3;
 266         else if (str[0] && str[1] && str[2] && str[3])
 267                 /* ascii string, but commands are not matched. */
 268                 return -EINVAL;
 269
 270         if (op != -1) {
 271                 if (op == 3) {
 272                         if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
 273                             sscanf(str, "%*s %llu", &address) != 1)
 274                                 return -EINVAL;
 275
 276                         data->op = op;
 277                         data->inject.address = address;
 278
 279                         return 0;
 280                 }
 281
 282                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 283                         return -EINVAL;
 284
 285                 data->head.block = block_id;
 286                 /* only ue and ce errors are supported */
 287                 if (!memcmp("ue", err, 2))
 288                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 289                 else if (!memcmp("ce", err, 2))
 290                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 291                 else
 292                         return -EINVAL;
 293
 294                 data->op = op;
 295
 296                 if (op == 2) {
 297                         if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 298                                    &sub_block, &address, &value) != 3 &&
 299                             sscanf(str, "%*s %*s %*s %u %llu %llu",
 300                                    &sub_block, &address, &value) != 3)
 301                                 return -EINVAL;
 302                         data->head.sub_block_index = sub_block;
 303                         data->inject.address = address;
 304                         data->inject.value = value;
 305                 }
 306         } else {
 307                 if (size < sizeof(*data))
 308                         return -EINVAL;
 309
 310                 if (copy_from_user(data, buf, sizeof(*data)))
 311                         return -EINVAL;
 312         }
 313
 314         return 0;
 315 }
 316
 317 /**
 318  * DOC: AMDGPU RAS debugfs control interface
 319  *
 320  * The control interface accepts struct ras_debug_if which has two members.
 321  *
 322  * First member: ras_debug_if::head or ras_debug_if::inject.
 323  *
 324  * head is used to indicate which IP block will be under control.
 325  *
 326  * head has four members, they are block, type, sub_block_index, name.
 327  * block: which IP will be under control.
 328  * type: what kind of error will be enabled/disabled/injected.
 329  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 330  * name: the name of IP.
 331  *
 332  * inject has two more members than head, they are address, value.
 333  * As their names indicate, inject operation will write the
 334  * value to the address.
 335  *
 336  * The second member: struct ras_debug_if::op.
 337  * It has three kinds of operations.
 338  *
 339  * - 0: disable RAS on the block. Take ::head as its data.
 340  * - 1: enable RAS on the block. Take ::head as its data.
 341  * - 2: inject errors on the block. Take ::inject as its data.
 342  *
 343  * How to use the interface?
 344  *
 345  * In a program
 346  *
 347  * Copy the struct ras_debug_if in your code and initialize it.
 348  * Write the struct to the control interface.
 349  *
 350  * From shell
 351  *
 352  * .. code-block:: bash
 353  *
 354  *      echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 355  *      echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 356  *      echo "inject  <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 357  *
 358  * Where N, is the card which you want to affect.
 359  *
 360  * "disable" requires only the block.
 361  * "enable" requires the block and error type.
 362  * "inject" requires the block, error type, address, and value.
 363  *
 364  * The block is one of: umc, sdma, gfx, etc.
 365  *      see ras_block_string[] for details
 366  *
 367  * The error type is one of: ue, ce, where,
 368  *      ue is multi-uncorrectable
 369  *      ce is single-correctable
 370  *
 371  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
 372  * The address and value are hexadecimal numbers, leading 0x is optional.
 373  *
 374  * For instance,
 375  *
 376  * .. code-block:: bash
 377  *
 378  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 379  *      echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 380  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 381  *
 382  * How to check the result of the operation?
 383  *
 384  * To check disable/enable, see "ras" features at,
 385  * /sys/class/drm/card[0/1/2...]/device/ras/features
 386  *
 387  * To check inject, see the corresponding error count at,
 388  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
 389  *
 390  * .. note::
 391  *      Operations are only allowed on blocks which are supported.
 392  *      Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
 393  *      to see which blocks support RAS on a particular asic.
 394  *
 395  */
 396 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
 397                                              const char __user *buf,
 398                                              size_t size, loff_t *pos)
 399 {
 400         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 401         struct ras_debug_if data;
 402         int ret = 0;
 403
 404         if (!amdgpu_ras_get_error_query_ready(adev)) {
 405                 dev_warn(adev->dev, "RAS WARN: error injection "
 406                                 "currently inaccessible\n");
 407                 return size;
 408         }
 409
 410         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 411         if (ret)
 412                 return ret;
 413
 414         if (data.op == 3) {
 415                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 416                 if (!ret)
 417                         return size;
 418                 else
 419                         return ret;
 420         }
 421
 422         if (!amdgpu_ras_is_supported(adev, data.head.block))
 423                 return -EINVAL;
 424
 425         switch (data.op) {
 426         case 0:
 427                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 428                 break;
 429         case 1:
 430                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 431                 break;
 432         case 2:
 433                 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
 434                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 435                         dev_warn(adev->dev, "RAS WARN: input address "
 436                                         "0x%llx is invalid.",
 437                                         data.inject.address);
 438                         ret = -EINVAL;
 439                         break;
 440                 }
 441
 442                 /* umc ce/ue error injection for a bad page is not allowed */
 443                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 444                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 445                         dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
 446                                  "already been marked as bad!\n",
 447                                  data.inject.address);
 448                         break;
 449                 }
 450
 451                 /* data.inject.address is offset instead of absolute gpu address */
 452                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 453                 break;
 454         default:
 455                 ret = -EINVAL;
 456                 break;
 457         }
 458
 459         if (ret)
 460                 return ret;
 461
 462         return size;
 463 }
 464
 465 /**
 466  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 467  *
 468  * Some boards contain an EEPROM which is used to persistently store a list of
 469  * bad pages which experiences ECC errors in vram.  This interface provides
 470  * a way to reset the EEPROM, e.g., after testing error injection.
 471  *
 472  * Usage:
 473  *
 474  * .. code-block:: bash
 475  *
 476  *      echo 1 > ../ras/ras_eeprom_reset
 477  *
 478  * will reset EEPROM table to 0 entries.
 479  *
 480  */
 481 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
 482                                                const char __user *buf,
 483                                                size_t size, loff_t *pos)
 484 {
 485         struct amdgpu_device *adev =
 486                 (struct amdgpu_device *)file_inode(f)->i_private;
 487         int ret;
 488
 489         ret = amdgpu_ras_eeprom_reset_table(
 490                 &(amdgpu_ras_get_context(adev)->eeprom_control));
 491
 492         if (!ret) {
 493                 /* Something was written to EEPROM.
 494                  */
 495                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 496                 return size;
 497         } else {
 498                 return ret;
 499         }
 500 }
 501
 502 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 503         .owner = THIS_MODULE,
 504         .read = NULL,
 505         .write = amdgpu_ras_debugfs_ctrl_write,
 506         .llseek = default_llseek
 507 };
 508
 509 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 510         .owner = THIS_MODULE,
 511         .read = NULL,
 512         .write = amdgpu_ras_debugfs_eeprom_write,
 513         .llseek = default_llseek
 514 };
 515
 516 /**
 517  * DOC: AMDGPU RAS sysfs Error Count Interface
 518  *
 519  * It allows the user to read the error count for each IP block on the gpu through
 520  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 521  *
 522  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 523  * (ce) error counts.
 524  *
 525  * The format of one line is below,
 526  *
 527  * [ce|ue]: count
 528  *
 529  * Example:
 530  *
 531  * .. code-block:: bash
 532  *
 533  *      ue: 0
 534  *      ce: 1
 535  *
 536  */
 537 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 538                 struct device_attribute *attr, char *buf)
 539 {
 540         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 541         struct ras_query_if info = {
 542                 .head = obj->head,
 543         };
 544
 545         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 546                 return sysfs_emit(buf, "Query currently inaccessible\n");
 547
 548         if (amdgpu_ras_query_error_status(obj->adev, &info))
 549                 return -EINVAL;
 550
 551         if (obj->adev->asic_type == CHIP_ALDEBARAN) {
 552                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 553                         DRM_WARN("Failed to reset error counter and error status");
 554         }
 555
 556         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 557                           "ce", info.ce_count);
 558 }
 559
 560 /* obj begin */
 561
 562 #define get_obj(obj) do { (obj)->use++; } while (0)
 563 #define alive_obj(obj) ((obj)->use)
 564
 565 static inline void put_obj(struct ras_manager *obj)
 566 {
 567         if (obj && (--obj->use == 0))
 568                 list_del(&obj->node);
 569         if (obj && (obj->use < 0))
 570                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
 571 }
 572
 573 /* make one obj and return it. */
 574 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 575                 struct ras_common_if *head)
 576 {
 577         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 578         struct ras_manager *obj;
 579
 580         if (!adev->ras_enabled || !con)
 581                 return NULL;
 582
 583         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 584                 return NULL;
 585
 586         if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 587                 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 588                         return NULL;
 589
 590                 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 591         } else
 592                 obj = &con->objs[head->block];
 593
 594         /* already exist. return obj? */
 595         if (alive_obj(obj))
 596                 return NULL;
 597
 598         obj->head = *head;
 599         obj->adev = adev;
 600         list_add(&obj->node, &con->head);
 601         get_obj(obj);
 602
 603         return obj;
 604 }
 605
 606 /* return an obj equal to head, or the first when head is NULL */
 607 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 608                 struct ras_common_if *head)
 609 {
 610         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 611         struct ras_manager *obj;
 612         int i;
 613
 614         if (!adev->ras_enabled || !con)
 615                 return NULL;
 616
 617         if (head) {
 618                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 619                         return NULL;
 620
 621                 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 622                         if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 623                                 return NULL;
 624
 625                         obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 626                 } else
 627                         obj = &con->objs[head->block];
 628
 629                 if (alive_obj(obj))
 630                         return obj;
 631         } else {
 632                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 633                         obj = &con->objs[i];
 634                         if (alive_obj(obj))
 635                                 return obj;
 636                 }
 637         }
 638
 639         return NULL;
 640 }
 641 /* obj end */
 642
 643 /* feature ctl begin */
 644 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 645                                          struct ras_common_if *head)
 646 {
 647         return adev->ras_hw_enabled & BIT(head->block);
 648 }
 649
 650 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 651                 struct ras_common_if *head)
 652 {
 653         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 654
 655         return con->features & BIT(head->block);
 656 }
 657
 658 /*
 659  * if obj is not created, then create one.
 660  * set feature enable flag.
 661  */
 662 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 663                 struct ras_common_if *head, int enable)
 664 {
 665         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 666         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 667
 668         /* If hardware does not support ras, then do not create obj.
 669          * But if hardware support ras, we can create the obj.
 670          * Ras framework checks con->hw_supported to see if it need do
 671          * corresponding initialization.
 672          * IP checks con->support to see if it need disable ras.
 673          */
 674         if (!amdgpu_ras_is_feature_allowed(adev, head))
 675                 return 0;
 676
 677         if (enable) {
 678                 if (!obj) {
 679                         obj = amdgpu_ras_create_obj(adev, head);
 680                         if (!obj)
 681                                 return -EINVAL;
 682                 } else {
 683                         /* In case we create obj somewhere else */
 684                         get_obj(obj);
 685                 }
 686                 con->features |= BIT(head->block);
 687         } else {
 688                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 689                         con->features &= ~BIT(head->block);
 690                         put_obj(obj);
 691                 }
 692         }
 693
 694         return 0;
 695 }
 696
 697 /* wrapper of psp_ras_enable_features */
 698 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 699                 struct ras_common_if *head, bool enable)
 700 {
 701         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 702         union ta_ras_cmd_input *info;
 703         int ret;
 704
 705         if (!con)
 706                 return -EINVAL;
 707
 708         info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 709         if (!info)
 710                 return -ENOMEM;
 711
 712         if (!enable) {
 713                 info->disable_features = (struct ta_ras_disable_features_input) {
 714                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 715                         .error_type = amdgpu_ras_error_to_ta(head->type),
 716                 };
 717         } else {
 718                 info->enable_features = (struct ta_ras_enable_features_input) {
 719                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 720                         .error_type = amdgpu_ras_error_to_ta(head->type),
 721                 };
 722         }
 723
 724         /* Do not enable if it is not allowed. */
 725         WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
 726
 727         if (!amdgpu_ras_intr_triggered()) {
 728                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 729                 if (ret) {
 730                         dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
 731                                 enable ? "enable":"disable",
 732                                 get_ras_block_str(head),
 733                                 amdgpu_ras_is_poison_mode_supported(adev), ret);
 734                         goto out;
 735                 }
 736         }
 737
 738         /* setup the obj */
 739         __amdgpu_ras_feature_enable(adev, head, enable);
 740         ret = 0;
 741 out:
 742         kfree(info);
 743         return ret;
 744 }
 745
 746 /* Only used in device probe stage and called only once. */
 747 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 748                 struct ras_common_if *head, bool enable)
 749 {
 750         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 751         int ret;
 752
 753         if (!con)
 754                 return -EINVAL;
 755
 756         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 757                 if (enable) {
 758                         /* There is no harm to issue a ras TA cmd regardless of
 759                          * the currecnt ras state.
 760                          * If current state == target state, it will do nothing
 761                          * But sometimes it requests driver to reset and repost
 762                          * with error code -EAGAIN.
 763                          */
 764                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 765                         /* With old ras TA, we might fail to enable ras.
 766                          * Log it and just setup the object.
 767                          * TODO need remove this WA in the future.
 768                          */
 769                         if (ret == -EINVAL) {
 770                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 771                                 if (!ret)
 772                                         dev_info(adev->dev,
 773                                                 "RAS INFO: %s setup object\n",
 774                                                 get_ras_block_str(head));
 775                         }
 776                 } else {
 777                         /* setup the object then issue a ras TA disable cmd.*/
 778                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 779                         if (ret)
 780                                 return ret;
 781
 782                         /* gfx block ras dsiable cmd must send to ras-ta */
 783                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 784                                 con->features |= BIT(head->block);
 785
 786                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 787
 788                         /* clean gfx block ras features flag */
 789                         if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
 790                                 con->features &= ~BIT(head->block);
 791                 }
 792         } else
 793                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 794
 795         return ret;
 796 }
 797
 798 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 799                 bool bypass)
 800 {
 801         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 802         struct ras_manager *obj, *tmp;
 803
 804         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 805                 /* bypass psp.
 806                  * aka just release the obj and corresponding flags
 807                  */
 808                 if (bypass) {
 809                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 810                                 break;
 811                 } else {
 812                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 813                                 break;
 814                 }
 815         }
 816
 817         return con->features;
 818 }
 819
 820 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 821                 bool bypass)
 822 {
 823         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 824         int i;
 825         const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
 826
 827         for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 828                 struct ras_common_if head = {
 829                         .block = i,
 830                         .type = default_ras_type,
 831                         .sub_block_index = 0,
 832                 };
 833
 834                 if (i == AMDGPU_RAS_BLOCK__MCA)
 835                         continue;
 836
 837                 if (bypass) {
 838                         /*
 839                          * bypass psp. vbios enable ras for us.
 840                          * so just create the obj
 841                          */
 842                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 843                                 break;
 844                 } else {
 845                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 846                                 break;
 847                 }
 848         }
 849
 850         for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 851                 struct ras_common_if head = {
 852                         .block = AMDGPU_RAS_BLOCK__MCA,
 853                         .type = default_ras_type,
 854                         .sub_block_index = i,
 855                 };
 856
 857                 if (bypass) {
 858                         /*
 859                          * bypass psp. vbios enable ras for us.
 860                          * so just create the obj
 861                          */
 862                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 863                                 break;
 864                 } else {
 865                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 866                                 break;
 867                 }
 868         }
 869
 870         return con->features;
 871 }
 872 /* feature ctl end */
 873
 874 static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
 875                 enum amdgpu_ras_block block)
 876 {
 877         if (!block_obj)
 878                 return -EINVAL;
 879
 880         if (block_obj->block == block)
 881                 return 0;
 882
 883         return -EINVAL;
 884 }
 885
 886 static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
 887                                         enum amdgpu_ras_block block, uint32_t sub_block_index)
 888 {
 889         struct amdgpu_ras_block_list *node, *tmp;
 890         struct amdgpu_ras_block_object *obj;
 891
 892         if (block >= AMDGPU_RAS_BLOCK__LAST)
 893                 return NULL;
 894
 895         if (!amdgpu_ras_is_supported(adev, block))
 896                 return NULL;
 897
 898         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
 899                 if (!node->ras_obj) {
 900                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
 901                         continue;
 902                 }
 903
 904                 obj = node->ras_obj;
 905                 if (obj->ras_block_match) {
 906                         if (obj->ras_block_match(obj, block, sub_block_index) == 0)
 907                                 return obj;
 908                 } else {
 909                         if (amdgpu_ras_block_match_default(obj, block) == 0)
 910                                 return obj;
 911                 }
 912         }
 913
 914         return NULL;
 915 }
 916
 917 static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
 918 {
 919         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 920         int ret = 0;
 921
 922         /*
 923          * choosing right query method according to
 924          * whether smu support query error information
 925          */
 926         ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
 927         if (ret == -EOPNOTSUPP) {
 928                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
 929                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
 930                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
 931
 932                 /* umc query_ras_error_address is also responsible for clearing
 933                  * error status
 934                  */
 935                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
 936                     adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
 937                         adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
 938         } else if (!ret) {
 939                 if (adev->umc.ras &&
 940                         adev->umc.ras->ecc_info_query_ras_error_count)
 941                         adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
 942
 943                 if (adev->umc.ras &&
 944                         adev->umc.ras->ecc_info_query_ras_error_address)
 945                         adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
 946         }
 947 }
 948
 949 /* query/inject/cure begin */
 950 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 951                                   struct ras_query_if *info)
 952 {
 953         struct amdgpu_ras_block_object *block_obj = NULL;
 954         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 955         struct ras_err_data err_data = {0, 0, 0, NULL};
 956
 957         if (!obj)
 958                 return -EINVAL;
 959
 960         if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
 961                 amdgpu_ras_get_ecc_info(adev, &err_data);
 962         } else {
 963                 block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
 964                 if (!block_obj || !block_obj->hw_ops)   {
 965                         dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
 966                                      get_ras_block_str(&info->head));
 967                         return -EINVAL;
 968                 }
 969
 970                 if (block_obj->hw_ops->query_ras_error_count)
 971                         block_obj->hw_ops->query_ras_error_count(adev, &err_data);
 972
 973                 if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
 974                     (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
 975                     (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
 976                                 if (block_obj->hw_ops->query_ras_error_status)
 977                                         block_obj->hw_ops->query_ras_error_status(adev);
 978                         }
 979         }
 980
 981         obj->err_data.ue_count += err_data.ue_count;
 982         obj->err_data.ce_count += err_data.ce_count;
 983
 984         info->ue_count = obj->err_data.ue_count;
 985         info->ce_count = obj->err_data.ce_count;
 986
 987         if (err_data.ce_count) {
 988                 if (adev->smuio.funcs &&
 989                     adev->smuio.funcs->get_socket_id &&
 990                     adev->smuio.funcs->get_die_id) {
 991                         dev_info(adev->dev, "socket: %d, die: %d "
 992                                         "%ld correctable hardware errors "
 993                                         "detected in %s block, no user "
 994                                         "action is needed.\n",
 995                                         adev->smuio.funcs->get_socket_id(adev),
 996                                         adev->smuio.funcs->get_die_id(adev),
 997                                         obj->err_data.ce_count,
 998                                         get_ras_block_str(&info->head));
 999                 } else {
1000                         dev_info(adev->dev, "%ld correctable hardware errors "
1001                                         "detected in %s block, no user "
1002                                         "action is needed.\n",
1003                                         obj->err_data.ce_count,
1004                                         get_ras_block_str(&info->head));
1005                 }
1006         }
1007         if (err_data.ue_count) {
1008                 if (adev->smuio.funcs &&
1009                     adev->smuio.funcs->get_socket_id &&
1010                     adev->smuio.funcs->get_die_id) {
1011                         dev_info(adev->dev, "socket: %d, die: %d "
1012                                         "%ld uncorrectable hardware errors "
1013                                         "detected in %s block\n",
1014                                         adev->smuio.funcs->get_socket_id(adev),
1015                                         adev->smuio.funcs->get_die_id(adev),
1016                                         obj->err_data.ue_count,
1017                                         get_ras_block_str(&info->head));
1018                 } else {
1019                         dev_info(adev->dev, "%ld uncorrectable hardware errors "
1020                                         "detected in %s block\n",
1021                                         obj->err_data.ue_count,
1022                                         get_ras_block_str(&info->head));
1023                 }
1024         }
1025
1026         if (!amdgpu_persistent_edc_harvesting_supported(adev))
1027                 amdgpu_ras_reset_error_status(adev, info->head.block);
1028
1029         return 0;
1030 }
1031
1032 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1033                 enum amdgpu_ras_block block)
1034 {
1035         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1036
1037         if (!amdgpu_ras_is_supported(adev, block))
1038                 return -EINVAL;
1039
1040         if (!block_obj || !block_obj->hw_ops)   {
1041                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1042                              ras_block_str(block));
1043                 return -EINVAL;
1044         }
1045
1046         if (block_obj->hw_ops->reset_ras_error_count)
1047                 block_obj->hw_ops->reset_ras_error_count(adev);
1048
1049         if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1050             (block == AMDGPU_RAS_BLOCK__MMHUB)) {
1051                 if (block_obj->hw_ops->reset_ras_error_status)
1052                         block_obj->hw_ops->reset_ras_error_status(adev);
1053         }
1054
1055         return 0;
1056 }
1057
1058 /* wrapper of psp_ras_trigger_error */
1059 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1060                 struct ras_inject_if *info)
1061 {
1062         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1063         struct ta_ras_trigger_error_input block_info = {
1064                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
1065                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1066                 .sub_block_index = info->head.sub_block_index,
1067                 .address = info->address,
1068                 .value = info->value,
1069         };
1070         int ret = -EINVAL;
1071         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1072                                                         info->head.block,
1073                                                         info->head.sub_block_index);
1074
1075         if (!obj)
1076                 return -EINVAL;
1077
1078         if (!block_obj || !block_obj->hw_ops)   {
1079                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1080                              get_ras_block_str(&info->head));
1081                 return -EINVAL;
1082         }
1083
1084         /* Calculate XGMI relative offset */
1085         if (adev->gmc.xgmi.num_physical_nodes > 1) {
1086                 block_info.address =
1087                         amdgpu_xgmi_get_relative_phy_addr(adev,
1088                                                           block_info.address);
1089         }
1090
1091         if (info->head.block == AMDGPU_RAS_BLOCK__GFX) {
1092                 if (block_obj->hw_ops->ras_error_inject)
1093                         ret = block_obj->hw_ops->ras_error_inject(adev, info);
1094         } else {
1095                 /* If defined special ras_error_inject(e.g: xgmi), implement special ras_error_inject */
1096                 if (block_obj->hw_ops->ras_error_inject)
1097                         ret = block_obj->hw_ops->ras_error_inject(adev, &block_info);
1098                 else  /*If not defined .ras_error_inject, use default ras_error_inject*/
1099                         ret = psp_ras_trigger_error(&adev->psp, &block_info);
1100         }
1101
1102         if (ret)
1103                 dev_err(adev->dev, "ras inject %s failed %d\n",
1104                         get_ras_block_str(&info->head), ret);
1105
1106         return ret;
1107 }
1108
1109 /**
1110  * amdgpu_ras_query_error_count -- Get error counts of all IPs
1111  * @adev: pointer to AMD GPU device
1112  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1113  * @ue_count: pointer to an integer to be set to the count of uncorrectible
1114  * errors.
1115  *
1116  * If set, @ce_count or @ue_count, count and return the corresponding
1117  * error counts in those integer pointers. Return 0 if the device
1118  * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1119  */
1120 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1121                                  unsigned long *ce_count,
1122                                  unsigned long *ue_count)
1123 {
1124         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1125         struct ras_manager *obj;
1126         unsigned long ce, ue;
1127
1128         if (!adev->ras_enabled || !con)
1129                 return -EOPNOTSUPP;
1130
1131         /* Don't count since no reporting.
1132          */
1133         if (!ce_count && !ue_count)
1134                 return 0;
1135
1136         ce = 0;
1137         ue = 0;
1138         list_for_each_entry(obj, &con->head, node) {
1139                 struct ras_query_if info = {
1140                         .head = obj->head,
1141                 };
1142                 int res;
1143
1144                 res = amdgpu_ras_query_error_status(adev, &info);
1145                 if (res)
1146                         return res;
1147
1148                 ce += info.ce_count;
1149                 ue += info.ue_count;
1150         }
1151
1152         if (ce_count)
1153                 *ce_count = ce;
1154
1155         if (ue_count)
1156                 *ue_count = ue;
1157
1158         return 0;
1159 }
1160 /* query/inject/cure end */
1161
1162
1163 /* sysfs begin */
1164
1165 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1166                 struct ras_badpage **bps, unsigned int *count);
1167
1168 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1169 {
1170         switch (flags) {
1171         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1172                 return "R";
1173         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1174                 return "P";
1175         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1176         default:
1177                 return "F";
1178         }
1179 }
1180
1181 /**
1182  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1183  *
1184  * It allows user to read the bad pages of vram on the gpu through
1185  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1186  *
1187  * It outputs multiple lines, and each line stands for one gpu page.
1188  *
1189  * The format of one line is below,
1190  * gpu pfn : gpu page size : flags
1191  *
1192  * gpu pfn and gpu page size are printed in hex format.
1193  * flags can be one of below character,
1194  *
1195  * R: reserved, this gpu page is reserved and not able to use.
1196  *
1197  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1198  * in next window of page_reserve.
1199  *
1200  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1201  *
1202  * Examples:
1203  *
1204  * .. code-block:: bash
1205  *
1206  *      0x00000001 : 0x00001000 : R
1207  *      0x00000002 : 0x00001000 : P
1208  *
1209  */
1210
1211 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1212                 struct kobject *kobj, struct bin_attribute *attr,
1213                 char *buf, loff_t ppos, size_t count)
1214 {
1215         struct amdgpu_ras *con =
1216                 container_of(attr, struct amdgpu_ras, badpages_attr);
1217         struct amdgpu_device *adev = con->adev;
1218         const unsigned int element_size =
1219                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1220         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1221         unsigned int end = div64_ul(ppos + count - 1, element_size);
1222         ssize_t s = 0;
1223         struct ras_badpage *bps = NULL;
1224         unsigned int bps_count = 0;
1225
1226         memset(buf, 0, count);
1227
1228         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1229                 return 0;
1230
1231         for (; start < end && start < bps_count; start++)
1232                 s += scnprintf(&buf[s], element_size + 1,
1233                                 "0x%08x : 0x%08x : %1s\n",
1234                                 bps[start].bp,
1235                                 bps[start].size,
1236                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1237
1238         kfree(bps);
1239
1240         return s;
1241 }
1242
1243 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1244                 struct device_attribute *attr, char *buf)
1245 {
1246         struct amdgpu_ras *con =
1247                 container_of(attr, struct amdgpu_ras, features_attr);
1248
1249         return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1250 }
1251
1252 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1253 {
1254         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1255
1256         sysfs_remove_file_from_group(&adev->dev->kobj,
1257                                 &con->badpages_attr.attr,
1258                                 RAS_FS_NAME);
1259 }
1260
1261 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1262 {
1263         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1264         struct attribute *attrs[] = {
1265                 &con->features_attr.attr,
1266                 NULL
1267         };
1268         struct attribute_group group = {
1269                 .name = RAS_FS_NAME,
1270                 .attrs = attrs,
1271         };
1272
1273         sysfs_remove_group(&adev->dev->kobj, &group);
1274
1275         return 0;
1276 }
1277
1278 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1279                 struct ras_fs_if *head)
1280 {
1281         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1282
1283         if (!obj || obj->attr_inuse)
1284                 return -EINVAL;
1285
1286         get_obj(obj);
1287
1288         memcpy(obj->fs_data.sysfs_name,
1289                         head->sysfs_name,
1290                         sizeof(obj->fs_data.sysfs_name));
1291
1292         obj->sysfs_attr = (struct device_attribute){
1293                 .attr = {
1294                         .name = obj->fs_data.sysfs_name,
1295                         .mode = S_IRUGO,
1296                 },
1297                         .show = amdgpu_ras_sysfs_read,
1298         };
1299         sysfs_attr_init(&obj->sysfs_attr.attr);
1300
1301         if (sysfs_add_file_to_group(&adev->dev->kobj,
1302                                 &obj->sysfs_attr.attr,
1303                                 RAS_FS_NAME)) {
1304                 put_obj(obj);
1305                 return -EINVAL;
1306         }
1307
1308         obj->attr_inuse = 1;
1309
1310         return 0;
1311 }
1312
1313 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1314                 struct ras_common_if *head)
1315 {
1316         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1317
1318         if (!obj || !obj->attr_inuse)
1319                 return -EINVAL;
1320
1321         sysfs_remove_file_from_group(&adev->dev->kobj,
1322                                 &obj->sysfs_attr.attr,
1323                                 RAS_FS_NAME);
1324         obj->attr_inuse = 0;
1325         put_obj(obj);
1326
1327         return 0;
1328 }
1329
1330 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1331 {
1332         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1333         struct ras_manager *obj, *tmp;
1334
1335         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1336                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1337         }
1338
1339         if (amdgpu_bad_page_threshold != 0)
1340                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1341
1342         amdgpu_ras_sysfs_remove_feature_node(adev);
1343
1344         return 0;
1345 }
1346 /* sysfs end */
1347
1348 /**
1349  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1350  *
1351  * Normally when there is an uncorrectable error, the driver will reset
1352  * the GPU to recover.  However, in the event of an unrecoverable error,
1353  * the driver provides an interface to reboot the system automatically
1354  * in that event.
1355  *
1356  * The following file in debugfs provides that interface:
1357  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1358  *
1359  * Usage:
1360  *
1361  * .. code-block:: bash
1362  *
1363  *      echo true > .../ras/auto_reboot
1364  *
1365  */
1366 /* debugfs begin */
1367 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1368 {
1369         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1370         struct drm_minor  *minor = adev_to_drm(adev)->primary;
1371         struct dentry     *dir;
1372
1373         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1374         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1375                             &amdgpu_ras_debugfs_ctrl_ops);
1376         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1377                             &amdgpu_ras_debugfs_eeprom_ops);
1378         debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1379                            &con->bad_page_cnt_threshold);
1380         debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1381         debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1382         debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1383                             &amdgpu_ras_debugfs_eeprom_size_ops);
1384         con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1385                                                        S_IRUGO, dir, adev,
1386                                                        &amdgpu_ras_debugfs_eeprom_table_ops);
1387         amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
1388
1389         /*
1390          * After one uncorrectable error happens, usually GPU recovery will
1391          * be scheduled. But due to the known problem in GPU recovery failing
1392          * to bring GPU back, below interface provides one direct way to
1393          * user to reboot system automatically in such case within
1394          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1395          * will never be called.
1396          */
1397         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1398
1399         /*
1400          * User could set this not to clean up hardware's error count register
1401          * of RAS IPs during ras recovery.
1402          */
1403         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1404                             &con->disable_ras_err_cnt_harvest);
1405         return dir;
1406 }
1407
1408 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1409                                       struct ras_fs_if *head,
1410                                       struct dentry *dir)
1411 {
1412         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1413
1414         if (!obj || !dir)
1415                 return;
1416
1417         get_obj(obj);
1418
1419         memcpy(obj->fs_data.debugfs_name,
1420                         head->debugfs_name,
1421                         sizeof(obj->fs_data.debugfs_name));
1422
1423         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1424                             obj, &amdgpu_ras_debugfs_ops);
1425 }
1426
1427 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1428 {
1429         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1430         struct dentry *dir;
1431         struct ras_manager *obj;
1432         struct ras_fs_if fs_info;
1433
1434         /*
1435          * it won't be called in resume path, no need to check
1436          * suspend and gpu reset status
1437          */
1438         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1439                 return;
1440
1441         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1442
1443         list_for_each_entry(obj, &con->head, node) {
1444                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1445                         (obj->attr_inuse == 1)) {
1446                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1447                                         get_ras_block_str(&obj->head));
1448                         fs_info.head = obj->head;
1449                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1450                 }
1451         }
1452 }
1453
1454 /* debugfs end */
1455
1456 /* ras fs */
1457 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1458                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1459 static DEVICE_ATTR(features, S_IRUGO,
1460                 amdgpu_ras_sysfs_features_read, NULL);
1461 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1462 {
1463         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1464         struct attribute_group group = {
1465                 .name = RAS_FS_NAME,
1466         };
1467         struct attribute *attrs[] = {
1468                 &con->features_attr.attr,
1469                 NULL
1470         };
1471         struct bin_attribute *bin_attrs[] = {
1472                 NULL,
1473                 NULL,
1474         };
1475         int r;
1476
1477         /* add features entry */
1478         con->features_attr = dev_attr_features;
1479         group.attrs = attrs;
1480         sysfs_attr_init(attrs[0]);
1481
1482         if (amdgpu_bad_page_threshold != 0) {
1483                 /* add bad_page_features entry */
1484                 bin_attr_gpu_vram_bad_pages.private = NULL;
1485                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1486                 bin_attrs[0] = &con->badpages_attr;
1487                 group.bin_attrs = bin_attrs;
1488                 sysfs_bin_attr_init(bin_attrs[0]);
1489         }
1490
1491         r = sysfs_create_group(&adev->dev->kobj, &group);
1492         if (r)
1493                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1494
1495         return 0;
1496 }
1497
1498 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1499 {
1500         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1501         struct ras_manager *con_obj, *ip_obj, *tmp;
1502
1503         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1504                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1505                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1506                         if (ip_obj)
1507                                 put_obj(ip_obj);
1508                 }
1509         }
1510
1511         amdgpu_ras_sysfs_remove_all(adev);
1512         return 0;
1513 }
1514 /* ras fs end */
1515
1516 /* ih begin */
1517 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1518 {
1519         struct ras_ih_data *data = &obj->ih_data;
1520         struct amdgpu_iv_entry entry;
1521         int ret;
1522         struct ras_err_data err_data = {0, 0, 0, NULL};
1523
1524         while (data->rptr != data->wptr) {
1525                 rmb();
1526                 memcpy(&entry, &data->ring[data->rptr],
1527                                 data->element_size);
1528
1529                 wmb();
1530                 data->rptr = (data->aligned_element_size +
1531                                 data->rptr) % data->ring_size;
1532
1533                 if (data->cb) {
1534                         if (amdgpu_ras_is_poison_mode_supported(obj->adev) &&
1535                             obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1536                                 dev_info(obj->adev->dev,
1537                                                 "Poison is created, no user action is needed.\n");
1538                         else {
1539                                 /* Let IP handle its data, maybe we need get the output
1540                                  * from the callback to udpate the error type/count, etc
1541                                  */
1542                                 memset(&err_data, 0, sizeof(err_data));
1543                                 ret = data->cb(obj->adev, &err_data, &entry);
1544                                 /* ue will trigger an interrupt, and in that case
1545                                  * we need do a reset to recovery the whole system.
1546                                  * But leave IP do that recovery, here we just dispatch
1547                                  * the error.
1548                                  */
1549                                 if (ret == AMDGPU_RAS_SUCCESS) {
1550                                         /* these counts could be left as 0 if
1551                                          * some blocks do not count error number
1552                                          */
1553                                         obj->err_data.ue_count += err_data.ue_count;
1554                                         obj->err_data.ce_count += err_data.ce_count;
1555                                 }
1556                         }
1557                 }
1558         }
1559 }
1560
1561 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1562 {
1563         struct ras_ih_data *data =
1564                 container_of(work, struct ras_ih_data, ih_work);
1565         struct ras_manager *obj =
1566                 container_of(data, struct ras_manager, ih_data);
1567
1568         amdgpu_ras_interrupt_handler(obj);
1569 }
1570
1571 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1572                 struct ras_dispatch_if *info)
1573 {
1574         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1575         struct ras_ih_data *data = &obj->ih_data;
1576
1577         if (!obj)
1578                 return -EINVAL;
1579
1580         if (data->inuse == 0)
1581                 return 0;
1582
1583         /* Might be overflow... */
1584         memcpy(&data->ring[data->wptr], info->entry,
1585                         data->element_size);
1586
1587         wmb();
1588         data->wptr = (data->aligned_element_size +
1589                         data->wptr) % data->ring_size;
1590
1591         schedule_work(&data->ih_work);
1592
1593         return 0;
1594 }
1595
1596 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1597                 struct ras_ih_if *info)
1598 {
1599         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1600         struct ras_ih_data *data;
1601
1602         if (!obj)
1603                 return -EINVAL;
1604
1605         data = &obj->ih_data;
1606         if (data->inuse == 0)
1607                 return 0;
1608
1609         cancel_work_sync(&data->ih_work);
1610
1611         kfree(data->ring);
1612         memset(data, 0, sizeof(*data));
1613         put_obj(obj);
1614
1615         return 0;
1616 }
1617
1618 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1619                 struct ras_ih_if *info)
1620 {
1621         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1622         struct ras_ih_data *data;
1623
1624         if (!obj) {
1625                 /* in case we registe the IH before enable ras feature */
1626                 obj = amdgpu_ras_create_obj(adev, &info->head);
1627                 if (!obj)
1628                         return -EINVAL;
1629         } else
1630                 get_obj(obj);
1631
1632         data = &obj->ih_data;
1633         /* add the callback.etc */
1634         *data = (struct ras_ih_data) {
1635                 .inuse = 0,
1636                 .cb = info->cb,
1637                 .element_size = sizeof(struct amdgpu_iv_entry),
1638                 .rptr = 0,
1639                 .wptr = 0,
1640         };
1641
1642         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1643
1644         data->aligned_element_size = ALIGN(data->element_size, 8);
1645         /* the ring can store 64 iv entries. */
1646         data->ring_size = 64 * data->aligned_element_size;
1647         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1648         if (!data->ring) {
1649                 put_obj(obj);
1650                 return -ENOMEM;
1651         }
1652
1653         /* IH is ready */
1654         data->inuse = 1;
1655
1656         return 0;
1657 }
1658
1659 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1660 {
1661         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1662         struct ras_manager *obj, *tmp;
1663
1664         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1665                 struct ras_ih_if info = {
1666                         .head = obj->head,
1667                 };
1668                 amdgpu_ras_interrupt_remove_handler(adev, &info);
1669         }
1670
1671         return 0;
1672 }
1673 /* ih end */
1674
1675 /* traversal all IPs except NBIO to query error counter */
1676 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1677 {
1678         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1679         struct ras_manager *obj;
1680
1681         if (!adev->ras_enabled || !con)
1682                 return;
1683
1684         list_for_each_entry(obj, &con->head, node) {
1685                 struct ras_query_if info = {
1686                         .head = obj->head,
1687                 };
1688
1689                 /*
1690                  * PCIE_BIF IP has one different isr by ras controller
1691                  * interrupt, the specific ras counter query will be
1692                  * done in that isr. So skip such block from common
1693                  * sync flood interrupt isr calling.
1694                  */
1695                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1696                         continue;
1697
1698                 /*
1699                  * this is a workaround for aldebaran, skip send msg to
1700                  * smu to get ecc_info table due to smu handle get ecc
1701                  * info table failed temporarily.
1702                  * should be removed until smu fix handle ecc_info table.
1703                  */
1704                 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
1705                         (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)))
1706                         continue;
1707
1708                 amdgpu_ras_query_error_status(adev, &info);
1709         }
1710 }
1711
1712 /* Parse RdRspStatus and WrRspStatus */
1713 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1714                                           struct ras_query_if *info)
1715 {
1716         struct amdgpu_ras_block_object *block_obj;
1717         /*
1718          * Only two block need to query read/write
1719          * RspStatus at current state
1720          */
1721         if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
1722                 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
1723                 return;
1724
1725         block_obj = amdgpu_ras_get_ras_block(adev,
1726                                         info->head.block,
1727                                         info->head.sub_block_index);
1728
1729         if (!block_obj || !block_obj->hw_ops) {
1730                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1731                              get_ras_block_str(&info->head));
1732                 return;
1733         }
1734
1735         if (block_obj->hw_ops->query_ras_error_status)
1736                 block_obj->hw_ops->query_ras_error_status(adev);
1737
1738 }
1739
1740 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1741 {
1742         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1743         struct ras_manager *obj;
1744
1745         if (!adev->ras_enabled || !con)
1746                 return;
1747
1748         list_for_each_entry(obj, &con->head, node) {
1749                 struct ras_query_if info = {
1750                         .head = obj->head,
1751                 };
1752
1753                 amdgpu_ras_error_status_query(adev, &info);
1754         }
1755 }
1756
1757 /* recovery begin */
1758
1759 /* return 0 on success.
1760  * caller need free bps.
1761  */
1762 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1763                 struct ras_badpage **bps, unsigned int *count)
1764 {
1765         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1766         struct ras_err_handler_data *data;
1767         int i = 0;
1768         int ret = 0, status;
1769
1770         if (!con || !con->eh_data || !bps || !count)
1771                 return -EINVAL;
1772
1773         mutex_lock(&con->recovery_lock);
1774         data = con->eh_data;
1775         if (!data || data->count == 0) {
1776                 *bps = NULL;
1777                 ret = -EINVAL;
1778                 goto out;
1779         }
1780
1781         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1782         if (!*bps) {
1783                 ret = -ENOMEM;
1784                 goto out;
1785         }
1786
1787         for (; i < data->count; i++) {
1788                 (*bps)[i] = (struct ras_badpage){
1789                         .bp = data->bps[i].retired_page,
1790                         .size = AMDGPU_GPU_PAGE_SIZE,
1791                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1792                 };
1793                 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
1794                                 data->bps[i].retired_page);
1795                 if (status == -EBUSY)
1796                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1797                 else if (status == -ENOENT)
1798                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1799         }
1800
1801         *count = data->count;
1802 out:
1803         mutex_unlock(&con->recovery_lock);
1804         return ret;
1805 }
1806
1807 static void amdgpu_ras_do_recovery(struct work_struct *work)
1808 {
1809         struct amdgpu_ras *ras =
1810                 container_of(work, struct amdgpu_ras, recovery_work);
1811         struct amdgpu_device *remote_adev = NULL;
1812         struct amdgpu_device *adev = ras->adev;
1813         struct list_head device_list, *device_list_handle =  NULL;
1814
1815         if (!ras->disable_ras_err_cnt_harvest) {
1816                 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1817
1818                 /* Build list of devices to query RAS related errors */
1819                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1820                         device_list_handle = &hive->device_list;
1821                 } else {
1822                         INIT_LIST_HEAD(&device_list);
1823                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
1824                         device_list_handle = &device_list;
1825                 }
1826
1827                 list_for_each_entry(remote_adev,
1828                                 device_list_handle, gmc.xgmi.head) {
1829                         amdgpu_ras_query_err_status(remote_adev);
1830                         amdgpu_ras_log_on_err_counter(remote_adev);
1831                 }
1832
1833                 amdgpu_put_xgmi_hive(hive);
1834         }
1835
1836         if (amdgpu_device_should_recover_gpu(ras->adev))
1837                 amdgpu_device_gpu_recover(ras->adev, NULL);
1838         atomic_set(&ras->in_recovery, 0);
1839 }
1840
1841 /* alloc/realloc bps array */
1842 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1843                 struct ras_err_handler_data *data, int pages)
1844 {
1845         unsigned int old_space = data->count + data->space_left;
1846         unsigned int new_space = old_space + pages;
1847         unsigned int align_space = ALIGN(new_space, 512);
1848         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1849
1850         if (!bps) {
1851                 kfree(bps);
1852                 return -ENOMEM;
1853         }
1854
1855         if (data->bps) {
1856                 memcpy(bps, data->bps,
1857                                 data->count * sizeof(*data->bps));
1858                 kfree(data->bps);
1859         }
1860
1861         data->bps = bps;
1862         data->space_left += align_space - old_space;
1863         return 0;
1864 }
1865
1866 /* it deal with vram only. */
1867 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1868                 struct eeprom_table_record *bps, int pages)
1869 {
1870         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1871         struct ras_err_handler_data *data;
1872         int ret = 0;
1873         uint32_t i;
1874
1875         if (!con || !con->eh_data || !bps || pages <= 0)
1876                 return 0;
1877
1878         mutex_lock(&con->recovery_lock);
1879         data = con->eh_data;
1880         if (!data)
1881                 goto out;
1882
1883         for (i = 0; i < pages; i++) {
1884                 if (amdgpu_ras_check_bad_page_unlock(con,
1885                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1886                         continue;
1887
1888                 if (!data->space_left &&
1889                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1890                         ret = -ENOMEM;
1891                         goto out;
1892                 }
1893
1894                 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,
1895                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1896                         AMDGPU_GPU_PAGE_SIZE);
1897
1898                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1899                 data->count++;
1900                 data->space_left--;
1901         }
1902 out:
1903         mutex_unlock(&con->recovery_lock);
1904
1905         return ret;
1906 }
1907
1908 /*
1909  * write error record array to eeprom, the function should be
1910  * protected by recovery_lock
1911  */
1912 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1913 {
1914         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1915         struct ras_err_handler_data *data;
1916         struct amdgpu_ras_eeprom_control *control;
1917         int save_count;
1918
1919         if (!con || !con->eh_data)
1920                 return 0;
1921
1922         mutex_lock(&con->recovery_lock);
1923         control = &con->eeprom_control;
1924         data = con->eh_data;
1925         save_count = data->count - control->ras_num_recs;
1926         mutex_unlock(&con->recovery_lock);
1927         /* only new entries are saved */
1928         if (save_count > 0) {
1929                 if (amdgpu_ras_eeprom_append(control,
1930                                              &data->bps[control->ras_num_recs],
1931                                              save_count)) {
1932                         dev_err(adev->dev, "Failed to save EEPROM table data!");
1933                         return -EIO;
1934                 }
1935
1936                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
1937         }
1938
1939         return 0;
1940 }
1941
1942 /*
1943  * read error record array in eeprom and reserve enough space for
1944  * storing new bad pages
1945  */
1946 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1947 {
1948         struct amdgpu_ras_eeprom_control *control =
1949                 &adev->psp.ras_context.ras->eeprom_control;
1950         struct eeprom_table_record *bps;
1951         int ret;
1952
1953         /* no bad page record, skip eeprom access */
1954         if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
1955                 return 0;
1956
1957         bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
1958         if (!bps)
1959                 return -ENOMEM;
1960
1961         ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
1962         if (ret)
1963                 dev_err(adev->dev, "Failed to load EEPROM table records!");
1964         else
1965                 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
1966
1967         kfree(bps);
1968         return ret;
1969 }
1970
1971 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
1972                                 uint64_t addr)
1973 {
1974         struct ras_err_handler_data *data = con->eh_data;
1975         int i;
1976
1977         addr >>= AMDGPU_GPU_PAGE_SHIFT;
1978         for (i = 0; i < data->count; i++)
1979                 if (addr == data->bps[i].retired_page)
1980                         return true;
1981
1982         return false;
1983 }
1984
1985 /*
1986  * check if an address belongs to bad page
1987  *
1988  * Note: this check is only for umc block
1989  */
1990 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
1991                                 uint64_t addr)
1992 {
1993         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1994         bool ret = false;
1995
1996         if (!con || !con->eh_data)
1997                 return ret;
1998
1999         mutex_lock(&con->recovery_lock);
2000         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
2001         mutex_unlock(&con->recovery_lock);
2002         return ret;
2003 }
2004
2005 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
2006                                           uint32_t max_count)
2007 {
2008         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2009
2010         /*
2011          * Justification of value bad_page_cnt_threshold in ras structure
2012          *
2013          * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
2014          * in eeprom, and introduce two scenarios accordingly.
2015          *
2016          * Bad page retirement enablement:
2017          *    - If amdgpu_bad_page_threshold = -1,
2018          *      bad_page_cnt_threshold = typical value by formula.
2019          *
2020          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
2021          *      max record length in eeprom, use it directly.
2022          *
2023          * Bad page retirement disablement:
2024          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
2025          *      functionality is disabled, and bad_page_cnt_threshold will
2026          *      take no effect.
2027          */
2028
2029         if (amdgpu_bad_page_threshold < 0) {
2030                 u64 val = adev->gmc.mc_vram_size;
2031
2032                 do_div(val, RAS_BAD_PAGE_COVER);
2033                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
2034                                                   max_count);
2035         } else {
2036                 con->bad_page_cnt_threshold = min_t(int, max_count,
2037                                                     amdgpu_bad_page_threshold);
2038         }
2039 }
2040
2041 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
2042 {
2043         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2044         struct ras_err_handler_data **data;
2045         u32  max_eeprom_records_count = 0;
2046         bool exc_err_limit = false;
2047         int ret;
2048
2049         if (!con)
2050                 return 0;
2051
2052         /* Allow access to RAS EEPROM via debugfs, when the ASIC
2053          * supports RAS and debugfs is enabled, but when
2054          * adev->ras_enabled is unset, i.e. when "ras_enable"
2055          * module parameter is set to 0.
2056          */
2057         con->adev = adev;
2058
2059         if (!adev->ras_enabled)
2060                 return 0;
2061
2062         data = &con->eh_data;
2063         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
2064         if (!*data) {
2065                 ret = -ENOMEM;
2066                 goto out;
2067         }
2068
2069         mutex_init(&con->recovery_lock);
2070         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2071         atomic_set(&con->in_recovery, 0);
2072
2073         max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count();
2074         amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
2075
2076         /* Todo: During test the SMU might fail to read the eeprom through I2C
2077          * when the GPU is pending on XGMI reset during probe time
2078          * (Mostly after second bus reset), skip it now
2079          */
2080         if (adev->gmc.xgmi.pending_reset)
2081                 return 0;
2082         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2083         /*
2084          * This calling fails when exc_err_limit is true or
2085          * ret != 0.
2086          */
2087         if (exc_err_limit || ret)
2088                 goto free;
2089
2090         if (con->eeprom_control.ras_num_recs) {
2091                 ret = amdgpu_ras_load_bad_pages(adev);
2092                 if (ret)
2093                         goto free;
2094
2095                 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
2096         }
2097
2098 #ifdef CONFIG_X86_MCE_AMD
2099         if ((adev->asic_type == CHIP_ALDEBARAN) &&
2100             (adev->gmc.xgmi.connected_to_cpu))
2101                 amdgpu_register_bad_pages_mca_notifier(adev);
2102 #endif
2103         return 0;
2104
2105 free:
2106         kfree((*data)->bps);
2107         kfree(*data);
2108         con->eh_data = NULL;
2109 out:
2110         dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
2111
2112         /*
2113          * Except error threshold exceeding case, other failure cases in this
2114          * function would not fail amdgpu driver init.
2115          */
2116         if (!exc_err_limit)
2117                 ret = 0;
2118         else
2119                 ret = -EINVAL;
2120
2121         return ret;
2122 }
2123
2124 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2125 {
2126         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2127         struct ras_err_handler_data *data = con->eh_data;
2128
2129         /* recovery_init failed to init it, fini is useless */
2130         if (!data)
2131                 return 0;
2132
2133         cancel_work_sync(&con->recovery_work);
2134
2135         mutex_lock(&con->recovery_lock);
2136         con->eh_data = NULL;
2137         kfree(data->bps);
2138         kfree(data);
2139         mutex_unlock(&con->recovery_lock);
2140
2141         return 0;
2142 }
2143 /* recovery end */
2144
2145 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2146 {
2147         return adev->asic_type == CHIP_VEGA10 ||
2148                 adev->asic_type == CHIP_VEGA20 ||
2149                 adev->asic_type == CHIP_ARCTURUS ||
2150                 adev->asic_type == CHIP_ALDEBARAN ||
2151                 adev->asic_type == CHIP_SIENNA_CICHLID;
2152 }
2153
2154 /*
2155  * this is workaround for vega20 workstation sku,
2156  * force enable gfx ras, ignore vbios gfx ras flag
2157  * due to GC EDC can not write
2158  */
2159 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2160 {
2161         struct atom_context *ctx = adev->mode_info.atom_context;
2162
2163         if (!ctx)
2164                 return;
2165
2166         if (strnstr(ctx->vbios_version, "D16406",
2167                     sizeof(ctx->vbios_version)) ||
2168                 strnstr(ctx->vbios_version, "D36002",
2169                         sizeof(ctx->vbios_version)))
2170                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2171 }
2172
2173 /*
2174  * check hardware's ras ability which will be saved in hw_supported.
2175  * if hardware does not support ras, we can skip some ras initializtion and
2176  * forbid some ras operations from IP.
2177  * if software itself, say boot parameter, limit the ras ability. We still
2178  * need allow IP do some limited operations, like disable. In such case,
2179  * we have to initialize ras as normal. but need check if operation is
2180  * allowed or not in each function.
2181  */
2182 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2183 {
2184         adev->ras_hw_enabled = adev->ras_enabled = 0;
2185
2186         if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
2187             !amdgpu_ras_asic_supported(adev))
2188                 return;
2189
2190         if (!adev->gmc.xgmi.connected_to_cpu) {
2191                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2192                         dev_info(adev->dev, "MEM ECC is active.\n");
2193                         adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2194                                                    1 << AMDGPU_RAS_BLOCK__DF);
2195                 } else {
2196                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2197                 }
2198
2199                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2200                         dev_info(adev->dev, "SRAM ECC is active.\n");
2201                         adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2202                                                     1 << AMDGPU_RAS_BLOCK__DF);
2203                 } else {
2204                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2205                 }
2206         } else {
2207                 /* driver only manages a few IP blocks RAS feature
2208                  * when GPU is connected cpu through XGMI */
2209                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2210                                            1 << AMDGPU_RAS_BLOCK__SDMA |
2211                                            1 << AMDGPU_RAS_BLOCK__MMHUB);
2212         }
2213
2214         amdgpu_ras_get_quirks(adev);
2215
2216         /* hw_supported needs to be aligned with RAS block mask. */
2217         adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2218
2219         adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2220                 adev->ras_hw_enabled & amdgpu_ras_mask;
2221 }
2222
2223 static void amdgpu_ras_counte_dw(struct work_struct *work)
2224 {
2225         struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2226                                               ras_counte_delay_work.work);
2227         struct amdgpu_device *adev = con->adev;
2228         struct drm_device *dev = adev_to_drm(adev);
2229         unsigned long ce_count, ue_count;
2230         int res;
2231
2232         res = pm_runtime_get_sync(dev->dev);
2233         if (res < 0)
2234                 goto Out;
2235
2236         /* Cache new values.
2237          */
2238         if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) {
2239                 atomic_set(&con->ras_ce_count, ce_count);
2240                 atomic_set(&con->ras_ue_count, ue_count);
2241         }
2242
2243         pm_runtime_mark_last_busy(dev->dev);
2244 Out:
2245         pm_runtime_put_autosuspend(dev->dev);
2246 }
2247
2248 int amdgpu_ras_init(struct amdgpu_device *adev)
2249 {
2250         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2251         int r;
2252         bool df_poison, umc_poison;
2253
2254         if (con)
2255                 return 0;
2256
2257         con = kmalloc(sizeof(struct amdgpu_ras) +
2258                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
2259                         sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
2260                         GFP_KERNEL|__GFP_ZERO);
2261         if (!con)
2262                 return -ENOMEM;
2263
2264         con->adev = adev;
2265         INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2266         atomic_set(&con->ras_ce_count, 0);
2267         atomic_set(&con->ras_ue_count, 0);
2268
2269         con->objs = (struct ras_manager *)(con + 1);
2270
2271         amdgpu_ras_set_context(adev, con);
2272
2273         amdgpu_ras_check_supported(adev);
2274
2275         if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2276                 /* set gfx block ras context feature for VEGA20 Gaming
2277                  * send ras disable cmd to ras ta during ras late init.
2278                  */
2279                 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2280                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2281
2282                         return 0;
2283                 }
2284
2285                 r = 0;
2286                 goto release_con;
2287         }
2288
2289         con->features = 0;
2290         INIT_LIST_HEAD(&con->head);
2291         /* Might need get this flag from vbios. */
2292         con->flags = RAS_DEFAULT_FLAGS;
2293
2294         /* initialize nbio ras function ahead of any other
2295          * ras functions so hardware fatal error interrupt
2296          * can be enabled as early as possible */
2297         switch (adev->asic_type) {
2298         case CHIP_VEGA20:
2299         case CHIP_ARCTURUS:
2300         case CHIP_ALDEBARAN:
2301                 if (!adev->gmc.xgmi.connected_to_cpu) {
2302                         adev->nbio.ras = &nbio_v7_4_ras;
2303                         amdgpu_ras_register_ras_block(adev, &adev->nbio.ras->ras_block);
2304                 }
2305                 break;
2306         default:
2307                 /* nbio ras is not available */
2308                 break;
2309         }
2310
2311         if (adev->nbio.ras &&
2312             adev->nbio.ras->init_ras_controller_interrupt) {
2313                 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
2314                 if (r)
2315                         goto release_con;
2316         }
2317
2318         if (adev->nbio.ras &&
2319             adev->nbio.ras->init_ras_err_event_athub_interrupt) {
2320                 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
2321                 if (r)
2322                         goto release_con;
2323         }
2324
2325         /* Init poison supported flag, the default value is false */
2326         if (adev->gmc.xgmi.connected_to_cpu) {
2327                 /* enabled by default when GPU is connected to CPU */
2328                 con->poison_supported = true;
2329         }
2330         else if (adev->df.funcs &&
2331             adev->df.funcs->query_ras_poison_mode &&
2332             adev->umc.ras &&
2333             adev->umc.ras->query_ras_poison_mode) {
2334                 df_poison =
2335                         adev->df.funcs->query_ras_poison_mode(adev);
2336                 umc_poison =
2337                         adev->umc.ras->query_ras_poison_mode(adev);
2338                 /* Only poison is set in both DF and UMC, we can support it */
2339                 if (df_poison && umc_poison)
2340                         con->poison_supported = true;
2341                 else if (df_poison != umc_poison)
2342                         dev_warn(adev->dev, "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2343                                         df_poison, umc_poison);
2344         }
2345
2346         if (amdgpu_ras_fs_init(adev)) {
2347                 r = -EINVAL;
2348                 goto release_con;
2349         }
2350
2351         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2352                  "hardware ability[%x] ras_mask[%x]\n",
2353                  adev->ras_hw_enabled, adev->ras_enabled);
2354
2355         return 0;
2356 release_con:
2357         amdgpu_ras_set_context(adev, NULL);
2358         kfree(con);
2359
2360         return r;
2361 }
2362
2363 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2364 {
2365         if (adev->gmc.xgmi.connected_to_cpu)
2366                 return 1;
2367         return 0;
2368 }
2369
2370 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2371                                         struct ras_common_if *ras_block)
2372 {
2373         struct ras_query_if info = {
2374                 .head = *ras_block,
2375         };
2376
2377         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2378                 return 0;
2379
2380         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2381                 DRM_WARN("RAS init harvest failure");
2382
2383         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2384                 DRM_WARN("RAS init harvest reset failure");
2385
2386         return 0;
2387 }
2388
2389 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2390 {
2391        struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2392
2393        if (!con)
2394                return false;
2395
2396        return con->poison_supported;
2397 }
2398
2399 /* helper function to handle common stuff in ip late init phase */
2400 int amdgpu_ras_late_init(struct amdgpu_device *adev,
2401                          struct ras_common_if *ras_block,
2402                          struct ras_fs_if *fs_info,
2403                          struct ras_ih_if *ih_info)
2404 {
2405         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2406         unsigned long ue_count, ce_count;
2407         int r;
2408
2409         /* disable RAS feature per IP block if it is not supported */
2410         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2411                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2412                 return 0;
2413         }
2414
2415         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2416         if (r) {
2417                 if (adev->in_suspend || amdgpu_in_reset(adev)) {
2418                         /* in resume phase, if fail to enable ras,
2419                          * clean up all ras fs nodes, and disable ras */
2420                         goto cleanup;
2421                 } else
2422                         return r;
2423         }
2424
2425         /* check for errors on warm reset edc persisant supported ASIC */
2426         amdgpu_persistent_edc_harvesting(adev, ras_block);
2427
2428         /* in resume phase, no need to create ras fs node */
2429         if (adev->in_suspend || amdgpu_in_reset(adev))
2430                 return 0;
2431
2432         if (ih_info->cb) {
2433                 r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
2434                 if (r)
2435                         goto interrupt;
2436         }
2437
2438         r = amdgpu_ras_sysfs_create(adev, fs_info);
2439         if (r)
2440                 goto sysfs;
2441
2442         /* Those are the cached values at init.
2443          */
2444         if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) {
2445                 atomic_set(&con->ras_ce_count, ce_count);
2446                 atomic_set(&con->ras_ue_count, ue_count);
2447         }
2448
2449         return 0;
2450 cleanup:
2451         amdgpu_ras_sysfs_remove(adev, ras_block);
2452 sysfs:
2453         if (ih_info->cb)
2454                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2455 interrupt:
2456         amdgpu_ras_feature_enable(adev, ras_block, 0);
2457         return r;
2458 }
2459
2460 /* helper function to remove ras fs node and interrupt handler */
2461 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
2462                           struct ras_common_if *ras_block,
2463                           struct ras_ih_if *ih_info)
2464 {
2465         if (!ras_block || !ih_info)
2466                 return;
2467
2468         amdgpu_ras_sysfs_remove(adev, ras_block);
2469         if (ih_info->cb)
2470                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2471 }
2472
2473 /* do some init work after IP late init as dependence.
2474  * and it runs in resume/gpu reset/booting up cases.
2475  */
2476 void amdgpu_ras_resume(struct amdgpu_device *adev)
2477 {
2478         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2479         struct ras_manager *obj, *tmp;
2480
2481         if (!adev->ras_enabled || !con) {
2482                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2483                 amdgpu_release_ras_context(adev);
2484
2485                 return;
2486         }
2487
2488         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2489                 /* Set up all other IPs which are not implemented. There is a
2490                  * tricky thing that IP's actual ras error type should be
2491                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2492                  * ERROR_NONE make sense anyway.
2493                  */
2494                 amdgpu_ras_enable_all_features(adev, 1);
2495
2496                 /* We enable ras on all hw_supported block, but as boot
2497                  * parameter might disable some of them and one or more IP has
2498                  * not implemented yet. So we disable them on behalf.
2499                  */
2500                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2501                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2502                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2503                                 /* there should be no any reference. */
2504                                 WARN_ON(alive_obj(obj));
2505                         }
2506                 }
2507         }
2508 }
2509
2510 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2511 {
2512         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2513
2514         if (!adev->ras_enabled || !con)
2515                 return;
2516
2517         amdgpu_ras_disable_all_features(adev, 0);
2518         /* Make sure all ras objects are disabled. */
2519         if (con->features)
2520                 amdgpu_ras_disable_all_features(adev, 1);
2521 }
2522
2523 /* do some fini work before IP fini as dependence */
2524 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2525 {
2526         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2527
2528         if (!adev->ras_enabled || !con)
2529                 return 0;
2530
2531
2532         /* Need disable ras on all IPs here before ip [hw/sw]fini */
2533         amdgpu_ras_disable_all_features(adev, 0);
2534         amdgpu_ras_recovery_fini(adev);
2535         return 0;
2536 }
2537
2538 int amdgpu_ras_fini(struct amdgpu_device *adev)
2539 {
2540         struct amdgpu_ras_block_list *ras_node, *tmp;
2541         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2542
2543         if (!adev->ras_enabled || !con)
2544                 return 0;
2545
2546         amdgpu_ras_fs_fini(adev);
2547         amdgpu_ras_interrupt_remove_all(adev);
2548
2549         WARN(con->features, "Feature mask is not cleared");
2550
2551         if (con->features)
2552                 amdgpu_ras_disable_all_features(adev, 1);
2553
2554         cancel_delayed_work_sync(&con->ras_counte_delay_work);
2555
2556         amdgpu_ras_set_context(adev, NULL);
2557         kfree(con);
2558
2559         /* Clear ras blocks from ras_list and free ras block list node */
2560         list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
2561                 list_del(&ras_node->node);
2562                 kfree(ras_node);
2563         }
2564
2565         return 0;
2566 }
2567
2568 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2569 {
2570         amdgpu_ras_check_supported(adev);
2571         if (!adev->ras_hw_enabled)
2572                 return;
2573
2574         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2575                 dev_info(adev->dev, "uncorrectable hardware error"
2576                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2577
2578                 amdgpu_ras_reset_gpu(adev);
2579         }
2580 }
2581
2582 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2583 {
2584         if (adev->asic_type == CHIP_VEGA20 &&
2585             adev->pm.fw_version <= 0x283400) {
2586                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2587                                 amdgpu_ras_intr_triggered();
2588         }
2589
2590         return false;
2591 }
2592
2593 void amdgpu_release_ras_context(struct amdgpu_device *adev)
2594 {
2595         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2596
2597         if (!con)
2598                 return;
2599
2600         if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
2601                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2602                 amdgpu_ras_set_context(adev, NULL);
2603                 kfree(con);
2604         }
2605 }
2606
2607 #ifdef CONFIG_X86_MCE_AMD
2608 static struct amdgpu_device *find_adev(uint32_t node_id)
2609 {
2610         int i;
2611         struct amdgpu_device *adev = NULL;
2612
2613         for (i = 0; i < mce_adev_list.num_gpu; i++) {
2614                 adev = mce_adev_list.devs[i];
2615
2616                 if (adev && adev->gmc.xgmi.connected_to_cpu &&
2617                     adev->gmc.xgmi.physical_node_id == node_id)
2618                         break;
2619                 adev = NULL;
2620         }
2621
2622         return adev;
2623 }
2624
2625 #define GET_MCA_IPID_GPUID(m)   (((m) >> 44) & 0xF)
2626 #define GET_UMC_INST(m)         (((m) >> 21) & 0x7)
2627 #define GET_CHAN_INDEX(m)       ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
2628 #define GPU_ID_OFFSET           8
2629
2630 static int amdgpu_bad_page_notifier(struct notifier_block *nb,
2631                                     unsigned long val, void *data)
2632 {
2633         struct mce *m = (struct mce *)data;
2634         struct amdgpu_device *adev = NULL;
2635         uint32_t gpu_id = 0;
2636         uint32_t umc_inst = 0;
2637         uint32_t ch_inst, channel_index = 0;
2638         struct ras_err_data err_data = {0, 0, 0, NULL};
2639         struct eeprom_table_record err_rec;
2640         uint64_t retired_page;
2641
2642         /*
2643          * If the error was generated in UMC_V2, which belongs to GPU UMCs,
2644          * and error occurred in DramECC (Extended error code = 0) then only
2645          * process the error, else bail out.
2646          */
2647         if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
2648                     (XEC(m->status, 0x3f) == 0x0)))
2649                 return NOTIFY_DONE;
2650
2651         /*
2652          * If it is correctable error, return.
2653          */
2654         if (mce_is_correctable(m))
2655                 return NOTIFY_OK;
2656
2657         /*
2658          * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
2659          */
2660         gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
2661
2662         adev = find_adev(gpu_id);
2663         if (!adev) {
2664                 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
2665                                                                 gpu_id);
2666                 return NOTIFY_DONE;
2667         }
2668
2669         /*
2670          * If it is uncorrectable error, then find out UMC instance and
2671          * channel index.
2672          */
2673         umc_inst = GET_UMC_INST(m->ipid);
2674         ch_inst = GET_CHAN_INDEX(m->ipid);
2675
2676         dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
2677                              umc_inst, ch_inst);
2678
2679         /*
2680          * Translate UMC channel address to Physical address
2681          */
2682         channel_index =
2683                 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num
2684                                           + ch_inst];
2685
2686         retired_page = ADDR_OF_8KB_BLOCK(m->addr) |
2687                         ADDR_OF_256B_BLOCK(channel_index) |
2688                         OFFSET_IN_256B_BLOCK(m->addr);
2689
2690         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
2691         err_data.err_addr = &err_rec;
2692         amdgpu_umc_fill_error_record(&err_data, m->addr,
2693                         retired_page, channel_index, umc_inst);
2694
2695         if (amdgpu_bad_page_threshold != 0) {
2696                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
2697                                                 err_data.err_addr_cnt);
2698                 amdgpu_ras_save_bad_pages(adev);
2699         }
2700
2701         return NOTIFY_OK;
2702 }
2703
2704 static struct notifier_block amdgpu_bad_page_nb = {
2705         .notifier_call  = amdgpu_bad_page_notifier,
2706         .priority       = MCE_PRIO_UC,
2707 };
2708
2709 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
2710 {
2711         /*
2712          * Add the adev to the mce_adev_list.
2713          * During mode2 reset, amdgpu device is temporarily
2714          * removed from the mgpu_info list which can cause
2715          * page retirement to fail.
2716          * Use this list instead of mgpu_info to find the amdgpu
2717          * device on which the UMC error was reported.
2718          */
2719         mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
2720
2721         /*
2722          * Register the x86 notifier only once
2723          * with MCE subsystem.
2724          */
2725         if (notifier_registered == false) {
2726                 mce_register_decode_chain(&amdgpu_bad_page_nb);
2727                 notifier_registered = true;
2728         }
2729 }
2730 #endif
2731
2732 struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
2733 {
2734         if (!adev)
2735                 return NULL;
2736
2737         return adev->psp.ras_context.ras;
2738 }
2739
2740 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
2741 {
2742         if (!adev)
2743                 return -EINVAL;
2744
2745         adev->psp.ras_context.ras = ras_con;
2746         return 0;
2747 }
2748
2749 /* check if ras is supported on block, say, sdma, gfx */
2750 int amdgpu_ras_is_supported(struct amdgpu_device *adev,
2751                 unsigned int block)
2752 {
2753         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2754
2755         if (block >= AMDGPU_RAS_BLOCK_COUNT)
2756                 return 0;
2757         return ras && (adev->ras_enabled & (1 << block));
2758 }
2759
2760 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
2761 {
2762         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2763
2764         if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
2765                 schedule_work(&ras->recovery_work);
2766         return 0;
2767 }
2768
2769
2770 /* Register each ip ras block into amdgpu ras */
2771 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
2772                 struct amdgpu_ras_block_object *ras_block_obj)
2773 {
2774         struct amdgpu_ras_block_list *ras_node;
2775         if (!adev || !ras_block_obj)
2776                 return -EINVAL;
2777
2778         if (!amdgpu_ras_asic_supported(adev))
2779                 return 0;
2780
2781         ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
2782         if (!ras_node)
2783                 return -ENOMEM;
2784
2785         INIT_LIST_HEAD(&ras_node->node);
2786         ras_node->ras_obj = ras_block_obj;
2787         list_add_tail(&ras_node->node, &adev->ras_list);
2788
2789         return 0;
2790 }