2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
27 * Kernel port Author: Dave Airlie
33 #include <drm/display/drm_dp_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fixed.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_fb_helper.h>
40 #include <drm/drm_framebuffer.h>
41 #include <drm/drm_plane_helper.h>
42 #include <drm/drm_probe_helper.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <linux/hrtimer.h>
46 #include "amdgpu_irq.h"
48 #include <drm/display/drm_dp_mst_helper.h>
49 #include "modules/inc/mod_freesync.h"
50 #include "amdgpu_dm_irq_params.h"
54 struct amdgpu_encoder;
58 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
59 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
60 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
61 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
63 #define to_dm_plane_state(x) container_of(x, struct dm_plane_state, base)
65 #define AMDGPU_MAX_HPD_PINS 6
66 #define AMDGPU_MAX_CRTCS 6
67 #define AMDGPU_MAX_PLANES 6
68 #define AMDGPU_MAX_AFMT_BLOCKS 9
70 enum amdgpu_rmx_type {
77 enum amdgpu_underscan_type {
83 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
84 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
93 AMDGPU_HPD_NONE = 0xff,
96 enum amdgpu_crtc_irq {
97 AMDGPU_CRTC_IRQ_VBLANK1 = 0,
98 AMDGPU_CRTC_IRQ_VBLANK2,
99 AMDGPU_CRTC_IRQ_VBLANK3,
100 AMDGPU_CRTC_IRQ_VBLANK4,
101 AMDGPU_CRTC_IRQ_VBLANK5,
102 AMDGPU_CRTC_IRQ_VBLANK6,
103 AMDGPU_CRTC_IRQ_VLINE1,
104 AMDGPU_CRTC_IRQ_VLINE2,
105 AMDGPU_CRTC_IRQ_VLINE3,
106 AMDGPU_CRTC_IRQ_VLINE4,
107 AMDGPU_CRTC_IRQ_VLINE5,
108 AMDGPU_CRTC_IRQ_VLINE6,
109 AMDGPU_CRTC_IRQ_NONE = 0xff
112 enum amdgpu_pageflip_irq {
113 AMDGPU_PAGEFLIP_IRQ_D1 = 0,
114 AMDGPU_PAGEFLIP_IRQ_D2,
115 AMDGPU_PAGEFLIP_IRQ_D3,
116 AMDGPU_PAGEFLIP_IRQ_D4,
117 AMDGPU_PAGEFLIP_IRQ_D5,
118 AMDGPU_PAGEFLIP_IRQ_D6,
119 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
122 enum amdgpu_flip_status {
125 AMDGPU_FLIP_SUBMITTED
128 #define AMDGPU_MAX_I2C_BUS 16
130 /* amdgpu gpio-based i2c
131 * 1. "mask" reg and bits
132 * grabs the gpio pins for software use
134 * 2. "a" reg and bits
137 * 3. "en" reg and bits
138 * sets the pin direction
140 * 4. "y" reg and bits
144 struct amdgpu_i2c_bus_rec {
146 /* id used by atom */
148 /* id used by atom */
149 enum amdgpu_hpd_id hpd;
150 /* can be used with hw i2c engine */
152 /* uses multi-media i2c engine */
155 uint32_t mask_clk_reg;
156 uint32_t mask_data_reg;
160 uint32_t en_data_reg;
163 uint32_t mask_clk_mask;
164 uint32_t mask_data_mask;
166 uint32_t a_data_mask;
167 uint32_t en_clk_mask;
168 uint32_t en_data_mask;
170 uint32_t y_data_mask;
173 #define AMDGPU_MAX_BIOS_CONNECTOR 16
176 #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0)
177 #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1)
178 #define AMDGPU_PLL_USE_REF_DIV (1 << 2)
179 #define AMDGPU_PLL_LEGACY (1 << 3)
180 #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4)
181 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5)
182 #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6)
183 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7)
184 #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8)
185 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
186 #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10)
187 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
188 #define AMDGPU_PLL_USE_POST_DIV (1 << 12)
189 #define AMDGPU_PLL_IS_LCD (1 << 13)
190 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
193 /* reference frequency */
194 uint32_t reference_freq;
197 uint32_t reference_div;
200 /* pll in/out limits */
203 uint32_t pll_out_min;
204 uint32_t pll_out_max;
205 uint32_t lcd_pll_out_min;
206 uint32_t lcd_pll_out_max;
210 uint32_t min_ref_div;
211 uint32_t max_ref_div;
212 uint32_t min_post_div;
213 uint32_t max_post_div;
214 uint32_t min_feedback_div;
215 uint32_t max_feedback_div;
216 uint32_t min_frac_feedback_div;
217 uint32_t max_frac_feedback_div;
219 /* flags for the current clock */
226 struct amdgpu_i2c_chan {
227 struct i2c_adapter adapter;
228 struct drm_device *dev;
229 struct i2c_algo_bit_data bit;
230 struct amdgpu_i2c_bus_rec rec;
231 struct drm_dp_aux aux;
239 bool last_buffer_filled_status;
241 struct amdgpu_audio_pin *pin;
247 struct amdgpu_audio_pin {
258 struct amdgpu_audio {
260 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
264 struct amdgpu_display_funcs {
265 /* display watermarks */
266 void (*bandwidth_update)(struct amdgpu_device *adev);
267 /* get frame count */
268 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
269 /* set backlight level */
270 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
272 /* get backlight level */
273 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
275 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
276 void (*hpd_set_polarity)(struct amdgpu_device *adev,
277 enum amdgpu_hpd_id hpd);
278 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
280 void (*page_flip)(struct amdgpu_device *adev,
281 int crtc_id, u64 crtc_base, bool async);
282 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
283 u32 *vbl, u32 *position);
284 /* display topology setup */
285 void (*add_encoder)(struct amdgpu_device *adev,
286 uint32_t encoder_enum,
287 uint32_t supported_device,
289 void (*add_connector)(struct amdgpu_device *adev,
290 uint32_t connector_id,
291 uint32_t supported_device,
293 struct amdgpu_i2c_bus_rec *i2c_bus,
294 uint16_t connector_object_id,
295 struct amdgpu_hpd *hpd,
296 struct amdgpu_router *router);
301 struct amdgpu_framebuffer {
302 struct drm_framebuffer base;
304 uint64_t tiling_flags;
307 /* caching for later use */
311 struct amdgpu_mode_info {
312 struct atom_context *atom_context;
313 struct card_info *atom_card_info;
314 bool mode_config_initialized;
315 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
316 struct drm_plane *planes[AMDGPU_MAX_PLANES];
317 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
318 /* DVI-I properties */
319 struct drm_property *coherent_mode_property;
320 /* DAC enable load detect */
321 struct drm_property *load_detect_property;
323 struct drm_property *underscan_property;
324 struct drm_property *underscan_hborder_property;
325 struct drm_property *underscan_vborder_property;
327 struct drm_property *audio_property;
329 struct drm_property *dither_property;
330 /* Adaptive Backlight Modulation (power feature) */
331 struct drm_property *abm_level_property;
332 /* hardcoded DFP edid from BIOS */
333 struct edid *bios_hardcoded_edid;
334 int bios_hardcoded_edid_size;
338 /* pointer to backlight encoder */
339 struct amdgpu_encoder *bl_encoder;
340 u8 bl_level; /* saved backlight level */
341 struct amdgpu_audio audio; /* audio stuff */
342 int num_crtc; /* number of crtcs */
343 int num_hpd; /* number of hpd pins */
344 int num_dig; /* number of dig blocks */
345 bool gpu_vm_support; /* supports display from GTT */
347 const struct amdgpu_display_funcs *funcs;
348 const enum drm_plane_type *plane_type;
351 #define AMDGPU_MAX_BL_LEVEL 0xFF
353 struct amdgpu_backlight_privdata {
354 struct amdgpu_encoder *encoder;
358 struct amdgpu_atom_ss {
360 uint16_t percentage_divider;
372 struct drm_crtc base;
376 uint32_t crtc_offset;
377 struct drm_gem_object *cursor_bo;
378 uint64_t cursor_addr;
385 int max_cursor_width;
386 int max_cursor_height;
387 enum amdgpu_rmx_type rmx_type;
392 struct drm_display_mode native_mode;
395 struct amdgpu_flip_work *pflip_works;
396 enum amdgpu_flip_status pflip_status;
397 int deferred_flip_completion;
398 /* parameters access from DM IRQ handler */
399 struct dm_irq_params dm_irq_params;
401 struct amdgpu_atom_ss ss;
405 u32 pll_reference_div;
408 struct drm_encoder *encoder;
409 struct drm_connector *connector;
414 u32 lb_vblank_lead_lines;
415 struct drm_display_mode hw_mode;
416 /* for virtual dce */
417 struct hrtimer vblank_timer;
418 enum amdgpu_interrupt_state vsync_timer_enabled;
421 struct drm_pending_vblank_event *event;
424 struct amdgpu_encoder_atom_dig {
428 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
431 uint16_t panel_pwr_delay;
434 struct drm_display_mode native_mode;
435 struct backlight_device *bl_dev;
437 uint8_t backlight_level;
439 struct amdgpu_afmt *afmt;
442 struct amdgpu_encoder {
443 struct drm_encoder base;
444 uint32_t encoder_enum;
447 uint32_t active_device;
449 uint32_t pixel_clock;
450 enum amdgpu_rmx_type rmx_type;
451 enum amdgpu_underscan_type underscan_type;
452 uint32_t underscan_hborder;
453 uint32_t underscan_vborder;
454 struct drm_display_mode native_mode;
456 int audio_polling_active;
461 struct amdgpu_connector_atom_dig {
463 u8 dpcd[DP_RECEIVER_CAP_SIZE];
464 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
471 struct amdgpu_gpio_rec {
480 enum amdgpu_hpd_id hpd;
482 struct amdgpu_gpio_rec gpio;
485 struct amdgpu_router {
487 struct amdgpu_i2c_bus_rec i2c_info;
492 u8 ddc_mux_control_pin;
497 u8 cd_mux_control_pin;
501 enum amdgpu_connector_audio {
502 AMDGPU_AUDIO_DISABLE = 0,
503 AMDGPU_AUDIO_ENABLE = 1,
504 AMDGPU_AUDIO_AUTO = 2
507 enum amdgpu_connector_dither {
508 AMDGPU_FMT_DITHER_DISABLE = 0,
509 AMDGPU_FMT_DITHER_ENABLE = 1,
512 struct amdgpu_dm_dp_aux {
513 struct drm_dp_aux aux;
514 struct ddc_service *ddc_service;
517 struct amdgpu_i2c_adapter {
518 struct i2c_adapter base;
520 struct ddc_service *ddc_service;
523 #define TO_DM_AUX(x) container_of((x), struct amdgpu_dm_dp_aux, aux)
525 struct amdgpu_connector {
526 struct drm_connector base;
527 uint32_t connector_id;
529 struct amdgpu_i2c_chan *ddc_bus;
530 /* some systems have an hdmi and vga port with a shared ddc line */
533 /* we need to mind the EDID between detect
534 and get modes due to analog/digital/tvencoder */
537 bool dac_load_detect;
538 bool detected_by_load; /* if the connection status was determined by load */
539 uint16_t connector_object_id;
540 struct amdgpu_hpd hpd;
541 struct amdgpu_router router;
542 struct amdgpu_i2c_chan *router_bus;
543 enum amdgpu_connector_audio audio;
544 enum amdgpu_connector_dither dither;
545 unsigned pixelclock_for_modeset;
548 /* TODO: start to use this struct and remove same field from base one */
549 struct amdgpu_mst_connector {
550 struct amdgpu_connector base;
552 struct drm_dp_mst_topology_mgr mst_mgr;
553 struct amdgpu_dm_dp_aux dm_dp_aux;
554 struct drm_dp_mst_port *port;
555 struct amdgpu_connector *mst_port;
556 bool is_mst_connector;
557 struct amdgpu_encoder *mst_encoder;
560 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
561 ((em) == ATOM_ENCODER_MODE_DP_MST))
563 /* Driver internal use only flags of amdgpu_display_get_crtc_scanoutpos() */
564 #define DRM_SCANOUTPOS_VALID (1 << 0)
565 #define DRM_SCANOUTPOS_IN_VBLANK (1 << 1)
566 #define DRM_SCANOUTPOS_ACCURATE (1 << 2)
567 #define USE_REAL_VBLANKSTART (1 << 30)
568 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
570 void amdgpu_link_encoder_connector(struct drm_device *dev);
572 struct drm_connector *
573 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
574 struct drm_connector *
575 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
576 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
579 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
580 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
582 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
585 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
587 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
588 unsigned int pipe, unsigned int flags, int *vpos,
589 int *hpos, ktime_t *stime, ktime_t *etime,
590 const struct drm_display_mode *mode);
592 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
594 void amdgpu_enc_destroy(struct drm_encoder *encoder);
595 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
596 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
597 const struct drm_display_mode *mode,
598 struct drm_display_mode *adjusted_mode);
599 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
600 struct drm_display_mode *adjusted_mode);
601 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
603 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
604 bool in_vblank_irq, int *vpos,
605 int *hpos, ktime_t *stime, ktime_t *etime,
606 const struct drm_display_mode *mode);
608 /* amdgpu_display.c */
609 void amdgpu_display_print_display_setup(struct drm_device *dev);
610 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev);
611 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
612 struct drm_modeset_acquire_ctx *ctx);
613 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
614 struct drm_framebuffer *fb,
615 struct drm_pending_vblank_event *event,
616 uint32_t page_flip_flags, uint32_t target,
617 struct drm_modeset_acquire_ctx *ctx);
618 extern const struct drm_mode_config_funcs amdgpu_mode_funcs;