drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_gfx.h"
  29 #include "amdgpu_rlc.h"
  30 #include "amdgpu_ras.h"
  31 #include "amdgpu_xcp.h"
  32
  33 /* delay 0.1 second to enable gfx off feature */
  34 #define GFX_OFF_DELAY_ENABLE         msecs_to_jiffies(100)
  35
  36 #define GFX_OFF_NO_DELAY 0
  37
  38 /*
  39  * GPU GFX IP block helpers function.
  40  */
  41
  42 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
  43                                 int pipe, int queue)
  44 {
  45         int bit = 0;
  46
  47         bit += mec * adev->gfx.mec.num_pipe_per_mec
  48                 * adev->gfx.mec.num_queue_per_pipe;
  49         bit += pipe * adev->gfx.mec.num_queue_per_pipe;
  50         bit += queue;
  51
  52         return bit;
  53 }
  54
  55 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
  56                                  int *mec, int *pipe, int *queue)
  57 {
  58         *queue = bit % adev->gfx.mec.num_queue_per_pipe;
  59         *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
  60                 % adev->gfx.mec.num_pipe_per_mec;
  61         *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
  62                / adev->gfx.mec.num_pipe_per_mec;
  63
  64 }
  65
  66 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
  67                                      int xcc_id, int mec, int pipe, int queue)
  68 {
  69         return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),
  70                         adev->gfx.mec_bitmap[xcc_id].queue_bitmap);
  71 }
  72
  73 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
  74                                int me, int pipe, int queue)
  75 {
  76         int bit = 0;
  77
  78         bit += me * adev->gfx.me.num_pipe_per_me
  79                 * adev->gfx.me.num_queue_per_pipe;
  80         bit += pipe * adev->gfx.me.num_queue_per_pipe;
  81         bit += queue;
  82
  83         return bit;
  84 }
  85
  86 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
  87                                 int *me, int *pipe, int *queue)
  88 {
  89         *queue = bit % adev->gfx.me.num_queue_per_pipe;
  90         *pipe = (bit / adev->gfx.me.num_queue_per_pipe)
  91                 % adev->gfx.me.num_pipe_per_me;
  92         *me = (bit / adev->gfx.me.num_queue_per_pipe)
  93                 / adev->gfx.me.num_pipe_per_me;
  94 }
  95
  96 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
  97                                     int me, int pipe, int queue)
  98 {
  99         return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue),
 100                         adev->gfx.me.queue_bitmap);
 101 }
 102
 103 /**
 104  * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
 105  *
 106  * @mask: array in which the per-shader array disable masks will be stored
 107  * @max_se: number of SEs
 108  * @max_sh: number of SHs
 109  *
 110  * The bitmask of CUs to be disabled in the shader array determined by se and
 111  * sh is stored in mask[se * max_sh + sh].
 112  */
 113 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
 114 {
 115         unsigned se, sh, cu;
 116         const char *p;
 117
 118         memset(mask, 0, sizeof(*mask) * max_se * max_sh);
 119
 120         if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
 121                 return;
 122
 123         p = amdgpu_disable_cu;
 124         for (;;) {
 125                 char *next;
 126                 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
 127                 if (ret < 3) {
 128                         DRM_ERROR("amdgpu: could not parse disable_cu\n");
 129                         return;
 130                 }
 131
 132                 if (se < max_se && sh < max_sh && cu < 16) {
 133                         DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
 134                         mask[se * max_sh + sh] |= 1u << cu;
 135                 } else {
 136                         DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
 137                                   se, sh, cu);
 138                 }
 139
 140                 next = strchr(p, ',');
 141                 if (!next)
 142                         break;
 143                 p = next + 1;
 144         }
 145 }
 146
 147 static bool amdgpu_gfx_is_graphics_multipipe_capable(struct amdgpu_device *adev)
 148 {
 149         return amdgpu_async_gfx_ring && adev->gfx.me.num_pipe_per_me > 1;
 150 }
 151
 152 static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev)
 153 {
 154         if (amdgpu_compute_multipipe != -1) {
 155                 DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
 156                          amdgpu_compute_multipipe);
 157                 return amdgpu_compute_multipipe == 1;
 158         }
 159
 160         if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))
 161                 return true;
 162
 163         /* FIXME: spreading the queues across pipes causes perf regressions
 164          * on POLARIS11 compute workloads */
 165         if (adev->asic_type == CHIP_POLARIS11)
 166                 return false;
 167
 168         return adev->gfx.mec.num_mec > 1;
 169 }
 170
 171 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
 172                                                 struct amdgpu_ring *ring)
 173 {
 174         int queue = ring->queue;
 175         int pipe = ring->pipe;
 176
 177         /* Policy: use pipe1 queue0 as high priority graphics queue if we
 178          * have more than one gfx pipe.
 179          */
 180         if (amdgpu_gfx_is_graphics_multipipe_capable(adev) &&
 181             adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) {
 182                 int me = ring->me;
 183                 int bit;
 184
 185                 bit = amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue);
 186                 if (ring == &adev->gfx.gfx_ring[bit])
 187                         return true;
 188         }
 189
 190         return false;
 191 }
 192
 193 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 194                                                struct amdgpu_ring *ring)
 195 {
 196         /* Policy: use 1st queue as high priority compute queue if we
 197          * have more than one compute queue.
 198          */
 199         if (adev->gfx.num_compute_rings > 1 &&
 200             ring == &adev->gfx.compute_ring[0])
 201                 return true;
 202
 203         return false;
 204 }
 205
 206 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
 207 {
 208         int i, j, queue, pipe;
 209         bool multipipe_policy = amdgpu_gfx_is_compute_multipipe_capable(adev);
 210         int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec *
 211                                      adev->gfx.mec.num_queue_per_pipe,
 212                                      adev->gfx.num_compute_rings);
 213         int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
 214
 215         if (multipipe_policy) {
 216                 /* policy: make queues evenly cross all pipes on MEC1 only
 217                  * for multiple xcc, just use the original policy for simplicity */
 218                 for (j = 0; j < num_xcc; j++) {
 219                         for (i = 0; i < max_queues_per_mec; i++) {
 220                                 pipe = i % adev->gfx.mec.num_pipe_per_mec;
 221                                 queue = (i / adev->gfx.mec.num_pipe_per_mec) %
 222                                          adev->gfx.mec.num_queue_per_pipe;
 223
 224                                 set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue,
 225                                         adev->gfx.mec_bitmap[j].queue_bitmap);
 226                         }
 227                 }
 228         } else {
 229                 /* policy: amdgpu owns all queues in the given pipe */
 230                 for (j = 0; j < num_xcc; j++) {
 231                         for (i = 0; i < max_queues_per_mec; ++i)
 232                                 set_bit(i, adev->gfx.mec_bitmap[j].queue_bitmap);
 233                 }
 234         }
 235
 236         for (j = 0; j < num_xcc; j++) {
 237                 dev_dbg(adev->dev, "mec queue bitmap weight=%d\n",
 238                         bitmap_weight(adev->gfx.mec_bitmap[j].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES));
 239         }
 240 }
 241
 242 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
 243 {
 244         int i, queue, pipe;
 245         bool multipipe_policy = amdgpu_gfx_is_graphics_multipipe_capable(adev);
 246         int max_queues_per_me = adev->gfx.me.num_pipe_per_me *
 247                                         adev->gfx.me.num_queue_per_pipe;
 248
 249         if (multipipe_policy) {
 250                 /* policy: amdgpu owns the first queue per pipe at this stage
 251                  * will extend to mulitple queues per pipe later */
 252                 for (i = 0; i < max_queues_per_me; i++) {
 253                         pipe = i % adev->gfx.me.num_pipe_per_me;
 254                         queue = (i / adev->gfx.me.num_pipe_per_me) %
 255                                 adev->gfx.me.num_queue_per_pipe;
 256
 257                         set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue,
 258                                 adev->gfx.me.queue_bitmap);
 259                 }
 260         } else {
 261                 for (i = 0; i < max_queues_per_me; ++i)
 262                         set_bit(i, adev->gfx.me.queue_bitmap);
 263         }
 264
 265         /* update the number of active graphics rings */
 266         adev->gfx.num_gfx_rings =
 267                 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 268 }
 269
 270 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
 271                                   struct amdgpu_ring *ring, int xcc_id)
 272 {
 273         int queue_bit;
 274         int mec, pipe, queue;
 275
 276         queue_bit = adev->gfx.mec.num_mec
 277                     * adev->gfx.mec.num_pipe_per_mec
 278                     * adev->gfx.mec.num_queue_per_pipe;
 279
 280         while (--queue_bit >= 0) {
 281                 if (test_bit(queue_bit, adev->gfx.mec_bitmap[xcc_id].queue_bitmap))
 282                         continue;
 283
 284                 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 285
 286                 /*
 287                  * 1. Using pipes 2/3 from MEC 2 seems cause problems.
 288                  * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
 289                  * only can be issued on queue 0.
 290                  */
 291                 if ((mec == 1 && pipe > 1) || queue != 0)
 292                         continue;
 293
 294                 ring->me = mec + 1;
 295                 ring->pipe = pipe;
 296                 ring->queue = queue;
 297
 298                 return 0;
 299         }
 300
 301         dev_err(adev->dev, "Failed to find a queue for KIQ\n");
 302         return -EINVAL;
 303 }
 304
 305 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 306                              struct amdgpu_ring *ring,
 307                              struct amdgpu_irq_src *irq, int xcc_id)
 308 {
 309         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 310         int r = 0;
 311
 312         spin_lock_init(&kiq->ring_lock);
 313
 314         ring->adev = NULL;
 315         ring->ring_obj = NULL;
 316         ring->use_doorbell = true;
 317         ring->xcc_id = xcc_id;
 318         ring->vm_hub = AMDGPU_GFXHUB(xcc_id);
 319         ring->doorbell_index =
 320                 (adev->doorbell_index.kiq +
 321                  xcc_id * adev->doorbell_index.xcc_doorbell_range)
 322                 << 1;
 323
 324         r = amdgpu_gfx_kiq_acquire(adev, ring, xcc_id);
 325         if (r)
 326                 return r;
 327
 328         ring->eop_gpu_addr = kiq->eop_gpu_addr;
 329         ring->no_scheduler = true;
 330         sprintf(ring->name, "kiq_%d.%d.%d.%d", xcc_id, ring->me, ring->pipe, ring->queue);
 331         r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0,
 332                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 333         if (r)
 334                 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
 335
 336         return r;
 337 }
 338
 339 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
 340 {
 341         amdgpu_ring_fini(ring);
 342 }
 343
 344 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id)
 345 {
 346         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 347
 348         amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
 349 }
 350
 351 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
 352                         unsigned hpd_size, int xcc_id)
 353 {
 354         int r;
 355         u32 *hpd;
 356         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 357
 358         r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE,
 359                                     AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
 360                                     &kiq->eop_gpu_addr, (void **)&hpd);
 361         if (r) {
 362                 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
 363                 return r;
 364         }
 365
 366         memset(hpd, 0, hpd_size);
 367
 368         r = amdgpu_bo_reserve(kiq->eop_obj, true);
 369         if (unlikely(r != 0))
 370                 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
 371         amdgpu_bo_kunmap(kiq->eop_obj);
 372         amdgpu_bo_unreserve(kiq->eop_obj);
 373
 374         return 0;
 375 }
 376
 377 /* create MQD for each compute/gfx queue */
 378 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
 379                            unsigned mqd_size, int xcc_id)
 380 {
 381         int r, i, j;
 382         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 383         struct amdgpu_ring *ring = &kiq->ring;
 384         u32 domain = AMDGPU_GEM_DOMAIN_GTT;
 385
 386         /* Only enable on gfx10 and 11 for now to avoid changing behavior on older chips */
 387         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0))
 388                 domain |= AMDGPU_GEM_DOMAIN_VRAM;
 389
 390         /* create MQD for KIQ */
 391         if (!adev->enable_mes_kiq && !ring->mqd_obj) {
 392                 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must
 393                  * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD
 394                  * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for
 395                  * KIQ MQD no matter SRIOV or Bare-metal
 396                  */
 397                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 398                                             AMDGPU_GEM_DOMAIN_VRAM |
 399                                             AMDGPU_GEM_DOMAIN_GTT,
 400                                             &ring->mqd_obj,
 401                                             &ring->mqd_gpu_addr,
 402                                             &ring->mqd_ptr);
 403                 if (r) {
 404                         dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
 405                         return r;
 406                 }
 407
 408                 /* prepare MQD backup */
 409                 kiq->mqd_backup = kmalloc(mqd_size, GFP_KERNEL);
 410                 if (!kiq->mqd_backup)
 411                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 412         }
 413
 414         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 415                 /* create MQD for each KGQ */
 416                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 417                         ring = &adev->gfx.gfx_ring[i];
 418                         if (!ring->mqd_obj) {
 419                                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 420                                                             domain, &ring->mqd_obj,
 421                                                             &ring->mqd_gpu_addr, &ring->mqd_ptr);
 422                                 if (r) {
 423                                         dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 424                                         return r;
 425                                 }
 426
 427                                 ring->mqd_size = mqd_size;
 428                                 /* prepare MQD backup */
 429                                 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
 430                                 if (!adev->gfx.me.mqd_backup[i])
 431                                         dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 432                         }
 433                 }
 434         }
 435
 436         /* create MQD for each KCQ */
 437         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 438                 j = i + xcc_id * adev->gfx.num_compute_rings;
 439                 ring = &adev->gfx.compute_ring[j];
 440                 if (!ring->mqd_obj) {
 441                         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 442                                                     domain, &ring->mqd_obj,
 443                                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
 444                         if (r) {
 445                                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 446                                 return r;
 447                         }
 448
 449                         ring->mqd_size = mqd_size;
 450                         /* prepare MQD backup */
 451                         adev->gfx.mec.mqd_backup[j] = kmalloc(mqd_size, GFP_KERNEL);
 452                         if (!adev->gfx.mec.mqd_backup[j])
 453                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 454                 }
 455         }
 456
 457         return 0;
 458 }
 459
 460 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id)
 461 {
 462         struct amdgpu_ring *ring = NULL;
 463         int i, j;
 464         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 465
 466         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 467                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 468                         ring = &adev->gfx.gfx_ring[i];
 469                         kfree(adev->gfx.me.mqd_backup[i]);
 470                         amdgpu_bo_free_kernel(&ring->mqd_obj,
 471                                               &ring->mqd_gpu_addr,
 472                                               &ring->mqd_ptr);
 473                 }
 474         }
 475
 476         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 477                 j = i + xcc_id * adev->gfx.num_compute_rings;
 478                 ring = &adev->gfx.compute_ring[j];
 479                 kfree(adev->gfx.mec.mqd_backup[j]);
 480                 amdgpu_bo_free_kernel(&ring->mqd_obj,
 481                                       &ring->mqd_gpu_addr,
 482                                       &ring->mqd_ptr);
 483         }
 484
 485         ring = &kiq->ring;
 486         kfree(kiq->mqd_backup);
 487         amdgpu_bo_free_kernel(&ring->mqd_obj,
 488                               &ring->mqd_gpu_addr,
 489                               &ring->mqd_ptr);
 490 }
 491
 492 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id)
 493 {
 494         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 495         struct amdgpu_ring *kiq_ring = &kiq->ring;
 496         int i, r = 0;
 497         int j;
 498
 499         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 500                 return -EINVAL;
 501
 502         spin_lock(&kiq->ring_lock);
 503         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
 504                                         adev->gfx.num_compute_rings)) {
 505                 spin_unlock(&kiq->ring_lock);
 506                 return -ENOMEM;
 507         }
 508
 509         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 510                 j = i + xcc_id * adev->gfx.num_compute_rings;
 511                 kiq->pmf->kiq_unmap_queues(kiq_ring,
 512                                            &adev->gfx.compute_ring[j],
 513                                            RESET_QUEUES, 0, 0);
 514         }
 515
 516         if (kiq_ring->sched.ready && !adev->job_hang)
 517                 r = amdgpu_ring_test_helper(kiq_ring);
 518         spin_unlock(&kiq->ring_lock);
 519
 520         return r;
 521 }
 522
 523 int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id)
 524 {
 525         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 526         struct amdgpu_ring *kiq_ring = &kiq->ring;
 527         int i, r = 0;
 528         int j;
 529
 530         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 531                 return -EINVAL;
 532
 533         spin_lock(&kiq->ring_lock);
 534         if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {
 535                 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
 536                                                 adev->gfx.num_gfx_rings)) {
 537                         spin_unlock(&kiq->ring_lock);
 538                         return -ENOMEM;
 539                 }
 540
 541                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 542                         j = i + xcc_id * adev->gfx.num_gfx_rings;
 543                         kiq->pmf->kiq_unmap_queues(kiq_ring,
 544                                                    &adev->gfx.gfx_ring[j],
 545                                                    PREEMPT_QUEUES, 0, 0);
 546                 }
 547         }
 548
 549         if (adev->gfx.kiq[0].ring.sched.ready && !adev->job_hang)
 550                 r = amdgpu_ring_test_helper(kiq_ring);
 551         spin_unlock(&kiq->ring_lock);
 552
 553         return r;
 554 }
 555
 556 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
 557                                         int queue_bit)
 558 {
 559         int mec, pipe, queue;
 560         int set_resource_bit = 0;
 561
 562         amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 563
 564         set_resource_bit = mec * 4 * 8 + pipe * 8 + queue;
 565
 566         return set_resource_bit;
 567 }
 568
 569 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id)
 570 {
 571         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 572         struct amdgpu_ring *kiq_ring = &kiq->ring;
 573         uint64_t queue_mask = 0;
 574         int r, i, j;
 575
 576         if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources)
 577                 return -EINVAL;
 578
 579         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
 580                 if (!test_bit(i, adev->gfx.mec_bitmap[xcc_id].queue_bitmap))
 581                         continue;
 582
 583                 /* This situation may be hit in the future if a new HW
 584                  * generation exposes more than 64 queues. If so, the
 585                  * definition of queue_mask needs updating */
 586                 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
 587                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
 588                         break;
 589                 }
 590
 591                 queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i));
 592         }
 593
 594         DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
 595                                                         kiq_ring->queue);
 596         amdgpu_device_flush_hdp(adev, NULL);
 597
 598         spin_lock(&kiq->ring_lock);
 599         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
 600                                         adev->gfx.num_compute_rings +
 601                                         kiq->pmf->set_resources_size);
 602         if (r) {
 603                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 604                 spin_unlock(&kiq->ring_lock);
 605                 return r;
 606         }
 607
 608         if (adev->enable_mes)
 609                 queue_mask = ~0ULL;
 610
 611         kiq->pmf->kiq_set_resources(kiq_ring, queue_mask);
 612         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 613                 j = i + xcc_id * adev->gfx.num_compute_rings;
 614                         kiq->pmf->kiq_map_queues(kiq_ring,
 615                                                  &adev->gfx.compute_ring[j]);
 616         }
 617
 618         r = amdgpu_ring_test_helper(kiq_ring);
 619         spin_unlock(&kiq->ring_lock);
 620         if (r)
 621                 DRM_ERROR("KCQ enable failed\n");
 622
 623         return r;
 624 }
 625
 626 int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id)
 627 {
 628         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 629         struct amdgpu_ring *kiq_ring = &kiq->ring;
 630         int r, i, j;
 631
 632         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
 633                 return -EINVAL;
 634
 635         amdgpu_device_flush_hdp(adev, NULL);
 636
 637         spin_lock(&kiq->ring_lock);
 638         /* No need to map kcq on the slave */
 639         if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {
 640                 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
 641                                                 adev->gfx.num_gfx_rings);
 642                 if (r) {
 643                         DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 644                         spin_unlock(&kiq->ring_lock);
 645                         return r;
 646                 }
 647
 648                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 649                         j = i + xcc_id * adev->gfx.num_gfx_rings;
 650                         kiq->pmf->kiq_map_queues(kiq_ring,
 651                                                  &adev->gfx.gfx_ring[j]);
 652                 }
 653         }
 654
 655         r = amdgpu_ring_test_helper(kiq_ring);
 656         spin_unlock(&kiq->ring_lock);
 657         if (r)
 658                 DRM_ERROR("KCQ enable failed\n");
 659
 660         return r;
 661 }
 662
 663 /* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
 664  *
 665  * @adev: amdgpu_device pointer
 666  * @bool enable true: enable gfx off feature, false: disable gfx off feature
 667  *
 668  * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled.
 669  * 2. other client can send request to disable gfx off feature, the request should be honored.
 670  * 3. other client can cancel their request of disable gfx off feature
 671  * 4. other client should not send request to enable gfx off feature before disable gfx off feature.
 672  */
 673
 674 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
 675 {
 676         unsigned long delay = GFX_OFF_DELAY_ENABLE;
 677
 678         if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 679                 return;
 680
 681         mutex_lock(&adev->gfx.gfx_off_mutex);
 682
 683         if (enable) {
 684                 /* If the count is already 0, it means there's an imbalance bug somewhere.
 685                  * Note that the bug may be in a different caller than the one which triggers the
 686                  * WARN_ON_ONCE.
 687                  */
 688                 if (WARN_ON_ONCE(adev->gfx.gfx_off_req_count == 0))
 689                         goto unlock;
 690
 691                 adev->gfx.gfx_off_req_count--;
 692
 693                 if (adev->gfx.gfx_off_req_count == 0 &&
 694                     !adev->gfx.gfx_off_state) {
 695                         /* If going to s2idle, no need to wait */
 696                         if (adev->in_s0ix) {
 697                                 if (!amdgpu_dpm_set_powergating_by_smu(adev,
 698                                                 AMD_IP_BLOCK_TYPE_GFX, true))
 699                                         adev->gfx.gfx_off_state = true;
 700                         } else {
 701                                 schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
 702                                               delay);
 703                         }
 704                 }
 705         } else {
 706                 if (adev->gfx.gfx_off_req_count == 0) {
 707                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
 708
 709                         if (adev->gfx.gfx_off_state &&
 710                             !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {
 711                                 adev->gfx.gfx_off_state = false;
 712
 713                                 if (adev->gfx.funcs->init_spm_golden) {
 714                                         dev_dbg(adev->dev,
 715                                                 "GFXOFF is disabled, re-init SPM golden settings\n");
 716                                         amdgpu_gfx_init_spm_golden(adev);
 717                                 }
 718                         }
 719                 }
 720
 721                 adev->gfx.gfx_off_req_count++;
 722         }
 723
 724 unlock:
 725         mutex_unlock(&adev->gfx.gfx_off_mutex);
 726 }
 727
 728 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value)
 729 {
 730         int r = 0;
 731
 732         mutex_lock(&adev->gfx.gfx_off_mutex);
 733
 734         r = amdgpu_dpm_set_residency_gfxoff(adev, value);
 735
 736         mutex_unlock(&adev->gfx.gfx_off_mutex);
 737
 738         return r;
 739 }
 740
 741 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *value)
 742 {
 743         int r = 0;
 744
 745         mutex_lock(&adev->gfx.gfx_off_mutex);
 746
 747         r = amdgpu_dpm_get_residency_gfxoff(adev, value);
 748
 749         mutex_unlock(&adev->gfx.gfx_off_mutex);
 750
 751         return r;
 752 }
 753
 754 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value)
 755 {
 756         int r = 0;
 757
 758         mutex_lock(&adev->gfx.gfx_off_mutex);
 759
 760         r = amdgpu_dpm_get_entrycount_gfxoff(adev, value);
 761
 762         mutex_unlock(&adev->gfx.gfx_off_mutex);
 763
 764         return r;
 765 }
 766
 767 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value)
 768 {
 769
 770         int r = 0;
 771
 772         mutex_lock(&adev->gfx.gfx_off_mutex);
 773
 774         r = amdgpu_dpm_get_status_gfxoff(adev, value);
 775
 776         mutex_unlock(&adev->gfx.gfx_off_mutex);
 777
 778         return r;
 779 }
 780
 781 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 782 {
 783         int r;
 784
 785         if (amdgpu_ras_is_supported(adev, ras_block->block)) {
 786                 if (!amdgpu_persistent_edc_harvesting_supported(adev))
 787                         amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX);
 788
 789                 r = amdgpu_ras_block_late_init(adev, ras_block);
 790                 if (r)
 791                         return r;
 792
 793                 if (adev->gfx.cp_ecc_error_irq.funcs) {
 794                         r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
 795                         if (r)
 796                                 goto late_fini;
 797                 }
 798         } else {
 799                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
 800         }
 801
 802         return 0;
 803 late_fini:
 804         amdgpu_ras_block_late_fini(adev, ras_block);
 805         return r;
 806 }
 807
 808 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev)
 809 {
 810         int err = 0;
 811         struct amdgpu_gfx_ras *ras = NULL;
 812
 813         /* adev->gfx.ras is NULL, which means gfx does not
 814          * support ras function, then do nothing here.
 815          */
 816         if (!adev->gfx.ras)
 817                 return 0;
 818
 819         ras = adev->gfx.ras;
 820
 821         err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
 822         if (err) {
 823                 dev_err(adev->dev, "Failed to register gfx ras block!\n");
 824                 return err;
 825         }
 826
 827         strcpy(ras->ras_block.ras_comm.name, "gfx");
 828         ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX;
 829         ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 830         adev->gfx.ras_if = &ras->ras_block.ras_comm;
 831
 832         /* If not define special ras_late_init function, use gfx default ras_late_init */
 833         if (!ras->ras_block.ras_late_init)
 834                 ras->ras_block.ras_late_init = amdgpu_gfx_ras_late_init;
 835
 836         /* If not defined special ras_cb function, use default ras_cb */
 837         if (!ras->ras_block.ras_cb)
 838                 ras->ras_block.ras_cb = amdgpu_gfx_process_ras_data_cb;
 839
 840         return 0;
 841 }
 842
 843 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev,
 844                                                 struct amdgpu_iv_entry *entry)
 845 {
 846         if (adev->gfx.ras && adev->gfx.ras->poison_consumption_handler)
 847                 return adev->gfx.ras->poison_consumption_handler(adev, entry);
 848
 849         return 0;
 850 }
 851
 852 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
 853                 void *err_data,
 854                 struct amdgpu_iv_entry *entry)
 855 {
 856         /* TODO ue will trigger an interrupt.
 857          *
 858          * When “Full RAS” is enabled, the per-IP interrupt sources should
 859          * be disabled and the driver should only look for the aggregated
 860          * interrupt via sync flood
 861          */
 862         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
 863                 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
 864                 if (adev->gfx.ras && adev->gfx.ras->ras_block.hw_ops &&
 865                     adev->gfx.ras->ras_block.hw_ops->query_ras_error_count)
 866                         adev->gfx.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
 867                 amdgpu_ras_reset_gpu(adev);
 868         }
 869         return AMDGPU_RAS_SUCCESS;
 870 }
 871
 872 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
 873                                   struct amdgpu_irq_src *source,
 874                                   struct amdgpu_iv_entry *entry)
 875 {
 876         struct ras_common_if *ras_if = adev->gfx.ras_if;
 877         struct ras_dispatch_if ih_data = {
 878                 .entry = entry,
 879         };
 880
 881         if (!ras_if)
 882                 return 0;
 883
 884         ih_data.head = *ras_if;
 885
 886         DRM_ERROR("CP ECC ERROR IRQ\n");
 887         amdgpu_ras_interrupt_dispatch(adev, &ih_data);
 888         return 0;
 889 }
 890
 891 void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev,
 892                 void *ras_error_status,
 893                 void (*func)(struct amdgpu_device *adev, void *ras_error_status,
 894                                 int xcc_id))
 895 {
 896         int i;
 897         int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
 898         uint32_t xcc_mask = GENMASK(num_xcc - 1, 0);
 899         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
 900
 901         if (err_data) {
 902                 err_data->ue_count = 0;
 903                 err_data->ce_count = 0;
 904         }
 905
 906         for_each_inst(i, xcc_mask)
 907                 func(adev, ras_error_status, i);
 908 }
 909
 910 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
 911 {
 912         signed long r, cnt = 0;
 913         unsigned long flags;
 914         uint32_t seq, reg_val_offs = 0, value = 0;
 915         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 916         struct amdgpu_ring *ring = &kiq->ring;
 917
 918         if (amdgpu_device_skip_hw_access(adev))
 919                 return 0;
 920
 921         if (adev->mes.ring.sched.ready)
 922                 return amdgpu_mes_rreg(adev, reg);
 923
 924         BUG_ON(!ring->funcs->emit_rreg);
 925
 926         spin_lock_irqsave(&kiq->ring_lock, flags);
 927         if (amdgpu_device_wb_get(adev, &reg_val_offs)) {
 928                 pr_err("critical bug! too many kiq readers\n");
 929                 goto failed_unlock;
 930         }
 931         amdgpu_ring_alloc(ring, 32);
 932         amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
 933         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 934         if (r)
 935                 goto failed_undo;
 936
 937         amdgpu_ring_commit(ring);
 938         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 939
 940         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 941
 942         /* don't wait anymore for gpu reset case because this way may
 943          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
 944          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
 945          * never return if we keep waiting in virt_kiq_rreg, which cause
 946          * gpu_recover() hang there.
 947          *
 948          * also don't wait anymore for IRQ context
 949          * */
 950         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
 951                 goto failed_kiq_read;
 952
 953         might_sleep();
 954         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 955                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 956                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 957         }
 958
 959         if (cnt > MAX_KIQ_REG_TRY)
 960                 goto failed_kiq_read;
 961
 962         mb();
 963         value = adev->wb.wb[reg_val_offs];
 964         amdgpu_device_wb_free(adev, reg_val_offs);
 965         return value;
 966
 967 failed_undo:
 968         amdgpu_ring_undo(ring);
 969 failed_unlock:
 970         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 971 failed_kiq_read:
 972         if (reg_val_offs)
 973                 amdgpu_device_wb_free(adev, reg_val_offs);
 974         dev_err(adev->dev, "failed to read reg:%x\n", reg);
 975         return ~0;
 976 }
 977
 978 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 979 {
 980         signed long r, cnt = 0;
 981         unsigned long flags;
 982         uint32_t seq;
 983         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 984         struct amdgpu_ring *ring = &kiq->ring;
 985
 986         BUG_ON(!ring->funcs->emit_wreg);
 987
 988         if (amdgpu_device_skip_hw_access(adev))
 989                 return;
 990
 991         if (adev->mes.ring.sched.ready) {
 992                 amdgpu_mes_wreg(adev, reg, v);
 993                 return;
 994         }
 995
 996         spin_lock_irqsave(&kiq->ring_lock, flags);
 997         amdgpu_ring_alloc(ring, 32);
 998         amdgpu_ring_emit_wreg(ring, reg, v);
 999         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
1000         if (r)
1001                 goto failed_undo;
1002
1003         amdgpu_ring_commit(ring);
1004         spin_unlock_irqrestore(&kiq->ring_lock, flags);
1005
1006         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
1007
1008         /* don't wait anymore for gpu reset case because this way may
1009          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
1010          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
1011          * never return if we keep waiting in virt_kiq_rreg, which cause
1012          * gpu_recover() hang there.
1013          *
1014          * also don't wait anymore for IRQ context
1015          * */
1016         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
1017                 goto failed_kiq_write;
1018
1019         might_sleep();
1020         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
1021
1022                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
1023                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
1024         }
1025
1026         if (cnt > MAX_KIQ_REG_TRY)
1027                 goto failed_kiq_write;
1028
1029         return;
1030
1031 failed_undo:
1032         amdgpu_ring_undo(ring);
1033         spin_unlock_irqrestore(&kiq->ring_lock, flags);
1034 failed_kiq_write:
1035         dev_err(adev->dev, "failed to write reg:%x\n", reg);
1036 }
1037
1038 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
1039 {
1040         if (amdgpu_num_kcq == -1) {
1041                 return 8;
1042         } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
1043                 dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");
1044                 return 8;
1045         }
1046         return amdgpu_num_kcq;
1047 }
1048
1049 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev,
1050                                   uint32_t ucode_id)
1051 {
1052         const struct gfx_firmware_header_v1_0 *cp_hdr;
1053         const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0;
1054         struct amdgpu_firmware_info *info = NULL;
1055         const struct firmware *ucode_fw;
1056         unsigned int fw_size;
1057
1058         switch (ucode_id) {
1059         case AMDGPU_UCODE_ID_CP_PFP:
1060                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1061                         adev->gfx.pfp_fw->data;
1062                 adev->gfx.pfp_fw_version =
1063                         le32_to_cpu(cp_hdr->header.ucode_version);
1064                 adev->gfx.pfp_feature_version =
1065                         le32_to_cpu(cp_hdr->ucode_feature_version);
1066                 ucode_fw = adev->gfx.pfp_fw;
1067                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1068                 break;
1069         case AMDGPU_UCODE_ID_CP_RS64_PFP:
1070                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1071                         adev->gfx.pfp_fw->data;
1072                 adev->gfx.pfp_fw_version =
1073                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1074                 adev->gfx.pfp_feature_version =
1075                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1076                 ucode_fw = adev->gfx.pfp_fw;
1077                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1078                 break;
1079         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
1080         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
1081                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1082                         adev->gfx.pfp_fw->data;
1083                 ucode_fw = adev->gfx.pfp_fw;
1084                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1085                 break;
1086         case AMDGPU_UCODE_ID_CP_ME:
1087                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1088                         adev->gfx.me_fw->data;
1089                 adev->gfx.me_fw_version =
1090                         le32_to_cpu(cp_hdr->header.ucode_version);
1091                 adev->gfx.me_feature_version =
1092                         le32_to_cpu(cp_hdr->ucode_feature_version);
1093                 ucode_fw = adev->gfx.me_fw;
1094                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1095                 break;
1096         case AMDGPU_UCODE_ID_CP_RS64_ME:
1097                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1098                         adev->gfx.me_fw->data;
1099                 adev->gfx.me_fw_version =
1100                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1101                 adev->gfx.me_feature_version =
1102                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1103                 ucode_fw = adev->gfx.me_fw;
1104                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1105                 break;
1106         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
1107         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
1108                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1109                         adev->gfx.me_fw->data;
1110                 ucode_fw = adev->gfx.me_fw;
1111                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1112                 break;
1113         case AMDGPU_UCODE_ID_CP_CE:
1114                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1115                         adev->gfx.ce_fw->data;
1116                 adev->gfx.ce_fw_version =
1117                         le32_to_cpu(cp_hdr->header.ucode_version);
1118                 adev->gfx.ce_feature_version =
1119                         le32_to_cpu(cp_hdr->ucode_feature_version);
1120                 ucode_fw = adev->gfx.ce_fw;
1121                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1122                 break;
1123         case AMDGPU_UCODE_ID_CP_MEC1:
1124                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1125                         adev->gfx.mec_fw->data;
1126                 adev->gfx.mec_fw_version =
1127                         le32_to_cpu(cp_hdr->header.ucode_version);
1128                 adev->gfx.mec_feature_version =
1129                         le32_to_cpu(cp_hdr->ucode_feature_version);
1130                 ucode_fw = adev->gfx.mec_fw;
1131                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1132                           le32_to_cpu(cp_hdr->jt_size) * 4;
1133                 break;
1134         case AMDGPU_UCODE_ID_CP_MEC1_JT:
1135                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1136                         adev->gfx.mec_fw->data;
1137                 ucode_fw = adev->gfx.mec_fw;
1138                 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
1139                 break;
1140         case AMDGPU_UCODE_ID_CP_MEC2:
1141                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1142                         adev->gfx.mec2_fw->data;
1143                 adev->gfx.mec2_fw_version =
1144                         le32_to_cpu(cp_hdr->header.ucode_version);
1145                 adev->gfx.mec2_feature_version =
1146                         le32_to_cpu(cp_hdr->ucode_feature_version);
1147                 ucode_fw = adev->gfx.mec2_fw;
1148                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1149                           le32_to_cpu(cp_hdr->jt_size) * 4;
1150                 break;
1151         case AMDGPU_UCODE_ID_CP_MEC2_JT:
1152                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1153                         adev->gfx.mec2_fw->data;
1154                 ucode_fw = adev->gfx.mec2_fw;
1155                 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
1156                 break;
1157         case AMDGPU_UCODE_ID_CP_RS64_MEC:
1158                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1159                         adev->gfx.mec_fw->data;
1160                 adev->gfx.mec_fw_version =
1161                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1162                 adev->gfx.mec_feature_version =
1163                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1164                 ucode_fw = adev->gfx.mec_fw;
1165                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1166                 break;
1167         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
1168         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
1169         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
1170         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
1171                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1172                         adev->gfx.mec_fw->data;
1173                 ucode_fw = adev->gfx.mec_fw;
1174                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1175                 break;
1176         default:
1177                 break;
1178         }
1179
1180         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1181                 info = &adev->firmware.ucode[ucode_id];
1182                 info->ucode_id = ucode_id;
1183                 info->fw = ucode_fw;
1184                 adev->firmware.fw_size += ALIGN(fw_size, PAGE_SIZE);
1185         }
1186 }
1187
1188 bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id)
1189 {
1190         return !(xcc_id % (adev->gfx.num_xcc_per_xcp ?
1191                         adev->gfx.num_xcc_per_xcp : 1));
1192 }
1193
1194 static ssize_t amdgpu_gfx_get_current_compute_partition(struct device *dev,
1195                                                 struct device_attribute *addr,
1196                                                 char *buf)
1197 {
1198         struct drm_device *ddev = dev_get_drvdata(dev);
1199         struct amdgpu_device *adev = drm_to_adev(ddev);
1200         int mode;
1201
1202         mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr,
1203                                                AMDGPU_XCP_FL_NONE);
1204
1205         return sysfs_emit(buf, "%s\n", amdgpu_gfx_compute_mode_desc(mode));
1206 }
1207
1208 static ssize_t amdgpu_gfx_set_compute_partition(struct device *dev,
1209                                                 struct device_attribute *addr,
1210                                                 const char *buf, size_t count)
1211 {
1212         struct drm_device *ddev = dev_get_drvdata(dev);
1213         struct amdgpu_device *adev = drm_to_adev(ddev);
1214         enum amdgpu_gfx_partition mode;
1215         int ret = 0, num_xcc;
1216
1217         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1218         if (num_xcc % 2 != 0)
1219                 return -EINVAL;
1220
1221         if (!strncasecmp("SPX", buf, strlen("SPX"))) {
1222                 mode = AMDGPU_SPX_PARTITION_MODE;
1223         } else if (!strncasecmp("DPX", buf, strlen("DPX"))) {
1224                 /*
1225                  * DPX mode needs AIDs to be in multiple of 2.
1226                  * Each AID connects 2 XCCs.
1227                  */
1228                 if (num_xcc%4)
1229                         return -EINVAL;
1230                 mode = AMDGPU_DPX_PARTITION_MODE;
1231         } else if (!strncasecmp("TPX", buf, strlen("TPX"))) {
1232                 if (num_xcc != 6)
1233                         return -EINVAL;
1234                 mode = AMDGPU_TPX_PARTITION_MODE;
1235         } else if (!strncasecmp("QPX", buf, strlen("QPX"))) {
1236                 if (num_xcc != 8)
1237                         return -EINVAL;
1238                 mode = AMDGPU_QPX_PARTITION_MODE;
1239         } else if (!strncasecmp("CPX", buf, strlen("CPX"))) {
1240                 mode = AMDGPU_CPX_PARTITION_MODE;
1241         } else {
1242                 return -EINVAL;
1243         }
1244
1245         ret = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, mode);
1246
1247         if (ret)
1248                 return ret;
1249
1250         return count;
1251 }
1252
1253 static ssize_t amdgpu_gfx_get_available_compute_partition(struct device *dev,
1254                                                 struct device_attribute *addr,
1255                                                 char *buf)
1256 {
1257         struct drm_device *ddev = dev_get_drvdata(dev);
1258         struct amdgpu_device *adev = drm_to_adev(ddev);
1259         char *supported_partition;
1260
1261         /* TBD */
1262         switch (NUM_XCC(adev->gfx.xcc_mask)) {
1263         case 8:
1264                 supported_partition = "SPX, DPX, QPX, CPX";
1265                 break;
1266         case 6:
1267                 supported_partition = "SPX, TPX, CPX";
1268                 break;
1269         case 4:
1270                 supported_partition = "SPX, DPX, CPX";
1271                 break;
1272         /* this seems only existing in emulation phase */
1273         case 2:
1274                 supported_partition = "SPX, CPX";
1275                 break;
1276         default:
1277                 supported_partition = "Not supported";
1278                 break;
1279         }
1280
1281         return sysfs_emit(buf, "%s\n", supported_partition);
1282 }
1283
1284 static DEVICE_ATTR(current_compute_partition, S_IRUGO | S_IWUSR,
1285                    amdgpu_gfx_get_current_compute_partition,
1286                    amdgpu_gfx_set_compute_partition);
1287
1288 static DEVICE_ATTR(available_compute_partition, S_IRUGO,
1289                    amdgpu_gfx_get_available_compute_partition, NULL);
1290
1291 int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev)
1292 {
1293         int r;
1294
1295         r = device_create_file(adev->dev, &dev_attr_current_compute_partition);
1296         if (r)
1297                 return r;
1298
1299         r = device_create_file(adev->dev, &dev_attr_available_compute_partition);
1300
1301         return r;
1302 }
1303
1304 void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev)
1305 {
1306         device_remove_file(adev->dev, &dev_attr_current_compute_partition);
1307         device_remove_file(adev->dev, &dev_attr_available_compute_partition);
1308 }