2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/ktime.h>
29 #include <linux/pagemap.h>
31 #include <drm/amdgpu_drm.h>
34 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
36 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
39 if (robj->gem_base.import_attach)
40 drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
41 amdgpu_mn_unregister(robj);
42 amdgpu_bo_unref(&robj);
46 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
47 int alignment, u32 initial_domain,
48 u64 flags, bool kernel,
49 struct reservation_object *resv,
50 struct drm_gem_object **obj)
56 /* At least align on page size */
57 if (alignment < PAGE_SIZE) {
58 alignment = PAGE_SIZE;
62 r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
63 flags, NULL, resv, 0, &bo);
65 if (r != -ERESTARTSYS) {
66 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
67 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
71 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
72 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
75 DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
76 size, initial_domain, alignment, r);
85 void amdgpu_gem_force_release(struct amdgpu_device *adev)
87 struct drm_device *ddev = adev->ddev;
88 struct drm_file *file;
90 mutex_lock(&ddev->filelist_mutex);
92 list_for_each_entry(file, &ddev->filelist, lhead) {
93 struct drm_gem_object *gobj;
96 WARN_ONCE(1, "Still active user space clients!\n");
97 spin_lock(&file->table_lock);
98 idr_for_each_entry(&file->object_idr, gobj, handle) {
99 WARN_ONCE(1, "And also active allocations!\n");
100 drm_gem_object_put_unlocked(gobj);
102 idr_destroy(&file->object_idr);
103 spin_unlock(&file->table_lock);
106 mutex_unlock(&ddev->filelist_mutex);
110 * Call from drm_gem_handle_create which appear in both new and open ioctl
113 int amdgpu_gem_object_open(struct drm_gem_object *obj,
114 struct drm_file *file_priv)
116 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
117 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
118 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
119 struct amdgpu_vm *vm = &fpriv->vm;
120 struct amdgpu_bo_va *bo_va;
121 struct mm_struct *mm;
124 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
125 if (mm && mm != current->mm)
128 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
129 abo->tbo.resv != vm->root.base.bo->tbo.resv)
132 r = amdgpu_bo_reserve(abo, false);
136 bo_va = amdgpu_vm_bo_find(vm, abo);
138 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
142 amdgpu_bo_unreserve(abo);
146 void amdgpu_gem_object_close(struct drm_gem_object *obj,
147 struct drm_file *file_priv)
149 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
150 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
151 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
152 struct amdgpu_vm *vm = &fpriv->vm;
154 struct amdgpu_bo_list_entry vm_pd;
155 struct list_head list, duplicates;
156 struct ttm_validate_buffer tv;
157 struct ww_acquire_ctx ticket;
158 struct amdgpu_bo_va *bo_va;
161 INIT_LIST_HEAD(&list);
162 INIT_LIST_HEAD(&duplicates);
166 list_add(&tv.head, &list);
168 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
170 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
172 dev_err(adev->dev, "leaking bo va because "
173 "we fail to reserve bo (%d)\n", r);
176 bo_va = amdgpu_vm_bo_find(vm, bo);
177 if (bo_va && --bo_va->ref_count == 0) {
178 amdgpu_vm_bo_rmv(adev, bo_va);
180 if (amdgpu_vm_ready(vm)) {
181 struct dma_fence *fence = NULL;
183 r = amdgpu_vm_clear_freed(adev, vm, &fence);
185 dev_err(adev->dev, "failed to clear page "
186 "tables on GEM object close (%d)\n", r);
190 amdgpu_bo_fence(bo, fence, true);
191 dma_fence_put(fence);
195 ttm_eu_backoff_reservation(&ticket, &list);
201 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
202 struct drm_file *filp)
204 struct amdgpu_device *adev = dev->dev_private;
205 struct amdgpu_fpriv *fpriv = filp->driver_priv;
206 struct amdgpu_vm *vm = &fpriv->vm;
207 union drm_amdgpu_gem_create *args = data;
208 uint64_t flags = args->in.domain_flags;
209 uint64_t size = args->in.bo_size;
210 struct reservation_object *resv = NULL;
211 struct drm_gem_object *gobj;
215 /* reject invalid gem flags */
216 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
217 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
218 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
219 AMDGPU_GEM_CREATE_VRAM_CLEARED |
220 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
221 AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
225 /* reject invalid gem domains */
226 if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU |
227 AMDGPU_GEM_DOMAIN_GTT |
228 AMDGPU_GEM_DOMAIN_VRAM |
229 AMDGPU_GEM_DOMAIN_GDS |
230 AMDGPU_GEM_DOMAIN_GWS |
231 AMDGPU_GEM_DOMAIN_OA))
234 /* create a gem object to contain this object in */
235 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
236 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
237 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
238 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
239 size = size << AMDGPU_GDS_SHIFT;
240 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
241 size = size << AMDGPU_GWS_SHIFT;
242 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
243 size = size << AMDGPU_OA_SHIFT;
247 size = roundup(size, PAGE_SIZE);
249 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
250 r = amdgpu_bo_reserve(vm->root.base.bo, false);
254 resv = vm->root.base.bo->tbo.resv;
257 r = amdgpu_gem_object_create(adev, size, args->in.alignment,
258 (u32)(0xffffffff & args->in.domains),
259 flags, false, resv, &gobj);
260 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
262 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
264 abo->parent = amdgpu_bo_ref(vm->root.base.bo);
266 amdgpu_bo_unreserve(vm->root.base.bo);
271 r = drm_gem_handle_create(filp, gobj, &handle);
272 /* drop reference from allocate - handle holds it now */
273 drm_gem_object_put_unlocked(gobj);
277 memset(args, 0, sizeof(*args));
278 args->out.handle = handle;
282 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
283 struct drm_file *filp)
285 struct amdgpu_device *adev = dev->dev_private;
286 struct drm_amdgpu_gem_userptr *args = data;
287 struct drm_gem_object *gobj;
288 struct amdgpu_bo *bo;
292 if (offset_in_page(args->addr | args->size))
295 /* reject unknown flag values */
296 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
297 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
298 AMDGPU_GEM_USERPTR_REGISTER))
301 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
302 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
304 /* if we want to write to it we must install a MMU notifier */
308 /* create a gem object to contain this object in */
309 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
314 bo = gem_to_amdgpu_bo(gobj);
315 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
316 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
317 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
321 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
322 r = amdgpu_mn_register(bo, args->addr);
327 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
328 r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
331 goto unlock_mmap_sem;
333 r = amdgpu_bo_reserve(bo, true);
337 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
338 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
339 amdgpu_bo_unreserve(bo);
344 r = drm_gem_handle_create(filp, gobj, &handle);
345 /* drop reference from allocate - handle holds it now */
346 drm_gem_object_put_unlocked(gobj);
350 args->handle = handle;
354 release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false);
357 up_read(¤t->mm->mmap_sem);
360 drm_gem_object_put_unlocked(gobj);
365 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
366 struct drm_device *dev,
367 uint32_t handle, uint64_t *offset_p)
369 struct drm_gem_object *gobj;
370 struct amdgpu_bo *robj;
372 gobj = drm_gem_object_lookup(filp, handle);
376 robj = gem_to_amdgpu_bo(gobj);
377 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
378 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
379 drm_gem_object_put_unlocked(gobj);
382 *offset_p = amdgpu_bo_mmap_offset(robj);
383 drm_gem_object_put_unlocked(gobj);
387 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
388 struct drm_file *filp)
390 union drm_amdgpu_gem_mmap *args = data;
391 uint32_t handle = args->in.handle;
392 memset(args, 0, sizeof(*args));
393 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
397 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
399 * @timeout_ns: timeout in ns
401 * Calculate the timeout in jiffies from an absolute timeout in ns.
403 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
405 unsigned long timeout_jiffies;
408 /* clamp timeout if it's to large */
409 if (((int64_t)timeout_ns) < 0)
410 return MAX_SCHEDULE_TIMEOUT;
412 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
413 if (ktime_to_ns(timeout) < 0)
416 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
417 /* clamp timeout to avoid unsigned-> signed overflow */
418 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
419 return MAX_SCHEDULE_TIMEOUT - 1;
421 return timeout_jiffies;
424 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
425 struct drm_file *filp)
427 union drm_amdgpu_gem_wait_idle *args = data;
428 struct drm_gem_object *gobj;
429 struct amdgpu_bo *robj;
430 uint32_t handle = args->in.handle;
431 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
435 gobj = drm_gem_object_lookup(filp, handle);
439 robj = gem_to_amdgpu_bo(gobj);
440 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
443 /* ret == 0 means not signaled,
444 * ret > 0 means signaled
445 * ret < 0 means interrupted before timeout
448 memset(args, 0, sizeof(*args));
449 args->out.status = (ret == 0);
453 drm_gem_object_put_unlocked(gobj);
457 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
458 struct drm_file *filp)
460 struct drm_amdgpu_gem_metadata *args = data;
461 struct drm_gem_object *gobj;
462 struct amdgpu_bo *robj;
465 DRM_DEBUG("%d \n", args->handle);
466 gobj = drm_gem_object_lookup(filp, args->handle);
469 robj = gem_to_amdgpu_bo(gobj);
471 r = amdgpu_bo_reserve(robj, false);
472 if (unlikely(r != 0))
475 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
476 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
477 r = amdgpu_bo_get_metadata(robj, args->data.data,
478 sizeof(args->data.data),
479 &args->data.data_size_bytes,
481 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
482 if (args->data.data_size_bytes > sizeof(args->data.data)) {
486 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
488 r = amdgpu_bo_set_metadata(robj, args->data.data,
489 args->data.data_size_bytes,
494 amdgpu_bo_unreserve(robj);
496 drm_gem_object_put_unlocked(gobj);
501 * amdgpu_gem_va_update_vm -update the bo_va in its VM
503 * @adev: amdgpu_device pointer
505 * @bo_va: bo_va to update
506 * @list: validation list
507 * @operation: map, unmap or clear
509 * Update the bo_va directly after setting its address. Errors are not
510 * vital here, so they are not reported back to userspace.
512 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
513 struct amdgpu_vm *vm,
514 struct amdgpu_bo_va *bo_va,
515 struct list_head *list,
520 if (!amdgpu_vm_ready(vm))
523 r = amdgpu_vm_update_directories(adev, vm);
527 r = amdgpu_vm_clear_freed(adev, vm, NULL);
531 if (operation == AMDGPU_VA_OP_MAP ||
532 operation == AMDGPU_VA_OP_REPLACE)
533 r = amdgpu_vm_bo_update(adev, bo_va, false);
536 if (r && r != -ERESTARTSYS)
537 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
540 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
541 struct drm_file *filp)
543 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
544 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
545 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
546 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
549 struct drm_amdgpu_gem_va *args = data;
550 struct drm_gem_object *gobj;
551 struct amdgpu_device *adev = dev->dev_private;
552 struct amdgpu_fpriv *fpriv = filp->driver_priv;
553 struct amdgpu_bo *abo;
554 struct amdgpu_bo_va *bo_va;
555 struct amdgpu_bo_list_entry vm_pd;
556 struct ttm_validate_buffer tv;
557 struct ww_acquire_ctx ticket;
558 struct list_head list, duplicates;
562 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
563 dev_err(&dev->pdev->dev,
564 "va_address 0x%LX is in reserved area 0x%LX\n",
565 args->va_address, AMDGPU_VA_RESERVED_SIZE);
569 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
570 dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
575 switch (args->operation) {
576 case AMDGPU_VA_OP_MAP:
577 case AMDGPU_VA_OP_UNMAP:
578 case AMDGPU_VA_OP_CLEAR:
579 case AMDGPU_VA_OP_REPLACE:
582 dev_err(&dev->pdev->dev, "unsupported operation %d\n",
587 INIT_LIST_HEAD(&list);
588 INIT_LIST_HEAD(&duplicates);
589 if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
590 !(args->flags & AMDGPU_VM_PAGE_PRT)) {
591 gobj = drm_gem_object_lookup(filp, args->handle);
594 abo = gem_to_amdgpu_bo(gobj);
597 list_add(&tv.head, &list);
603 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
605 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
610 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
615 } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
616 bo_va = fpriv->prt_va;
621 switch (args->operation) {
622 case AMDGPU_VA_OP_MAP:
623 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
628 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
629 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
630 args->offset_in_bo, args->map_size,
633 case AMDGPU_VA_OP_UNMAP:
634 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
637 case AMDGPU_VA_OP_CLEAR:
638 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
642 case AMDGPU_VA_OP_REPLACE:
643 r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
648 va_flags = amdgpu_vm_get_pte_flags(adev, args->flags);
649 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
650 args->offset_in_bo, args->map_size,
656 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
657 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, &list,
661 ttm_eu_backoff_reservation(&ticket, &list);
664 drm_gem_object_put_unlocked(gobj);
668 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
669 struct drm_file *filp)
671 struct amdgpu_device *adev = dev->dev_private;
672 struct drm_amdgpu_gem_op *args = data;
673 struct drm_gem_object *gobj;
674 struct amdgpu_bo *robj;
677 gobj = drm_gem_object_lookup(filp, args->handle);
681 robj = gem_to_amdgpu_bo(gobj);
683 r = amdgpu_bo_reserve(robj, false);
688 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
689 struct drm_amdgpu_gem_create_in info;
690 void __user *out = u64_to_user_ptr(args->value);
692 info.bo_size = robj->gem_base.size;
693 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
694 info.domains = robj->preferred_domains;
695 info.domain_flags = robj->flags;
696 amdgpu_bo_unreserve(robj);
697 if (copy_to_user(out, &info, sizeof(info)))
701 case AMDGPU_GEM_OP_SET_PLACEMENT:
702 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) {
704 amdgpu_bo_unreserve(robj);
707 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
709 amdgpu_bo_unreserve(robj);
712 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
713 AMDGPU_GEM_DOMAIN_GTT |
714 AMDGPU_GEM_DOMAIN_CPU);
715 robj->allowed_domains = robj->preferred_domains;
716 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
717 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
719 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
720 amdgpu_vm_bo_invalidate(adev, robj, true);
722 amdgpu_bo_unreserve(robj);
725 amdgpu_bo_unreserve(robj);
730 drm_gem_object_put_unlocked(gobj);
734 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
735 struct drm_device *dev,
736 struct drm_mode_create_dumb *args)
738 struct amdgpu_device *adev = dev->dev_private;
739 struct drm_gem_object *gobj;
743 args->pitch = amdgpu_align_pitch(adev, args->width,
744 DIV_ROUND_UP(args->bpp, 8), 0);
745 args->size = (u64)args->pitch * args->height;
746 args->size = ALIGN(args->size, PAGE_SIZE);
748 r = amdgpu_gem_object_create(adev, args->size, 0,
749 AMDGPU_GEM_DOMAIN_VRAM,
750 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
755 r = drm_gem_handle_create(file_priv, gobj, &handle);
756 /* drop reference from allocate - handle holds it now */
757 drm_gem_object_put_unlocked(gobj);
761 args->handle = handle;
765 #if defined(CONFIG_DEBUG_FS)
766 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
768 struct drm_gem_object *gobj = ptr;
769 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
770 struct seq_file *m = data;
773 const char *placement;
777 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
779 case AMDGPU_GEM_DOMAIN_VRAM:
782 case AMDGPU_GEM_DOMAIN_GTT:
785 case AMDGPU_GEM_DOMAIN_CPU:
790 seq_printf(m, "\t0x%08x: %12ld byte %s",
791 id, amdgpu_bo_size(bo), placement);
793 offset = ACCESS_ONCE(bo->tbo.mem.start);
794 if (offset != AMDGPU_BO_INVALID_OFFSET)
795 seq_printf(m, " @ 0x%010Lx", offset);
797 pin_count = ACCESS_ONCE(bo->pin_count);
799 seq_printf(m, " pin count %d", pin_count);
805 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
807 struct drm_info_node *node = (struct drm_info_node *)m->private;
808 struct drm_device *dev = node->minor->dev;
809 struct drm_file *file;
812 r = mutex_lock_interruptible(&dev->filelist_mutex);
816 list_for_each_entry(file, &dev->filelist, lhead) {
817 struct task_struct *task;
820 * Although we have a valid reference on file->pid, that does
821 * not guarantee that the task_struct who called get_pid() is
822 * still alive (e.g. get_pid(current) => fork() => exit()).
823 * Therefore, we need to protect this ->comm access using RCU.
826 task = pid_task(file->pid, PIDTYPE_PID);
827 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
828 task ? task->comm : "<unknown>");
831 spin_lock(&file->table_lock);
832 idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
833 spin_unlock(&file->table_lock);
836 mutex_unlock(&dev->filelist_mutex);
840 static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
841 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
845 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev)
847 #if defined(CONFIG_DEBUG_FS)
848 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);