drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_discovery.h"
  28 #include "soc15_hw_ip.h"
  29 #include "discovery.h"
  30
  31 #include "soc15.h"
  32 #include "gfx_v9_0.h"
  33 #include "gfx_v9_4_3.h"
  34 #include "gmc_v9_0.h"
  35 #include "df_v1_7.h"
  36 #include "df_v3_6.h"
  37 #include "df_v4_3.h"
  38 #include "nbio_v6_1.h"
  39 #include "nbio_v7_0.h"
  40 #include "nbio_v7_4.h"
  41 #include "nbio_v7_9.h"
  42 #include "hdp_v4_0.h"
  43 #include "vega10_ih.h"
  44 #include "vega20_ih.h"
  45 #include "sdma_v4_0.h"
  46 #include "sdma_v4_4_2.h"
  47 #include "uvd_v7_0.h"
  48 #include "vce_v4_0.h"
  49 #include "vcn_v1_0.h"
  50 #include "vcn_v2_5.h"
  51 #include "jpeg_v2_5.h"
  52 #include "smuio_v9_0.h"
  53 #include "gmc_v10_0.h"
  54 #include "gmc_v11_0.h"
  55 #include "gfxhub_v2_0.h"
  56 #include "mmhub_v2_0.h"
  57 #include "nbio_v2_3.h"
  58 #include "nbio_v4_3.h"
  59 #include "nbio_v7_2.h"
  60 #include "nbio_v7_7.h"
  61 #include "hdp_v5_0.h"
  62 #include "hdp_v5_2.h"
  63 #include "hdp_v6_0.h"
  64 #include "nv.h"
  65 #include "soc21.h"
  66 #include "navi10_ih.h"
  67 #include "ih_v6_0.h"
  68 #include "ih_v6_1.h"
  69 #include "gfx_v10_0.h"
  70 #include "gfx_v11_0.h"
  71 #include "sdma_v5_0.h"
  72 #include "sdma_v5_2.h"
  73 #include "sdma_v6_0.h"
  74 #include "lsdma_v6_0.h"
  75 #include "vcn_v2_0.h"
  76 #include "jpeg_v2_0.h"
  77 #include "vcn_v3_0.h"
  78 #include "jpeg_v3_0.h"
  79 #include "vcn_v4_0.h"
  80 #include "jpeg_v4_0.h"
  81 #include "vcn_v4_0_3.h"
  82 #include "jpeg_v4_0_3.h"
  83 #include "amdgpu_vkms.h"
  84 #include "mes_v10_1.h"
  85 #include "mes_v11_0.h"
  86 #include "smuio_v11_0.h"
  87 #include "smuio_v11_0_6.h"
  88 #include "smuio_v13_0.h"
  89 #include "smuio_v13_0_3.h"
  90 #include "smuio_v13_0_6.h"
  91
  92 #define FIRMWARE_IP_DISCOVERY "amdgpu/ip_discovery.bin"
  93 MODULE_FIRMWARE(FIRMWARE_IP_DISCOVERY);
  94
  95 #define mmRCC_CONFIG_MEMSIZE    0xde3
  96 #define mmMM_INDEX              0x0
  97 #define mmMM_INDEX_HI           0x6
  98 #define mmMM_DATA               0x1
  99
 100 static const char *hw_id_names[HW_ID_MAX] = {
 101         [MP1_HWID]              = "MP1",
 102         [MP2_HWID]              = "MP2",
 103         [THM_HWID]              = "THM",
 104         [SMUIO_HWID]            = "SMUIO",
 105         [FUSE_HWID]             = "FUSE",
 106         [CLKA_HWID]             = "CLKA",
 107         [PWR_HWID]              = "PWR",
 108         [GC_HWID]               = "GC",
 109         [UVD_HWID]              = "UVD",
 110         [AUDIO_AZ_HWID]         = "AUDIO_AZ",
 111         [ACP_HWID]              = "ACP",
 112         [DCI_HWID]              = "DCI",
 113         [DMU_HWID]              = "DMU",
 114         [DCO_HWID]              = "DCO",
 115         [DIO_HWID]              = "DIO",
 116         [XDMA_HWID]             = "XDMA",
 117         [DCEAZ_HWID]            = "DCEAZ",
 118         [DAZ_HWID]              = "DAZ",
 119         [SDPMUX_HWID]           = "SDPMUX",
 120         [NTB_HWID]              = "NTB",
 121         [IOHC_HWID]             = "IOHC",
 122         [L2IMU_HWID]            = "L2IMU",
 123         [VCE_HWID]              = "VCE",
 124         [MMHUB_HWID]            = "MMHUB",
 125         [ATHUB_HWID]            = "ATHUB",
 126         [DBGU_NBIO_HWID]        = "DBGU_NBIO",
 127         [DFX_HWID]              = "DFX",
 128         [DBGU0_HWID]            = "DBGU0",
 129         [DBGU1_HWID]            = "DBGU1",
 130         [OSSSYS_HWID]           = "OSSSYS",
 131         [HDP_HWID]              = "HDP",
 132         [SDMA0_HWID]            = "SDMA0",
 133         [SDMA1_HWID]            = "SDMA1",
 134         [SDMA2_HWID]            = "SDMA2",
 135         [SDMA3_HWID]            = "SDMA3",
 136         [LSDMA_HWID]            = "LSDMA",
 137         [ISP_HWID]              = "ISP",
 138         [DBGU_IO_HWID]          = "DBGU_IO",
 139         [DF_HWID]               = "DF",
 140         [CLKB_HWID]             = "CLKB",
 141         [FCH_HWID]              = "FCH",
 142         [DFX_DAP_HWID]          = "DFX_DAP",
 143         [L1IMU_PCIE_HWID]       = "L1IMU_PCIE",
 144         [L1IMU_NBIF_HWID]       = "L1IMU_NBIF",
 145         [L1IMU_IOAGR_HWID]      = "L1IMU_IOAGR",
 146         [L1IMU3_HWID]           = "L1IMU3",
 147         [L1IMU4_HWID]           = "L1IMU4",
 148         [L1IMU5_HWID]           = "L1IMU5",
 149         [L1IMU6_HWID]           = "L1IMU6",
 150         [L1IMU7_HWID]           = "L1IMU7",
 151         [L1IMU8_HWID]           = "L1IMU8",
 152         [L1IMU9_HWID]           = "L1IMU9",
 153         [L1IMU10_HWID]          = "L1IMU10",
 154         [L1IMU11_HWID]          = "L1IMU11",
 155         [L1IMU12_HWID]          = "L1IMU12",
 156         [L1IMU13_HWID]          = "L1IMU13",
 157         [L1IMU14_HWID]          = "L1IMU14",
 158         [L1IMU15_HWID]          = "L1IMU15",
 159         [WAFLC_HWID]            = "WAFLC",
 160         [FCH_USB_PD_HWID]       = "FCH_USB_PD",
 161         [PCIE_HWID]             = "PCIE",
 162         [PCS_HWID]              = "PCS",
 163         [DDCL_HWID]             = "DDCL",
 164         [SST_HWID]              = "SST",
 165         [IOAGR_HWID]            = "IOAGR",
 166         [NBIF_HWID]             = "NBIF",
 167         [IOAPIC_HWID]           = "IOAPIC",
 168         [SYSTEMHUB_HWID]        = "SYSTEMHUB",
 169         [NTBCCP_HWID]           = "NTBCCP",
 170         [UMC_HWID]              = "UMC",
 171         [SATA_HWID]             = "SATA",
 172         [USB_HWID]              = "USB",
 173         [CCXSEC_HWID]           = "CCXSEC",
 174         [XGMI_HWID]             = "XGMI",
 175         [XGBE_HWID]             = "XGBE",
 176         [MP0_HWID]              = "MP0",
 177 };
 178
 179 static int hw_id_map[MAX_HWIP] = {
 180         [GC_HWIP]       = GC_HWID,
 181         [HDP_HWIP]      = HDP_HWID,
 182         [SDMA0_HWIP]    = SDMA0_HWID,
 183         [SDMA1_HWIP]    = SDMA1_HWID,
 184         [SDMA2_HWIP]    = SDMA2_HWID,
 185         [SDMA3_HWIP]    = SDMA3_HWID,
 186         [LSDMA_HWIP]    = LSDMA_HWID,
 187         [MMHUB_HWIP]    = MMHUB_HWID,
 188         [ATHUB_HWIP]    = ATHUB_HWID,
 189         [NBIO_HWIP]     = NBIF_HWID,
 190         [MP0_HWIP]      = MP0_HWID,
 191         [MP1_HWIP]      = MP1_HWID,
 192         [UVD_HWIP]      = UVD_HWID,
 193         [VCE_HWIP]      = VCE_HWID,
 194         [DF_HWIP]       = DF_HWID,
 195         [DCE_HWIP]      = DMU_HWID,
 196         [OSSSYS_HWIP]   = OSSSYS_HWID,
 197         [SMUIO_HWIP]    = SMUIO_HWID,
 198         [PWR_HWIP]      = PWR_HWID,
 199         [NBIF_HWIP]     = NBIF_HWID,
 200         [THM_HWIP]      = THM_HWID,
 201         [CLK_HWIP]      = CLKA_HWID,
 202         [UMC_HWIP]      = UMC_HWID,
 203         [XGMI_HWIP]     = XGMI_HWID,
 204         [DCI_HWIP]      = DCI_HWID,
 205         [PCIE_HWIP]     = PCIE_HWID,
 206 };
 207
 208 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary)
 209 {
 210         u64 tmr_offset, tmr_size, pos;
 211         void *discv_regn;
 212         int ret;
 213
 214         ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size);
 215         if (ret)
 216                 return ret;
 217
 218         pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET;
 219
 220         /* This region is read-only and reserved from system use */
 221         discv_regn = memremap(pos, adev->mman.discovery_tmr_size, MEMREMAP_WC);
 222         if (discv_regn) {
 223                 memcpy(binary, discv_regn, adev->mman.discovery_tmr_size);
 224                 memunmap(discv_regn);
 225                 return 0;
 226         }
 227
 228         return -ENOENT;
 229 }
 230
 231 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev,
 232                                                  uint8_t *binary)
 233 {
 234         uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
 235         int ret = 0;
 236
 237         if (vram_size) {
 238                 uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
 239                 amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
 240                                           adev->mman.discovery_tmr_size, false);
 241         } else {
 242                 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary);
 243         }
 244
 245         return ret;
 246 }
 247
 248 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, uint8_t *binary)
 249 {
 250         const struct firmware *fw;
 251         const char *fw_name;
 252         int r;
 253
 254         switch (amdgpu_discovery) {
 255         case 2:
 256                 fw_name = FIRMWARE_IP_DISCOVERY;
 257                 break;
 258         default:
 259                 dev_warn(adev->dev, "amdgpu_discovery is not set properly\n");
 260                 return -EINVAL;
 261         }
 262
 263         r = request_firmware(&fw, fw_name, adev->dev);
 264         if (r) {
 265                 dev_err(adev->dev, "can't load firmware \"%s\"\n",
 266                         fw_name);
 267                 return r;
 268         }
 269
 270         memcpy((u8 *)binary, (u8 *)fw->data, fw->size);
 271         release_firmware(fw);
 272
 273         return 0;
 274 }
 275
 276 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
 277 {
 278         uint16_t checksum = 0;
 279         int i;
 280
 281         for (i = 0; i < size; i++)
 282                 checksum += data[i];
 283
 284         return checksum;
 285 }
 286
 287 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
 288                                                     uint16_t expected)
 289 {
 290         return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
 291 }
 292
 293 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
 294 {
 295         struct binary_header *bhdr;
 296         bhdr = (struct binary_header *)binary;
 297
 298         return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
 299 }
 300
 301 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)
 302 {
 303         /*
 304          * So far, apply this quirk only on those Navy Flounder boards which
 305          * have a bad harvest table of VCN config.
 306          */
 307         if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) &&
 308                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) {
 309                 switch (adev->pdev->revision) {
 310                 case 0xC1:
 311                 case 0xC2:
 312                 case 0xC3:
 313                 case 0xC5:
 314                 case 0xC7:
 315                 case 0xCF:
 316                 case 0xDF:
 317                         adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 318                         adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1;
 319                         break;
 320                 default:
 321                         break;
 322                 }
 323         }
 324 }
 325
 326 static int amdgpu_discovery_init(struct amdgpu_device *adev)
 327 {
 328         struct table_info *info;
 329         struct binary_header *bhdr;
 330         uint16_t offset;
 331         uint16_t size;
 332         uint16_t checksum;
 333         int r;
 334
 335         adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;
 336         adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);
 337         if (!adev->mman.discovery_bin)
 338                 return -ENOMEM;
 339
 340         /* Read from file if it is the preferred option */
 341         if (amdgpu_discovery == 2) {
 342                 dev_info(adev->dev, "use ip discovery information from file");
 343                 r = amdgpu_discovery_read_binary_from_file(adev, adev->mman.discovery_bin);
 344
 345                 if (r) {
 346                         dev_err(adev->dev, "failed to read ip discovery binary from file\n");
 347                         r = -EINVAL;
 348                         goto out;
 349                 }
 350
 351         } else {
 352                 r = amdgpu_discovery_read_binary_from_mem(
 353                         adev, adev->mman.discovery_bin);
 354                 if (r)
 355                         goto out;
 356         }
 357
 358         /* check the ip discovery binary signature */
 359         if (!amdgpu_discovery_verify_binary_signature(adev->mman.discovery_bin)) {
 360                 dev_err(adev->dev,
 361                         "get invalid ip discovery binary signature\n");
 362                 r = -EINVAL;
 363                 goto out;
 364         }
 365
 366         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 367
 368         offset = offsetof(struct binary_header, binary_checksum) +
 369                 sizeof(bhdr->binary_checksum);
 370         size = le16_to_cpu(bhdr->binary_size) - offset;
 371         checksum = le16_to_cpu(bhdr->binary_checksum);
 372
 373         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 374                                               size, checksum)) {
 375                 dev_err(adev->dev, "invalid ip discovery binary checksum\n");
 376                 r = -EINVAL;
 377                 goto out;
 378         }
 379
 380         info = &bhdr->table_list[IP_DISCOVERY];
 381         offset = le16_to_cpu(info->offset);
 382         checksum = le16_to_cpu(info->checksum);
 383
 384         if (offset) {
 385                 struct ip_discovery_header *ihdr =
 386                         (struct ip_discovery_header *)(adev->mman.discovery_bin + offset);
 387                 if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
 388                         dev_err(adev->dev, "invalid ip discovery data table signature\n");
 389                         r = -EINVAL;
 390                         goto out;
 391                 }
 392
 393                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 394                                                       le16_to_cpu(ihdr->size), checksum)) {
 395                         dev_err(adev->dev, "invalid ip discovery data table checksum\n");
 396                         r = -EINVAL;
 397                         goto out;
 398                 }
 399         }
 400
 401         info = &bhdr->table_list[GC];
 402         offset = le16_to_cpu(info->offset);
 403         checksum = le16_to_cpu(info->checksum);
 404
 405         if (offset) {
 406                 struct gpu_info_header *ghdr =
 407                         (struct gpu_info_header *)(adev->mman.discovery_bin + offset);
 408
 409                 if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) {
 410                         dev_err(adev->dev, "invalid ip discovery gc table id\n");
 411                         r = -EINVAL;
 412                         goto out;
 413                 }
 414
 415                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 416                                                       le32_to_cpu(ghdr->size), checksum)) {
 417                         dev_err(adev->dev, "invalid gc data table checksum\n");
 418                         r = -EINVAL;
 419                         goto out;
 420                 }
 421         }
 422
 423         info = &bhdr->table_list[HARVEST_INFO];
 424         offset = le16_to_cpu(info->offset);
 425         checksum = le16_to_cpu(info->checksum);
 426
 427         if (offset) {
 428                 struct harvest_info_header *hhdr =
 429                         (struct harvest_info_header *)(adev->mman.discovery_bin + offset);
 430
 431                 if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) {
 432                         dev_err(adev->dev, "invalid ip discovery harvest table signature\n");
 433                         r = -EINVAL;
 434                         goto out;
 435                 }
 436
 437                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 438                                                       sizeof(struct harvest_table), checksum)) {
 439                         dev_err(adev->dev, "invalid harvest data table checksum\n");
 440                         r = -EINVAL;
 441                         goto out;
 442                 }
 443         }
 444
 445         info = &bhdr->table_list[VCN_INFO];
 446         offset = le16_to_cpu(info->offset);
 447         checksum = le16_to_cpu(info->checksum);
 448
 449         if (offset) {
 450                 struct vcn_info_header *vhdr =
 451                         (struct vcn_info_header *)(adev->mman.discovery_bin + offset);
 452
 453                 if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) {
 454                         dev_err(adev->dev, "invalid ip discovery vcn table id\n");
 455                         r = -EINVAL;
 456                         goto out;
 457                 }
 458
 459                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 460                                                       le32_to_cpu(vhdr->size_bytes), checksum)) {
 461                         dev_err(adev->dev, "invalid vcn data table checksum\n");
 462                         r = -EINVAL;
 463                         goto out;
 464                 }
 465         }
 466
 467         info = &bhdr->table_list[MALL_INFO];
 468         offset = le16_to_cpu(info->offset);
 469         checksum = le16_to_cpu(info->checksum);
 470
 471         if (0 && offset) {
 472                 struct mall_info_header *mhdr =
 473                         (struct mall_info_header *)(adev->mman.discovery_bin + offset);
 474
 475                 if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) {
 476                         dev_err(adev->dev, "invalid ip discovery mall table id\n");
 477                         r = -EINVAL;
 478                         goto out;
 479                 }
 480
 481                 if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 482                                                       le32_to_cpu(mhdr->size_bytes), checksum)) {
 483                         dev_err(adev->dev, "invalid mall data table checksum\n");
 484                         r = -EINVAL;
 485                         goto out;
 486                 }
 487         }
 488
 489         return 0;
 490
 491 out:
 492         kfree(adev->mman.discovery_bin);
 493         adev->mman.discovery_bin = NULL;
 494
 495         return r;
 496 }
 497
 498 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev);
 499
 500 void amdgpu_discovery_fini(struct amdgpu_device *adev)
 501 {
 502         amdgpu_discovery_sysfs_fini(adev);
 503         kfree(adev->mman.discovery_bin);
 504         adev->mman.discovery_bin = NULL;
 505 }
 506
 507 static int amdgpu_discovery_validate_ip(const struct ip_v4 *ip)
 508 {
 509         if (ip->instance_number >= HWIP_MAX_INSTANCE) {
 510                 DRM_ERROR("Unexpected instance_number (%d) from ip discovery blob\n",
 511                           ip->instance_number);
 512                 return -EINVAL;
 513         }
 514         if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) {
 515                 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n",
 516                           le16_to_cpu(ip->hw_id));
 517                 return -EINVAL;
 518         }
 519
 520         return 0;
 521 }
 522
 523 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev,
 524                                                 uint32_t *vcn_harvest_count)
 525 {
 526         struct binary_header *bhdr;
 527         struct ip_discovery_header *ihdr;
 528         struct die_header *dhdr;
 529         struct ip_v4 *ip;
 530         uint16_t die_offset, ip_offset, num_dies, num_ips;
 531         int i, j;
 532
 533         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 534         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 535                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 536         num_dies = le16_to_cpu(ihdr->num_dies);
 537
 538         /* scan harvest bit of all IP data structures */
 539         for (i = 0; i < num_dies; i++) {
 540                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
 541                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 542                 num_ips = le16_to_cpu(dhdr->num_ips);
 543                 ip_offset = die_offset + sizeof(*dhdr);
 544
 545                 for (j = 0; j < num_ips; j++) {
 546                         ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset);
 547
 548                         if (amdgpu_discovery_validate_ip(ip))
 549                                 goto next_ip;
 550
 551                         if (le16_to_cpu(ip->variant) == 1) {
 552                                 switch (le16_to_cpu(ip->hw_id)) {
 553                                 case VCN_HWID:
 554                                         (*vcn_harvest_count)++;
 555                                         if (ip->instance_number == 0) {
 556                                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
 557                                                 adev->vcn.inst_mask &=
 558                                                         ~AMDGPU_VCN_HARVEST_VCN0;
 559                                                 adev->jpeg.inst_mask &=
 560                                                         ~AMDGPU_VCN_HARVEST_VCN0;
 561                                         } else {
 562                                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 563                                                 adev->vcn.inst_mask &=
 564                                                         ~AMDGPU_VCN_HARVEST_VCN1;
 565                                                 adev->jpeg.inst_mask &=
 566                                                         ~AMDGPU_VCN_HARVEST_VCN1;
 567                                         }
 568                                         break;
 569                                 case DMU_HWID:
 570                                         adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
 571                                         break;
 572                                 default:
 573                                         break;
 574                                 }
 575                         }
 576 next_ip:
 577                         if (ihdr->base_addr_64_bit)
 578                                 ip_offset += struct_size(ip, base_address_64, ip->num_base_address);
 579                         else
 580                                 ip_offset += struct_size(ip, base_address, ip->num_base_address);
 581                 }
 582         }
 583 }
 584
 585 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev,
 586                                                      uint32_t *vcn_harvest_count,
 587                                                      uint32_t *umc_harvest_count)
 588 {
 589         struct binary_header *bhdr;
 590         struct harvest_table *harvest_info;
 591         u16 offset;
 592         int i;
 593         uint32_t umc_harvest_config = 0;
 594
 595         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 596         offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset);
 597
 598         if (!offset) {
 599                 dev_err(adev->dev, "invalid harvest table offset\n");
 600                 return;
 601         }
 602
 603         harvest_info = (struct harvest_table *)(adev->mman.discovery_bin + offset);
 604
 605         for (i = 0; i < 32; i++) {
 606                 if (le16_to_cpu(harvest_info->list[i].hw_id) == 0)
 607                         break;
 608
 609                 switch (le16_to_cpu(harvest_info->list[i].hw_id)) {
 610                 case VCN_HWID:
 611                         (*vcn_harvest_count)++;
 612                         adev->vcn.harvest_config |=
 613                                 (1 << harvest_info->list[i].number_instance);
 614                         adev->jpeg.harvest_config |=
 615                                 (1 << harvest_info->list[i].number_instance);
 616
 617                         adev->vcn.inst_mask &=
 618                                 ~(1U << harvest_info->list[i].number_instance);
 619                         adev->jpeg.inst_mask &=
 620                                 ~(1U << harvest_info->list[i].number_instance);
 621                         break;
 622                 case DMU_HWID:
 623                         adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
 624                         break;
 625                 case UMC_HWID:
 626                         umc_harvest_config |=
 627                                 1 << (le16_to_cpu(harvest_info->list[i].number_instance));
 628                         (*umc_harvest_count)++;
 629                         break;
 630                 case GC_HWID:
 631                         adev->gfx.xcc_mask &=
 632                                 ~(1U << harvest_info->list[i].number_instance);
 633                         break;
 634                 case SDMA0_HWID:
 635                         adev->sdma.sdma_mask &=
 636                                 ~(1U << harvest_info->list[i].number_instance);
 637                         break;
 638                 default:
 639                         break;
 640                 }
 641         }
 642
 643         adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) &
 644                                 ~umc_harvest_config;
 645 }
 646
 647 /* ================================================== */
 648
 649 struct ip_hw_instance {
 650         struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */
 651
 652         int hw_id;
 653         u8  num_instance;
 654         u8  major, minor, revision;
 655         u8  harvest;
 656
 657         int num_base_addresses;
 658         u32 base_addr[];
 659 };
 660
 661 struct ip_hw_id {
 662         struct kset hw_id_kset;  /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */
 663         int hw_id;
 664 };
 665
 666 struct ip_die_entry {
 667         struct kset ip_kset;     /* ip_discovery/die/#die/, contains ip_hw_id  */
 668         u16 num_ips;
 669 };
 670
 671 /* -------------------------------------------------- */
 672
 673 struct ip_hw_instance_attr {
 674         struct attribute attr;
 675         ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf);
 676 };
 677
 678 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 679 {
 680         return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id);
 681 }
 682
 683 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 684 {
 685         return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance);
 686 }
 687
 688 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 689 {
 690         return sysfs_emit(buf, "%d\n", ip_hw_instance->major);
 691 }
 692
 693 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 694 {
 695         return sysfs_emit(buf, "%d\n", ip_hw_instance->minor);
 696 }
 697
 698 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 699 {
 700         return sysfs_emit(buf, "%d\n", ip_hw_instance->revision);
 701 }
 702
 703 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 704 {
 705         return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest);
 706 }
 707
 708 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 709 {
 710         return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses);
 711 }
 712
 713 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf)
 714 {
 715         ssize_t res, at;
 716         int ii;
 717
 718         for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) {
 719                 /* Here we satisfy the condition that, at + size <= PAGE_SIZE.
 720                  */
 721                 if (at + 12 > PAGE_SIZE)
 722                         break;
 723                 res = sysfs_emit_at(buf, at, "0x%08X\n",
 724                                     ip_hw_instance->base_addr[ii]);
 725                 if (res <= 0)
 726                         break;
 727                 at += res;
 728         }
 729
 730         return res < 0 ? res : at;
 731 }
 732
 733 static struct ip_hw_instance_attr ip_hw_attr[] = {
 734         __ATTR_RO(hw_id),
 735         __ATTR_RO(num_instance),
 736         __ATTR_RO(major),
 737         __ATTR_RO(minor),
 738         __ATTR_RO(revision),
 739         __ATTR_RO(harvest),
 740         __ATTR_RO(num_base_addresses),
 741         __ATTR_RO(base_addr),
 742 };
 743
 744 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1];
 745 ATTRIBUTE_GROUPS(ip_hw_instance);
 746
 747 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj)
 748 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr)
 749
 750 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj,
 751                                         struct attribute *attr,
 752                                         char *buf)
 753 {
 754         struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
 755         struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr);
 756
 757         if (!ip_hw_attr->show)
 758                 return -EIO;
 759
 760         return ip_hw_attr->show(ip_hw_instance, buf);
 761 }
 762
 763 static const struct sysfs_ops ip_hw_instance_sysfs_ops = {
 764         .show = ip_hw_instance_attr_show,
 765 };
 766
 767 static void ip_hw_instance_release(struct kobject *kobj)
 768 {
 769         struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
 770
 771         kfree(ip_hw_instance);
 772 }
 773
 774 static const struct kobj_type ip_hw_instance_ktype = {
 775         .release = ip_hw_instance_release,
 776         .sysfs_ops = &ip_hw_instance_sysfs_ops,
 777         .default_groups = ip_hw_instance_groups,
 778 };
 779
 780 /* -------------------------------------------------- */
 781
 782 #define to_ip_hw_id(x)  container_of(to_kset(x), struct ip_hw_id, hw_id_kset)
 783
 784 static void ip_hw_id_release(struct kobject *kobj)
 785 {
 786         struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj);
 787
 788         if (!list_empty(&ip_hw_id->hw_id_kset.list))
 789                 DRM_ERROR("ip_hw_id->hw_id_kset is not empty");
 790         kfree(ip_hw_id);
 791 }
 792
 793 static const struct kobj_type ip_hw_id_ktype = {
 794         .release = ip_hw_id_release,
 795         .sysfs_ops = &kobj_sysfs_ops,
 796 };
 797
 798 /* -------------------------------------------------- */
 799
 800 static void die_kobj_release(struct kobject *kobj);
 801 static void ip_disc_release(struct kobject *kobj);
 802
 803 struct ip_die_entry_attribute {
 804         struct attribute attr;
 805         ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf);
 806 };
 807
 808 #define to_ip_die_entry_attr(x)  container_of(x, struct ip_die_entry_attribute, attr)
 809
 810 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf)
 811 {
 812         return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips);
 813 }
 814
 815 /* If there are more ip_die_entry attrs, other than the number of IPs,
 816  * we can make this intro an array of attrs, and then initialize
 817  * ip_die_entry_attrs in a loop.
 818  */
 819 static struct ip_die_entry_attribute num_ips_attr =
 820         __ATTR_RO(num_ips);
 821
 822 static struct attribute *ip_die_entry_attrs[] = {
 823         &num_ips_attr.attr,
 824         NULL,
 825 };
 826 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */
 827
 828 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset)
 829
 830 static ssize_t ip_die_entry_attr_show(struct kobject *kobj,
 831                                       struct attribute *attr,
 832                                       char *buf)
 833 {
 834         struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr);
 835         struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
 836
 837         if (!ip_die_entry_attr->show)
 838                 return -EIO;
 839
 840         return ip_die_entry_attr->show(ip_die_entry, buf);
 841 }
 842
 843 static void ip_die_entry_release(struct kobject *kobj)
 844 {
 845         struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
 846
 847         if (!list_empty(&ip_die_entry->ip_kset.list))
 848                 DRM_ERROR("ip_die_entry->ip_kset is not empty");
 849         kfree(ip_die_entry);
 850 }
 851
 852 static const struct sysfs_ops ip_die_entry_sysfs_ops = {
 853         .show = ip_die_entry_attr_show,
 854 };
 855
 856 static const struct kobj_type ip_die_entry_ktype = {
 857         .release = ip_die_entry_release,
 858         .sysfs_ops = &ip_die_entry_sysfs_ops,
 859         .default_groups = ip_die_entry_groups,
 860 };
 861
 862 static const struct kobj_type die_kobj_ktype = {
 863         .release = die_kobj_release,
 864         .sysfs_ops = &kobj_sysfs_ops,
 865 };
 866
 867 static const struct kobj_type ip_discovery_ktype = {
 868         .release = ip_disc_release,
 869         .sysfs_ops = &kobj_sysfs_ops,
 870 };
 871
 872 struct ip_discovery_top {
 873         struct kobject kobj;    /* ip_discovery/ */
 874         struct kset die_kset;   /* ip_discovery/die/, contains ip_die_entry */
 875         struct amdgpu_device *adev;
 876 };
 877
 878 static void die_kobj_release(struct kobject *kobj)
 879 {
 880         struct ip_discovery_top *ip_top = container_of(to_kset(kobj),
 881                                                        struct ip_discovery_top,
 882                                                        die_kset);
 883         if (!list_empty(&ip_top->die_kset.list))
 884                 DRM_ERROR("ip_top->die_kset is not empty");
 885 }
 886
 887 static void ip_disc_release(struct kobject *kobj)
 888 {
 889         struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top,
 890                                                        kobj);
 891         struct amdgpu_device *adev = ip_top->adev;
 892
 893         adev->ip_top = NULL;
 894         kfree(ip_top);
 895 }
 896
 897 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev,
 898                                                  uint16_t hw_id, uint8_t inst)
 899 {
 900         uint8_t harvest = 0;
 901
 902         /* Until a uniform way is figured, get mask based on hwid */
 903         switch (hw_id) {
 904         case VCN_HWID:
 905                 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0;
 906                 break;
 907         case DMU_HWID:
 908                 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK)
 909                         harvest = 0x1;
 910                 break;
 911         case UMC_HWID:
 912                 /* TODO: It needs another parsing; for now, ignore.*/
 913                 break;
 914         case GC_HWID:
 915                 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0;
 916                 break;
 917         case SDMA0_HWID:
 918                 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0;
 919                 break;
 920         default:
 921                 break;
 922         }
 923
 924         return harvest;
 925 }
 926
 927 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,
 928                                       struct ip_die_entry *ip_die_entry,
 929                                       const size_t _ip_offset, const int num_ips,
 930                                       bool reg_base_64)
 931 {
 932         int ii, jj, kk, res;
 933
 934         DRM_DEBUG("num_ips:%d", num_ips);
 935
 936         /* Find all IPs of a given HW ID, and add their instance to
 937          * #die/#hw_id/#instance/<attributes>
 938          */
 939         for (ii = 0; ii < HW_ID_MAX; ii++) {
 940                 struct ip_hw_id *ip_hw_id = NULL;
 941                 size_t ip_offset = _ip_offset;
 942
 943                 for (jj = 0; jj < num_ips; jj++) {
 944                         struct ip_v4 *ip;
 945                         struct ip_hw_instance *ip_hw_instance;
 946
 947                         ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset);
 948                         if (amdgpu_discovery_validate_ip(ip) ||
 949                             le16_to_cpu(ip->hw_id) != ii)
 950                                 goto next_ip;
 951
 952                         DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset);
 953
 954                         /* We have a hw_id match; register the hw
 955                          * block if not yet registered.
 956                          */
 957                         if (!ip_hw_id) {
 958                                 ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL);
 959                                 if (!ip_hw_id)
 960                                         return -ENOMEM;
 961                                 ip_hw_id->hw_id = ii;
 962
 963                                 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii);
 964                                 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset;
 965                                 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype;
 966                                 res = kset_register(&ip_hw_id->hw_id_kset);
 967                                 if (res) {
 968                                         DRM_ERROR("Couldn't register ip_hw_id kset");
 969                                         kfree(ip_hw_id);
 970                                         return res;
 971                                 }
 972                                 if (hw_id_names[ii]) {
 973                                         res = sysfs_create_link(&ip_die_entry->ip_kset.kobj,
 974                                                                 &ip_hw_id->hw_id_kset.kobj,
 975                                                                 hw_id_names[ii]);
 976                                         if (res) {
 977                                                 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n",
 978                                                           hw_id_names[ii],
 979                                                           kobject_name(&ip_die_entry->ip_kset.kobj));
 980                                         }
 981                                 }
 982                         }
 983
 984                         /* Now register its instance.
 985                          */
 986                         ip_hw_instance = kzalloc(struct_size(ip_hw_instance,
 987                                                              base_addr,
 988                                                              ip->num_base_address),
 989                                                  GFP_KERNEL);
 990                         if (!ip_hw_instance) {
 991                                 DRM_ERROR("no memory for ip_hw_instance");
 992                                 return -ENOMEM;
 993                         }
 994                         ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */
 995                         ip_hw_instance->num_instance = ip->instance_number;
 996                         ip_hw_instance->major = ip->major;
 997                         ip_hw_instance->minor = ip->minor;
 998                         ip_hw_instance->revision = ip->revision;
 999                         ip_hw_instance->harvest =
1000                                 amdgpu_discovery_get_harvest_info(
1001                                         adev, ip_hw_instance->hw_id,
1002                                         ip_hw_instance->num_instance);
1003                         ip_hw_instance->num_base_addresses = ip->num_base_address;
1004
1005                         for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) {
1006                                 if (reg_base_64)
1007                                         ip_hw_instance->base_addr[kk] =
1008                                                 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF;
1009                                 else
1010                                         ip_hw_instance->base_addr[kk] = ip->base_address[kk];
1011                         }
1012
1013                         kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype);
1014                         ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset;
1015                         res = kobject_add(&ip_hw_instance->kobj, NULL,
1016                                           "%d", ip_hw_instance->num_instance);
1017 next_ip:
1018                         if (reg_base_64)
1019                                 ip_offset += struct_size(ip, base_address_64,
1020                                                          ip->num_base_address);
1021                         else
1022                                 ip_offset += struct_size(ip, base_address,
1023                                                          ip->num_base_address);
1024                 }
1025         }
1026
1027         return 0;
1028 }
1029
1030 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev)
1031 {
1032         struct binary_header *bhdr;
1033         struct ip_discovery_header *ihdr;
1034         struct die_header *dhdr;
1035         struct kset *die_kset = &adev->ip_top->die_kset;
1036         u16 num_dies, die_offset, num_ips;
1037         size_t ip_offset;
1038         int ii, res;
1039
1040         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1041         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1042                                               le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
1043         num_dies = le16_to_cpu(ihdr->num_dies);
1044
1045         DRM_DEBUG("number of dies: %d\n", num_dies);
1046
1047         for (ii = 0; ii < num_dies; ii++) {
1048                 struct ip_die_entry *ip_die_entry;
1049
1050                 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset);
1051                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
1052                 num_ips = le16_to_cpu(dhdr->num_ips);
1053                 ip_offset = die_offset + sizeof(*dhdr);
1054
1055                 /* Add the die to the kset.
1056                  *
1057                  * dhdr->die_id == ii, which was checked in
1058                  * amdgpu_discovery_reg_base_init().
1059                  */
1060
1061                 ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL);
1062                 if (!ip_die_entry)
1063                         return -ENOMEM;
1064
1065                 ip_die_entry->num_ips = num_ips;
1066
1067                 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id));
1068                 ip_die_entry->ip_kset.kobj.kset = die_kset;
1069                 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype;
1070                 res = kset_register(&ip_die_entry->ip_kset);
1071                 if (res) {
1072                         DRM_ERROR("Couldn't register ip_die_entry kset");
1073                         kfree(ip_die_entry);
1074                         return res;
1075                 }
1076
1077                 amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips, !!ihdr->base_addr_64_bit);
1078         }
1079
1080         return 0;
1081 }
1082
1083 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)
1084 {
1085         struct kset *die_kset;
1086         int res, ii;
1087
1088         if (!adev->mman.discovery_bin)
1089                 return -EINVAL;
1090
1091         adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL);
1092         if (!adev->ip_top)
1093                 return -ENOMEM;
1094
1095         adev->ip_top->adev = adev;
1096
1097         res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype,
1098                                    &adev->dev->kobj, "ip_discovery");
1099         if (res) {
1100                 DRM_ERROR("Couldn't init and add ip_discovery/");
1101                 goto Err;
1102         }
1103
1104         die_kset = &adev->ip_top->die_kset;
1105         kobject_set_name(&die_kset->kobj, "%s", "die");
1106         die_kset->kobj.parent = &adev->ip_top->kobj;
1107         die_kset->kobj.ktype = &die_kobj_ktype;
1108         res = kset_register(&adev->ip_top->die_kset);
1109         if (res) {
1110                 DRM_ERROR("Couldn't register die_kset");
1111                 goto Err;
1112         }
1113
1114         for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
1115                 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
1116         ip_hw_instance_attrs[ii] = NULL;
1117
1118         res = amdgpu_discovery_sysfs_recurse(adev);
1119
1120         return res;
1121 Err:
1122         kobject_put(&adev->ip_top->kobj);
1123         return res;
1124 }
1125
1126 /* -------------------------------------------------- */
1127
1128 #define list_to_kobj(el) container_of(el, struct kobject, entry)
1129
1130 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id)
1131 {
1132         struct list_head *el, *tmp;
1133         struct kset *hw_id_kset;
1134
1135         hw_id_kset = &ip_hw_id->hw_id_kset;
1136         spin_lock(&hw_id_kset->list_lock);
1137         list_for_each_prev_safe(el, tmp, &hw_id_kset->list) {
1138                 list_del_init(el);
1139                 spin_unlock(&hw_id_kset->list_lock);
1140                 /* kobject is embedded in ip_hw_instance */
1141                 kobject_put(list_to_kobj(el));
1142                 spin_lock(&hw_id_kset->list_lock);
1143         }
1144         spin_unlock(&hw_id_kset->list_lock);
1145         kobject_put(&ip_hw_id->hw_id_kset.kobj);
1146 }
1147
1148 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry)
1149 {
1150         struct list_head *el, *tmp;
1151         struct kset *ip_kset;
1152
1153         ip_kset = &ip_die_entry->ip_kset;
1154         spin_lock(&ip_kset->list_lock);
1155         list_for_each_prev_safe(el, tmp, &ip_kset->list) {
1156                 list_del_init(el);
1157                 spin_unlock(&ip_kset->list_lock);
1158                 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el)));
1159                 spin_lock(&ip_kset->list_lock);
1160         }
1161         spin_unlock(&ip_kset->list_lock);
1162         kobject_put(&ip_die_entry->ip_kset.kobj);
1163 }
1164
1165 static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
1166 {
1167         struct list_head *el, *tmp;
1168         struct kset *die_kset;
1169
1170         die_kset = &adev->ip_top->die_kset;
1171         spin_lock(&die_kset->list_lock);
1172         list_for_each_prev_safe(el, tmp, &die_kset->list) {
1173                 list_del_init(el);
1174                 spin_unlock(&die_kset->list_lock);
1175                 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
1176                 spin_lock(&die_kset->list_lock);
1177         }
1178         spin_unlock(&die_kset->list_lock);
1179         kobject_put(&adev->ip_top->die_kset.kobj);
1180         kobject_put(&adev->ip_top->kobj);
1181 }
1182
1183 /* ================================================== */
1184
1185 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
1186 {
1187         struct binary_header *bhdr;
1188         struct ip_discovery_header *ihdr;
1189         struct die_header *dhdr;
1190         struct ip_v4 *ip;
1191         uint16_t die_offset;
1192         uint16_t ip_offset;
1193         uint16_t num_dies;
1194         uint16_t num_ips;
1195         uint8_t num_base_address;
1196         int hw_ip;
1197         int i, j, k;
1198         int r;
1199
1200         r = amdgpu_discovery_init(adev);
1201         if (r) {
1202                 DRM_ERROR("amdgpu_discovery_init failed\n");
1203                 return r;
1204         }
1205
1206         adev->gfx.xcc_mask = 0;
1207         adev->sdma.sdma_mask = 0;
1208         adev->vcn.inst_mask = 0;
1209         adev->jpeg.inst_mask = 0;
1210         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1211         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
1212                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
1213         num_dies = le16_to_cpu(ihdr->num_dies);
1214
1215         DRM_DEBUG("number of dies: %d\n", num_dies);
1216
1217         for (i = 0; i < num_dies; i++) {
1218                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
1219                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
1220                 num_ips = le16_to_cpu(dhdr->num_ips);
1221                 ip_offset = die_offset + sizeof(*dhdr);
1222
1223                 if (le16_to_cpu(dhdr->die_id) != i) {
1224                         DRM_ERROR("invalid die id %d, expected %d\n",
1225                                         le16_to_cpu(dhdr->die_id), i);
1226                         return -EINVAL;
1227                 }
1228
1229                 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
1230                                 le16_to_cpu(dhdr->die_id), num_ips);
1231
1232                 for (j = 0; j < num_ips; j++) {
1233                         ip = (struct ip_v4 *)(adev->mman.discovery_bin + ip_offset);
1234
1235                         if (amdgpu_discovery_validate_ip(ip))
1236                                 goto next_ip;
1237
1238                         num_base_address = ip->num_base_address;
1239
1240                         DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
1241                                   hw_id_names[le16_to_cpu(ip->hw_id)],
1242                                   le16_to_cpu(ip->hw_id),
1243                                   ip->instance_number,
1244                                   ip->major, ip->minor,
1245                                   ip->revision);
1246
1247                         if (le16_to_cpu(ip->hw_id) == VCN_HWID) {
1248                                 /* Bit [5:0]: original revision value
1249                                  * Bit [7:6]: en/decode capability:
1250                                  *     0b00 : VCN function normally
1251                                  *     0b10 : encode is disabled
1252                                  *     0b01 : decode is disabled
1253                                  */
1254                                 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] =
1255                                         ip->revision & 0xc0;
1256                                 ip->revision &= ~0xc0;
1257                                 if (adev->vcn.num_vcn_inst <
1258                                     AMDGPU_MAX_VCN_INSTANCES) {
1259                                         adev->vcn.num_vcn_inst++;
1260                                         adev->vcn.inst_mask |=
1261                                                 (1U << ip->instance_number);
1262                                         adev->jpeg.inst_mask |=
1263                                                 (1U << ip->instance_number);
1264                                 } else {
1265                                         dev_err(adev->dev, "Too many VCN instances: %d vs %d\n",
1266                                                 adev->vcn.num_vcn_inst + 1,
1267                                                 AMDGPU_MAX_VCN_INSTANCES);
1268                                 }
1269                         }
1270                         if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
1271                             le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
1272                             le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
1273                             le16_to_cpu(ip->hw_id) == SDMA3_HWID) {
1274                                 if (adev->sdma.num_instances <
1275                                     AMDGPU_MAX_SDMA_INSTANCES) {
1276                                         adev->sdma.num_instances++;
1277                                         adev->sdma.sdma_mask |=
1278                                                 (1U << ip->instance_number);
1279                                 } else {
1280                                         dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n",
1281                                                 adev->sdma.num_instances + 1,
1282                                                 AMDGPU_MAX_SDMA_INSTANCES);
1283                                 }
1284                         }
1285
1286                         if (le16_to_cpu(ip->hw_id) == UMC_HWID) {
1287                                 adev->gmc.num_umc++;
1288                                 adev->umc.node_inst_num++;
1289                         }
1290
1291                         if (le16_to_cpu(ip->hw_id) == GC_HWID)
1292                                 adev->gfx.xcc_mask |=
1293                                         (1U << ip->instance_number);
1294
1295                         for (k = 0; k < num_base_address; k++) {
1296                                 /*
1297                                  * convert the endianness of base addresses in place,
1298                                  * so that we don't need to convert them when accessing adev->reg_offset.
1299                                  */
1300                                 if (ihdr->base_addr_64_bit)
1301                                         /* Truncate the 64bit base address from ip discovery
1302                                          * and only store lower 32bit ip base in reg_offset[].
1303                                          * Bits > 32 follows ASIC specific format, thus just
1304                                          * discard them and handle it within specific ASIC.
1305                                          * By this way reg_offset[] and related helpers can
1306                                          * stay unchanged.
1307                                          * The base address is in dwords, thus clear the
1308                                          * highest 2 bits to store.
1309                                          */
1310                                         ip->base_address[k] =
1311                                                 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF;
1312                                 else
1313                                         ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
1314                                 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
1315                         }
1316
1317                         for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
1318                                 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) &&
1319                                     hw_id_map[hw_ip] != 0) {
1320                                         DRM_DEBUG("set register base offset for %s\n",
1321                                                         hw_id_names[le16_to_cpu(ip->hw_id)]);
1322                                         adev->reg_offset[hw_ip][ip->instance_number] =
1323                                                 ip->base_address;
1324                                         /* Instance support is somewhat inconsistent.
1325                                          * SDMA is a good example.  Sienna cichlid has 4 total
1326                                          * SDMA instances, each enumerated separately (HWIDs
1327                                          * 42, 43, 68, 69).  Arcturus has 8 total SDMA instances,
1328                                          * but they are enumerated as multiple instances of the
1329                                          * same HWIDs (4x HWID 42, 4x HWID 43).  UMC is another
1330                                          * example.  On most chips there are multiple instances
1331                                          * with the same HWID.
1332                                          */
1333                                         adev->ip_versions[hw_ip][ip->instance_number] =
1334                                                 IP_VERSION(ip->major, ip->minor, ip->revision);
1335                                 }
1336                         }
1337
1338 next_ip:
1339                         if (ihdr->base_addr_64_bit)
1340                                 ip_offset += struct_size(ip, base_address_64, ip->num_base_address);
1341                         else
1342                                 ip_offset += struct_size(ip, base_address, ip->num_base_address);
1343                 }
1344         }
1345
1346         return 0;
1347 }
1348
1349 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
1350 {
1351         int vcn_harvest_count = 0;
1352         int umc_harvest_count = 0;
1353
1354         /*
1355          * Harvest table does not fit Navi1x and legacy GPUs,
1356          * so read harvest bit per IP data structure to set
1357          * harvest configuration.
1358          */
1359         if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0) &&
1360             adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 3)) {
1361                 if ((adev->pdev->device == 0x731E &&
1362                         (adev->pdev->revision == 0xC6 ||
1363                          adev->pdev->revision == 0xC7)) ||
1364                         (adev->pdev->device == 0x7340 &&
1365                          adev->pdev->revision == 0xC9) ||
1366                         (adev->pdev->device == 0x7360 &&
1367                          adev->pdev->revision == 0xC7))
1368                         amdgpu_discovery_read_harvest_bit_per_ip(adev,
1369                                 &vcn_harvest_count);
1370         } else {
1371                 amdgpu_discovery_read_from_harvest_table(adev,
1372                                                          &vcn_harvest_count,
1373                                                          &umc_harvest_count);
1374         }
1375
1376         amdgpu_discovery_harvest_config_quirk(adev);
1377
1378         if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
1379                 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
1380                 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
1381         }
1382
1383         if (umc_harvest_count < adev->gmc.num_umc) {
1384                 adev->gmc.num_umc -= umc_harvest_count;
1385         }
1386 }
1387
1388 union gc_info {
1389         struct gc_info_v1_0 v1;
1390         struct gc_info_v1_1 v1_1;
1391         struct gc_info_v1_2 v1_2;
1392         struct gc_info_v2_0 v2;
1393 };
1394
1395 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
1396 {
1397         struct binary_header *bhdr;
1398         union gc_info *gc_info;
1399         u16 offset;
1400
1401         if (!adev->mman.discovery_bin) {
1402                 DRM_ERROR("ip discovery uninitialized\n");
1403                 return -EINVAL;
1404         }
1405
1406         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1407         offset = le16_to_cpu(bhdr->table_list[GC].offset);
1408
1409         if (!offset)
1410                 return 0;
1411
1412         gc_info = (union gc_info *)(adev->mman.discovery_bin + offset);
1413
1414         switch (le16_to_cpu(gc_info->v1.header.version_major)) {
1415         case 1:
1416                 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
1417                 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
1418                                                       le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa));
1419                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1420                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
1421                 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
1422                 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs);
1423                 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds);
1424                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth);
1425                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth);
1426                 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer);
1427                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size);
1428                 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd);
1429                 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu);
1430                 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size);
1431                 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) /
1432                         le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1433                 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc);
1434                 if (gc_info->v1.header.version_minor >= 1) {
1435                         adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa);
1436                         adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface);
1437                         adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps);
1438                 }
1439                 if (gc_info->v1.header.version_minor >= 2) {
1440                         adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg);
1441                         adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size);
1442                         adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp);
1443                         adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc);
1444                         adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc);
1445                         adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa);
1446                         adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance);
1447                         adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu);
1448                 }
1449                 break;
1450         case 2:
1451                 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se);
1452                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh);
1453                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1454                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se);
1455                 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs);
1456                 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs);
1457                 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds);
1458                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth);
1459                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth);
1460                 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer);
1461                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size);
1462                 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd);
1463                 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu);
1464                 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size);
1465                 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) /
1466                         le32_to_cpu(gc_info->v2.gc_num_sh_per_se);
1467                 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc);
1468                 break;
1469         default:
1470                 dev_err(adev->dev,
1471                         "Unhandled GC info table %d.%d\n",
1472                         le16_to_cpu(gc_info->v1.header.version_major),
1473                         le16_to_cpu(gc_info->v1.header.version_minor));
1474                 return -EINVAL;
1475         }
1476         return 0;
1477 }
1478
1479 union mall_info {
1480         struct mall_info_v1_0 v1;
1481 };
1482
1483 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)
1484 {
1485         struct binary_header *bhdr;
1486         union mall_info *mall_info;
1487         u32 u, mall_size_per_umc, m_s_present, half_use;
1488         u64 mall_size;
1489         u16 offset;
1490
1491         if (!adev->mman.discovery_bin) {
1492                 DRM_ERROR("ip discovery uninitialized\n");
1493                 return -EINVAL;
1494         }
1495
1496         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1497         offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset);
1498
1499         if (!offset)
1500                 return 0;
1501
1502         mall_info = (union mall_info *)(adev->mman.discovery_bin + offset);
1503
1504         switch (le16_to_cpu(mall_info->v1.header.version_major)) {
1505         case 1:
1506                 mall_size = 0;
1507                 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m);
1508                 m_s_present = le32_to_cpu(mall_info->v1.m_s_present);
1509                 half_use = le32_to_cpu(mall_info->v1.m_half_use);
1510                 for (u = 0; u < adev->gmc.num_umc; u++) {
1511                         if (m_s_present & (1 << u))
1512                                 mall_size += mall_size_per_umc * 2;
1513                         else if (half_use & (1 << u))
1514                                 mall_size += mall_size_per_umc / 2;
1515                         else
1516                                 mall_size += mall_size_per_umc;
1517                 }
1518                 adev->gmc.mall_size = mall_size;
1519                 adev->gmc.m_half_use = half_use;
1520                 break;
1521         default:
1522                 dev_err(adev->dev,
1523                         "Unhandled MALL info table %d.%d\n",
1524                         le16_to_cpu(mall_info->v1.header.version_major),
1525                         le16_to_cpu(mall_info->v1.header.version_minor));
1526                 return -EINVAL;
1527         }
1528         return 0;
1529 }
1530
1531 union vcn_info {
1532         struct vcn_info_v1_0 v1;
1533 };
1534
1535 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
1536 {
1537         struct binary_header *bhdr;
1538         union vcn_info *vcn_info;
1539         u16 offset;
1540         int v;
1541
1542         if (!adev->mman.discovery_bin) {
1543                 DRM_ERROR("ip discovery uninitialized\n");
1544                 return -EINVAL;
1545         }
1546
1547         /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
1548          * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES
1549          * but that may change in the future with new GPUs so keep this
1550          * check for defensive purposes.
1551          */
1552         if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) {
1553                 dev_err(adev->dev, "invalid vcn instances\n");
1554                 return -EINVAL;
1555         }
1556
1557         bhdr = (struct binary_header *)adev->mman.discovery_bin;
1558         offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset);
1559
1560         if (!offset)
1561                 return 0;
1562
1563         vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset);
1564
1565         switch (le16_to_cpu(vcn_info->v1.header.version_major)) {
1566         case 1:
1567                 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES
1568                  * so this won't overflow.
1569                  */
1570                 for (v = 0; v < adev->vcn.num_vcn_inst; v++) {
1571                         adev->vcn.vcn_codec_disable_mask[v] =
1572                                 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);
1573                 }
1574                 break;
1575         default:
1576                 dev_err(adev->dev,
1577                         "Unhandled VCN info table %d.%d\n",
1578                         le16_to_cpu(vcn_info->v1.header.version_major),
1579                         le16_to_cpu(vcn_info->v1.header.version_minor));
1580                 return -EINVAL;
1581         }
1582         return 0;
1583 }
1584
1585 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
1586 {
1587         /* what IP to use for this? */
1588         switch (adev->ip_versions[GC_HWIP][0]) {
1589         case IP_VERSION(9, 0, 1):
1590         case IP_VERSION(9, 1, 0):
1591         case IP_VERSION(9, 2, 1):
1592         case IP_VERSION(9, 2, 2):
1593         case IP_VERSION(9, 3, 0):
1594         case IP_VERSION(9, 4, 0):
1595         case IP_VERSION(9, 4, 1):
1596         case IP_VERSION(9, 4, 2):
1597         case IP_VERSION(9, 4, 3):
1598                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
1599                 break;
1600         case IP_VERSION(10, 1, 10):
1601         case IP_VERSION(10, 1, 1):
1602         case IP_VERSION(10, 1, 2):
1603         case IP_VERSION(10, 1, 3):
1604         case IP_VERSION(10, 1, 4):
1605         case IP_VERSION(10, 3, 0):
1606         case IP_VERSION(10, 3, 1):
1607         case IP_VERSION(10, 3, 2):
1608         case IP_VERSION(10, 3, 3):
1609         case IP_VERSION(10, 3, 4):
1610         case IP_VERSION(10, 3, 5):
1611         case IP_VERSION(10, 3, 6):
1612         case IP_VERSION(10, 3, 7):
1613                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
1614                 break;
1615         case IP_VERSION(11, 0, 0):
1616         case IP_VERSION(11, 0, 1):
1617         case IP_VERSION(11, 0, 2):
1618         case IP_VERSION(11, 0, 3):
1619         case IP_VERSION(11, 0, 4):
1620                 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);
1621                 break;
1622         default:
1623                 dev_err(adev->dev,
1624                         "Failed to add common ip block(GC_HWIP:0x%x)\n",
1625                         adev->ip_versions[GC_HWIP][0]);
1626                 return -EINVAL;
1627         }
1628         return 0;
1629 }
1630
1631 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
1632 {
1633         /* use GC or MMHUB IP version */
1634         switch (adev->ip_versions[GC_HWIP][0]) {
1635         case IP_VERSION(9, 0, 1):
1636         case IP_VERSION(9, 1, 0):
1637         case IP_VERSION(9, 2, 1):
1638         case IP_VERSION(9, 2, 2):
1639         case IP_VERSION(9, 3, 0):
1640         case IP_VERSION(9, 4, 0):
1641         case IP_VERSION(9, 4, 1):
1642         case IP_VERSION(9, 4, 2):
1643         case IP_VERSION(9, 4, 3):
1644                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
1645                 break;
1646         case IP_VERSION(10, 1, 10):
1647         case IP_VERSION(10, 1, 1):
1648         case IP_VERSION(10, 1, 2):
1649         case IP_VERSION(10, 1, 3):
1650         case IP_VERSION(10, 1, 4):
1651         case IP_VERSION(10, 3, 0):
1652         case IP_VERSION(10, 3, 1):
1653         case IP_VERSION(10, 3, 2):
1654         case IP_VERSION(10, 3, 3):
1655         case IP_VERSION(10, 3, 4):
1656         case IP_VERSION(10, 3, 5):
1657         case IP_VERSION(10, 3, 6):
1658         case IP_VERSION(10, 3, 7):
1659                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
1660                 break;
1661         case IP_VERSION(11, 0, 0):
1662         case IP_VERSION(11, 0, 1):
1663         case IP_VERSION(11, 0, 2):
1664         case IP_VERSION(11, 0, 3):
1665         case IP_VERSION(11, 0, 4):
1666                 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block);
1667                 break;
1668         default:
1669                 dev_err(adev->dev,
1670                         "Failed to add gmc ip block(GC_HWIP:0x%x)\n",
1671                         adev->ip_versions[GC_HWIP][0]);
1672                 return -EINVAL;
1673         }
1674         return 0;
1675 }
1676
1677 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
1678 {
1679         switch (adev->ip_versions[OSSSYS_HWIP][0]) {
1680         case IP_VERSION(4, 0, 0):
1681         case IP_VERSION(4, 0, 1):
1682         case IP_VERSION(4, 1, 0):
1683         case IP_VERSION(4, 1, 1):
1684         case IP_VERSION(4, 3, 0):
1685                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
1686                 break;
1687         case IP_VERSION(4, 2, 0):
1688         case IP_VERSION(4, 2, 1):
1689         case IP_VERSION(4, 4, 0):
1690         case IP_VERSION(4, 4, 2):
1691                 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
1692                 break;
1693         case IP_VERSION(5, 0, 0):
1694         case IP_VERSION(5, 0, 1):
1695         case IP_VERSION(5, 0, 2):
1696         case IP_VERSION(5, 0, 3):
1697         case IP_VERSION(5, 2, 0):
1698         case IP_VERSION(5, 2, 1):
1699                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
1700                 break;
1701         case IP_VERSION(6, 0, 0):
1702         case IP_VERSION(6, 0, 1):
1703         case IP_VERSION(6, 0, 2):
1704                 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block);
1705                 break;
1706         case IP_VERSION(6, 1, 0):
1707                 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block);
1708                 break;
1709         default:
1710                 dev_err(adev->dev,
1711                         "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n",
1712                         adev->ip_versions[OSSSYS_HWIP][0]);
1713                 return -EINVAL;
1714         }
1715         return 0;
1716 }
1717
1718 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
1719 {
1720         switch (adev->ip_versions[MP0_HWIP][0]) {
1721         case IP_VERSION(9, 0, 0):
1722                 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
1723                 break;
1724         case IP_VERSION(10, 0, 0):
1725         case IP_VERSION(10, 0, 1):
1726                 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
1727                 break;
1728         case IP_VERSION(11, 0, 0):
1729         case IP_VERSION(11, 0, 2):
1730         case IP_VERSION(11, 0, 4):
1731         case IP_VERSION(11, 0, 5):
1732         case IP_VERSION(11, 0, 9):
1733         case IP_VERSION(11, 0, 7):
1734         case IP_VERSION(11, 0, 11):
1735         case IP_VERSION(11, 0, 12):
1736         case IP_VERSION(11, 0, 13):
1737         case IP_VERSION(11, 5, 0):
1738                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
1739                 break;
1740         case IP_VERSION(11, 0, 8):
1741                 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
1742                 break;
1743         case IP_VERSION(11, 0, 3):
1744         case IP_VERSION(12, 0, 1):
1745                 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
1746                 break;
1747         case IP_VERSION(13, 0, 0):
1748         case IP_VERSION(13, 0, 1):
1749         case IP_VERSION(13, 0, 2):
1750         case IP_VERSION(13, 0, 3):
1751         case IP_VERSION(13, 0, 5):
1752         case IP_VERSION(13, 0, 6):
1753         case IP_VERSION(13, 0, 7):
1754         case IP_VERSION(13, 0, 8):
1755         case IP_VERSION(13, 0, 10):
1756         case IP_VERSION(13, 0, 11):
1757         case IP_VERSION(14, 0, 0):
1758                 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
1759                 break;
1760         case IP_VERSION(13, 0, 4):
1761                 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block);
1762                 break;
1763         default:
1764                 dev_err(adev->dev,
1765                         "Failed to add psp ip block(MP0_HWIP:0x%x)\n",
1766                         adev->ip_versions[MP0_HWIP][0]);
1767                 return -EINVAL;
1768         }
1769         return 0;
1770 }
1771
1772 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
1773 {
1774         switch (adev->ip_versions[MP1_HWIP][0]) {
1775         case IP_VERSION(9, 0, 0):
1776         case IP_VERSION(10, 0, 0):
1777         case IP_VERSION(10, 0, 1):
1778         case IP_VERSION(11, 0, 2):
1779                 if (adev->asic_type == CHIP_ARCTURUS)
1780                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1781                 else
1782                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
1783                 break;
1784         case IP_VERSION(11, 0, 0):
1785         case IP_VERSION(11, 0, 5):
1786         case IP_VERSION(11, 0, 9):
1787         case IP_VERSION(11, 0, 7):
1788         case IP_VERSION(11, 0, 8):
1789         case IP_VERSION(11, 0, 11):
1790         case IP_VERSION(11, 0, 12):
1791         case IP_VERSION(11, 0, 13):
1792         case IP_VERSION(11, 5, 0):
1793                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
1794                 break;
1795         case IP_VERSION(12, 0, 0):
1796         case IP_VERSION(12, 0, 1):
1797                 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
1798                 break;
1799         case IP_VERSION(13, 0, 0):
1800         case IP_VERSION(13, 0, 1):
1801         case IP_VERSION(13, 0, 2):
1802         case IP_VERSION(13, 0, 3):
1803         case IP_VERSION(13, 0, 4):
1804         case IP_VERSION(13, 0, 5):
1805         case IP_VERSION(13, 0, 6):
1806         case IP_VERSION(13, 0, 7):
1807         case IP_VERSION(13, 0, 8):
1808         case IP_VERSION(13, 0, 10):
1809         case IP_VERSION(13, 0, 11):
1810                 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
1811                 break;
1812         default:
1813                 dev_err(adev->dev,
1814                         "Failed to add smu ip block(MP1_HWIP:0x%x)\n",
1815                         adev->ip_versions[MP1_HWIP][0]);
1816                 return -EINVAL;
1817         }
1818         return 0;
1819 }
1820
1821 #if defined(CONFIG_DRM_AMD_DC)
1822 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev)
1823 {
1824         amdgpu_device_set_sriov_virtual_display(adev);
1825         amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
1826 }
1827 #endif
1828
1829 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
1830 {
1831         if (adev->enable_virtual_display) {
1832                 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
1833                 return 0;
1834         }
1835
1836         if (!amdgpu_device_has_dc_support(adev))
1837                 return 0;
1838
1839 #if defined(CONFIG_DRM_AMD_DC)
1840         if (adev->ip_versions[DCE_HWIP][0]) {
1841                 switch (adev->ip_versions[DCE_HWIP][0]) {
1842                 case IP_VERSION(1, 0, 0):
1843                 case IP_VERSION(1, 0, 1):
1844                 case IP_VERSION(2, 0, 2):
1845                 case IP_VERSION(2, 0, 0):
1846                 case IP_VERSION(2, 0, 3):
1847                 case IP_VERSION(2, 1, 0):
1848                 case IP_VERSION(3, 0, 0):
1849                 case IP_VERSION(3, 0, 2):
1850                 case IP_VERSION(3, 0, 3):
1851                 case IP_VERSION(3, 0, 1):
1852                 case IP_VERSION(3, 1, 2):
1853                 case IP_VERSION(3, 1, 3):
1854                 case IP_VERSION(3, 1, 4):
1855                 case IP_VERSION(3, 1, 5):
1856                 case IP_VERSION(3, 1, 6):
1857                 case IP_VERSION(3, 2, 0):
1858                 case IP_VERSION(3, 2, 1):
1859                         if (amdgpu_sriov_vf(adev))
1860                                 amdgpu_discovery_set_sriov_display(adev);
1861                         else
1862                                 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1863                         break;
1864                 default:
1865                         dev_err(adev->dev,
1866                                 "Failed to add dm ip block(DCE_HWIP:0x%x)\n",
1867                                 adev->ip_versions[DCE_HWIP][0]);
1868                         return -EINVAL;
1869                 }
1870         } else if (adev->ip_versions[DCI_HWIP][0]) {
1871                 switch (adev->ip_versions[DCI_HWIP][0]) {
1872                 case IP_VERSION(12, 0, 0):
1873                 case IP_VERSION(12, 0, 1):
1874                 case IP_VERSION(12, 1, 0):
1875                         if (amdgpu_sriov_vf(adev))
1876                                 amdgpu_discovery_set_sriov_display(adev);
1877                         else
1878                                 amdgpu_device_ip_block_add(adev, &dm_ip_block);
1879                         break;
1880                 default:
1881                         dev_err(adev->dev,
1882                                 "Failed to add dm ip block(DCI_HWIP:0x%x)\n",
1883                                 adev->ip_versions[DCI_HWIP][0]);
1884                         return -EINVAL;
1885                 }
1886         }
1887 #endif
1888         return 0;
1889 }
1890
1891 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
1892 {
1893         switch (adev->ip_versions[GC_HWIP][0]) {
1894         case IP_VERSION(9, 0, 1):
1895         case IP_VERSION(9, 1, 0):
1896         case IP_VERSION(9, 2, 1):
1897         case IP_VERSION(9, 2, 2):
1898         case IP_VERSION(9, 3, 0):
1899         case IP_VERSION(9, 4, 0):
1900         case IP_VERSION(9, 4, 1):
1901         case IP_VERSION(9, 4, 2):
1902                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
1903                 break;
1904         case IP_VERSION(9, 4, 3):
1905                 if (!amdgpu_exp_hw_support)
1906                         return -EINVAL;
1907                 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block);
1908                 break;
1909         case IP_VERSION(10, 1, 10):
1910         case IP_VERSION(10, 1, 2):
1911         case IP_VERSION(10, 1, 1):
1912         case IP_VERSION(10, 1, 3):
1913         case IP_VERSION(10, 1, 4):
1914         case IP_VERSION(10, 3, 0):
1915         case IP_VERSION(10, 3, 2):
1916         case IP_VERSION(10, 3, 1):
1917         case IP_VERSION(10, 3, 4):
1918         case IP_VERSION(10, 3, 5):
1919         case IP_VERSION(10, 3, 6):
1920         case IP_VERSION(10, 3, 3):
1921         case IP_VERSION(10, 3, 7):
1922                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
1923                 break;
1924         case IP_VERSION(11, 0, 0):
1925         case IP_VERSION(11, 0, 1):
1926         case IP_VERSION(11, 0, 2):
1927         case IP_VERSION(11, 0, 3):
1928         case IP_VERSION(11, 0, 4):
1929                 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block);
1930                 break;
1931         default:
1932                 dev_err(adev->dev,
1933                         "Failed to add gfx ip block(GC_HWIP:0x%x)\n",
1934                         adev->ip_versions[GC_HWIP][0]);
1935                 return -EINVAL;
1936         }
1937         return 0;
1938 }
1939
1940 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
1941 {
1942         switch (adev->ip_versions[SDMA0_HWIP][0]) {
1943         case IP_VERSION(4, 0, 0):
1944         case IP_VERSION(4, 0, 1):
1945         case IP_VERSION(4, 1, 0):
1946         case IP_VERSION(4, 1, 1):
1947         case IP_VERSION(4, 1, 2):
1948         case IP_VERSION(4, 2, 0):
1949         case IP_VERSION(4, 2, 2):
1950         case IP_VERSION(4, 4, 0):
1951                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
1952                 break;
1953         case IP_VERSION(4, 4, 2):
1954                 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block);
1955                 break;
1956         case IP_VERSION(5, 0, 0):
1957         case IP_VERSION(5, 0, 1):
1958         case IP_VERSION(5, 0, 2):
1959         case IP_VERSION(5, 0, 5):
1960                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
1961                 break;
1962         case IP_VERSION(5, 2, 0):
1963         case IP_VERSION(5, 2, 2):
1964         case IP_VERSION(5, 2, 4):
1965         case IP_VERSION(5, 2, 5):
1966         case IP_VERSION(5, 2, 6):
1967         case IP_VERSION(5, 2, 3):
1968         case IP_VERSION(5, 2, 1):
1969         case IP_VERSION(5, 2, 7):
1970                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
1971                 break;
1972         case IP_VERSION(6, 0, 0):
1973         case IP_VERSION(6, 0, 1):
1974         case IP_VERSION(6, 0, 2):
1975         case IP_VERSION(6, 0, 3):
1976         case IP_VERSION(6, 1, 0):
1977                 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block);
1978                 break;
1979         default:
1980                 dev_err(adev->dev,
1981                         "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n",
1982                         adev->ip_versions[SDMA0_HWIP][0]);
1983                 return -EINVAL;
1984         }
1985         return 0;
1986 }
1987
1988 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
1989 {
1990         if (adev->ip_versions[VCE_HWIP][0]) {
1991                 switch (adev->ip_versions[UVD_HWIP][0]) {
1992                 case IP_VERSION(7, 0, 0):
1993                 case IP_VERSION(7, 2, 0):
1994                         /* UVD is not supported on vega20 SR-IOV */
1995                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
1996                                 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
1997                         break;
1998                 default:
1999                         dev_err(adev->dev,
2000                                 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n",
2001                                 adev->ip_versions[UVD_HWIP][0]);
2002                         return -EINVAL;
2003                 }
2004                 switch (adev->ip_versions[VCE_HWIP][0]) {
2005                 case IP_VERSION(4, 0, 0):
2006                 case IP_VERSION(4, 1, 0):
2007                         /* VCE is not supported on vega20 SR-IOV */
2008                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
2009                                 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
2010                         break;
2011                 default:
2012                         dev_err(adev->dev,
2013                                 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n",
2014                                 adev->ip_versions[VCE_HWIP][0]);
2015                         return -EINVAL;
2016                 }
2017         } else {
2018                 switch (adev->ip_versions[UVD_HWIP][0]) {
2019                 case IP_VERSION(1, 0, 0):
2020                 case IP_VERSION(1, 0, 1):
2021                         amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
2022                         break;
2023                 case IP_VERSION(2, 0, 0):
2024                 case IP_VERSION(2, 0, 2):
2025                 case IP_VERSION(2, 2, 0):
2026                         amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
2027                         if (!amdgpu_sriov_vf(adev))
2028                                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
2029                         break;
2030                 case IP_VERSION(2, 0, 3):
2031                         break;
2032                 case IP_VERSION(2, 5, 0):
2033                         amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
2034                         amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
2035                         break;
2036                 case IP_VERSION(2, 6, 0):
2037                         amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
2038                         amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
2039                         break;
2040                 case IP_VERSION(3, 0, 0):
2041                 case IP_VERSION(3, 0, 16):
2042                 case IP_VERSION(3, 1, 1):
2043                 case IP_VERSION(3, 1, 2):
2044                 case IP_VERSION(3, 0, 2):
2045                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
2046                         if (!amdgpu_sriov_vf(adev))
2047                                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
2048                         break;
2049                 case IP_VERSION(3, 0, 33):
2050                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
2051                         break;
2052                 case IP_VERSION(4, 0, 0):
2053                 case IP_VERSION(4, 0, 2):
2054                 case IP_VERSION(4, 0, 4):
2055                         amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block);
2056                         amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
2057                         break;
2058                 case IP_VERSION(4, 0, 3):
2059                         amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block);
2060                         amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block);
2061                         break;
2062                 default:
2063                         dev_err(adev->dev,
2064                                 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n",
2065                                 adev->ip_versions[UVD_HWIP][0]);
2066                         return -EINVAL;
2067                 }
2068         }
2069         return 0;
2070 }
2071
2072 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
2073 {
2074         switch (adev->ip_versions[GC_HWIP][0]) {
2075         case IP_VERSION(10, 1, 10):
2076         case IP_VERSION(10, 1, 1):
2077         case IP_VERSION(10, 1, 2):
2078         case IP_VERSION(10, 1, 3):
2079         case IP_VERSION(10, 1, 4):
2080         case IP_VERSION(10, 3, 0):
2081         case IP_VERSION(10, 3, 1):
2082         case IP_VERSION(10, 3, 2):
2083         case IP_VERSION(10, 3, 3):
2084         case IP_VERSION(10, 3, 4):
2085         case IP_VERSION(10, 3, 5):
2086         case IP_VERSION(10, 3, 6):
2087                 if (amdgpu_mes) {
2088                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
2089                         adev->enable_mes = true;
2090                         if (amdgpu_mes_kiq)
2091                                 adev->enable_mes_kiq = true;
2092                 }
2093                 break;
2094         case IP_VERSION(11, 0, 0):
2095         case IP_VERSION(11, 0, 1):
2096         case IP_VERSION(11, 0, 2):
2097         case IP_VERSION(11, 0, 3):
2098         case IP_VERSION(11, 0, 4):
2099                 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block);
2100                 adev->enable_mes = true;
2101                 adev->enable_mes_kiq = true;
2102                 break;
2103         default:
2104                 break;
2105         }
2106         return 0;
2107 }
2108
2109 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev)
2110 {
2111         switch (adev->ip_versions[GC_HWIP][0]) {
2112         case IP_VERSION(9, 4, 3):
2113                 aqua_vanjaram_init_soc_config(adev);
2114                 break;
2115         default:
2116                 break;
2117         }
2118 }
2119
2120 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
2121 {
2122         int r;
2123
2124         switch (adev->asic_type) {
2125         case CHIP_VEGA10:
2126                 vega10_reg_base_init(adev);
2127                 adev->sdma.num_instances = 2;
2128                 adev->gmc.num_umc = 4;
2129                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
2130                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
2131                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
2132                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
2133                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
2134                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0);
2135                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
2136                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
2137                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
2138                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
2139                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
2140                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
2141                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
2142                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
2143                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
2144                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
2145                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
2146                 break;
2147         case CHIP_VEGA12:
2148                 vega10_reg_base_init(adev);
2149                 adev->sdma.num_instances = 2;
2150                 adev->gmc.num_umc = 4;
2151                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
2152                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
2153                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
2154                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
2155                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
2156                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1);
2157                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
2158                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
2159                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
2160                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
2161                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
2162                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
2163                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
2164                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
2165                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
2166                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
2167                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
2168                 break;
2169         case CHIP_RAVEN:
2170                 vega10_reg_base_init(adev);
2171                 adev->sdma.num_instances = 1;
2172                 adev->vcn.num_vcn_inst = 1;
2173                 adev->gmc.num_umc = 2;
2174                 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
2175                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
2176                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
2177                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
2178                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
2179                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
2180                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
2181                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
2182                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
2183                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
2184                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
2185                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
2186                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
2187                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
2188                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
2189                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
2190                 } else {
2191                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
2192                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
2193                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
2194                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
2195                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
2196                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
2197                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
2198                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
2199                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
2200                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
2201                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
2202                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
2203                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
2204                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
2205                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
2206                 }
2207                 break;
2208         case CHIP_VEGA20:
2209                 vega20_reg_base_init(adev);
2210                 adev->sdma.num_instances = 2;
2211                 adev->gmc.num_umc = 8;
2212                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
2213                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
2214                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
2215                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
2216                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
2217                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0);
2218                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
2219                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
2220                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
2221                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
2222                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
2223                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
2224                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
2225                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
2226                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
2227                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0);
2228                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
2229                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
2230                 break;
2231         case CHIP_ARCTURUS:
2232                 arct_reg_base_init(adev);
2233                 adev->sdma.num_instances = 8;
2234                 adev->vcn.num_vcn_inst = 2;
2235                 adev->gmc.num_umc = 8;
2236                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
2237                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
2238                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
2239                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
2240                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
2241                 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2);
2242                 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2);
2243                 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2);
2244                 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2);
2245                 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2);
2246                 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2);
2247                 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2);
2248                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
2249                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
2250                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
2251                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
2252                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
2253                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
2254                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
2255                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
2256                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
2257                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0);
2258                 break;
2259         case CHIP_ALDEBARAN:
2260                 aldebaran_reg_base_init(adev);
2261                 adev->sdma.num_instances = 5;
2262                 adev->vcn.num_vcn_inst = 2;
2263                 adev->gmc.num_umc = 4;
2264                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
2265                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
2266                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
2267                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
2268                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
2269                 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0);
2270                 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0);
2271                 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0);
2272                 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0);
2273                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
2274                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
2275                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
2276                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
2277                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
2278                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
2279                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
2280                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
2281                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
2282                 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0);
2283                 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
2284                 break;
2285         default:
2286                 r = amdgpu_discovery_reg_base_init(adev);
2287                 if (r)
2288                         return -EINVAL;
2289
2290                 amdgpu_discovery_harvest_ip(adev);
2291                 amdgpu_discovery_get_gfx_info(adev);
2292                 amdgpu_discovery_get_mall_info(adev);
2293                 amdgpu_discovery_get_vcn_info(adev);
2294                 break;
2295         }
2296
2297         amdgpu_discovery_init_soc_config(adev);
2298         amdgpu_discovery_sysfs_init(adev);
2299
2300         switch (adev->ip_versions[GC_HWIP][0]) {
2301         case IP_VERSION(9, 0, 1):
2302         case IP_VERSION(9, 2, 1):
2303         case IP_VERSION(9, 4, 0):
2304         case IP_VERSION(9, 4, 1):
2305         case IP_VERSION(9, 4, 2):
2306         case IP_VERSION(9, 4, 3):
2307                 adev->family = AMDGPU_FAMILY_AI;
2308                 break;
2309         case IP_VERSION(9, 1, 0):
2310         case IP_VERSION(9, 2, 2):
2311         case IP_VERSION(9, 3, 0):
2312                 adev->family = AMDGPU_FAMILY_RV;
2313                 break;
2314         case IP_VERSION(10, 1, 10):
2315         case IP_VERSION(10, 1, 1):
2316         case IP_VERSION(10, 1, 2):
2317         case IP_VERSION(10, 1, 3):
2318         case IP_VERSION(10, 1, 4):
2319         case IP_VERSION(10, 3, 0):
2320         case IP_VERSION(10, 3, 2):
2321         case IP_VERSION(10, 3, 4):
2322         case IP_VERSION(10, 3, 5):
2323                 adev->family = AMDGPU_FAMILY_NV;
2324                 break;
2325         case IP_VERSION(10, 3, 1):
2326                 adev->family = AMDGPU_FAMILY_VGH;
2327                 adev->apu_flags |= AMD_APU_IS_VANGOGH;
2328                 break;
2329         case IP_VERSION(10, 3, 3):
2330                 adev->family = AMDGPU_FAMILY_YC;
2331                 break;
2332         case IP_VERSION(10, 3, 6):
2333                 adev->family = AMDGPU_FAMILY_GC_10_3_6;
2334                 break;
2335         case IP_VERSION(10, 3, 7):
2336                 adev->family = AMDGPU_FAMILY_GC_10_3_7;
2337                 break;
2338         case IP_VERSION(11, 0, 0):
2339         case IP_VERSION(11, 0, 2):
2340         case IP_VERSION(11, 0, 3):
2341                 adev->family = AMDGPU_FAMILY_GC_11_0_0;
2342                 break;
2343         case IP_VERSION(11, 0, 1):
2344         case IP_VERSION(11, 0, 4):
2345                 adev->family = AMDGPU_FAMILY_GC_11_0_1;
2346                 break;
2347         default:
2348                 return -EINVAL;
2349         }
2350
2351         switch (adev->ip_versions[GC_HWIP][0]) {
2352         case IP_VERSION(9, 1, 0):
2353         case IP_VERSION(9, 2, 2):
2354         case IP_VERSION(9, 3, 0):
2355         case IP_VERSION(10, 1, 3):
2356         case IP_VERSION(10, 1, 4):
2357         case IP_VERSION(10, 3, 1):
2358         case IP_VERSION(10, 3, 3):
2359         case IP_VERSION(10, 3, 6):
2360         case IP_VERSION(10, 3, 7):
2361         case IP_VERSION(11, 0, 1):
2362         case IP_VERSION(11, 0, 4):
2363                 adev->flags |= AMD_IS_APU;
2364                 break;
2365         default:
2366                 break;
2367         }
2368
2369         if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
2370                 adev->gmc.xgmi.supported = true;
2371
2372         /* set NBIO version */
2373         switch (adev->ip_versions[NBIO_HWIP][0]) {
2374         case IP_VERSION(6, 1, 0):
2375         case IP_VERSION(6, 2, 0):
2376                 adev->nbio.funcs = &nbio_v6_1_funcs;
2377                 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
2378                 break;
2379         case IP_VERSION(7, 0, 0):
2380         case IP_VERSION(7, 0, 1):
2381         case IP_VERSION(2, 5, 0):
2382                 adev->nbio.funcs = &nbio_v7_0_funcs;
2383                 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
2384                 break;
2385         case IP_VERSION(7, 4, 0):
2386         case IP_VERSION(7, 4, 1):
2387         case IP_VERSION(7, 4, 4):
2388                 adev->nbio.funcs = &nbio_v7_4_funcs;
2389                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
2390                 break;
2391         case IP_VERSION(7, 9, 0):
2392                 adev->nbio.funcs = &nbio_v7_9_funcs;
2393                 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg;
2394                 break;
2395         case IP_VERSION(7, 2, 0):
2396         case IP_VERSION(7, 2, 1):
2397         case IP_VERSION(7, 3, 0):
2398         case IP_VERSION(7, 5, 0):
2399         case IP_VERSION(7, 5, 1):
2400                 adev->nbio.funcs = &nbio_v7_2_funcs;
2401                 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
2402                 break;
2403         case IP_VERSION(2, 1, 1):
2404         case IP_VERSION(2, 3, 0):
2405         case IP_VERSION(2, 3, 1):
2406         case IP_VERSION(2, 3, 2):
2407         case IP_VERSION(3, 3, 0):
2408         case IP_VERSION(3, 3, 1):
2409         case IP_VERSION(3, 3, 2):
2410         case IP_VERSION(3, 3, 3):
2411                 adev->nbio.funcs = &nbio_v2_3_funcs;
2412                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
2413                 break;
2414         case IP_VERSION(4, 3, 0):
2415         case IP_VERSION(4, 3, 1):
2416                 if (amdgpu_sriov_vf(adev))
2417                         adev->nbio.funcs = &nbio_v4_3_sriov_funcs;
2418                 else
2419                         adev->nbio.funcs = &nbio_v4_3_funcs;
2420                 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg;
2421                 break;
2422         case IP_VERSION(7, 7, 0):
2423         case IP_VERSION(7, 7, 1):
2424                 adev->nbio.funcs = &nbio_v7_7_funcs;
2425                 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg;
2426                 break;
2427         default:
2428                 break;
2429         }
2430
2431         switch (adev->ip_versions[HDP_HWIP][0]) {
2432         case IP_VERSION(4, 0, 0):
2433         case IP_VERSION(4, 0, 1):
2434         case IP_VERSION(4, 1, 0):
2435         case IP_VERSION(4, 1, 1):
2436         case IP_VERSION(4, 1, 2):
2437         case IP_VERSION(4, 2, 0):
2438         case IP_VERSION(4, 2, 1):
2439         case IP_VERSION(4, 4, 0):
2440         case IP_VERSION(4, 4, 2):
2441                 adev->hdp.funcs = &hdp_v4_0_funcs;
2442                 break;
2443         case IP_VERSION(5, 0, 0):
2444         case IP_VERSION(5, 0, 1):
2445         case IP_VERSION(5, 0, 2):
2446         case IP_VERSION(5, 0, 3):
2447         case IP_VERSION(5, 0, 4):
2448         case IP_VERSION(5, 2, 0):
2449                 adev->hdp.funcs = &hdp_v5_0_funcs;
2450                 break;
2451         case IP_VERSION(5, 2, 1):
2452                 adev->hdp.funcs = &hdp_v5_2_funcs;
2453                 break;
2454         case IP_VERSION(6, 0, 0):
2455         case IP_VERSION(6, 0, 1):
2456         case IP_VERSION(6, 1, 0):
2457                 adev->hdp.funcs = &hdp_v6_0_funcs;
2458                 break;
2459         default:
2460                 break;
2461         }
2462
2463         switch (adev->ip_versions[DF_HWIP][0]) {
2464         case IP_VERSION(3, 6, 0):
2465         case IP_VERSION(3, 6, 1):
2466         case IP_VERSION(3, 6, 2):
2467                 adev->df.funcs = &df_v3_6_funcs;
2468                 break;
2469         case IP_VERSION(2, 1, 0):
2470         case IP_VERSION(2, 1, 1):
2471         case IP_VERSION(2, 5, 0):
2472         case IP_VERSION(3, 5, 1):
2473         case IP_VERSION(3, 5, 2):
2474                 adev->df.funcs = &df_v1_7_funcs;
2475                 break;
2476         case IP_VERSION(4, 3, 0):
2477                 adev->df.funcs = &df_v4_3_funcs;
2478                 break;
2479         default:
2480                 break;
2481         }
2482
2483         switch (adev->ip_versions[SMUIO_HWIP][0]) {
2484         case IP_VERSION(9, 0, 0):
2485         case IP_VERSION(9, 0, 1):
2486         case IP_VERSION(10, 0, 0):
2487         case IP_VERSION(10, 0, 1):
2488         case IP_VERSION(10, 0, 2):
2489                 adev->smuio.funcs = &smuio_v9_0_funcs;
2490                 break;
2491         case IP_VERSION(11, 0, 0):
2492         case IP_VERSION(11, 0, 2):
2493         case IP_VERSION(11, 0, 3):
2494         case IP_VERSION(11, 0, 4):
2495         case IP_VERSION(11, 0, 7):
2496         case IP_VERSION(11, 0, 8):
2497                 adev->smuio.funcs = &smuio_v11_0_funcs;
2498                 break;
2499         case IP_VERSION(11, 0, 6):
2500         case IP_VERSION(11, 0, 10):
2501         case IP_VERSION(11, 0, 11):
2502         case IP_VERSION(11, 5, 0):
2503         case IP_VERSION(13, 0, 1):
2504         case IP_VERSION(13, 0, 9):
2505         case IP_VERSION(13, 0, 10):
2506                 adev->smuio.funcs = &smuio_v11_0_6_funcs;
2507                 break;
2508         case IP_VERSION(13, 0, 2):
2509                 adev->smuio.funcs = &smuio_v13_0_funcs;
2510                 break;
2511         case IP_VERSION(13, 0, 3):
2512                 adev->smuio.funcs = &smuio_v13_0_3_funcs;
2513                 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) {
2514                         adev->flags |= AMD_IS_APU;
2515                 }
2516                 break;
2517         case IP_VERSION(13, 0, 6):
2518         case IP_VERSION(13, 0, 8):
2519         case IP_VERSION(14, 0, 0):
2520                 adev->smuio.funcs = &smuio_v13_0_6_funcs;
2521                 break;
2522         default:
2523                 break;
2524         }
2525
2526         switch (adev->ip_versions[LSDMA_HWIP][0]) {
2527         case IP_VERSION(6, 0, 0):
2528         case IP_VERSION(6, 0, 1):
2529         case IP_VERSION(6, 0, 2):
2530         case IP_VERSION(6, 0, 3):
2531                 adev->lsdma.funcs = &lsdma_v6_0_funcs;
2532                 break;
2533         default:
2534                 break;
2535         }
2536
2537         r = amdgpu_discovery_set_common_ip_blocks(adev);
2538         if (r)
2539                 return r;
2540
2541         r = amdgpu_discovery_set_gmc_ip_blocks(adev);
2542         if (r)
2543                 return r;
2544
2545         /* For SR-IOV, PSP needs to be initialized before IH */
2546         if (amdgpu_sriov_vf(adev)) {
2547                 r = amdgpu_discovery_set_psp_ip_blocks(adev);
2548                 if (r)
2549                         return r;
2550                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
2551                 if (r)
2552                         return r;
2553         } else {
2554                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
2555                 if (r)
2556                         return r;
2557
2558                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
2559                         r = amdgpu_discovery_set_psp_ip_blocks(adev);
2560                         if (r)
2561                                 return r;
2562                 }
2563         }
2564
2565         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
2566                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
2567                 if (r)
2568                         return r;
2569         }
2570
2571         r = amdgpu_discovery_set_display_ip_blocks(adev);
2572         if (r)
2573                 return r;
2574
2575         r = amdgpu_discovery_set_gc_ip_blocks(adev);
2576         if (r)
2577                 return r;
2578
2579         r = amdgpu_discovery_set_sdma_ip_blocks(adev);
2580         if (r)
2581                 return r;
2582
2583         if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
2584              !amdgpu_sriov_vf(adev)) ||
2585             (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) {
2586                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
2587                 if (r)
2588                         return r;
2589         }
2590
2591         r = amdgpu_discovery_set_mm_ip_blocks(adev);
2592         if (r)
2593                 return r;
2594
2595         r = amdgpu_discovery_set_mes_ip_blocks(adev);
2596         if (r)
2597                 return r;
2598
2599         return 0;
2600 }
2601