2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_ttm.h"
55 #include "amdgpu_gds.h"
56 #include "amd_powerplay.h"
57 #include "amdgpu_acp.h"
59 #include "gpu_scheduler.h"
64 extern int amdgpu_modeset;
65 extern int amdgpu_vram_limit;
66 extern int amdgpu_gart_size;
67 extern int amdgpu_moverate;
68 extern int amdgpu_benchmarking;
69 extern int amdgpu_testing;
70 extern int amdgpu_audio;
71 extern int amdgpu_disp_priority;
72 extern int amdgpu_hw_i2c;
73 extern int amdgpu_pcie_gen2;
74 extern int amdgpu_msi;
75 extern int amdgpu_lockup_timeout;
76 extern int amdgpu_dpm;
77 extern int amdgpu_smc_load_fw;
78 extern int amdgpu_aspm;
79 extern int amdgpu_runtime_pm;
80 extern unsigned amdgpu_ip_block_mask;
81 extern int amdgpu_bapm;
82 extern int amdgpu_deep_color;
83 extern int amdgpu_vm_size;
84 extern int amdgpu_vm_block_size;
85 extern int amdgpu_vm_fault_stop;
86 extern int amdgpu_vm_debug;
87 extern int amdgpu_sched_jobs;
88 extern int amdgpu_sched_hw_submission;
89 extern int amdgpu_powerplay;
90 extern int amdgpu_powercontainment;
91 extern unsigned amdgpu_pcie_gen_cap;
92 extern unsigned amdgpu_pcie_lane_cap;
93 extern unsigned amdgpu_cg_mask;
94 extern unsigned amdgpu_pg_mask;
95 extern char *amdgpu_disable_cu;
96 extern int amdgpu_sclk_deep_sleep_en;
97 extern char *amdgpu_virtual_display;
99 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
100 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
101 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
102 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
103 #define AMDGPU_IB_POOL_SIZE 16
104 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
105 #define AMDGPUFB_CONN_LIMIT 4
106 #define AMDGPU_BIOS_NUM_SCRATCH 8
108 /* max number of rings */
109 #define AMDGPU_MAX_RINGS 16
110 #define AMDGPU_MAX_GFX_RINGS 1
111 #define AMDGPU_MAX_COMPUTE_RINGS 8
112 #define AMDGPU_MAX_VCE_RINGS 3
114 /* max number of IP instances */
115 #define AMDGPU_MAX_SDMA_INSTANCES 2
117 /* hardcode that limit for now */
118 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
120 /* hard reset data */
121 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
124 #define AMDGPU_RESET_GFX (1 << 0)
125 #define AMDGPU_RESET_COMPUTE (1 << 1)
126 #define AMDGPU_RESET_DMA (1 << 2)
127 #define AMDGPU_RESET_CP (1 << 3)
128 #define AMDGPU_RESET_GRBM (1 << 4)
129 #define AMDGPU_RESET_DMA1 (1 << 5)
130 #define AMDGPU_RESET_RLC (1 << 6)
131 #define AMDGPU_RESET_SEM (1 << 7)
132 #define AMDGPU_RESET_IH (1 << 8)
133 #define AMDGPU_RESET_VMC (1 << 9)
134 #define AMDGPU_RESET_MC (1 << 10)
135 #define AMDGPU_RESET_DISPLAY (1 << 11)
136 #define AMDGPU_RESET_UVD (1 << 12)
137 #define AMDGPU_RESET_VCE (1 << 13)
138 #define AMDGPU_RESET_VCE1 (1 << 14)
140 /* GFX current status */
141 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
142 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
143 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
144 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
145 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
147 /* max cursor sizes (in pixels) */
148 #define CIK_CURSOR_WIDTH 128
149 #define CIK_CURSOR_HEIGHT 128
151 struct amdgpu_device;
155 struct amdgpu_cs_parser;
157 struct amdgpu_irq_src;
161 AMDGPU_CP_IRQ_GFX_EOP = 0,
162 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
163 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
164 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
165 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
166 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
167 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
168 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
169 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
174 enum amdgpu_sdma_irq {
175 AMDGPU_SDMA_IRQ_TRAP0 = 0,
176 AMDGPU_SDMA_IRQ_TRAP1,
181 enum amdgpu_thermal_irq {
182 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
183 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
185 AMDGPU_THERMAL_IRQ_LAST
188 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
189 enum amd_ip_block_type block_type,
190 enum amd_clockgating_state state);
191 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
192 enum amd_ip_block_type block_type,
193 enum amd_powergating_state state);
194 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
195 enum amd_ip_block_type block_type);
196 bool amdgpu_is_idle(struct amdgpu_device *adev,
197 enum amd_ip_block_type block_type);
199 struct amdgpu_ip_block_version {
200 enum amd_ip_block_type type;
204 const struct amd_ip_funcs *funcs;
207 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
208 enum amd_ip_block_type type,
209 u32 major, u32 minor);
211 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
212 struct amdgpu_device *adev,
213 enum amd_ip_block_type type);
215 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
216 struct amdgpu_buffer_funcs {
217 /* maximum bytes in a single operation */
218 uint32_t copy_max_bytes;
220 /* number of dw to reserve per operation */
221 unsigned copy_num_dw;
223 /* used for buffer migration */
224 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
225 /* src addr in bytes */
227 /* dst addr in bytes */
229 /* number of byte to transfer */
230 uint32_t byte_count);
232 /* maximum bytes in a single operation */
233 uint32_t fill_max_bytes;
235 /* number of dw to reserve per operation */
236 unsigned fill_num_dw;
238 /* used for buffer clearing */
239 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
240 /* value to write to memory */
242 /* dst addr in bytes */
244 /* number of byte to fill */
245 uint32_t byte_count);
248 /* provided by hw blocks that can write ptes, e.g., sdma */
249 struct amdgpu_vm_pte_funcs {
250 /* copy pte entries from GART */
251 void (*copy_pte)(struct amdgpu_ib *ib,
252 uint64_t pe, uint64_t src,
254 /* write pte one entry at a time with addr mapping */
255 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
256 uint64_t value, unsigned count,
258 /* for linear pte/pde updates without addr mapping */
259 void (*set_pte_pde)(struct amdgpu_ib *ib,
261 uint64_t addr, unsigned count,
262 uint32_t incr, uint32_t flags);
265 /* provided by the gmc block */
266 struct amdgpu_gart_funcs {
267 /* flush the vm tlb via mmio */
268 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
270 /* write pte/pde updates using the cpu */
271 int (*set_pte_pde)(struct amdgpu_device *adev,
272 void *cpu_pt_addr, /* cpu addr of page table */
273 uint32_t gpu_page_idx, /* pte/pde to update */
274 uint64_t addr, /* addr to write into pte/pde */
275 uint32_t flags); /* access flags */
278 /* provided by the ih block */
279 struct amdgpu_ih_funcs {
280 /* ring read/write ptr handling, called from interrupt context */
281 u32 (*get_wptr)(struct amdgpu_device *adev);
282 void (*decode_iv)(struct amdgpu_device *adev,
283 struct amdgpu_iv_entry *entry);
284 void (*set_rptr)(struct amdgpu_device *adev);
287 /* provided by hw blocks that expose a ring buffer for commands */
288 struct amdgpu_ring_funcs {
289 /* ring read/write ptr handling */
290 u32 (*get_rptr)(struct amdgpu_ring *ring);
291 u32 (*get_wptr)(struct amdgpu_ring *ring);
292 void (*set_wptr)(struct amdgpu_ring *ring);
293 /* validating and patching of IBs */
294 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
295 /* command emit functions */
296 void (*emit_ib)(struct amdgpu_ring *ring,
297 struct amdgpu_ib *ib,
298 unsigned vm_id, bool ctx_switch);
299 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
300 uint64_t seq, unsigned flags);
301 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
302 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
304 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
305 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
306 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
307 uint32_t gds_base, uint32_t gds_size,
308 uint32_t gws_base, uint32_t gws_size,
309 uint32_t oa_base, uint32_t oa_size);
310 /* testing functions */
311 int (*test_ring)(struct amdgpu_ring *ring);
312 int (*test_ib)(struct amdgpu_ring *ring, long timeout);
313 /* insert NOP packets */
314 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
315 /* pad the indirect buffer to the necessary number of dw */
316 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
317 unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
318 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
319 /* note usage for clock and power gating */
320 void (*begin_use)(struct amdgpu_ring *ring);
321 void (*end_use)(struct amdgpu_ring *ring);
322 void (*emit_switch_buffer) (struct amdgpu_ring *ring);
328 bool amdgpu_get_bios(struct amdgpu_device *adev);
329 bool amdgpu_read_bios(struct amdgpu_device *adev);
334 struct amdgpu_dummy_page {
338 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
339 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
346 #define AMDGPU_MAX_PPLL 3
348 struct amdgpu_clock {
349 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
350 struct amdgpu_pll spll;
351 struct amdgpu_pll mpll;
353 uint32_t default_mclk;
354 uint32_t default_sclk;
355 uint32_t default_dispclk;
356 uint32_t current_dispclk;
358 uint32_t max_pixel_clock;
364 struct amdgpu_fence_driver {
366 volatile uint32_t *cpu_addr;
367 /* sync_seq is protected by ring emission lock */
371 struct amdgpu_irq_src *irq_src;
373 struct timer_list fallback_timer;
374 unsigned num_fences_mask;
376 struct fence **fences;
379 /* some special values for the owner field */
380 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
381 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
383 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
384 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
386 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
387 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
388 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
390 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
391 unsigned num_hw_submission);
392 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
393 struct amdgpu_irq_src *irq_src,
395 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
396 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
397 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence);
398 void amdgpu_fence_process(struct amdgpu_ring *ring);
399 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
400 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
406 struct amdgpu_bo_list_entry {
407 struct amdgpu_bo *robj;
408 struct ttm_validate_buffer tv;
409 struct amdgpu_bo_va *bo_va;
411 struct page **user_pages;
412 int user_invalidated;
415 struct amdgpu_bo_va_mapping {
416 struct list_head list;
417 struct interval_tree_node it;
422 /* bo virtual addresses in a specific vm */
423 struct amdgpu_bo_va {
424 /* protected by bo being reserved */
425 struct list_head bo_list;
426 struct fence *last_pt_update;
429 /* protected by vm mutex and spinlock */
430 struct list_head vm_status;
432 /* mappings for this bo_va */
433 struct list_head invalids;
434 struct list_head valids;
436 /* constant after initialization */
437 struct amdgpu_vm *vm;
438 struct amdgpu_bo *bo;
441 #define AMDGPU_GEM_DOMAIN_MAX 0x3
444 /* Protected by gem.mutex */
445 struct list_head list;
446 /* Protected by tbo.reserved */
447 u32 prefered_domains;
449 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
450 struct ttm_placement placement;
451 struct ttm_buffer_object tbo;
452 struct ttm_bo_kmap_obj kmap;
460 /* list of all virtual address to which this bo
464 /* Constant after initialization */
465 struct amdgpu_device *adev;
466 struct drm_gem_object gem_base;
467 struct amdgpu_bo *parent;
468 struct amdgpu_bo *shadow;
470 struct ttm_bo_kmap_obj dma_buf_vmap;
471 struct amdgpu_mn *mn;
472 struct list_head mn_list;
473 struct list_head shadow_list;
475 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
477 void amdgpu_gem_object_free(struct drm_gem_object *obj);
478 int amdgpu_gem_object_open(struct drm_gem_object *obj,
479 struct drm_file *file_priv);
480 void amdgpu_gem_object_close(struct drm_gem_object *obj,
481 struct drm_file *file_priv);
482 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
483 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
484 struct drm_gem_object *
485 amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
486 struct dma_buf_attachment *attach,
487 struct sg_table *sg);
488 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
489 struct drm_gem_object *gobj,
491 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
492 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
493 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
494 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
495 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
496 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
498 /* sub-allocation manager, it has to be protected by another lock.
499 * By conception this is an helper for other part of the driver
500 * like the indirect buffer or semaphore, which both have their
503 * Principe is simple, we keep a list of sub allocation in offset
504 * order (first entry has offset == 0, last entry has the highest
507 * When allocating new object we first check if there is room at
508 * the end total_size - (last_object_offset + last_object_size) >=
509 * alloc_size. If so we allocate new object there.
511 * When there is not enough room at the end, we start waiting for
512 * each sub object until we reach object_offset+object_size >=
513 * alloc_size, this object then become the sub object we return.
515 * Alignment can't be bigger than page size.
517 * Hole are not considered for allocation to keep things simple.
518 * Assumption is that there won't be hole (all object on same
522 #define AMDGPU_SA_NUM_FENCE_LISTS 32
524 struct amdgpu_sa_manager {
525 wait_queue_head_t wq;
526 struct amdgpu_bo *bo;
527 struct list_head *hole;
528 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
529 struct list_head olist;
537 /* sub-allocation buffer */
538 struct amdgpu_sa_bo {
539 struct list_head olist;
540 struct list_head flist;
541 struct amdgpu_sa_manager *manager;
550 void amdgpu_gem_force_release(struct amdgpu_device *adev);
551 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
552 int alignment, u32 initial_domain,
553 u64 flags, bool kernel,
554 struct drm_gem_object **obj);
556 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
557 struct drm_device *dev,
558 struct drm_mode_create_dumb *args);
559 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
560 struct drm_device *dev,
561 uint32_t handle, uint64_t *offset_p);
566 DECLARE_HASHTABLE(fences, 4);
567 struct fence *last_vm_update;
570 void amdgpu_sync_create(struct amdgpu_sync *sync);
571 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
573 int amdgpu_sync_resv(struct amdgpu_device *adev,
574 struct amdgpu_sync *sync,
575 struct reservation_object *resv,
577 struct fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
578 struct amdgpu_ring *ring);
579 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
580 void amdgpu_sync_free(struct amdgpu_sync *sync);
581 int amdgpu_sync_init(void);
582 void amdgpu_sync_fini(void);
583 int amdgpu_fence_slab_init(void);
584 void amdgpu_fence_slab_fini(void);
587 * GART structures, functions & helpers
591 #define AMDGPU_GPU_PAGE_SIZE 4096
592 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
593 #define AMDGPU_GPU_PAGE_SHIFT 12
594 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
597 dma_addr_t table_addr;
598 struct amdgpu_bo *robj;
600 unsigned num_gpu_pages;
601 unsigned num_cpu_pages;
603 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
607 const struct amdgpu_gart_funcs *gart_funcs;
610 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
611 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
612 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
613 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
614 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
615 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
616 int amdgpu_gart_init(struct amdgpu_device *adev);
617 void amdgpu_gart_fini(struct amdgpu_device *adev);
618 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
620 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
621 int pages, struct page **pagelist,
622 dma_addr_t *dma_addr, uint32_t flags);
623 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
626 * GPU MC structures, functions & helpers
629 resource_size_t aper_size;
630 resource_size_t aper_base;
631 resource_size_t agp_base;
632 /* for some chips with <= 32MB we need to lie
633 * about vram size near mc fb location */
635 u64 visible_vram_size;
646 const struct firmware *fw; /* MC firmware */
648 struct amdgpu_irq_src vm_fault;
650 uint32_t srbm_soft_reset;
651 struct amdgpu_mode_mc_save save;
655 * GPU doorbell structures, functions & helpers
657 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
659 AMDGPU_DOORBELL_KIQ = 0x000,
660 AMDGPU_DOORBELL_HIQ = 0x001,
661 AMDGPU_DOORBELL_DIQ = 0x002,
662 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
663 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
664 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
665 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
666 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
667 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
668 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
669 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
670 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
671 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
672 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
673 AMDGPU_DOORBELL_IH = 0x1E8,
674 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
675 AMDGPU_DOORBELL_INVALID = 0xFFFF
676 } AMDGPU_DOORBELL_ASSIGNMENT;
678 struct amdgpu_doorbell {
680 resource_size_t base;
681 resource_size_t size;
683 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
686 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
687 phys_addr_t *aperture_base,
688 size_t *aperture_size,
689 size_t *start_offset);
695 struct amdgpu_flip_work {
696 struct delayed_work flip_work;
697 struct work_struct unpin_work;
698 struct amdgpu_device *adev;
702 struct drm_pending_vblank_event *event;
703 struct amdgpu_bo *old_rbo;
705 unsigned shared_count;
706 struct fence **shared;
717 struct amdgpu_sa_bo *sa_bo;
724 enum amdgpu_ring_type {
725 AMDGPU_RING_TYPE_GFX,
726 AMDGPU_RING_TYPE_COMPUTE,
727 AMDGPU_RING_TYPE_SDMA,
728 AMDGPU_RING_TYPE_UVD,
732 extern const struct amd_sched_backend_ops amdgpu_sched_ops;
734 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
735 struct amdgpu_job **job, struct amdgpu_vm *vm);
736 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
737 struct amdgpu_job **job);
739 void amdgpu_job_free_resources(struct amdgpu_job *job);
740 void amdgpu_job_free(struct amdgpu_job *job);
741 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
742 struct amd_sched_entity *entity, void *owner,
746 struct amdgpu_device *adev;
747 const struct amdgpu_ring_funcs *funcs;
748 struct amdgpu_fence_driver fence_drv;
749 struct amd_gpu_scheduler sched;
751 struct amdgpu_bo *ring_obj;
752 volatile uint32_t *ring;
768 struct amdgpu_bo *mqd_obj;
773 uint64_t current_ctx;
774 enum amdgpu_ring_type type;
776 unsigned cond_exe_offs;
777 u64 cond_exe_gpu_addr;
778 volatile u32 *cond_exe_cpu_addr;
779 #if defined(CONFIG_DEBUG_FS)
788 /* maximum number of VMIDs */
789 #define AMDGPU_NUM_VM 16
791 /* Maximum number of PTEs the hardware can write with one command */
792 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF
794 /* number of entries in page table */
795 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
797 /* PTBs (Page Table Blocks) need to be aligned to 32K */
798 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
800 /* LOG2 number of continuous pages for the fragment field */
801 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
803 #define AMDGPU_PTE_VALID (1 << 0)
804 #define AMDGPU_PTE_SYSTEM (1 << 1)
805 #define AMDGPU_PTE_SNOOPED (1 << 2)
808 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
810 #define AMDGPU_PTE_READABLE (1 << 5)
811 #define AMDGPU_PTE_WRITEABLE (1 << 6)
813 #define AMDGPU_PTE_FRAG(x) ((x & 0x1f) << 7)
815 /* How to programm VM fault handling */
816 #define AMDGPU_VM_FAULT_STOP_NEVER 0
817 #define AMDGPU_VM_FAULT_STOP_FIRST 1
818 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
820 struct amdgpu_vm_pt {
821 struct amdgpu_bo_list_entry entry;
823 uint64_t shadow_addr;
827 /* tree of virtual addresses mapped */
830 /* protecting invalidated */
831 spinlock_t status_lock;
833 /* BOs moved, but not yet updated in the PT */
834 struct list_head invalidated;
836 /* BOs cleared in the PT because of a move */
837 struct list_head cleared;
839 /* BO mappings freed, but not yet updated in the PT */
840 struct list_head freed;
842 /* contains the page directory */
843 struct amdgpu_bo *page_directory;
844 unsigned max_pde_used;
845 struct fence *page_directory_fence;
846 uint64_t last_eviction_counter;
848 /* array of page tables, one for each page directory entry */
849 struct amdgpu_vm_pt *page_tables;
851 /* for id and flush management per ring */
852 struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS];
854 /* protecting freed */
855 spinlock_t freed_lock;
857 /* Scheduler entity for page table updates */
858 struct amd_sched_entity entity;
864 struct amdgpu_vm_id {
865 struct list_head list;
867 struct amdgpu_sync active;
868 struct fence *last_flush;
871 uint64_t pd_gpu_addr;
872 /* last flushed PD/PT update */
873 struct fence *flushed_updates;
875 uint32_t current_gpu_reset_count;
885 struct amdgpu_vm_manager {
886 /* Handling of VMIDs */
889 struct list_head ids_lru;
890 struct amdgpu_vm_id ids[AMDGPU_NUM_VM];
892 /* Handling of VM fences */
894 unsigned seqno[AMDGPU_MAX_RINGS];
897 /* vram base address for page table entry */
898 u64 vram_base_offset;
901 /* vm pte handling */
902 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
903 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
904 unsigned vm_pte_num_rings;
905 atomic_t vm_pte_next_ring;
906 /* client id counter */
907 atomic64_t client_counter;
910 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
911 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
912 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
913 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
914 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
915 struct list_head *validated,
916 struct amdgpu_bo_list_entry *entry);
917 void amdgpu_vm_get_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
918 struct list_head *duplicates);
919 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
920 struct amdgpu_vm *vm);
921 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
922 struct amdgpu_sync *sync, struct fence *fence,
923 struct amdgpu_job *job);
924 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job);
925 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
926 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
927 struct amdgpu_vm *vm);
928 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
929 struct amdgpu_vm *vm);
930 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
931 struct amdgpu_sync *sync);
932 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
933 struct amdgpu_bo_va *bo_va,
935 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
936 struct amdgpu_bo *bo);
937 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
938 struct amdgpu_bo *bo);
939 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
940 struct amdgpu_vm *vm,
941 struct amdgpu_bo *bo);
942 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
943 struct amdgpu_bo_va *bo_va,
944 uint64_t addr, uint64_t offset,
945 uint64_t size, uint32_t flags);
946 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
947 struct amdgpu_bo_va *bo_va,
949 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
950 struct amdgpu_bo_va *bo_va);
953 * context related structures
956 struct amdgpu_ctx_ring {
958 struct fence **fences;
959 struct amd_sched_entity entity;
963 struct kref refcount;
964 struct amdgpu_device *adev;
965 unsigned reset_counter;
966 spinlock_t ring_lock;
967 struct fence **fences;
968 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
971 struct amdgpu_ctx_mgr {
972 struct amdgpu_device *adev;
974 /* protected by lock */
975 struct idr ctx_handles;
978 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
979 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
981 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
982 struct fence *fence);
983 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
984 struct amdgpu_ring *ring, uint64_t seq);
986 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
987 struct drm_file *filp);
989 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
990 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
993 * file private structure
996 struct amdgpu_fpriv {
998 struct mutex bo_list_lock;
999 struct idr bo_list_handles;
1000 struct amdgpu_ctx_mgr ctx_mgr;
1007 struct amdgpu_bo_list {
1009 struct amdgpu_bo *gds_obj;
1010 struct amdgpu_bo *gws_obj;
1011 struct amdgpu_bo *oa_obj;
1012 unsigned first_userptr;
1013 unsigned num_entries;
1014 struct amdgpu_bo_list_entry *array;
1017 struct amdgpu_bo_list *
1018 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1019 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1020 struct list_head *validated);
1021 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1022 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1027 #include "clearstate_defs.h"
1029 struct amdgpu_rlc_funcs {
1030 void (*enter_safe_mode)(struct amdgpu_device *adev);
1031 void (*exit_safe_mode)(struct amdgpu_device *adev);
1035 /* for power gating */
1036 struct amdgpu_bo *save_restore_obj;
1037 uint64_t save_restore_gpu_addr;
1038 volatile uint32_t *sr_ptr;
1039 const u32 *reg_list;
1041 /* for clear state */
1042 struct amdgpu_bo *clear_state_obj;
1043 uint64_t clear_state_gpu_addr;
1044 volatile uint32_t *cs_ptr;
1045 const struct cs_section_def *cs_data;
1046 u32 clear_state_size;
1048 struct amdgpu_bo *cp_table_obj;
1049 uint64_t cp_table_gpu_addr;
1050 volatile uint32_t *cp_table_ptr;
1053 /* safe mode for updating CG/PG state */
1055 const struct amdgpu_rlc_funcs *funcs;
1057 /* for firmware data */
1058 u32 save_and_restore_offset;
1059 u32 clear_state_descriptor_offset;
1060 u32 avail_scratch_ram_locations;
1061 u32 reg_restore_list_size;
1062 u32 reg_list_format_start;
1063 u32 reg_list_format_separate_start;
1064 u32 starting_offsets_start;
1065 u32 reg_list_format_size_bytes;
1066 u32 reg_list_size_bytes;
1068 u32 *register_list_format;
1069 u32 *register_restore;
1073 struct amdgpu_bo *hpd_eop_obj;
1074 u64 hpd_eop_gpu_addr;
1081 * GPU scratch registers structures, functions & helpers
1083 struct amdgpu_scratch {
1091 * GFX configurations
1093 struct amdgpu_gca_config {
1094 unsigned max_shader_engines;
1095 unsigned max_tile_pipes;
1096 unsigned max_cu_per_sh;
1097 unsigned max_sh_per_se;
1098 unsigned max_backends_per_se;
1099 unsigned max_texture_channel_caches;
1101 unsigned max_gs_threads;
1102 unsigned max_hw_contexts;
1103 unsigned sc_prim_fifo_size_frontend;
1104 unsigned sc_prim_fifo_size_backend;
1105 unsigned sc_hiz_tile_fifo_size;
1106 unsigned sc_earlyz_tile_fifo_size;
1108 unsigned num_tile_pipes;
1109 unsigned backend_enable_mask;
1110 unsigned mem_max_burst_length_bytes;
1111 unsigned mem_row_size_in_kb;
1112 unsigned shader_engine_tile_size;
1114 unsigned multi_gpu_tile_size;
1115 unsigned mc_arb_ramcfg;
1116 unsigned gb_addr_config;
1119 uint32_t tile_mode_array[32];
1120 uint32_t macrotile_mode_array[16];
1123 struct amdgpu_cu_info {
1124 uint32_t number; /* total active CU number */
1125 uint32_t ao_cu_mask;
1126 uint32_t bitmap[4][4];
1129 struct amdgpu_gfx_funcs {
1130 /* get the gpu clock counter */
1131 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1132 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
1136 struct mutex gpu_clock_mutex;
1137 struct amdgpu_gca_config config;
1138 struct amdgpu_rlc rlc;
1139 struct amdgpu_mec mec;
1140 struct amdgpu_scratch scratch;
1141 const struct firmware *me_fw; /* ME firmware */
1142 uint32_t me_fw_version;
1143 const struct firmware *pfp_fw; /* PFP firmware */
1144 uint32_t pfp_fw_version;
1145 const struct firmware *ce_fw; /* CE firmware */
1146 uint32_t ce_fw_version;
1147 const struct firmware *rlc_fw; /* RLC firmware */
1148 uint32_t rlc_fw_version;
1149 const struct firmware *mec_fw; /* MEC firmware */
1150 uint32_t mec_fw_version;
1151 const struct firmware *mec2_fw; /* MEC2 firmware */
1152 uint32_t mec2_fw_version;
1153 uint32_t me_feature_version;
1154 uint32_t ce_feature_version;
1155 uint32_t pfp_feature_version;
1156 uint32_t rlc_feature_version;
1157 uint32_t mec_feature_version;
1158 uint32_t mec2_feature_version;
1159 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1160 unsigned num_gfx_rings;
1161 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1162 unsigned num_compute_rings;
1163 struct amdgpu_irq_src eop_irq;
1164 struct amdgpu_irq_src priv_reg_irq;
1165 struct amdgpu_irq_src priv_inst_irq;
1167 uint32_t gfx_current_status;
1169 unsigned ce_ram_size;
1170 struct amdgpu_cu_info cu_info;
1171 const struct amdgpu_gfx_funcs *funcs;
1174 uint32_t grbm_soft_reset;
1175 uint32_t srbm_soft_reset;
1178 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
1179 unsigned size, struct amdgpu_ib *ib);
1180 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
1182 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
1183 struct amdgpu_ib *ib, struct fence *last_vm_update,
1184 struct amdgpu_job *job, struct fence **f);
1185 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1186 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1187 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1188 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1189 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
1190 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
1191 void amdgpu_ring_commit(struct amdgpu_ring *ring);
1192 void amdgpu_ring_undo(struct amdgpu_ring *ring);
1193 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1194 unsigned ring_size, u32 nop, u32 align_mask,
1195 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1196 enum amdgpu_ring_type ring_type);
1197 void amdgpu_ring_fini(struct amdgpu_ring *ring);
1202 struct amdgpu_cs_chunk {
1208 struct amdgpu_cs_parser {
1209 struct amdgpu_device *adev;
1210 struct drm_file *filp;
1211 struct amdgpu_ctx *ctx;
1215 struct amdgpu_cs_chunk *chunks;
1217 /* scheduler job object */
1218 struct amdgpu_job *job;
1220 /* buffer objects */
1221 struct ww_acquire_ctx ticket;
1222 struct amdgpu_bo_list *bo_list;
1223 struct amdgpu_bo_list_entry vm_pd;
1224 struct list_head validated;
1225 struct fence *fence;
1226 uint64_t bytes_moved_threshold;
1227 uint64_t bytes_moved;
1228 struct amdgpu_bo_list_entry *evictable;
1231 struct amdgpu_bo_list_entry uf_entry;
1235 struct amd_sched_job base;
1236 struct amdgpu_device *adev;
1237 struct amdgpu_vm *vm;
1238 struct amdgpu_ring *ring;
1239 struct amdgpu_sync sync;
1240 struct amdgpu_ib *ibs;
1241 struct fence *fence; /* the hw fence */
1245 bool vm_needs_flush;
1247 uint64_t vm_pd_addr;
1248 uint32_t gds_base, gds_size;
1249 uint32_t gws_base, gws_size;
1250 uint32_t oa_base, oa_size;
1252 /* user fence handling */
1254 uint64_t uf_sequence;
1257 #define to_amdgpu_job(sched_job) \
1258 container_of((sched_job), struct amdgpu_job, base)
1260 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1261 uint32_t ib_idx, int idx)
1263 return p->job->ibs[ib_idx].ptr[idx];
1266 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1267 uint32_t ib_idx, int idx,
1270 p->job->ibs[ib_idx].ptr[idx] = value;
1276 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1279 struct amdgpu_bo *wb_obj;
1280 volatile uint32_t *wb;
1282 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1283 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1286 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1287 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1291 enum amdgpu_int_thermal_type {
1293 THERMAL_TYPE_EXTERNAL,
1294 THERMAL_TYPE_EXTERNAL_GPIO,
1297 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1298 THERMAL_TYPE_EVERGREEN,
1302 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1307 enum amdgpu_dpm_auto_throttle_src {
1308 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1309 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1312 enum amdgpu_dpm_event_src {
1313 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1314 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1315 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1316 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1317 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1320 #define AMDGPU_MAX_VCE_LEVELS 6
1322 enum amdgpu_vce_level {
1323 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1324 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1325 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1326 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1327 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1328 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1332 u32 caps; /* vbios flags */
1333 u32 class; /* vbios flags */
1334 u32 class2; /* vbios flags */
1342 enum amdgpu_vce_level vce_level;
1347 struct amdgpu_dpm_thermal {
1348 /* thermal interrupt work */
1349 struct work_struct work;
1350 /* low temperature threshold */
1352 /* high temperature threshold */
1354 /* was last interrupt low to high or high to low */
1356 /* interrupt source */
1357 struct amdgpu_irq_src irq;
1360 enum amdgpu_clk_action
1366 struct amdgpu_blacklist_clocks
1370 enum amdgpu_clk_action action;
1373 struct amdgpu_clock_and_voltage_limits {
1380 struct amdgpu_clock_array {
1385 struct amdgpu_clock_voltage_dependency_entry {
1390 struct amdgpu_clock_voltage_dependency_table {
1392 struct amdgpu_clock_voltage_dependency_entry *entries;
1395 union amdgpu_cac_leakage_entry {
1407 struct amdgpu_cac_leakage_table {
1409 union amdgpu_cac_leakage_entry *entries;
1412 struct amdgpu_phase_shedding_limits_entry {
1418 struct amdgpu_phase_shedding_limits_table {
1420 struct amdgpu_phase_shedding_limits_entry *entries;
1423 struct amdgpu_uvd_clock_voltage_dependency_entry {
1429 struct amdgpu_uvd_clock_voltage_dependency_table {
1431 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1434 struct amdgpu_vce_clock_voltage_dependency_entry {
1440 struct amdgpu_vce_clock_voltage_dependency_table {
1442 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1445 struct amdgpu_ppm_table {
1447 u16 cpu_core_number;
1449 u32 small_ac_platform_tdp;
1451 u32 small_ac_platform_tdc;
1458 struct amdgpu_cac_tdp_table {
1460 u16 configurable_tdp;
1462 u16 battery_power_limit;
1463 u16 small_power_limit;
1464 u16 low_cac_leakage;
1465 u16 high_cac_leakage;
1466 u16 maximum_power_delivery_limit;
1469 struct amdgpu_dpm_dynamic_state {
1470 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1471 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1472 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1473 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1474 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1475 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1476 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1477 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1478 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1479 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1480 struct amdgpu_clock_array valid_sclk_values;
1481 struct amdgpu_clock_array valid_mclk_values;
1482 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1483 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1484 u32 mclk_sclk_ratio;
1485 u32 sclk_mclk_delta;
1486 u16 vddc_vddci_delta;
1487 u16 min_vddc_for_pcie_gen2;
1488 struct amdgpu_cac_leakage_table cac_leakage_table;
1489 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1490 struct amdgpu_ppm_table *ppm_table;
1491 struct amdgpu_cac_tdp_table *cac_tdp_table;
1494 struct amdgpu_dpm_fan {
1505 u16 default_max_fan_pwm;
1506 u16 default_fan_output_sensitivity;
1507 u16 fan_output_sensitivity;
1508 bool ucode_fan_control;
1511 enum amdgpu_pcie_gen {
1512 AMDGPU_PCIE_GEN1 = 0,
1513 AMDGPU_PCIE_GEN2 = 1,
1514 AMDGPU_PCIE_GEN3 = 2,
1515 AMDGPU_PCIE_GEN_INVALID = 0xffff
1518 enum amdgpu_dpm_forced_level {
1519 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1520 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1521 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1522 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
1525 struct amdgpu_vce_state {
1536 struct amdgpu_dpm_funcs {
1537 int (*get_temperature)(struct amdgpu_device *adev);
1538 int (*pre_set_power_state)(struct amdgpu_device *adev);
1539 int (*set_power_state)(struct amdgpu_device *adev);
1540 void (*post_set_power_state)(struct amdgpu_device *adev);
1541 void (*display_configuration_changed)(struct amdgpu_device *adev);
1542 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1543 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1544 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1545 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1546 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1547 bool (*vblank_too_short)(struct amdgpu_device *adev);
1548 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1549 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
1550 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1551 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1552 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1553 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1554 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1555 int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask);
1556 int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf);
1557 int (*get_sclk_od)(struct amdgpu_device *adev);
1558 int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value);
1559 int (*get_mclk_od)(struct amdgpu_device *adev);
1560 int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value);
1564 struct amdgpu_ps *ps;
1565 /* number of valid power states */
1567 /* current power state that is active */
1568 struct amdgpu_ps *current_ps;
1569 /* requested power state */
1570 struct amdgpu_ps *requested_ps;
1571 /* boot up power state */
1572 struct amdgpu_ps *boot_ps;
1573 /* default uvd power state */
1574 struct amdgpu_ps *uvd_ps;
1575 /* vce requirements */
1576 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1577 enum amdgpu_vce_level vce_level;
1578 enum amd_pm_state_type state;
1579 enum amd_pm_state_type user_state;
1581 u32 voltage_response_time;
1582 u32 backbias_response_time;
1584 u32 new_active_crtcs;
1585 int new_active_crtc_count;
1586 u32 current_active_crtcs;
1587 int current_active_crtc_count;
1588 struct amdgpu_dpm_dynamic_state dyn_state;
1589 struct amdgpu_dpm_fan fan;
1592 u32 near_tdp_limit_adjusted;
1593 u32 sq_ramping_threshold;
1597 u16 load_line_slope;
1600 /* special states active */
1601 bool thermal_active;
1604 /* thermal handling */
1605 struct amdgpu_dpm_thermal thermal;
1607 enum amdgpu_dpm_forced_level forced_level;
1616 struct amdgpu_i2c_chan *i2c_bus;
1617 /* internal thermal controller on rv6xx+ */
1618 enum amdgpu_int_thermal_type int_thermal_type;
1619 struct device *int_hwmon_dev;
1620 /* fan control parameters */
1622 u8 fan_pulses_per_revolution;
1627 bool sysfs_initialized;
1628 struct amdgpu_dpm dpm;
1629 const struct firmware *fw; /* SMC firmware */
1630 uint32_t fw_version;
1631 const struct amdgpu_dpm_funcs *funcs;
1632 uint32_t pcie_gen_mask;
1633 uint32_t pcie_mlw_mask;
1634 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
1637 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1642 #define AMDGPU_DEFAULT_UVD_HANDLES 10
1643 #define AMDGPU_MAX_UVD_HANDLES 40
1644 #define AMDGPU_UVD_STACK_SIZE (200*1024)
1645 #define AMDGPU_UVD_HEAP_SIZE (256*1024)
1646 #define AMDGPU_UVD_SESSION_SIZE (50*1024)
1647 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1650 struct amdgpu_bo *vcpu_bo;
1653 unsigned fw_version;
1655 unsigned max_handles;
1656 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1657 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1658 struct delayed_work idle_work;
1659 const struct firmware *fw; /* UVD firmware */
1660 struct amdgpu_ring ring;
1661 struct amdgpu_irq_src irq;
1662 bool address_64_bit;
1664 struct amd_sched_entity entity;
1665 uint32_t srbm_soft_reset;
1671 #define AMDGPU_MAX_VCE_HANDLES 16
1672 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1674 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1675 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1678 struct amdgpu_bo *vcpu_bo;
1680 unsigned fw_version;
1681 unsigned fb_version;
1682 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1683 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1684 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
1685 struct delayed_work idle_work;
1686 struct mutex idle_mutex;
1687 const struct firmware *fw; /* VCE firmware */
1688 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1689 struct amdgpu_irq_src irq;
1690 unsigned harvest_config;
1691 struct amd_sched_entity entity;
1692 uint32_t srbm_soft_reset;
1699 struct amdgpu_sdma_instance {
1701 const struct firmware *fw;
1702 uint32_t fw_version;
1703 uint32_t feature_version;
1705 struct amdgpu_ring ring;
1709 struct amdgpu_sdma {
1710 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1711 #ifdef CONFIG_DRM_AMDGPU_SI
1712 //SI DMA has a difference trap irq number for the second engine
1713 struct amdgpu_irq_src trap_irq_1;
1715 struct amdgpu_irq_src trap_irq;
1716 struct amdgpu_irq_src illegal_inst_irq;
1718 uint32_t srbm_soft_reset;
1724 struct amdgpu_firmware {
1725 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1727 struct amdgpu_bo *fw_buf;
1728 unsigned int fw_size;
1734 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1740 void amdgpu_test_moves(struct amdgpu_device *adev);
1741 void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1742 struct amdgpu_ring *cpA,
1743 struct amdgpu_ring *cpB);
1744 void amdgpu_test_syncing(struct amdgpu_device *adev);
1749 #if defined(CONFIG_MMU_NOTIFIER)
1750 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1751 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1753 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1757 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1763 struct amdgpu_debugfs {
1764 const struct drm_info_list *files;
1768 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1769 const struct drm_info_list *files,
1771 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1773 #if defined(CONFIG_DEBUG_FS)
1774 int amdgpu_debugfs_init(struct drm_minor *minor);
1775 void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1778 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1781 * amdgpu smumgr functions
1783 struct amdgpu_smumgr_funcs {
1784 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1785 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1786 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1792 struct amdgpu_smumgr {
1793 struct amdgpu_bo *toc_buf;
1794 struct amdgpu_bo *smu_buf;
1795 /* asic priv smu data */
1797 spinlock_t smu_lock;
1798 /* smumgr functions */
1799 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1800 /* ucode loading complete flag */
1805 * ASIC specific register table accessible by UMD
1807 struct amdgpu_allowed_register_entry {
1808 uint32_t reg_offset;
1814 * ASIC specific functions.
1816 struct amdgpu_asic_funcs {
1817 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1818 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1819 u8 *bios, u32 length_bytes);
1820 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1821 u32 sh_num, u32 reg_offset, u32 *value);
1822 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1823 int (*reset)(struct amdgpu_device *adev);
1824 /* get the reference clock */
1825 u32 (*get_xclk)(struct amdgpu_device *adev);
1826 /* MM block clocks */
1827 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1828 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1829 /* query virtual capabilities */
1830 u32 (*get_virtual_caps)(struct amdgpu_device *adev);
1831 /* static power management */
1832 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1833 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
1839 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1840 struct drm_file *filp);
1841 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1842 struct drm_file *filp);
1844 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1845 struct drm_file *filp);
1846 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1847 struct drm_file *filp);
1848 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1849 struct drm_file *filp);
1850 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1851 struct drm_file *filp);
1852 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1853 struct drm_file *filp);
1854 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1855 struct drm_file *filp);
1856 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1857 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1859 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1860 struct drm_file *filp);
1862 /* VRAM scratch page for HDP bug, default vram page */
1863 struct amdgpu_vram_scratch {
1864 struct amdgpu_bo *robj;
1865 volatile uint32_t *ptr;
1872 struct amdgpu_atif_notification_cfg {
1877 struct amdgpu_atif_notifications {
1878 bool display_switch;
1879 bool expansion_mode_change;
1881 bool forced_power_state;
1882 bool system_power_state;
1883 bool display_conf_change;
1885 bool brightness_change;
1886 bool dgpu_display_event;
1889 struct amdgpu_atif_functions {
1891 bool sbios_requests;
1892 bool select_active_disp;
1894 bool get_tv_standard;
1895 bool set_tv_standard;
1896 bool get_panel_expansion_mode;
1897 bool set_panel_expansion_mode;
1898 bool temperature_change;
1899 bool graphics_device_types;
1902 struct amdgpu_atif {
1903 struct amdgpu_atif_notifications notifications;
1904 struct amdgpu_atif_functions functions;
1905 struct amdgpu_atif_notification_cfg notification_cfg;
1906 struct amdgpu_encoder *encoder_for_bl;
1909 struct amdgpu_atcs_functions {
1913 bool pcie_bus_width;
1916 struct amdgpu_atcs {
1917 struct amdgpu_atcs_functions functions;
1923 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1924 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
1927 /* GPU virtualization */
1928 #define AMDGPU_VIRT_CAPS_SRIOV_EN (1 << 0)
1929 #define AMDGPU_VIRT_CAPS_IS_VF (1 << 1)
1930 struct amdgpu_virtualization {
1931 bool supports_sr_iov;
1937 * Core structure, functions and helpers.
1939 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1940 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1942 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1943 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1945 struct amdgpu_ip_block_status {
1952 struct amdgpu_device {
1954 struct drm_device *ddev;
1955 struct pci_dev *pdev;
1957 #ifdef CONFIG_DRM_AMD_ACP
1958 struct amdgpu_acp acp;
1962 enum amd_asic_type asic_type;
1965 uint32_t external_rev_id;
1966 unsigned long flags;
1968 const struct amdgpu_asic_funcs *asic_funcs;
1972 struct work_struct reset_work;
1973 struct notifier_block acpi_nb;
1974 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1975 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1976 unsigned debugfs_count;
1977 #if defined(CONFIG_DEBUG_FS)
1978 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1980 struct amdgpu_atif atif;
1981 struct amdgpu_atcs atcs;
1982 struct mutex srbm_mutex;
1983 /* GRBM index mutex. Protects concurrent access to GRBM index */
1984 struct mutex grbm_idx_mutex;
1985 struct dev_pm_domain vga_pm_domain;
1986 bool have_disp_power_ref;
1991 struct amdgpu_bo *stollen_vga_memory;
1992 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1994 /* Register/doorbell mmio */
1995 resource_size_t rmmio_base;
1996 resource_size_t rmmio_size;
1997 void __iomem *rmmio;
1998 /* protects concurrent MM_INDEX/DATA based register access */
1999 spinlock_t mmio_idx_lock;
2000 /* protects concurrent SMC based register access */
2001 spinlock_t smc_idx_lock;
2002 amdgpu_rreg_t smc_rreg;
2003 amdgpu_wreg_t smc_wreg;
2004 /* protects concurrent PCIE register access */
2005 spinlock_t pcie_idx_lock;
2006 amdgpu_rreg_t pcie_rreg;
2007 amdgpu_wreg_t pcie_wreg;
2008 amdgpu_rreg_t pciep_rreg;
2009 amdgpu_wreg_t pciep_wreg;
2010 /* protects concurrent UVD register access */
2011 spinlock_t uvd_ctx_idx_lock;
2012 amdgpu_rreg_t uvd_ctx_rreg;
2013 amdgpu_wreg_t uvd_ctx_wreg;
2014 /* protects concurrent DIDT register access */
2015 spinlock_t didt_idx_lock;
2016 amdgpu_rreg_t didt_rreg;
2017 amdgpu_wreg_t didt_wreg;
2018 /* protects concurrent gc_cac register access */
2019 spinlock_t gc_cac_idx_lock;
2020 amdgpu_rreg_t gc_cac_rreg;
2021 amdgpu_wreg_t gc_cac_wreg;
2022 /* protects concurrent ENDPOINT (audio) register access */
2023 spinlock_t audio_endpt_idx_lock;
2024 amdgpu_block_rreg_t audio_endpt_rreg;
2025 amdgpu_block_wreg_t audio_endpt_wreg;
2026 void __iomem *rio_mem;
2027 resource_size_t rio_mem_size;
2028 struct amdgpu_doorbell doorbell;
2030 /* clock/pll info */
2031 struct amdgpu_clock clock;
2034 struct amdgpu_mc mc;
2035 struct amdgpu_gart gart;
2036 struct amdgpu_dummy_page dummy_page;
2037 struct amdgpu_vm_manager vm_manager;
2039 /* memory management */
2040 struct amdgpu_mman mman;
2041 struct amdgpu_vram_scratch vram_scratch;
2042 struct amdgpu_wb wb;
2043 atomic64_t vram_usage;
2044 atomic64_t vram_vis_usage;
2045 atomic64_t gtt_usage;
2046 atomic64_t num_bytes_moved;
2047 atomic64_t num_evictions;
2048 atomic_t gpu_reset_counter;
2050 /* data for buffer migration throttling */
2054 s64 accum_us; /* accumulated microseconds */
2059 bool enable_virtual_display;
2060 struct amdgpu_mode_info mode_info;
2061 struct work_struct hotplug_work;
2062 struct amdgpu_irq_src crtc_irq;
2063 struct amdgpu_irq_src pageflip_irq;
2064 struct amdgpu_irq_src hpd_irq;
2069 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2071 struct amdgpu_sa_manager ring_tmp_bo;
2074 struct amdgpu_irq irq;
2077 struct amd_powerplay powerplay;
2079 bool pp_force_state_enabled;
2082 struct amdgpu_pm pm;
2087 struct amdgpu_smumgr smu;
2090 struct amdgpu_gfx gfx;
2093 struct amdgpu_sdma sdma;
2096 struct amdgpu_uvd uvd;
2099 struct amdgpu_vce vce;
2102 struct amdgpu_firmware firmware;
2105 struct amdgpu_gds gds;
2107 const struct amdgpu_ip_block_version *ip_blocks;
2109 struct amdgpu_ip_block_status *ip_block_status;
2110 struct mutex mn_lock;
2111 DECLARE_HASHTABLE(mn_hash, 7);
2113 /* tracking pinned memory */
2115 u64 invisible_pin_size;
2118 /* amdkfd interface */
2119 struct kfd_dev *kfd;
2121 struct amdgpu_virtualization virtualization;
2123 /* link all shadow bo */
2124 struct list_head shadow_list;
2125 struct mutex shadow_list_lock;
2127 spinlock_t gtt_list_lock;
2128 struct list_head gtt_list;
2132 bool amdgpu_device_is_px(struct drm_device *dev);
2133 int amdgpu_device_init(struct amdgpu_device *adev,
2134 struct drm_device *ddev,
2135 struct pci_dev *pdev,
2137 void amdgpu_device_fini(struct amdgpu_device *adev);
2138 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2140 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2141 bool always_indirect);
2142 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2143 bool always_indirect);
2144 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2145 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2147 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2148 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2151 * Registers read & write functions.
2153 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2154 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2155 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2156 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2157 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2158 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2159 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2160 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2161 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2162 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
2163 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
2164 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2165 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2166 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2167 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2168 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2169 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2170 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
2171 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
2172 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2173 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2174 #define WREG32_P(reg, val, mask) \
2176 uint32_t tmp_ = RREG32(reg); \
2178 tmp_ |= ((val) & ~(mask)); \
2179 WREG32(reg, tmp_); \
2181 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2182 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2183 #define WREG32_PLL_P(reg, val, mask) \
2185 uint32_t tmp_ = RREG32_PLL(reg); \
2187 tmp_ |= ((val) & ~(mask)); \
2188 WREG32_PLL(reg, tmp_); \
2190 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2191 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2192 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2194 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2195 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2197 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2198 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2200 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2201 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2202 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2204 #define REG_GET_FIELD(value, reg, field) \
2205 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2207 #define WREG32_FIELD(reg, field, val) \
2208 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
2213 #define RBIOS8(i) (adev->bios[i])
2214 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2215 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2220 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2222 if (ring->count_dw <= 0)
2223 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2224 ring->ring[ring->wptr++] = v;
2225 ring->wptr &= ring->ptr_mask;
2229 static inline struct amdgpu_sdma_instance *
2230 amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
2232 struct amdgpu_device *adev = ring->adev;
2235 for (i = 0; i < adev->sdma.num_instances; i++)
2236 if (&adev->sdma.instance[i].ring == ring)
2239 if (i < AMDGPU_MAX_SDMA_INSTANCES)
2240 return &adev->sdma.instance[i];
2248 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2249 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2250 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2251 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2252 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2253 #define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev)))
2254 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
2255 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
2256 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2257 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2258 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
2259 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2260 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2261 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2262 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2263 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
2264 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2265 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2266 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2267 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
2268 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2269 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2270 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2271 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
2272 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
2273 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2274 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2275 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2276 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2277 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
2278 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
2279 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
2280 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
2281 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
2282 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2283 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2284 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2285 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2286 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2287 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2288 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2289 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2290 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2291 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2292 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2293 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2294 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2295 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
2296 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2297 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2298 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2299 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2300 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2301 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
2302 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2303 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2304 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2305 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2306 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2307 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2308 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2309 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2310 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
2311 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
2313 #define amdgpu_dpm_get_temperature(adev) \
2314 ((adev)->pp_enabled ? \
2315 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
2316 (adev)->pm.funcs->get_temperature((adev)))
2318 #define amdgpu_dpm_set_fan_control_mode(adev, m) \
2319 ((adev)->pp_enabled ? \
2320 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
2321 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
2323 #define amdgpu_dpm_get_fan_control_mode(adev) \
2324 ((adev)->pp_enabled ? \
2325 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
2326 (adev)->pm.funcs->get_fan_control_mode((adev)))
2328 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
2329 ((adev)->pp_enabled ? \
2330 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2331 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
2333 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
2334 ((adev)->pp_enabled ? \
2335 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2336 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
2338 #define amdgpu_dpm_get_sclk(adev, l) \
2339 ((adev)->pp_enabled ? \
2340 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
2341 (adev)->pm.funcs->get_sclk((adev), (l)))
2343 #define amdgpu_dpm_get_mclk(adev, l) \
2344 ((adev)->pp_enabled ? \
2345 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
2346 (adev)->pm.funcs->get_mclk((adev), (l)))
2349 #define amdgpu_dpm_force_performance_level(adev, l) \
2350 ((adev)->pp_enabled ? \
2351 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
2352 (adev)->pm.funcs->force_performance_level((adev), (l)))
2354 #define amdgpu_dpm_powergate_uvd(adev, g) \
2355 ((adev)->pp_enabled ? \
2356 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
2357 (adev)->pm.funcs->powergate_uvd((adev), (g)))
2359 #define amdgpu_dpm_powergate_vce(adev, g) \
2360 ((adev)->pp_enabled ? \
2361 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
2362 (adev)->pm.funcs->powergate_vce((adev), (g)))
2364 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
2365 ((adev)->pp_enabled ? \
2366 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
2367 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
2369 #define amdgpu_dpm_get_current_power_state(adev) \
2370 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
2372 #define amdgpu_dpm_get_performance_level(adev) \
2373 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
2375 #define amdgpu_dpm_get_pp_num_states(adev, data) \
2376 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2378 #define amdgpu_dpm_get_pp_table(adev, table) \
2379 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2381 #define amdgpu_dpm_set_pp_table(adev, buf, size) \
2382 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2384 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2385 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2387 #define amdgpu_dpm_force_clock_level(adev, type, level) \
2388 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2390 #define amdgpu_dpm_get_sclk_od(adev) \
2391 (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)
2393 #define amdgpu_dpm_set_sclk_od(adev, value) \
2394 (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)
2396 #define amdgpu_dpm_get_mclk_od(adev) \
2397 ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
2399 #define amdgpu_dpm_set_mclk_od(adev, value) \
2400 ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
2402 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
2403 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
2405 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2407 /* Common functions */
2408 int amdgpu_gpu_reset(struct amdgpu_device *adev);
2409 bool amdgpu_need_backup(struct amdgpu_device *adev);
2410 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2411 bool amdgpu_card_posted(struct amdgpu_device *adev);
2412 void amdgpu_update_display_priority(struct amdgpu_device *adev);
2414 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2415 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2416 u32 ip_instance, u32 ring,
2417 struct amdgpu_ring **out_ring);
2418 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2419 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2420 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
2421 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2423 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2424 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
2425 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2427 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
2428 int *last_invalidated);
2429 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2430 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2431 struct ttm_mem_reg *mem);
2432 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2433 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2434 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2435 u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev);
2436 int amdgpu_ttm_global_init(struct amdgpu_device *adev);
2437 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2438 const u32 *registers,
2439 const u32 array_size);
2441 bool amdgpu_device_is_px(struct drm_device *dev);
2443 #if defined(CONFIG_VGA_SWITCHEROO)
2444 void amdgpu_register_atpx_handler(void);
2445 void amdgpu_unregister_atpx_handler(void);
2446 bool amdgpu_has_atpx_dgpu_power_cntl(void);
2447 bool amdgpu_is_atpx_hybrid(void);
2449 static inline void amdgpu_register_atpx_handler(void) {}
2450 static inline void amdgpu_unregister_atpx_handler(void) {}
2451 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2452 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
2458 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2459 extern const int amdgpu_max_kms_ioctl;
2461 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2462 int amdgpu_driver_unload_kms(struct drm_device *dev);
2463 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2464 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2465 void amdgpu_driver_postclose_kms(struct drm_device *dev,
2466 struct drm_file *file_priv);
2467 void amdgpu_driver_preclose_kms(struct drm_device *dev,
2468 struct drm_file *file_priv);
2469 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
2470 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
2471 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2472 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2473 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2474 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
2476 struct timeval *vblank_time,
2478 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2482 * functions used by amdgpu_encoder.c
2484 struct amdgpu_afmt_acr {
2498 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2501 #if defined(CONFIG_ACPI)
2502 int amdgpu_acpi_init(struct amdgpu_device *adev);
2503 void amdgpu_acpi_fini(struct amdgpu_device *adev);
2504 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2505 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2506 u8 perf_req, bool advertise);
2507 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2509 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2510 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2513 struct amdgpu_bo_va_mapping *
2514 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2515 uint64_t addr, struct amdgpu_bo **bo);
2517 #include "amdgpu_object.h"