drivers/firmware/arm_scmi/clock.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * System Control and Management Interface (SCMI) Clock Protocol
   4  *
   5  * Copyright (C) 2018-2021 ARM Ltd.
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/sort.h>
  10
  11 #include "common.h"
  12
  13 enum scmi_clock_protocol_cmd {
  14         CLOCK_ATTRIBUTES = 0x3,
  15         CLOCK_DESCRIBE_RATES = 0x4,
  16         CLOCK_RATE_SET = 0x5,
  17         CLOCK_RATE_GET = 0x6,
  18         CLOCK_CONFIG_SET = 0x7,
  19 };
  20
  21 struct scmi_msg_resp_clock_protocol_attributes {
  22         __le16 num_clocks;
  23         u8 max_async_req;
  24         u8 reserved;
  25 };
  26
  27 struct scmi_msg_resp_clock_attributes {
  28         __le32 attributes;
  29 #define CLOCK_ENABLE    BIT(0)
  30         u8 name[SCMI_MAX_STR_SIZE];
  31         __le32 clock_enable_latency;
  32 };
  33
  34 struct scmi_clock_set_config {
  35         __le32 id;
  36         __le32 attributes;
  37 };
  38
  39 struct scmi_msg_clock_describe_rates {
  40         __le32 id;
  41         __le32 rate_index;
  42 };
  43
  44 struct scmi_msg_resp_clock_describe_rates {
  45         __le32 num_rates_flags;
  46 #define NUM_RETURNED(x)         ((x) & 0xfff)
  47 #define RATE_DISCRETE(x)        !((x) & BIT(12))
  48 #define NUM_REMAINING(x)        ((x) >> 16)
  49         struct {
  50                 __le32 value_low;
  51                 __le32 value_high;
  52         } rate[0];
  53 #define RATE_TO_U64(X)          \
  54 ({                              \
  55         typeof(X) x = (X);      \
  56         le32_to_cpu((x).value_low) | (u64)le32_to_cpu((x).value_high) << 32; \
  57 })
  58 };
  59
  60 struct scmi_clock_set_rate {
  61         __le32 flags;
  62 #define CLOCK_SET_ASYNC         BIT(0)
  63 #define CLOCK_SET_IGNORE_RESP   BIT(1)
  64 #define CLOCK_SET_ROUND_UP      BIT(2)
  65 #define CLOCK_SET_ROUND_AUTO    BIT(3)
  66         __le32 id;
  67         __le32 value_low;
  68         __le32 value_high;
  69 };
  70
  71 struct clock_info {
  72         u32 version;
  73         int num_clocks;
  74         int max_async_req;
  75         atomic_t cur_async_req;
  76         struct scmi_clock_info *clk;
  77 };
  78
  79 static int
  80 scmi_clock_protocol_attributes_get(const struct scmi_protocol_handle *ph,
  81                                    struct clock_info *ci)
  82 {
  83         int ret;
  84         struct scmi_xfer *t;
  85         struct scmi_msg_resp_clock_protocol_attributes *attr;
  86
  87         ret = ph->xops->xfer_get_init(ph, PROTOCOL_ATTRIBUTES,
  88                                       0, sizeof(*attr), &t);
  89         if (ret)
  90                 return ret;
  91
  92         attr = t->rx.buf;
  93
  94         ret = ph->xops->do_xfer(ph, t);
  95         if (!ret) {
  96                 ci->num_clocks = le16_to_cpu(attr->num_clocks);
  97                 ci->max_async_req = attr->max_async_req;
  98         }
  99
 100         ph->xops->xfer_put(ph, t);
 101         return ret;
 102 }
 103
 104 static int scmi_clock_attributes_get(const struct scmi_protocol_handle *ph,
 105                                      u32 clk_id, struct scmi_clock_info *clk)
 106 {
 107         int ret;
 108         struct scmi_xfer *t;
 109         struct scmi_msg_resp_clock_attributes *attr;
 110
 111         ret = ph->xops->xfer_get_init(ph, CLOCK_ATTRIBUTES,
 112                                       sizeof(clk_id), sizeof(*attr), &t);
 113         if (ret)
 114                 return ret;
 115
 116         put_unaligned_le32(clk_id, t->tx.buf);
 117         attr = t->rx.buf;
 118
 119         ret = ph->xops->do_xfer(ph, t);
 120         if (!ret) {
 121                 strlcpy(clk->name, attr->name, SCMI_MAX_STR_SIZE);
 122                 /* Is optional field clock_enable_latency provided ? */
 123                 if (t->rx.len == sizeof(*attr))
 124                         clk->enable_latency =
 125                                 le32_to_cpu(attr->clock_enable_latency);
 126         } else {
 127                 clk->name[0] = '\0';
 128         }
 129
 130         ph->xops->xfer_put(ph, t);
 131         return ret;
 132 }
 133
 134 static int rate_cmp_func(const void *_r1, const void *_r2)
 135 {
 136         const u64 *r1 = _r1, *r2 = _r2;
 137
 138         if (*r1 < *r2)
 139                 return -1;
 140         else if (*r1 == *r2)
 141                 return 0;
 142         else
 143                 return 1;
 144 }
 145
 146 static int
 147 scmi_clock_describe_rates_get(const struct scmi_protocol_handle *ph, u32 clk_id,
 148                               struct scmi_clock_info *clk)
 149 {
 150         u64 *rate = NULL;
 151         int ret, cnt;
 152         bool rate_discrete = false;
 153         u32 tot_rate_cnt = 0, rates_flag;
 154         u16 num_returned, num_remaining;
 155         struct scmi_xfer *t;
 156         struct scmi_msg_clock_describe_rates *clk_desc;
 157         struct scmi_msg_resp_clock_describe_rates *rlist;
 158
 159         ret = ph->xops->xfer_get_init(ph, CLOCK_DESCRIBE_RATES,
 160                                       sizeof(*clk_desc), 0, &t);
 161         if (ret)
 162                 return ret;
 163
 164         clk_desc = t->tx.buf;
 165         rlist = t->rx.buf;
 166
 167         do {
 168                 clk_desc->id = cpu_to_le32(clk_id);
 169                 /* Set the number of rates to be skipped/already read */
 170                 clk_desc->rate_index = cpu_to_le32(tot_rate_cnt);
 171
 172                 ret = ph->xops->do_xfer(ph, t);
 173                 if (ret)
 174                         goto err;
 175
 176                 rates_flag = le32_to_cpu(rlist->num_rates_flags);
 177                 num_remaining = NUM_REMAINING(rates_flag);
 178                 rate_discrete = RATE_DISCRETE(rates_flag);
 179                 num_returned = NUM_RETURNED(rates_flag);
 180
 181                 if (tot_rate_cnt + num_returned > SCMI_MAX_NUM_RATES) {
 182                         dev_err(ph->dev, "No. of rates > MAX_NUM_RATES");
 183                         break;
 184                 }
 185
 186                 if (!rate_discrete) {
 187                         clk->range.min_rate = RATE_TO_U64(rlist->rate[0]);
 188                         clk->range.max_rate = RATE_TO_U64(rlist->rate[1]);
 189                         clk->range.step_size = RATE_TO_U64(rlist->rate[2]);
 190                         dev_dbg(ph->dev, "Min %llu Max %llu Step %llu Hz\n",
 191                                 clk->range.min_rate, clk->range.max_rate,
 192                                 clk->range.step_size);
 193                         break;
 194                 }
 195
 196                 rate = &clk->list.rates[tot_rate_cnt];
 197                 for (cnt = 0; cnt < num_returned; cnt++, rate++) {
 198                         *rate = RATE_TO_U64(rlist->rate[cnt]);
 199                         dev_dbg(ph->dev, "Rate %llu Hz\n", *rate);
 200                 }
 201
 202                 tot_rate_cnt += num_returned;
 203
 204                 ph->xops->reset_rx_to_maxsz(ph, t);
 205                 /*
 206                  * check for both returned and remaining to avoid infinite
 207                  * loop due to buggy firmware
 208                  */
 209         } while (num_returned && num_remaining);
 210
 211         if (rate_discrete && rate) {
 212                 clk->list.num_rates = tot_rate_cnt;
 213                 sort(rate, tot_rate_cnt, sizeof(*rate), rate_cmp_func, NULL);
 214         }
 215
 216         clk->rate_discrete = rate_discrete;
 217
 218 err:
 219         ph->xops->xfer_put(ph, t);
 220         return ret;
 221 }
 222
 223 static int
 224 scmi_clock_rate_get(const struct scmi_protocol_handle *ph,
 225                     u32 clk_id, u64 *value)
 226 {
 227         int ret;
 228         struct scmi_xfer *t;
 229
 230         ret = ph->xops->xfer_get_init(ph, CLOCK_RATE_GET,
 231                                       sizeof(__le32), sizeof(u64), &t);
 232         if (ret)
 233                 return ret;
 234
 235         put_unaligned_le32(clk_id, t->tx.buf);
 236
 237         ret = ph->xops->do_xfer(ph, t);
 238         if (!ret)
 239                 *value = get_unaligned_le64(t->rx.buf);
 240
 241         ph->xops->xfer_put(ph, t);
 242         return ret;
 243 }
 244
 245 static int scmi_clock_rate_set(const struct scmi_protocol_handle *ph,
 246                                u32 clk_id, u64 rate)
 247 {
 248         int ret;
 249         u32 flags = 0;
 250         struct scmi_xfer *t;
 251         struct scmi_clock_set_rate *cfg;
 252         struct clock_info *ci = ph->get_priv(ph);
 253
 254         ret = ph->xops->xfer_get_init(ph, CLOCK_RATE_SET, sizeof(*cfg), 0, &t);
 255         if (ret)
 256                 return ret;
 257
 258         if (ci->max_async_req &&
 259             atomic_inc_return(&ci->cur_async_req) < ci->max_async_req)
 260                 flags |= CLOCK_SET_ASYNC;
 261
 262         cfg = t->tx.buf;
 263         cfg->flags = cpu_to_le32(flags);
 264         cfg->id = cpu_to_le32(clk_id);
 265         cfg->value_low = cpu_to_le32(rate & 0xffffffff);
 266         cfg->value_high = cpu_to_le32(rate >> 32);
 267
 268         if (flags & CLOCK_SET_ASYNC)
 269                 ret = ph->xops->do_xfer_with_response(ph, t);
 270         else
 271                 ret = ph->xops->do_xfer(ph, t);
 272
 273         if (ci->max_async_req)
 274                 atomic_dec(&ci->cur_async_req);
 275
 276         ph->xops->xfer_put(ph, t);
 277         return ret;
 278 }
 279
 280 static int
 281 scmi_clock_config_set(const struct scmi_protocol_handle *ph, u32 clk_id,
 282                       u32 config, bool atomic)
 283 {
 284         int ret;
 285         struct scmi_xfer *t;
 286         struct scmi_clock_set_config *cfg;
 287
 288         ret = ph->xops->xfer_get_init(ph, CLOCK_CONFIG_SET,
 289                                       sizeof(*cfg), 0, &t);
 290         if (ret)
 291                 return ret;
 292
 293         t->hdr.poll_completion = atomic;
 294
 295         cfg = t->tx.buf;
 296         cfg->id = cpu_to_le32(clk_id);
 297         cfg->attributes = cpu_to_le32(config);
 298
 299         ret = ph->xops->do_xfer(ph, t);
 300
 301         ph->xops->xfer_put(ph, t);
 302         return ret;
 303 }
 304
 305 static int scmi_clock_enable(const struct scmi_protocol_handle *ph, u32 clk_id)
 306 {
 307         return scmi_clock_config_set(ph, clk_id, CLOCK_ENABLE, false);
 308 }
 309
 310 static int scmi_clock_disable(const struct scmi_protocol_handle *ph, u32 clk_id)
 311 {
 312         return scmi_clock_config_set(ph, clk_id, 0, false);
 313 }
 314
 315 static int scmi_clock_enable_atomic(const struct scmi_protocol_handle *ph,
 316                                     u32 clk_id)
 317 {
 318         return scmi_clock_config_set(ph, clk_id, CLOCK_ENABLE, true);
 319 }
 320
 321 static int scmi_clock_disable_atomic(const struct scmi_protocol_handle *ph,
 322                                      u32 clk_id)
 323 {
 324         return scmi_clock_config_set(ph, clk_id, 0, true);
 325 }
 326
 327 static int scmi_clock_count_get(const struct scmi_protocol_handle *ph)
 328 {
 329         struct clock_info *ci = ph->get_priv(ph);
 330
 331         return ci->num_clocks;
 332 }
 333
 334 static const struct scmi_clock_info *
 335 scmi_clock_info_get(const struct scmi_protocol_handle *ph, u32 clk_id)
 336 {
 337         struct clock_info *ci = ph->get_priv(ph);
 338         struct scmi_clock_info *clk = ci->clk + clk_id;
 339
 340         if (!clk->name[0])
 341                 return NULL;
 342
 343         return clk;
 344 }
 345
 346 static const struct scmi_clk_proto_ops clk_proto_ops = {
 347         .count_get = scmi_clock_count_get,
 348         .info_get = scmi_clock_info_get,
 349         .rate_get = scmi_clock_rate_get,
 350         .rate_set = scmi_clock_rate_set,
 351         .enable = scmi_clock_enable,
 352         .disable = scmi_clock_disable,
 353         .enable_atomic = scmi_clock_enable_atomic,
 354         .disable_atomic = scmi_clock_disable_atomic,
 355 };
 356
 357 static int scmi_clock_protocol_init(const struct scmi_protocol_handle *ph)
 358 {
 359         u32 version;
 360         int clkid, ret;
 361         struct clock_info *cinfo;
 362
 363         ph->xops->version_get(ph, &version);
 364
 365         dev_dbg(ph->dev, "Clock Version %d.%d\n",
 366                 PROTOCOL_REV_MAJOR(version), PROTOCOL_REV_MINOR(version));
 367
 368         cinfo = devm_kzalloc(ph->dev, sizeof(*cinfo), GFP_KERNEL);
 369         if (!cinfo)
 370                 return -ENOMEM;
 371
 372         scmi_clock_protocol_attributes_get(ph, cinfo);
 373
 374         cinfo->clk = devm_kcalloc(ph->dev, cinfo->num_clocks,
 375                                   sizeof(*cinfo->clk), GFP_KERNEL);
 376         if (!cinfo->clk)
 377                 return -ENOMEM;
 378
 379         for (clkid = 0; clkid < cinfo->num_clocks; clkid++) {
 380                 struct scmi_clock_info *clk = cinfo->clk + clkid;
 381
 382                 ret = scmi_clock_attributes_get(ph, clkid, clk);
 383                 if (!ret)
 384                         scmi_clock_describe_rates_get(ph, clkid, clk);
 385         }
 386
 387         cinfo->version = version;
 388         return ph->set_priv(ph, cinfo);
 389 }
 390
 391 static const struct scmi_protocol scmi_clock = {
 392         .id = SCMI_PROTOCOL_CLOCK,
 393         .owner = THIS_MODULE,
 394         .instance_init = &scmi_clock_protocol_init,
 395         .ops = &clk_proto_ops,
 396 };
 397
 398 DEFINE_SCMI_PROTOCOL_REGISTER_UNREGISTER(clock, scmi_clock)