drivers/clk/ti/dpll.c

   1 /*
   2  * OMAP DPLL clock support
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * Tero Kristo <t-kristo@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/clk-provider.h>
  20 #include <linux/slab.h>
  21 #include <linux/err.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/clk/ti.h>
  25 #include "clock.h"
  26
  27 #undef pr_fmt
  28 #define pr_fmt(fmt) "%s: " fmt, __func__
  29
  30 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
  31         defined(CONFIG_SOC_DRA7XX)
  32 static const struct clk_ops dpll_m4xen_ck_ops = {
  33         .enable         = &omap3_noncore_dpll_enable,
  34         .disable        = &omap3_noncore_dpll_disable,
  35         .recalc_rate    = &omap4_dpll_regm4xen_recalc,
  36         .round_rate     = &omap4_dpll_regm4xen_round_rate,
  37         .set_rate       = &omap3_noncore_dpll_set_rate,
  38         .set_parent     = &omap3_noncore_dpll_set_parent,
  39         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
  40         .determine_rate = &omap4_dpll_regm4xen_determine_rate,
  41         .get_parent     = &omap2_init_dpll_parent,
  42         .save_context   = &omap3_core_dpll_save_context,
  43         .restore_context = &omap3_core_dpll_restore_context,
  44 };
  45 #else
  46 static const struct clk_ops dpll_m4xen_ck_ops = {};
  47 #endif
  48
  49 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) || \
  50         defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) || \
  51         defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
  52 static const struct clk_ops dpll_core_ck_ops = {
  53         .recalc_rate    = &omap3_dpll_recalc,
  54         .get_parent     = &omap2_init_dpll_parent,
  55 };
  56
  57 static const struct clk_ops dpll_ck_ops = {
  58         .enable         = &omap3_noncore_dpll_enable,
  59         .disable        = &omap3_noncore_dpll_disable,
  60         .recalc_rate    = &omap3_dpll_recalc,
  61         .round_rate     = &omap2_dpll_round_rate,
  62         .set_rate       = &omap3_noncore_dpll_set_rate,
  63         .set_parent     = &omap3_noncore_dpll_set_parent,
  64         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
  65         .determine_rate = &omap3_noncore_dpll_determine_rate,
  66         .get_parent     = &omap2_init_dpll_parent,
  67         .save_context   = &omap3_noncore_dpll_save_context,
  68         .restore_context = &omap3_noncore_dpll_restore_context,
  69 };
  70
  71 static const struct clk_ops dpll_no_gate_ck_ops = {
  72         .recalc_rate    = &omap3_dpll_recalc,
  73         .get_parent     = &omap2_init_dpll_parent,
  74         .round_rate     = &omap2_dpll_round_rate,
  75         .set_rate       = &omap3_noncore_dpll_set_rate,
  76         .set_parent     = &omap3_noncore_dpll_set_parent,
  77         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
  78         .determine_rate = &omap3_noncore_dpll_determine_rate,
  79         .save_context   = &omap3_noncore_dpll_save_context,
  80         .restore_context = &omap3_noncore_dpll_restore_context
  81 };
  82 #else
  83 static const struct clk_ops dpll_core_ck_ops = {};
  84 static const struct clk_ops dpll_ck_ops = {};
  85 static const struct clk_ops dpll_no_gate_ck_ops = {};
  86 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {};
  87 #endif
  88
  89 #ifdef CONFIG_ARCH_OMAP2
  90 static const struct clk_ops omap2_dpll_core_ck_ops = {
  91         .get_parent     = &omap2_init_dpll_parent,
  92         .recalc_rate    = &omap2_dpllcore_recalc,
  93         .round_rate     = &omap2_dpll_round_rate,
  94         .set_rate       = &omap2_reprogram_dpllcore,
  95 };
  96 #else
  97 static const struct clk_ops omap2_dpll_core_ck_ops = {};
  98 #endif
  99
 100 #ifdef CONFIG_ARCH_OMAP3
 101 static const struct clk_ops omap3_dpll_core_ck_ops = {
 102         .get_parent     = &omap2_init_dpll_parent,
 103         .recalc_rate    = &omap3_dpll_recalc,
 104         .round_rate     = &omap2_dpll_round_rate,
 105 };
 106 #else
 107 static const struct clk_ops omap3_dpll_core_ck_ops = {};
 108 #endif
 109
 110 #ifdef CONFIG_ARCH_OMAP3
 111 static const struct clk_ops omap3_dpll_ck_ops = {
 112         .enable         = &omap3_noncore_dpll_enable,
 113         .disable        = &omap3_noncore_dpll_disable,
 114         .get_parent     = &omap2_init_dpll_parent,
 115         .recalc_rate    = &omap3_dpll_recalc,
 116         .set_rate       = &omap3_noncore_dpll_set_rate,
 117         .set_parent     = &omap3_noncore_dpll_set_parent,
 118         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
 119         .determine_rate = &omap3_noncore_dpll_determine_rate,
 120         .round_rate     = &omap2_dpll_round_rate,
 121 };
 122
 123 static const struct clk_ops omap3_dpll5_ck_ops = {
 124         .enable         = &omap3_noncore_dpll_enable,
 125         .disable        = &omap3_noncore_dpll_disable,
 126         .get_parent     = &omap2_init_dpll_parent,
 127         .recalc_rate    = &omap3_dpll_recalc,
 128         .set_rate       = &omap3_dpll5_set_rate,
 129         .set_parent     = &omap3_noncore_dpll_set_parent,
 130         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
 131         .determine_rate = &omap3_noncore_dpll_determine_rate,
 132         .round_rate     = &omap2_dpll_round_rate,
 133 };
 134
 135 static const struct clk_ops omap3_dpll_per_ck_ops = {
 136         .enable         = &omap3_noncore_dpll_enable,
 137         .disable        = &omap3_noncore_dpll_disable,
 138         .get_parent     = &omap2_init_dpll_parent,
 139         .recalc_rate    = &omap3_dpll_recalc,
 140         .set_rate       = &omap3_dpll4_set_rate,
 141         .set_parent     = &omap3_noncore_dpll_set_parent,
 142         .set_rate_and_parent    = &omap3_dpll4_set_rate_and_parent,
 143         .determine_rate = &omap3_noncore_dpll_determine_rate,
 144         .round_rate     = &omap2_dpll_round_rate,
 145 };
 146 #endif
 147
 148 static const struct clk_ops dpll_x2_ck_ops = {
 149         .recalc_rate    = &omap3_clkoutx2_recalc,
 150 };
 151
 152 /**
 153  * _register_dpll - low level registration of a DPLL clock
 154  * @user: pointer to the hardware clock definition for the clock
 155  * @node: device node for the clock
 156  *
 157  * Finalizes DPLL registration process. In case a failure (clk-ref or
 158  * clk-bypass is missing), the clock is added to retry list and
 159  * the initialization is retried on later stage.
 160  */
 161 static void __init _register_dpll(void *user,
 162                                   struct device_node *node)
 163 {
 164         struct clk_hw *hw = user;
 165         struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
 166         struct dpll_data *dd = clk_hw->dpll_data;
 167         const char *name;
 168         struct clk *clk;
 169         const struct clk_init_data *init = hw->init;
 170
 171         clk = of_clk_get(node, 0);
 172         if (IS_ERR(clk)) {
 173                 pr_debug("clk-ref missing for %pOFn, retry later\n",
 174                          node);
 175                 if (!ti_clk_retry_init(node, hw, _register_dpll))
 176                         return;
 177
 178                 goto cleanup;
 179         }
 180
 181         dd->clk_ref = __clk_get_hw(clk);
 182
 183         clk = of_clk_get(node, 1);
 184
 185         if (IS_ERR(clk)) {
 186                 pr_debug("clk-bypass missing for %pOFn, retry later\n",
 187                          node);
 188                 if (!ti_clk_retry_init(node, hw, _register_dpll))
 189                         return;
 190
 191                 goto cleanup;
 192         }
 193
 194         dd->clk_bypass = __clk_get_hw(clk);
 195
 196         /* register the clock */
 197         name = ti_dt_clk_name(node);
 198         clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
 199
 200         if (!IS_ERR(clk)) {
 201                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 202                 kfree(init->parent_names);
 203                 kfree(init);
 204                 return;
 205         }
 206
 207 cleanup:
 208         kfree(clk_hw->dpll_data);
 209         kfree(init->parent_names);
 210         kfree(init);
 211         kfree(clk_hw);
 212 }
 213
 214 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
 215         defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
 216         defined(CONFIG_SOC_AM43XX)
 217 /**
 218  * _register_dpll_x2 - Registers a DPLLx2 clock
 219  * @node: device node for this clock
 220  * @ops: clk_ops for this clock
 221  * @hw_ops: clk_hw_ops for this clock
 222  *
 223  * Initializes a DPLL x 2 clock from device tree data.
 224  */
 225 static void _register_dpll_x2(struct device_node *node,
 226                               const struct clk_ops *ops,
 227                               const struct clk_hw_omap_ops *hw_ops)
 228 {
 229         struct clk *clk;
 230         struct clk_init_data init = { NULL };
 231         struct clk_hw_omap *clk_hw;
 232         const char *name = ti_dt_clk_name(node);
 233         const char *parent_name;
 234
 235         parent_name = of_clk_get_parent_name(node, 0);
 236         if (!parent_name) {
 237                 pr_err("%pOFn must have parent\n", node);
 238                 return;
 239         }
 240
 241         clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
 242         if (!clk_hw)
 243                 return;
 244
 245         clk_hw->ops = hw_ops;
 246         clk_hw->hw.init = &init;
 247
 248         init.name = name;
 249         init.ops = ops;
 250         init.parent_names = &parent_name;
 251         init.num_parents = 1;
 252
 253 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
 254         defined(CONFIG_SOC_DRA7XX)
 255         if (hw_ops == &clkhwops_omap4_dpllmx) {
 256                 int ret;
 257
 258                 /* Check if register defined, if not, drop hw-ops */
 259                 ret = of_property_count_elems_of_size(node, "reg", 1);
 260                 if (ret <= 0) {
 261                         clk_hw->ops = NULL;
 262                 } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) {
 263                         kfree(clk_hw);
 264                         return;
 265                 }
 266         }
 267 #endif
 268
 269         /* register the clock */
 270         clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
 271
 272         if (IS_ERR(clk))
 273                 kfree(clk_hw);
 274         else
 275                 of_clk_add_provider(node, of_clk_src_simple_get, clk);
 276 }
 277 #endif
 278
 279 /**
 280  * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
 281  * @node: device node containing the DPLL info
 282  * @ops: ops for the DPLL
 283  * @ddt: DPLL data template to use
 284  *
 285  * Initializes a DPLL clock from device tree data.
 286  */
 287 static void __init of_ti_dpll_setup(struct device_node *node,
 288                                     const struct clk_ops *ops,
 289                                     const struct dpll_data *ddt)
 290 {
 291         struct clk_hw_omap *clk_hw = NULL;
 292         struct clk_init_data *init = NULL;
 293         const char **parent_names = NULL;
 294         struct dpll_data *dd = NULL;
 295         int ssc_clk_index;
 296         u8 dpll_mode = 0;
 297         u32 min_div;
 298
 299         dd = kmemdup(ddt, sizeof(*dd), GFP_KERNEL);
 300         clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
 301         init = kzalloc(sizeof(*init), GFP_KERNEL);
 302         if (!dd || !clk_hw || !init)
 303                 goto cleanup;
 304
 305         clk_hw->dpll_data = dd;
 306         clk_hw->ops = &clkhwops_omap3_dpll;
 307         clk_hw->hw.init = init;
 308
 309         init->name = ti_dt_clk_name(node);
 310         init->ops = ops;
 311
 312         init->num_parents = of_clk_get_parent_count(node);
 313         if (!init->num_parents) {
 314                 pr_err("%pOFn must have parent(s)\n", node);
 315                 goto cleanup;
 316         }
 317
 318         parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL);
 319         if (!parent_names)
 320                 goto cleanup;
 321
 322         of_clk_parent_fill(node, parent_names, init->num_parents);
 323
 324         init->parent_names = parent_names;
 325
 326         if (ti_clk_get_reg_addr(node, 0, &dd->control_reg))
 327                 goto cleanup;
 328
 329         /*
 330          * Special case for OMAP2 DPLL, register order is different due to
 331          * missing idlest_reg, also clkhwops is different. Detected from
 332          * missing idlest_mask.
 333          */
 334         if (!dd->idlest_mask) {
 335                 if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg))
 336                         goto cleanup;
 337 #ifdef CONFIG_ARCH_OMAP2
 338                 clk_hw->ops = &clkhwops_omap2xxx_dpll;
 339                 omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
 340 #endif
 341         } else {
 342                 if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg))
 343                         goto cleanup;
 344
 345                 if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg))
 346                         goto cleanup;
 347         }
 348
 349         if (dd->autoidle_mask) {
 350                 if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg))
 351                         goto cleanup;
 352
 353                 ssc_clk_index = 4;
 354         } else {
 355                 ssc_clk_index = 3;
 356         }
 357
 358         if (dd->ssc_deltam_int_mask && dd->ssc_deltam_frac_mask &&
 359             dd->ssc_modfreq_mant_mask && dd->ssc_modfreq_exp_mask) {
 360                 if (ti_clk_get_reg_addr(node, ssc_clk_index++,
 361                                         &dd->ssc_deltam_reg))
 362                         goto cleanup;
 363
 364                 if (ti_clk_get_reg_addr(node, ssc_clk_index++,
 365                                         &dd->ssc_modfreq_reg))
 366                         goto cleanup;
 367
 368                 of_property_read_u32(node, "ti,ssc-modfreq-hz",
 369                                      &dd->ssc_modfreq);
 370                 of_property_read_u32(node, "ti,ssc-deltam", &dd->ssc_deltam);
 371                 dd->ssc_downspread =
 372                         of_property_read_bool(node, "ti,ssc-downspread");
 373         }
 374
 375         if (of_property_read_bool(node, "ti,low-power-stop"))
 376                 dpll_mode |= 1 << DPLL_LOW_POWER_STOP;
 377
 378         if (of_property_read_bool(node, "ti,low-power-bypass"))
 379                 dpll_mode |= 1 << DPLL_LOW_POWER_BYPASS;
 380
 381         if (of_property_read_bool(node, "ti,lock"))
 382                 dpll_mode |= 1 << DPLL_LOCKED;
 383
 384         if (!of_property_read_u32(node, "ti,min-div", &min_div) &&
 385             min_div > dd->min_divider)
 386                 dd->min_divider = min_div;
 387
 388         if (dpll_mode)
 389                 dd->modes = dpll_mode;
 390
 391         _register_dpll(&clk_hw->hw, node);
 392         return;
 393
 394 cleanup:
 395         kfree(dd);
 396         kfree(parent_names);
 397         kfree(init);
 398         kfree(clk_hw);
 399 }
 400
 401 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
 402         defined(CONFIG_SOC_DRA7XX)
 403 static void __init of_ti_omap4_dpll_x2_setup(struct device_node *node)
 404 {
 405         _register_dpll_x2(node, &dpll_x2_ck_ops, &clkhwops_omap4_dpllmx);
 406 }
 407 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
 408                of_ti_omap4_dpll_x2_setup);
 409 #endif
 410
 411 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 412 static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
 413 {
 414         _register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
 415 }
 416 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
 417                of_ti_am3_dpll_x2_setup);
 418 #endif
 419
 420 #ifdef CONFIG_ARCH_OMAP3
 421 static void __init of_ti_omap3_dpll_setup(struct device_node *node)
 422 {
 423         const struct dpll_data dd = {
 424                 .idlest_mask = 0x1,
 425                 .enable_mask = 0x7,
 426                 .autoidle_mask = 0x7,
 427                 .mult_mask = 0x7ff << 8,
 428                 .div1_mask = 0x7f,
 429                 .max_multiplier = 2047,
 430                 .max_divider = 128,
 431                 .min_divider = 1,
 432                 .freqsel_mask = 0xf0,
 433                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 434         };
 435
 436         if ((of_machine_is_compatible("ti,omap3630") ||
 437              of_machine_is_compatible("ti,omap36xx")) &&
 438              of_node_name_eq(node, "dpll5_ck"))
 439                 of_ti_dpll_setup(node, &omap3_dpll5_ck_ops, &dd);
 440         else
 441                 of_ti_dpll_setup(node, &omap3_dpll_ck_ops, &dd);
 442 }
 443 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
 444                of_ti_omap3_dpll_setup);
 445
 446 static void __init of_ti_omap3_core_dpll_setup(struct device_node *node)
 447 {
 448         const struct dpll_data dd = {
 449                 .idlest_mask = 0x1,
 450                 .enable_mask = 0x7,
 451                 .autoidle_mask = 0x7,
 452                 .mult_mask = 0x7ff << 16,
 453                 .div1_mask = 0x7f << 8,
 454                 .max_multiplier = 2047,
 455                 .max_divider = 128,
 456                 .min_divider = 1,
 457                 .freqsel_mask = 0xf0,
 458         };
 459
 460         of_ti_dpll_setup(node, &omap3_dpll_core_ck_ops, &dd);
 461 }
 462 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
 463                of_ti_omap3_core_dpll_setup);
 464
 465 static void __init of_ti_omap3_per_dpll_setup(struct device_node *node)
 466 {
 467         const struct dpll_data dd = {
 468                 .idlest_mask = 0x1 << 1,
 469                 .enable_mask = 0x7 << 16,
 470                 .autoidle_mask = 0x7 << 3,
 471                 .mult_mask = 0x7ff << 8,
 472                 .div1_mask = 0x7f,
 473                 .max_multiplier = 2047,
 474                 .max_divider = 128,
 475                 .min_divider = 1,
 476                 .freqsel_mask = 0xf00000,
 477                 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 478         };
 479
 480         of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
 481 }
 482 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
 483                of_ti_omap3_per_dpll_setup);
 484
 485 static void __init of_ti_omap3_per_jtype_dpll_setup(struct device_node *node)
 486 {
 487         const struct dpll_data dd = {
 488                 .idlest_mask = 0x1 << 1,
 489                 .enable_mask = 0x7 << 16,
 490                 .autoidle_mask = 0x7 << 3,
 491                 .mult_mask = 0xfff << 8,
 492                 .div1_mask = 0x7f,
 493                 .max_multiplier = 4095,
 494                 .max_divider = 128,
 495                 .min_divider = 1,
 496                 .sddiv_mask = 0xff << 24,
 497                 .dco_mask = 0xe << 20,
 498                 .flags = DPLL_J_TYPE,
 499                 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 500         };
 501
 502         of_ti_dpll_setup(node, &omap3_dpll_per_ck_ops, &dd);
 503 }
 504 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
 505                of_ti_omap3_per_jtype_dpll_setup);
 506 #endif
 507
 508 static void __init of_ti_omap4_dpll_setup(struct device_node *node)
 509 {
 510         const struct dpll_data dd = {
 511                 .idlest_mask = 0x1,
 512                 .enable_mask = 0x7,
 513                 .autoidle_mask = 0x7,
 514                 .mult_mask = 0x7ff << 8,
 515                 .div1_mask = 0x7f,
 516                 .max_multiplier = 2047,
 517                 .max_divider = 128,
 518                 .min_divider = 1,
 519                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 520         };
 521
 522         of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
 523 }
 524 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
 525                of_ti_omap4_dpll_setup);
 526
 527 static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node)
 528 {
 529         const struct dpll_data dd = {
 530                 .idlest_mask = 0x1,
 531                 .enable_mask = 0x7,
 532                 .autoidle_mask = 0x7,
 533                 .mult_mask = 0x7ff << 8,
 534                 .div1_mask = 0x7f,
 535                 .max_multiplier = 2047,
 536                 .max_divider = 128,
 537                 .dcc_mask = BIT(22),
 538                 .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */
 539                 .min_divider = 1,
 540                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 541         };
 542
 543         of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
 544 }
 545 CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
 546                of_ti_omap5_mpu_dpll_setup);
 547
 548 static void __init of_ti_omap4_core_dpll_setup(struct device_node *node)
 549 {
 550         const struct dpll_data dd = {
 551                 .idlest_mask = 0x1,
 552                 .enable_mask = 0x7,
 553                 .autoidle_mask = 0x7,
 554                 .mult_mask = 0x7ff << 8,
 555                 .div1_mask = 0x7f,
 556                 .max_multiplier = 2047,
 557                 .max_divider = 128,
 558                 .min_divider = 1,
 559                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 560         };
 561
 562         of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
 563 }
 564 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
 565                of_ti_omap4_core_dpll_setup);
 566
 567 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
 568         defined(CONFIG_SOC_DRA7XX)
 569 static void __init of_ti_omap4_m4xen_dpll_setup(struct device_node *node)
 570 {
 571         const struct dpll_data dd = {
 572                 .idlest_mask = 0x1,
 573                 .enable_mask = 0x7,
 574                 .autoidle_mask = 0x7,
 575                 .mult_mask = 0x7ff << 8,
 576                 .div1_mask = 0x7f,
 577                 .max_multiplier = 2047,
 578                 .max_divider = 128,
 579                 .min_divider = 1,
 580                 .m4xen_mask = 0x800,
 581                 .lpmode_mask = 1 << 10,
 582                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 583         };
 584
 585         of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
 586 }
 587 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
 588                of_ti_omap4_m4xen_dpll_setup);
 589
 590 static void __init of_ti_omap4_jtype_dpll_setup(struct device_node *node)
 591 {
 592         const struct dpll_data dd = {
 593                 .idlest_mask = 0x1,
 594                 .enable_mask = 0x7,
 595                 .autoidle_mask = 0x7,
 596                 .mult_mask = 0xfff << 8,
 597                 .div1_mask = 0xff,
 598                 .max_multiplier = 4095,
 599                 .max_divider = 256,
 600                 .min_divider = 1,
 601                 .sddiv_mask = 0xff << 24,
 602                 .flags = DPLL_J_TYPE,
 603                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 604         };
 605
 606         of_ti_dpll_setup(node, &dpll_m4xen_ck_ops, &dd);
 607 }
 608 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
 609                of_ti_omap4_jtype_dpll_setup);
 610 #endif
 611
 612 static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
 613 {
 614         const struct dpll_data dd = {
 615                 .idlest_mask = 0x1,
 616                 .enable_mask = 0x7,
 617                 .ssc_enable_mask = 0x1 << 12,
 618                 .ssc_downspread_mask = 0x1 << 14,
 619                 .mult_mask = 0x7ff << 8,
 620                 .div1_mask = 0x7f,
 621                 .ssc_deltam_int_mask = 0x3 << 18,
 622                 .ssc_deltam_frac_mask = 0x3ffff,
 623                 .ssc_modfreq_mant_mask = 0x7f,
 624                 .ssc_modfreq_exp_mask = 0x7 << 8,
 625                 .max_multiplier = 2047,
 626                 .max_divider = 128,
 627                 .min_divider = 1,
 628                 .max_rate = 1000000000,
 629                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 630         };
 631
 632         of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
 633 }
 634 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
 635                of_ti_am3_no_gate_dpll_setup);
 636
 637 static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
 638 {
 639         const struct dpll_data dd = {
 640                 .idlest_mask = 0x1,
 641                 .enable_mask = 0x7,
 642                 .mult_mask = 0x7ff << 8,
 643                 .div1_mask = 0x7f,
 644                 .max_multiplier = 4095,
 645                 .max_divider = 256,
 646                 .min_divider = 2,
 647                 .flags = DPLL_J_TYPE,
 648                 .max_rate = 2000000000,
 649                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 650         };
 651
 652         of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
 653 }
 654 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
 655                of_ti_am3_jtype_dpll_setup);
 656
 657 static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
 658 {
 659         const struct dpll_data dd = {
 660                 .idlest_mask = 0x1,
 661                 .enable_mask = 0x7,
 662                 .mult_mask = 0x7ff << 8,
 663                 .div1_mask = 0x7f,
 664                 .max_multiplier = 2047,
 665                 .max_divider = 128,
 666                 .min_divider = 1,
 667                 .max_rate = 2000000000,
 668                 .flags = DPLL_J_TYPE,
 669                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 670         };
 671
 672         of_ti_dpll_setup(node, &dpll_no_gate_ck_ops, &dd);
 673 }
 674 CLK_OF_DECLARE(ti_am3_no_gate_jtype_dpll_clock,
 675                "ti,am3-dpll-no-gate-j-type-clock",
 676                of_ti_am3_no_gate_jtype_dpll_setup);
 677
 678 static void __init of_ti_am3_dpll_setup(struct device_node *node)
 679 {
 680         const struct dpll_data dd = {
 681                 .idlest_mask = 0x1,
 682                 .enable_mask = 0x7,
 683                 .ssc_enable_mask = 0x1 << 12,
 684                 .ssc_downspread_mask = 0x1 << 14,
 685                 .mult_mask = 0x7ff << 8,
 686                 .div1_mask = 0x7f,
 687                 .ssc_deltam_int_mask = 0x3 << 18,
 688                 .ssc_deltam_frac_mask = 0x3ffff,
 689                 .ssc_modfreq_mant_mask = 0x7f,
 690                 .ssc_modfreq_exp_mask = 0x7 << 8,
 691                 .max_multiplier = 2047,
 692                 .max_divider = 128,
 693                 .min_divider = 1,
 694                 .max_rate = 1000000000,
 695                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 696         };
 697
 698         of_ti_dpll_setup(node, &dpll_ck_ops, &dd);
 699 }
 700 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
 701
 702 static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
 703 {
 704         const struct dpll_data dd = {
 705                 .idlest_mask = 0x1,
 706                 .enable_mask = 0x7,
 707                 .mult_mask = 0x7ff << 8,
 708                 .div1_mask = 0x7f,
 709                 .max_multiplier = 2047,
 710                 .max_divider = 128,
 711                 .min_divider = 1,
 712                 .max_rate = 1000000000,
 713                 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 714         };
 715
 716         of_ti_dpll_setup(node, &dpll_core_ck_ops, &dd);
 717 }
 718 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
 719                of_ti_am3_core_dpll_setup);
 720
 721 static void __init of_ti_omap2_core_dpll_setup(struct device_node *node)
 722 {
 723         const struct dpll_data dd = {
 724                 .enable_mask = 0x3,
 725                 .mult_mask = 0x3ff << 12,
 726                 .div1_mask = 0xf << 8,
 727                 .max_divider = 16,
 728                 .min_divider = 1,
 729         };
 730
 731         of_ti_dpll_setup(node, &omap2_dpll_core_ck_ops, &dd);
 732 }
 733 CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",
 734                of_ti_omap2_core_dpll_setup);