2 * Copyright (c) 2016 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * Based on ccu-sun8i-h3.c by Maxime Ripard.
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk-provider.h>
20 #include <linux/of_address.h>
22 #include "ccu_common.h"
23 #include "ccu_reset.h"
34 #include "ccu_phase.h"
37 #include "ccu-sun6i-a31.h"
39 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
49 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
50 * the base (2x, 4x and 8x), and one variable divider (the one true
53 * With sigma-delta modulation for fractional-N on the audio PLL,
54 * we have to use specific dividers. This means the variable divider
55 * can no longer be used, as the audio codec requests the exact clock
56 * rates we support through this mechanism. So we now hard code the
57 * variable divider to 1. This means the clock rates will no longer
58 * match the clock names.
60 #define SUN6I_A31_PLL_AUDIO_REG 0x008
62 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
63 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
64 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
67 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
71 pll_audio_sdm_table, BIT(24),
77 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
81 BIT(24), /* frac enable */
82 BIT(25), /* frac select */
83 270000000, /* frac rate 0 */
84 297000000, /* frac rate 1 */
89 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
93 BIT(24), /* frac enable */
94 BIT(25), /* frac select */
95 270000000, /* frac rate 0 */
96 297000000, /* frac rate 1 */
101 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
108 CLK_SET_RATE_UNGATE);
110 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
117 CLK_SET_RATE_UNGATE);
119 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
123 BIT(24), /* frac enable */
124 BIT(25), /* frac select */
125 270000000, /* frac rate 0 */
126 297000000, /* frac rate 1 */
129 CLK_SET_RATE_UNGATE);
131 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
135 BIT(24), /* frac enable */
136 BIT(25), /* frac select */
137 270000000, /* frac rate 0 */
138 297000000, /* frac rate 1 */
141 CLK_SET_RATE_UNGATE);
144 * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
146 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
147 * integer / fractional clock with switchable multipliers and dividers.
148 * This is not supported here. We hardcode the PLL to MIPI mode.
150 #define SUN6I_A31_PLL_MIPI_REG 0x040
152 static const char * const pll_mipi_parents[] = { "pll-video0", "pll-video1" };
153 static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi",
154 pll_mipi_parents, 0x040,
159 BIT(31) | BIT(23) | BIT(22), /* gate */
161 CLK_SET_RATE_UNGATE);
163 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll9_clk, "pll9",
167 BIT(24), /* frac enable */
168 BIT(25), /* frac select */
169 270000000, /* frac rate 0 */
170 297000000, /* frac rate 1 */
173 CLK_SET_RATE_UNGATE);
175 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll10_clk, "pll10",
179 BIT(24), /* frac enable */
180 BIT(25), /* frac select */
181 270000000, /* frac rate 0 */
182 297000000, /* frac rate 1 */
185 CLK_SET_RATE_UNGATE);
187 static const char * const cpux_parents[] = { "osc32k", "osc24M",
188 "pll-cpu", "pll-cpu" };
189 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpux_parents,
190 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
192 static struct clk_div_table axi_div_table[] = {
193 { .val = 0, .div = 1 },
194 { .val = 1, .div = 2 },
195 { .val = 2, .div = 3 },
196 { .val = 3, .div = 4 },
197 { .val = 4, .div = 4 },
198 { .val = 5, .div = 4 },
199 { .val = 6, .div = 4 },
200 { .val = 7, .div = 4 },
204 static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu",
205 0x050, 0, 3, axi_div_table, 0);
207 #define SUN6I_A31_AHB1_REG 0x054
209 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
210 "axi", "pll-periph" };
211 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
212 { .index = 3, .shift = 6, .width = 2 },
215 static struct ccu_div ahb1_clk = {
216 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
222 .var_predivs = ahb1_predivs,
223 .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
228 .features = CCU_FEATURE_VARIABLE_PREDIV,
229 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
236 static struct clk_div_table apb1_div_table[] = {
237 { .val = 0, .div = 2 },
238 { .val = 1, .div = 2 },
239 { .val = 2, .div = 4 },
240 { .val = 3, .div = 8 },
244 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
245 0x054, 8, 2, apb1_div_table, 0);
247 static const char * const apb2_parents[] = { "osc32k", "osc24M",
248 "pll-periph", "pll-periph" };
249 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
255 static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1",
257 static SUNXI_CCU_GATE(ahb1_ss_clk, "ahb1-ss", "ahb1",
259 static SUNXI_CCU_GATE(ahb1_dma_clk, "ahb1-dma", "ahb1",
261 static SUNXI_CCU_GATE(ahb1_mmc0_clk, "ahb1-mmc0", "ahb1",
263 static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1",
265 static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1",
267 static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1",
269 static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1",
271 static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1",
273 static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1",
275 static SUNXI_CCU_GATE(ahb1_emac_clk, "ahb1-emac", "ahb1",
277 static SUNXI_CCU_GATE(ahb1_ts_clk, "ahb1-ts", "ahb1",
279 static SUNXI_CCU_GATE(ahb1_hstimer_clk, "ahb1-hstimer", "ahb1",
281 static SUNXI_CCU_GATE(ahb1_spi0_clk, "ahb1-spi0", "ahb1",
283 static SUNXI_CCU_GATE(ahb1_spi1_clk, "ahb1-spi1", "ahb1",
285 static SUNXI_CCU_GATE(ahb1_spi2_clk, "ahb1-spi2", "ahb1",
287 static SUNXI_CCU_GATE(ahb1_spi3_clk, "ahb1-spi3", "ahb1",
289 static SUNXI_CCU_GATE(ahb1_otg_clk, "ahb1-otg", "ahb1",
291 static SUNXI_CCU_GATE(ahb1_ehci0_clk, "ahb1-ehci0", "ahb1",
293 static SUNXI_CCU_GATE(ahb1_ehci1_clk, "ahb1-ehci1", "ahb1",
295 static SUNXI_CCU_GATE(ahb1_ohci0_clk, "ahb1-ohci0", "ahb1",
297 static SUNXI_CCU_GATE(ahb1_ohci1_clk, "ahb1-ohci1", "ahb1",
299 static SUNXI_CCU_GATE(ahb1_ohci2_clk, "ahb1-ohci2", "ahb1",
302 static SUNXI_CCU_GATE(ahb1_ve_clk, "ahb1-ve", "ahb1",
304 static SUNXI_CCU_GATE(ahb1_lcd0_clk, "ahb1-lcd0", "ahb1",
306 static SUNXI_CCU_GATE(ahb1_lcd1_clk, "ahb1-lcd1", "ahb1",
308 static SUNXI_CCU_GATE(ahb1_csi_clk, "ahb1-csi", "ahb1",
310 static SUNXI_CCU_GATE(ahb1_hdmi_clk, "ahb1-hdmi", "ahb1",
312 static SUNXI_CCU_GATE(ahb1_be0_clk, "ahb1-be0", "ahb1",
314 static SUNXI_CCU_GATE(ahb1_be1_clk, "ahb1-be1", "ahb1",
316 static SUNXI_CCU_GATE(ahb1_fe0_clk, "ahb1-fe0", "ahb1",
318 static SUNXI_CCU_GATE(ahb1_fe1_clk, "ahb1-fe1", "ahb1",
320 static SUNXI_CCU_GATE(ahb1_mp_clk, "ahb1-mp", "ahb1",
322 static SUNXI_CCU_GATE(ahb1_gpu_clk, "ahb1-gpu", "ahb1",
324 static SUNXI_CCU_GATE(ahb1_deu0_clk, "ahb1-deu0", "ahb1",
326 static SUNXI_CCU_GATE(ahb1_deu1_clk, "ahb1-deu1", "ahb1",
328 static SUNXI_CCU_GATE(ahb1_drc0_clk, "ahb1-drc0", "ahb1",
330 static SUNXI_CCU_GATE(ahb1_drc1_clk, "ahb1-drc1", "ahb1",
333 static SUNXI_CCU_GATE(apb1_codec_clk, "apb1-codec", "apb1",
335 static SUNXI_CCU_GATE(apb1_spdif_clk, "apb1-spdif", "apb1",
337 static SUNXI_CCU_GATE(apb1_digital_mic_clk, "apb1-digital-mic", "apb1",
339 static SUNXI_CCU_GATE(apb1_pio_clk, "apb1-pio", "apb1",
341 static SUNXI_CCU_GATE(apb1_daudio0_clk, "apb1-daudio0", "apb1",
343 static SUNXI_CCU_GATE(apb1_daudio1_clk, "apb1-daudio1", "apb1",
346 static SUNXI_CCU_GATE(apb2_i2c0_clk, "apb2-i2c0", "apb2",
348 static SUNXI_CCU_GATE(apb2_i2c1_clk, "apb2-i2c1", "apb2",
350 static SUNXI_CCU_GATE(apb2_i2c2_clk, "apb2-i2c2", "apb2",
352 static SUNXI_CCU_GATE(apb2_i2c3_clk, "apb2-i2c3", "apb2",
354 static SUNXI_CCU_GATE(apb2_uart0_clk, "apb2-uart0", "apb2",
356 static SUNXI_CCU_GATE(apb2_uart1_clk, "apb2-uart1", "apb2",
358 static SUNXI_CCU_GATE(apb2_uart2_clk, "apb2-uart2", "apb2",
360 static SUNXI_CCU_GATE(apb2_uart3_clk, "apb2-uart3", "apb2",
362 static SUNXI_CCU_GATE(apb2_uart4_clk, "apb2-uart4", "apb2",
364 static SUNXI_CCU_GATE(apb2_uart5_clk, "apb2-uart5", "apb2",
367 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
368 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", mod0_default_parents,
376 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", mod0_default_parents,
384 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents,
392 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
394 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
397 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents,
405 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
407 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
410 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents,
418 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
420 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
423 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents,
431 static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3",
433 static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3",
436 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
443 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
450 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
457 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
463 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
470 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
477 static const char * const daudio_parents[] = { "pll-audio-8x", "pll-audio-4x",
478 "pll-audio-2x", "pll-audio" };
479 static SUNXI_CCU_MUX_WITH_GATE(daudio0_clk, "daudio0", daudio_parents,
480 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
481 static SUNXI_CCU_MUX_WITH_GATE(daudio1_clk, "daudio1", daudio_parents,
482 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
484 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", daudio_parents,
485 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
487 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
489 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
491 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
493 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
495 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M",
497 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M",
500 /* TODO emac clk not supported yet */
502 static const char * const dram_parents[] = { "pll-ddr", "pll-periph" };
503 static SUNXI_CCU_MP_WITH_MUX_GATE(mdfs_clk, "mdfs", dram_parents, 0x0f0,
510 static SUNXI_CCU_M_WITH_MUX(sdram0_clk, "sdram0", dram_parents,
511 0x0f4, 0, 4, 4, 1, CLK_IS_CRITICAL);
512 static SUNXI_CCU_M_WITH_MUX(sdram1_clk, "sdram1", dram_parents,
513 0x0f4, 8, 4, 12, 1, CLK_IS_CRITICAL);
515 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "mdfs",
517 static SUNXI_CCU_GATE(dram_csi_isp_clk, "dram-csi-isp", "mdfs",
519 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "mdfs",
521 static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "mdfs",
523 static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "mdfs",
525 static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "mdfs",
527 static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "mdfs",
529 static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "mdfs",
531 static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "mdfs",
533 static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "mdfs",
535 static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "mdfs",
537 static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "mdfs",
540 static const char * const de_parents[] = { "pll-video0", "pll-video1",
541 "pll-periph-2x", "pll-gpu",
543 static SUNXI_CCU_M_WITH_MUX_GATE(be0_clk, "be0", de_parents,
544 0x104, 0, 4, 24, 3, BIT(31), 0);
545 static SUNXI_CCU_M_WITH_MUX_GATE(be1_clk, "be1", de_parents,
546 0x108, 0, 4, 24, 3, BIT(31), 0);
547 static SUNXI_CCU_M_WITH_MUX_GATE(fe0_clk, "fe0", de_parents,
548 0x10c, 0, 4, 24, 3, BIT(31), 0);
549 static SUNXI_CCU_M_WITH_MUX_GATE(fe1_clk, "fe1", de_parents,
550 0x110, 0, 4, 24, 3, BIT(31), 0);
552 static const char * const mp_parents[] = { "pll-video0", "pll-video1",
554 static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", mp_parents,
555 0x114, 0, 4, 24, 3, BIT(31), 0);
557 static const char * const lcd_ch0_parents[] = { "pll-video0", "pll-video1",
559 "pll-video1-2x", "pll-mipi" };
560 static SUNXI_CCU_MUX_WITH_GATE(lcd0_ch0_clk, "lcd0-ch0", lcd_ch0_parents,
561 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
562 static SUNXI_CCU_MUX_WITH_GATE(lcd1_ch0_clk, "lcd1-ch0", lcd_ch0_parents,
563 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
565 static const char * const lcd_ch1_parents[] = { "pll-video0", "pll-video1",
568 static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents,
569 0x12c, 0, 4, 24, 3, BIT(31),
570 CLK_SET_RATE_PARENT);
571 static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,
572 0x130, 0, 4, 24, 3, BIT(31),
573 CLK_SET_RATE_PARENT);
575 static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",
576 "pll9", "pll10", "pll-mipi",
578 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_sclk_clk, "csi0-sclk", csi_sclk_parents,
579 0x134, 16, 4, 24, 3, BIT(31), 0);
581 static const char * const csi_mclk_parents[] = { "pll-video0", "pll-video1",
583 static const u8 csi_mclk_table[] = { 0, 1, 5 };
584 static struct ccu_div csi0_mclk_clk = {
586 .div = _SUNXI_CCU_DIV(0, 4),
587 .mux = _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table),
590 .hw.init = CLK_HW_INIT_PARENTS("csi0-mclk",
597 static struct ccu_div csi1_mclk_clk = {
599 .div = _SUNXI_CCU_DIV(0, 4),
600 .mux = _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table),
603 .hw.init = CLK_HW_INIT_PARENTS("csi1-mclk",
610 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
611 0x13c, 16, 3, BIT(31), 0);
613 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
614 0x140, BIT(31), CLK_SET_RATE_PARENT);
615 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
617 static SUNXI_CCU_GATE(digital_mic_clk, "digital-mic", "pll-audio",
618 0x148, BIT(31), CLK_SET_RATE_PARENT);
620 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents,
621 0x150, 0, 4, 24, 2, BIT(31),
622 CLK_SET_RATE_PARENT);
624 static SUNXI_CCU_GATE(hdmi_ddc_clk, "ddc", "osc24M", 0x150, BIT(30), 0);
626 static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
628 static const char * const mbus_parents[] = { "osc24M", "pll-periph",
630 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus0_clk, "mbus0", mbus_parents, 0x15c,
637 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus1_clk, "mbus1", mbus_parents, 0x160,
644 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", lcd_ch1_parents,
645 0x168, 16, 3, 24, 2, BIT(31),
646 CLK_SET_RATE_PARENT);
647 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_dphy_clk, "mipi-dsi-dphy",
648 lcd_ch1_parents, 0x168, 0, 3, 8, 2,
649 BIT(15), CLK_SET_RATE_PARENT);
650 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_dphy_clk, "mipi-csi-dphy",
651 lcd_ch1_parents, 0x16c, 0, 3, 8, 2,
654 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc0_clk, "iep-drc0", de_parents,
655 0x180, 0, 3, 24, 2, BIT(31), 0);
656 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc1_clk, "iep-drc1", de_parents,
657 0x184, 0, 3, 24, 2, BIT(31), 0);
658 static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu0_clk, "iep-deu0", de_parents,
659 0x188, 0, 3, 24, 2, BIT(31), 0);
660 static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu1_clk, "iep-deu1", de_parents,
661 0x18c, 0, 3, 24, 2, BIT(31), 0);
663 static const char * const gpu_parents[] = { "pll-gpu", "pll-periph-2x",
664 "pll-video0", "pll-video1",
666 static const struct ccu_mux_fixed_prediv gpu_predivs[] = {
667 { .index = 1, .div = 3, },
670 static struct ccu_div gpu_core_clk = {
672 .div = _SUNXI_CCU_DIV(0, 3),
676 .fixed_predivs = gpu_predivs,
677 .n_predivs = ARRAY_SIZE(gpu_predivs),
681 .features = CCU_FEATURE_FIXED_PREDIV,
682 .hw.init = CLK_HW_INIT_PARENTS("gpu-core",
689 static struct ccu_div gpu_memory_clk = {
691 .div = _SUNXI_CCU_DIV(0, 3),
695 .fixed_predivs = gpu_predivs,
696 .n_predivs = ARRAY_SIZE(gpu_predivs),
700 .features = CCU_FEATURE_FIXED_PREDIV,
701 .hw.init = CLK_HW_INIT_PARENTS("gpu-memory",
708 static struct ccu_div gpu_hyd_clk = {
710 .div = _SUNXI_CCU_DIV(0, 3),
714 .fixed_predivs = gpu_predivs,
715 .n_predivs = ARRAY_SIZE(gpu_predivs),
719 .features = CCU_FEATURE_FIXED_PREDIV,
720 .hw.init = CLK_HW_INIT_PARENTS("gpu-hyd",
727 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", mod0_default_parents, 0x1b0,
733 static SUNXI_CCU_M_WITH_MUX_GATE(trace_clk, "trace", mod0_default_parents,
740 static const char * const clk_out_parents[] = { "osc24M", "osc32k", "osc24M",
742 static const u8 clk_out_table[] = { 0, 1, 2, 11, 13 };
744 static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
745 { .index = 0, .div = 750, },
746 { .index = 3, .div = 4, },
747 { .index = 4, .div = 4, },
750 static struct ccu_mp out_a_clk = {
752 .m = _SUNXI_CCU_DIV(8, 5),
753 .p = _SUNXI_CCU_DIV(20, 2),
757 .table = clk_out_table,
758 .fixed_predivs = clk_out_predivs,
759 .n_predivs = ARRAY_SIZE(clk_out_predivs),
763 .features = CCU_FEATURE_FIXED_PREDIV,
764 .hw.init = CLK_HW_INIT_PARENTS("out-a",
771 static struct ccu_mp out_b_clk = {
773 .m = _SUNXI_CCU_DIV(8, 5),
774 .p = _SUNXI_CCU_DIV(20, 2),
778 .table = clk_out_table,
779 .fixed_predivs = clk_out_predivs,
780 .n_predivs = ARRAY_SIZE(clk_out_predivs),
784 .features = CCU_FEATURE_FIXED_PREDIV,
785 .hw.init = CLK_HW_INIT_PARENTS("out-b",
792 static struct ccu_mp out_c_clk = {
794 .m = _SUNXI_CCU_DIV(8, 5),
795 .p = _SUNXI_CCU_DIV(20, 2),
799 .table = clk_out_table,
800 .fixed_predivs = clk_out_predivs,
801 .n_predivs = ARRAY_SIZE(clk_out_predivs),
805 .features = CCU_FEATURE_FIXED_PREDIV,
806 .hw.init = CLK_HW_INIT_PARENTS("out-c",
813 static struct ccu_common *sun6i_a31_ccu_clks[] = {
815 &pll_audio_base_clk.common,
816 &pll_video0_clk.common,
819 &pll_periph_clk.common,
820 &pll_video1_clk.common,
822 &pll_mipi_clk.common,
830 &ahb1_mipidsi_clk.common,
832 &ahb1_dma_clk.common,
833 &ahb1_mmc0_clk.common,
834 &ahb1_mmc1_clk.common,
835 &ahb1_mmc2_clk.common,
836 &ahb1_mmc3_clk.common,
837 &ahb1_nand1_clk.common,
838 &ahb1_nand0_clk.common,
839 &ahb1_sdram_clk.common,
840 &ahb1_emac_clk.common,
842 &ahb1_hstimer_clk.common,
843 &ahb1_spi0_clk.common,
844 &ahb1_spi1_clk.common,
845 &ahb1_spi2_clk.common,
846 &ahb1_spi3_clk.common,
847 &ahb1_otg_clk.common,
848 &ahb1_ehci0_clk.common,
849 &ahb1_ehci1_clk.common,
850 &ahb1_ohci0_clk.common,
851 &ahb1_ohci1_clk.common,
852 &ahb1_ohci2_clk.common,
854 &ahb1_lcd0_clk.common,
855 &ahb1_lcd1_clk.common,
856 &ahb1_csi_clk.common,
857 &ahb1_hdmi_clk.common,
858 &ahb1_be0_clk.common,
859 &ahb1_be1_clk.common,
860 &ahb1_fe0_clk.common,
861 &ahb1_fe1_clk.common,
863 &ahb1_gpu_clk.common,
864 &ahb1_deu0_clk.common,
865 &ahb1_deu1_clk.common,
866 &ahb1_drc0_clk.common,
867 &ahb1_drc1_clk.common,
868 &apb1_codec_clk.common,
869 &apb1_spdif_clk.common,
870 &apb1_digital_mic_clk.common,
871 &apb1_pio_clk.common,
872 &apb1_daudio0_clk.common,
873 &apb1_daudio1_clk.common,
874 &apb2_i2c0_clk.common,
875 &apb2_i2c1_clk.common,
876 &apb2_i2c2_clk.common,
877 &apb2_i2c3_clk.common,
878 &apb2_uart0_clk.common,
879 &apb2_uart1_clk.common,
880 &apb2_uart2_clk.common,
881 &apb2_uart3_clk.common,
882 &apb2_uart4_clk.common,
883 &apb2_uart5_clk.common,
887 &mmc0_sample_clk.common,
888 &mmc0_output_clk.common,
890 &mmc1_sample_clk.common,
891 &mmc1_output_clk.common,
893 &mmc2_sample_clk.common,
894 &mmc2_output_clk.common,
896 &mmc3_sample_clk.common,
897 &mmc3_output_clk.common,
907 &usb_phy0_clk.common,
908 &usb_phy1_clk.common,
909 &usb_phy2_clk.common,
910 &usb_ohci0_clk.common,
911 &usb_ohci1_clk.common,
912 &usb_ohci2_clk.common,
917 &dram_csi_isp_clk.common,
919 &dram_drc0_clk.common,
920 &dram_drc1_clk.common,
921 &dram_deu0_clk.common,
922 &dram_deu1_clk.common,
923 &dram_fe0_clk.common,
924 &dram_fe1_clk.common,
925 &dram_be0_clk.common,
926 &dram_be1_clk.common,
933 &lcd0_ch0_clk.common,
934 &lcd1_ch0_clk.common,
935 &lcd0_ch1_clk.common,
936 &lcd1_ch1_clk.common,
937 &csi0_sclk_clk.common,
938 &csi0_mclk_clk.common,
939 &csi1_mclk_clk.common,
943 &digital_mic_clk.common,
945 &hdmi_ddc_clk.common,
949 &mipi_dsi_clk.common,
950 &mipi_dsi_dphy_clk.common,
951 &mipi_csi_dphy_clk.common,
952 &iep_drc0_clk.common,
953 &iep_drc1_clk.common,
954 &iep_deu0_clk.common,
955 &iep_deu1_clk.common,
956 &gpu_core_clk.common,
957 &gpu_memory_clk.common,
966 /* We hardcode the divider to 1 for now */
967 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
968 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
969 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
970 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
971 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
972 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
973 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
974 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
975 static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
976 "pll-periph", 1, 2, 0);
977 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
978 "pll-video0", 1, 2, CLK_SET_RATE_PARENT);
979 static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
980 "pll-video1", 1, 2, CLK_SET_RATE_PARENT);
982 static struct clk_hw_onecell_data sun6i_a31_hw_clks = {
984 [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
985 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
986 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
987 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
988 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
989 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
990 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
991 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
992 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
993 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
994 [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
995 [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw,
996 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
997 [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
998 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
999 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
1000 [CLK_PLL9] = &pll9_clk.common.hw,
1001 [CLK_PLL10] = &pll10_clk.common.hw,
1002 [CLK_CPU] = &cpu_clk.common.hw,
1003 [CLK_AXI] = &axi_clk.common.hw,
1004 [CLK_AHB1] = &ahb1_clk.common.hw,
1005 [CLK_APB1] = &apb1_clk.common.hw,
1006 [CLK_APB2] = &apb2_clk.common.hw,
1007 [CLK_AHB1_MIPIDSI] = &ahb1_mipidsi_clk.common.hw,
1008 [CLK_AHB1_SS] = &ahb1_ss_clk.common.hw,
1009 [CLK_AHB1_DMA] = &ahb1_dma_clk.common.hw,
1010 [CLK_AHB1_MMC0] = &ahb1_mmc0_clk.common.hw,
1011 [CLK_AHB1_MMC1] = &ahb1_mmc1_clk.common.hw,
1012 [CLK_AHB1_MMC2] = &ahb1_mmc2_clk.common.hw,
1013 [CLK_AHB1_MMC3] = &ahb1_mmc3_clk.common.hw,
1014 [CLK_AHB1_NAND1] = &ahb1_nand1_clk.common.hw,
1015 [CLK_AHB1_NAND0] = &ahb1_nand0_clk.common.hw,
1016 [CLK_AHB1_SDRAM] = &ahb1_sdram_clk.common.hw,
1017 [CLK_AHB1_EMAC] = &ahb1_emac_clk.common.hw,
1018 [CLK_AHB1_TS] = &ahb1_ts_clk.common.hw,
1019 [CLK_AHB1_HSTIMER] = &ahb1_hstimer_clk.common.hw,
1020 [CLK_AHB1_SPI0] = &ahb1_spi0_clk.common.hw,
1021 [CLK_AHB1_SPI1] = &ahb1_spi1_clk.common.hw,
1022 [CLK_AHB1_SPI2] = &ahb1_spi2_clk.common.hw,
1023 [CLK_AHB1_SPI3] = &ahb1_spi3_clk.common.hw,
1024 [CLK_AHB1_OTG] = &ahb1_otg_clk.common.hw,
1025 [CLK_AHB1_EHCI0] = &ahb1_ehci0_clk.common.hw,
1026 [CLK_AHB1_EHCI1] = &ahb1_ehci1_clk.common.hw,
1027 [CLK_AHB1_OHCI0] = &ahb1_ohci0_clk.common.hw,
1028 [CLK_AHB1_OHCI1] = &ahb1_ohci1_clk.common.hw,
1029 [CLK_AHB1_OHCI2] = &ahb1_ohci2_clk.common.hw,
1030 [CLK_AHB1_VE] = &ahb1_ve_clk.common.hw,
1031 [CLK_AHB1_LCD0] = &ahb1_lcd0_clk.common.hw,
1032 [CLK_AHB1_LCD1] = &ahb1_lcd1_clk.common.hw,
1033 [CLK_AHB1_CSI] = &ahb1_csi_clk.common.hw,
1034 [CLK_AHB1_HDMI] = &ahb1_hdmi_clk.common.hw,
1035 [CLK_AHB1_BE0] = &ahb1_be0_clk.common.hw,
1036 [CLK_AHB1_BE1] = &ahb1_be1_clk.common.hw,
1037 [CLK_AHB1_FE0] = &ahb1_fe0_clk.common.hw,
1038 [CLK_AHB1_FE1] = &ahb1_fe1_clk.common.hw,
1039 [CLK_AHB1_MP] = &ahb1_mp_clk.common.hw,
1040 [CLK_AHB1_GPU] = &ahb1_gpu_clk.common.hw,
1041 [CLK_AHB1_DEU0] = &ahb1_deu0_clk.common.hw,
1042 [CLK_AHB1_DEU1] = &ahb1_deu1_clk.common.hw,
1043 [CLK_AHB1_DRC0] = &ahb1_drc0_clk.common.hw,
1044 [CLK_AHB1_DRC1] = &ahb1_drc1_clk.common.hw,
1045 [CLK_APB1_CODEC] = &apb1_codec_clk.common.hw,
1046 [CLK_APB1_SPDIF] = &apb1_spdif_clk.common.hw,
1047 [CLK_APB1_DIGITAL_MIC] = &apb1_digital_mic_clk.common.hw,
1048 [CLK_APB1_PIO] = &apb1_pio_clk.common.hw,
1049 [CLK_APB1_DAUDIO0] = &apb1_daudio0_clk.common.hw,
1050 [CLK_APB1_DAUDIO1] = &apb1_daudio1_clk.common.hw,
1051 [CLK_APB2_I2C0] = &apb2_i2c0_clk.common.hw,
1052 [CLK_APB2_I2C1] = &apb2_i2c1_clk.common.hw,
1053 [CLK_APB2_I2C2] = &apb2_i2c2_clk.common.hw,
1054 [CLK_APB2_I2C3] = &apb2_i2c3_clk.common.hw,
1055 [CLK_APB2_UART0] = &apb2_uart0_clk.common.hw,
1056 [CLK_APB2_UART1] = &apb2_uart1_clk.common.hw,
1057 [CLK_APB2_UART2] = &apb2_uart2_clk.common.hw,
1058 [CLK_APB2_UART3] = &apb2_uart3_clk.common.hw,
1059 [CLK_APB2_UART4] = &apb2_uart4_clk.common.hw,
1060 [CLK_APB2_UART5] = &apb2_uart5_clk.common.hw,
1061 [CLK_NAND0] = &nand0_clk.common.hw,
1062 [CLK_NAND1] = &nand1_clk.common.hw,
1063 [CLK_MMC0] = &mmc0_clk.common.hw,
1064 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
1065 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
1066 [CLK_MMC1] = &mmc1_clk.common.hw,
1067 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
1068 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
1069 [CLK_MMC2] = &mmc2_clk.common.hw,
1070 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
1071 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
1072 [CLK_MMC3] = &mmc3_clk.common.hw,
1073 [CLK_MMC3_SAMPLE] = &mmc3_sample_clk.common.hw,
1074 [CLK_MMC3_OUTPUT] = &mmc3_output_clk.common.hw,
1075 [CLK_TS] = &ts_clk.common.hw,
1076 [CLK_SS] = &ss_clk.common.hw,
1077 [CLK_SPI0] = &spi0_clk.common.hw,
1078 [CLK_SPI1] = &spi1_clk.common.hw,
1079 [CLK_SPI2] = &spi2_clk.common.hw,
1080 [CLK_SPI3] = &spi3_clk.common.hw,
1081 [CLK_DAUDIO0] = &daudio0_clk.common.hw,
1082 [CLK_DAUDIO1] = &daudio1_clk.common.hw,
1083 [CLK_SPDIF] = &spdif_clk.common.hw,
1084 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
1085 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
1086 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
1087 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1088 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
1089 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
1090 [CLK_MDFS] = &mdfs_clk.common.hw,
1091 [CLK_SDRAM0] = &sdram0_clk.common.hw,
1092 [CLK_SDRAM1] = &sdram1_clk.common.hw,
1093 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
1094 [CLK_DRAM_CSI_ISP] = &dram_csi_isp_clk.common.hw,
1095 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
1096 [CLK_DRAM_DRC0] = &dram_drc0_clk.common.hw,
1097 [CLK_DRAM_DRC1] = &dram_drc1_clk.common.hw,
1098 [CLK_DRAM_DEU0] = &dram_deu0_clk.common.hw,
1099 [CLK_DRAM_DEU1] = &dram_deu1_clk.common.hw,
1100 [CLK_DRAM_FE0] = &dram_fe0_clk.common.hw,
1101 [CLK_DRAM_FE1] = &dram_fe1_clk.common.hw,
1102 [CLK_DRAM_BE0] = &dram_be0_clk.common.hw,
1103 [CLK_DRAM_BE1] = &dram_be1_clk.common.hw,
1104 [CLK_DRAM_MP] = &dram_mp_clk.common.hw,
1105 [CLK_BE0] = &be0_clk.common.hw,
1106 [CLK_BE1] = &be1_clk.common.hw,
1107 [CLK_FE0] = &fe0_clk.common.hw,
1108 [CLK_FE1] = &fe1_clk.common.hw,
1109 [CLK_MP] = &mp_clk.common.hw,
1110 [CLK_LCD0_CH0] = &lcd0_ch0_clk.common.hw,
1111 [CLK_LCD1_CH0] = &lcd1_ch0_clk.common.hw,
1112 [CLK_LCD0_CH1] = &lcd0_ch1_clk.common.hw,
1113 [CLK_LCD1_CH1] = &lcd1_ch1_clk.common.hw,
1114 [CLK_CSI0_SCLK] = &csi0_sclk_clk.common.hw,
1115 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
1116 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
1117 [CLK_VE] = &ve_clk.common.hw,
1118 [CLK_CODEC] = &codec_clk.common.hw,
1119 [CLK_AVS] = &avs_clk.common.hw,
1120 [CLK_DIGITAL_MIC] = &digital_mic_clk.common.hw,
1121 [CLK_HDMI] = &hdmi_clk.common.hw,
1122 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
1123 [CLK_PS] = &ps_clk.common.hw,
1124 [CLK_MBUS0] = &mbus0_clk.common.hw,
1125 [CLK_MBUS1] = &mbus1_clk.common.hw,
1126 [CLK_MIPI_DSI] = &mipi_dsi_clk.common.hw,
1127 [CLK_MIPI_DSI_DPHY] = &mipi_dsi_dphy_clk.common.hw,
1128 [CLK_MIPI_CSI_DPHY] = &mipi_csi_dphy_clk.common.hw,
1129 [CLK_IEP_DRC0] = &iep_drc0_clk.common.hw,
1130 [CLK_IEP_DRC1] = &iep_drc1_clk.common.hw,
1131 [CLK_IEP_DEU0] = &iep_deu0_clk.common.hw,
1132 [CLK_IEP_DEU1] = &iep_deu1_clk.common.hw,
1133 [CLK_GPU_CORE] = &gpu_core_clk.common.hw,
1134 [CLK_GPU_MEMORY] = &gpu_memory_clk.common.hw,
1135 [CLK_GPU_HYD] = &gpu_hyd_clk.common.hw,
1136 [CLK_ATS] = &ats_clk.common.hw,
1137 [CLK_TRACE] = &trace_clk.common.hw,
1138 [CLK_OUT_A] = &out_a_clk.common.hw,
1139 [CLK_OUT_B] = &out_b_clk.common.hw,
1140 [CLK_OUT_C] = &out_c_clk.common.hw,
1145 static struct ccu_reset_map sun6i_a31_ccu_resets[] = {
1146 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
1147 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
1148 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
1150 [RST_AHB1_MIPI_DSI] = { 0x2c0, BIT(1) },
1151 [RST_AHB1_SS] = { 0x2c0, BIT(5) },
1152 [RST_AHB1_DMA] = { 0x2c0, BIT(6) },
1153 [RST_AHB1_MMC0] = { 0x2c0, BIT(8) },
1154 [RST_AHB1_MMC1] = { 0x2c0, BIT(9) },
1155 [RST_AHB1_MMC2] = { 0x2c0, BIT(10) },
1156 [RST_AHB1_MMC3] = { 0x2c0, BIT(11) },
1157 [RST_AHB1_NAND1] = { 0x2c0, BIT(12) },
1158 [RST_AHB1_NAND0] = { 0x2c0, BIT(13) },
1159 [RST_AHB1_SDRAM] = { 0x2c0, BIT(14) },
1160 [RST_AHB1_EMAC] = { 0x2c0, BIT(17) },
1161 [RST_AHB1_TS] = { 0x2c0, BIT(18) },
1162 [RST_AHB1_HSTIMER] = { 0x2c0, BIT(19) },
1163 [RST_AHB1_SPI0] = { 0x2c0, BIT(20) },
1164 [RST_AHB1_SPI1] = { 0x2c0, BIT(21) },
1165 [RST_AHB1_SPI2] = { 0x2c0, BIT(22) },
1166 [RST_AHB1_SPI3] = { 0x2c0, BIT(23) },
1167 [RST_AHB1_OTG] = { 0x2c0, BIT(24) },
1168 [RST_AHB1_EHCI0] = { 0x2c0, BIT(26) },
1169 [RST_AHB1_EHCI1] = { 0x2c0, BIT(27) },
1170 [RST_AHB1_OHCI0] = { 0x2c0, BIT(29) },
1171 [RST_AHB1_OHCI1] = { 0x2c0, BIT(30) },
1172 [RST_AHB1_OHCI2] = { 0x2c0, BIT(31) },
1174 [RST_AHB1_VE] = { 0x2c4, BIT(0) },
1175 [RST_AHB1_LCD0] = { 0x2c4, BIT(4) },
1176 [RST_AHB1_LCD1] = { 0x2c4, BIT(5) },
1177 [RST_AHB1_CSI] = { 0x2c4, BIT(8) },
1178 [RST_AHB1_HDMI] = { 0x2c4, BIT(11) },
1179 [RST_AHB1_BE0] = { 0x2c4, BIT(12) },
1180 [RST_AHB1_BE1] = { 0x2c4, BIT(13) },
1181 [RST_AHB1_FE0] = { 0x2c4, BIT(14) },
1182 [RST_AHB1_FE1] = { 0x2c4, BIT(15) },
1183 [RST_AHB1_MP] = { 0x2c4, BIT(18) },
1184 [RST_AHB1_GPU] = { 0x2c4, BIT(20) },
1185 [RST_AHB1_DEU0] = { 0x2c4, BIT(23) },
1186 [RST_AHB1_DEU1] = { 0x2c4, BIT(24) },
1187 [RST_AHB1_DRC0] = { 0x2c4, BIT(25) },
1188 [RST_AHB1_DRC1] = { 0x2c4, BIT(26) },
1189 [RST_AHB1_LVDS] = { 0x2c8, BIT(0) },
1191 [RST_APB1_CODEC] = { 0x2d0, BIT(0) },
1192 [RST_APB1_SPDIF] = { 0x2d0, BIT(1) },
1193 [RST_APB1_DIGITAL_MIC] = { 0x2d0, BIT(4) },
1194 [RST_APB1_DAUDIO0] = { 0x2d0, BIT(12) },
1195 [RST_APB1_DAUDIO1] = { 0x2d0, BIT(13) },
1197 [RST_APB2_I2C0] = { 0x2d8, BIT(0) },
1198 [RST_APB2_I2C1] = { 0x2d8, BIT(1) },
1199 [RST_APB2_I2C2] = { 0x2d8, BIT(2) },
1200 [RST_APB2_I2C3] = { 0x2d8, BIT(3) },
1201 [RST_APB2_UART0] = { 0x2d8, BIT(16) },
1202 [RST_APB2_UART1] = { 0x2d8, BIT(17) },
1203 [RST_APB2_UART2] = { 0x2d8, BIT(18) },
1204 [RST_APB2_UART3] = { 0x2d8, BIT(19) },
1205 [RST_APB2_UART4] = { 0x2d8, BIT(20) },
1206 [RST_APB2_UART5] = { 0x2d8, BIT(21) },
1209 static const struct sunxi_ccu_desc sun6i_a31_ccu_desc = {
1210 .ccu_clks = sun6i_a31_ccu_clks,
1211 .num_ccu_clks = ARRAY_SIZE(sun6i_a31_ccu_clks),
1213 .hw_clks = &sun6i_a31_hw_clks,
1215 .resets = sun6i_a31_ccu_resets,
1216 .num_resets = ARRAY_SIZE(sun6i_a31_ccu_resets),
1219 static struct ccu_mux_nb sun6i_a31_cpu_nb = {
1220 .common = &cpu_clk.common,
1222 .delay_us = 1, /* > 8 clock cycles at 24 MHz */
1223 .bypass_index = 1, /* index of 24 MHz oscillator */
1226 static void __init sun6i_a31_ccu_setup(struct device_node *node)
1231 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1233 pr_err("%pOF: Could not map the clock registers\n", node);
1237 /* Force the PLL-Audio-1x divider to 1 */
1238 val = readl(reg + SUN6I_A31_PLL_AUDIO_REG);
1239 val &= ~GENMASK(19, 16);
1240 writel(val | (0 << 16), reg + SUN6I_A31_PLL_AUDIO_REG);
1242 /* Force PLL-MIPI to MIPI mode */
1243 val = readl(reg + SUN6I_A31_PLL_MIPI_REG);
1245 writel(val, reg + SUN6I_A31_PLL_MIPI_REG);
1247 /* Force AHB1 to PLL6 / 3 */
1248 val = readl(reg + SUN6I_A31_AHB1_REG);
1249 /* set PLL6 pre-div = 3 */
1250 val &= ~GENMASK(7, 6);
1252 /* select PLL6 / pre-div */
1253 val &= ~GENMASK(13, 12);
1255 writel(val, reg + SUN6I_A31_AHB1_REG);
1257 sunxi_ccu_probe(node, reg, &sun6i_a31_ccu_desc);
1259 ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
1262 CLK_OF_DECLARE(sun6i_a31_ccu, "allwinner,sun6i-a31-ccu",
1263 sun6i_a31_ccu_setup);