drivers/clk/socfpga/clk-periph-a10.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Altera Corporation. All rights reserved
   4  */
   5 #include <linux/slab.h>
   6 #include <linux/clk-provider.h>
   7 #include <linux/io.h>
   8 #include <linux/of.h>
   9
  10 #include "clk.h"
  11
  12 #define CLK_MGR_FREE_SHIFT              16
  13 #define CLK_MGR_FREE_MASK               0x7
  14
  15 #define SOCFPGA_MPU_FREE_CLK            "mpu_free_clk"
  16 #define SOCFPGA_NOC_FREE_CLK            "noc_free_clk"
  17 #define SOCFPGA_SDMMC_FREE_CLK          "sdmmc_free_clk"
  18 #define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
  19
  20 static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
  21                                              unsigned long parent_rate)
  22 {
  23         struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
  24         u32 div;
  25
  26         if (socfpgaclk->fixed_div) {
  27                 div = socfpgaclk->fixed_div;
  28         } else if (socfpgaclk->div_reg) {
  29                 div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
  30                 div &= GENMASK(socfpgaclk->width - 1, 0);
  31                 div += 1;
  32         } else {
  33                 div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
  34         }
  35
  36         return parent_rate / div;
  37 }
  38
  39 static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
  40 {
  41         struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
  42         u32 clk_src;
  43
  44         clk_src = readl(socfpgaclk->hw.reg);
  45         if (streq(hwclk->init->name, SOCFPGA_MPU_FREE_CLK) ||
  46             streq(hwclk->init->name, SOCFPGA_NOC_FREE_CLK) ||
  47             streq(hwclk->init->name, SOCFPGA_SDMMC_FREE_CLK))
  48                 return (clk_src >> CLK_MGR_FREE_SHIFT) &
  49                         CLK_MGR_FREE_MASK;
  50         else
  51                 return 0;
  52 }
  53
  54 static const struct clk_ops periclk_ops = {
  55         .recalc_rate = clk_periclk_recalc_rate,
  56         .get_parent = clk_periclk_get_parent,
  57 };
  58
  59 static __init void __socfpga_periph_init(struct device_node *node,
  60         const struct clk_ops *ops)
  61 {
  62         u32 reg;
  63         struct clk *clk;
  64         struct socfpga_periph_clk *periph_clk;
  65         const char *clk_name = node->name;
  66         const char *parent_name[SOCFPGA_MAX_PARENTS];
  67         struct clk_init_data init;
  68         int rc;
  69         u32 fixed_div;
  70         u32 div_reg[3];
  71
  72         of_property_read_u32(node, "reg", &reg);
  73
  74         periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
  75         if (WARN_ON(!periph_clk))
  76                 return;
  77
  78         periph_clk->hw.reg = clk_mgr_a10_base_addr + reg;
  79
  80         rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
  81         if (!rc) {
  82                 periph_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0];
  83                 periph_clk->shift = div_reg[1];
  84                 periph_clk->width = div_reg[2];
  85         } else {
  86                 periph_clk->div_reg = NULL;
  87         }
  88
  89         rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
  90         if (rc)
  91                 periph_clk->fixed_div = 0;
  92         else
  93                 periph_clk->fixed_div = fixed_div;
  94
  95         of_property_read_string(node, "clock-output-names", &clk_name);
  96
  97         init.name = clk_name;
  98         init.ops = ops;
  99         init.flags = 0;
 100
 101         init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
 102         init.parent_names = parent_name;
 103
 104         periph_clk->hw.hw.init = &init;
 105
 106         clk = clk_register(NULL, &periph_clk->hw.hw);
 107         if (WARN_ON(IS_ERR(clk))) {
 108                 kfree(periph_clk);
 109                 return;
 110         }
 111         rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
 112         if (rc < 0) {
 113                 pr_err("Could not register clock provider for node:%s\n",
 114                        clk_name);
 115                 goto err_clk;
 116         }
 117
 118         return;
 119
 120 err_clk:
 121         clk_unregister(clk);
 122 }
 123
 124 void __init socfpga_a10_periph_init(struct device_node *node)
 125 {
 126         __socfpga_periph_init(node, &periclk_ops);
 127 }