1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2023 Linaro Ltd.
4 * Author: Peter Griffin <peter.griffin@linaro.org>
6 * Common Clock Framework support for GS101.
10 #include <linux/clk-provider.h>
12 #include <linux/platform_device.h>
14 #include <dt-bindings/clock/google,gs101.h>
17 #include "clk-exynos-arm64.h"
19 /* NOTE: Must be equal to the last clock ID increased by one */
20 #define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1)
21 #define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1)
22 #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
24 /* ---- CMU_TOP ------------------------------------------------------------- */
26 /* Register Offset definitions for CMU_TOP (0x1e080000) */
28 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
29 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
30 #define PLL_LOCKTIME_PLL_SHARED2 0x0008
31 #define PLL_LOCKTIME_PLL_SHARED3 0x000c
32 #define PLL_LOCKTIME_PLL_SPARE 0x0010
33 #define PLL_CON0_PLL_SHARED0 0x0100
34 #define PLL_CON1_PLL_SHARED0 0x0104
35 #define PLL_CON2_PLL_SHARED0 0x0108
36 #define PLL_CON3_PLL_SHARED0 0x010c
37 #define PLL_CON4_PLL_SHARED0 0x0110
38 #define PLL_CON0_PLL_SHARED1 0x0140
39 #define PLL_CON1_PLL_SHARED1 0x0144
40 #define PLL_CON2_PLL_SHARED1 0x0148
41 #define PLL_CON3_PLL_SHARED1 0x014c
42 #define PLL_CON4_PLL_SHARED1 0x0150
43 #define PLL_CON0_PLL_SHARED2 0x0180
44 #define PLL_CON1_PLL_SHARED2 0x0184
45 #define PLL_CON2_PLL_SHARED2 0x0188
46 #define PLL_CON3_PLL_SHARED2 0x018c
47 #define PLL_CON4_PLL_SHARED2 0x0190
48 #define PLL_CON0_PLL_SHARED3 0x01c0
49 #define PLL_CON1_PLL_SHARED3 0x01c4
50 #define PLL_CON2_PLL_SHARED3 0x01c8
51 #define PLL_CON3_PLL_SHARED3 0x01cc
52 #define PLL_CON4_PLL_SHARED3 0x01d0
53 #define PLL_CON0_PLL_SPARE 0x0200
54 #define PLL_CON1_PLL_SPARE 0x0204
55 #define PLL_CON2_PLL_SPARE 0x0208
56 #define PLL_CON3_PLL_SPARE 0x020c
57 #define PLL_CON4_PLL_SPARE 0x0210
58 #define CMU_CMU_TOP_CONTROLLER_OPTION 0x0800
59 #define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 0x0810
60 #define CMU_HCHGEN_CLKMUX_CMU_BOOST 0x0840
61 #define CMU_HCHGEN_CLKMUX_TOP_BOOST 0x0844
62 #define CMU_HCHGEN_CLKMUX 0x0850
63 #define POWER_FAIL_DETECT_PLL 0x0864
64 #define EARLY_WAKEUP_FORCED_0_ENABLE 0x0870
65 #define EARLY_WAKEUP_FORCED_1_ENABLE 0x0874
66 #define EARLY_WAKEUP_APM_CTRL 0x0878
67 #define EARLY_WAKEUP_CLUSTER0_CTRL 0x087c
68 #define EARLY_WAKEUP_DPU_CTRL 0x0880
69 #define EARLY_WAKEUP_CSIS_CTRL 0x0884
70 #define EARLY_WAKEUP_APM_DEST 0x0890
71 #define EARLY_WAKEUP_CLUSTER0_DEST 0x0894
72 #define EARLY_WAKEUP_DPU_DEST 0x0898
73 #define EARLY_WAKEUP_CSIS_DEST 0x089c
74 #define EARLY_WAKEUP_SW_TRIG_APM 0x08c0
75 #define EARLY_WAKEUP_SW_TRIG_APM_SET 0x08c4
76 #define EARLY_WAKEUP_SW_TRIG_APM_CLEAR 0x08c8
77 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0 0x08d0
78 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET 0x08d4
79 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR 0x08d8
80 #define EARLY_WAKEUP_SW_TRIG_DPU 0x08e0
81 #define EARLY_WAKEUP_SW_TRIG_DPU_SET 0x08e4
82 #define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR 0x08e8
83 #define EARLY_WAKEUP_SW_TRIG_CSIS 0x08f0
84 #define EARLY_WAKEUP_SW_TRIG_CSIS_SET 0x08f4
85 #define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR 0x08f8
86 #define CLK_CON_MUX_MUX_CLKCMU_BO_BUS 0x1000
87 #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x1004
88 #define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008
89 #define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS 0x100c
90 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1010
91 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1014
92 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1018
93 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x101c
94 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1020
95 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1024
96 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1028
97 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x102c
98 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030
99 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 0x1034
100 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1038
101 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x103c
102 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1040
103 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1044
104 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048
105 #define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c
106 #define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS 0x1050
107 #define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x1054
108 #define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x1058
109 #define CLK_CON_MUX_MUX_CLKCMU_EH_BUS 0x105c
110 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1060
111 #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1064
112 #define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA 0x1068
113 #define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD 0x106c
114 #define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB 0x1070
115 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1074
116 #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 0x1078
117 #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 0x107c
118 #define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC 0x1080
119 #define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084
120 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1088
121 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x108c
122 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1090
123 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG 0x1094
124 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1098
125 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x109c
126 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x10a0
127 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD 0x10a4
128 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a8
129 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x10ac
130 #define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10b0
131 #define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10b4
132 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC 0x10b8
133 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x10bc
134 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10c0
135 #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c4
136 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c8
137 #define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS 0x10cc
138 #define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS 0x10d0
139 #define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS 0x10d4
140 #define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA 0x10d8
141 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10dc
142 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10e0
143 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10e4
144 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10e8
145 #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10ec
146 #define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 0x10f0
147 #define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF 0x10f4
148 #define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS 0x10f8
149 #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU 0x10fc
150 #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL 0x1100
151 #define CLK_CON_MUX_MUX_CLKCMU_TPU_UART 0x1104
152 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108
153 #define CLK_CON_DIV_CLKCMU_BO_BUS 0x1800
154 #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1804
155 #define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808
156 #define CLK_CON_DIV_CLKCMU_BUS2_BUS 0x180c
157 #define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810
158 #define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814
159 #define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818
160 #define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c
161 #define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1820
162 #define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1824
163 #define CLK_CON_DIV_CLKCMU_CIS_CLK6 0x1828
164 #define CLK_CON_DIV_CLKCMU_CIS_CLK7 0x182c
165 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830
166 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1834
167 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838
168 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
169 #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1840
170 #define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1844
171 #define CLK_CON_DIV_CLKCMU_DISP_BUS 0x1848
172 #define CLK_CON_DIV_CLKCMU_DNS_BUS 0x184c
173 #define CLK_CON_DIV_CLKCMU_DPU_BUS 0x1850
174 #define CLK_CON_DIV_CLKCMU_EH_BUS 0x1854
175 #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1858
176 #define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x185c
177 #define CLK_CON_DIV_CLKCMU_G3AA_G3AA 0x1860
178 #define CLK_CON_DIV_CLKCMU_G3D_BUSD 0x1864
179 #define CLK_CON_DIV_CLKCMU_G3D_GLB 0x1868
180 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x186c
181 #define CLK_CON_DIV_CLKCMU_GDC_GDC0 0x1870
182 #define CLK_CON_DIV_CLKCMU_GDC_GDC1 0x1874
183 #define CLK_CON_DIV_CLKCMU_GDC_SCSC 0x1878
184 #define CLK_CON_DIV_CLKCMU_HPM 0x187c
185 #define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1880
186 #define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1884
187 #define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1888
188 #define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG 0x188c
189 #define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1890
190 #define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1894
191 #define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1898
192 #define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD 0x189c
193 #define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x18a0
194 #define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x18a4
195 #define CLK_CON_DIV_CLKCMU_IPP_BUS 0x18a8
196 #define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18ac
197 #define CLK_CON_DIV_CLKCMU_MCSC_ITSC 0x18b0
198 #define CLK_CON_DIV_CLKCMU_MCSC_MCSC 0x18b4
199 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18b8
200 #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18bc
201 #define CLK_CON_DIV_CLKCMU_MISC_BUS 0x18c0
202 #define CLK_CON_DIV_CLKCMU_MISC_SSS 0x18c4
203 #define CLK_CON_DIV_CLKCMU_OTP 0x18c8
204 #define CLK_CON_DIV_CLKCMU_PDP_BUS 0x18cc
205 #define CLK_CON_DIV_CLKCMU_PDP_VRA 0x18d0
206 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18d4
207 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18d8
208 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18dc
209 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18e0
210 #define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18e4
211 #define CLK_CON_DIV_CLKCMU_TPU_BUS 0x18e8
212 #define CLK_CON_DIV_CLKCMU_TPU_TPU 0x18ec
213 #define CLK_CON_DIV_CLKCMU_TPU_TPUCTL 0x18f0
214 #define CLK_CON_DIV_CLKCMU_TPU_UART 0x18f4
215 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18f8
216 #define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18fc
217 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x1900
218 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1904
219 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1908
220 #define CLK_CON_DIV_PLL_SHARED0_DIV5 0x190c
221 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1910
222 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1914
223 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1918
224 #define CLK_CON_DIV_PLL_SHARED2_DIV2 0x191c
225 #define CLK_CON_DIV_PLL_SHARED3_DIV2 0x1920
226 #define CLK_CON_GAT_CLKCMU_BUS0_BOOST 0x2000
227 #define CLK_CON_GAT_CLKCMU_BUS1_BOOST 0x2004
228 #define CLK_CON_GAT_CLKCMU_BUS2_BOOST 0x2008
229 #define CLK_CON_GAT_CLKCMU_CORE_BOOST 0x200c
230 #define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST 0x2010
231 #define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST 0x2014
232 #define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST 0x2018
233 #define CLK_CON_GAT_CLKCMU_MIF_BOOST 0x201c
234 #define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2020
235 #define CLK_CON_GAT_GATE_CLKCMU_BO_BUS 0x2024
236 #define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2028
237 #define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x202c
238 #define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS 0x2030
239 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2034
240 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2038
241 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x203c
242 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2040
243 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2044
244 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2048
245 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x204c
246 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x2050
247 #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2054
248 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2058
249 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x205c
250 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2060
251 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2064
252 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2068
253 #define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x206c
254 #define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS 0x2070
255 #define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x2074
256 #define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2078
257 #define CLK_CON_GAT_GATE_CLKCMU_EH_BUS 0x207c
258 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080
259 #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2084
260 #define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA 0x2088
261 #define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD 0x208c
262 #define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB 0x2090
263 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2094
264 #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 0x2098
265 #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 0x209c
266 #define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC 0x20a0
267 #define CLK_CON_GAT_GATE_CLKCMU_HPM 0x20a4
268 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x20a8
269 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ac
270 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x20b0
271 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG 0x20b4
272 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x20b8
273 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x20bc
274 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20c0
275 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD 0x20c4
276 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20c8
277 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD 0x20cc
278 #define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20d0
279 #define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20d4
280 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC 0x20d8
281 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x20dc
282 #define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20e0
283 #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20e4
284 #define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS 0x20e8
285 #define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS 0x20ec
286 #define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS 0x20f0
287 #define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA 0x20f4
288 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20f8
289 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20fc
290 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x2100
291 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x2104
292 #define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x2108
293 #define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF 0x210c
294 #define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS 0x2110
295 #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU 0x2114
296 #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL 0x2118
297 #define CLK_CON_GAT_GATE_CLKCMU_TPU_UART 0x211c
298 #define DMYQCH_CON_CMU_TOP_CMUREF_QCH 0x3000
299 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 0x3004
300 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 0x3008
301 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 0x300c
302 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 0x3010
303 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 0x3014
304 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 0x3018
305 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 0x301c
306 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 0x3020
307 #define DMYQCH_CON_OTP_QCH 0x3024
308 #define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP 0x3c00
309 #define QUEUE_ENTRY0_BLK_CMU_CMU_TOP 0x3c10
310 #define QUEUE_ENTRY1_BLK_CMU_CMU_TOP 0x3c14
311 #define QUEUE_ENTRY2_BLK_CMU_CMU_TOP 0x3c18
312 #define QUEUE_ENTRY3_BLK_CMU_CMU_TOP 0x3c1c
313 #define QUEUE_ENTRY4_BLK_CMU_CMU_TOP 0x3c20
314 #define QUEUE_ENTRY5_BLK_CMU_CMU_TOP 0x3c24
315 #define QUEUE_ENTRY6_BLK_CMU_CMU_TOP 0x3c28
316 #define QUEUE_ENTRY7_BLK_CMU_CMU_TOP 0x3c2c
317 #define MIFMIRROR_QUEUE_CTRL_REG 0x3e00
318 #define MIFMIRROR_QUEUE_ENTRY0 0x3e10
319 #define MIFMIRROR_QUEUE_ENTRY1 0x3e14
320 #define MIFMIRROR_QUEUE_ENTRY2 0x3e18
321 #define MIFMIRROR_QUEUE_ENTRY3 0x3e1c
322 #define MIFMIRROR_QUEUE_ENTRY4 0x3e20
323 #define MIFMIRROR_QUEUE_ENTRY5 0x3e24
324 #define MIFMIRROR_QUEUE_ENTRY6 0x3e28
325 #define MIFMIRROR_QUEUE_ENTRY7 0x3e2c
326 #define MIFMIRROR_QUEUE_BUSY 0x3e30
327 #define GENERALIO_ACD_CHANNEL_0 0x3f00
328 #define GENERALIO_ACD_CHANNEL_1 0x3f04
329 #define GENERALIO_ACD_CHANNEL_2 0x3f08
330 #define GENERALIO_ACD_CHANNEL_3 0x3f0c
331 #define GENERALIO_ACD_MASK 0x3f14
333 static const unsigned long cmu_top_clk_regs[] __initconst = {
334 PLL_LOCKTIME_PLL_SHARED0,
335 PLL_LOCKTIME_PLL_SHARED1,
336 PLL_LOCKTIME_PLL_SHARED2,
337 PLL_LOCKTIME_PLL_SHARED3,
338 PLL_LOCKTIME_PLL_SPARE,
339 PLL_CON0_PLL_SHARED0,
340 PLL_CON1_PLL_SHARED0,
341 PLL_CON2_PLL_SHARED0,
342 PLL_CON3_PLL_SHARED0,
343 PLL_CON4_PLL_SHARED0,
344 PLL_CON0_PLL_SHARED1,
345 PLL_CON1_PLL_SHARED1,
346 PLL_CON2_PLL_SHARED1,
347 PLL_CON3_PLL_SHARED1,
348 PLL_CON4_PLL_SHARED1,
349 PLL_CON0_PLL_SHARED2,
350 PLL_CON1_PLL_SHARED2,
351 PLL_CON2_PLL_SHARED2,
352 PLL_CON3_PLL_SHARED2,
353 PLL_CON4_PLL_SHARED2,
354 PLL_CON0_PLL_SHARED3,
355 PLL_CON1_PLL_SHARED3,
356 PLL_CON2_PLL_SHARED3,
357 PLL_CON3_PLL_SHARED3,
358 PLL_CON4_PLL_SHARED3,
364 CMU_CMU_TOP_CONTROLLER_OPTION,
365 CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0,
366 CMU_HCHGEN_CLKMUX_CMU_BOOST,
367 CMU_HCHGEN_CLKMUX_TOP_BOOST,
369 POWER_FAIL_DETECT_PLL,
370 EARLY_WAKEUP_FORCED_0_ENABLE,
371 EARLY_WAKEUP_FORCED_1_ENABLE,
372 EARLY_WAKEUP_APM_CTRL,
373 EARLY_WAKEUP_CLUSTER0_CTRL,
374 EARLY_WAKEUP_DPU_CTRL,
375 EARLY_WAKEUP_CSIS_CTRL,
376 EARLY_WAKEUP_APM_DEST,
377 EARLY_WAKEUP_CLUSTER0_DEST,
378 EARLY_WAKEUP_DPU_DEST,
379 EARLY_WAKEUP_CSIS_DEST,
380 EARLY_WAKEUP_SW_TRIG_APM,
381 EARLY_WAKEUP_SW_TRIG_APM_SET,
382 EARLY_WAKEUP_SW_TRIG_APM_CLEAR,
383 EARLY_WAKEUP_SW_TRIG_CLUSTER0,
384 EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET,
385 EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR,
386 EARLY_WAKEUP_SW_TRIG_DPU,
387 EARLY_WAKEUP_SW_TRIG_DPU_SET,
388 EARLY_WAKEUP_SW_TRIG_DPU_CLEAR,
389 EARLY_WAKEUP_SW_TRIG_CSIS,
390 EARLY_WAKEUP_SW_TRIG_CSIS_SET,
391 EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR,
392 CLK_CON_MUX_MUX_CLKCMU_BO_BUS,
393 CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
394 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,
395 CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS,
396 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
397 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
398 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
399 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
400 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,
401 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,
402 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6,
403 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7,
404 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
405 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1,
406 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
407 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
408 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
409 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
410 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
411 CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS,
412 CLK_CON_MUX_MUX_CLKCMU_DISP_BUS,
413 CLK_CON_MUX_MUX_CLKCMU_DNS_BUS,
414 CLK_CON_MUX_MUX_CLKCMU_DPU_BUS,
415 CLK_CON_MUX_MUX_CLKCMU_EH_BUS,
416 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
417 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
418 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA,
419 CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD,
420 CLK_CON_MUX_MUX_CLKCMU_G3D_GLB,
421 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
422 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0,
423 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1,
424 CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC,
425 CLK_CON_MUX_MUX_CLKCMU_HPM,
426 CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS,
427 CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
428 CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
429 CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG,
430 CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS,
431 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,
432 CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS,
433 CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD,
434 CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE,
435 CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
436 CLK_CON_MUX_MUX_CLKCMU_IPP_BUS,
437 CLK_CON_MUX_MUX_CLKCMU_ITP_BUS,
438 CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC,
439 CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC,
440 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
441 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
442 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
443 CLK_CON_MUX_MUX_CLKCMU_MISC_BUS,
444 CLK_CON_MUX_MUX_CLKCMU_MISC_SSS,
445 CLK_CON_MUX_MUX_CLKCMU_PDP_BUS,
446 CLK_CON_MUX_MUX_CLKCMU_PDP_VRA,
447 CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
448 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
449 CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
450 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
451 CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
452 CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1,
453 CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF,
454 CLK_CON_MUX_MUX_CLKCMU_TPU_BUS,
455 CLK_CON_MUX_MUX_CLKCMU_TPU_TPU,
456 CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL,
457 CLK_CON_MUX_MUX_CLKCMU_TPU_UART,
458 CLK_CON_MUX_MUX_CMU_CMUREF,
459 CLK_CON_DIV_CLKCMU_BO_BUS,
460 CLK_CON_DIV_CLKCMU_BUS0_BUS,
461 CLK_CON_DIV_CLKCMU_BUS1_BUS,
462 CLK_CON_DIV_CLKCMU_BUS2_BUS,
463 CLK_CON_DIV_CLKCMU_CIS_CLK0,
464 CLK_CON_DIV_CLKCMU_CIS_CLK1,
465 CLK_CON_DIV_CLKCMU_CIS_CLK2,
466 CLK_CON_DIV_CLKCMU_CIS_CLK3,
467 CLK_CON_DIV_CLKCMU_CIS_CLK4,
468 CLK_CON_DIV_CLKCMU_CIS_CLK5,
469 CLK_CON_DIV_CLKCMU_CIS_CLK6,
470 CLK_CON_DIV_CLKCMU_CIS_CLK7,
471 CLK_CON_DIV_CLKCMU_CORE_BUS,
472 CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
473 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
474 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
475 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
476 CLK_CON_DIV_CLKCMU_CSIS_BUS,
477 CLK_CON_DIV_CLKCMU_DISP_BUS,
478 CLK_CON_DIV_CLKCMU_DNS_BUS,
479 CLK_CON_DIV_CLKCMU_DPU_BUS,
480 CLK_CON_DIV_CLKCMU_EH_BUS,
481 CLK_CON_DIV_CLKCMU_G2D_G2D,
482 CLK_CON_DIV_CLKCMU_G2D_MSCL,
483 CLK_CON_DIV_CLKCMU_G3AA_G3AA,
484 CLK_CON_DIV_CLKCMU_G3D_BUSD,
485 CLK_CON_DIV_CLKCMU_G3D_GLB,
486 CLK_CON_DIV_CLKCMU_G3D_SWITCH,
487 CLK_CON_DIV_CLKCMU_GDC_GDC0,
488 CLK_CON_DIV_CLKCMU_GDC_GDC1,
489 CLK_CON_DIV_CLKCMU_GDC_SCSC,
490 CLK_CON_DIV_CLKCMU_HPM,
491 CLK_CON_DIV_CLKCMU_HSI0_BUS,
492 CLK_CON_DIV_CLKCMU_HSI0_DPGTC,
493 CLK_CON_DIV_CLKCMU_HSI0_USB31DRD,
494 CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG,
495 CLK_CON_DIV_CLKCMU_HSI1_BUS,
496 CLK_CON_DIV_CLKCMU_HSI1_PCIE,
497 CLK_CON_DIV_CLKCMU_HSI2_BUS,
498 CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD,
499 CLK_CON_DIV_CLKCMU_HSI2_PCIE,
500 CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD,
501 CLK_CON_DIV_CLKCMU_IPP_BUS,
502 CLK_CON_DIV_CLKCMU_ITP_BUS,
503 CLK_CON_DIV_CLKCMU_MCSC_ITSC,
504 CLK_CON_DIV_CLKCMU_MCSC_MCSC,
505 CLK_CON_DIV_CLKCMU_MFC_MFC,
506 CLK_CON_DIV_CLKCMU_MIF_BUSP,
507 CLK_CON_DIV_CLKCMU_MISC_BUS,
508 CLK_CON_DIV_CLKCMU_MISC_SSS,
509 CLK_CON_DIV_CLKCMU_OTP,
510 CLK_CON_DIV_CLKCMU_PDP_BUS,
511 CLK_CON_DIV_CLKCMU_PDP_VRA,
512 CLK_CON_DIV_CLKCMU_PERIC0_BUS,
513 CLK_CON_DIV_CLKCMU_PERIC0_IP,
514 CLK_CON_DIV_CLKCMU_PERIC1_BUS,
515 CLK_CON_DIV_CLKCMU_PERIC1_IP,
516 CLK_CON_DIV_CLKCMU_TNR_BUS,
517 CLK_CON_DIV_CLKCMU_TPU_BUS,
518 CLK_CON_DIV_CLKCMU_TPU_TPU,
519 CLK_CON_DIV_CLKCMU_TPU_TPUCTL,
520 CLK_CON_DIV_CLKCMU_TPU_UART,
521 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
522 CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
523 CLK_CON_DIV_PLL_SHARED0_DIV2,
524 CLK_CON_DIV_PLL_SHARED0_DIV3,
525 CLK_CON_DIV_PLL_SHARED0_DIV4,
526 CLK_CON_DIV_PLL_SHARED0_DIV5,
527 CLK_CON_DIV_PLL_SHARED1_DIV2,
528 CLK_CON_DIV_PLL_SHARED1_DIV3,
529 CLK_CON_DIV_PLL_SHARED1_DIV4,
530 CLK_CON_DIV_PLL_SHARED2_DIV2,
531 CLK_CON_DIV_PLL_SHARED3_DIV2,
532 CLK_CON_GAT_CLKCMU_BUS0_BOOST,
533 CLK_CON_GAT_CLKCMU_BUS1_BOOST,
534 CLK_CON_GAT_CLKCMU_BUS2_BOOST,
535 CLK_CON_GAT_CLKCMU_CORE_BOOST,
536 CLK_CON_GAT_CLKCMU_CPUCL0_BOOST,
537 CLK_CON_GAT_CLKCMU_CPUCL1_BOOST,
538 CLK_CON_GAT_CLKCMU_CPUCL2_BOOST,
539 CLK_CON_GAT_CLKCMU_MIF_BOOST,
540 CLK_CON_GAT_CLKCMU_MIF_SWITCH,
541 CLK_CON_GAT_GATE_CLKCMU_BO_BUS,
542 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS,
543 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS,
544 CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS,
545 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
546 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
547 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
548 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
549 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,
550 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,
551 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6,
552 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7,
553 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
554 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
555 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
556 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
557 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
558 CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
559 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS,
560 CLK_CON_GAT_GATE_CLKCMU_DISP_BUS,
561 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS,
562 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS,
563 CLK_CON_GAT_GATE_CLKCMU_EH_BUS,
564 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
565 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
566 CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA,
567 CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD,
568 CLK_CON_GAT_GATE_CLKCMU_G3D_GLB,
569 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
570 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0,
571 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1,
572 CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC,
573 CLK_CON_GAT_GATE_CLKCMU_HPM,
574 CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS,
575 CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
576 CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
577 CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,
578 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS,
579 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
580 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS,
581 CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,
582 CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE,
583 CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,
584 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS,
585 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS,
586 CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC,
587 CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC,
588 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,
589 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
590 CLK_CON_GAT_GATE_CLKCMU_MISC_BUS,
591 CLK_CON_GAT_GATE_CLKCMU_MISC_SSS,
592 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS,
593 CLK_CON_GAT_GATE_CLKCMU_PDP_VRA,
594 CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
595 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
596 CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
597 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
598 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS,
599 CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF,
600 CLK_CON_GAT_GATE_CLKCMU_TPU_BUS,
601 CLK_CON_GAT_GATE_CLKCMU_TPU_TPU,
602 CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL,
603 CLK_CON_GAT_GATE_CLKCMU_TPU_UART,
604 DMYQCH_CON_CMU_TOP_CMUREF_QCH,
605 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0,
606 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1,
607 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2,
608 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3,
609 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4,
610 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5,
611 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6,
612 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7,
614 QUEUE_CTRL_REG_BLK_CMU_CMU_TOP,
615 QUEUE_ENTRY0_BLK_CMU_CMU_TOP,
616 QUEUE_ENTRY1_BLK_CMU_CMU_TOP,
617 QUEUE_ENTRY2_BLK_CMU_CMU_TOP,
618 QUEUE_ENTRY3_BLK_CMU_CMU_TOP,
619 QUEUE_ENTRY4_BLK_CMU_CMU_TOP,
620 QUEUE_ENTRY5_BLK_CMU_CMU_TOP,
621 QUEUE_ENTRY6_BLK_CMU_CMU_TOP,
622 QUEUE_ENTRY7_BLK_CMU_CMU_TOP,
623 MIFMIRROR_QUEUE_CTRL_REG,
624 MIFMIRROR_QUEUE_ENTRY0,
625 MIFMIRROR_QUEUE_ENTRY1,
626 MIFMIRROR_QUEUE_ENTRY2,
627 MIFMIRROR_QUEUE_ENTRY3,
628 MIFMIRROR_QUEUE_ENTRY4,
629 MIFMIRROR_QUEUE_ENTRY5,
630 MIFMIRROR_QUEUE_ENTRY6,
631 MIFMIRROR_QUEUE_ENTRY7,
632 MIFMIRROR_QUEUE_BUSY,
633 GENERALIO_ACD_CHANNEL_0,
634 GENERALIO_ACD_CHANNEL_1,
635 GENERALIO_ACD_CHANNEL_2,
636 GENERALIO_ACD_CHANNEL_3,
640 static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = {
641 /* CMU_TOP_PURECLKCOMP */
642 PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
643 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
645 PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
646 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,
648 PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
649 PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2,
651 PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
652 PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3,
654 PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk",
655 PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE,
659 /* List of parent clocks for Muxes in CMU_TOP */
660 PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" };
661 PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" };
662 PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" };
663 PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" };
664 PNAME(mout_pll_spare_p) = { "oscclk", "fout_spare_pll" };
665 PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3",
666 "fout_shared3_pll", "dout_cmu_shared1_div3",
667 "dout_cmu_shared0_div4",
668 "dout_cmu_shared1_div4",
669 "fout_spare_pll", "oscclk" };
670 PNAME(mout_cmu_bus0_bus_p) = { "dout_cmu_shared0_div4",
671 "dout_cmu_shared1_div4",
672 "dout_cmu_shared2_div2",
673 "dout_cmu_shared3_div2",
674 "fout_spare_pll", "oscclk",
675 "oscclk", "oscclk" };
676 PNAME(mout_cmu_bus1_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
677 "dout_cmu_shared1_div3",
678 "dout_cmu_shared0_div4",
679 "dout_cmu_shared1_div4",
680 "dout_cmu_shared2_div2",
681 "fout_spare_pll", "oscclk" };
682 PNAME(mout_cmu_bus2_bus_p) = { "dout_cmu_shared0_div2",
683 "dout_cmu_shared1_div2",
684 "fout_shared2_pll", "fout_shared3_pll",
685 "dout_cmu_shared0_div3",
686 "dout_cmu_shared1_div3",
687 "dout_cmu_shared0_div5", "fout_spare_pll" };
688 PNAME(mout_cmu_cis_clk0_7_p) = { "oscclk", "dout_cmu_shared0_div3",
689 "dout_cmu_shared1_div3",
690 "dout_cmu_shared2_div2",
691 "dout_cmu_shared3_div2", "fout_spare_pll",
692 "oscclk", "oscclk" };
693 PNAME(mout_cmu_cmu_boost_p) = { "dout_cmu_shared0_div4",
694 "dout_cmu_shared1_div4",
695 "dout_cmu_shared2_div2",
696 "dout_cmu_shared3_div2" };
697 PNAME(mout_cmu_cmu_boost_option1_p) = { "dout_cmu_cmu_boost",
698 "gout_cmu_boost_option1" };
699 PNAME(mout_cmu_core_bus_p) = { "dout_cmu_shared0_div2",
700 "dout_cmu_shared1_div2",
701 "fout_shared2_pll", "fout_shared3_pll",
702 "dout_cmu_shared0_div3",
703 "dout_cmu_shared1_div3",
704 "dout_cmu_shared0_div5", "fout_spare_pll" };
705 PNAME(mout_cmu_cpucl0_dbg_p) = { "fout_shared2_pll", "fout_shared3_pll",
706 "dout_cmu_shared0_div4",
707 "dout_cmu_shared1_div4",
708 "dout_cmu_shared2_div2", "fout_spare_pll",
709 "oscclk", "oscclk" };
710 PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2",
711 "dout_cmu_shared1_div2", "fout_shared2_pll",
712 "fout_shared3_pll", "dout_cmu_shared0_div3",
713 "dout_cmu_shared1_div3", "fout_spare_pll" };
714 PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2",
715 "dout_cmu_shared1_div2", "fout_shared2_pll",
716 "fout_shared3_pll", "dout_cmu_shared0_div3",
717 "dout_cmu_shared1_div3", "fout_spare_pll" };
718 PNAME(mout_cmu_cpucl2_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2",
719 "dout_cmu_shared1_div2", "fout_shared2_pll",
720 "fout_shared3_pll", "dout_cmu_shared0_div3",
721 "dout_cmu_shared1_div3", "fout_spare_pll" };
722 PNAME(mout_cmu_csis_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
723 "dout_cmu_shared1_div3",
724 "dout_cmu_shared0_div4",
725 "dout_cmu_shared1_div4",
726 "dout_cmu_shared2_div2",
727 "fout_spare_pll", "oscclk" };
728 PNAME(mout_cmu_disp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
729 "dout_cmu_shared1_div3",
730 "dout_cmu_shared0_div4",
731 "dout_cmu_shared1_div4",
732 "dout_cmu_shared2_div2",
733 "fout_spare_pll", "oscclk" };
734 PNAME(mout_cmu_dns_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
735 "dout_cmu_shared1_div3",
736 "dout_cmu_shared0_div4",
737 "dout_cmu_shared1_div4",
738 "dout_cmu_shared2_div2",
739 "fout_spare_pll", "oscclk" };
740 PNAME(mout_cmu_dpu_p) = { "dout_cmu_shared0_div3",
742 "dout_cmu_shared1_div3",
743 "dout_cmu_shared0_div4",
744 "dout_cmu_shared1_div4",
745 "dout_cmu_shared2_div2",
746 "fout_spare_pll", "oscclk" };
747 PNAME(mout_cmu_eh_bus_p) = { "dout_cmu_shared0_div2",
748 "dout_cmu_shared1_div2",
749 "fout_shared2_pll", "fout_shared3_pll",
750 "dout_cmu_shared0_div3",
751 "dout_cmu_shared1_div3",
752 "dout_cmu_shared0_div5", "fout_spare_pll" };
753 PNAME(mout_cmu_g2d_g2d_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
754 "dout_cmu_shared1_div3",
755 "dout_cmu_shared0_div4",
756 "dout_cmu_shared1_div4",
757 "dout_cmu_shared2_div2",
758 "fout_spare_pll", "oscclk" };
759 PNAME(mout_cmu_g2d_mscl_p) = { "dout_cmu_shared0_div4",
760 "dout_cmu_shared1_div4",
761 "dout_cmu_shared2_div2",
762 "dout_cmu_shared3_div2",
763 "fout_spare_pll", "oscclk",
764 "oscclk", "oscclk" };
765 PNAME(mout_cmu_g3aa_g3aa_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
766 "dout_cmu_shared1_div3",
767 "dout_cmu_shared0_div4",
768 "dout_cmu_shared1_div4",
769 "dout_cmu_shared2_div2",
770 "fout_spare_pll", "oscclk" };
771 PNAME(mout_cmu_g3d_busd_p) = { "dout_cmu_shared0_div2",
772 "dout_cmu_shared1_div2",
773 "fout_shared2_pll", "fout_shared3_pll",
774 "dout_cmu_shared0_div3",
775 "dout_cmu_shared1_div3",
776 "dout_cmu_shared0_div4", "fout_spare_pll" };
777 PNAME(mout_cmu_g3d_glb_p) = { "dout_cmu_shared0_div2",
778 "dout_cmu_shared1_div2",
779 "fout_shared2_pll", "fout_shared3_pll",
780 "dout_cmu_shared0_div3",
781 "dout_cmu_shared1_div3",
782 "dout_cmu_shared0_div4", "fout_spare_pll" };
783 PNAME(mout_cmu_g3d_switch_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3",
784 "fout_shared3_pll", "dout_cmu_shared1_div3",
785 "dout_cmu_shared0_div4",
786 "dout_cmu_shared1_div4",
787 "fout_spare_pll", "fout_spare_pll"};
788 PNAME(mout_cmu_gdc_gdc0_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
789 "dout_cmu_shared1_div3",
790 "dout_cmu_shared0_div4",
791 "dout_cmu_shared1_div4",
792 "dout_cmu_shared2_div2",
793 "fout_spare_pll", "oscclk" };
794 PNAME(mout_cmu_gdc_gdc1_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
795 "dout_cmu_shared1_div3",
796 "dout_cmu_shared0_div4",
797 "dout_cmu_shared1_div4",
798 "dout_cmu_shared2_div2",
799 "fout_spare_pll", "oscclk" };
800 PNAME(mout_cmu_gdc_scsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
801 "dout_cmu_shared1_div3",
802 "dout_cmu_shared0_div4",
803 "dout_cmu_shared1_div4",
804 "dout_cmu_shared2_div2",
805 "fout_spare_pll", "oscclk" };
806 PNAME(mout_cmu_hpm_p) = { "oscclk", "dout_cmu_shared1_div3",
807 "dout_cmu_shared0_div4",
808 "dout_cmu_shared2_div2" };
809 PNAME(mout_cmu_hsi0_bus_p) = { "dout_cmu_shared0_div4",
810 "dout_cmu_shared1_div4",
811 "dout_cmu_shared2_div2",
812 "dout_cmu_shared3_div2",
813 "fout_spare_pll", "oscclk",
814 "oscclk", "oscclk" };
815 PNAME(mout_cmu_hsi0_dpgtc_p) = { "oscclk", "dout_cmu_shared0_div4",
816 "dout_cmu_shared2_div2", "fout_spare_pll" };
817 PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_cmu_shared2_div2" };
818 PNAME(mout_cmu_hsi0_usbdpdbg_p) = { "oscclk", "dout_cmu_shared2_div2" };
819 PNAME(mout_cmu_hsi1_bus_p) = { "dout_cmu_shared0_div4",
820 "dout_cmu_shared1_div4",
821 "dout_cmu_shared2_div2",
822 "dout_cmu_shared3_div2",
824 PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "dout_cmu_shared2_div2" };
825 PNAME(mout_cmu_hsi2_bus_p) = { "dout_cmu_shared0_div4",
826 "dout_cmu_shared1_div4",
827 "dout_cmu_shared2_div2",
828 "dout_cmu_shared3_div2",
829 "fout_spare_pll", "oscclk",
830 "oscclk", "oscclk" };
831 PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll",
832 "dout_cmu_shared0_div4", "fout_spare_pll" };
833 PNAME(mout_cmu_hsi2_pcie0_p) = { "oscclk", "dout_cmu_shared2_div2" };
834 PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_cmu_shared0_div4",
835 "dout_cmu_shared2_div2", "fout_spare_pll" };
836 PNAME(mout_cmu_ipp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
837 "dout_cmu_shared1_div3",
838 "dout_cmu_shared0_div4",
839 "dout_cmu_shared1_div4",
840 "dout_cmu_shared2_div2",
841 "fout_spare_pll", "oscclk" };
842 PNAME(mout_cmu_itp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
843 "dout_cmu_shared1_div3",
844 "dout_cmu_shared0_div4",
845 "dout_cmu_shared1_div4",
846 "dout_cmu_shared2_div2",
847 "fout_spare_pll", "oscclk" };
848 PNAME(mout_cmu_mcsc_itsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
849 "dout_cmu_shared1_div3",
850 "dout_cmu_shared0_div4",
851 "dout_cmu_shared1_div4",
852 "dout_cmu_shared2_div2",
853 "fout_spare_pll", "oscclk" };
854 PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
855 "dout_cmu_shared1_div3",
856 "dout_cmu_shared0_div4",
857 "dout_cmu_shared1_div4",
858 "dout_cmu_shared2_div2",
859 "fout_spare_pll", "oscclk" };
860 PNAME(mout_cmu_mfc_mfc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
861 "dout_cmu_shared0_div4",
862 "dout_cmu_shared1_div4",
863 "dout_cmu_shared2_div2", "fout_spare_pll",
864 "oscclk", "oscclk" };
865 PNAME(mout_cmu_mif_busp_p) = { "dout_cmu_shared0_div4",
866 "dout_cmu_shared1_div4",
867 "dout_cmu_shared0_div5", "fout_spare_pll" };
868 PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
869 "dout_cmu_shared0_div2",
870 "dout_cmu_shared1_div2",
871 "fout_shared2_pll", "dout_cmu_shared0_div3",
872 "fout_shared3_pll", "fout_spare_pll" };
873 PNAME(mout_cmu_misc_bus_p) = { "dout_cmu_shared0_div4",
874 "dout_cmu_shared2_div2",
875 "dout_cmu_shared3_div2", "fout_spare_pll" };
876 PNAME(mout_cmu_misc_sss_p) = { "dout_cmu_shared0_div4",
877 "dout_cmu_shared2_div2",
878 "dout_cmu_shared3_div2", "fout_spare_pll" };
879 PNAME(mout_cmu_pdp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
880 "dout_cmu_shared1_div3",
881 "dout_cmu_shared0_div4",
882 "dout_cmu_shared1_div4",
883 "dout_cmu_shared2_div2",
884 "fout_spare_pll", "oscclk" };
885 PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3",
886 "fout_shared3_pll", "dout_cmu_shared1_div3",
887 "dout_cmu_shared0_div4",
888 "dout_cmu_shared1_div4",
889 "fout_spare_pll", "oscclk" };
890 PNAME(mout_cmu_peric0_bus_p) = { "dout_cmu_shared0_div4",
891 "dout_cmu_shared2_div2",
892 "dout_cmu_shared3_div2", "fout_spare_pll" };
893 PNAME(mout_cmu_peric0_ip_p) = { "dout_cmu_shared0_div4",
894 "dout_cmu_shared2_div2",
895 "dout_cmu_shared3_div2", "fout_spare_pll" };
896 PNAME(mout_cmu_peric1_bus_p) = { "dout_cmu_shared0_div4",
897 "dout_cmu_shared2_div2",
898 "dout_cmu_shared3_div2", "fout_spare_pll" };
899 PNAME(mout_cmu_peric1_ip_p) = { "dout_cmu_shared0_div4",
900 "dout_cmu_shared2_div2",
901 "dout_cmu_shared3_div2", "fout_spare_pll" };
902 PNAME(mout_cmu_tnr_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
903 "dout_cmu_shared1_div3",
904 "dout_cmu_shared0_div4",
905 "dout_cmu_shared1_div4",
906 "dout_cmu_shared2_div2",
907 "fout_spare_pll", "oscclk" };
908 PNAME(mout_cmu_top_boost_option1_p) = { "oscclk",
909 "gout_cmu_boost_option1" };
910 PNAME(mout_cmu_top_cmuref_p) = { "dout_cmu_shared0_div4",
911 "dout_cmu_shared1_div4",
912 "dout_cmu_shared2_div2",
913 "dout_cmu_shared3_div2" };
914 PNAME(mout_cmu_tpu_bus_p) = { "dout_cmu_shared0_div2",
915 "dout_cmu_shared1_div2",
918 "dout_cmu_shared0_div3",
919 "dout_cmu_shared1_div3",
920 "dout_cmu_shared0_div4",
922 PNAME(mout_cmu_tpu_tpu_p) = { "dout_cmu_shared0_div2",
923 "dout_cmu_shared1_div2",
926 "dout_cmu_shared0_div3",
927 "dout_cmu_shared1_div3",
928 "dout_cmu_shared0_div4", "fout_spare_pll" };
929 PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_cmu_shared0_div2",
930 "dout_cmu_shared1_div2",
931 "fout_shared2_pll", "fout_shared3_pll",
932 "dout_cmu_shared0_div3",
933 "dout_cmu_shared1_div3",
934 "dout_cmu_shared0_div4", "fout_spare_pll" };
935 PNAME(mout_cmu_tpu_uart_p) = { "dout_cmu_shared0_div4",
936 "dout_cmu_shared2_div2",
937 "dout_cmu_shared3_div2", "fout_spare_pll" };
938 PNAME(mout_cmu_cmuref_p) = { "mout_cmu_top_boost_option1",
942 * Register name to clock name mangling strategy used in this file
944 * Replace PLL_CON0_PLL with CLK_MOUT_PLL and mout_pll
945 * Replace CLK_CON_MUX_MUX_CLKCMU with CLK_MOUT_CMU and mout_cmu
946 * Replace CLK_CON_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu
947 * Replace CLK_CON_DIV_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu
948 * Replace CLK_CON_GAT_CLKCMU with CLK_GOUT_CMU and gout_cmu
949 * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu
951 * For gates remove _UID _BLK _IPCLKPORT and _RSTNSYNC
954 static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = {
955 MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p,
956 PLL_CON0_PLL_SHARED0, 4, 1),
957 MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p,
958 PLL_CON0_PLL_SHARED1, 4, 1),
959 MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p,
960 PLL_CON0_PLL_SHARED2, 4, 1),
961 MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p,
962 PLL_CON0_PLL_SHARED3, 4, 1),
963 MUX(CLK_MOUT_PLL_SPARE, "mout_pll_spare", mout_pll_spare_p,
964 PLL_CON0_PLL_SPARE, 4, 1),
965 MUX(CLK_MOUT_CMU_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p,
966 CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 3),
967 MUX(CLK_MOUT_CMU_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p,
968 CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 3),
969 MUX(CLK_MOUT_CMU_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p,
970 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 3),
971 MUX(CLK_MOUT_CMU_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p,
972 CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 3),
973 MUX(CLK_MOUT_CMU_CIS_CLK0, "mout_cmu_cis_clk0", mout_cmu_cis_clk0_7_p,
974 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 3),
975 MUX(CLK_MOUT_CMU_CIS_CLK1, "mout_cmu_cis_clk1", mout_cmu_cis_clk0_7_p,
976 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 3),
977 MUX(CLK_MOUT_CMU_CIS_CLK2, "mout_cmu_cis_clk2", mout_cmu_cis_clk0_7_p,
978 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 3),
979 MUX(CLK_MOUT_CMU_CIS_CLK3, "mout_cmu_cis_clk3", mout_cmu_cis_clk0_7_p,
980 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 3),
981 MUX(CLK_MOUT_CMU_CIS_CLK4, "mout_cmu_cis_clk4", mout_cmu_cis_clk0_7_p,
982 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 3),
983 MUX(CLK_MOUT_CMU_CIS_CLK5, "mout_cmu_cis_clk5", mout_cmu_cis_clk0_7_p,
984 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 3),
985 MUX(CLK_MOUT_CMU_CIS_CLK6, "mout_cmu_cis_clk6", mout_cmu_cis_clk0_7_p,
986 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 0, 3),
987 MUX(CLK_MOUT_CMU_CIS_CLK7, "mout_cmu_cis_clk7", mout_cmu_cis_clk0_7_p,
988 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 0, 3),
989 MUX(CLK_MOUT_CMU_CMU_BOOST, "mout_cmu_cmu_boost", mout_cmu_cmu_boost_p,
990 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
991 MUX(CLK_MOUT_CMU_BOOST_OPTION1, "mout_cmu_boost_option1",
992 mout_cmu_cmu_boost_option1_p,
993 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 0, 1),
994 MUX(CLK_MOUT_CMU_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p,
995 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
996 MUX(CLK_MOUT_CMU_CPUCL0_DBG, "mout_cmu_cpucl0_dbg",
997 mout_cmu_cpucl0_dbg_p, CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3),
998 MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch",
999 mout_cmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
1001 MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch",
1002 mout_cmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
1004 MUX(CLK_MOUT_CMU_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch",
1005 mout_cmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
1007 MUX(CLK_MOUT_CMU_CSIS_BUS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p,
1008 CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 3),
1009 MUX(CLK_MOUT_CMU_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p,
1010 CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 3),
1011 MUX(CLK_MOUT_CMU_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p,
1012 CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 3),
1013 MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p,
1014 CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 3),
1015 MUX(CLK_MOUT_CMU_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p,
1016 CLK_CON_MUX_MUX_CLKCMU_EH_BUS, 0, 3),
1017 MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p,
1018 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3),
1019 MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p,
1020 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 3),
1021 MUX(CLK_MOUT_CMU_G3AA_G3AA, "mout_cmu_g3aa_g3aa", mout_cmu_g3aa_g3aa_p,
1022 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 3),
1023 MUX(CLK_MOUT_CMU_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p,
1024 CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 3),
1025 MUX(CLK_MOUT_CMU_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p,
1026 CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 3),
1027 MUX(CLK_MOUT_CMU_G3D_SWITCH, "mout_cmu_g3d_switch",
1028 mout_cmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 3),
1029 MUX(CLK_MOUT_CMU_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p,
1030 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 3),
1031 MUX(CLK_MOUT_CMU_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p,
1032 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 3),
1033 MUX(CLK_MOUT_CMU_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p,
1034 CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 3),
1035 MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p,
1036 CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
1037 MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p,
1038 CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 3),
1039 MUX(CLK_MOUT_CMU_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc",
1040 mout_cmu_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2),
1041 MUX(CLK_MOUT_CMU_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd",
1042 mout_cmu_hsi0_usb31drd_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
1044 MUX(CLK_MOUT_CMU_HSI0_USBDPDBG, "mout_cmu_hsi0_usbdpdbg",
1045 mout_cmu_hsi0_usbdpdbg_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG,
1047 MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p,
1048 CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3),
1049 MUX(CLK_MOUT_CMU_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p,
1050 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1),
1051 MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p,
1052 CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 3),
1053 MUX(CLK_MOUT_CMU_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card",
1054 mout_cmu_hsi2_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD,
1056 MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p,
1057 CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 1),
1058 MUX(CLK_MOUT_CMU_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd",
1059 mout_cmu_hsi2_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
1061 MUX(CLK_MOUT_CMU_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p,
1062 CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 3),
1063 MUX(CLK_MOUT_CMU_ITP_BUS, "mout_cmu_itp_bus", mout_cmu_itp_bus_p,
1064 CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 3),
1065 MUX(CLK_MOUT_CMU_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p,
1066 CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 3),
1067 MUX(CLK_MOUT_CMU_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p,
1068 CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 3),
1069 MUX(CLK_MOUT_CMU_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p,
1070 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 3),
1071 MUX(CLK_MOUT_CMU_MIF_BUSP, "mout_cmu_mif_busp", mout_cmu_mif_busp_p,
1072 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
1073 MUX(CLK_MOUT_CMU_MIF_SWITCH, "mout_cmu_mif_switch",
1074 mout_cmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
1075 MUX(CLK_MOUT_CMU_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p,
1076 CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2),
1077 MUX(CLK_MOUT_CMU_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p,
1078 CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2),
1079 MUX(CLK_MOUT_CMU_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p,
1080 CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 3),
1081 MUX(CLK_MOUT_CMU_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p,
1082 CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 3),
1083 MUX(CLK_MOUT_CMU_PERIC0_BUS, "mout_cmu_peric0_bus",
1084 mout_cmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
1085 MUX(CLK_MOUT_CMU_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p,
1086 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
1087 MUX(CLK_MOUT_CMU_PERIC1_BUS, "mout_cmu_peric1_bus",
1088 mout_cmu_peric1_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 2),
1089 MUX(CLK_MOUT_CMU_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p,
1090 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 2),
1091 MUX(CLK_MOUT_CMU_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p,
1092 CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3),
1093 MUX(CLK_MOUT_CMU_TOP_BOOST_OPTION1, "mout_cmu_top_boost_option1",
1094 mout_cmu_top_boost_option1_p,
1095 CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 0, 1),
1096 MUX(CLK_MOUT_CMU_TOP_CMUREF, "mout_cmu_top_cmuref",
1097 mout_cmu_top_cmuref_p, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 0, 2),
1098 MUX(CLK_MOUT_CMU_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p,
1099 CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 3),
1100 MUX(CLK_MOUT_CMU_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p,
1101 CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 3),
1102 MUX(CLK_MOUT_CMU_TPU_TPUCTL, "mout_cmu_tpu_tpuctl",
1103 mout_cmu_tpu_tpuctl_p, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 3),
1104 MUX(CLK_MOUT_CMU_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p,
1105 CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2),
1106 MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref", mout_cmu_cmuref_p,
1107 CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
1110 static const struct samsung_div_clock cmu_top_div_clks[] __initconst = {
1111 DIV(CLK_DOUT_CMU_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus",
1112 CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4),
1113 DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus",
1114 CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),
1115 DIV(CLK_DOUT_CMU_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus",
1116 CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
1117 DIV(CLK_DOUT_CMU_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus",
1118 CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4),
1119 DIV(CLK_DOUT_CMU_CIS_CLK0, "dout_cmu_cis_clk0", "gout_cmu_cis_clk0",
1120 CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5),
1121 DIV(CLK_DOUT_CMU_CIS_CLK1, "dout_cmu_cis_clk1", "gout_cmu_cis_clk1",
1122 CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5),
1123 DIV(CLK_DOUT_CMU_CIS_CLK2, "dout_cmu_cis_clk2", "gout_cmu_cis_clk2",
1124 CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5),
1125 DIV(CLK_DOUT_CMU_CIS_CLK3, "dout_cmu_cis_clk3", "gout_cmu_cis_clk3",
1126 CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5),
1127 DIV(CLK_DOUT_CMU_CIS_CLK4, "dout_cmu_cis_clk4", "gout_cmu_cis_clk4",
1128 CLK_CON_DIV_CLKCMU_CIS_CLK4, 0, 5),
1129 DIV(CLK_DOUT_CMU_CIS_CLK5, "dout_cmu_cis_clk5", "gout_cmu_cis_clk5",
1130 CLK_CON_DIV_CLKCMU_CIS_CLK5, 0, 5),
1131 DIV(CLK_DOUT_CMU_CIS_CLK6, "dout_cmu_cis_clk6", "gout_cmu_cis_clk6",
1132 CLK_CON_DIV_CLKCMU_CIS_CLK6, 0, 5),
1133 DIV(CLK_DOUT_CMU_CIS_CLK7, "dout_cmu_cis_clk7", "gout_cmu_cis_clk7",
1134 CLK_CON_DIV_CLKCMU_CIS_CLK7, 0, 5),
1135 DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
1136 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
1137 DIV(CLK_DOUT_CMU_CPUCL0_DBG, "dout_cmu_cpucl0_dbg",
1138 "gout_cmu_cpucl0_dbg", CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
1139 DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch",
1140 "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
1141 DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch",
1142 "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
1143 DIV(CLK_DOUT_CMU_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch",
1144 "gout_cmu_cpucl2_switch", CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
1145 DIV(CLK_DOUT_CMU_CSIS_BUS, "dout_cmu_csis_bus", "gout_cmu_csis_bus",
1146 CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),
1147 DIV(CLK_DOUT_CMU_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus",
1148 CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4),
1149 DIV(CLK_DOUT_CMU_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus",
1150 CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),
1151 DIV(CLK_DOUT_CMU_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus",
1152 CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4),
1153 DIV(CLK_DOUT_CMU_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus",
1154 CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4),
1155 DIV(CLK_DOUT_CMU_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d",
1156 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
1157 DIV(CLK_DOUT_CMU_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl",
1158 CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
1159 DIV(CLK_DOUT_CMU_G3AA_G3AA, "dout_cmu_g3aa_g3aa", "gout_cmu_g3aa_g3aa",
1160 CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),
1161 DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",
1162 CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),
1163 DIV(CLK_DOUT_CMU_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb",
1164 CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),
1165 DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_switch",
1166 "gout_cmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
1167 DIV(CLK_DOUT_CMU_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0",
1168 CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4),
1169 DIV(CLK_DOUT_CMU_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1",
1170 CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4),
1171 DIV(CLK_DOUT_CMU_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc",
1172 CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4),
1173 DIV(CLK_DOUT_CMU_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm",
1174 CLK_CON_DIV_CLKCMU_HPM, 0, 2),
1175 DIV(CLK_DOUT_CMU_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus",
1176 CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),
1177 DIV(CLK_DOUT_CMU_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc",
1178 "gout_cmu_hsi0_dpgtc", CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4),
1179 DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd",
1180 "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5),
1181 DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",
1182 CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4),
1183 DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie",
1184 CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3),
1185 DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",
1186 CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
1187 DIV(CLK_DOUT_CMU_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card",
1188 "gout_cmu_hsi2_mmc_card", CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9),
1189 DIV(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie",
1190 CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3),
1191 DIV(CLK_DOUT_CMU_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd",
1192 "gout_cmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4),
1193 DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",
1194 CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
1195 DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus",
1196 CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),
1197 DIV(CLK_DOUT_CMU_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc",
1198 CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4),
1199 DIV(CLK_DOUT_CMU_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc",
1200 CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4),
1201 DIV(CLK_DOUT_CMU_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc",
1202 CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
1203 DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_cmu_mif_busp", "gout_cmu_mif_busp",
1204 CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
1205 DIV(CLK_DOUT_CMU_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus",
1206 CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4),
1207 DIV(CLK_DOUT_CMU_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss",
1208 CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4),
1209 DIV(CLK_DOUT_CMU_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus",
1210 CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4),
1211 DIV(CLK_DOUT_CMU_PDP_VRA, "dout_cmu_pdp_vra", "gout_cmu_pdp_vra",
1212 CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4),
1213 DIV(CLK_DOUT_CMU_PERIC0_BUS, "dout_cmu_peric0_bus",
1214 "gout_cmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
1215 DIV(CLK_DOUT_CMU_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip",
1216 CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
1217 DIV(CLK_DOUT_CMU_PERIC1_BUS, "dout_cmu_peric1_bus",
1218 "gout_cmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
1219 DIV(CLK_DOUT_CMU_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip",
1220 CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
1221 DIV(CLK_DOUT_CMU_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus",
1222 CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
1223 DIV(CLK_DOUT_CMU_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus",
1224 CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4),
1225 DIV(CLK_DOUT_CMU_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu",
1226 CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4),
1227 DIV(CLK_DOUT_CMU_TPU_TPUCTL, "dout_cmu_tpu_tpuctl",
1228 "gout_cmu_tpu_tpuctl", CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4),
1229 DIV(CLK_DOUT_CMU_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart",
1230 CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4),
1231 DIV(CLK_DOUT_CMU_CMU_BOOST, "dout_cmu_cmu_boost", "gout_cmu_cmu_boost",
1232 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
1233 DIV(CLK_DOUT_CMU_CMU_CMUREF, "dout_cmu_cmuref", "gout_cmu_cmuref",
1234 CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2),
1235 DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2",
1236 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
1237 DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3",
1238 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
1239 DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4",
1240 "dout_cmu_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
1241 DIV(CLK_DOUT_CMU_SHARED0_DIV5, "dout_cmu_shared0_div5",
1242 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
1243 DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2",
1244 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
1245 DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3",
1246 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
1247 DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4",
1248 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
1249 DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2",
1250 "mout_pll_shared2", CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
1251 DIV(CLK_DOUT_CMU_SHARED3_DIV2, "dout_cmu_shared3_div2",
1252 "mout_pll_shared3", CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1),
1255 static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = {
1256 FFACTOR(CLK_DOUT_CMU_HSI0_USBDPDBG, "dout_cmu_hsi0_usbdpdbg",
1257 "gout_cmu_hsi0_usbdpdbg", 1, 4, 0),
1258 FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0),
1261 static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = {
1262 GATE(CLK_GOUT_CMU_BUS0_BOOST, "gout_cmu_bus0_boost",
1263 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0),
1264 GATE(CLK_GOUT_CMU_BUS1_BOOST, "gout_cmu_bus1_boost",
1265 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS1_BOOST, 21, 0, 0),
1266 GATE(CLK_GOUT_CMU_BUS2_BOOST, "gout_cmu_bus2_boost",
1267 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS2_BOOST, 21, 0, 0),
1268 GATE(CLK_GOUT_CMU_CORE_BOOST, "gout_cmu_core_boost",
1269 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CORE_BOOST, 21, 0, 0),
1270 GATE(CLK_GOUT_CMU_CPUCL0_BOOST, "gout_cmu_cpucl0_boost",
1271 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL0_BOOST,
1273 GATE(CLK_GOUT_CMU_CPUCL1_BOOST, "gout_cmu_cpucl1_boost",
1274 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL1_BOOST,
1276 GATE(CLK_GOUT_CMU_CPUCL2_BOOST, "gout_cmu_cpucl2_boost",
1277 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL2_BOOST,
1279 GATE(CLK_GOUT_CMU_MIF_BOOST, "gout_cmu_mif_boost",
1280 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_MIF_BOOST,
1282 GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch",
1283 "mout_cmu_mif_switch", CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),
1284 GATE(CLK_GOUT_CMU_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",
1285 CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0),
1286 GATE(CLK_GOUT_CMU_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
1287 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0),
1288 GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
1289 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0),
1290 GATE(CLK_GOUT_CMU_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus",
1291 CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0),
1292 GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0",
1293 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0),
1294 GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1",
1295 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0),
1296 GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2",
1297 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0),
1298 GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3",
1299 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0),
1300 GATE(CLK_GOUT_CMU_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4",
1301 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0),
1302 GATE(CLK_GOUT_CMU_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5",
1303 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0),
1304 GATE(CLK_GOUT_CMU_CIS_CLK6, "gout_cmu_cis_clk6", "mout_cmu_cis_clk6",
1305 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 21, 0, 0),
1306 GATE(CLK_GOUT_CMU_CIS_CLK7, "gout_cmu_cis_clk7", "mout_cmu_cis_clk7",
1307 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 21, 0, 0),
1308 GATE(CLK_GOUT_CMU_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_cmu_boost",
1309 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0),
1310 GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
1311 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
1312 GATE(CLK_GOUT_CMU_CPUCL0_DBG, "gout_cmu_cpucl0_dbg",
1313 "mout_cmu_cpucl0_dbg", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
1315 GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch",
1316 "mout_cmu_cpucl0_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
1318 GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch",
1319 "mout_cmu_cpucl1_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
1321 GATE(CLK_GOUT_CMU_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch",
1322 "mout_cmu_cpucl2_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
1324 GATE(CLK_GOUT_CMU_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
1325 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
1326 GATE(CLK_GOUT_CMU_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus",
1327 CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0),
1328 GATE(CLK_GOUT_CMU_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",
1329 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),
1330 GATE(CLK_GOUT_CMU_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",
1331 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0),
1332 GATE(CLK_GOUT_CMU_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus",
1333 CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0),
1334 GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
1335 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
1336 GATE(CLK_GOUT_CMU_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
1337 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
1338 GATE(CLK_GOUT_CMU_G3AA_G3AA, "gout_cmu_g3aa_g3aa", "mout_cmu_g3aa_g3aa",
1339 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),
1340 GATE(CLK_GOUT_CMU_G3D_BUSD, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd",
1341 CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0),
1342 GATE(CLK_GOUT_CMU_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb",
1343 CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0),
1344 GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch",
1345 "mout_cmu_g3d_switch", CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
1347 GATE(CLK_GOUT_CMU_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0",
1348 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0),
1349 GATE(CLK_GOUT_CMU_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1",
1350 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0),
1351 GATE(CLK_GOUT_CMU_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc",
1352 CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0),
1353 GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
1354 CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
1355 GATE(CLK_GOUT_CMU_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus",
1356 CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
1357 GATE(CLK_GOUT_CMU_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc",
1358 "mout_cmu_hsi0_dpgtc", CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
1360 GATE(CLK_GOUT_CMU_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd",
1361 "mout_cmu_hsi0_usb31drd", CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
1363 GATE(CLK_GOUT_CMU_HSI0_USBDPDBG, "gout_cmu_hsi0_usbdpdbg",
1364 "mout_cmu_hsi0_usbdpdbg", CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,
1366 GATE(CLK_GOUT_CMU_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
1367 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
1368 GATE(CLK_GOUT_CMU_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie",
1369 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0),
1370 GATE(CLK_GOUT_CMU_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
1371 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
1372 GATE(CLK_GOUT_CMU_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card",
1373 "mout_cmu_hsi2_mmc_card", CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,
1375 GATE(CLK_GOUT_CMU_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie",
1376 CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0),
1377 GATE(CLK_GOUT_CMU_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd",
1378 "mout_cmu_hsi2_ufs_embd", CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,
1380 GATE(CLK_GOUT_CMU_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
1381 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
1382 GATE(CLK_GOUT_CMU_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus",
1383 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),
1384 GATE(CLK_GOUT_CMU_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc",
1385 CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0),
1386 GATE(CLK_GOUT_CMU_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc",
1387 CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0),
1388 GATE(CLK_GOUT_CMU_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc",
1389 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
1390 GATE(CLK_GOUT_CMU_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
1391 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),
1392 GATE(CLK_GOUT_CMU_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
1393 CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),
1394 GATE(CLK_GOUT_CMU_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
1395 CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),
1396 GATE(CLK_GOUT_CMU_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
1397 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
1398 GATE(CLK_GOUT_CMU_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra",
1399 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
1400 GATE(CLK_GOUT_CMU_PERIC0_BUS, "gout_cmu_peric0_bus",
1401 "mout_cmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
1403 GATE(CLK_GOUT_CMU_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip",
1404 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0),
1405 GATE(CLK_GOUT_CMU_PERIC1_BUS, "gout_cmu_peric1_bus",
1406 "mout_cmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
1408 GATE(CLK_GOUT_CMU_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip",
1409 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0),
1410 GATE(CLK_GOUT_CMU_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",
1411 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),
1412 GATE(CLK_GOUT_CMU_TOP_CMUREF, "gout_cmu_top_cmuref",
1413 "mout_cmu_top_cmuref", CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF,
1415 GATE(CLK_GOUT_CMU_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus",
1416 CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0),
1417 GATE(CLK_GOUT_CMU_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu",
1418 CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0),
1419 GATE(CLK_GOUT_CMU_TPU_TPUCTL, "gout_cmu_tpu_tpuctl",
1420 "mout_cmu_tpu_tpuctl", CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL,
1422 GATE(CLK_GOUT_CMU_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart",
1423 CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0),
1426 static const struct samsung_cmu_info top_cmu_info __initconst = {
1427 .pll_clks = cmu_top_pll_clks,
1428 .nr_pll_clks = ARRAY_SIZE(cmu_top_pll_clks),
1429 .mux_clks = cmu_top_mux_clks,
1430 .nr_mux_clks = ARRAY_SIZE(cmu_top_mux_clks),
1431 .div_clks = cmu_top_div_clks,
1432 .nr_div_clks = ARRAY_SIZE(cmu_top_div_clks),
1433 .fixed_factor_clks = cmu_top_ffactor,
1434 .nr_fixed_factor_clks = ARRAY_SIZE(cmu_top_ffactor),
1435 .gate_clks = cmu_top_gate_clks,
1436 .nr_gate_clks = ARRAY_SIZE(cmu_top_gate_clks),
1437 .nr_clk_ids = CLKS_NR_TOP,
1438 .clk_regs = cmu_top_clk_regs,
1439 .nr_clk_regs = ARRAY_SIZE(cmu_top_clk_regs),
1442 static void __init gs101_cmu_top_init(struct device_node *np)
1444 exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
1447 /* Register CMU_TOP early, as it's a dependency for other early domains */
1448 CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
1449 gs101_cmu_top_init);
1451 /* ---- CMU_APM ------------------------------------------------------------- */
1453 /* Register Offset definitions for CMU_APM (0x17400000) */
1454 #define APM_CMU_APM_CONTROLLER_OPTION 0x0800
1455 #define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810
1456 #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000
1457 #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004
1458 #define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800
1459 #define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804
1460 #define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808
1461 #define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c
1462 #define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000
1463 #define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004
1464 #define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008
1465 #define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c
1466 #define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010
1467 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014
1468 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018
1469 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c
1470 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020
1471 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024
1472 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028
1473 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c
1474 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030
1475 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034
1476 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038
1477 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c
1478 #define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040
1479 #define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044
1480 #define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048
1481 #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c
1482 #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050
1483 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054
1484 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058
1485 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c
1486 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060
1487 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064
1488 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068
1489 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c
1490 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070
1491 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074
1492 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c
1493 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080
1494 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084
1495 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088
1496 #define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c
1497 #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090
1498 #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094
1499 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098
1500 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c
1501 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0
1502 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4
1503 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8
1504 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac
1505 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0
1506 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4
1507 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8
1508 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc
1509 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0
1510 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4
1511 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc
1512 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0
1513 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4
1514 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8
1515 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc
1516 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0
1517 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4
1518 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8
1519 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec
1520 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0
1521 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4
1522 #define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8
1523 #define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc
1524 #define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000
1525 #define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004
1526 #define PCH_CON_LHM_AXI_P_APM_PCH 0x3008
1527 #define PCH_CON_LHS_AXI_D_APM_PCH 0x300c
1528 #define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010
1529 #define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014
1530 #define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018
1531 #define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c
1532 #define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020
1533 #define QCH_CON_APBIF_RTC_QCH 0x3024
1534 #define QCH_CON_APBIF_TRTC_QCH 0x3028
1535 #define QCH_CON_APM_CMU_APM_QCH 0x302c
1536 #define QCH_CON_APM_USI0_UART_QCH 0x3030
1537 #define QCH_CON_APM_USI0_USI_QCH 0x3034
1538 #define QCH_CON_APM_USI1_UART_QCH 0x3038
1539 #define QCH_CON_D_TZPC_APM_QCH 0x303c
1540 #define QCH_CON_GPC_APM_QCH 0x3040
1541 #define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044
1542 #define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048
1543 #define QCH_CON_INTMEM_QCH 0x304c
1544 #define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050
1545 #define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054
1546 #define QCH_CON_LHM_AXI_P_APM_QCH 0x3058
1547 #define QCH_CON_LHS_AXI_D_APM_QCH 0x305c
1548 #define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060
1549 #define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064
1550 #define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068
1551 #define QCH_CON_MAILBOX_APM_AP_QCH 0x306c
1552 #define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070
1553 #define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078
1554 #define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c
1555 #define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080
1556 #define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084
1557 #define QCH_CON_PMU_INTR_GEN_QCH 0x3088
1558 #define QCH_CON_ROM_CRC32_HOST_QCH 0x308c
1559 #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090
1560 #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094
1561 #define QCH_CON_SPEEDY_APM_QCH 0x3098
1562 #define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c
1563 #define QCH_CON_SSMT_D_APM_QCH 0x30a0
1564 #define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4
1565 #define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8
1566 #define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac
1567 #define QCH_CON_SYSMMU_D_APM_QCH 0x30b0
1568 #define QCH_CON_SYSREG_APM_QCH 0x30b8
1569 #define QCH_CON_UASC_APM_QCH 0x30bc
1570 #define QCH_CON_UASC_DBGCORE_QCH 0x30c0
1571 #define QCH_CON_UASC_G_SWD_QCH 0x30c4
1572 #define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8
1573 #define QCH_CON_UASC_P_APM_QCH 0x30cc
1574 #define QCH_CON_WDT_APM_QCH 0x30d0
1575 #define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00
1577 static const unsigned long apm_clk_regs[] __initconst = {
1578 APM_CMU_APM_CONTROLLER_OPTION,
1579 CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0,
1580 CLK_CON_MUX_MUX_CLKCMU_APM_FUNC,
1581 CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC,
1582 CLK_CON_DIV_DIV_CLK_APM_BOOST,
1583 CLK_CON_DIV_DIV_CLK_APM_USI0_UART,
1584 CLK_CON_DIV_DIV_CLK_APM_USI0_USI,
1585 CLK_CON_DIV_DIV_CLK_APM_USI1_UART,
1586 CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK,
1587 CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1,
1588 CLK_CON_GAT_CLK_CMU_BOOST_OPTION1,
1589 CLK_CON_GAT_CLK_CORE_BOOST_OPTION1,
1590 CLK_CON_GAT_GATE_CLKCMU_APM_FUNC,
1591 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
1592 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
1593 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
1594 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK,
1595 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK,
1596 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK,
1597 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK,
1598 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK,
1599 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK,
1600 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK,
1601 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK,
1602 CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK,
1603 CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK,
1604 CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
1605 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK,
1606 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK,
1607 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK,
1608 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK,
1609 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,
1610 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
1611 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
1612 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
1613 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK,
1614 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
1615 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK,
1616 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK,
1617 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK,
1618 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK,
1619 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
1620 CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
1621 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,
1622 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,
1623 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
1624 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,
1625 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK,
1626 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK,
1627 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK,
1628 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,
1629 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK,
1630 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK,
1631 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK,
1632 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK,
1633 CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,
1634 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2,
1635 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
1636 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK,
1637 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK,
1638 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK,
1639 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK,
1640 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK,
1641 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK,
1642 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK,
1643 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK,
1644 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK,
1645 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK,
1646 CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK,
1647 CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK,
1650 PNAME(mout_apm_func_p) = { "oscclk", "mout_apm_funcsrc",
1651 "pad_clk_apm", "oscclk" };
1652 PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm",
1653 "pll_alv_div16_apm" };
1655 static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
1656 FRATE(CLK_APM_PLL_DIV2_APM, "pll_alv_div2_apm", NULL, 0, 393216000),
1657 FRATE(CLK_APM_PLL_DIV4_APM, "pll_alv_div4_apm", NULL, 0, 196608000),
1658 FRATE(CLK_APM_PLL_DIV16_APM, "pll_alv_div16_apm", NULL, 0, 49152000),
1661 static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
1662 MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p,
1663 CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1),
1664 MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p,
1665 CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1),
1668 static const struct samsung_div_clock apm_div_clks[] __initconst = {
1669 DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func",
1670 CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1),
1671 DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func",
1672 CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7),
1673 DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func",
1674 CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7),
1675 DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func",
1676 CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7),
1679 static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
1680 GATE(CLK_GOUT_APM_APM_CMU_APM_PCLK,
1681 "gout_apm_apm_cmu_apm_pclk", "mout_apm_func",
1682 CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 21, 0, 0),
1683 GATE(CLK_GOUT_BUS0_BOOST_OPTION1, "gout_bus0_boost_option1",
1684 "dout_apm_boost", CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, 21, 0, 0),
1685 GATE(CLK_GOUT_CMU_BOOST_OPTION1, "gout_cmu_boost_option1",
1686 "dout_apm_boost", CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 21, 0, 0),
1687 GATE(CLK_GOUT_CORE_BOOST_OPTION1, "gout_core_boost_option1",
1688 "dout_apm_boost", CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, 21, 0, 0),
1689 GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func",
1690 CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0),
1691 GATE(CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK,
1692 "gout_apm_apbif_gpio_alive_pclk", "gout_apm_func",
1693 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
1695 GATE(CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK,
1696 "gout_apm_apbif_gpio_far_alive_pclk", "gout_apm_func",
1697 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
1699 GATE(CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK,
1700 "gout_apm_apbif_pmu_alive_pclk", "gout_apm_func",
1701 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
1703 GATE(CLK_GOUT_APM_APBIF_RTC_PCLK,
1704 "gout_apm_apbif_rtc_pclk", "gout_apm_func",
1705 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 21, 0, 0),
1706 GATE(CLK_GOUT_APM_APBIF_TRTC_PCLK,
1707 "gout_apm_apbif_trtc_pclk", "gout_apm_func",
1708 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 21, 0, 0),
1709 GATE(CLK_GOUT_APM_APM_USI0_UART_IPCLK,
1710 "gout_apm_apm_usi0_uart_ipclk", "dout_apm_usi0_uart",
1711 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK,
1713 GATE(CLK_GOUT_APM_APM_USI0_UART_PCLK,
1714 "gout_apm_apm_usi0_uart_pclk", "gout_apm_func",
1715 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK,
1717 GATE(CLK_GOUT_APM_APM_USI0_USI_IPCLK,
1718 "gout_apm_apm_usi0_usi_ipclk", "dout_apm_usi0_usi",
1719 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK,
1721 GATE(CLK_GOUT_APM_APM_USI0_USI_PCLK,
1722 "gout_apm_apm_usi0_usi_pclk", "gout_apm_func",
1723 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK,
1725 GATE(CLK_GOUT_APM_APM_USI1_UART_IPCLK,
1726 "gout_apm_apm_usi1_uart_ipclk", "dout_apm_usi1_uart",
1727 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK,
1729 GATE(CLK_GOUT_APM_APM_USI1_UART_PCLK,
1730 "gout_apm_apm_usi1_uart_pclk", "gout_apm_func",
1731 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK,
1733 GATE(CLK_GOUT_APM_D_TZPC_APM_PCLK,
1734 "gout_apm_d_tzpc_apm_pclk", "gout_apm_func",
1735 CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 21, 0, 0),
1736 GATE(CLK_GOUT_APM_GPC_APM_PCLK,
1737 "gout_apm_gpc_apm_pclk", "gout_apm_func",
1738 CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 21, 0, 0),
1739 GATE(CLK_GOUT_APM_GREBEINTEGRATION_HCLK,
1740 "gout_apm_grebeintegration_hclk", "gout_apm_func",
1741 CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
1743 GATE(CLK_GOUT_APM_INTMEM_ACLK,
1744 "gout_apm_intmem_aclk", "gout_apm_func",
1745 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 21, 0, 0),
1746 GATE(CLK_GOUT_APM_INTMEM_PCLK,
1747 "gout_apm_intmem_pclk", "gout_apm_func",
1748 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 21, 0, 0),
1749 GATE(CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK,
1750 "gout_apm_lhm_axi_g_swd_i_clk", "gout_apm_func",
1751 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK,
1753 GATE(CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK,
1754 "gout_apm_lhm_axi_p_aocapm_i_clk", "gout_apm_func",
1755 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK,
1757 GATE(CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK,
1758 "gout_apm_lhm_axi_p_apm_i_clk", "gout_apm_func",
1759 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
1761 GATE(CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK,
1762 "gout_apm_lhs_axi_d_apm_i_clk", "gout_apm_func",
1763 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
1765 GATE(CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK,
1766 "gout_apm_lhs_axi_g_dbgcore_i_clk", "gout_apm_func",
1767 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
1769 GATE(CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK,
1770 "gout_apm_lhs_axi_g_scan2dram_i_clk",
1772 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
1774 GATE(CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK,
1775 "gout_apm_mailbox_apm_aoc_pclk", "gout_apm_func",
1776 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK,
1778 GATE(CLK_GOUT_APM_MAILBOX_APM_AP_PCLK,
1779 "gout_apm_mailbox_apm_ap_pclk", "gout_apm_func",
1780 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
1782 GATE(CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK,
1783 "gout_apm_mailbox_apm_gsa_pclk", "gout_apm_func",
1784 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK,
1786 GATE(CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK,
1787 "gout_apm_mailbox_apm_swd_pclk", "gout_apm_func",
1788 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK,
1790 GATE(CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK,
1791 "gout_apm_mailbox_apm_tpu_pclk", "gout_apm_func",
1792 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK,
1794 GATE(CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK,
1795 "gout_apm_mailbox_ap_aoc_pclk", "gout_apm_func",
1796 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK,
1798 GATE(CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK,
1799 "gout_apm_mailbox_ap_dbgcore_pclk", "gout_apm_func",
1800 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
1802 GATE(CLK_GOUT_APM_PMU_INTR_GEN_PCLK,
1803 "gout_apm_pmu_intr_gen_pclk", "gout_apm_func",
1804 CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
1806 GATE(CLK_GOUT_APM_ROM_CRC32_HOST_ACLK,
1807 "gout_apm_rom_crc32_host_aclk", "gout_apm_func",
1808 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,
1810 GATE(CLK_GOUT_APM_ROM_CRC32_HOST_PCLK,
1811 "gout_apm_rom_crc32_host_pclk", "gout_apm_func",
1812 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,
1814 GATE(CLK_GOUT_APM_CLK_APM_BUS_CLK,
1815 "gout_apm_clk_apm_bus_clk", "gout_apm_func",
1816 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
1818 GATE(CLK_GOUT_APM_CLK_APM_USI0_UART_CLK,
1819 "gout_apm_clk_apm_usi0_uart_clk",
1820 "dout_apm_usi0_uart",
1821 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,
1823 GATE(CLK_GOUT_APM_CLK_APM_USI0_USI_CLK,
1824 "gout_apm_clk_apm_usi0_usi_clk",
1825 "dout_apm_usi0_usi",
1826 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,
1828 GATE(CLK_GOUT_APM_CLK_APM_USI1_UART_CLK,
1829 "gout_apm_clk_apm_usi1_uart_clk",
1830 "dout_apm_usi1_uart",
1831 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK,
1833 GATE(CLK_GOUT_APM_SPEEDY_APM_PCLK,
1834 "gout_apm_speedy_apm_pclk", "gout_apm_func",
1835 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 21, 0, 0),
1836 GATE(CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK,
1837 "gout_apm_speedy_sub_apm_pclk", "gout_apm_func",
1838 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,
1840 GATE(CLK_GOUT_APM_SSMT_D_APM_ACLK,
1841 "gout_apm_ssmt_d_apm_aclk", "gout_apm_func",
1842 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 21, 0, 0),
1843 GATE(CLK_GOUT_APM_SSMT_D_APM_PCLK,
1844 "gout_apm_ssmt_d_apm_pclk", "gout_apm_func",
1845 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 21, 0, 0),
1846 GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK,
1847 "gout_apm_ssmt_g_dbgcore_aclk", "gout_apm_func",
1848 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK,
1850 GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK,
1851 "gout_apm_ssmt_g_dbgcore_pclk", "gout_apm_func",
1852 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK,
1854 GATE(CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK,
1855 "gout_apm_ss_dbgcore_ss_dbgcore_hclk",
1857 CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,
1859 GATE(CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2,
1860 "gout_apm_sysmmu_d_dpm_clk_s2", "gout_apm_func",
1861 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2,
1863 GATE(CLK_GOUT_APM_SYSREG_APM_PCLK,
1864 "gout_apm_sysreg_apm_pclk", "gout_apm_func",
1865 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 21, 0, 0),
1866 GATE(CLK_GOUT_APM_UASC_APM_ACLK,
1867 "gout_apm_uasc_apm_aclk", "gout_apm_func",
1868 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 21, 0, 0),
1869 GATE(CLK_GOUT_APM_UASC_APM_PCLK,
1870 "gout_apm_uasc_apm_pclk", "gout_apm_func",
1871 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 21, 0, 0),
1872 GATE(CLK_GOUT_APM_UASC_DBGCORE_ACLK,
1873 "gout_apm_uasc_dbgcore_aclk", "gout_apm_func",
1874 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK,
1876 GATE(CLK_GOUT_APM_UASC_DBGCORE_PCLK,
1877 "gout_apm_uasc_dbgcore_pclk", "gout_apm_func",
1878 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK,
1880 GATE(CLK_GOUT_APM_UASC_G_SWD_ACLK,
1881 "gout_apm_uasc_g_swd_aclk", "gout_apm_func",
1882 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, 21, 0, 0),
1883 GATE(CLK_GOUT_APM_UASC_G_SWD_PCLK,
1884 "gout_apm_uasc_g_swd_pclk", "gout_apm_func",
1885 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0),
1886 GATE(CLK_GOUT_APM_UASC_P_AOCAPM_ACLK,
1887 "gout_apm_uasc_p_aocapm_aclk", "gout_apm_func",
1888 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK,
1890 GATE(CLK_GOUT_APM_UASC_P_AOCAPM_PCLK,
1891 "gout_apm_uasc_p_aocapm_pclk", "gout_apm_func",
1892 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0),
1893 GATE(CLK_GOUT_APM_UASC_P_APM_ACLK,
1894 "gout_apm_uasc_p_apm_aclk", "gout_apm_func",
1895 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, 0, 0),
1896 GATE(CLK_GOUT_APM_UASC_P_APM_PCLK,
1897 "gout_apm_uasc_p_apm_pclk", "gout_apm_func",
1898 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, 0, 0),
1899 GATE(CLK_GOUT_APM_WDT_APM_PCLK,
1900 "gout_apm_wdt_apm_pclk", "gout_apm_func",
1901 CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 21, 0, 0),
1902 GATE(CLK_GOUT_APM_XIU_DP_APM_ACLK,
1903 "gout_apm_xiu_dp_apm_aclk", "gout_apm_func",
1904 CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, 0, 0),
1907 static const struct samsung_cmu_info apm_cmu_info __initconst = {
1908 .mux_clks = apm_mux_clks,
1909 .nr_mux_clks = ARRAY_SIZE(apm_mux_clks),
1910 .div_clks = apm_div_clks,
1911 .nr_div_clks = ARRAY_SIZE(apm_div_clks),
1912 .gate_clks = apm_gate_clks,
1913 .nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
1914 .fixed_clks = apm_fixed_clks,
1915 .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
1916 .nr_clk_ids = CLKS_NR_APM,
1917 .clk_regs = apm_clk_regs,
1918 .nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
1921 /* ---- CMU_MISC ------------------------------------------------------------ */
1923 /* Register Offset definitions for CMU_MISC (0x10010000) */
1924 #define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER 0x0600
1925 #define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER 0x0604
1926 #define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER 0x0610
1927 #define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER 0x0614
1928 #define MISC_CMU_MISC_CONTROLLER_OPTION 0x0800
1929 #define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0 0x0810
1930 #define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000
1931 #define CLK_CON_DIV_DIV_CLK_MISC_BUSP 0x1800
1932 #define CLK_CON_DIV_DIV_CLK_MISC_GIC 0x1804
1933 #define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK 0x2000
1934 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2004
1935 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK 0x2008
1936 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x200c
1937 #define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK 0x2010
1938 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM 0x2014
1939 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM 0x2018
1940 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM 0x201c
1941 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A 0x2020
1942 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK 0x2024
1943 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK 0x2028
1944 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK 0x202c
1945 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK 0x2030
1946 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK 0x2034
1947 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK 0x2038
1948 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK 0x203c
1949 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK 0x2040
1950 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK 0x2044
1951 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK 0x2048
1952 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK 0x204c
1953 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2050
1954 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK 0x2054
1955 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2058
1956 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK 0x205c
1957 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK 0x2060
1958 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK 0x2064
1959 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK 0x2068
1960 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK 0x206c
1961 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK 0x2070
1962 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK 0x2074
1963 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK 0x2078
1964 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK 0x207c
1965 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK 0x2080
1966 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK 0x2084
1967 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK 0x2088
1968 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK 0x208c
1969 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK 0x2090
1970 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2094
1971 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK 0x2098
1972 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK 0x209c
1973 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK 0x20a0
1974 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK 0x20a4
1975 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK 0x20a8
1976 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK 0x20ac
1977 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK 0x20b0
1978 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK 0x20b4
1979 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK 0x20b8
1980 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK 0x20bc
1981 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK 0x20c0
1982 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK 0x20c4
1983 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK 0x20c8
1984 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK 0x20cc
1985 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK 0x20d0
1986 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK 0x20d4
1987 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK 0x20d8
1988 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK 0x20dc
1989 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK 0x20e0
1990 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK 0x20e4
1991 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK 0x20e8
1992 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK 0x20ec
1993 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK 0x20f0
1994 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2 0x20f4
1995 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1 0x20f8
1996 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK 0x20fc
1997 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK 0x2100
1998 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK 0x2104
1999 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2108
2000 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x210c
2001 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK 0x2110
2002 #define DMYQCH_CON_PPMU_DMA_QCH 0x3000
2003 #define DMYQCH_CON_PUF_QCH 0x3004
2004 #define PCH_CON_LHM_AXI_D_SSS_PCH 0x300c
2005 #define PCH_CON_LHM_AXI_P_GIC_PCH 0x3010
2006 #define PCH_CON_LHM_AXI_P_MISC_PCH 0x3014
2007 #define PCH_CON_LHS_ACEL_D_MISC_PCH 0x3018
2008 #define PCH_CON_LHS_AST_IRI_GICCPU_PCH 0x301c
2009 #define PCH_CON_LHS_AXI_D_SSS_PCH 0x3020
2010 #define QCH_CON_ADM_AHB_SSS_QCH 0x3024
2011 #define QCH_CON_DIT_QCH 0x3028
2012 #define QCH_CON_GIC_QCH 0x3030
2013 #define QCH_CON_LHM_AST_ICC_CPUGIC_QCH 0x3038
2014 #define QCH_CON_LHM_AXI_D_SSS_QCH 0x303c
2015 #define QCH_CON_LHM_AXI_P_GIC_QCH 0x3040
2016 #define QCH_CON_LHM_AXI_P_MISC_QCH 0x3044
2017 #define QCH_CON_LHS_ACEL_D_MISC_QCH 0x3048
2018 #define QCH_CON_LHS_AST_IRI_GICCPU_QCH 0x304c
2019 #define QCH_CON_LHS_AXI_D_SSS_QCH 0x3050
2020 #define QCH_CON_MCT_QCH 0x3054
2021 #define QCH_CON_MISC_CMU_MISC_QCH 0x3058
2022 #define QCH_CON_OTP_CON_BIRA_QCH 0x305c
2023 #define QCH_CON_OTP_CON_BISR_QCH 0x3060
2024 #define QCH_CON_OTP_CON_TOP_QCH 0x3064
2025 #define QCH_CON_PDMA_QCH 0x3068
2026 #define QCH_CON_PPMU_MISC_QCH 0x306c
2027 #define QCH_CON_QE_DIT_QCH 0x3070
2028 #define QCH_CON_QE_PDMA_QCH 0x3074
2029 #define QCH_CON_QE_PPMU_DMA_QCH 0x3078
2030 #define QCH_CON_QE_RTIC_QCH 0x307c
2031 #define QCH_CON_QE_SPDMA_QCH 0x3080
2032 #define QCH_CON_QE_SSS_QCH 0x3084
2033 #define QCH_CON_RTIC_QCH 0x3088
2034 #define QCH_CON_SPDMA_QCH 0x308c
2035 #define QCH_CON_SSMT_DIT_QCH 0x3090
2036 #define QCH_CON_SSMT_PDMA_QCH 0x3094
2037 #define QCH_CON_SSMT_PPMU_DMA_QCH 0x3098
2038 #define QCH_CON_SSMT_RTIC_QCH 0x309c
2039 #define QCH_CON_SSMT_SPDMA_QCH 0x30a0
2040 #define QCH_CON_SSMT_SSS_QCH 0x30a4
2041 #define QCH_CON_SSS_QCH 0x30a8
2042 #define QCH_CON_SYSMMU_MISC_QCH 0x30ac
2043 #define QCH_CON_SYSMMU_SSS_QCH 0x30b0
2044 #define QCH_CON_SYSREG_MISC_QCH 0x30b4
2045 #define QCH_CON_TMU_SUB_QCH 0x30b8
2046 #define QCH_CON_TMU_TOP_QCH 0x30bc
2047 #define QCH_CON_WDT_CLUSTER0_QCH 0x30c0
2048 #define QCH_CON_WDT_CLUSTER1_QCH 0x30c4
2049 #define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC 0x3c00
2051 static const unsigned long misc_clk_regs[] __initconst = {
2052 PLL_CON0_MUX_CLKCMU_MISC_BUS_USER,
2053 PLL_CON1_MUX_CLKCMU_MISC_BUS_USER,
2054 PLL_CON0_MUX_CLKCMU_MISC_SSS_USER,
2055 PLL_CON1_MUX_CLKCMU_MISC_SSS_USER,
2056 MISC_CMU_MISC_CONTROLLER_OPTION,
2057 CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0,
2058 CLK_CON_MUX_MUX_CLK_MISC_GIC,
2059 CLK_CON_DIV_DIV_CLK_MISC_BUSP,
2060 CLK_CON_DIV_DIV_CLK_MISC_GIC,
2061 CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
2062 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
2063 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK,
2064 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
2065 CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK,
2066 CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
2067 CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
2068 CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM,
2069 CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A,
2070 CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK,
2071 CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK,
2072 CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK,
2073 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK,
2074 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK,
2075 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK,
2076 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK,
2077 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK,
2078 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK,
2079 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK,
2080 CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK,
2081 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
2082 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK,
2083 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
2084 CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK,
2085 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK,
2086 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK,
2087 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK,
2088 CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK,
2089 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK,
2090 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK,
2091 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK,
2092 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK,
2093 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK,
2094 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK,
2095 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK,
2096 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK,
2097 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK,
2098 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK,
2099 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK,
2100 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK,
2101 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK,
2102 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK,
2103 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK,
2104 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK,
2105 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK,
2106 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK,
2107 CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK,
2108 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK,
2109 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK,
2110 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK,
2111 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK,
2112 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK,
2113 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK,
2114 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK,
2115 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK,
2116 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK,
2117 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK,
2118 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK,
2119 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK,
2120 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK,
2121 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK,
2122 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2,
2123 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1,
2124 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
2125 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK,
2126 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK,
2127 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
2128 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
2129 CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK,
2130 DMYQCH_CON_PPMU_DMA_QCH,
2132 PCH_CON_LHM_AXI_D_SSS_PCH,
2133 PCH_CON_LHM_AXI_P_GIC_PCH,
2134 PCH_CON_LHM_AXI_P_MISC_PCH,
2135 PCH_CON_LHS_ACEL_D_MISC_PCH,
2136 PCH_CON_LHS_AST_IRI_GICCPU_PCH,
2137 PCH_CON_LHS_AXI_D_SSS_PCH,
2138 QCH_CON_ADM_AHB_SSS_QCH,
2141 QCH_CON_LHM_AST_ICC_CPUGIC_QCH,
2142 QCH_CON_LHM_AXI_D_SSS_QCH,
2143 QCH_CON_LHM_AXI_P_GIC_QCH,
2144 QCH_CON_LHM_AXI_P_MISC_QCH,
2145 QCH_CON_LHS_ACEL_D_MISC_QCH,
2146 QCH_CON_LHS_AST_IRI_GICCPU_QCH,
2147 QCH_CON_LHS_AXI_D_SSS_QCH,
2149 QCH_CON_MISC_CMU_MISC_QCH,
2150 QCH_CON_OTP_CON_BIRA_QCH,
2151 QCH_CON_OTP_CON_BISR_QCH,
2152 QCH_CON_OTP_CON_TOP_QCH,
2154 QCH_CON_PPMU_MISC_QCH,
2156 QCH_CON_QE_PDMA_QCH,
2157 QCH_CON_QE_PPMU_DMA_QCH,
2158 QCH_CON_QE_RTIC_QCH,
2159 QCH_CON_QE_SPDMA_QCH,
2163 QCH_CON_SSMT_DIT_QCH,
2164 QCH_CON_SSMT_PDMA_QCH,
2165 QCH_CON_SSMT_PPMU_DMA_QCH,
2166 QCH_CON_SSMT_RTIC_QCH,
2167 QCH_CON_SSMT_SPDMA_QCH,
2168 QCH_CON_SSMT_SSS_QCH,
2170 QCH_CON_SYSMMU_MISC_QCH,
2171 QCH_CON_SYSMMU_SSS_QCH,
2172 QCH_CON_SYSREG_MISC_QCH,
2173 QCH_CON_TMU_SUB_QCH,
2174 QCH_CON_TMU_TOP_QCH,
2175 QCH_CON_WDT_CLUSTER0_QCH,
2176 QCH_CON_WDT_CLUSTER1_QCH,
2177 QUEUE_CTRL_REG_BLK_MISC_CMU_MISC,
2180 /* List of parent clocks for Muxes in CMU_MISC */
2181 PNAME(mout_misc_bus_user_p) = { "oscclk", "dout_cmu_misc_bus" };
2182 PNAME(mout_misc_sss_user_p) = { "oscclk", "dout_cmu_misc_sss" };
2183 PNAME(mout_misc_gic_p) = { "dout_misc_gic", "oscclk" };
2185 static const struct samsung_mux_clock misc_mux_clks[] __initconst = {
2186 MUX(CLK_MOUT_MISC_BUS_USER, "mout_misc_bus_user", mout_misc_bus_user_p,
2187 PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 4, 1),
2188 MUX(CLK_MOUT_MISC_SSS_USER, "mout_misc_sss_user", mout_misc_sss_user_p,
2189 PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 4, 1),
2190 MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic", mout_misc_gic_p,
2191 CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 0),
2194 static const struct samsung_div_clock misc_div_clks[] __initconst = {
2195 DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user",
2196 CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3),
2197 DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user",
2198 CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3),
2201 static const struct samsung_gate_clock misc_gate_clks[] __initconst = {
2202 GATE(CLK_GOUT_MISC_MISC_CMU_MISC_PCLK,
2203 "gout_misc_misc_cmu_misc_pclk", "dout_misc_busp",
2204 CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
2206 GATE(CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK,
2207 "gout_misc_otp_con_bira_i_oscclk", "oscclk",
2208 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
2210 GATE(CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK,
2211 "gout_misc_otp_con_bisr_i_oscclk", "oscclk",
2212 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK,
2214 GATE(CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK,
2215 "gout_misc_otp_con_top_i_oscclk", "oscclk",
2216 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
2218 GATE(CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK,
2219 "gout_misc_clk_misc_oscclk_clk", "oscclk",
2220 CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK,
2222 GATE(CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM,
2223 "gout_misc_adm_ahb_sss_hclkm", "mout_misc_sss_user",
2224 CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
2226 GATE(CLK_GOUT_MISC_AD_APB_DIT_PCLKM,
2227 "gout_misc_ad_apb_dit_pclkm", "mout_misc_bus_user",
2228 CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
2230 GATE(CLK_GOUT_MISC_D_TZPC_MISC_PCLK,
2231 "gout_misc_d_tzpc_misc_pclk", "dout_misc_busp",
2232 CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK,
2234 GATE(CLK_GOUT_MISC_GIC_GICCLK,
2235 "gout_misc_gic_gicclk", "mout_misc_gic",
2236 CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK,
2238 GATE(CLK_GOUT_MISC_GPC_MISC_PCLK,
2239 "gout_misc_gpc_misc_pclk", "dout_misc_busp",
2240 CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK,
2242 GATE(CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK,
2243 "gout_misc_lhm_ast_icc_gpugic_i_clk", "mout_misc_gic",
2244 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK,
2246 GATE(CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK,
2247 "gout_misc_lhm_axi_d_sss_i_clk", "mout_misc_bus_user",
2248 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK,
2250 GATE(CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK,
2251 "gout_misc_lhm_axi_p_gic_i_clk", "mout_misc_gic",
2252 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK,
2254 GATE(CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK,
2255 "gout_misc_lhm_axi_p_misc_i_clk", "dout_misc_busp",
2256 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK,
2258 GATE(CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK,
2259 "gout_misc_lhs_acel_d_misc_i_clk", "mout_misc_bus_user",
2260 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK,
2262 GATE(CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK,
2263 "gout_misc_lhs_ast_iri_giccpu_i_clk", "mout_misc_gic",
2264 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK,
2266 GATE(CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK,
2267 "gout_misc_lhs_axi_d_sss_i_clk", "mout_misc_sss_user",
2268 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK,
2270 GATE(CLK_GOUT_MISC_MCT_PCLK, "gout_misc_mct_pclk",
2272 CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK,
2274 GATE(CLK_GOUT_MISC_OTP_CON_BIRA_PCLK,
2275 "gout_misc_otp_con_bira_pclk", "dout_misc_busp",
2276 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
2278 GATE(CLK_GOUT_MISC_OTP_CON_BISR_PCLK,
2279 "gout_misc_otp_con_bisr_pclk", "dout_misc_busp",
2280 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK,
2282 GATE(CLK_GOUT_MISC_OTP_CON_TOP_PCLK,
2283 "gout_misc_otp_con_top_pclk", "dout_misc_busp",
2284 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
2286 GATE(CLK_GOUT_MISC_PDMA_ACLK, "gout_misc_pdma_aclk",
2287 "mout_misc_bus_user",
2288 CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK,
2290 GATE(CLK_GOUT_MISC_PPMU_MISC_ACLK,
2291 "gout_misc_ppmu_misc_aclk", "mout_misc_bus_user",
2292 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK,
2294 GATE(CLK_GOUT_MISC_PPMU_MISC_PCLK,
2295 "gout_misc_ppmu_misc_pclk", "dout_misc_busp",
2296 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK,
2298 GATE(CLK_GOUT_MISC_PUF_I_CLK,
2299 "gout_misc_puf_i_clk", "mout_misc_sss_user",
2300 CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK,
2302 GATE(CLK_GOUT_MISC_QE_DIT_ACLK,
2303 "gout_misc_qe_dit_aclk", "mout_misc_bus_user",
2304 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK,
2306 GATE(CLK_GOUT_MISC_QE_DIT_PCLK,
2307 "gout_misc_qe_dit_pclk", "dout_misc_busp",
2308 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK,
2310 GATE(CLK_GOUT_MISC_QE_PDMA_ACLK,
2311 "gout_misc_qe_pdma_aclk", "mout_misc_bus_user",
2312 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK,
2314 GATE(CLK_GOUT_MISC_QE_PDMA_PCLK,
2315 "gout_misc_qe_pdma_pclk", "dout_misc_busp",
2316 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK,
2318 GATE(CLK_GOUT_MISC_QE_PPMU_DMA_ACLK,
2319 "gout_misc_qe_ppmu_dma_aclk", "mout_misc_bus_user",
2320 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK,
2322 GATE(CLK_GOUT_MISC_QE_PPMU_DMA_PCLK,
2323 "gout_misc_qe_ppmu_dma_pclk", "dout_misc_busp",
2324 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK,
2326 GATE(CLK_GOUT_MISC_QE_RTIC_ACLK,
2327 "gout_misc_qe_rtic_aclk", "mout_misc_bus_user",
2328 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK,
2330 GATE(CLK_GOUT_MISC_QE_RTIC_PCLK,
2331 "gout_misc_qe_rtic_pclk", "dout_misc_busp",
2332 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK,
2334 GATE(CLK_GOUT_MISC_QE_SPDMA_ACLK,
2335 "gout_misc_qe_spdma_aclk", "mout_misc_bus_user",
2336 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK,
2338 GATE(CLK_GOUT_MISC_QE_SPDMA_PCLK,
2339 "gout_misc_qe_spdma_pclk", "dout_misc_busp",
2340 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK,
2342 GATE(CLK_GOUT_MISC_QE_SSS_ACLK,
2343 "gout_misc_qe_sss_aclk", "mout_misc_sss_user",
2344 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK,
2346 GATE(CLK_GOUT_MISC_QE_SSS_PCLK,
2347 "gout_misc_qe_sss_pclk", "dout_misc_busp",
2348 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK,
2350 GATE(CLK_GOUT_MISC_CLK_MISC_BUSD_CLK,
2351 "gout_misc_clk_misc_busd_clk", "mout_misc_bus_user",
2352 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK,
2354 GATE(CLK_GOUT_MISC_CLK_MISC_BUSP_CLK,
2355 "gout_misc_clk_misc_busp_clk", "dout_misc_busp",
2356 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK,
2358 GATE(CLK_GOUT_MISC_CLK_MISC_GIC_CLK,
2359 "gout_misc_clk_misc_gic_clk", "mout_misc_gic",
2360 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK,
2362 GATE(CLK_GOUT_MISC_CLK_MISC_SSS_CLK,
2363 "gout_misc_clk_misc_sss_clk", "mout_misc_sss_user",
2364 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK,
2366 GATE(CLK_GOUT_MISC_RTIC_I_ACLK,
2367 "gout_misc_rtic_i_aclk", "mout_misc_bus_user",
2368 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK,
2370 GATE(CLK_GOUT_MISC_RTIC_I_PCLK, "gout_misc_rtic_i_pclk",
2372 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK,
2374 GATE(CLK_GOUT_MISC_SPDMA_ACLK,
2375 "gout_misc_spdma_ipclockport_aclk", "mout_misc_bus_user",
2376 CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK,
2378 GATE(CLK_GOUT_MISC_SSMT_DIT_ACLK,
2379 "gout_misc_ssmt_dit_aclk", "mout_misc_bus_user",
2380 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK,
2382 GATE(CLK_GOUT_MISC_SSMT_DIT_PCLK,
2383 "gout_misc_ssmt_dit_pclk", "dout_misc_busp",
2384 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK,
2386 GATE(CLK_GOUT_MISC_SSMT_PDMA_ACLK,
2387 "gout_misc_ssmt_pdma_aclk", "mout_misc_bus_user",
2388 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK,
2390 GATE(CLK_GOUT_MISC_SSMT_PDMA_PCLK,
2391 "gout_misc_ssmt_pdma_pclk", "dout_misc_busp",
2392 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK,
2394 GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK,
2395 "gout_misc_ssmt_ppmu_dma_aclk", "mout_misc_bus_user",
2396 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK,
2398 GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK,
2399 "gout_misc_ssmt_ppmu_dma_pclk", "dout_misc_busp",
2400 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK,
2402 GATE(CLK_GOUT_MISC_SSMT_RTIC_ACLK,
2403 "gout_misc_ssmt_rtic_aclk", "mout_misc_bus_user",
2404 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK,
2406 GATE(CLK_GOUT_MISC_SSMT_RTIC_PCLK,
2407 "gout_misc_ssmt_rtic_pclk", "dout_misc_busp",
2408 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK,
2410 GATE(CLK_GOUT_MISC_SSMT_SPDMA_ACLK,
2411 "gout_misc_ssmt_spdma_aclk", "mout_misc_bus_user",
2412 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK,
2414 GATE(CLK_GOUT_MISC_SSMT_SPDMA_PCLK,
2415 "gout_misc_ssmt_spdma_pclk", "dout_misc_busp",
2416 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK,
2418 GATE(CLK_GOUT_MISC_SSMT_SSS_ACLK,
2419 "gout_misc_ssmt_sss_aclk", "mout_misc_bus_user",
2420 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK,
2422 GATE(CLK_GOUT_MISC_SSMT_SSS_PCLK,
2423 "gout_misc_ssmt_sss_pclk", "dout_misc_busp",
2424 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK,
2426 GATE(CLK_GOUT_MISC_SSS_I_ACLK,
2427 "gout_misc_sss_i_aclk", "mout_misc_bus_user",
2428 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK,
2430 GATE(CLK_GOUT_MISC_SSS_I_PCLK,
2431 "gout_misc_sss_i_pclk", "dout_misc_busp",
2432 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK,
2434 GATE(CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2,
2435 "gout_misc_sysmmu_misc_clk_s2", "mout_misc_bus_user",
2436 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2,
2438 GATE(CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1,
2439 "gout_misc_sysmmu_sss_clk_s1", "mout_misc_sss_user",
2440 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1,
2442 GATE(CLK_GOUT_MISC_SYSREG_MISC_PCLK,
2443 "gout_misc_sysreg_misc_pclk", "dout_misc_busp",
2444 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
2446 GATE(CLK_GOUT_MISC_TMU_SUB_PCLK,
2447 "gout_misc_tmu_sub_pclk", "dout_misc_busp",
2448 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK,
2450 GATE(CLK_GOUT_MISC_TMU_TOP_PCLK,
2451 "gout_misc_tmu_top_pclk", "dout_misc_busp",
2452 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK,
2454 GATE(CLK_GOUT_MISC_WDT_CLUSTER0_PCLK,
2455 "gout_misc_wdt_cluster0_pclk", "dout_misc_busp",
2456 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
2458 GATE(CLK_GOUT_MISC_WDT_CLUSTER1_PCLK,
2459 "gout_misc_wdt_cluster1_pclk", "dout_misc_busp",
2460 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
2462 GATE(CLK_GOUT_MISC_XIU_D_MISC_ACLK,
2463 "gout_misc_xiu_d_misc_aclk", "mout_misc_bus_user",
2464 CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK,
2468 static const struct samsung_cmu_info misc_cmu_info __initconst = {
2469 .mux_clks = misc_mux_clks,
2470 .nr_mux_clks = ARRAY_SIZE(misc_mux_clks),
2471 .div_clks = misc_div_clks,
2472 .nr_div_clks = ARRAY_SIZE(misc_div_clks),
2473 .gate_clks = misc_gate_clks,
2474 .nr_gate_clks = ARRAY_SIZE(misc_gate_clks),
2475 .nr_clk_ids = CLKS_NR_MISC,
2476 .clk_regs = misc_clk_regs,
2477 .nr_clk_regs = ARRAY_SIZE(misc_clk_regs),
2481 /* ---- platform_driver ----------------------------------------------------- */
2483 static int __init gs101_cmu_probe(struct platform_device *pdev)
2485 const struct samsung_cmu_info *info;
2486 struct device *dev = &pdev->dev;
2488 info = of_device_get_match_data(dev);
2489 exynos_arm64_register_cmu(dev, dev->of_node, info);
2494 static const struct of_device_id gs101_cmu_of_match[] = {
2496 .compatible = "google,gs101-cmu-apm",
2497 .data = &apm_cmu_info,
2499 .compatible = "google,gs101-cmu-misc",
2500 .data = &misc_cmu_info,
2505 static struct platform_driver gs101_cmu_driver __refdata = {
2507 .name = "gs101-cmu",
2508 .of_match_table = gs101_cmu_of_match,
2509 .suppress_bind_attrs = true,
2511 .probe = gs101_cmu_probe,
2514 static int __init gs101_cmu_init(void)
2516 return platform_driver_register(&gs101_cmu_driver);
2518 core_initcall(gs101_cmu_init);
git.samba.org / sfrench / cifs-2.6.git / blob