drivers/clk/qcom/mmcc-apq8084.c

   1 /*
   2  * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/module.h>
  17 #include <linux/regmap.h>
  18 #include <linux/reset-controller.h>
  19
  20 #include <dt-bindings/clock/qcom,mmcc-apq8084.h>
  21 #include <dt-bindings/reset/qcom,mmcc-apq8084.h>
  22
  23 #include "common.h"
  24 #include "clk-regmap.h"
  25 #include "clk-pll.h"
  26 #include "clk-rcg.h"
  27 #include "clk-branch.h"
  28 #include "reset.h"
  29 #include "gdsc.h"
  30
  31 enum {
  32         P_XO,
  33         P_MMPLL0,
  34         P_EDPLINK,
  35         P_MMPLL1,
  36         P_HDMIPLL,
  37         P_GPLL0,
  38         P_EDPVCO,
  39         P_MMPLL4,
  40         P_DSI0PLL,
  41         P_DSI0PLL_BYTE,
  42         P_MMPLL2,
  43         P_MMPLL3,
  44         P_GPLL1,
  45         P_DSI1PLL,
  46         P_DSI1PLL_BYTE,
  47         P_MMSLEEP,
  48 };
  49
  50 static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
  51         { P_XO, 0 },
  52         { P_MMPLL0, 1 },
  53         { P_MMPLL1, 2 },
  54         { P_GPLL0, 5 }
  55 };
  56
  57 static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
  58         "xo",
  59         "mmpll0_vote",
  60         "mmpll1_vote",
  61         "mmss_gpll0_vote",
  62 };
  63
  64 static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
  65         { P_XO, 0 },
  66         { P_MMPLL0, 1 },
  67         { P_HDMIPLL, 4 },
  68         { P_GPLL0, 5 },
  69         { P_DSI0PLL, 2 },
  70         { P_DSI1PLL, 3 }
  71 };
  72
  73 static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
  74         "xo",
  75         "mmpll0_vote",
  76         "hdmipll",
  77         "mmss_gpll0_vote",
  78         "dsi0pll",
  79         "dsi1pll",
  80 };
  81
  82 static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
  83         { P_XO, 0 },
  84         { P_MMPLL0, 1 },
  85         { P_MMPLL1, 2 },
  86         { P_GPLL0, 5 },
  87         { P_MMPLL2, 3 }
  88 };
  89
  90 static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
  91         "xo",
  92         "mmpll0_vote",
  93         "mmpll1_vote",
  94         "mmss_gpll0_vote",
  95         "mmpll2",
  96 };
  97
  98 static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
  99         { P_XO, 0 },
 100         { P_MMPLL0, 1 },
 101         { P_MMPLL1, 2 },
 102         { P_GPLL0, 5 },
 103         { P_MMPLL3, 3 }
 104 };
 105
 106 static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
 107         "xo",
 108         "mmpll0_vote",
 109         "mmpll1_vote",
 110         "mmss_gpll0_vote",
 111         "mmpll3",
 112 };
 113
 114 static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
 115         { P_XO, 0 },
 116         { P_EDPLINK, 4 },
 117         { P_HDMIPLL, 3 },
 118         { P_EDPVCO, 5 },
 119         { P_DSI0PLL, 1 },
 120         { P_DSI1PLL, 2 }
 121 };
 122
 123 static const char * const mmcc_xo_dsi_hdmi_edp[] = {
 124         "xo",
 125         "edp_link_clk",
 126         "hdmipll",
 127         "edp_vco_div",
 128         "dsi0pll",
 129         "dsi1pll",
 130 };
 131
 132 static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
 133         { P_XO, 0 },
 134         { P_EDPLINK, 4 },
 135         { P_HDMIPLL, 3 },
 136         { P_GPLL0, 5 },
 137         { P_DSI0PLL, 1 },
 138         { P_DSI1PLL, 2 }
 139 };
 140
 141 static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
 142         "xo",
 143         "edp_link_clk",
 144         "hdmipll",
 145         "gpll0_vote",
 146         "dsi0pll",
 147         "dsi1pll",
 148 };
 149
 150 static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
 151         { P_XO, 0 },
 152         { P_EDPLINK, 4 },
 153         { P_HDMIPLL, 3 },
 154         { P_GPLL0, 5 },
 155         { P_DSI0PLL_BYTE, 1 },
 156         { P_DSI1PLL_BYTE, 2 }
 157 };
 158
 159 static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
 160         "xo",
 161         "edp_link_clk",
 162         "hdmipll",
 163         "gpll0_vote",
 164         "dsi0pllbyte",
 165         "dsi1pllbyte",
 166 };
 167
 168 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
 169         { P_XO, 0 },
 170         { P_MMPLL0, 1 },
 171         { P_MMPLL1, 2 },
 172         { P_GPLL0, 5 },
 173         { P_MMPLL4, 3 }
 174 };
 175
 176 static const char * const mmcc_xo_mmpll0_1_4_gpll0[] = {
 177         "xo",
 178         "mmpll0",
 179         "mmpll1",
 180         "mmpll4",
 181         "gpll0",
 182 };
 183
 184 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
 185         { P_XO, 0 },
 186         { P_MMPLL0, 1 },
 187         { P_MMPLL1, 2 },
 188         { P_MMPLL4, 3 },
 189         { P_GPLL0, 5 },
 190         { P_GPLL1, 4 }
 191 };
 192
 193 static const char * const mmcc_xo_mmpll0_1_4_gpll1_0[] = {
 194         "xo",
 195         "mmpll0",
 196         "mmpll1",
 197         "mmpll4",
 198         "gpll1",
 199         "gpll0",
 200 };
 201
 202 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
 203         { P_XO, 0 },
 204         { P_MMPLL0, 1 },
 205         { P_MMPLL1, 2 },
 206         { P_MMPLL4, 3 },
 207         { P_GPLL0, 5 },
 208         { P_GPLL1, 4 },
 209         { P_MMSLEEP, 6 }
 210 };
 211
 212 static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
 213         "xo",
 214         "mmpll0",
 215         "mmpll1",
 216         "mmpll4",
 217         "gpll1",
 218         "gpll0",
 219         "sleep_clk_src",
 220 };
 221
 222 static struct clk_pll mmpll0 = {
 223         .l_reg = 0x0004,
 224         .m_reg = 0x0008,
 225         .n_reg = 0x000c,
 226         .config_reg = 0x0014,
 227         .mode_reg = 0x0000,
 228         .status_reg = 0x001c,
 229         .status_bit = 17,
 230         .clkr.hw.init = &(struct clk_init_data){
 231                 .name = "mmpll0",
 232                 .parent_names = (const char *[]){ "xo" },
 233                 .num_parents = 1,
 234                 .ops = &clk_pll_ops,
 235         },
 236 };
 237
 238 static struct clk_regmap mmpll0_vote = {
 239         .enable_reg = 0x0100,
 240         .enable_mask = BIT(0),
 241         .hw.init = &(struct clk_init_data){
 242                 .name = "mmpll0_vote",
 243                 .parent_names = (const char *[]){ "mmpll0" },
 244                 .num_parents = 1,
 245                 .ops = &clk_pll_vote_ops,
 246         },
 247 };
 248
 249 static struct clk_pll mmpll1 = {
 250         .l_reg = 0x0044,
 251         .m_reg = 0x0048,
 252         .n_reg = 0x004c,
 253         .config_reg = 0x0050,
 254         .mode_reg = 0x0040,
 255         .status_reg = 0x005c,
 256         .status_bit = 17,
 257         .clkr.hw.init = &(struct clk_init_data){
 258                 .name = "mmpll1",
 259                 .parent_names = (const char *[]){ "xo" },
 260                 .num_parents = 1,
 261                 .ops = &clk_pll_ops,
 262         },
 263 };
 264
 265 static struct clk_regmap mmpll1_vote = {
 266         .enable_reg = 0x0100,
 267         .enable_mask = BIT(1),
 268         .hw.init = &(struct clk_init_data){
 269                 .name = "mmpll1_vote",
 270                 .parent_names = (const char *[]){ "mmpll1" },
 271                 .num_parents = 1,
 272                 .ops = &clk_pll_vote_ops,
 273         },
 274 };
 275
 276 static struct clk_pll mmpll2 = {
 277         .l_reg = 0x4104,
 278         .m_reg = 0x4108,
 279         .n_reg = 0x410c,
 280         .config_reg = 0x4110,
 281         .mode_reg = 0x4100,
 282         .status_reg = 0x411c,
 283         .clkr.hw.init = &(struct clk_init_data){
 284                 .name = "mmpll2",
 285                 .parent_names = (const char *[]){ "xo" },
 286                 .num_parents = 1,
 287                 .ops = &clk_pll_ops,
 288         },
 289 };
 290
 291 static struct clk_pll mmpll3 = {
 292         .l_reg = 0x0084,
 293         .m_reg = 0x0088,
 294         .n_reg = 0x008c,
 295         .config_reg = 0x0090,
 296         .mode_reg = 0x0080,
 297         .status_reg = 0x009c,
 298         .status_bit = 17,
 299         .clkr.hw.init = &(struct clk_init_data){
 300                 .name = "mmpll3",
 301                 .parent_names = (const char *[]){ "xo" },
 302                 .num_parents = 1,
 303                 .ops = &clk_pll_ops,
 304         },
 305 };
 306
 307 static struct clk_pll mmpll4 = {
 308         .l_reg = 0x00a4,
 309         .m_reg = 0x00a8,
 310         .n_reg = 0x00ac,
 311         .config_reg = 0x00b0,
 312         .mode_reg = 0x0080,
 313         .status_reg = 0x00bc,
 314         .clkr.hw.init = &(struct clk_init_data){
 315                 .name = "mmpll4",
 316                 .parent_names = (const char *[]){ "xo" },
 317                 .num_parents = 1,
 318                 .ops = &clk_pll_ops,
 319         },
 320 };
 321
 322 static struct clk_rcg2 mmss_ahb_clk_src = {
 323         .cmd_rcgr = 0x5000,
 324         .hid_width = 5,
 325         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 326         .clkr.hw.init = &(struct clk_init_data){
 327                 .name = "mmss_ahb_clk_src",
 328                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 329                 .num_parents = 4,
 330                 .ops = &clk_rcg2_ops,
 331         },
 332 };
 333
 334 static struct freq_tbl ftbl_mmss_axi_clk[] = {
 335         F(19200000, P_XO, 1, 0, 0),
 336         F(37500000, P_GPLL0, 16, 0, 0),
 337         F(50000000, P_GPLL0, 12, 0, 0),
 338         F(75000000, P_GPLL0, 8, 0, 0),
 339         F(100000000, P_GPLL0, 6, 0, 0),
 340         F(150000000, P_GPLL0, 4, 0, 0),
 341         F(333430000, P_MMPLL1, 3.5, 0, 0),
 342         F(400000000, P_MMPLL0, 2, 0, 0),
 343         F(466800000, P_MMPLL1, 2.5, 0, 0),
 344 };
 345
 346 static struct clk_rcg2 mmss_axi_clk_src = {
 347         .cmd_rcgr = 0x5040,
 348         .hid_width = 5,
 349         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 350         .freq_tbl = ftbl_mmss_axi_clk,
 351         .clkr.hw.init = &(struct clk_init_data){
 352                 .name = "mmss_axi_clk_src",
 353                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 354                 .num_parents = 4,
 355                 .ops = &clk_rcg2_ops,
 356         },
 357 };
 358
 359 static struct freq_tbl ftbl_ocmemnoc_clk[] = {
 360         F(19200000, P_XO, 1, 0, 0),
 361         F(37500000, P_GPLL0, 16, 0, 0),
 362         F(50000000, P_GPLL0, 12, 0, 0),
 363         F(75000000, P_GPLL0, 8, 0, 0),
 364         F(109090000, P_GPLL0, 5.5, 0, 0),
 365         F(150000000, P_GPLL0, 4, 0, 0),
 366         F(228570000, P_MMPLL0, 3.5, 0, 0),
 367         F(320000000, P_MMPLL0, 2.5, 0, 0),
 368 };
 369
 370 static struct clk_rcg2 ocmemnoc_clk_src = {
 371         .cmd_rcgr = 0x5090,
 372         .hid_width = 5,
 373         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 374         .freq_tbl = ftbl_ocmemnoc_clk,
 375         .clkr.hw.init = &(struct clk_init_data){
 376                 .name = "ocmemnoc_clk_src",
 377                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 378                 .num_parents = 4,
 379                 .ops = &clk_rcg2_ops,
 380         },
 381 };
 382
 383 static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
 384         F(100000000, P_GPLL0, 6, 0, 0),
 385         F(200000000, P_MMPLL0, 4, 0, 0),
 386         { }
 387 };
 388
 389 static struct clk_rcg2 csi0_clk_src = {
 390         .cmd_rcgr = 0x3090,
 391         .hid_width = 5,
 392         .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
 393         .freq_tbl = ftbl_camss_csi0_3_clk,
 394         .clkr.hw.init = &(struct clk_init_data){
 395                 .name = "csi0_clk_src",
 396                 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
 397                 .num_parents = 5,
 398                 .ops = &clk_rcg2_ops,
 399         },
 400 };
 401
 402 static struct clk_rcg2 csi1_clk_src = {
 403         .cmd_rcgr = 0x3100,
 404         .hid_width = 5,
 405         .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
 406         .freq_tbl = ftbl_camss_csi0_3_clk,
 407         .clkr.hw.init = &(struct clk_init_data){
 408                 .name = "csi1_clk_src",
 409                 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
 410                 .num_parents = 5,
 411                 .ops = &clk_rcg2_ops,
 412         },
 413 };
 414
 415 static struct clk_rcg2 csi2_clk_src = {
 416         .cmd_rcgr = 0x3160,
 417         .hid_width = 5,
 418         .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
 419         .freq_tbl = ftbl_camss_csi0_3_clk,
 420         .clkr.hw.init = &(struct clk_init_data){
 421                 .name = "csi2_clk_src",
 422                 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
 423                 .num_parents = 5,
 424                 .ops = &clk_rcg2_ops,
 425         },
 426 };
 427
 428 static struct clk_rcg2 csi3_clk_src = {
 429         .cmd_rcgr = 0x31c0,
 430         .hid_width = 5,
 431         .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
 432         .freq_tbl = ftbl_camss_csi0_3_clk,
 433         .clkr.hw.init = &(struct clk_init_data){
 434                 .name = "csi3_clk_src",
 435                 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
 436                 .num_parents = 5,
 437                 .ops = &clk_rcg2_ops,
 438         },
 439 };
 440
 441 static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
 442         F(37500000, P_GPLL0, 16, 0, 0),
 443         F(50000000, P_GPLL0, 12, 0, 0),
 444         F(60000000, P_GPLL0, 10, 0, 0),
 445         F(80000000, P_GPLL0, 7.5, 0, 0),
 446         F(100000000, P_GPLL0, 6, 0, 0),
 447         F(109090000, P_GPLL0, 5.5, 0, 0),
 448         F(133330000, P_GPLL0, 4.5, 0, 0),
 449         F(200000000, P_GPLL0, 3, 0, 0),
 450         F(228570000, P_MMPLL0, 3.5, 0, 0),
 451         F(266670000, P_MMPLL0, 3, 0, 0),
 452         F(320000000, P_MMPLL0, 2.5, 0, 0),
 453         F(465000000, P_MMPLL4, 2, 0, 0),
 454         F(600000000, P_GPLL0, 1, 0, 0),
 455         { }
 456 };
 457
 458 static struct clk_rcg2 vfe0_clk_src = {
 459         .cmd_rcgr = 0x3600,
 460         .hid_width = 5,
 461         .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
 462         .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
 463         .clkr.hw.init = &(struct clk_init_data){
 464                 .name = "vfe0_clk_src",
 465                 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
 466                 .num_parents = 5,
 467                 .ops = &clk_rcg2_ops,
 468         },
 469 };
 470
 471 static struct clk_rcg2 vfe1_clk_src = {
 472         .cmd_rcgr = 0x3620,
 473         .hid_width = 5,
 474         .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
 475         .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
 476         .clkr.hw.init = &(struct clk_init_data){
 477                 .name = "vfe1_clk_src",
 478                 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
 479                 .num_parents = 5,
 480                 .ops = &clk_rcg2_ops,
 481         },
 482 };
 483
 484 static struct freq_tbl ftbl_mdss_mdp_clk[] = {
 485         F(37500000, P_GPLL0, 16, 0, 0),
 486         F(60000000, P_GPLL0, 10, 0, 0),
 487         F(75000000, P_GPLL0, 8, 0, 0),
 488         F(85710000, P_GPLL0, 7, 0, 0),
 489         F(100000000, P_GPLL0, 6, 0, 0),
 490         F(150000000, P_GPLL0, 4, 0, 0),
 491         F(160000000, P_MMPLL0, 5, 0, 0),
 492         F(200000000, P_MMPLL0, 4, 0, 0),
 493         F(228570000, P_MMPLL0, 3.5, 0, 0),
 494         F(300000000, P_GPLL0, 2, 0, 0),
 495         F(320000000, P_MMPLL0, 2.5, 0, 0),
 496         { }
 497 };
 498
 499 static struct clk_rcg2 mdp_clk_src = {
 500         .cmd_rcgr = 0x2040,
 501         .hid_width = 5,
 502         .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
 503         .freq_tbl = ftbl_mdss_mdp_clk,
 504         .clkr.hw.init = &(struct clk_init_data){
 505                 .name = "mdp_clk_src",
 506                 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
 507                 .num_parents = 6,
 508                 .ops = &clk_rcg2_ops,
 509         },
 510 };
 511
 512 static struct clk_rcg2 gfx3d_clk_src = {
 513         .cmd_rcgr = 0x4000,
 514         .hid_width = 5,
 515         .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
 516         .clkr.hw.init = &(struct clk_init_data){
 517                 .name = "gfx3d_clk_src",
 518                 .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
 519                 .num_parents = 5,
 520                 .ops = &clk_rcg2_ops,
 521         },
 522 };
 523
 524 static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
 525         F(75000000, P_GPLL0, 8, 0, 0),
 526         F(133330000, P_GPLL0, 4.5, 0, 0),
 527         F(200000000, P_GPLL0, 3, 0, 0),
 528         F(228570000, P_MMPLL0, 3.5, 0, 0),
 529         F(266670000, P_MMPLL0, 3, 0, 0),
 530         F(320000000, P_MMPLL0, 2.5, 0, 0),
 531         { }
 532 };
 533
 534 static struct clk_rcg2 jpeg0_clk_src = {
 535         .cmd_rcgr = 0x3500,
 536         .hid_width = 5,
 537         .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
 538         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 539         .clkr.hw.init = &(struct clk_init_data){
 540                 .name = "jpeg0_clk_src",
 541                 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
 542                 .num_parents = 5,
 543                 .ops = &clk_rcg2_ops,
 544         },
 545 };
 546
 547 static struct clk_rcg2 jpeg1_clk_src = {
 548         .cmd_rcgr = 0x3520,
 549         .hid_width = 5,
 550         .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
 551         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 552         .clkr.hw.init = &(struct clk_init_data){
 553                 .name = "jpeg1_clk_src",
 554                 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
 555                 .num_parents = 5,
 556                 .ops = &clk_rcg2_ops,
 557         },
 558 };
 559
 560 static struct clk_rcg2 jpeg2_clk_src = {
 561         .cmd_rcgr = 0x3540,
 562         .hid_width = 5,
 563         .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
 564         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 565         .clkr.hw.init = &(struct clk_init_data){
 566                 .name = "jpeg2_clk_src",
 567                 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
 568                 .num_parents = 5,
 569                 .ops = &clk_rcg2_ops,
 570         },
 571 };
 572
 573 static struct clk_rcg2 pclk0_clk_src = {
 574         .cmd_rcgr = 0x2000,
 575         .mnd_width = 8,
 576         .hid_width = 5,
 577         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 578         .clkr.hw.init = &(struct clk_init_data){
 579                 .name = "pclk0_clk_src",
 580                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 581                 .num_parents = 6,
 582                 .ops = &clk_pixel_ops,
 583                 .flags = CLK_SET_RATE_PARENT,
 584         },
 585 };
 586
 587 static struct clk_rcg2 pclk1_clk_src = {
 588         .cmd_rcgr = 0x2020,
 589         .mnd_width = 8,
 590         .hid_width = 5,
 591         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 592         .clkr.hw.init = &(struct clk_init_data){
 593                 .name = "pclk1_clk_src",
 594                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 595                 .num_parents = 6,
 596                 .ops = &clk_pixel_ops,
 597                 .flags = CLK_SET_RATE_PARENT,
 598         },
 599 };
 600
 601 static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
 602         F(50000000, P_GPLL0, 12, 0, 0),
 603         F(100000000, P_GPLL0, 6, 0, 0),
 604         F(133330000, P_GPLL0, 4.5, 0, 0),
 605         F(200000000, P_MMPLL0, 4, 0, 0),
 606         F(266670000, P_MMPLL0, 3, 0, 0),
 607         F(465000000, P_MMPLL3, 2, 0, 0),
 608         { }
 609 };
 610
 611 static struct clk_rcg2 vcodec0_clk_src = {
 612         .cmd_rcgr = 0x1000,
 613         .mnd_width = 8,
 614         .hid_width = 5,
 615         .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
 616         .freq_tbl = ftbl_venus0_vcodec0_clk,
 617         .clkr.hw.init = &(struct clk_init_data){
 618                 .name = "vcodec0_clk_src",
 619                 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
 620                 .num_parents = 5,
 621                 .ops = &clk_rcg2_ops,
 622         },
 623 };
 624
 625 static struct freq_tbl ftbl_avsync_vp_clk[] = {
 626         F(150000000, P_GPLL0, 4, 0, 0),
 627         F(320000000, P_MMPLL0, 2.5, 0, 0),
 628         { }
 629 };
 630
 631 static struct clk_rcg2 vp_clk_src = {
 632         .cmd_rcgr = 0x2430,
 633         .hid_width = 5,
 634         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 635         .freq_tbl = ftbl_avsync_vp_clk,
 636         .clkr.hw.init = &(struct clk_init_data){
 637                 .name = "vp_clk_src",
 638                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 639                 .num_parents = 4,
 640                 .ops = &clk_rcg2_ops,
 641         },
 642 };
 643
 644 static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
 645         F(19200000, P_XO, 1, 0, 0),
 646         { }
 647 };
 648
 649 static struct clk_rcg2 cci_clk_src = {
 650         .cmd_rcgr = 0x3300,
 651         .mnd_width = 8,
 652         .hid_width = 5,
 653         .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
 654         .freq_tbl = ftbl_camss_cci_cci_clk,
 655         .clkr.hw.init = &(struct clk_init_data){
 656                 .name = "cci_clk_src",
 657                 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
 658                 .num_parents = 6,
 659                 .ops = &clk_rcg2_ops,
 660         },
 661 };
 662
 663 static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
 664         F(10000, P_XO, 16, 1, 120),
 665         F(24000, P_XO, 16, 1, 50),
 666         F(6000000, P_GPLL0, 10, 1, 10),
 667         F(12000000, P_GPLL0, 10, 1, 5),
 668         F(13000000, P_GPLL0, 4, 13, 150),
 669         F(24000000, P_GPLL0, 5, 1, 5),
 670         { }
 671 };
 672
 673 static struct clk_rcg2 camss_gp0_clk_src = {
 674         .cmd_rcgr = 0x3420,
 675         .mnd_width = 8,
 676         .hid_width = 5,
 677         .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
 678         .freq_tbl = ftbl_camss_gp0_1_clk,
 679         .clkr.hw.init = &(struct clk_init_data){
 680                 .name = "camss_gp0_clk_src",
 681                 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
 682                 .num_parents = 7,
 683                 .ops = &clk_rcg2_ops,
 684         },
 685 };
 686
 687 static struct clk_rcg2 camss_gp1_clk_src = {
 688         .cmd_rcgr = 0x3450,
 689         .mnd_width = 8,
 690         .hid_width = 5,
 691         .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
 692         .freq_tbl = ftbl_camss_gp0_1_clk,
 693         .clkr.hw.init = &(struct clk_init_data){
 694                 .name = "camss_gp1_clk_src",
 695                 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
 696                 .num_parents = 7,
 697                 .ops = &clk_rcg2_ops,
 698         },
 699 };
 700
 701 static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
 702         F(4800000, P_XO, 4, 0, 0),
 703         F(6000000, P_GPLL0, 10, 1, 10),
 704         F(8000000, P_GPLL0, 15, 1, 5),
 705         F(9600000, P_XO, 2, 0, 0),
 706         F(16000000, P_MMPLL0, 10, 1, 5),
 707         F(19200000, P_XO, 1, 0, 0),
 708         F(24000000, P_GPLL0, 5, 1, 5),
 709         F(32000000, P_MMPLL0, 5, 1, 5),
 710         F(48000000, P_GPLL0, 12.5, 0, 0),
 711         F(64000000, P_MMPLL0, 12.5, 0, 0),
 712         { }
 713 };
 714
 715 static struct clk_rcg2 mclk0_clk_src = {
 716         .cmd_rcgr = 0x3360,
 717         .mnd_width = 8,
 718         .hid_width = 5,
 719         .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
 720         .freq_tbl = ftbl_camss_mclk0_3_clk,
 721         .clkr.hw.init = &(struct clk_init_data){
 722                 .name = "mclk0_clk_src",
 723                 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
 724                 .num_parents = 6,
 725                 .ops = &clk_rcg2_ops,
 726         },
 727 };
 728
 729 static struct clk_rcg2 mclk1_clk_src = {
 730         .cmd_rcgr = 0x3390,
 731         .mnd_width = 8,
 732         .hid_width = 5,
 733         .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
 734         .freq_tbl = ftbl_camss_mclk0_3_clk,
 735         .clkr.hw.init = &(struct clk_init_data){
 736                 .name = "mclk1_clk_src",
 737                 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
 738                 .num_parents = 6,
 739                 .ops = &clk_rcg2_ops,
 740         },
 741 };
 742
 743 static struct clk_rcg2 mclk2_clk_src = {
 744         .cmd_rcgr = 0x33c0,
 745         .mnd_width = 8,
 746         .hid_width = 5,
 747         .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
 748         .freq_tbl = ftbl_camss_mclk0_3_clk,
 749         .clkr.hw.init = &(struct clk_init_data){
 750                 .name = "mclk2_clk_src",
 751                 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
 752                 .num_parents = 6,
 753                 .ops = &clk_rcg2_ops,
 754         },
 755 };
 756
 757 static struct clk_rcg2 mclk3_clk_src = {
 758         .cmd_rcgr = 0x33f0,
 759         .mnd_width = 8,
 760         .hid_width = 5,
 761         .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
 762         .freq_tbl = ftbl_camss_mclk0_3_clk,
 763         .clkr.hw.init = &(struct clk_init_data){
 764                 .name = "mclk3_clk_src",
 765                 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
 766                 .num_parents = 6,
 767                 .ops = &clk_rcg2_ops,
 768         },
 769 };
 770
 771 static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
 772         F(100000000, P_GPLL0, 6, 0, 0),
 773         F(200000000, P_MMPLL0, 4, 0, 0),
 774         { }
 775 };
 776
 777 static struct clk_rcg2 csi0phytimer_clk_src = {
 778         .cmd_rcgr = 0x3000,
 779         .hid_width = 5,
 780         .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
 781         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 782         .clkr.hw.init = &(struct clk_init_data){
 783                 .name = "csi0phytimer_clk_src",
 784                 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
 785                 .num_parents = 5,
 786                 .ops = &clk_rcg2_ops,
 787         },
 788 };
 789
 790 static struct clk_rcg2 csi1phytimer_clk_src = {
 791         .cmd_rcgr = 0x3030,
 792         .hid_width = 5,
 793         .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
 794         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 795         .clkr.hw.init = &(struct clk_init_data){
 796                 .name = "csi1phytimer_clk_src",
 797                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 798                 .num_parents = 5,
 799                 .ops = &clk_rcg2_ops,
 800         },
 801 };
 802
 803 static struct clk_rcg2 csi2phytimer_clk_src = {
 804         .cmd_rcgr = 0x3060,
 805         .hid_width = 5,
 806         .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
 807         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 808         .clkr.hw.init = &(struct clk_init_data){
 809                 .name = "csi2phytimer_clk_src",
 810                 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
 811                 .num_parents = 5,
 812                 .ops = &clk_rcg2_ops,
 813         },
 814 };
 815
 816 static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
 817         F(133330000, P_GPLL0, 4.5, 0, 0),
 818         F(266670000, P_MMPLL0, 3, 0, 0),
 819         F(320000000, P_MMPLL0, 2.5, 0, 0),
 820         F(372000000, P_MMPLL4, 2.5, 0, 0),
 821         F(465000000, P_MMPLL4, 2, 0, 0),
 822         F(600000000, P_GPLL0, 1, 0, 0),
 823         { }
 824 };
 825
 826 static struct clk_rcg2 cpp_clk_src = {
 827         .cmd_rcgr = 0x3640,
 828         .hid_width = 5,
 829         .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
 830         .freq_tbl = ftbl_camss_vfe_cpp_clk,
 831         .clkr.hw.init = &(struct clk_init_data){
 832                 .name = "cpp_clk_src",
 833                 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
 834                 .num_parents = 5,
 835                 .ops = &clk_rcg2_ops,
 836         },
 837 };
 838
 839 static struct clk_rcg2 byte0_clk_src = {
 840         .cmd_rcgr = 0x2120,
 841         .hid_width = 5,
 842         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 843         .clkr.hw.init = &(struct clk_init_data){
 844                 .name = "byte0_clk_src",
 845                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 846                 .num_parents = 6,
 847                 .ops = &clk_byte2_ops,
 848                 .flags = CLK_SET_RATE_PARENT,
 849         },
 850 };
 851
 852 static struct clk_rcg2 byte1_clk_src = {
 853         .cmd_rcgr = 0x2140,
 854         .hid_width = 5,
 855         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 856         .clkr.hw.init = &(struct clk_init_data){
 857                 .name = "byte1_clk_src",
 858                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 859                 .num_parents = 6,
 860                 .ops = &clk_byte2_ops,
 861                 .flags = CLK_SET_RATE_PARENT,
 862         },
 863 };
 864
 865 static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
 866         F(19200000, P_XO, 1, 0, 0),
 867         { }
 868 };
 869
 870 static struct clk_rcg2 edpaux_clk_src = {
 871         .cmd_rcgr = 0x20e0,
 872         .hid_width = 5,
 873         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 874         .freq_tbl = ftbl_mdss_edpaux_clk,
 875         .clkr.hw.init = &(struct clk_init_data){
 876                 .name = "edpaux_clk_src",
 877                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 878                 .num_parents = 4,
 879                 .ops = &clk_rcg2_ops,
 880         },
 881 };
 882
 883 static struct freq_tbl ftbl_mdss_edplink_clk[] = {
 884         F(135000000, P_EDPLINK, 2, 0, 0),
 885         F(270000000, P_EDPLINK, 11, 0, 0),
 886         { }
 887 };
 888
 889 static struct clk_rcg2 edplink_clk_src = {
 890         .cmd_rcgr = 0x20c0,
 891         .hid_width = 5,
 892         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 893         .freq_tbl = ftbl_mdss_edplink_clk,
 894         .clkr.hw.init = &(struct clk_init_data){
 895                 .name = "edplink_clk_src",
 896                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 897                 .num_parents = 6,
 898                 .ops = &clk_rcg2_ops,
 899                 .flags = CLK_SET_RATE_PARENT,
 900         },
 901 };
 902
 903 static struct freq_tbl edp_pixel_freq_tbl[] = {
 904         { .src = P_EDPVCO },
 905         { }
 906 };
 907
 908 static struct clk_rcg2 edppixel_clk_src = {
 909         .cmd_rcgr = 0x20a0,
 910         .mnd_width = 8,
 911         .hid_width = 5,
 912         .parent_map = mmcc_xo_dsi_hdmi_edp_map,
 913         .freq_tbl = edp_pixel_freq_tbl,
 914         .clkr.hw.init = &(struct clk_init_data){
 915                 .name = "edppixel_clk_src",
 916                 .parent_names = mmcc_xo_dsi_hdmi_edp,
 917                 .num_parents = 6,
 918                 .ops = &clk_edp_pixel_ops,
 919         },
 920 };
 921
 922 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
 923         F(19200000, P_XO, 1, 0, 0),
 924         { }
 925 };
 926
 927 static struct clk_rcg2 esc0_clk_src = {
 928         .cmd_rcgr = 0x2160,
 929         .hid_width = 5,
 930         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 931         .freq_tbl = ftbl_mdss_esc0_1_clk,
 932         .clkr.hw.init = &(struct clk_init_data){
 933                 .name = "esc0_clk_src",
 934                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 935                 .num_parents = 6,
 936                 .ops = &clk_rcg2_ops,
 937         },
 938 };
 939
 940 static struct clk_rcg2 esc1_clk_src = {
 941         .cmd_rcgr = 0x2180,
 942         .hid_width = 5,
 943         .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
 944         .freq_tbl = ftbl_mdss_esc0_1_clk,
 945         .clkr.hw.init = &(struct clk_init_data){
 946                 .name = "esc1_clk_src",
 947                 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
 948                 .num_parents = 6,
 949                 .ops = &clk_rcg2_ops,
 950         },
 951 };
 952
 953 static struct freq_tbl extpclk_freq_tbl[] = {
 954         { .src = P_HDMIPLL },
 955         { }
 956 };
 957
 958 static struct clk_rcg2 extpclk_clk_src = {
 959         .cmd_rcgr = 0x2060,
 960         .hid_width = 5,
 961         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 962         .freq_tbl = extpclk_freq_tbl,
 963         .clkr.hw.init = &(struct clk_init_data){
 964                 .name = "extpclk_clk_src",
 965                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 966                 .num_parents = 6,
 967                 .ops = &clk_byte_ops,
 968                 .flags = CLK_SET_RATE_PARENT,
 969         },
 970 };
 971
 972 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
 973         F(19200000, P_XO, 1, 0, 0),
 974         { }
 975 };
 976
 977 static struct clk_rcg2 hdmi_clk_src = {
 978         .cmd_rcgr = 0x2100,
 979         .hid_width = 5,
 980         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 981         .freq_tbl = ftbl_mdss_hdmi_clk,
 982         .clkr.hw.init = &(struct clk_init_data){
 983                 .name = "hdmi_clk_src",
 984                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 985                 .num_parents = 4,
 986                 .ops = &clk_rcg2_ops,
 987         },
 988 };
 989
 990 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
 991         F(19200000, P_XO, 1, 0, 0),
 992         { }
 993 };
 994
 995 static struct clk_rcg2 vsync_clk_src = {
 996         .cmd_rcgr = 0x2080,
 997         .hid_width = 5,
 998         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 999         .freq_tbl = ftbl_mdss_vsync_clk,
1000         .clkr.hw.init = &(struct clk_init_data){
1001                 .name = "vsync_clk_src",
1002                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1003                 .num_parents = 4,
1004                 .ops = &clk_rcg2_ops,
1005         },
1006 };
1007
1008 static struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
1009         F(50000000, P_GPLL0, 12, 0, 0),
1010         { }
1011 };
1012
1013 static struct clk_rcg2 rbcpr_clk_src = {
1014         .cmd_rcgr = 0x4060,
1015         .hid_width = 5,
1016         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1017         .freq_tbl = ftbl_mmss_rbcpr_clk,
1018         .clkr.hw.init = &(struct clk_init_data){
1019                 .name = "rbcpr_clk_src",
1020                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1021                 .num_parents = 4,
1022                 .ops = &clk_rcg2_ops,
1023         },
1024 };
1025
1026 static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
1027         F(19200000, P_XO, 1, 0, 0),
1028         { }
1029 };
1030
1031 static struct clk_rcg2 rbbmtimer_clk_src = {
1032         .cmd_rcgr = 0x4090,
1033         .hid_width = 5,
1034         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1035         .freq_tbl = ftbl_oxili_rbbmtimer_clk,
1036         .clkr.hw.init = &(struct clk_init_data){
1037                 .name = "rbbmtimer_clk_src",
1038                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1039                 .num_parents = 4,
1040                 .ops = &clk_rcg2_ops,
1041         },
1042 };
1043
1044 static struct freq_tbl ftbl_vpu_maple_clk[] = {
1045         F(50000000, P_GPLL0, 12, 0, 0),
1046         F(100000000, P_GPLL0, 6, 0, 0),
1047         F(133330000, P_GPLL0, 4.5, 0, 0),
1048         F(200000000, P_MMPLL0, 4, 0, 0),
1049         F(266670000, P_MMPLL0, 3, 0, 0),
1050         F(465000000, P_MMPLL3, 2, 0, 0),
1051         { }
1052 };
1053
1054 static struct clk_rcg2 maple_clk_src = {
1055         .cmd_rcgr = 0x1320,
1056         .hid_width = 5,
1057         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1058         .freq_tbl = ftbl_vpu_maple_clk,
1059         .clkr.hw.init = &(struct clk_init_data){
1060                 .name = "maple_clk_src",
1061                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1062                 .num_parents = 4,
1063                 .ops = &clk_rcg2_ops,
1064         },
1065 };
1066
1067 static struct freq_tbl ftbl_vpu_vdp_clk[] = {
1068         F(50000000, P_GPLL0, 12, 0, 0),
1069         F(100000000, P_GPLL0, 6, 0, 0),
1070         F(200000000, P_MMPLL0, 4, 0, 0),
1071         F(320000000, P_MMPLL0, 2.5, 0, 0),
1072         F(400000000, P_MMPLL0, 2, 0, 0),
1073         { }
1074 };
1075
1076 static struct clk_rcg2 vdp_clk_src = {
1077         .cmd_rcgr = 0x1300,
1078         .hid_width = 5,
1079         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1080         .freq_tbl = ftbl_vpu_vdp_clk,
1081         .clkr.hw.init = &(struct clk_init_data){
1082                 .name = "vdp_clk_src",
1083                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1084                 .num_parents = 4,
1085                 .ops = &clk_rcg2_ops,
1086         },
1087 };
1088
1089 static struct freq_tbl ftbl_vpu_bus_clk[] = {
1090         F(40000000, P_GPLL0, 15, 0, 0),
1091         F(80000000, P_MMPLL0, 10, 0, 0),
1092         { }
1093 };
1094
1095 static struct clk_rcg2 vpu_bus_clk_src = {
1096         .cmd_rcgr = 0x1340,
1097         .hid_width = 5,
1098         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1099         .freq_tbl = ftbl_vpu_bus_clk,
1100         .clkr.hw.init = &(struct clk_init_data){
1101                 .name = "vpu_bus_clk_src",
1102                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1103                 .num_parents = 4,
1104                 .ops = &clk_rcg2_ops,
1105         },
1106 };
1107
1108 static struct clk_branch mmss_cxo_clk = {
1109         .halt_reg = 0x5104,
1110         .clkr = {
1111                 .enable_reg = 0x5104,
1112                 .enable_mask = BIT(0),
1113                 .hw.init = &(struct clk_init_data){
1114                         .name = "mmss_cxo_clk",
1115                         .parent_names = (const char *[]){ "xo" },
1116                         .num_parents = 1,
1117                         .flags = CLK_SET_RATE_PARENT,
1118                         .ops = &clk_branch2_ops,
1119                 },
1120         },
1121 };
1122
1123 static struct clk_branch mmss_sleepclk_clk = {
1124         .halt_reg = 0x5100,
1125         .clkr = {
1126                 .enable_reg = 0x5100,
1127                 .enable_mask = BIT(0),
1128                 .hw.init = &(struct clk_init_data){
1129                         .name = "mmss_sleepclk_clk",
1130                         .parent_names = (const char *[]){
1131                                 "sleep_clk_src",
1132                         },
1133                         .num_parents = 1,
1134                         .flags = CLK_SET_RATE_PARENT,
1135                         .ops = &clk_branch2_ops,
1136                 },
1137         },
1138 };
1139
1140 static struct clk_branch avsync_ahb_clk = {
1141         .halt_reg = 0x2414,
1142         .clkr = {
1143                 .enable_reg = 0x2414,
1144                 .enable_mask = BIT(0),
1145                 .hw.init = &(struct clk_init_data){
1146                         .name = "avsync_ahb_clk",
1147                         .parent_names = (const char *[]){
1148                                 "mmss_ahb_clk_src",
1149                         },
1150                         .num_parents = 1,
1151                         .flags = CLK_SET_RATE_PARENT,
1152                         .ops = &clk_branch2_ops,
1153                 },
1154         },
1155 };
1156
1157 static struct clk_branch avsync_edppixel_clk = {
1158         .halt_reg = 0x2418,
1159         .clkr = {
1160                 .enable_reg = 0x2418,
1161                 .enable_mask = BIT(0),
1162                 .hw.init = &(struct clk_init_data){
1163                         .name = "avsync_edppixel_clk",
1164                         .parent_names = (const char *[]){
1165                                 "edppixel_clk_src",
1166                         },
1167                         .num_parents = 1,
1168                         .flags = CLK_SET_RATE_PARENT,
1169                         .ops = &clk_branch2_ops,
1170                 },
1171         },
1172 };
1173
1174 static struct clk_branch avsync_extpclk_clk = {
1175         .halt_reg = 0x2410,
1176         .clkr = {
1177                 .enable_reg = 0x2410,
1178                 .enable_mask = BIT(0),
1179                 .hw.init = &(struct clk_init_data){
1180                         .name = "avsync_extpclk_clk",
1181                         .parent_names = (const char *[]){
1182                                 "extpclk_clk_src",
1183                         },
1184                         .num_parents = 1,
1185                         .flags = CLK_SET_RATE_PARENT,
1186                         .ops = &clk_branch2_ops,
1187                 },
1188         },
1189 };
1190
1191 static struct clk_branch avsync_pclk0_clk = {
1192         .halt_reg = 0x241c,
1193         .clkr = {
1194                 .enable_reg = 0x241c,
1195                 .enable_mask = BIT(0),
1196                 .hw.init = &(struct clk_init_data){
1197                         .name = "avsync_pclk0_clk",
1198                         .parent_names = (const char *[]){
1199                                 "pclk0_clk_src",
1200                         },
1201                         .num_parents = 1,
1202                         .flags = CLK_SET_RATE_PARENT,
1203                         .ops = &clk_branch2_ops,
1204                 },
1205         },
1206 };
1207
1208 static struct clk_branch avsync_pclk1_clk = {
1209         .halt_reg = 0x2420,
1210         .clkr = {
1211                 .enable_reg = 0x2420,
1212                 .enable_mask = BIT(0),
1213                 .hw.init = &(struct clk_init_data){
1214                         .name = "avsync_pclk1_clk",
1215                         .parent_names = (const char *[]){
1216                                 "pclk1_clk_src",
1217                         },
1218                         .num_parents = 1,
1219                         .flags = CLK_SET_RATE_PARENT,
1220                         .ops = &clk_branch2_ops,
1221                 },
1222         },
1223 };
1224
1225 static struct clk_branch avsync_vp_clk = {
1226         .halt_reg = 0x2404,
1227         .clkr = {
1228                 .enable_reg = 0x2404,
1229                 .enable_mask = BIT(0),
1230                 .hw.init = &(struct clk_init_data){
1231                         .name = "avsync_vp_clk",
1232                         .parent_names = (const char *[]){
1233                                 "vp_clk_src",
1234                         },
1235                         .num_parents = 1,
1236                         .flags = CLK_SET_RATE_PARENT,
1237                         .ops = &clk_branch2_ops,
1238                 },
1239         },
1240 };
1241
1242 static struct clk_branch camss_ahb_clk = {
1243         .halt_reg = 0x348c,
1244         .clkr = {
1245                 .enable_reg = 0x348c,
1246                 .enable_mask = BIT(0),
1247                 .hw.init = &(struct clk_init_data){
1248                         .name = "camss_ahb_clk",
1249                         .parent_names = (const char *[]){
1250                                 "mmss_ahb_clk_src",
1251                         },
1252                         .num_parents = 1,
1253                         .flags = CLK_SET_RATE_PARENT,
1254                         .ops = &clk_branch2_ops,
1255                 },
1256         },
1257 };
1258
1259 static struct clk_branch camss_cci_cci_ahb_clk = {
1260         .halt_reg = 0x3348,
1261         .clkr = {
1262                 .enable_reg = 0x3348,
1263                 .enable_mask = BIT(0),
1264                 .hw.init = &(struct clk_init_data){
1265                         .name = "camss_cci_cci_ahb_clk",
1266                         .parent_names = (const char *[]){
1267                                 "mmss_ahb_clk_src",
1268                         },
1269                         .num_parents = 1,
1270                         .ops = &clk_branch2_ops,
1271                 },
1272         },
1273 };
1274
1275 static struct clk_branch camss_cci_cci_clk = {
1276         .halt_reg = 0x3344,
1277         .clkr = {
1278                 .enable_reg = 0x3344,
1279                 .enable_mask = BIT(0),
1280                 .hw.init = &(struct clk_init_data){
1281                         .name = "camss_cci_cci_clk",
1282                         .parent_names = (const char *[]){
1283                                 "cci_clk_src",
1284                         },
1285                         .num_parents = 1,
1286                         .flags = CLK_SET_RATE_PARENT,
1287                         .ops = &clk_branch2_ops,
1288                 },
1289         },
1290 };
1291
1292 static struct clk_branch camss_csi0_ahb_clk = {
1293         .halt_reg = 0x30bc,
1294         .clkr = {
1295                 .enable_reg = 0x30bc,
1296                 .enable_mask = BIT(0),
1297                 .hw.init = &(struct clk_init_data){
1298                         .name = "camss_csi0_ahb_clk",
1299                         .parent_names = (const char *[]){
1300                                 "mmss_ahb_clk_src",
1301                         },
1302                         .num_parents = 1,
1303                         .ops = &clk_branch2_ops,
1304                 },
1305         },
1306 };
1307
1308 static struct clk_branch camss_csi0_clk = {
1309         .halt_reg = 0x30b4,
1310         .clkr = {
1311                 .enable_reg = 0x30b4,
1312                 .enable_mask = BIT(0),
1313                 .hw.init = &(struct clk_init_data){
1314                         .name = "camss_csi0_clk",
1315                         .parent_names = (const char *[]){
1316                                 "csi0_clk_src",
1317                         },
1318                         .num_parents = 1,
1319                         .flags = CLK_SET_RATE_PARENT,
1320                         .ops = &clk_branch2_ops,
1321                 },
1322         },
1323 };
1324
1325 static struct clk_branch camss_csi0phy_clk = {
1326         .halt_reg = 0x30c4,
1327         .clkr = {
1328                 .enable_reg = 0x30c4,
1329                 .enable_mask = BIT(0),
1330                 .hw.init = &(struct clk_init_data){
1331                         .name = "camss_csi0phy_clk",
1332                         .parent_names = (const char *[]){
1333                                 "csi0_clk_src",
1334                         },
1335                         .num_parents = 1,
1336                         .flags = CLK_SET_RATE_PARENT,
1337                         .ops = &clk_branch2_ops,
1338                 },
1339         },
1340 };
1341
1342 static struct clk_branch camss_csi0pix_clk = {
1343         .halt_reg = 0x30e4,
1344         .clkr = {
1345                 .enable_reg = 0x30e4,
1346                 .enable_mask = BIT(0),
1347                 .hw.init = &(struct clk_init_data){
1348                         .name = "camss_csi0pix_clk",
1349                         .parent_names = (const char *[]){
1350                                 "csi0_clk_src",
1351                         },
1352                         .num_parents = 1,
1353                         .flags = CLK_SET_RATE_PARENT,
1354                         .ops = &clk_branch2_ops,
1355                 },
1356         },
1357 };
1358
1359 static struct clk_branch camss_csi0rdi_clk = {
1360         .halt_reg = 0x30d4,
1361         .clkr = {
1362                 .enable_reg = 0x30d4,
1363                 .enable_mask = BIT(0),
1364                 .hw.init = &(struct clk_init_data){
1365                         .name = "camss_csi0rdi_clk",
1366                         .parent_names = (const char *[]){
1367                                 "csi0_clk_src",
1368                         },
1369                         .num_parents = 1,
1370                         .flags = CLK_SET_RATE_PARENT,
1371                         .ops = &clk_branch2_ops,
1372                 },
1373         },
1374 };
1375
1376 static struct clk_branch camss_csi1_ahb_clk = {
1377         .halt_reg = 0x3128,
1378         .clkr = {
1379                 .enable_reg = 0x3128,
1380                 .enable_mask = BIT(0),
1381                 .hw.init = &(struct clk_init_data){
1382                         .name = "camss_csi1_ahb_clk",
1383                         .parent_names = (const char *[]){
1384                                 "mmss_ahb_clk_src",
1385                         },
1386                         .num_parents = 1,
1387                         .flags = CLK_SET_RATE_PARENT,
1388                         .ops = &clk_branch2_ops,
1389                 },
1390         },
1391 };
1392
1393 static struct clk_branch camss_csi1_clk = {
1394         .halt_reg = 0x3124,
1395         .clkr = {
1396                 .enable_reg = 0x3124,
1397                 .enable_mask = BIT(0),
1398                 .hw.init = &(struct clk_init_data){
1399                         .name = "camss_csi1_clk",
1400                         .parent_names = (const char *[]){
1401                                 "csi1_clk_src",
1402                         },
1403                         .num_parents = 1,
1404                         .flags = CLK_SET_RATE_PARENT,
1405                         .ops = &clk_branch2_ops,
1406                 },
1407         },
1408 };
1409
1410 static struct clk_branch camss_csi1phy_clk = {
1411         .halt_reg = 0x3134,
1412         .clkr = {
1413                 .enable_reg = 0x3134,
1414                 .enable_mask = BIT(0),
1415                 .hw.init = &(struct clk_init_data){
1416                         .name = "camss_csi1phy_clk",
1417                         .parent_names = (const char *[]){
1418                                 "csi1_clk_src",
1419                         },
1420                         .num_parents = 1,
1421                         .flags = CLK_SET_RATE_PARENT,
1422                         .ops = &clk_branch2_ops,
1423                 },
1424         },
1425 };
1426
1427 static struct clk_branch camss_csi1pix_clk = {
1428         .halt_reg = 0x3154,
1429         .clkr = {
1430                 .enable_reg = 0x3154,
1431                 .enable_mask = BIT(0),
1432                 .hw.init = &(struct clk_init_data){
1433                         .name = "camss_csi1pix_clk",
1434                         .parent_names = (const char *[]){
1435                                 "csi1_clk_src",
1436                         },
1437                         .num_parents = 1,
1438                         .flags = CLK_SET_RATE_PARENT,
1439                         .ops = &clk_branch2_ops,
1440                 },
1441         },
1442 };
1443
1444 static struct clk_branch camss_csi1rdi_clk = {
1445         .halt_reg = 0x3144,
1446         .clkr = {
1447                 .enable_reg = 0x3144,
1448                 .enable_mask = BIT(0),
1449                 .hw.init = &(struct clk_init_data){
1450                         .name = "camss_csi1rdi_clk",
1451                         .parent_names = (const char *[]){
1452                                 "csi1_clk_src",
1453                         },
1454                         .num_parents = 1,
1455                         .flags = CLK_SET_RATE_PARENT,
1456                         .ops = &clk_branch2_ops,
1457                 },
1458         },
1459 };
1460
1461 static struct clk_branch camss_csi2_ahb_clk = {
1462         .halt_reg = 0x3188,
1463         .clkr = {
1464                 .enable_reg = 0x3188,
1465                 .enable_mask = BIT(0),
1466                 .hw.init = &(struct clk_init_data){
1467                         .name = "camss_csi2_ahb_clk",
1468                         .parent_names = (const char *[]){
1469                                 "mmss_ahb_clk_src",
1470                         },
1471                         .num_parents = 1,
1472                         .ops = &clk_branch2_ops,
1473                 },
1474         },
1475 };
1476
1477 static struct clk_branch camss_csi2_clk = {
1478         .halt_reg = 0x3184,
1479         .clkr = {
1480                 .enable_reg = 0x3184,
1481                 .enable_mask = BIT(0),
1482                 .hw.init = &(struct clk_init_data){
1483                         .name = "camss_csi2_clk",
1484                         .parent_names = (const char *[]){
1485                                 "csi2_clk_src",
1486                         },
1487                         .num_parents = 1,
1488                         .flags = CLK_SET_RATE_PARENT,
1489                         .ops = &clk_branch2_ops,
1490                 },
1491         },
1492 };
1493
1494 static struct clk_branch camss_csi2phy_clk = {
1495         .halt_reg = 0x3194,
1496         .clkr = {
1497                 .enable_reg = 0x3194,
1498                 .enable_mask = BIT(0),
1499                 .hw.init = &(struct clk_init_data){
1500                         .name = "camss_csi2phy_clk",
1501                         .parent_names = (const char *[]){
1502                                 "csi2_clk_src",
1503                         },
1504                         .num_parents = 1,
1505                         .flags = CLK_SET_RATE_PARENT,
1506                         .ops = &clk_branch2_ops,
1507                 },
1508         },
1509 };
1510
1511 static struct clk_branch camss_csi2pix_clk = {
1512         .halt_reg = 0x31b4,
1513         .clkr = {
1514                 .enable_reg = 0x31b4,
1515                 .enable_mask = BIT(0),
1516                 .hw.init = &(struct clk_init_data){
1517                         .name = "camss_csi2pix_clk",
1518                         .parent_names = (const char *[]){
1519                                 "csi2_clk_src",
1520                         },
1521                         .num_parents = 1,
1522                         .flags = CLK_SET_RATE_PARENT,
1523                         .ops = &clk_branch2_ops,
1524                 },
1525         },
1526 };
1527
1528 static struct clk_branch camss_csi2rdi_clk = {
1529         .halt_reg = 0x31a4,
1530         .clkr = {
1531                 .enable_reg = 0x31a4,
1532                 .enable_mask = BIT(0),
1533                 .hw.init = &(struct clk_init_data){
1534                         .name = "camss_csi2rdi_clk",
1535                         .parent_names = (const char *[]){
1536                                 "csi2_clk_src",
1537                         },
1538                         .num_parents = 1,
1539                         .flags = CLK_SET_RATE_PARENT,
1540                         .ops = &clk_branch2_ops,
1541                 },
1542         },
1543 };
1544
1545 static struct clk_branch camss_csi3_ahb_clk = {
1546         .halt_reg = 0x31e8,
1547         .clkr = {
1548                 .enable_reg = 0x31e8,
1549                 .enable_mask = BIT(0),
1550                 .hw.init = &(struct clk_init_data){
1551                         .name = "camss_csi3_ahb_clk",
1552                         .parent_names = (const char *[]){
1553                                 "mmss_ahb_clk_src",
1554                         },
1555                         .num_parents = 1,
1556                         .ops = &clk_branch2_ops,
1557                 },
1558         },
1559 };
1560
1561 static struct clk_branch camss_csi3_clk = {
1562         .halt_reg = 0x31e4,
1563         .clkr = {
1564                 .enable_reg = 0x31e4,
1565                 .enable_mask = BIT(0),
1566                 .hw.init = &(struct clk_init_data){
1567                         .name = "camss_csi3_clk",
1568                         .parent_names = (const char *[]){
1569                                 "csi3_clk_src",
1570                         },
1571                         .num_parents = 1,
1572                         .flags = CLK_SET_RATE_PARENT,
1573                         .ops = &clk_branch2_ops,
1574                 },
1575         },
1576 };
1577
1578 static struct clk_branch camss_csi3phy_clk = {
1579         .halt_reg = 0x31f4,
1580         .clkr = {
1581                 .enable_reg = 0x31f4,
1582                 .enable_mask = BIT(0),
1583                 .hw.init = &(struct clk_init_data){
1584                         .name = "camss_csi3phy_clk",
1585                         .parent_names = (const char *[]){
1586                                 "csi3_clk_src",
1587                         },
1588                         .num_parents = 1,
1589                         .flags = CLK_SET_RATE_PARENT,
1590                         .ops = &clk_branch2_ops,
1591                 },
1592         },
1593 };
1594
1595 static struct clk_branch camss_csi3pix_clk = {
1596         .halt_reg = 0x3214,
1597         .clkr = {
1598                 .enable_reg = 0x3214,
1599                 .enable_mask = BIT(0),
1600                 .hw.init = &(struct clk_init_data){
1601                         .name = "camss_csi3pix_clk",
1602                         .parent_names = (const char *[]){
1603                                 "csi3_clk_src",
1604                         },
1605                         .num_parents = 1,
1606                         .flags = CLK_SET_RATE_PARENT,
1607                         .ops = &clk_branch2_ops,
1608                 },
1609         },
1610 };
1611
1612 static struct clk_branch camss_csi3rdi_clk = {
1613         .halt_reg = 0x3204,
1614         .clkr = {
1615                 .enable_reg = 0x3204,
1616                 .enable_mask = BIT(0),
1617                 .hw.init = &(struct clk_init_data){
1618                         .name = "camss_csi3rdi_clk",
1619                         .parent_names = (const char *[]){
1620                                 "csi3_clk_src",
1621                         },
1622                         .num_parents = 1,
1623                         .flags = CLK_SET_RATE_PARENT,
1624                         .ops = &clk_branch2_ops,
1625                 },
1626         },
1627 };
1628
1629 static struct clk_branch camss_csi_vfe0_clk = {
1630         .halt_reg = 0x3704,
1631         .clkr = {
1632                 .enable_reg = 0x3704,
1633                 .enable_mask = BIT(0),
1634                 .hw.init = &(struct clk_init_data){
1635                         .name = "camss_csi_vfe0_clk",
1636                         .parent_names = (const char *[]){
1637                                 "vfe0_clk_src",
1638                         },
1639                         .num_parents = 1,
1640                         .flags = CLK_SET_RATE_PARENT,
1641                         .ops = &clk_branch2_ops,
1642                 },
1643         },
1644 };
1645
1646 static struct clk_branch camss_csi_vfe1_clk = {
1647         .halt_reg = 0x3714,
1648         .clkr = {
1649                 .enable_reg = 0x3714,
1650                 .enable_mask = BIT(0),
1651                 .hw.init = &(struct clk_init_data){
1652                         .name = "camss_csi_vfe1_clk",
1653                         .parent_names = (const char *[]){
1654                                 "vfe1_clk_src",
1655                         },
1656                         .num_parents = 1,
1657                         .flags = CLK_SET_RATE_PARENT,
1658                         .ops = &clk_branch2_ops,
1659                 },
1660         },
1661 };
1662
1663 static struct clk_branch camss_gp0_clk = {
1664         .halt_reg = 0x3444,
1665         .clkr = {
1666                 .enable_reg = 0x3444,
1667                 .enable_mask = BIT(0),
1668                 .hw.init = &(struct clk_init_data){
1669                         .name = "camss_gp0_clk",
1670                         .parent_names = (const char *[]){
1671                                 "camss_gp0_clk_src",
1672                         },
1673                         .num_parents = 1,
1674                         .flags = CLK_SET_RATE_PARENT,
1675                         .ops = &clk_branch2_ops,
1676                 },
1677         },
1678 };
1679
1680 static struct clk_branch camss_gp1_clk = {
1681         .halt_reg = 0x3474,
1682         .clkr = {
1683                 .enable_reg = 0x3474,
1684                 .enable_mask = BIT(0),
1685                 .hw.init = &(struct clk_init_data){
1686                         .name = "camss_gp1_clk",
1687                         .parent_names = (const char *[]){
1688                                 "camss_gp1_clk_src",
1689                         },
1690                         .num_parents = 1,
1691                         .flags = CLK_SET_RATE_PARENT,
1692                         .ops = &clk_branch2_ops,
1693                 },
1694         },
1695 };
1696
1697 static struct clk_branch camss_ispif_ahb_clk = {
1698         .halt_reg = 0x3224,
1699         .clkr = {
1700                 .enable_reg = 0x3224,
1701                 .enable_mask = BIT(0),
1702                 .hw.init = &(struct clk_init_data){
1703                         .name = "camss_ispif_ahb_clk",
1704                         .parent_names = (const char *[]){
1705                                 "mmss_ahb_clk_src",
1706                         },
1707                         .num_parents = 1,
1708                         .flags = CLK_SET_RATE_PARENT,
1709                         .ops = &clk_branch2_ops,
1710                 },
1711         },
1712 };
1713
1714 static struct clk_branch camss_jpeg_jpeg0_clk = {
1715         .halt_reg = 0x35a8,
1716         .clkr = {
1717                 .enable_reg = 0x35a8,
1718                 .enable_mask = BIT(0),
1719                 .hw.init = &(struct clk_init_data){
1720                         .name = "camss_jpeg_jpeg0_clk",
1721                         .parent_names = (const char *[]){
1722                                 "jpeg0_clk_src",
1723                         },
1724                         .num_parents = 1,
1725                         .flags = CLK_SET_RATE_PARENT,
1726                         .ops = &clk_branch2_ops,
1727                 },
1728         },
1729 };
1730
1731 static struct clk_branch camss_jpeg_jpeg1_clk = {
1732         .halt_reg = 0x35ac,
1733         .clkr = {
1734                 .enable_reg = 0x35ac,
1735                 .enable_mask = BIT(0),
1736                 .hw.init = &(struct clk_init_data){
1737                         .name = "camss_jpeg_jpeg1_clk",
1738                         .parent_names = (const char *[]){
1739                                 "jpeg1_clk_src",
1740                         },
1741                         .num_parents = 1,
1742                         .flags = CLK_SET_RATE_PARENT,
1743                         .ops = &clk_branch2_ops,
1744                 },
1745         },
1746 };
1747
1748 static struct clk_branch camss_jpeg_jpeg2_clk = {
1749         .halt_reg = 0x35b0,
1750         .clkr = {
1751                 .enable_reg = 0x35b0,
1752                 .enable_mask = BIT(0),
1753                 .hw.init = &(struct clk_init_data){
1754                         .name = "camss_jpeg_jpeg2_clk",
1755                         .parent_names = (const char *[]){
1756                                 "jpeg2_clk_src",
1757                         },
1758                         .num_parents = 1,
1759                         .flags = CLK_SET_RATE_PARENT,
1760                         .ops = &clk_branch2_ops,
1761                 },
1762         },
1763 };
1764
1765 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1766         .halt_reg = 0x35b4,
1767         .clkr = {
1768                 .enable_reg = 0x35b4,
1769                 .enable_mask = BIT(0),
1770                 .hw.init = &(struct clk_init_data){
1771                         .name = "camss_jpeg_jpeg_ahb_clk",
1772                         .parent_names = (const char *[]){
1773                                 "mmss_ahb_clk_src",
1774                         },
1775                         .num_parents = 1,
1776                         .ops = &clk_branch2_ops,
1777                 },
1778         },
1779 };
1780
1781 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1782         .halt_reg = 0x35b8,
1783         .clkr = {
1784                 .enable_reg = 0x35b8,
1785                 .enable_mask = BIT(0),
1786                 .hw.init = &(struct clk_init_data){
1787                         .name = "camss_jpeg_jpeg_axi_clk",
1788                         .parent_names = (const char *[]){
1789                                 "mmss_axi_clk_src",
1790                         },
1791                         .num_parents = 1,
1792                         .ops = &clk_branch2_ops,
1793                 },
1794         },
1795 };
1796
1797 static struct clk_branch camss_mclk0_clk = {
1798         .halt_reg = 0x3384,
1799         .clkr = {
1800                 .enable_reg = 0x3384,
1801                 .enable_mask = BIT(0),
1802                 .hw.init = &(struct clk_init_data){
1803                         .name = "camss_mclk0_clk",
1804                         .parent_names = (const char *[]){
1805                                 "mclk0_clk_src",
1806                         },
1807                         .num_parents = 1,
1808                         .flags = CLK_SET_RATE_PARENT,
1809                         .ops = &clk_branch2_ops,
1810                 },
1811         },
1812 };
1813
1814 static struct clk_branch camss_mclk1_clk = {
1815         .halt_reg = 0x33b4,
1816         .clkr = {
1817                 .enable_reg = 0x33b4,
1818                 .enable_mask = BIT(0),
1819                 .hw.init = &(struct clk_init_data){
1820                         .name = "camss_mclk1_clk",
1821                         .parent_names = (const char *[]){
1822                                 "mclk1_clk_src",
1823                         },
1824                         .num_parents = 1,
1825                         .flags = CLK_SET_RATE_PARENT,
1826                         .ops = &clk_branch2_ops,
1827                 },
1828         },
1829 };
1830
1831 static struct clk_branch camss_mclk2_clk = {
1832         .halt_reg = 0x33e4,
1833         .clkr = {
1834                 .enable_reg = 0x33e4,
1835                 .enable_mask = BIT(0),
1836                 .hw.init = &(struct clk_init_data){
1837                         .name = "camss_mclk2_clk",
1838                         .parent_names = (const char *[]){
1839                                 "mclk2_clk_src",
1840                         },
1841                         .num_parents = 1,
1842                         .flags = CLK_SET_RATE_PARENT,
1843                         .ops = &clk_branch2_ops,
1844                 },
1845         },
1846 };
1847
1848 static struct clk_branch camss_mclk3_clk = {
1849         .halt_reg = 0x3414,
1850         .clkr = {
1851                 .enable_reg = 0x3414,
1852                 .enable_mask = BIT(0),
1853                 .hw.init = &(struct clk_init_data){
1854                         .name = "camss_mclk3_clk",
1855                         .parent_names = (const char *[]){
1856                                 "mclk3_clk_src",
1857                         },
1858                         .num_parents = 1,
1859                         .flags = CLK_SET_RATE_PARENT,
1860                         .ops = &clk_branch2_ops,
1861                 },
1862         },
1863 };
1864
1865 static struct clk_branch camss_micro_ahb_clk = {
1866         .halt_reg = 0x3494,
1867         .clkr = {
1868                 .enable_reg = 0x3494,
1869                 .enable_mask = BIT(0),
1870                 .hw.init = &(struct clk_init_data){
1871                         .name = "camss_micro_ahb_clk",
1872                         .parent_names = (const char *[]){
1873                                 "mmss_ahb_clk_src",
1874                         },
1875                         .num_parents = 1,
1876                         .ops = &clk_branch2_ops,
1877                 },
1878         },
1879 };
1880
1881 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1882         .halt_reg = 0x3024,
1883         .clkr = {
1884                 .enable_reg = 0x3024,
1885                 .enable_mask = BIT(0),
1886                 .hw.init = &(struct clk_init_data){
1887                         .name = "camss_phy0_csi0phytimer_clk",
1888                         .parent_names = (const char *[]){
1889                                 "csi0phytimer_clk_src",
1890                         },
1891                         .num_parents = 1,
1892                         .flags = CLK_SET_RATE_PARENT,
1893                         .ops = &clk_branch2_ops,
1894                 },
1895         },
1896 };
1897
1898 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1899         .halt_reg = 0x3054,
1900         .clkr = {
1901                 .enable_reg = 0x3054,
1902                 .enable_mask = BIT(0),
1903                 .hw.init = &(struct clk_init_data){
1904                         .name = "camss_phy1_csi1phytimer_clk",
1905                         .parent_names = (const char *[]){
1906                                 "csi1phytimer_clk_src",
1907                         },
1908                         .num_parents = 1,
1909                         .flags = CLK_SET_RATE_PARENT,
1910                         .ops = &clk_branch2_ops,
1911                 },
1912         },
1913 };
1914
1915 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1916         .halt_reg = 0x3084,
1917         .clkr = {
1918                 .enable_reg = 0x3084,
1919                 .enable_mask = BIT(0),
1920                 .hw.init = &(struct clk_init_data){
1921                         .name = "camss_phy2_csi2phytimer_clk",
1922                         .parent_names = (const char *[]){
1923                                 "csi2phytimer_clk_src",
1924                         },
1925                         .num_parents = 1,
1926                         .flags = CLK_SET_RATE_PARENT,
1927                         .ops = &clk_branch2_ops,
1928                 },
1929         },
1930 };
1931
1932 static struct clk_branch camss_top_ahb_clk = {
1933         .halt_reg = 0x3484,
1934         .clkr = {
1935                 .enable_reg = 0x3484,
1936                 .enable_mask = BIT(0),
1937                 .hw.init = &(struct clk_init_data){
1938                         .name = "camss_top_ahb_clk",
1939                         .parent_names = (const char *[]){
1940                                 "mmss_ahb_clk_src",
1941                         },
1942                         .num_parents = 1,
1943                         .flags = CLK_SET_RATE_PARENT,
1944                         .ops = &clk_branch2_ops,
1945                 },
1946         },
1947 };
1948
1949 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1950         .halt_reg = 0x36b4,
1951         .clkr = {
1952                 .enable_reg = 0x36b4,
1953                 .enable_mask = BIT(0),
1954                 .hw.init = &(struct clk_init_data){
1955                         .name = "camss_vfe_cpp_ahb_clk",
1956                         .parent_names = (const char *[]){
1957                                 "mmss_ahb_clk_src",
1958                         },
1959                         .num_parents = 1,
1960                         .flags = CLK_SET_RATE_PARENT,
1961                         .ops = &clk_branch2_ops,
1962                 },
1963         },
1964 };
1965
1966 static struct clk_branch camss_vfe_cpp_clk = {
1967         .halt_reg = 0x36b0,
1968         .clkr = {
1969                 .enable_reg = 0x36b0,
1970                 .enable_mask = BIT(0),
1971                 .hw.init = &(struct clk_init_data){
1972                         .name = "camss_vfe_cpp_clk",
1973                         .parent_names = (const char *[]){
1974                                 "cpp_clk_src",
1975                         },
1976                         .num_parents = 1,
1977                         .flags = CLK_SET_RATE_PARENT,
1978                         .ops = &clk_branch2_ops,
1979                 },
1980         },
1981 };
1982
1983 static struct clk_branch camss_vfe_vfe0_clk = {
1984         .halt_reg = 0x36a8,
1985         .clkr = {
1986                 .enable_reg = 0x36a8,
1987                 .enable_mask = BIT(0),
1988                 .hw.init = &(struct clk_init_data){
1989                         .name = "camss_vfe_vfe0_clk",
1990                         .parent_names = (const char *[]){
1991                                 "vfe0_clk_src",
1992                         },
1993                         .num_parents = 1,
1994                         .flags = CLK_SET_RATE_PARENT,
1995                         .ops = &clk_branch2_ops,
1996                 },
1997         },
1998 };
1999
2000 static struct clk_branch camss_vfe_vfe1_clk = {
2001         .halt_reg = 0x36ac,
2002         .clkr = {
2003                 .enable_reg = 0x36ac,
2004                 .enable_mask = BIT(0),
2005                 .hw.init = &(struct clk_init_data){
2006                         .name = "camss_vfe_vfe1_clk",
2007                         .parent_names = (const char *[]){
2008                                 "vfe1_clk_src",
2009                         },
2010                         .num_parents = 1,
2011                         .flags = CLK_SET_RATE_PARENT,
2012                         .ops = &clk_branch2_ops,
2013                 },
2014         },
2015 };
2016
2017 static struct clk_branch camss_vfe_vfe_ahb_clk = {
2018         .halt_reg = 0x36b8,
2019         .clkr = {
2020                 .enable_reg = 0x36b8,
2021                 .enable_mask = BIT(0),
2022                 .hw.init = &(struct clk_init_data){
2023                         .name = "camss_vfe_vfe_ahb_clk",
2024                         .parent_names = (const char *[]){
2025                                 "mmss_ahb_clk_src",
2026                         },
2027                         .num_parents = 1,
2028                         .flags = CLK_SET_RATE_PARENT,
2029                         .ops = &clk_branch2_ops,
2030                 },
2031         },
2032 };
2033
2034 static struct clk_branch camss_vfe_vfe_axi_clk = {
2035         .halt_reg = 0x36bc,
2036         .clkr = {
2037                 .enable_reg = 0x36bc,
2038                 .enable_mask = BIT(0),
2039                 .hw.init = &(struct clk_init_data){
2040                         .name = "camss_vfe_vfe_axi_clk",
2041                         .parent_names = (const char *[]){
2042                                 "mmss_axi_clk_src",
2043                         },
2044                         .num_parents = 1,
2045                         .flags = CLK_SET_RATE_PARENT,
2046                         .ops = &clk_branch2_ops,
2047                 },
2048         },
2049 };
2050
2051 static struct clk_branch mdss_ahb_clk = {
2052         .halt_reg = 0x2308,
2053         .clkr = {
2054                 .enable_reg = 0x2308,
2055                 .enable_mask = BIT(0),
2056                 .hw.init = &(struct clk_init_data){
2057                         .name = "mdss_ahb_clk",
2058                         .parent_names = (const char *[]){
2059                                 "mmss_ahb_clk_src",
2060                         },
2061                         .num_parents = 1,
2062                         .flags = CLK_SET_RATE_PARENT,
2063                         .ops = &clk_branch2_ops,
2064                 },
2065         },
2066 };
2067
2068 static struct clk_branch mdss_axi_clk = {
2069         .halt_reg = 0x2310,
2070         .clkr = {
2071                 .enable_reg = 0x2310,
2072                 .enable_mask = BIT(0),
2073                 .hw.init = &(struct clk_init_data){
2074                         .name = "mdss_axi_clk",
2075                         .parent_names = (const char *[]){
2076                                 "mmss_axi_clk_src",
2077                         },
2078                         .num_parents = 1,
2079                         .flags = CLK_SET_RATE_PARENT,
2080                         .ops = &clk_branch2_ops,
2081                 },
2082         },
2083 };
2084
2085 static struct clk_branch mdss_byte0_clk = {
2086         .halt_reg = 0x233c,
2087         .clkr = {
2088                 .enable_reg = 0x233c,
2089                 .enable_mask = BIT(0),
2090                 .hw.init = &(struct clk_init_data){
2091                         .name = "mdss_byte0_clk",
2092                         .parent_names = (const char *[]){
2093                                 "byte0_clk_src",
2094                         },
2095                         .num_parents = 1,
2096                         .flags = CLK_SET_RATE_PARENT,
2097                         .ops = &clk_branch2_ops,
2098                 },
2099         },
2100 };
2101
2102 static struct clk_branch mdss_byte1_clk = {
2103         .halt_reg = 0x2340,
2104         .clkr = {
2105                 .enable_reg = 0x2340,
2106                 .enable_mask = BIT(0),
2107                 .hw.init = &(struct clk_init_data){
2108                         .name = "mdss_byte1_clk",
2109                         .parent_names = (const char *[]){
2110                                 "byte1_clk_src",
2111                         },
2112                         .num_parents = 1,
2113                         .flags = CLK_SET_RATE_PARENT,
2114                         .ops = &clk_branch2_ops,
2115                 },
2116         },
2117 };
2118
2119 static struct clk_branch mdss_edpaux_clk = {
2120         .halt_reg = 0x2334,
2121         .clkr = {
2122                 .enable_reg = 0x2334,
2123                 .enable_mask = BIT(0),
2124                 .hw.init = &(struct clk_init_data){
2125                         .name = "mdss_edpaux_clk",
2126                         .parent_names = (const char *[]){
2127                                 "edpaux_clk_src",
2128                         },
2129                         .num_parents = 1,
2130                         .flags = CLK_SET_RATE_PARENT,
2131                         .ops = &clk_branch2_ops,
2132                 },
2133         },
2134 };
2135
2136 static struct clk_branch mdss_edplink_clk = {
2137         .halt_reg = 0x2330,
2138         .clkr = {
2139                 .enable_reg = 0x2330,
2140                 .enable_mask = BIT(0),
2141                 .hw.init = &(struct clk_init_data){
2142                         .name = "mdss_edplink_clk",
2143                         .parent_names = (const char *[]){
2144                                 "edplink_clk_src",
2145                         },
2146                         .num_parents = 1,
2147                         .flags = CLK_SET_RATE_PARENT,
2148                         .ops = &clk_branch2_ops,
2149                 },
2150         },
2151 };
2152
2153 static struct clk_branch mdss_edppixel_clk = {
2154         .halt_reg = 0x232c,
2155         .clkr = {
2156                 .enable_reg = 0x232c,
2157                 .enable_mask = BIT(0),
2158                 .hw.init = &(struct clk_init_data){
2159                         .name = "mdss_edppixel_clk",
2160                         .parent_names = (const char *[]){
2161                                 "edppixel_clk_src",
2162                         },
2163                         .num_parents = 1,
2164                         .flags = CLK_SET_RATE_PARENT,
2165                         .ops = &clk_branch2_ops,
2166                 },
2167         },
2168 };
2169
2170 static struct clk_branch mdss_esc0_clk = {
2171         .halt_reg = 0x2344,
2172         .clkr = {
2173                 .enable_reg = 0x2344,
2174                 .enable_mask = BIT(0),
2175                 .hw.init = &(struct clk_init_data){
2176                         .name = "mdss_esc0_clk",
2177                         .parent_names = (const char *[]){
2178                                 "esc0_clk_src",
2179                         },
2180                         .num_parents = 1,
2181                         .flags = CLK_SET_RATE_PARENT,
2182                         .ops = &clk_branch2_ops,
2183                 },
2184         },
2185 };
2186
2187 static struct clk_branch mdss_esc1_clk = {
2188         .halt_reg = 0x2348,
2189         .clkr = {
2190                 .enable_reg = 0x2348,
2191                 .enable_mask = BIT(0),
2192                 .hw.init = &(struct clk_init_data){
2193                         .name = "mdss_esc1_clk",
2194                         .parent_names = (const char *[]){
2195                                 "esc1_clk_src",
2196                         },
2197                         .num_parents = 1,
2198                         .flags = CLK_SET_RATE_PARENT,
2199                         .ops = &clk_branch2_ops,
2200                 },
2201         },
2202 };
2203
2204 static struct clk_branch mdss_extpclk_clk = {
2205         .halt_reg = 0x2324,
2206         .clkr = {
2207                 .enable_reg = 0x2324,
2208                 .enable_mask = BIT(0),
2209                 .hw.init = &(struct clk_init_data){
2210                         .name = "mdss_extpclk_clk",
2211                         .parent_names = (const char *[]){
2212                                 "extpclk_clk_src",
2213                         },
2214                         .num_parents = 1,
2215                         .flags = CLK_SET_RATE_PARENT,
2216                         .ops = &clk_branch2_ops,
2217                 },
2218         },
2219 };
2220
2221 static struct clk_branch mdss_hdmi_ahb_clk = {
2222         .halt_reg = 0x230c,
2223         .clkr = {
2224                 .enable_reg = 0x230c,
2225                 .enable_mask = BIT(0),
2226                 .hw.init = &(struct clk_init_data){
2227                         .name = "mdss_hdmi_ahb_clk",
2228                         .parent_names = (const char *[]){
2229                                 "mmss_ahb_clk_src",
2230                         },
2231                         .num_parents = 1,
2232                         .flags = CLK_SET_RATE_PARENT,
2233                         .ops = &clk_branch2_ops,
2234                 },
2235         },
2236 };
2237
2238 static struct clk_branch mdss_hdmi_clk = {
2239         .halt_reg = 0x2338,
2240         .clkr = {
2241                 .enable_reg = 0x2338,
2242                 .enable_mask = BIT(0),
2243                 .hw.init = &(struct clk_init_data){
2244                         .name = "mdss_hdmi_clk",
2245                         .parent_names = (const char *[]){
2246                                 "hdmi_clk_src",
2247                         },
2248                         .num_parents = 1,
2249                         .flags = CLK_SET_RATE_PARENT,
2250                         .ops = &clk_branch2_ops,
2251                 },
2252         },
2253 };
2254
2255 static struct clk_branch mdss_mdp_clk = {
2256         .halt_reg = 0x231c,
2257         .clkr = {
2258                 .enable_reg = 0x231c,
2259                 .enable_mask = BIT(0),
2260                 .hw.init = &(struct clk_init_data){
2261                         .name = "mdss_mdp_clk",
2262                         .parent_names = (const char *[]){
2263                                 "mdp_clk_src",
2264                         },
2265                         .num_parents = 1,
2266                         .flags = CLK_SET_RATE_PARENT,
2267                         .ops = &clk_branch2_ops,
2268                 },
2269         },
2270 };
2271
2272 static struct clk_branch mdss_mdp_lut_clk = {
2273         .halt_reg = 0x2320,
2274         .clkr = {
2275                 .enable_reg = 0x2320,
2276                 .enable_mask = BIT(0),
2277                 .hw.init = &(struct clk_init_data){
2278                         .name = "mdss_mdp_lut_clk",
2279                         .parent_names = (const char *[]){
2280                                 "mdp_clk_src",
2281                         },
2282                         .num_parents = 1,
2283                         .flags = CLK_SET_RATE_PARENT,
2284                         .ops = &clk_branch2_ops,
2285                 },
2286         },
2287 };
2288
2289 static struct clk_branch mdss_pclk0_clk = {
2290         .halt_reg = 0x2314,
2291         .clkr = {
2292                 .enable_reg = 0x2314,
2293                 .enable_mask = BIT(0),
2294                 .hw.init = &(struct clk_init_data){
2295                         .name = "mdss_pclk0_clk",
2296                         .parent_names = (const char *[]){
2297                                 "pclk0_clk_src",
2298                         },
2299                         .num_parents = 1,
2300                         .flags = CLK_SET_RATE_PARENT,
2301                         .ops = &clk_branch2_ops,
2302                 },
2303         },
2304 };
2305
2306 static struct clk_branch mdss_pclk1_clk = {
2307         .halt_reg = 0x2318,
2308         .clkr = {
2309                 .enable_reg = 0x2318,
2310                 .enable_mask = BIT(0),
2311                 .hw.init = &(struct clk_init_data){
2312                         .name = "mdss_pclk1_clk",
2313                         .parent_names = (const char *[]){
2314                                 "pclk1_clk_src",
2315                         },
2316                         .num_parents = 1,
2317                         .flags = CLK_SET_RATE_PARENT,
2318                         .ops = &clk_branch2_ops,
2319                 },
2320         },
2321 };
2322
2323 static struct clk_branch mdss_vsync_clk = {
2324         .halt_reg = 0x2328,
2325         .clkr = {
2326                 .enable_reg = 0x2328,
2327                 .enable_mask = BIT(0),
2328                 .hw.init = &(struct clk_init_data){
2329                         .name = "mdss_vsync_clk",
2330                         .parent_names = (const char *[]){
2331                                 "vsync_clk_src",
2332                         },
2333                         .num_parents = 1,
2334                         .flags = CLK_SET_RATE_PARENT,
2335                         .ops = &clk_branch2_ops,
2336                 },
2337         },
2338 };
2339
2340 static struct clk_branch mmss_rbcpr_ahb_clk = {
2341         .halt_reg = 0x4088,
2342         .clkr = {
2343                 .enable_reg = 0x4088,
2344                 .enable_mask = BIT(0),
2345                 .hw.init = &(struct clk_init_data){
2346                         .name = "mmss_rbcpr_ahb_clk",
2347                         .parent_names = (const char *[]){
2348                                 "mmss_ahb_clk_src",
2349                         },
2350                         .num_parents = 1,
2351                         .flags = CLK_SET_RATE_PARENT,
2352                         .ops = &clk_branch2_ops,
2353                 },
2354         },
2355 };
2356
2357 static struct clk_branch mmss_rbcpr_clk = {
2358         .halt_reg = 0x4084,
2359         .clkr = {
2360                 .enable_reg = 0x4084,
2361                 .enable_mask = BIT(0),
2362                 .hw.init = &(struct clk_init_data){
2363                         .name = "mmss_rbcpr_clk",
2364                         .parent_names = (const char *[]){
2365                                 "rbcpr_clk_src",
2366                         },
2367                         .num_parents = 1,
2368                         .flags = CLK_SET_RATE_PARENT,
2369                         .ops = &clk_branch2_ops,
2370                 },
2371         },
2372 };
2373
2374 static struct clk_branch mmss_spdm_ahb_clk = {
2375         .halt_reg = 0x0230,
2376         .clkr = {
2377                 .enable_reg = 0x0230,
2378                 .enable_mask = BIT(0),
2379                 .hw.init = &(struct clk_init_data){
2380                         .name = "mmss_spdm_ahb_clk",
2381                         .parent_names = (const char *[]){
2382                                 "mmss_spdm_ahb_div_clk",
2383                         },
2384                         .num_parents = 1,
2385                         .flags = CLK_SET_RATE_PARENT,
2386                         .ops = &clk_branch2_ops,
2387                 },
2388         },
2389 };
2390
2391 static struct clk_branch mmss_spdm_axi_clk = {
2392         .halt_reg = 0x0210,
2393         .clkr = {
2394                 .enable_reg = 0x0210,
2395                 .enable_mask = BIT(0),
2396                 .hw.init = &(struct clk_init_data){
2397                         .name = "mmss_spdm_axi_clk",
2398                         .parent_names = (const char *[]){
2399                                 "mmss_spdm_axi_div_clk",
2400                         },
2401                         .num_parents = 1,
2402                         .flags = CLK_SET_RATE_PARENT,
2403                         .ops = &clk_branch2_ops,
2404                 },
2405         },
2406 };
2407
2408 static struct clk_branch mmss_spdm_csi0_clk = {
2409         .halt_reg = 0x023c,
2410         .clkr = {
2411                 .enable_reg = 0x023c,
2412                 .enable_mask = BIT(0),
2413                 .hw.init = &(struct clk_init_data){
2414                         .name = "mmss_spdm_csi0_clk",
2415                         .parent_names = (const char *[]){
2416                                 "mmss_spdm_csi0_div_clk",
2417                         },
2418                         .num_parents = 1,
2419                         .flags = CLK_SET_RATE_PARENT,
2420                         .ops = &clk_branch2_ops,
2421                 },
2422         },
2423 };
2424
2425 static struct clk_branch mmss_spdm_gfx3d_clk = {
2426         .halt_reg = 0x022c,
2427         .clkr = {
2428                 .enable_reg = 0x022c,
2429                 .enable_mask = BIT(0),
2430                 .hw.init = &(struct clk_init_data){
2431                         .name = "mmss_spdm_gfx3d_clk",
2432                         .parent_names = (const char *[]){
2433                                 "mmss_spdm_gfx3d_div_clk",
2434                         },
2435                         .num_parents = 1,
2436                         .flags = CLK_SET_RATE_PARENT,
2437                         .ops = &clk_branch2_ops,
2438                 },
2439         },
2440 };
2441
2442 static struct clk_branch mmss_spdm_jpeg0_clk = {
2443         .halt_reg = 0x0204,
2444         .clkr = {
2445                 .enable_reg = 0x0204,
2446                 .enable_mask = BIT(0),
2447                 .hw.init = &(struct clk_init_data){
2448                         .name = "mmss_spdm_jpeg0_clk",
2449                         .parent_names = (const char *[]){
2450                                 "mmss_spdm_jpeg0_div_clk",
2451                         },
2452                         .num_parents = 1,
2453                         .flags = CLK_SET_RATE_PARENT,
2454                         .ops = &clk_branch2_ops,
2455                 },
2456         },
2457 };
2458
2459 static struct clk_branch mmss_spdm_jpeg1_clk = {
2460         .halt_reg = 0x0208,
2461         .clkr = {
2462                 .enable_reg = 0x0208,
2463                 .enable_mask = BIT(0),
2464                 .hw.init = &(struct clk_init_data){
2465                         .name = "mmss_spdm_jpeg1_clk",
2466                         .parent_names = (const char *[]){
2467                                 "mmss_spdm_jpeg1_div_clk",
2468                         },
2469                         .num_parents = 1,
2470                         .flags = CLK_SET_RATE_PARENT,
2471                         .ops = &clk_branch2_ops,
2472                 },
2473         },
2474 };
2475
2476 static struct clk_branch mmss_spdm_jpeg2_clk = {
2477         .halt_reg = 0x0224,
2478         .clkr = {
2479                 .enable_reg = 0x0224,
2480                 .enable_mask = BIT(0),
2481                 .hw.init = &(struct clk_init_data){
2482                         .name = "mmss_spdm_jpeg2_clk",
2483                         .parent_names = (const char *[]){
2484                                 "mmss_spdm_jpeg2_div_clk",
2485                         },
2486                         .num_parents = 1,
2487                         .flags = CLK_SET_RATE_PARENT,
2488                         .ops = &clk_branch2_ops,
2489                 },
2490         },
2491 };
2492
2493 static struct clk_branch mmss_spdm_mdp_clk = {
2494         .halt_reg = 0x020c,
2495         .clkr = {
2496                 .enable_reg = 0x020c,
2497                 .enable_mask = BIT(0),
2498                 .hw.init = &(struct clk_init_data){
2499                         .name = "mmss_spdm_mdp_clk",
2500                         .parent_names = (const char *[]){
2501                                 "mmss_spdm_mdp_div_clk",
2502                         },
2503                         .num_parents = 1,
2504                         .flags = CLK_SET_RATE_PARENT,
2505                         .ops = &clk_branch2_ops,
2506                 },
2507         },
2508 };
2509
2510 static struct clk_branch mmss_spdm_pclk0_clk = {
2511         .halt_reg = 0x0234,
2512         .clkr = {
2513                 .enable_reg = 0x0234,
2514                 .enable_mask = BIT(0),
2515                 .hw.init = &(struct clk_init_data){
2516                         .name = "mmss_spdm_pclk0_clk",
2517                         .parent_names = (const char *[]){
2518                                 "mmss_spdm_pclk0_div_clk",
2519                         },
2520                         .num_parents = 1,
2521                         .flags = CLK_SET_RATE_PARENT,
2522                         .ops = &clk_branch2_ops,
2523                 },
2524         },
2525 };
2526
2527 static struct clk_branch mmss_spdm_pclk1_clk = {
2528         .halt_reg = 0x0228,
2529         .clkr = {
2530                 .enable_reg = 0x0228,
2531                 .enable_mask = BIT(0),
2532                 .hw.init = &(struct clk_init_data){
2533                         .name = "mmss_spdm_pclk1_clk",
2534                         .parent_names = (const char *[]){
2535                                 "mmss_spdm_pclk1_div_clk",
2536                         },
2537                         .num_parents = 1,
2538                         .flags = CLK_SET_RATE_PARENT,
2539                         .ops = &clk_branch2_ops,
2540                 },
2541         },
2542 };
2543
2544 static struct clk_branch mmss_spdm_vcodec0_clk = {
2545         .halt_reg = 0x0214,
2546         .clkr = {
2547                 .enable_reg = 0x0214,
2548                 .enable_mask = BIT(0),
2549                 .hw.init = &(struct clk_init_data){
2550                         .name = "mmss_spdm_vcodec0_clk",
2551                         .parent_names = (const char *[]){
2552                                 "mmss_spdm_vcodec0_div_clk",
2553                         },
2554                         .num_parents = 1,
2555                         .flags = CLK_SET_RATE_PARENT,
2556                         .ops = &clk_branch2_ops,
2557                 },
2558         },
2559 };
2560
2561 static struct clk_branch mmss_spdm_vfe0_clk = {
2562         .halt_reg = 0x0218,
2563         .clkr = {
2564                 .enable_reg = 0x0218,
2565                 .enable_mask = BIT(0),
2566                 .hw.init = &(struct clk_init_data){
2567                         .name = "mmss_spdm_vfe0_clk",
2568                         .parent_names = (const char *[]){
2569                                 "mmss_spdm_vfe0_div_clk",
2570                         },
2571                         .num_parents = 1,
2572                         .flags = CLK_SET_RATE_PARENT,
2573                         .ops = &clk_branch2_ops,
2574                 },
2575         },
2576 };
2577
2578 static struct clk_branch mmss_spdm_vfe1_clk = {
2579         .halt_reg = 0x021c,
2580         .clkr = {
2581                 .enable_reg = 0x021c,
2582                 .enable_mask = BIT(0),
2583                 .hw.init = &(struct clk_init_data){
2584                         .name = "mmss_spdm_vfe1_clk",
2585                         .parent_names = (const char *[]){
2586                                 "mmss_spdm_vfe1_div_clk",
2587                         },
2588                         .num_parents = 1,
2589                         .flags = CLK_SET_RATE_PARENT,
2590                         .ops = &clk_branch2_ops,
2591                 },
2592         },
2593 };
2594
2595 static struct clk_branch mmss_spdm_rm_axi_clk = {
2596         .halt_reg = 0x0304,
2597         .clkr = {
2598                 .enable_reg = 0x0304,
2599                 .enable_mask = BIT(0),
2600                 .hw.init = &(struct clk_init_data){
2601                         .name = "mmss_spdm_rm_axi_clk",
2602                         .parent_names = (const char *[]){
2603                                 "mmss_axi_clk_src",
2604                         },
2605                         .num_parents = 1,
2606                         .flags = CLK_SET_RATE_PARENT,
2607                         .ops = &clk_branch2_ops,
2608                 },
2609         },
2610 };
2611
2612 static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
2613         .halt_reg = 0x0308,
2614         .clkr = {
2615                 .enable_reg = 0x0308,
2616                 .enable_mask = BIT(0),
2617                 .hw.init = &(struct clk_init_data){
2618                         .name = "mmss_spdm_rm_ocmemnoc_clk",
2619                         .parent_names = (const char *[]){
2620                                 "ocmemnoc_clk_src",
2621                         },
2622                         .num_parents = 1,
2623                         .flags = CLK_SET_RATE_PARENT,
2624                         .ops = &clk_branch2_ops,
2625                 },
2626         },
2627 };
2628
2629
2630 static struct clk_branch mmss_misc_ahb_clk = {
2631         .halt_reg = 0x502c,
2632         .clkr = {
2633                 .enable_reg = 0x502c,
2634                 .enable_mask = BIT(0),
2635                 .hw.init = &(struct clk_init_data){
2636                         .name = "mmss_misc_ahb_clk",
2637                         .parent_names = (const char *[]){
2638                                 "mmss_ahb_clk_src",
2639                         },
2640                         .num_parents = 1,
2641                         .flags = CLK_SET_RATE_PARENT,
2642                         .ops = &clk_branch2_ops,
2643                 },
2644         },
2645 };
2646
2647 static struct clk_branch mmss_mmssnoc_ahb_clk = {
2648         .halt_reg = 0x5024,
2649         .clkr = {
2650                 .enable_reg = 0x5024,
2651                 .enable_mask = BIT(0),
2652                 .hw.init = &(struct clk_init_data){
2653                         .name = "mmss_mmssnoc_ahb_clk",
2654                         .parent_names = (const char *[]){
2655                                 "mmss_ahb_clk_src",
2656                         },
2657                         .num_parents = 1,
2658                         .ops = &clk_branch2_ops,
2659                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2660                 },
2661         },
2662 };
2663
2664 static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2665         .halt_reg = 0x5028,
2666         .clkr = {
2667                 .enable_reg = 0x5028,
2668                 .enable_mask = BIT(0),
2669                 .hw.init = &(struct clk_init_data){
2670                         .name = "mmss_mmssnoc_bto_ahb_clk",
2671                         .parent_names = (const char *[]){
2672                                 "mmss_ahb_clk_src",
2673                         },
2674                         .num_parents = 1,
2675                         .ops = &clk_branch2_ops,
2676                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2677                 },
2678         },
2679 };
2680
2681 static struct clk_branch mmss_mmssnoc_axi_clk = {
2682         .halt_reg = 0x506c,
2683         .clkr = {
2684                 .enable_reg = 0x506c,
2685                 .enable_mask = BIT(0),
2686                 .hw.init = &(struct clk_init_data){
2687                         .name = "mmss_mmssnoc_axi_clk",
2688                         .parent_names = (const char *[]){
2689                                 "mmss_axi_clk_src",
2690                         },
2691                         .num_parents = 1,
2692                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2693                         .ops = &clk_branch2_ops,
2694                 },
2695         },
2696 };
2697
2698 static struct clk_branch mmss_s0_axi_clk = {
2699         .halt_reg = 0x5064,
2700         .clkr = {
2701                 .enable_reg = 0x5064,
2702                 .enable_mask = BIT(0),
2703                 .hw.init = &(struct clk_init_data){
2704                         .name = "mmss_s0_axi_clk",
2705                         .parent_names = (const char *[]){
2706                                 "mmss_axi_clk_src",
2707                         },
2708                         .num_parents = 1,
2709                         .ops = &clk_branch2_ops,
2710                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2711                 },
2712         },
2713 };
2714
2715 static struct clk_branch ocmemcx_ahb_clk = {
2716         .halt_reg = 0x405c,
2717         .clkr = {
2718                 .enable_reg = 0x405c,
2719                 .enable_mask = BIT(0),
2720                 .hw.init = &(struct clk_init_data){
2721                         .name = "ocmemcx_ahb_clk",
2722                         .parent_names = (const char *[]){
2723                                 "mmss_ahb_clk_src",
2724                         },
2725                         .num_parents = 1,
2726                         .flags = CLK_SET_RATE_PARENT,
2727                         .ops = &clk_branch2_ops,
2728                 },
2729         },
2730 };
2731
2732 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2733         .halt_reg = 0x4058,
2734         .clkr = {
2735                 .enable_reg = 0x4058,
2736                 .enable_mask = BIT(0),
2737                 .hw.init = &(struct clk_init_data){
2738                         .name = "ocmemcx_ocmemnoc_clk",
2739                         .parent_names = (const char *[]){
2740                                 "ocmemnoc_clk_src",
2741                         },
2742                         .num_parents = 1,
2743                         .flags = CLK_SET_RATE_PARENT,
2744                         .ops = &clk_branch2_ops,
2745                 },
2746         },
2747 };
2748
2749 static struct clk_branch oxili_ocmemgx_clk = {
2750         .halt_reg = 0x402c,
2751         .clkr = {
2752                 .enable_reg = 0x402c,
2753                 .enable_mask = BIT(0),
2754                 .hw.init = &(struct clk_init_data){
2755                         .name = "oxili_ocmemgx_clk",
2756                         .parent_names = (const char *[]){
2757                                 "gfx3d_clk_src",
2758                         },
2759                         .num_parents = 1,
2760                         .flags = CLK_SET_RATE_PARENT,
2761                         .ops = &clk_branch2_ops,
2762                 },
2763         },
2764 };
2765
2766 static struct clk_branch oxili_gfx3d_clk = {
2767         .halt_reg = 0x4028,
2768         .clkr = {
2769                 .enable_reg = 0x4028,
2770                 .enable_mask = BIT(0),
2771                 .hw.init = &(struct clk_init_data){
2772                         .name = "oxili_gfx3d_clk",
2773                         .parent_names = (const char *[]){
2774                                 "gfx3d_clk_src",
2775                         },
2776                         .num_parents = 1,
2777                         .flags = CLK_SET_RATE_PARENT,
2778                         .ops = &clk_branch2_ops,
2779                 },
2780         },
2781 };
2782
2783 static struct clk_branch oxili_rbbmtimer_clk = {
2784         .halt_reg = 0x40b0,
2785         .clkr = {
2786                 .enable_reg = 0x40b0,
2787                 .enable_mask = BIT(0),
2788                 .hw.init = &(struct clk_init_data){
2789                         .name = "oxili_rbbmtimer_clk",
2790                         .parent_names = (const char *[]){
2791                                 "rbbmtimer_clk_src",
2792                         },
2793                         .num_parents = 1,
2794                         .flags = CLK_SET_RATE_PARENT,
2795                         .ops = &clk_branch2_ops,
2796                 },
2797         },
2798 };
2799
2800 static struct clk_branch oxilicx_ahb_clk = {
2801         .halt_reg = 0x403c,
2802         .clkr = {
2803                 .enable_reg = 0x403c,
2804                 .enable_mask = BIT(0),
2805                 .hw.init = &(struct clk_init_data){
2806                         .name = "oxilicx_ahb_clk",
2807                         .parent_names = (const char *[]){
2808                                 "mmss_ahb_clk_src",
2809                         },
2810                         .num_parents = 1,
2811                         .flags = CLK_SET_RATE_PARENT,
2812                         .ops = &clk_branch2_ops,
2813                 },
2814         },
2815 };
2816
2817 static struct clk_branch venus0_ahb_clk = {
2818         .halt_reg = 0x1030,
2819         .clkr = {
2820                 .enable_reg = 0x1030,
2821                 .enable_mask = BIT(0),
2822                 .hw.init = &(struct clk_init_data){
2823                         .name = "venus0_ahb_clk",
2824                         .parent_names = (const char *[]){
2825                                 "mmss_ahb_clk_src",
2826                         },
2827                         .num_parents = 1,
2828                         .flags = CLK_SET_RATE_PARENT,
2829                         .ops = &clk_branch2_ops,
2830                 },
2831         },
2832 };
2833
2834 static struct clk_branch venus0_axi_clk = {
2835         .halt_reg = 0x1034,
2836         .clkr = {
2837                 .enable_reg = 0x1034,
2838                 .enable_mask = BIT(0),
2839                 .hw.init = &(struct clk_init_data){
2840                         .name = "venus0_axi_clk",
2841                         .parent_names = (const char *[]){
2842                                 "mmss_axi_clk_src",
2843                         },
2844                         .num_parents = 1,
2845                         .flags = CLK_SET_RATE_PARENT,
2846                         .ops = &clk_branch2_ops,
2847                 },
2848         },
2849 };
2850
2851 static struct clk_branch venus0_core0_vcodec_clk = {
2852         .halt_reg = 0x1048,
2853         .clkr = {
2854                 .enable_reg = 0x1048,
2855                 .enable_mask = BIT(0),
2856                 .hw.init = &(struct clk_init_data){
2857                         .name = "venus0_core0_vcodec_clk",
2858                         .parent_names = (const char *[]){
2859                                 "vcodec0_clk_src",
2860                         },
2861                         .num_parents = 1,
2862                         .flags = CLK_SET_RATE_PARENT,
2863                         .ops = &clk_branch2_ops,
2864                 },
2865         },
2866 };
2867
2868 static struct clk_branch venus0_core1_vcodec_clk = {
2869         .halt_reg = 0x104c,
2870         .clkr = {
2871                 .enable_reg = 0x104c,
2872                 .enable_mask = BIT(0),
2873                 .hw.init = &(struct clk_init_data){
2874                         .name = "venus0_core1_vcodec_clk",
2875                         .parent_names = (const char *[]){
2876                                 "vcodec0_clk_src",
2877                         },
2878                         .num_parents = 1,
2879                         .flags = CLK_SET_RATE_PARENT,
2880                         .ops = &clk_branch2_ops,
2881                 },
2882         },
2883 };
2884
2885 static struct clk_branch venus0_ocmemnoc_clk = {
2886         .halt_reg = 0x1038,
2887         .clkr = {
2888                 .enable_reg = 0x1038,
2889                 .enable_mask = BIT(0),
2890                 .hw.init = &(struct clk_init_data){
2891                         .name = "venus0_ocmemnoc_clk",
2892                         .parent_names = (const char *[]){
2893                                 "ocmemnoc_clk_src",
2894                         },
2895                         .num_parents = 1,
2896                         .flags = CLK_SET_RATE_PARENT,
2897                         .ops = &clk_branch2_ops,
2898                 },
2899         },
2900 };
2901
2902 static struct clk_branch venus0_vcodec0_clk = {
2903         .halt_reg = 0x1028,
2904         .clkr = {
2905                 .enable_reg = 0x1028,
2906                 .enable_mask = BIT(0),
2907                 .hw.init = &(struct clk_init_data){
2908                         .name = "venus0_vcodec0_clk",
2909                         .parent_names = (const char *[]){
2910                                 "vcodec0_clk_src",
2911                         },
2912                         .num_parents = 1,
2913                         .flags = CLK_SET_RATE_PARENT,
2914                         .ops = &clk_branch2_ops,
2915                 },
2916         },
2917 };
2918
2919 static struct clk_branch vpu_ahb_clk = {
2920         .halt_reg = 0x1430,
2921         .clkr = {
2922                 .enable_reg = 0x1430,
2923                 .enable_mask = BIT(0),
2924                 .hw.init = &(struct clk_init_data){
2925                         .name = "vpu_ahb_clk",
2926                         .parent_names = (const char *[]){
2927                                 "mmss_ahb_clk_src",
2928                         },
2929                         .num_parents = 1,
2930                         .flags = CLK_SET_RATE_PARENT,
2931                         .ops = &clk_branch2_ops,
2932                 },
2933         },
2934 };
2935
2936 static struct clk_branch vpu_axi_clk = {
2937         .halt_reg = 0x143c,
2938         .clkr = {
2939                 .enable_reg = 0x143c,
2940                 .enable_mask = BIT(0),
2941                 .hw.init = &(struct clk_init_data){
2942                         .name = "vpu_axi_clk",
2943                         .parent_names = (const char *[]){
2944                                 "mmss_axi_clk_src",
2945                         },
2946                         .num_parents = 1,
2947                         .flags = CLK_SET_RATE_PARENT,
2948                         .ops = &clk_branch2_ops,
2949                 },
2950         },
2951 };
2952
2953 static struct clk_branch vpu_bus_clk = {
2954         .halt_reg = 0x1440,
2955         .clkr = {
2956                 .enable_reg = 0x1440,
2957                 .enable_mask = BIT(0),
2958                 .hw.init = &(struct clk_init_data){
2959                         .name = "vpu_bus_clk",
2960                         .parent_names = (const char *[]){
2961                                 "vpu_bus_clk_src",
2962                         },
2963                         .num_parents = 1,
2964                         .flags = CLK_SET_RATE_PARENT,
2965                         .ops = &clk_branch2_ops,
2966                 },
2967         },
2968 };
2969
2970 static struct clk_branch vpu_cxo_clk = {
2971         .halt_reg = 0x1434,
2972         .clkr = {
2973                 .enable_reg = 0x1434,
2974                 .enable_mask = BIT(0),
2975                 .hw.init = &(struct clk_init_data){
2976                         .name = "vpu_cxo_clk",
2977                         .parent_names = (const char *[]){ "xo" },
2978                         .num_parents = 1,
2979                         .flags = CLK_SET_RATE_PARENT,
2980                         .ops = &clk_branch2_ops,
2981                 },
2982         },
2983 };
2984
2985 static struct clk_branch vpu_maple_clk = {
2986         .halt_reg = 0x142c,
2987         .clkr = {
2988                 .enable_reg = 0x142c,
2989                 .enable_mask = BIT(0),
2990                 .hw.init = &(struct clk_init_data){
2991                         .name = "vpu_maple_clk",
2992                         .parent_names = (const char *[]){
2993                                 "maple_clk_src",
2994                         },
2995                         .num_parents = 1,
2996                         .flags = CLK_SET_RATE_PARENT,
2997                         .ops = &clk_branch2_ops,
2998                 },
2999         },
3000 };
3001
3002 static struct clk_branch vpu_sleep_clk = {
3003         .halt_reg = 0x1438,
3004         .clkr = {
3005                 .enable_reg = 0x1438,
3006                 .enable_mask = BIT(0),
3007                 .hw.init = &(struct clk_init_data){
3008                         .name = "vpu_sleep_clk",
3009                         .parent_names = (const char *[]){
3010                                 "sleep_clk_src",
3011                         },
3012                         .num_parents = 1,
3013                         .flags = CLK_SET_RATE_PARENT,
3014                         .ops = &clk_branch2_ops,
3015                 },
3016         },
3017 };
3018
3019 static struct clk_branch vpu_vdp_clk = {
3020         .halt_reg = 0x1428,
3021         .clkr = {
3022                 .enable_reg = 0x1428,
3023                 .enable_mask = BIT(0),
3024                 .hw.init = &(struct clk_init_data){
3025                         .name = "vpu_vdp_clk",
3026                         .parent_names = (const char *[]){
3027                                 "vdp_clk_src",
3028                         },
3029                         .num_parents = 1,
3030                         .flags = CLK_SET_RATE_PARENT,
3031                         .ops = &clk_branch2_ops,
3032                 },
3033         },
3034 };
3035
3036 static const struct pll_config mmpll1_config = {
3037         .l = 60,
3038         .m = 25,
3039         .n = 32,
3040         .vco_val = 0x0,
3041         .vco_mask = 0x3 << 20,
3042         .pre_div_val = 0x0,
3043         .pre_div_mask = 0x7 << 12,
3044         .post_div_val = 0x0,
3045         .post_div_mask = 0x3 << 8,
3046         .mn_ena_mask = BIT(24),
3047         .main_output_mask = BIT(0),
3048 };
3049
3050 static const struct pll_config mmpll3_config = {
3051         .l = 48,
3052         .m = 7,
3053         .n = 16,
3054         .vco_val = 0x0,
3055         .vco_mask = 0x3 << 20,
3056         .pre_div_val = 0x0,
3057         .pre_div_mask = 0x7 << 12,
3058         .post_div_val = 0x0,
3059         .post_div_mask = 0x3 << 8,
3060         .mn_ena_mask = BIT(24),
3061         .main_output_mask = BIT(0),
3062         .aux_output_mask = BIT(1),
3063 };
3064
3065 static struct gdsc venus0_gdsc = {
3066         .gdscr = 0x1024,
3067         .pd = {
3068                 .name = "venus0",
3069         },
3070         .pwrsts = PWRSTS_OFF_ON,
3071 };
3072
3073 static struct gdsc venus0_core0_gdsc = {
3074         .gdscr = 0x1040,
3075         .pd = {
3076                 .name = "venus0_core0",
3077         },
3078         .pwrsts = PWRSTS_OFF_ON,
3079 };
3080
3081 static struct gdsc venus0_core1_gdsc = {
3082         .gdscr = 0x1044,
3083         .pd = {
3084                 .name = "venus0_core1",
3085         },
3086         .pwrsts = PWRSTS_OFF_ON,
3087 };
3088
3089 static struct gdsc mdss_gdsc = {
3090         .gdscr = 0x2304,
3091         .cxcs = (unsigned int []){ 0x231c, 0x2320 },
3092         .cxc_count = 2,
3093         .pd = {
3094                 .name = "mdss",
3095         },
3096         .pwrsts = PWRSTS_OFF_ON,
3097 };
3098
3099 static struct gdsc camss_jpeg_gdsc = {
3100         .gdscr = 0x35a4,
3101         .pd = {
3102                 .name = "camss_jpeg",
3103         },
3104         .pwrsts = PWRSTS_OFF_ON,
3105 };
3106
3107 static struct gdsc camss_vfe_gdsc = {
3108         .gdscr = 0x36a4,
3109         .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 },
3110         .cxc_count = 3,
3111         .pd = {
3112                 .name = "camss_vfe",
3113         },
3114         .pwrsts = PWRSTS_OFF_ON,
3115 };
3116
3117 static struct gdsc oxili_gdsc = {
3118         .gdscr = 0x4024,
3119         .cxcs = (unsigned int []){ 0x4028 },
3120         .cxc_count = 1,
3121         .pd = {
3122                 .name = "oxili",
3123         },
3124         .pwrsts = PWRSTS_OFF_ON,
3125 };
3126
3127 static struct gdsc oxilicx_gdsc = {
3128         .gdscr = 0x4034,
3129         .pd = {
3130                 .name = "oxilicx",
3131         },
3132         .pwrsts = PWRSTS_OFF_ON,
3133 };
3134
3135 static struct clk_regmap *mmcc_apq8084_clocks[] = {
3136         [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
3137         [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
3138         [MMPLL0] = &mmpll0.clkr,
3139         [MMPLL0_VOTE] = &mmpll0_vote,
3140         [MMPLL1] = &mmpll1.clkr,
3141         [MMPLL1_VOTE] = &mmpll1_vote,
3142         [MMPLL2] = &mmpll2.clkr,
3143         [MMPLL3] = &mmpll3.clkr,
3144         [MMPLL4] = &mmpll4.clkr,
3145         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3146         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3147         [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3148         [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
3149         [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3150         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3151         [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3152         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3153         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3154         [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3155         [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
3156         [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3157         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3158         [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
3159         [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
3160         [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
3161         [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
3162         [VP_CLK_SRC] = &vp_clk_src.clkr,
3163         [CCI_CLK_SRC] = &cci_clk_src.clkr,
3164         [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3165         [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3166         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3167         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3168         [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3169         [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
3170         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3171         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3172         [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
3173         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3174         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3175         [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3176         [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
3177         [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
3178         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3179         [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3180         [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
3181         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3182         [MMSS_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
3183         [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
3184         [MAPLE_CLK_SRC] = &maple_clk_src.clkr,
3185         [VDP_CLK_SRC] = &vdp_clk_src.clkr,
3186         [VPU_BUS_CLK_SRC] = &vpu_bus_clk_src.clkr,
3187         [MMSS_CXO_CLK] = &mmss_cxo_clk.clkr,
3188         [MMSS_SLEEPCLK_CLK] = &mmss_sleepclk_clk.clkr,
3189         [AVSYNC_AHB_CLK] = &avsync_ahb_clk.clkr,
3190         [AVSYNC_EDPPIXEL_CLK] = &avsync_edppixel_clk.clkr,
3191         [AVSYNC_EXTPCLK_CLK] = &avsync_extpclk_clk.clkr,
3192         [AVSYNC_PCLK0_CLK] = &avsync_pclk0_clk.clkr,
3193         [AVSYNC_PCLK1_CLK] = &avsync_pclk1_clk.clkr,
3194         [AVSYNC_VP_CLK] = &avsync_vp_clk.clkr,
3195         [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3196         [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
3197         [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
3198         [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3199         [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3200         [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3201         [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3202         [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3203         [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3204         [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3205         [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3206         [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3207         [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3208         [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3209         [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3210         [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3211         [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3212         [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3213         [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3214         [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3215         [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3216         [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3217         [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3218         [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3219         [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3220         [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3221         [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3222         [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3223         [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
3224         [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
3225         [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
3226         [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
3227         [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
3228         [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3229         [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3230         [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3231         [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3232         [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3233         [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
3234         [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
3235         [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
3236         [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3237         [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
3238         [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
3239         [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
3240         [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
3241         [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
3242         [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
3243         [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3244         [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3245         [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3246         [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3247         [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
3248         [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
3249         [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
3250         [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3251         [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3252         [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3253         [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3254         [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3255         [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3256         [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
3257         [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3258         [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3259         [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3260         [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3261         [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3262         [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
3263         [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
3264         [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
3265         [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
3266         [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
3267         [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
3268         [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
3269         [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
3270         [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
3271         [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
3272         [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
3273         [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
3274         [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
3275         [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
3276         [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
3277         [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
3278         [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
3279         [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
3280         [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
3281         [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
3282         [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
3283         [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
3284         [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
3285         [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
3286         [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
3287         [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
3288         [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
3289         [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
3290         [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
3291         [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
3292         [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
3293         [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
3294         [VPU_AHB_CLK] = &vpu_ahb_clk.clkr,
3295         [VPU_AXI_CLK] = &vpu_axi_clk.clkr,
3296         [VPU_BUS_CLK] = &vpu_bus_clk.clkr,
3297         [VPU_CXO_CLK] = &vpu_cxo_clk.clkr,
3298         [VPU_MAPLE_CLK] = &vpu_maple_clk.clkr,
3299         [VPU_SLEEP_CLK] = &vpu_sleep_clk.clkr,
3300         [VPU_VDP_CLK] = &vpu_vdp_clk.clkr,
3301 };
3302
3303 static const struct qcom_reset_map mmcc_apq8084_resets[] = {
3304         [MMSS_SPDM_RESET] = { 0x0200 },
3305         [MMSS_SPDM_RM_RESET] = { 0x0300 },
3306         [VENUS0_RESET] = { 0x1020 },
3307         [VPU_RESET] = { 0x1400 },
3308         [MDSS_RESET] = { 0x2300 },
3309         [AVSYNC_RESET] = { 0x2400 },
3310         [CAMSS_PHY0_RESET] = { 0x3020 },
3311         [CAMSS_PHY1_RESET] = { 0x3050 },
3312         [CAMSS_PHY2_RESET] = { 0x3080 },
3313         [CAMSS_CSI0_RESET] = { 0x30b0 },
3314         [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
3315         [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
3316         [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
3317         [CAMSS_CSI1_RESET] = { 0x3120 },
3318         [CAMSS_CSI1PHY_RESET] = { 0x3130 },
3319         [CAMSS_CSI1RDI_RESET] = { 0x3140 },
3320         [CAMSS_CSI1PIX_RESET] = { 0x3150 },
3321         [CAMSS_CSI2_RESET] = { 0x3180 },
3322         [CAMSS_CSI2PHY_RESET] = { 0x3190 },
3323         [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
3324         [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
3325         [CAMSS_CSI3_RESET] = { 0x31e0 },
3326         [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
3327         [CAMSS_CSI3RDI_RESET] = { 0x3200 },
3328         [CAMSS_CSI3PIX_RESET] = { 0x3210 },
3329         [CAMSS_ISPIF_RESET] = { 0x3220 },
3330         [CAMSS_CCI_RESET] = { 0x3340 },
3331         [CAMSS_MCLK0_RESET] = { 0x3380 },
3332         [CAMSS_MCLK1_RESET] = { 0x33b0 },
3333         [CAMSS_MCLK2_RESET] = { 0x33e0 },
3334         [CAMSS_MCLK3_RESET] = { 0x3410 },
3335         [CAMSS_GP0_RESET] = { 0x3440 },
3336         [CAMSS_GP1_RESET] = { 0x3470 },
3337         [CAMSS_TOP_RESET] = { 0x3480 },
3338         [CAMSS_AHB_RESET] = { 0x3488 },
3339         [CAMSS_MICRO_RESET] = { 0x3490 },
3340         [CAMSS_JPEG_RESET] = { 0x35a0 },
3341         [CAMSS_VFE_RESET] = { 0x36a0 },
3342         [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
3343         [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
3344         [OXILI_RESET] = { 0x4020 },
3345         [OXILICX_RESET] = { 0x4030 },
3346         [OCMEMCX_RESET] = { 0x4050 },
3347         [MMSS_RBCRP_RESET] = { 0x4080 },
3348         [MMSSNOCAHB_RESET] = { 0x5020 },
3349         [MMSSNOCAXI_RESET] = { 0x5060 },
3350 };
3351
3352 static struct gdsc *mmcc_apq8084_gdscs[] = {
3353         [VENUS0_GDSC] = &venus0_gdsc,
3354         [VENUS0_CORE0_GDSC] = &venus0_core0_gdsc,
3355         [VENUS0_CORE1_GDSC] = &venus0_core1_gdsc,
3356         [MDSS_GDSC] = &mdss_gdsc,
3357         [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc,
3358         [CAMSS_VFE_GDSC] = &camss_vfe_gdsc,
3359         [OXILI_GDSC] = &oxili_gdsc,
3360         [OXILICX_GDSC] = &oxilicx_gdsc,
3361 };
3362
3363 static const struct regmap_config mmcc_apq8084_regmap_config = {
3364         .reg_bits       = 32,
3365         .reg_stride     = 4,
3366         .val_bits       = 32,
3367         .max_register   = 0x5104,
3368         .fast_io        = true,
3369 };
3370
3371 static const struct qcom_cc_desc mmcc_apq8084_desc = {
3372         .config = &mmcc_apq8084_regmap_config,
3373         .clks = mmcc_apq8084_clocks,
3374         .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
3375         .resets = mmcc_apq8084_resets,
3376         .num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
3377         .gdscs = mmcc_apq8084_gdscs,
3378         .num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs),
3379 };
3380
3381 static const struct of_device_id mmcc_apq8084_match_table[] = {
3382         { .compatible = "qcom,mmcc-apq8084" },
3383         { }
3384 };
3385 MODULE_DEVICE_TABLE(of, mmcc_apq8084_match_table);
3386
3387 static int mmcc_apq8084_probe(struct platform_device *pdev)
3388 {
3389         int ret;
3390         struct regmap *regmap;
3391
3392         ret = qcom_cc_probe(pdev, &mmcc_apq8084_desc);
3393         if (ret)
3394                 return ret;
3395
3396         regmap = dev_get_regmap(&pdev->dev, NULL);
3397         clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
3398         clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
3399
3400         return 0;
3401 }
3402
3403 static struct platform_driver mmcc_apq8084_driver = {
3404         .probe          = mmcc_apq8084_probe,
3405         .driver         = {
3406                 .name   = "mmcc-apq8084",
3407                 .of_match_table = mmcc_apq8084_match_table,
3408         },
3409 };
3410 module_platform_driver(mmcc_apq8084_driver);
3411
3412 MODULE_DESCRIPTION("QCOM MMCC APQ8084 Driver");
3413 MODULE_LICENSE("GPL v2");
3414 MODULE_ALIAS("platform:mmcc-apq8084");