drivers/clk/qcom/gcc-msm8939.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright 2020 Linaro Limited
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
  18 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
  19
  20 #include "common.h"
  21 #include "clk-regmap.h"
  22 #include "clk-pll.h"
  23 #include "clk-rcg.h"
  24 #include "clk-branch.h"
  25 #include "reset.h"
  26 #include "gdsc.h"
  27
  28 enum {
  29         P_XO,
  30         P_GPLL0,
  31         P_GPLL0_AUX,
  32         P_BIMC,
  33         P_GPLL1,
  34         P_GPLL1_AUX,
  35         P_GPLL2,
  36         P_GPLL2_AUX,
  37         P_GPLL3,
  38         P_GPLL3_AUX,
  39         P_GPLL4,
  40         P_GPLL5,
  41         P_GPLL5_AUX,
  42         P_GPLL5_EARLY,
  43         P_GPLL6,
  44         P_GPLL6_AUX,
  45         P_SLEEP_CLK,
  46         P_DSI0_PHYPLL_BYTE,
  47         P_DSI0_PHYPLL_DSI,
  48         P_EXT_PRI_I2S,
  49         P_EXT_SEC_I2S,
  50         P_EXT_MCLK,
  51 };
  52
  53 static struct clk_pll gpll0 = {
  54         .l_reg = 0x21004,
  55         .m_reg = 0x21008,
  56         .n_reg = 0x2100c,
  57         .config_reg = 0x21010,
  58         .mode_reg = 0x21000,
  59         .status_reg = 0x2101c,
  60         .status_bit = 17,
  61         .clkr.hw.init = &(struct clk_init_data){
  62                 .name = "gpll0",
  63                 .parent_data = &(const struct clk_parent_data) {
  64                         .fw_name = "xo",
  65                 },
  66                 .num_parents = 1,
  67                 .ops = &clk_pll_ops,
  68         },
  69 };
  70
  71 static struct clk_regmap gpll0_vote = {
  72         .enable_reg = 0x45000,
  73         .enable_mask = BIT(0),
  74         .hw.init = &(struct clk_init_data){
  75                 .name = "gpll0_vote",
  76                 .parent_data = &(const struct clk_parent_data) {
  77                         .hw = &gpll0.clkr.hw,
  78                 },
  79                 .num_parents = 1,
  80                 .ops = &clk_pll_vote_ops,
  81         },
  82 };
  83
  84 static struct clk_pll gpll1 = {
  85         .l_reg = 0x20004,
  86         .m_reg = 0x20008,
  87         .n_reg = 0x2000c,
  88         .config_reg = 0x20010,
  89         .mode_reg = 0x20000,
  90         .status_reg = 0x2001c,
  91         .status_bit = 17,
  92         .clkr.hw.init = &(struct clk_init_data){
  93                 .name = "gpll1",
  94                 .parent_data = &(const struct clk_parent_data) {
  95                         .fw_name = "xo",
  96                 },
  97                 .num_parents = 1,
  98                 .ops = &clk_pll_ops,
  99         },
 100 };
 101
 102 static struct clk_regmap gpll1_vote = {
 103         .enable_reg = 0x45000,
 104         .enable_mask = BIT(1),
 105         .hw.init = &(struct clk_init_data){
 106                 .name = "gpll1_vote",
 107                 .parent_data = &(const struct clk_parent_data) {
 108                         .hw = &gpll1.clkr.hw,
 109                 },
 110                 .num_parents = 1,
 111                 .ops = &clk_pll_vote_ops,
 112         },
 113 };
 114
 115 static struct clk_pll gpll2 = {
 116         .l_reg = 0x4a004,
 117         .m_reg = 0x4a008,
 118         .n_reg = 0x4a00c,
 119         .config_reg = 0x4a010,
 120         .mode_reg = 0x4a000,
 121         .status_reg = 0x4a01c,
 122         .status_bit = 17,
 123         .clkr.hw.init = &(struct clk_init_data){
 124                 .name = "gpll2",
 125                 .parent_data = &(const struct clk_parent_data) {
 126                         .fw_name = "xo",
 127                 },
 128                 .num_parents = 1,
 129                 .ops = &clk_pll_ops,
 130         },
 131 };
 132
 133 static struct clk_regmap gpll2_vote = {
 134         .enable_reg = 0x45000,
 135         .enable_mask = BIT(2),
 136         .hw.init = &(struct clk_init_data){
 137                 .name = "gpll2_vote",
 138                 .parent_data = &(const struct clk_parent_data) {
 139                         .hw = &gpll2.clkr.hw,
 140                 },
 141                 .num_parents = 1,
 142                 .ops = &clk_pll_vote_ops,
 143         },
 144 };
 145
 146 static struct clk_pll bimc_pll = {
 147         .l_reg = 0x23004,
 148         .m_reg = 0x23008,
 149         .n_reg = 0x2300c,
 150         .config_reg = 0x23010,
 151         .mode_reg = 0x23000,
 152         .status_reg = 0x2301c,
 153         .status_bit = 17,
 154         .clkr.hw.init = &(struct clk_init_data){
 155                 .name = "bimc_pll",
 156                 .parent_data = &(const struct clk_parent_data) {
 157                         .fw_name = "xo",
 158                 },
 159                 .num_parents = 1,
 160                 .ops = &clk_pll_ops,
 161         },
 162 };
 163
 164 static struct clk_regmap bimc_pll_vote = {
 165         .enable_reg = 0x45000,
 166         .enable_mask = BIT(3),
 167         .hw.init = &(struct clk_init_data){
 168                 .name = "bimc_pll_vote",
 169                 .parent_data = &(const struct clk_parent_data) {
 170                         .hw = &bimc_pll.clkr.hw,
 171                 },
 172                 .num_parents = 1,
 173                 .ops = &clk_pll_vote_ops,
 174         },
 175 };
 176
 177 static struct clk_pll gpll3 = {
 178         .l_reg = 0x22004,
 179         .m_reg = 0x22008,
 180         .n_reg = 0x2200c,
 181         .config_reg = 0x22010,
 182         .mode_reg = 0x22000,
 183         .status_reg = 0x2201c,
 184         .status_bit = 17,
 185         .clkr.hw.init = &(struct clk_init_data){
 186                 .name = "gpll3",
 187                 .parent_data = &(const struct clk_parent_data) {
 188                         .fw_name = "xo",
 189                 },
 190                 .num_parents = 1,
 191                 .ops = &clk_pll_ops,
 192         },
 193 };
 194
 195 static struct clk_regmap gpll3_vote = {
 196         .enable_reg = 0x45000,
 197         .enable_mask = BIT(4),
 198         .hw.init = &(struct clk_init_data){
 199                 .name = "gpll3_vote",
 200                 .parent_data = &(const struct clk_parent_data) {
 201                         .hw = &gpll3.clkr.hw,
 202                 },
 203                 .num_parents = 1,
 204                 .ops = &clk_pll_vote_ops,
 205         },
 206 };
 207
 208 /* GPLL3 at 1100 MHz, main output enabled. */
 209 static const struct pll_config gpll3_config = {
 210         .l = 57,
 211         .m = 7,
 212         .n = 24,
 213         .vco_val = 0x0,
 214         .vco_mask = BIT(20),
 215         .pre_div_val = 0x0,
 216         .pre_div_mask = BIT(12),
 217         .post_div_val = 0x0,
 218         .post_div_mask = BIT(9) | BIT(8),
 219         .mn_ena_mask = BIT(24),
 220         .main_output_mask = BIT(0),
 221         .aux_output_mask = BIT(1),
 222 };
 223
 224 static struct clk_pll gpll4 = {
 225         .l_reg = 0x24004,
 226         .m_reg = 0x24008,
 227         .n_reg = 0x2400c,
 228         .config_reg = 0x24010,
 229         .mode_reg = 0x24000,
 230         .status_reg = 0x2401c,
 231         .status_bit = 17,
 232         .clkr.hw.init = &(struct clk_init_data){
 233                 .name = "gpll4",
 234                 .parent_data = &(const struct clk_parent_data) {
 235                         .fw_name = "xo",
 236                 },
 237                 .num_parents = 1,
 238                 .ops = &clk_pll_ops,
 239         },
 240 };
 241
 242 static struct clk_regmap gpll4_vote = {
 243         .enable_reg = 0x45000,
 244         .enable_mask = BIT(5),
 245         .hw.init = &(struct clk_init_data){
 246                 .name = "gpll4_vote",
 247                 .parent_data = &(const struct clk_parent_data) {
 248                         .hw = &gpll4.clkr.hw,
 249                 },
 250                 .num_parents = 1,
 251                 .ops = &clk_pll_vote_ops,
 252         },
 253 };
 254
 255 /* GPLL4 at 1200 MHz, main output enabled. */
 256 static struct pll_config gpll4_config = {
 257         .l = 62,
 258         .m = 1,
 259         .n = 2,
 260         .vco_val = 0x0,
 261         .vco_mask = BIT(20),
 262         .pre_div_val = 0x0,
 263         .pre_div_mask = BIT(12),
 264         .post_div_val = 0x0,
 265         .post_div_mask = BIT(9) | BIT(8),
 266         .mn_ena_mask = BIT(24),
 267         .main_output_mask = BIT(0),
 268 };
 269
 270 static struct clk_pll gpll5 = {
 271         .l_reg = 0x25004,
 272         .m_reg = 0x25008,
 273         .n_reg = 0x2500c,
 274         .config_reg = 0x25010,
 275         .mode_reg = 0x25000,
 276         .status_reg = 0x2501c,
 277         .status_bit = 17,
 278         .clkr.hw.init = &(struct clk_init_data){
 279                 .name = "gpll5",
 280                 .parent_data = &(const struct clk_parent_data) {
 281                         .fw_name = "xo",
 282                 },
 283                 .num_parents = 1,
 284                 .ops = &clk_pll_ops,
 285         },
 286 };
 287
 288 static struct clk_regmap gpll5_vote = {
 289         .enable_reg = 0x45000,
 290         .enable_mask = BIT(6),
 291         .hw.init = &(struct clk_init_data){
 292                 .name = "gpll5_vote",
 293                 .parent_data = &(const struct clk_parent_data) {
 294                         .hw = &gpll5.clkr.hw,
 295                 },
 296                 .num_parents = 1,
 297                 .ops = &clk_pll_vote_ops,
 298         },
 299 };
 300
 301 static struct clk_pll gpll6 = {
 302         .l_reg = 0x37004,
 303         .m_reg = 0x37008,
 304         .n_reg = 0x3700c,
 305         .config_reg = 0x37010,
 306         .mode_reg = 0x37000,
 307         .status_reg = 0x3701c,
 308         .status_bit = 17,
 309         .clkr.hw.init = &(struct clk_init_data){
 310                 .name = "gpll6",
 311                 .parent_data = &(const struct clk_parent_data) {
 312                         .fw_name = "xo",
 313                 },
 314                 .num_parents = 1,
 315                 .ops = &clk_pll_ops,
 316         },
 317 };
 318
 319 static struct clk_regmap gpll6_vote = {
 320         .enable_reg = 0x45000,
 321         .enable_mask = BIT(7),
 322         .hw.init = &(struct clk_init_data){
 323                 .name = "gpll6_vote",
 324                 .parent_data = &(const struct clk_parent_data) {
 325                         .hw = &gpll6.clkr.hw,
 326                 },
 327                 .num_parents = 1,
 328                 .ops = &clk_pll_vote_ops,
 329         },
 330 };
 331
 332 static const struct parent_map gcc_xo_gpll0_map[] = {
 333         { P_XO, 0 },
 334         { P_GPLL0, 1 },
 335 };
 336
 337 static const struct clk_parent_data gcc_xo_gpll0_parent_data[] = {
 338         { .fw_name = "xo" },
 339         { .hw = &gpll0_vote.hw },
 340 };
 341
 342 static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
 343         { P_XO, 0 },
 344         { P_GPLL0, 1 },
 345         { P_BIMC, 2 },
 346 };
 347
 348 static const struct clk_parent_data gcc_xo_gpll0_bimc_parent_data[] = {
 349         { .fw_name = "xo" },
 350         { .hw = &gpll0_vote.hw },
 351         { .hw = &bimc_pll_vote.hw },
 352 };
 353
 354 static const struct parent_map gcc_xo_gpll0_gpll6a_map[] = {
 355         { P_XO, 0 },
 356         { P_GPLL0, 1 },
 357         { P_GPLL6_AUX, 2 },
 358 };
 359
 360 static const struct clk_parent_data gcc_xo_gpll0_gpll6a_parent_data[] = {
 361         { .fw_name = "xo" },
 362         { .hw = &gpll0_vote.hw },
 363         { .hw = &gpll6_vote.hw },
 364 };
 365
 366 static const struct parent_map gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map[] = {
 367         { P_XO, 0 },
 368         { P_GPLL0, 1 },
 369         { P_GPLL2_AUX, 4 },
 370         { P_GPLL3, 2 },
 371         { P_GPLL6_AUX, 3 },
 372 };
 373
 374 static const struct clk_parent_data gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data[] = {
 375         { .fw_name = "xo" },
 376         { .hw = &gpll0_vote.hw },
 377         { .hw = &gpll2_vote.hw },
 378         { .hw = &gpll3_vote.hw },
 379         { .hw = &gpll6_vote.hw },
 380 };
 381
 382 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
 383         { P_XO, 0 },
 384         { P_GPLL0, 1 },
 385         { P_GPLL2, 2 },
 386 };
 387
 388 static const struct clk_parent_data gcc_xo_gpll0_gpll2_parent_data[] = {
 389         { .fw_name = "xo" },
 390         { .hw = &gpll0_vote.hw },
 391         { .hw = &gpll2_vote.hw },
 392 };
 393
 394 static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {
 395         { P_XO, 0 },
 396         { P_GPLL0, 1 },
 397         { P_GPLL2, 3 },
 398         { P_GPLL4, 2 },
 399 };
 400
 401 static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_parent_data[] = {
 402         { .fw_name = "xo" },
 403         { .hw = &gpll0_vote.hw },
 404         { .hw = &gpll2_vote.hw },
 405         { .hw = &gpll4_vote.hw },
 406 };
 407
 408 static const struct parent_map gcc_xo_gpll0a_map[] = {
 409         { P_XO, 0 },
 410         { P_GPLL0_AUX, 2 },
 411 };
 412
 413 static const struct clk_parent_data gcc_xo_gpll0a_parent_data[] = {
 414         { .fw_name = "xo" },
 415         { .hw = &gpll0_vote.hw },
 416 };
 417
 418 static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
 419         { P_XO, 0 },
 420         { P_GPLL0, 1 },
 421         { P_GPLL1_AUX, 2 },
 422         { P_SLEEP_CLK, 6 },
 423 };
 424
 425 static const struct clk_parent_data gcc_xo_gpll0_gpll1a_sleep_parent_data[] = {
 426         { .fw_name = "xo" },
 427         { .hw = &gpll0_vote.hw },
 428         { .hw = &gpll1_vote.hw },
 429         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 430 };
 431
 432 static const struct parent_map gcc_xo_gpll0_gpll1a_gpll6_sleep_map[] = {
 433         { P_XO, 0 },
 434         { P_GPLL0, 1 },
 435         { P_GPLL1_AUX, 2 },
 436         { P_GPLL6, 2 },
 437         { P_SLEEP_CLK, 6 },
 438 };
 439
 440 static const struct clk_parent_data gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data[] = {
 441         { .fw_name = "xo" },
 442         { .hw = &gpll0_vote.hw },
 443         { .hw = &gpll1_vote.hw },
 444         { .hw = &gpll6_vote.hw },
 445         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 446 };
 447
 448 static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
 449         { P_XO, 0 },
 450         { P_GPLL0, 1 },
 451         { P_GPLL1_AUX, 2 },
 452 };
 453
 454 static const struct clk_parent_data gcc_xo_gpll0_gpll1a_parent_data[] = {
 455         { .fw_name = "xo" },
 456         { .hw = &gpll0_vote.hw },
 457         { .hw = &gpll1_vote.hw },
 458 };
 459
 460 static const struct parent_map gcc_xo_dsibyte_map[] = {
 461         { P_XO, 0, },
 462         { P_DSI0_PHYPLL_BYTE, 2 },
 463 };
 464
 465 static const struct clk_parent_data gcc_xo_dsibyte_parent_data[] = {
 466         { .fw_name = "xo" },
 467         { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 468 };
 469
 470 static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
 471         { P_XO, 0 },
 472         { P_GPLL0_AUX, 2 },
 473         { P_DSI0_PHYPLL_BYTE, 1 },
 474 };
 475
 476 static const struct clk_parent_data gcc_xo_gpll0a_dsibyte_parent_data[] = {
 477         { .fw_name = "xo" },
 478         { .hw = &gpll0_vote.hw },
 479         { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
 480 };
 481
 482 static const struct parent_map gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map[] = {
 483         { P_XO, 0 },
 484         { P_GPLL1, 1 },
 485         { P_DSI0_PHYPLL_DSI, 2 },
 486         { P_GPLL6, 3 },
 487         { P_GPLL3_AUX, 4 },
 488         { P_GPLL0_AUX, 5 },
 489 };
 490
 491 static const struct clk_parent_data gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data[] = {
 492         { .fw_name = "xo" },
 493         { .hw = &gpll1_vote.hw },
 494         { .fw_name = "dsi0pll", .name = "dsi0pll" },
 495         { .hw = &gpll6_vote.hw },
 496         { .hw = &gpll3_vote.hw },
 497         { .hw = &gpll0_vote.hw },
 498 };
 499
 500 static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
 501         { P_XO, 0 },
 502         { P_GPLL0_AUX, 2 },
 503         { P_DSI0_PHYPLL_DSI, 1 },
 504 };
 505
 506 static const struct clk_parent_data gcc_xo_gpll0a_dsiphy_parent_data[] = {
 507         { .fw_name = "xo" },
 508         { .hw = &gpll0_vote.hw },
 509         { .fw_name = "dsi0pll", .name = "dsi0pll" },
 510 };
 511
 512 static const struct parent_map gcc_xo_gpll0_gpll5a_gpll6_bimc_map[] = {
 513         { P_XO, 0 },
 514         { P_GPLL0, 1 },
 515         { P_GPLL5_AUX, 3 },
 516         { P_GPLL6, 2 },
 517         { P_BIMC, 4 },
 518 };
 519
 520 static const struct clk_parent_data gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data[] = {
 521         { .fw_name = "xo" },
 522         { .hw = &gpll0_vote.hw },
 523         { .hw = &gpll5_vote.hw },
 524         { .hw = &gpll6_vote.hw },
 525         { .hw = &bimc_pll_vote.hw },
 526 };
 527
 528 static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
 529         { P_XO, 0 },
 530         { P_GPLL0, 1 },
 531         { P_GPLL1, 2 },
 532         { P_SLEEP_CLK, 6 }
 533 };
 534
 535 static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep_parent_data[] = {
 536         { .fw_name = "xo" },
 537         { .hw = &gpll0_vote.hw },
 538         { .hw = &gpll1_vote.hw },
 539         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 540 };
 541
 542 static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
 543         { P_XO, 0 },
 544         { P_GPLL1, 1 },
 545         { P_EXT_PRI_I2S, 2 },
 546         { P_EXT_MCLK, 3 },
 547         { P_SLEEP_CLK, 6 }
 548 };
 549
 550 static const struct clk_parent_data gcc_xo_gpll1_epi2s_emclk_sleep_parent_data[] = {
 551         { .fw_name = "xo" },
 552         { .hw = &gpll0_vote.hw },
 553         { .fw_name = "ext_pri_i2s", .name = "ext_pri_i2s" },
 554         { .fw_name = "ext_mclk", .name = "ext_mclk" },
 555         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 556 };
 557
 558 static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
 559         { P_XO, 0 },
 560         { P_GPLL1, 1 },
 561         { P_EXT_SEC_I2S, 2 },
 562         { P_EXT_MCLK, 3 },
 563         { P_SLEEP_CLK, 6 }
 564 };
 565
 566 static const struct clk_parent_data gcc_xo_gpll1_esi2s_emclk_sleep_parent_data[] = {
 567         { .fw_name = "xo" },
 568         { .hw = &gpll1_vote.hw },
 569         { .fw_name = "ext_sec_i2s", .name = "ext_sec_i2s" },
 570         { .fw_name = "ext_mclk", .name = "ext_mclk" },
 571         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 572 };
 573
 574 static const struct parent_map gcc_xo_sleep_map[] = {
 575         { P_XO, 0 },
 576         { P_SLEEP_CLK, 6 }
 577 };
 578
 579 static const struct clk_parent_data gcc_xo_sleep_parent_data[] = {
 580         { .fw_name = "xo" },
 581         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 582 };
 583
 584 static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
 585         { P_XO, 0 },
 586         { P_GPLL1, 1 },
 587         { P_EXT_MCLK, 2 },
 588         { P_SLEEP_CLK, 6 }
 589 };
 590
 591 static const struct clk_parent_data gcc_xo_gpll1_emclk_sleep_parent_data[] = {
 592         { .fw_name = "xo" },
 593         { .hw = &gpll1_vote.hw },
 594         { .fw_name = "ext_mclk", .name = "ext_mclk" },
 595         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 596 };
 597
 598 static const struct parent_map gcc_xo_gpll6_gpll0_map[] = {
 599         { P_XO, 0 },
 600         { P_GPLL6, 1 },
 601         { P_GPLL0, 2 },
 602 };
 603
 604 static const struct clk_parent_data gcc_xo_gpll6_gpll0_parent_data[] = {
 605         { .fw_name = "xo" },
 606         { .hw = &gpll6_vote.hw },
 607         { .hw = &gpll0_vote.hw },
 608 };
 609
 610 static const struct parent_map gcc_xo_gpll6_gpll0a_map[] = {
 611         { P_XO, 0 },
 612         { P_GPLL6, 1 },
 613         { P_GPLL0_AUX, 2 },
 614 };
 615
 616 static const struct clk_parent_data gcc_xo_gpll6_gpll0a_parent_data[] = {
 617         { .fw_name = "xo" },
 618         { .hw = &gpll6_vote.hw },
 619         { .hw = &gpll0_vote.hw },
 620 };
 621
 622 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 623         .cmd_rcgr = 0x27000,
 624         .hid_width = 5,
 625         .parent_map = gcc_xo_gpll0_map,
 626         .clkr.hw.init = &(struct clk_init_data){
 627                 .name = "pcnoc_bfdcd_clk_src",
 628                 .parent_data = gcc_xo_gpll0_parent_data,
 629                 .num_parents = 2,
 630                 .ops = &clk_rcg2_ops,
 631         },
 632 };
 633
 634 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
 635         .cmd_rcgr = 0x26004,
 636         .hid_width = 5,
 637         .parent_map = gcc_xo_gpll0_gpll6a_map,
 638         .clkr.hw.init = &(struct clk_init_data){
 639                 .name = "system_noc_bfdcd_clk_src",
 640                 .parent_data = gcc_xo_gpll0_gpll6a_parent_data,
 641                 .num_parents = 3,
 642                 .ops = &clk_rcg2_ops,
 643         },
 644 };
 645
 646 static struct clk_rcg2 bimc_ddr_clk_src = {
 647         .cmd_rcgr = 0x32004,
 648         .hid_width = 5,
 649         .parent_map = gcc_xo_gpll0_bimc_map,
 650         .clkr.hw.init = &(struct clk_init_data){
 651                 .name = "bimc_ddr_clk_src",
 652                 .parent_data = gcc_xo_gpll0_bimc_parent_data,
 653                 .num_parents = 3,
 654                 .ops = &clk_rcg2_ops,
 655                 .flags = CLK_GET_RATE_NOCACHE,
 656         },
 657 };
 658
 659 static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
 660         F(40000000, P_GPLL0, 10, 1, 2),
 661         F(80000000, P_GPLL0, 10, 0, 0),
 662         { }
 663 };
 664
 665 static struct clk_rcg2 camss_ahb_clk_src = {
 666         .cmd_rcgr = 0x5a000,
 667         .mnd_width = 8,
 668         .hid_width = 5,
 669         .parent_map = gcc_xo_gpll0_map,
 670         .freq_tbl = ftbl_gcc_camss_ahb_clk,
 671         .clkr.hw.init = &(struct clk_init_data){
 672                 .name = "camss_ahb_clk_src",
 673                 .parent_data = gcc_xo_gpll0_parent_data,
 674                 .num_parents = 2,
 675                 .ops = &clk_rcg2_ops,
 676         },
 677 };
 678
 679 static const struct freq_tbl ftbl_apss_ahb_clk[] = {
 680         F(19200000, P_XO, 1, 0, 0),
 681         F(50000000, P_GPLL0, 16, 0, 0),
 682         F(100000000, P_GPLL0, 8, 0, 0),
 683         F(133330000, P_GPLL0, 6, 0, 0),
 684         { }
 685 };
 686
 687 static struct clk_rcg2 apss_ahb_clk_src = {
 688         .cmd_rcgr = 0x46000,
 689         .hid_width = 5,
 690         .parent_map = gcc_xo_gpll0_map,
 691         .freq_tbl = ftbl_apss_ahb_clk,
 692         .clkr.hw.init = &(struct clk_init_data){
 693                 .name = "apss_ahb_clk_src",
 694                 .parent_data = gcc_xo_gpll0_parent_data,
 695                 .num_parents = 2,
 696                 .ops = &clk_rcg2_ops,
 697         },
 698 };
 699
 700 static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
 701         F(100000000, P_GPLL0, 8, 0,     0),
 702         F(200000000, P_GPLL0, 4, 0,     0),
 703         { }
 704 };
 705
 706 static struct clk_rcg2 csi0_clk_src = {
 707         .cmd_rcgr = 0x4e020,
 708         .hid_width = 5,
 709         .parent_map = gcc_xo_gpll0_map,
 710         .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 711         .clkr.hw.init = &(struct clk_init_data){
 712                 .name = "csi0_clk_src",
 713                 .parent_data = gcc_xo_gpll0_parent_data,
 714                 .num_parents = 2,
 715                 .ops = &clk_rcg2_ops,
 716         },
 717 };
 718
 719 static struct clk_rcg2 csi1_clk_src = {
 720         .cmd_rcgr = 0x4f020,
 721         .hid_width = 5,
 722         .parent_map = gcc_xo_gpll0_map,
 723         .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
 724         .clkr.hw.init = &(struct clk_init_data){
 725                 .name = "csi1_clk_src",
 726                 .parent_data = gcc_xo_gpll0_parent_data,
 727                 .num_parents = 2,
 728                 .ops = &clk_rcg2_ops,
 729         },
 730 };
 731
 732 static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
 733         F(19200000, P_XO, 1, 0, 0),
 734         F(50000000, P_GPLL0, 16, 0, 0),
 735         F(80000000, P_GPLL0, 10, 0, 0),
 736         F(100000000, P_GPLL0, 8, 0, 0),
 737         F(160000000, P_GPLL0, 5, 0, 0),
 738         F(200000000, P_GPLL0, 4, 0, 0),
 739         F(220000000, P_GPLL3, 5, 0, 0),
 740         F(266670000, P_GPLL0, 3, 0, 0),
 741         F(310000000, P_GPLL2_AUX, 3, 0, 0),
 742         F(400000000, P_GPLL0, 2, 0, 0),
 743         F(465000000, P_GPLL2_AUX, 2, 0, 0),
 744         F(550000000, P_GPLL3, 2, 0, 0),
 745         { }
 746 };
 747
 748 static struct clk_rcg2 gfx3d_clk_src = {
 749         .cmd_rcgr = 0x59000,
 750         .hid_width = 5,
 751         .parent_map = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_map,
 752         .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
 753         .clkr.hw.init = &(struct clk_init_data){
 754                 .name = "gfx3d_clk_src",
 755                 .parent_data = gcc_xo_gpll0_gpll2a_gpll3_gpll6a_parent_data,
 756                 .num_parents = 5,
 757                 .ops = &clk_rcg2_ops,
 758         },
 759 };
 760
 761 static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
 762         F(50000000, P_GPLL0, 16, 0, 0),
 763         F(80000000, P_GPLL0, 10, 0, 0),
 764         F(100000000, P_GPLL0, 8, 0, 0),
 765         F(160000000, P_GPLL0, 5, 0, 0),
 766         F(177780000, P_GPLL0, 4.5, 0, 0),
 767         F(200000000, P_GPLL0, 4, 0, 0),
 768         F(266670000, P_GPLL0, 3, 0, 0),
 769         F(320000000, P_GPLL0, 2.5, 0, 0),
 770         F(400000000, P_GPLL0, 2, 0, 0),
 771         F(465000000, P_GPLL2, 2, 0, 0),
 772         F(480000000, P_GPLL4, 2.5, 0, 0),
 773         F(600000000, P_GPLL4, 2, 0, 0),
 774         { }
 775 };
 776
 777 static struct clk_rcg2 vfe0_clk_src = {
 778         .cmd_rcgr = 0x58000,
 779         .hid_width = 5,
 780         .parent_map = gcc_xo_gpll0_gpll2_gpll4_map,
 781         .freq_tbl = ftbl_gcc_camss_vfe0_clk,
 782         .clkr.hw.init = &(struct clk_init_data){
 783                 .name = "vfe0_clk_src",
 784                 .parent_data = gcc_xo_gpll0_gpll2_gpll4_parent_data,
 785                 .num_parents = 4,
 786                 .ops = &clk_rcg2_ops,
 787         },
 788 };
 789
 790 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
 791         F(19200000, P_XO, 1, 0, 0),
 792         F(50000000, P_GPLL0, 16, 0, 0),
 793         { }
 794 };
 795
 796 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 797         .cmd_rcgr = 0x0200c,
 798         .hid_width = 5,
 799         .parent_map = gcc_xo_gpll0_map,
 800         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 801         .clkr.hw.init = &(struct clk_init_data){
 802                 .name = "blsp1_qup1_i2c_apps_clk_src",
 803                 .parent_data = gcc_xo_gpll0_parent_data,
 804                 .num_parents = 2,
 805                 .ops = &clk_rcg2_ops,
 806         },
 807 };
 808
 809 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
 810         F(960000, P_XO, 10, 1, 2),
 811         F(4800000, P_XO, 4, 0, 0),
 812         F(9600000, P_XO, 2, 0, 0),
 813         F(16000000, P_GPLL0, 10, 1, 5),
 814         F(19200000, P_XO, 1, 0, 0),
 815         F(25000000, P_GPLL0, 16, 1, 2),
 816         F(50000000, P_GPLL0, 16, 0, 0),
 817         { }
 818 };
 819
 820 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 821         .cmd_rcgr = 0x02024,
 822         .mnd_width = 8,
 823         .hid_width = 5,
 824         .parent_map = gcc_xo_gpll0_map,
 825         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 826         .clkr.hw.init = &(struct clk_init_data){
 827                 .name = "blsp1_qup1_spi_apps_clk_src",
 828                 .parent_data = gcc_xo_gpll0_parent_data,
 829                 .num_parents = 2,
 830                 .ops = &clk_rcg2_ops,
 831         },
 832 };
 833
 834 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 835         .cmd_rcgr = 0x03000,
 836         .hid_width = 5,
 837         .parent_map = gcc_xo_gpll0_map,
 838         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 839         .clkr.hw.init = &(struct clk_init_data){
 840                 .name = "blsp1_qup2_i2c_apps_clk_src",
 841                 .parent_data = gcc_xo_gpll0_parent_data,
 842                 .num_parents = 2,
 843                 .ops = &clk_rcg2_ops,
 844         },
 845 };
 846
 847 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 848         .cmd_rcgr = 0x03014,
 849         .mnd_width = 8,
 850         .hid_width = 5,
 851         .parent_map = gcc_xo_gpll0_map,
 852         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 853         .clkr.hw.init = &(struct clk_init_data){
 854                 .name = "blsp1_qup2_spi_apps_clk_src",
 855                 .parent_data = gcc_xo_gpll0_parent_data,
 856                 .num_parents = 2,
 857                 .ops = &clk_rcg2_ops,
 858         },
 859 };
 860
 861 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 862         .cmd_rcgr = 0x04000,
 863         .hid_width = 5,
 864         .parent_map = gcc_xo_gpll0_map,
 865         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 866         .clkr.hw.init = &(struct clk_init_data){
 867                 .name = "blsp1_qup3_i2c_apps_clk_src",
 868                 .parent_data = gcc_xo_gpll0_parent_data,
 869                 .num_parents = 2,
 870                 .ops = &clk_rcg2_ops,
 871         },
 872 };
 873
 874 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 875         .cmd_rcgr = 0x04024,
 876         .mnd_width = 8,
 877         .hid_width = 5,
 878         .parent_map = gcc_xo_gpll0_map,
 879         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 880         .clkr.hw.init = &(struct clk_init_data){
 881                 .name = "blsp1_qup3_spi_apps_clk_src",
 882                 .parent_data = gcc_xo_gpll0_parent_data,
 883                 .num_parents = 2,
 884                 .ops = &clk_rcg2_ops,
 885         },
 886 };
 887
 888 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 889         .cmd_rcgr = 0x05000,
 890         .hid_width = 5,
 891         .parent_map = gcc_xo_gpll0_map,
 892         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 893         .clkr.hw.init = &(struct clk_init_data){
 894                 .name = "blsp1_qup4_i2c_apps_clk_src",
 895                 .parent_data = gcc_xo_gpll0_parent_data,
 896                 .num_parents = 2,
 897                 .ops = &clk_rcg2_ops,
 898         },
 899 };
 900
 901 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 902         .cmd_rcgr = 0x05024,
 903         .mnd_width = 8,
 904         .hid_width = 5,
 905         .parent_map = gcc_xo_gpll0_map,
 906         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 907         .clkr.hw.init = &(struct clk_init_data){
 908                 .name = "blsp1_qup4_spi_apps_clk_src",
 909                 .parent_data = gcc_xo_gpll0_parent_data,
 910                 .num_parents = 2,
 911                 .ops = &clk_rcg2_ops,
 912         },
 913 };
 914
 915 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 916         .cmd_rcgr = 0x06000,
 917         .hid_width = 5,
 918         .parent_map = gcc_xo_gpll0_map,
 919         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 920         .clkr.hw.init = &(struct clk_init_data){
 921                 .name = "blsp1_qup5_i2c_apps_clk_src",
 922                 .parent_data = gcc_xo_gpll0_parent_data,
 923                 .num_parents = 2,
 924                 .ops = &clk_rcg2_ops,
 925         },
 926 };
 927
 928 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 929         .cmd_rcgr = 0x06024,
 930         .mnd_width = 8,
 931         .hid_width = 5,
 932         .parent_map = gcc_xo_gpll0_map,
 933         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 934         .clkr.hw.init = &(struct clk_init_data){
 935                 .name = "blsp1_qup5_spi_apps_clk_src",
 936                 .parent_data = gcc_xo_gpll0_parent_data,
 937                 .num_parents = 2,
 938                 .ops = &clk_rcg2_ops,
 939         },
 940 };
 941
 942 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 943         .cmd_rcgr = 0x07000,
 944         .hid_width = 5,
 945         .parent_map = gcc_xo_gpll0_map,
 946         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 947         .clkr.hw.init = &(struct clk_init_data){
 948                 .name = "blsp1_qup6_i2c_apps_clk_src",
 949                 .parent_data = gcc_xo_gpll0_parent_data,
 950                 .num_parents = 2,
 951                 .ops = &clk_rcg2_ops,
 952         },
 953 };
 954
 955 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 956         .cmd_rcgr = 0x07024,
 957         .mnd_width = 8,
 958         .hid_width = 5,
 959         .parent_map = gcc_xo_gpll0_map,
 960         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 961         .clkr.hw.init = &(struct clk_init_data){
 962                 .name = "blsp1_qup6_spi_apps_clk_src",
 963                 .parent_data = gcc_xo_gpll0_parent_data,
 964                 .num_parents = 2,
 965                 .ops = &clk_rcg2_ops,
 966         },
 967 };
 968
 969 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
 970         F(3686400, P_GPLL0, 1, 72, 15625),
 971         F(7372800, P_GPLL0, 1, 144, 15625),
 972         F(14745600, P_GPLL0, 1, 288, 15625),
 973         F(16000000, P_GPLL0, 10, 1, 5),
 974         F(19200000, P_XO, 1, 0, 0),
 975         F(24000000, P_GPLL0, 1, 3, 100),
 976         F(25000000, P_GPLL0, 16, 1, 2),
 977         F(32000000, P_GPLL0, 1, 1, 25),
 978         F(40000000, P_GPLL0, 1, 1, 20),
 979         F(46400000, P_GPLL0, 1, 29, 500),
 980         F(48000000, P_GPLL0, 1, 3, 50),
 981         F(51200000, P_GPLL0, 1, 8, 125),
 982         F(56000000, P_GPLL0, 1, 7, 100),
 983         F(58982400, P_GPLL0, 1, 1152, 15625),
 984         F(60000000, P_GPLL0, 1, 3, 40),
 985         { }
 986 };
 987
 988 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 989         .cmd_rcgr = 0x02044,
 990         .mnd_width = 16,
 991         .hid_width = 5,
 992         .parent_map = gcc_xo_gpll0_map,
 993         .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 994         .clkr.hw.init = &(struct clk_init_data){
 995                 .name = "blsp1_uart1_apps_clk_src",
 996                 .parent_data = gcc_xo_gpll0_parent_data,
 997                 .num_parents = 2,
 998                 .ops = &clk_rcg2_ops,
 999         },
1000 };
1001
1002 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
1003         .cmd_rcgr = 0x03034,
1004         .mnd_width = 16,
1005         .hid_width = 5,
1006         .parent_map = gcc_xo_gpll0_map,
1007         .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
1008         .clkr.hw.init = &(struct clk_init_data){
1009                 .name = "blsp1_uart2_apps_clk_src",
1010                 .parent_data = gcc_xo_gpll0_parent_data,
1011                 .num_parents = 2,
1012                 .ops = &clk_rcg2_ops,
1013         },
1014 };
1015
1016 static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
1017         F(19200000,     P_XO, 1, 0,     0),
1018         { }
1019 };
1020
1021 static struct clk_rcg2 cci_clk_src = {
1022         .cmd_rcgr = 0x51000,
1023         .mnd_width = 8,
1024         .hid_width = 5,
1025         .parent_map = gcc_xo_gpll0a_map,
1026         .freq_tbl = ftbl_gcc_camss_cci_clk,
1027         .clkr.hw.init = &(struct clk_init_data){
1028                 .name = "cci_clk_src",
1029                 .parent_data = gcc_xo_gpll0a_parent_data,
1030                 .num_parents = 2,
1031                 .ops = &clk_rcg2_ops,
1032         },
1033 };
1034
1035 static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
1036         F(100000000, P_GPLL0, 8, 0, 0),
1037         F(200000000, P_GPLL0, 4, 0, 0),
1038         { }
1039 };
1040
1041 static struct clk_rcg2 camss_gp0_clk_src = {
1042         .cmd_rcgr = 0x54000,
1043         .mnd_width = 8,
1044         .hid_width = 5,
1045         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1046         .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1047         .clkr.hw.init = &(struct clk_init_data){
1048                 .name = "camss_gp0_clk_src",
1049                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1050                 .num_parents = 4,
1051                 .ops = &clk_rcg2_ops,
1052         },
1053 };
1054
1055 static struct clk_rcg2 camss_gp1_clk_src = {
1056         .cmd_rcgr = 0x55000,
1057         .mnd_width = 8,
1058         .hid_width = 5,
1059         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1060         .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1061         .clkr.hw.init = &(struct clk_init_data){
1062                 .name = "camss_gp1_clk_src",
1063                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1064                 .num_parents = 4,
1065                 .ops = &clk_rcg2_ops,
1066         },
1067 };
1068
1069 static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
1070         F(133330000, P_GPLL0, 6, 0,     0),
1071         F(266670000, P_GPLL0, 3, 0,     0),
1072         F(320000000, P_GPLL0, 2.5, 0, 0),
1073         { }
1074 };
1075
1076 static struct clk_rcg2 jpeg0_clk_src = {
1077         .cmd_rcgr = 0x57000,
1078         .hid_width = 5,
1079         .parent_map = gcc_xo_gpll0_map,
1080         .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
1081         .clkr.hw.init = &(struct clk_init_data){
1082                 .name = "jpeg0_clk_src",
1083                 .parent_data = gcc_xo_gpll0_parent_data,
1084                 .num_parents = 2,
1085                 .ops = &clk_rcg2_ops,
1086         },
1087 };
1088
1089 static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
1090         F(24000000, P_GPLL0, 1, 1, 45),
1091         F(66670000, P_GPLL0, 12, 0, 0),
1092         { }
1093 };
1094
1095 static struct clk_rcg2 mclk0_clk_src = {
1096         .cmd_rcgr = 0x52000,
1097         .mnd_width = 8,
1098         .hid_width = 5,
1099         .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
1100         .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
1101         .clkr.hw.init = &(struct clk_init_data){
1102                 .name = "mclk0_clk_src",
1103                 .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
1104                 .num_parents = 5,
1105                 .ops = &clk_rcg2_ops,
1106         },
1107 };
1108
1109 static struct clk_rcg2 mclk1_clk_src = {
1110         .cmd_rcgr = 0x53000,
1111         .mnd_width = 8,
1112         .hid_width = 5,
1113         .parent_map = gcc_xo_gpll0_gpll1a_gpll6_sleep_map,
1114         .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
1115         .clkr.hw.init = &(struct clk_init_data){
1116                 .name = "mclk1_clk_src",
1117                 .parent_data = gcc_xo_gpll0_gpll1a_gpll6_sleep_parent_data,
1118                 .num_parents = 5,
1119                 .ops = &clk_rcg2_ops,
1120         },
1121 };
1122
1123 static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
1124         F(100000000, P_GPLL0, 8, 0,     0),
1125         F(200000000, P_GPLL0, 4, 0,     0),
1126         { }
1127 };
1128
1129 static struct clk_rcg2 csi0phytimer_clk_src = {
1130         .cmd_rcgr = 0x4e000,
1131         .hid_width = 5,
1132         .parent_map = gcc_xo_gpll0_gpll1a_map,
1133         .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1134         .clkr.hw.init = &(struct clk_init_data){
1135                 .name = "csi0phytimer_clk_src",
1136                 .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
1137                 .num_parents = 3,
1138                 .ops = &clk_rcg2_ops,
1139         },
1140 };
1141
1142 static struct clk_rcg2 csi1phytimer_clk_src = {
1143         .cmd_rcgr = 0x4f000,
1144         .hid_width = 5,
1145         .parent_map = gcc_xo_gpll0_gpll1a_map,
1146         .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1147         .clkr.hw.init = &(struct clk_init_data){
1148                 .name = "csi1phytimer_clk_src",
1149                 .parent_data = gcc_xo_gpll0_gpll1a_parent_data,
1150                 .num_parents = 3,
1151                 .ops = &clk_rcg2_ops,
1152         },
1153 };
1154
1155 static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
1156         F(160000000, P_GPLL0, 5, 0, 0),
1157         F(320000000, P_GPLL0, 2.5, 0, 0),
1158         F(465000000, P_GPLL2, 2, 0, 0),
1159         { }
1160 };
1161
1162 static struct clk_rcg2 cpp_clk_src = {
1163         .cmd_rcgr = 0x58018,
1164         .hid_width = 5,
1165         .parent_map = gcc_xo_gpll0_gpll2_map,
1166         .freq_tbl = ftbl_gcc_camss_cpp_clk,
1167         .clkr.hw.init = &(struct clk_init_data){
1168                 .name = "cpp_clk_src",
1169                 .parent_data = gcc_xo_gpll0_gpll2_parent_data,
1170                 .num_parents = 3,
1171                 .ops = &clk_rcg2_ops,
1172         },
1173 };
1174
1175 static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
1176         F(50000000, P_GPLL0, 16, 0, 0),
1177         F(80000000, P_GPLL0, 10, 0, 0),
1178         F(100000000, P_GPLL0, 8, 0, 0),
1179         F(160000000, P_GPLL0, 5, 0, 0),
1180         { }
1181 };
1182
1183 /* This is not in the documentation but is in the downstream driver */
1184 static struct clk_rcg2 crypto_clk_src = {
1185         .cmd_rcgr = 0x16004,
1186         .hid_width = 5,
1187         .parent_map = gcc_xo_gpll0_map,
1188         .freq_tbl = ftbl_gcc_crypto_clk,
1189         .clkr.hw.init = &(struct clk_init_data){
1190                 .name = "crypto_clk_src",
1191                 .parent_data = gcc_xo_gpll0_parent_data,
1192                 .num_parents = 2,
1193                 .ops = &clk_rcg2_ops,
1194         },
1195 };
1196
1197 static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
1198         F(19200000, P_XO, 1, 0, 0),
1199         { }
1200 };
1201
1202 static struct clk_rcg2 gp1_clk_src = {
1203         .cmd_rcgr = 0x08004,
1204         .mnd_width = 8,
1205         .hid_width = 5,
1206         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1207         .freq_tbl = ftbl_gcc_gp1_3_clk,
1208         .clkr.hw.init = &(struct clk_init_data){
1209                 .name = "gp1_clk_src",
1210                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1211                 .num_parents = 3,
1212                 .ops = &clk_rcg2_ops,
1213         },
1214 };
1215
1216 static struct clk_rcg2 gp2_clk_src = {
1217         .cmd_rcgr = 0x09004,
1218         .mnd_width = 8,
1219         .hid_width = 5,
1220         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1221         .freq_tbl = ftbl_gcc_gp1_3_clk,
1222         .clkr.hw.init = &(struct clk_init_data){
1223                 .name = "gp2_clk_src",
1224                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1225                 .num_parents = 3,
1226                 .ops = &clk_rcg2_ops,
1227         },
1228 };
1229
1230 static struct clk_rcg2 gp3_clk_src = {
1231         .cmd_rcgr = 0x0a004,
1232         .mnd_width = 8,
1233         .hid_width = 5,
1234         .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
1235         .freq_tbl = ftbl_gcc_gp1_3_clk,
1236         .clkr.hw.init = &(struct clk_init_data){
1237                 .name = "gp3_clk_src",
1238                 .parent_data = gcc_xo_gpll0_gpll1a_sleep_parent_data,
1239                 .num_parents = 3,
1240                 .ops = &clk_rcg2_ops,
1241         },
1242 };
1243
1244 static struct clk_rcg2 byte0_clk_src = {
1245         .cmd_rcgr = 0x4d044,
1246         .hid_width = 5,
1247         .parent_map = gcc_xo_gpll0a_dsibyte_map,
1248         .clkr.hw.init = &(struct clk_init_data){
1249                 .name = "byte0_clk_src",
1250                 .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
1251                 .num_parents = 3,
1252                 .ops = &clk_byte2_ops,
1253                 .flags = CLK_SET_RATE_PARENT,
1254         },
1255 };
1256
1257 static struct clk_rcg2 byte1_clk_src = {
1258         .cmd_rcgr = 0x4d0b0,
1259         .hid_width = 5,
1260         .parent_map = gcc_xo_gpll0a_dsibyte_map,
1261         .clkr.hw.init = &(struct clk_init_data){
1262                 .name = "byte1_clk_src",
1263                 .parent_data = gcc_xo_gpll0a_dsibyte_parent_data,
1264                 .num_parents = 3,
1265                 .ops = &clk_byte2_ops,
1266                 .flags = CLK_SET_RATE_PARENT,
1267         },
1268 };
1269
1270 static const struct freq_tbl ftbl_gcc_mdss_esc_clk[] = {
1271         F(19200000, P_XO, 1, 0, 0),
1272         { }
1273 };
1274
1275 static struct clk_rcg2 esc0_clk_src = {
1276         .cmd_rcgr = 0x4d060,
1277         .hid_width = 5,
1278         .parent_map = gcc_xo_dsibyte_map,
1279         .freq_tbl = ftbl_gcc_mdss_esc_clk,
1280         .clkr.hw.init = &(struct clk_init_data){
1281                 .name = "esc0_clk_src",
1282                 .parent_data = gcc_xo_dsibyte_parent_data,
1283                 .num_parents = 2,
1284                 .ops = &clk_rcg2_ops,
1285         },
1286 };
1287
1288 static struct clk_rcg2 esc1_clk_src = {
1289         .cmd_rcgr = 0x4d0a8,
1290         .hid_width = 5,
1291         .parent_map = gcc_xo_dsibyte_map,
1292         .freq_tbl = ftbl_gcc_mdss_esc_clk,
1293         .clkr.hw.init = &(struct clk_init_data){
1294                 .name = "esc1_clk_src",
1295                 .parent_data = gcc_xo_dsibyte_parent_data,
1296                 .num_parents = 2,
1297                 .ops = &clk_rcg2_ops,
1298         },
1299 };
1300
1301 static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
1302         F(50000000, P_GPLL0_AUX, 16, 0, 0),
1303         F(80000000, P_GPLL0_AUX, 10, 0, 0),
1304         F(100000000, P_GPLL0_AUX, 8, 0, 0),
1305         F(160000000, P_GPLL0_AUX, 5, 0, 0),
1306         F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
1307         F(200000000, P_GPLL0_AUX, 4, 0, 0),
1308         F(266670000, P_GPLL0_AUX, 3, 0, 0),
1309         F(307200000, P_GPLL1, 2, 0, 0),
1310         F(366670000, P_GPLL3_AUX, 3, 0, 0),
1311         { }
1312 };
1313
1314 static struct clk_rcg2 mdp_clk_src = {
1315         .cmd_rcgr = 0x4d014,
1316         .hid_width = 5,
1317         .parent_map = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_map,
1318         .freq_tbl = ftbl_gcc_mdss_mdp_clk,
1319         .clkr.hw.init = &(struct clk_init_data){
1320                 .name = "mdp_clk_src",
1321                 .parent_data = gcc_xo_gpll1_dsiphy_gpll6_gpll3a_gpll0a_parent_data,
1322                 .num_parents = 6,
1323                 .ops = &clk_rcg2_ops,
1324         },
1325 };
1326
1327 static struct clk_rcg2 pclk0_clk_src = {
1328         .cmd_rcgr = 0x4d000,
1329         .mnd_width = 8,
1330         .hid_width = 5,
1331         .parent_map = gcc_xo_gpll0a_dsiphy_map,
1332         .clkr.hw.init = &(struct clk_init_data){
1333                 .name = "pclk0_clk_src",
1334                 .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
1335                 .num_parents = 3,
1336                 .ops = &clk_pixel_ops,
1337                 .flags = CLK_SET_RATE_PARENT,
1338         },
1339 };
1340
1341 static struct clk_rcg2 pclk1_clk_src = {
1342         .cmd_rcgr = 0x4d0b8,
1343         .mnd_width = 8,
1344         .hid_width = 5,
1345         .parent_map = gcc_xo_gpll0a_dsiphy_map,
1346         .clkr.hw.init = &(struct clk_init_data){
1347                 .name = "pclk1_clk_src",
1348                 .parent_data = gcc_xo_gpll0a_dsiphy_parent_data,
1349                 .num_parents = 3,
1350                 .ops = &clk_pixel_ops,
1351                 .flags = CLK_SET_RATE_PARENT,
1352         },
1353 };
1354
1355 static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
1356         F(19200000, P_XO, 1, 0, 0),
1357         { }
1358 };
1359
1360 static struct clk_rcg2 vsync_clk_src = {
1361         .cmd_rcgr = 0x4d02c,
1362         .hid_width = 5,
1363         .parent_map = gcc_xo_gpll0a_map,
1364         .freq_tbl = ftbl_gcc_mdss_vsync_clk,
1365         .clkr.hw.init = &(struct clk_init_data){
1366                 .name = "vsync_clk_src",
1367                 .parent_data = gcc_xo_gpll0a_parent_data,
1368                 .num_parents = 2,
1369                 .ops = &clk_rcg2_ops,
1370         },
1371 };
1372
1373 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1374         F(64000000, P_GPLL0, 12.5, 0, 0),
1375         { }
1376 };
1377
1378 /* This is not in the documentation but is in the downstream driver */
1379 static struct clk_rcg2 pdm2_clk_src = {
1380         .cmd_rcgr = 0x44010,
1381         .hid_width = 5,
1382         .parent_map = gcc_xo_gpll0_map,
1383         .freq_tbl = ftbl_gcc_pdm2_clk,
1384         .clkr.hw.init = &(struct clk_init_data){
1385                 .name = "pdm2_clk_src",
1386                 .parent_data = gcc_xo_gpll0_parent_data,
1387                 .num_parents = 2,
1388                 .ops = &clk_rcg2_ops,
1389         },
1390 };
1391
1392 static const struct freq_tbl ftbl_gcc_sdcc_apps_clk[] = {
1393         F(144000, P_XO, 16, 3, 25),
1394         F(400000, P_XO, 12, 1, 4),
1395         F(20000000, P_GPLL0, 10, 1, 4),
1396         F(25000000, P_GPLL0, 16, 1, 2),
1397         F(50000000, P_GPLL0, 16, 0, 0),
1398         F(100000000, P_GPLL0, 8, 0, 0),
1399         F(177770000, P_GPLL0, 4.5, 0, 0),
1400         F(200000000, P_GPLL0, 4, 0, 0),
1401         { }
1402 };
1403
1404 static struct clk_rcg2 sdcc1_apps_clk_src = {
1405         .cmd_rcgr = 0x42004,
1406         .mnd_width = 8,
1407         .hid_width = 5,
1408         .parent_map = gcc_xo_gpll0_map,
1409         .freq_tbl = ftbl_gcc_sdcc_apps_clk,
1410         .clkr.hw.init = &(struct clk_init_data){
1411                 .name = "sdcc1_apps_clk_src",
1412                 .parent_data = gcc_xo_gpll0_parent_data,
1413                 .num_parents = 2,
1414                 .ops = &clk_rcg2_floor_ops,
1415         },
1416 };
1417
1418 static struct clk_rcg2 sdcc2_apps_clk_src = {
1419         .cmd_rcgr = 0x43004,
1420         .mnd_width = 8,
1421         .hid_width = 5,
1422         .parent_map = gcc_xo_gpll0_map,
1423         .freq_tbl = ftbl_gcc_sdcc_apps_clk,
1424         .clkr.hw.init = &(struct clk_init_data){
1425                 .name = "sdcc2_apps_clk_src",
1426                 .parent_data = gcc_xo_gpll0_parent_data,
1427                 .num_parents = 2,
1428                 .ops = &clk_rcg2_floor_ops,
1429         },
1430 };
1431
1432 static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
1433         F(154285000, P_GPLL6, 7, 0, 0),
1434         F(320000000, P_GPLL0, 2.5, 0, 0),
1435         F(400000000, P_GPLL0, 2, 0, 0),
1436         { }
1437 };
1438
1439 static struct clk_rcg2 apss_tcu_clk_src = {
1440         .cmd_rcgr = 0x1207c,
1441         .hid_width = 5,
1442         .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
1443         .freq_tbl = ftbl_gcc_apss_tcu_clk,
1444         .clkr.hw.init = &(struct clk_init_data){
1445                 .name = "apss_tcu_clk_src",
1446                 .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
1447                 .num_parents = 5,
1448                 .ops = &clk_rcg2_ops,
1449         },
1450 };
1451
1452 static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
1453         F(19200000, P_XO, 1, 0, 0),
1454         F(100000000, P_GPLL0, 8, 0, 0),
1455         F(200000000, P_GPLL0, 4, 0, 0),
1456         F(266500000, P_BIMC, 4, 0, 0),
1457         F(400000000, P_GPLL0, 2, 0, 0),
1458         F(533000000, P_BIMC, 2, 0, 0),
1459         { }
1460 };
1461
1462 static struct clk_rcg2 bimc_gpu_clk_src = {
1463         .cmd_rcgr = 0x31028,
1464         .hid_width = 5,
1465         .parent_map = gcc_xo_gpll0_gpll5a_gpll6_bimc_map,
1466         .freq_tbl = ftbl_gcc_bimc_gpu_clk,
1467         .clkr.hw.init = &(struct clk_init_data){
1468                 .name = "bimc_gpu_clk_src",
1469                 .parent_data = gcc_xo_gpll0_gpll5a_gpll6_bimc_parent_data,
1470                 .num_parents = 5,
1471                 .flags = CLK_GET_RATE_NOCACHE,
1472                 .ops = &clk_rcg2_ops,
1473         },
1474 };
1475
1476 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1477         F(80000000, P_GPLL0, 10, 0, 0),
1478         { }
1479 };
1480
1481 static struct clk_rcg2 usb_hs_system_clk_src = {
1482         .cmd_rcgr = 0x41010,
1483         .hid_width = 5,
1484         .parent_map = gcc_xo_gpll0_map,
1485         .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1486         .clkr.hw.init = &(struct clk_init_data){
1487                 .name = "usb_hs_system_clk_src",
1488                 .parent_data = gcc_xo_gpll0_parent_data,
1489                 .num_parents = 2,
1490                 .ops = &clk_rcg2_ops,
1491         },
1492 };
1493
1494 static const struct freq_tbl ftbl_gcc_usb_fs_system_clk[] = {
1495         F(64000000, P_GPLL0, 12.5, 0, 0),
1496         { }
1497 };
1498
1499 static struct clk_rcg2 usb_fs_system_clk_src = {
1500         .cmd_rcgr = 0x3f010,
1501         .hid_width = 5,
1502         .parent_map = gcc_xo_gpll0_map,
1503         .freq_tbl = ftbl_gcc_usb_fs_system_clk,
1504         .clkr.hw.init = &(struct clk_init_data){
1505                 .name = "usb_fs_system_clk_src",
1506                 .parent_data = gcc_xo_gpll6_gpll0_parent_data,
1507                 .num_parents = 3,
1508                 .ops = &clk_rcg2_ops,
1509         },
1510 };
1511
1512 static const struct freq_tbl ftbl_gcc_usb_fs_ic_clk[] = {
1513         F(60000000, P_GPLL6, 1, 1, 18),
1514         { }
1515 };
1516
1517 static struct clk_rcg2 usb_fs_ic_clk_src = {
1518         .cmd_rcgr = 0x3f034,
1519         .hid_width = 5,
1520         .parent_map = gcc_xo_gpll0_map,
1521         .freq_tbl = ftbl_gcc_usb_fs_ic_clk,
1522         .clkr.hw.init = &(struct clk_init_data){
1523                 .name = "usb_fs_ic_clk_src",
1524                 .parent_data = gcc_xo_gpll6_gpll0a_parent_data,
1525                 .num_parents = 3,
1526                 .ops = &clk_rcg2_ops,
1527         },
1528 };
1529
1530 static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
1531         F(3200000, P_XO, 6, 0, 0),
1532         F(6400000, P_XO, 3, 0, 0),
1533         F(9600000, P_XO, 2, 0, 0),
1534         F(19200000, P_XO, 1, 0, 0),
1535         F(40000000, P_GPLL0, 10, 1, 2),
1536         F(66670000, P_GPLL0, 12, 0, 0),
1537         F(80000000, P_GPLL0, 10, 0, 0),
1538         F(100000000, P_GPLL0, 8, 0, 0),
1539         { }
1540 };
1541
1542 static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
1543         .cmd_rcgr = 0x1c010,
1544         .hid_width = 5,
1545         .mnd_width = 8,
1546         .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
1547         .freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
1548         .clkr.hw.init = &(struct clk_init_data){
1549                 .name = "ultaudio_ahbfabric_clk_src",
1550                 .parent_data = gcc_xo_gpll0_gpll1_sleep_parent_data,
1551                 .num_parents = 4,
1552                 .ops = &clk_rcg2_ops,
1553         },
1554 };
1555
1556 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
1557         .halt_reg = 0x1c028,
1558         .clkr = {
1559                 .enable_reg = 0x1c028,
1560                 .enable_mask = BIT(0),
1561                 .hw.init = &(struct clk_init_data){
1562                         .name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
1563                         .parent_data = &(const struct clk_parent_data){
1564                                 .hw = &ultaudio_ahbfabric_clk_src.clkr.hw,
1565                         },
1566                         .num_parents = 1,
1567                         .flags = CLK_SET_RATE_PARENT,
1568                         .ops = &clk_branch2_ops,
1569                 },
1570         },
1571 };
1572
1573 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
1574         .halt_reg = 0x1c024,
1575         .clkr = {
1576                 .enable_reg = 0x1c024,
1577                 .enable_mask = BIT(0),
1578                 .hw.init = &(struct clk_init_data){
1579                         .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
1580                         .parent_data = &(const struct clk_parent_data){
1581                                 .hw = &ultaudio_ahbfabric_clk_src.clkr.hw,
1582                         },
1583                         .num_parents = 1,
1584                         .flags = CLK_SET_RATE_PARENT,
1585                         .ops = &clk_branch2_ops,
1586                 },
1587         },
1588 };
1589
1590 static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
1591         F(128000, P_XO, 10, 1, 15),
1592         F(256000, P_XO, 5, 1, 15),
1593         F(384000, P_XO, 5, 1, 10),
1594         F(512000, P_XO, 5, 2, 15),
1595         F(576000, P_XO, 5, 3, 20),
1596         F(705600, P_GPLL1, 16, 1, 80),
1597         F(768000, P_XO, 5, 1, 5),
1598         F(800000, P_XO, 5, 5, 24),
1599         F(1024000, P_XO, 5, 4, 15),
1600         F(1152000, P_XO, 1, 3, 50),
1601         F(1411200, P_GPLL1, 16, 1, 40),
1602         F(1536000, P_XO, 1, 2, 25),
1603         F(1600000, P_XO, 12, 0, 0),
1604         F(1728000, P_XO, 5, 9, 20),
1605         F(2048000, P_XO, 5, 8, 15),
1606         F(2304000, P_XO, 5, 3, 5),
1607         F(2400000, P_XO, 8, 0, 0),
1608         F(2822400, P_GPLL1, 16, 1, 20),
1609         F(3072000, P_XO, 5, 4, 5),
1610         F(4096000, P_GPLL1, 9, 2, 49),
1611         F(4800000, P_XO, 4, 0, 0),
1612         F(5644800, P_GPLL1, 16, 1, 10),
1613         F(6144000, P_GPLL1, 7, 1, 21),
1614         F(8192000, P_GPLL1, 9, 4, 49),
1615         F(9600000, P_XO, 2, 0, 0),
1616         F(11289600, P_GPLL1, 16, 1, 5),
1617         F(12288000, P_GPLL1, 7, 2, 21),
1618         { }
1619 };
1620
1621 static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src = {
1622         .cmd_rcgr = 0x1c054,
1623         .hid_width = 5,
1624         .mnd_width = 8,
1625         .parent_map = gcc_xo_gpll1_epi2s_emclk_sleep_map,
1626         .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1627         .clkr.hw.init = &(struct clk_init_data){
1628                 .name = "ultaudio_lpaif_pri_i2s_clk_src",
1629                 .parent_data = gcc_xo_gpll1_epi2s_emclk_sleep_parent_data,
1630                 .num_parents = 5,
1631                 .ops = &clk_rcg2_ops,
1632         },
1633 };
1634
1635 static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk = {
1636         .halt_reg = 0x1c068,
1637         .clkr = {
1638                 .enable_reg = 0x1c068,
1639                 .enable_mask = BIT(0),
1640                 .hw.init = &(struct clk_init_data){
1641                         .name = "gcc_ultaudio_lpaif_pri_i2s_clk",
1642                         .parent_data = &(const struct clk_parent_data){
1643                                 .hw = &ultaudio_lpaif_pri_i2s_clk_src.clkr.hw,
1644                         },
1645                         .num_parents = 1,
1646                         .flags = CLK_SET_RATE_PARENT,
1647                         .ops = &clk_branch2_ops,
1648                 },
1649         },
1650 };
1651
1652 static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src = {
1653         .cmd_rcgr = 0x1c06c,
1654         .hid_width = 5,
1655         .mnd_width = 8,
1656         .parent_map = gcc_xo_gpll1_esi2s_emclk_sleep_map,
1657         .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1658         .clkr.hw.init = &(struct clk_init_data){
1659                 .name = "ultaudio_lpaif_sec_i2s_clk_src",
1660                 .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
1661                 .num_parents = 5,
1662                 .ops = &clk_rcg2_ops,
1663         },
1664 };
1665
1666 static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk = {
1667         .halt_reg = 0x1c080,
1668         .clkr = {
1669                 .enable_reg = 0x1c080,
1670                 .enable_mask = BIT(0),
1671                 .hw.init = &(struct clk_init_data){
1672                         .name = "gcc_ultaudio_lpaif_sec_i2s_clk",
1673                         .parent_data = &(const struct clk_parent_data){
1674                                 .hw = &ultaudio_lpaif_sec_i2s_clk_src.clkr.hw,
1675                         },
1676                         .num_parents = 1,
1677                         .flags = CLK_SET_RATE_PARENT,
1678                         .ops = &clk_branch2_ops,
1679                 },
1680         },
1681 };
1682
1683 static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src = {
1684         .cmd_rcgr = 0x1c084,
1685         .hid_width = 5,
1686         .mnd_width = 8,
1687         .parent_map = gcc_xo_gpll1_emclk_sleep_map,
1688         .freq_tbl = ftbl_gcc_ultaudio_lpaif_i2s_clk,
1689         .clkr.hw.init = &(struct clk_init_data){
1690                 .name = "ultaudio_lpaif_aux_i2s_clk_src",
1691                 .parent_data = gcc_xo_gpll1_esi2s_emclk_sleep_parent_data,
1692                 .num_parents = 5,
1693                 .ops = &clk_rcg2_ops,
1694         },
1695 };
1696
1697 static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk = {
1698         .halt_reg = 0x1c098,
1699         .clkr = {
1700                 .enable_reg = 0x1c098,
1701                 .enable_mask = BIT(0),
1702                 .hw.init = &(struct clk_init_data){
1703                         .name = "gcc_ultaudio_lpaif_aux_i2s_clk",
1704                         .parent_data = &(const struct clk_parent_data){
1705                                 .hw = &ultaudio_lpaif_aux_i2s_clk_src.clkr.hw,
1706                         },
1707                         .num_parents = 1,
1708                         .flags = CLK_SET_RATE_PARENT,
1709                         .ops = &clk_branch2_ops,
1710                 },
1711         },
1712 };
1713
1714 static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk[] = {
1715         F(19200000, P_XO, 1, 0, 0),
1716         { }
1717 };
1718
1719 static struct clk_rcg2 ultaudio_xo_clk_src = {
1720         .cmd_rcgr = 0x1c034,
1721         .hid_width = 5,
1722         .parent_map = gcc_xo_sleep_map,
1723         .freq_tbl = ftbl_gcc_ultaudio_xo_clk,
1724         .clkr.hw.init = &(struct clk_init_data){
1725                 .name = "ultaudio_xo_clk_src",
1726                 .parent_data = gcc_xo_sleep_parent_data,
1727                 .num_parents = 2,
1728                 .ops = &clk_rcg2_ops,
1729         },
1730 };
1731
1732 static struct clk_branch gcc_ultaudio_avsync_xo_clk = {
1733         .halt_reg = 0x1c04c,
1734         .clkr = {
1735                 .enable_reg = 0x1c04c,
1736                 .enable_mask = BIT(0),
1737                 .hw.init = &(struct clk_init_data){
1738                         .name = "gcc_ultaudio_avsync_xo_clk",
1739                         .parent_data = &(const struct clk_parent_data){
1740                                 .hw = &ultaudio_xo_clk_src.clkr.hw,
1741                         },
1742                         .num_parents = 1,
1743                         .flags = CLK_SET_RATE_PARENT,
1744                         .ops = &clk_branch2_ops,
1745                 },
1746         },
1747 };
1748
1749 static struct clk_branch gcc_ultaudio_stc_xo_clk = {
1750         .halt_reg = 0x1c050,
1751         .clkr = {
1752                 .enable_reg = 0x1c050,
1753                 .enable_mask = BIT(0),
1754                 .hw.init = &(struct clk_init_data){
1755                         .name = "gcc_ultaudio_stc_xo_clk",
1756                         .parent_data = &(const struct clk_parent_data){
1757                                 .hw = &ultaudio_xo_clk_src.clkr.hw,
1758                         },
1759                         .num_parents = 1,
1760                         .flags = CLK_SET_RATE_PARENT,
1761                         .ops = &clk_branch2_ops,
1762                 },
1763         },
1764 };
1765
1766 static const struct freq_tbl ftbl_codec_clk[] = {
1767         F(9600000, P_XO, 2, 0, 0),
1768         F(12288000, P_XO, 1, 16, 25),
1769         F(19200000, P_XO, 1, 0, 0),
1770         F(11289600, P_EXT_MCLK, 1, 0, 0),
1771         { }
1772 };
1773
1774 static struct clk_rcg2 codec_digcodec_clk_src = {
1775         .cmd_rcgr = 0x1c09c,
1776         .mnd_width = 8,
1777         .hid_width = 5,
1778         .parent_map = gcc_xo_gpll1_emclk_sleep_map,
1779         .freq_tbl = ftbl_codec_clk,
1780         .clkr.hw.init = &(struct clk_init_data){
1781                 .name = "codec_digcodec_clk_src",
1782                 .parent_data = gcc_xo_gpll1_emclk_sleep_parent_data,
1783                 .num_parents = 4,
1784                 .ops = &clk_rcg2_ops,
1785         },
1786 };
1787
1788 static struct clk_branch gcc_codec_digcodec_clk = {
1789         .halt_reg = 0x1c0b0,
1790         .clkr = {
1791                 .enable_reg = 0x1c0b0,
1792                 .enable_mask = BIT(0),
1793                 .hw.init = &(struct clk_init_data){
1794                         .name = "gcc_ultaudio_codec_digcodec_clk",
1795                         .parent_data = &(const struct clk_parent_data){
1796                                 .hw = &codec_digcodec_clk_src.clkr.hw,
1797                         },
1798                         .num_parents = 1,
1799                         .flags = CLK_SET_RATE_PARENT,
1800                         .ops = &clk_branch2_ops,
1801                 },
1802         },
1803 };
1804
1805 static struct clk_branch gcc_ultaudio_pcnoc_mport_clk = {
1806         .halt_reg = 0x1c000,
1807         .clkr = {
1808                 .enable_reg = 0x1c000,
1809                 .enable_mask = BIT(0),
1810                 .hw.init = &(struct clk_init_data){
1811                         .name = "gcc_ultaudio_pcnoc_mport_clk",
1812                         .parent_data = &(const struct clk_parent_data){
1813                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
1814                         },
1815                         .num_parents = 1,
1816                         .ops = &clk_branch2_ops,
1817                 },
1818         },
1819 };
1820
1821 static struct clk_branch gcc_ultaudio_pcnoc_sway_clk = {
1822         .halt_reg = 0x1c004,
1823         .clkr = {
1824                 .enable_reg = 0x1c004,
1825                 .enable_mask = BIT(0),
1826                 .hw.init = &(struct clk_init_data){
1827                         .name = "gcc_ultaudio_pcnoc_sway_clk",
1828                         .parent_data = &(const struct clk_parent_data){
1829                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
1830                         },
1831                         .num_parents = 1,
1832                         .ops = &clk_branch2_ops,
1833                 },
1834         },
1835 };
1836
1837 static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
1838         F(100000000, P_GPLL0, 8, 0, 0),
1839         F(160000000, P_GPLL0, 5, 0, 0),
1840         F(228570000, P_GPLL0, 3.5, 0, 0),
1841         { }
1842 };
1843
1844 static struct clk_rcg2 vcodec0_clk_src = {
1845         .cmd_rcgr = 0x4C000,
1846         .mnd_width = 8,
1847         .hid_width = 5,
1848         .parent_map = gcc_xo_gpll0_map,
1849         .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
1850         .clkr.hw.init = &(struct clk_init_data){
1851                 .name = "vcodec0_clk_src",
1852                 .parent_data = gcc_xo_gpll0_parent_data,
1853                 .num_parents = 2,
1854                 .ops = &clk_rcg2_ops,
1855         },
1856 };
1857
1858 static struct clk_branch gcc_blsp1_ahb_clk = {
1859         .halt_reg = 0x01008,
1860         .halt_check = BRANCH_HALT_VOTED,
1861         .clkr = {
1862                 .enable_reg = 0x45004,
1863                 .enable_mask = BIT(10),
1864                 .hw.init = &(struct clk_init_data){
1865                         .name = "gcc_blsp1_ahb_clk",
1866                         .parent_data = &(const struct clk_parent_data){
1867                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
1868                         },
1869                         .num_parents = 1,
1870                         .ops = &clk_branch2_ops,
1871                 },
1872         },
1873 };
1874
1875 static struct clk_branch gcc_blsp1_sleep_clk = {
1876         .halt_reg = 0x01004,
1877         .clkr = {
1878                 .enable_reg = 0x01004,
1879                 .enable_mask = BIT(0),
1880                 .hw.init = &(struct clk_init_data){
1881                         .name = "gcc_blsp1_sleep_clk",
1882                         .ops = &clk_branch2_ops,
1883                 },
1884         },
1885 };
1886
1887 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1888         .halt_reg = 0x02008,
1889         .clkr = {
1890                 .enable_reg = 0x02008,
1891                 .enable_mask = BIT(0),
1892                 .hw.init = &(struct clk_init_data){
1893                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1894                         .parent_data = &(const struct clk_parent_data){
1895                                 .hw = &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1896                         },
1897                         .num_parents = 1,
1898                         .flags = CLK_SET_RATE_PARENT,
1899                         .ops = &clk_branch2_ops,
1900                 },
1901         },
1902 };
1903
1904 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1905         .halt_reg = 0x02004,
1906         .clkr = {
1907                 .enable_reg = 0x02004,
1908                 .enable_mask = BIT(0),
1909                 .hw.init = &(struct clk_init_data){
1910                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1911                         .parent_data = &(const struct clk_parent_data){
1912                                 .hw = &blsp1_qup1_spi_apps_clk_src.clkr.hw,
1913                         },
1914                         .num_parents = 1,
1915                         .flags = CLK_SET_RATE_PARENT,
1916                         .ops = &clk_branch2_ops,
1917                 },
1918         },
1919 };
1920
1921 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1922         .halt_reg = 0x03010,
1923         .clkr = {
1924                 .enable_reg = 0x03010,
1925                 .enable_mask = BIT(0),
1926                 .hw.init = &(struct clk_init_data){
1927                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1928                         .parent_data = &(const struct clk_parent_data){
1929                                 .hw = &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1930                         },
1931                         .num_parents = 1,
1932                         .flags = CLK_SET_RATE_PARENT,
1933                         .ops = &clk_branch2_ops,
1934                 },
1935         },
1936 };
1937
1938 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1939         .halt_reg = 0x0300c,
1940         .clkr = {
1941                 .enable_reg = 0x0300c,
1942                 .enable_mask = BIT(0),
1943                 .hw.init = &(struct clk_init_data){
1944                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1945                         .parent_data = &(const struct clk_parent_data){
1946                                 .hw = &blsp1_qup2_spi_apps_clk_src.clkr.hw,
1947                         },
1948                         .num_parents = 1,
1949                         .flags = CLK_SET_RATE_PARENT,
1950                         .ops = &clk_branch2_ops,
1951                 },
1952         },
1953 };
1954
1955 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1956         .halt_reg = 0x04020,
1957         .clkr = {
1958                 .enable_reg = 0x04020,
1959                 .enable_mask = BIT(0),
1960                 .hw.init = &(struct clk_init_data){
1961                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1962                         .parent_data = &(const struct clk_parent_data){
1963                                 .hw = &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1964                         },
1965                         .num_parents = 1,
1966                         .flags = CLK_SET_RATE_PARENT,
1967                         .ops = &clk_branch2_ops,
1968                 },
1969         },
1970 };
1971
1972 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1973         .halt_reg = 0x0401c,
1974         .clkr = {
1975                 .enable_reg = 0x0401c,
1976                 .enable_mask = BIT(0),
1977                 .hw.init = &(struct clk_init_data){
1978                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1979                         .parent_data = &(const struct clk_parent_data){
1980                                 .hw = &blsp1_qup3_spi_apps_clk_src.clkr.hw,
1981                         },
1982                         .num_parents = 1,
1983                         .flags = CLK_SET_RATE_PARENT,
1984                         .ops = &clk_branch2_ops,
1985                 },
1986         },
1987 };
1988
1989 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1990         .halt_reg = 0x05020,
1991         .clkr = {
1992                 .enable_reg = 0x05020,
1993                 .enable_mask = BIT(0),
1994                 .hw.init = &(struct clk_init_data){
1995                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1996                         .parent_data = &(const struct clk_parent_data){
1997                                 .hw = &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
1998                         },
1999                         .num_parents = 1,
2000                         .flags = CLK_SET_RATE_PARENT,
2001                         .ops = &clk_branch2_ops,
2002                 },
2003         },
2004 };
2005
2006 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2007         .halt_reg = 0x0501c,
2008         .clkr = {
2009                 .enable_reg = 0x0501c,
2010                 .enable_mask = BIT(0),
2011                 .hw.init = &(struct clk_init_data){
2012                         .name = "gcc_blsp1_qup4_spi_apps_clk",
2013                         .parent_data = &(const struct clk_parent_data){
2014                                 .hw = &blsp1_qup4_spi_apps_clk_src.clkr.hw,
2015                         },
2016                         .num_parents = 1,
2017                         .flags = CLK_SET_RATE_PARENT,
2018                         .ops = &clk_branch2_ops,
2019                 },
2020         },
2021 };
2022
2023 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2024         .halt_reg = 0x06020,
2025         .clkr = {
2026                 .enable_reg = 0x06020,
2027                 .enable_mask = BIT(0),
2028                 .hw.init = &(struct clk_init_data){
2029                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
2030                         .parent_data = &(const struct clk_parent_data){
2031                                 .hw = &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
2032                         },
2033                         .num_parents = 1,
2034                         .flags = CLK_SET_RATE_PARENT,
2035                         .ops = &clk_branch2_ops,
2036                 },
2037         },
2038 };
2039
2040 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2041         .halt_reg = 0x0601c,
2042         .clkr = {
2043                 .enable_reg = 0x0601c,
2044                 .enable_mask = BIT(0),
2045                 .hw.init = &(struct clk_init_data){
2046                         .name = "gcc_blsp1_qup5_spi_apps_clk",
2047                         .parent_data = &(const struct clk_parent_data){
2048                                 .hw = &blsp1_qup5_spi_apps_clk_src.clkr.hw,
2049                         },
2050                         .num_parents = 1,
2051                         .flags = CLK_SET_RATE_PARENT,
2052                         .ops = &clk_branch2_ops,
2053                 },
2054         },
2055 };
2056
2057 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
2058         .halt_reg = 0x07020,
2059         .clkr = {
2060                 .enable_reg = 0x07020,
2061                 .enable_mask = BIT(0),
2062                 .hw.init = &(struct clk_init_data){
2063                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
2064                         .parent_data = &(const struct clk_parent_data){
2065                                 .hw = &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
2066                         },
2067                         .num_parents = 1,
2068                         .flags = CLK_SET_RATE_PARENT,
2069                         .ops = &clk_branch2_ops,
2070                 },
2071         },
2072 };
2073
2074 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2075         .halt_reg = 0x0701c,
2076         .clkr = {
2077                 .enable_reg = 0x0701c,
2078                 .enable_mask = BIT(0),
2079                 .hw.init = &(struct clk_init_data){
2080                         .name = "gcc_blsp1_qup6_spi_apps_clk",
2081                         .parent_data = &(const struct clk_parent_data){
2082                                 .hw = &blsp1_qup6_spi_apps_clk_src.clkr.hw,
2083                         },
2084                         .num_parents = 1,
2085                         .flags = CLK_SET_RATE_PARENT,
2086                         .ops = &clk_branch2_ops,
2087                 },
2088         },
2089 };
2090
2091 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2092         .halt_reg = 0x0203c,
2093         .clkr = {
2094                 .enable_reg = 0x0203c,
2095                 .enable_mask = BIT(0),
2096                 .hw.init = &(struct clk_init_data){
2097                         .name = "gcc_blsp1_uart1_apps_clk",
2098                         .parent_data = &(const struct clk_parent_data){
2099                                 .hw = &blsp1_uart1_apps_clk_src.clkr.hw,
2100                         },
2101                         .num_parents = 1,
2102                         .flags = CLK_SET_RATE_PARENT,
2103                         .ops = &clk_branch2_ops,
2104                 },
2105         },
2106 };
2107
2108 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2109         .halt_reg = 0x0302c,
2110         .clkr = {
2111                 .enable_reg = 0x0302c,
2112                 .enable_mask = BIT(0),
2113                 .hw.init = &(struct clk_init_data){
2114                         .name = "gcc_blsp1_uart2_apps_clk",
2115                         .parent_data = &(const struct clk_parent_data){
2116                                 .hw = &blsp1_uart2_apps_clk_src.clkr.hw,
2117                         },
2118                         .num_parents = 1,
2119                         .flags = CLK_SET_RATE_PARENT,
2120                         .ops = &clk_branch2_ops,
2121                 },
2122         },
2123 };
2124
2125 static struct clk_branch gcc_boot_rom_ahb_clk = {
2126         .halt_reg = 0x1300c,
2127         .halt_check = BRANCH_HALT_VOTED,
2128         .clkr = {
2129                 .enable_reg = 0x45004,
2130                 .enable_mask = BIT(7),
2131                 .hw.init = &(struct clk_init_data){
2132                         .name = "gcc_boot_rom_ahb_clk",
2133                         .parent_data = &(const struct clk_parent_data){
2134                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2135                         },
2136                         .num_parents = 1,
2137                         .ops = &clk_branch2_ops,
2138                 },
2139         },
2140 };
2141
2142 static struct clk_branch gcc_camss_cci_ahb_clk = {
2143         .halt_reg = 0x5101c,
2144         .clkr = {
2145                 .enable_reg = 0x5101c,
2146                 .enable_mask = BIT(0),
2147                 .hw.init = &(struct clk_init_data){
2148                         .name = "gcc_camss_cci_ahb_clk",
2149                         .parent_data = &(const struct clk_parent_data){
2150                                 .hw = &camss_ahb_clk_src.clkr.hw,
2151                         },
2152                         .num_parents = 1,
2153                         .flags = CLK_SET_RATE_PARENT,
2154                         .ops = &clk_branch2_ops,
2155                 },
2156         },
2157 };
2158
2159 static struct clk_branch gcc_camss_cci_clk = {
2160         .halt_reg = 0x51018,
2161         .clkr = {
2162                 .enable_reg = 0x51018,
2163                 .enable_mask = BIT(0),
2164                 .hw.init = &(struct clk_init_data){
2165                         .name = "gcc_camss_cci_clk",
2166                         .parent_data = &(const struct clk_parent_data){
2167                                 .hw = &cci_clk_src.clkr.hw,
2168                         },
2169                         .num_parents = 1,
2170                         .flags = CLK_SET_RATE_PARENT,
2171                         .ops = &clk_branch2_ops,
2172                 },
2173         },
2174 };
2175
2176 static struct clk_branch gcc_camss_csi0_ahb_clk = {
2177         .halt_reg = 0x4e040,
2178         .clkr = {
2179                 .enable_reg = 0x4e040,
2180                 .enable_mask = BIT(0),
2181                 .hw.init = &(struct clk_init_data){
2182                         .name = "gcc_camss_csi0_ahb_clk",
2183                         .parent_data = &(const struct clk_parent_data){
2184                                 .hw = &camss_ahb_clk_src.clkr.hw,
2185                         },
2186                         .num_parents = 1,
2187                         .flags = CLK_SET_RATE_PARENT,
2188                         .ops = &clk_branch2_ops,
2189                 },
2190         },
2191 };
2192
2193 static struct clk_branch gcc_camss_csi0_clk = {
2194         .halt_reg = 0x4e03c,
2195         .clkr = {
2196                 .enable_reg = 0x4e03c,
2197                 .enable_mask = BIT(0),
2198                 .hw.init = &(struct clk_init_data){
2199                         .name = "gcc_camss_csi0_clk",
2200                         .parent_data = &(const struct clk_parent_data){
2201                                 .hw = &csi0_clk_src.clkr.hw,
2202                         },
2203                         .num_parents = 1,
2204                         .flags = CLK_SET_RATE_PARENT,
2205                         .ops = &clk_branch2_ops,
2206                 },
2207         },
2208 };
2209
2210 static struct clk_branch gcc_camss_csi0phy_clk = {
2211         .halt_reg = 0x4e048,
2212         .clkr = {
2213                 .enable_reg = 0x4e048,
2214                 .enable_mask = BIT(0),
2215                 .hw.init = &(struct clk_init_data){
2216                         .name = "gcc_camss_csi0phy_clk",
2217                         .parent_data = &(const struct clk_parent_data){
2218                                 .hw = &csi0_clk_src.clkr.hw,
2219                         },
2220                         .num_parents = 1,
2221                         .flags = CLK_SET_RATE_PARENT,
2222                         .ops = &clk_branch2_ops,
2223                 },
2224         },
2225 };
2226
2227 static struct clk_branch gcc_camss_csi0pix_clk = {
2228         .halt_reg = 0x4e058,
2229         .clkr = {
2230                 .enable_reg = 0x4e058,
2231                 .enable_mask = BIT(0),
2232                 .hw.init = &(struct clk_init_data){
2233                         .name = "gcc_camss_csi0pix_clk",
2234                         .parent_data = &(const struct clk_parent_data){
2235                                 .hw = &csi0_clk_src.clkr.hw,
2236                         },
2237                         .num_parents = 1,
2238                         .flags = CLK_SET_RATE_PARENT,
2239                         .ops = &clk_branch2_ops,
2240                 },
2241         },
2242 };
2243
2244 static struct clk_branch gcc_camss_csi0rdi_clk = {
2245         .halt_reg = 0x4e050,
2246         .clkr = {
2247                 .enable_reg = 0x4e050,
2248                 .enable_mask = BIT(0),
2249                 .hw.init = &(struct clk_init_data){
2250                         .name = "gcc_camss_csi0rdi_clk",
2251                         .parent_data = &(const struct clk_parent_data){
2252                                 .hw = &csi0_clk_src.clkr.hw,
2253                         },
2254                         .num_parents = 1,
2255                         .flags = CLK_SET_RATE_PARENT,
2256                         .ops = &clk_branch2_ops,
2257                 },
2258         },
2259 };
2260
2261 static struct clk_branch gcc_camss_csi1_ahb_clk = {
2262         .halt_reg = 0x4f040,
2263         .clkr = {
2264                 .enable_reg = 0x4f040,
2265                 .enable_mask = BIT(0),
2266                 .hw.init = &(struct clk_init_data){
2267                         .name = "gcc_camss_csi1_ahb_clk",
2268                         .parent_data = &(const struct clk_parent_data){
2269                                 .hw = &camss_ahb_clk_src.clkr.hw,
2270                         },
2271                         .num_parents = 1,
2272                         .flags = CLK_SET_RATE_PARENT,
2273                         .ops = &clk_branch2_ops,
2274                 },
2275         },
2276 };
2277
2278 static struct clk_branch gcc_camss_csi1_clk = {
2279         .halt_reg = 0x4f03c,
2280         .clkr = {
2281                 .enable_reg = 0x4f03c,
2282                 .enable_mask = BIT(0),
2283                 .hw.init = &(struct clk_init_data){
2284                         .name = "gcc_camss_csi1_clk",
2285                         .parent_data = &(const struct clk_parent_data){
2286                                 .hw = &csi1_clk_src.clkr.hw,
2287                         },
2288                         .num_parents = 1,
2289                         .flags = CLK_SET_RATE_PARENT,
2290                         .ops = &clk_branch2_ops,
2291                 },
2292         },
2293 };
2294
2295 static struct clk_branch gcc_camss_csi1phy_clk = {
2296         .halt_reg = 0x4f048,
2297         .clkr = {
2298                 .enable_reg = 0x4f048,
2299                 .enable_mask = BIT(0),
2300                 .hw.init = &(struct clk_init_data){
2301                         .name = "gcc_camss_csi1phy_clk",
2302                         .parent_data = &(const struct clk_parent_data){
2303                                 .hw = &csi1_clk_src.clkr.hw,
2304                         },
2305                         .num_parents = 1,
2306                         .flags = CLK_SET_RATE_PARENT,
2307                         .ops = &clk_branch2_ops,
2308                 },
2309         },
2310 };
2311
2312 static struct clk_branch gcc_camss_csi1pix_clk = {
2313         .halt_reg = 0x4f058,
2314         .clkr = {
2315                 .enable_reg = 0x4f058,
2316                 .enable_mask = BIT(0),
2317                 .hw.init = &(struct clk_init_data){
2318                         .name = "gcc_camss_csi1pix_clk",
2319                         .parent_data = &(const struct clk_parent_data){
2320                                 .hw = &csi1_clk_src.clkr.hw,
2321                         },
2322                         .num_parents = 1,
2323                         .flags = CLK_SET_RATE_PARENT,
2324                         .ops = &clk_branch2_ops,
2325                 },
2326         },
2327 };
2328
2329 static struct clk_branch gcc_camss_csi1rdi_clk = {
2330         .halt_reg = 0x4f050,
2331         .clkr = {
2332                 .enable_reg = 0x4f050,
2333                 .enable_mask = BIT(0),
2334                 .hw.init = &(struct clk_init_data){
2335                         .name = "gcc_camss_csi1rdi_clk",
2336                         .parent_data = &(const struct clk_parent_data){
2337                                 .hw = &csi1_clk_src.clkr.hw,
2338                         },
2339                         .num_parents = 1,
2340                         .flags = CLK_SET_RATE_PARENT,
2341                         .ops = &clk_branch2_ops,
2342                 },
2343         },
2344 };
2345
2346 static struct clk_branch gcc_camss_csi_vfe0_clk = {
2347         .halt_reg = 0x58050,
2348         .clkr = {
2349                 .enable_reg = 0x58050,
2350                 .enable_mask = BIT(0),
2351                 .hw.init = &(struct clk_init_data){
2352                         .name = "gcc_camss_csi_vfe0_clk",
2353                         .parent_data = &(const struct clk_parent_data){
2354                                 .hw = &vfe0_clk_src.clkr.hw,
2355                         },
2356                         .num_parents = 1,
2357                         .flags = CLK_SET_RATE_PARENT,
2358                         .ops = &clk_branch2_ops,
2359                 },
2360         },
2361 };
2362
2363 static struct clk_branch gcc_camss_gp0_clk = {
2364         .halt_reg = 0x54018,
2365         .clkr = {
2366                 .enable_reg = 0x54018,
2367                 .enable_mask = BIT(0),
2368                 .hw.init = &(struct clk_init_data){
2369                         .name = "gcc_camss_gp0_clk",
2370                         .parent_data = &(const struct clk_parent_data){
2371                                 .hw = &camss_gp0_clk_src.clkr.hw,
2372                         },
2373                         .num_parents = 1,
2374                         .flags = CLK_SET_RATE_PARENT,
2375                         .ops = &clk_branch2_ops,
2376                 },
2377         },
2378 };
2379
2380 static struct clk_branch gcc_camss_gp1_clk = {
2381         .halt_reg = 0x55018,
2382         .clkr = {
2383                 .enable_reg = 0x55018,
2384                 .enable_mask = BIT(0),
2385                 .hw.init = &(struct clk_init_data){
2386                         .name = "gcc_camss_gp1_clk",
2387                         .parent_data = &(const struct clk_parent_data){
2388                                 .hw = &camss_gp1_clk_src.clkr.hw,
2389                         },
2390                         .num_parents = 1,
2391                         .flags = CLK_SET_RATE_PARENT,
2392                         .ops = &clk_branch2_ops,
2393                 },
2394         },
2395 };
2396
2397 static struct clk_branch gcc_camss_ispif_ahb_clk = {
2398         .halt_reg = 0x50004,
2399         .clkr = {
2400                 .enable_reg = 0x50004,
2401                 .enable_mask = BIT(0),
2402                 .hw.init = &(struct clk_init_data){
2403                         .name = "gcc_camss_ispif_ahb_clk",
2404                         .parent_data = &(const struct clk_parent_data){
2405                                 .hw = &camss_ahb_clk_src.clkr.hw,
2406                         },
2407                         .num_parents = 1,
2408                         .flags = CLK_SET_RATE_PARENT,
2409                         .ops = &clk_branch2_ops,
2410                 },
2411         },
2412 };
2413
2414 static struct clk_branch gcc_camss_jpeg0_clk = {
2415         .halt_reg = 0x57020,
2416         .clkr = {
2417                 .enable_reg = 0x57020,
2418                 .enable_mask = BIT(0),
2419                 .hw.init = &(struct clk_init_data){
2420                         .name = "gcc_camss_jpeg0_clk",
2421                         .parent_data = &(const struct clk_parent_data){
2422                                 .hw = &jpeg0_clk_src.clkr.hw,
2423                         },
2424                         .num_parents = 1,
2425                         .flags = CLK_SET_RATE_PARENT,
2426                         .ops = &clk_branch2_ops,
2427                 },
2428         },
2429 };
2430
2431 static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2432         .halt_reg = 0x57024,
2433         .clkr = {
2434                 .enable_reg = 0x57024,
2435                 .enable_mask = BIT(0),
2436                 .hw.init = &(struct clk_init_data){
2437                         .name = "gcc_camss_jpeg_ahb_clk",
2438                         .parent_data = &(const struct clk_parent_data){
2439                                 .hw = &camss_ahb_clk_src.clkr.hw,
2440                         },
2441                         .num_parents = 1,
2442                         .flags = CLK_SET_RATE_PARENT,
2443                         .ops = &clk_branch2_ops,
2444                 },
2445         },
2446 };
2447
2448 static struct clk_branch gcc_camss_jpeg_axi_clk = {
2449         .halt_reg = 0x57028,
2450         .clkr = {
2451                 .enable_reg = 0x57028,
2452                 .enable_mask = BIT(0),
2453                 .hw.init = &(struct clk_init_data){
2454                         .name = "gcc_camss_jpeg_axi_clk",
2455                         .parent_data = &(const struct clk_parent_data){
2456                                 .hw = &system_noc_bfdcd_clk_src.clkr.hw,
2457                         },
2458                         .num_parents = 1,
2459                         .flags = CLK_SET_RATE_PARENT,
2460                         .ops = &clk_branch2_ops,
2461                 },
2462         },
2463 };
2464
2465 static struct clk_branch gcc_camss_mclk0_clk = {
2466         .halt_reg = 0x52018,
2467         .clkr = {
2468                 .enable_reg = 0x52018,
2469                 .enable_mask = BIT(0),
2470                 .hw.init = &(struct clk_init_data){
2471                         .name = "gcc_camss_mclk0_clk",
2472                         .parent_data = &(const struct clk_parent_data){
2473                                 .hw = &mclk0_clk_src.clkr.hw,
2474                         },
2475                         .num_parents = 1,
2476                         .flags = CLK_SET_RATE_PARENT,
2477                         .ops = &clk_branch2_ops,
2478                 },
2479         },
2480 };
2481
2482 static struct clk_branch gcc_camss_mclk1_clk = {
2483         .halt_reg = 0x53018,
2484         .clkr = {
2485                 .enable_reg = 0x53018,
2486                 .enable_mask = BIT(0),
2487                 .hw.init = &(struct clk_init_data){
2488                         .name = "gcc_camss_mclk1_clk",
2489                         .parent_data = &(const struct clk_parent_data){
2490                                 .hw = &mclk1_clk_src.clkr.hw,
2491                         },
2492                         .num_parents = 1,
2493                         .flags = CLK_SET_RATE_PARENT,
2494                         .ops = &clk_branch2_ops,
2495                 },
2496         },
2497 };
2498
2499 static struct clk_branch gcc_camss_micro_ahb_clk = {
2500         .halt_reg = 0x5600c,
2501         .clkr = {
2502                 .enable_reg = 0x5600c,
2503                 .enable_mask = BIT(0),
2504                 .hw.init = &(struct clk_init_data){
2505                         .name = "gcc_camss_micro_ahb_clk",
2506                         .parent_data = &(const struct clk_parent_data){
2507                                 .hw = &camss_ahb_clk_src.clkr.hw,
2508                         },
2509                         .num_parents = 1,
2510                         .flags = CLK_SET_RATE_PARENT,
2511                         .ops = &clk_branch2_ops,
2512                 },
2513         },
2514 };
2515
2516 static struct clk_branch gcc_camss_csi0phytimer_clk = {
2517         .halt_reg = 0x4e01c,
2518         .clkr = {
2519                 .enable_reg = 0x4e01c,
2520                 .enable_mask = BIT(0),
2521                 .hw.init = &(struct clk_init_data){
2522                         .name = "gcc_camss_csi0phytimer_clk",
2523                         .parent_data = &(const struct clk_parent_data){
2524                                 .hw = &csi0phytimer_clk_src.clkr.hw,
2525                         },
2526                         .num_parents = 1,
2527                         .flags = CLK_SET_RATE_PARENT,
2528                         .ops = &clk_branch2_ops,
2529                 },
2530         },
2531 };
2532
2533 static struct clk_branch gcc_camss_csi1phytimer_clk = {
2534         .halt_reg = 0x4f01c,
2535         .clkr = {
2536                 .enable_reg = 0x4f01c,
2537                 .enable_mask = BIT(0),
2538                 .hw.init = &(struct clk_init_data){
2539                         .name = "gcc_camss_csi1phytimer_clk",
2540                         .parent_data = &(const struct clk_parent_data){
2541                                 .hw = &csi1phytimer_clk_src.clkr.hw,
2542                         },
2543                         .num_parents = 1,
2544                         .flags = CLK_SET_RATE_PARENT,
2545                         .ops = &clk_branch2_ops,
2546                 },
2547         },
2548 };
2549
2550 static struct clk_branch gcc_camss_ahb_clk = {
2551         .halt_reg = 0x5a014,
2552         .clkr = {
2553                 .enable_reg = 0x5a014,
2554                 .enable_mask = BIT(0),
2555                 .hw.init = &(struct clk_init_data){
2556                         .name = "gcc_camss_ahb_clk",
2557                         .parent_data = &(const struct clk_parent_data){
2558                                 .hw = &camss_ahb_clk_src.clkr.hw,
2559                         },
2560                         .num_parents = 1,
2561                         .flags = CLK_SET_RATE_PARENT,
2562                         .ops = &clk_branch2_ops,
2563                 },
2564         },
2565 };
2566
2567 static struct clk_branch gcc_camss_top_ahb_clk = {
2568         .halt_reg = 0x56004,
2569         .clkr = {
2570                 .enable_reg = 0x56004,
2571                 .enable_mask = BIT(0),
2572                 .hw.init = &(struct clk_init_data){
2573                         .name = "gcc_camss_top_ahb_clk",
2574                         .parent_data = &(const struct clk_parent_data){
2575                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2576                         },
2577                         .num_parents = 1,
2578                         .flags = CLK_SET_RATE_PARENT,
2579                         .ops = &clk_branch2_ops,
2580                 },
2581         },
2582 };
2583
2584 static struct clk_branch gcc_camss_cpp_ahb_clk = {
2585         .halt_reg = 0x58040,
2586         .clkr = {
2587                 .enable_reg = 0x58040,
2588                 .enable_mask = BIT(0),
2589                 .hw.init = &(struct clk_init_data){
2590                         .name = "gcc_camss_cpp_ahb_clk",
2591                         .parent_data = &(const struct clk_parent_data){
2592                                 .hw = &camss_ahb_clk_src.clkr.hw,
2593                         },
2594                         .num_parents = 1,
2595                         .flags = CLK_SET_RATE_PARENT,
2596                         .ops = &clk_branch2_ops,
2597                 },
2598         },
2599 };
2600
2601 static struct clk_branch gcc_camss_cpp_clk = {
2602         .halt_reg = 0x5803c,
2603         .clkr = {
2604                 .enable_reg = 0x5803c,
2605                 .enable_mask = BIT(0),
2606                 .hw.init = &(struct clk_init_data){
2607                         .name = "gcc_camss_cpp_clk",
2608                         .parent_data = &(const struct clk_parent_data){
2609                                 .hw = &cpp_clk_src.clkr.hw,
2610                         },
2611                         .num_parents = 1,
2612                         .flags = CLK_SET_RATE_PARENT,
2613                         .ops = &clk_branch2_ops,
2614                 },
2615         },
2616 };
2617
2618 static struct clk_branch gcc_camss_vfe0_clk = {
2619         .halt_reg = 0x58038,
2620         .clkr = {
2621                 .enable_reg = 0x58038,
2622                 .enable_mask = BIT(0),
2623                 .hw.init = &(struct clk_init_data){
2624                         .name = "gcc_camss_vfe0_clk",
2625                         .parent_data = &(const struct clk_parent_data){
2626                                 .hw = &vfe0_clk_src.clkr.hw,
2627                         },
2628                         .num_parents = 1,
2629                         .flags = CLK_SET_RATE_PARENT,
2630                         .ops = &clk_branch2_ops,
2631                 },
2632         },
2633 };
2634
2635 static struct clk_branch gcc_camss_vfe_ahb_clk = {
2636         .halt_reg = 0x58044,
2637         .clkr = {
2638                 .enable_reg = 0x58044,
2639                 .enable_mask = BIT(0),
2640                 .hw.init = &(struct clk_init_data){
2641                         .name = "gcc_camss_vfe_ahb_clk",
2642                         .parent_data = &(const struct clk_parent_data){
2643                                 .hw = &camss_ahb_clk_src.clkr.hw,
2644                         },
2645                         .num_parents = 1,
2646                         .flags = CLK_SET_RATE_PARENT,
2647                         .ops = &clk_branch2_ops,
2648                 },
2649         },
2650 };
2651
2652 static struct clk_branch gcc_camss_vfe_axi_clk = {
2653         .halt_reg = 0x58048,
2654         .clkr = {
2655                 .enable_reg = 0x58048,
2656                 .enable_mask = BIT(0),
2657                 .hw.init = &(struct clk_init_data){
2658                         .name = "gcc_camss_vfe_axi_clk",
2659                         .parent_data = &(const struct clk_parent_data){
2660                                 .hw = &system_noc_bfdcd_clk_src.clkr.hw,
2661                         },
2662                         .num_parents = 1,
2663                         .flags = CLK_SET_RATE_PARENT,
2664                         .ops = &clk_branch2_ops,
2665                 },
2666         },
2667 };
2668
2669 static struct clk_branch gcc_crypto_ahb_clk = {
2670         .halt_reg = 0x16024,
2671         .halt_check = BRANCH_HALT_VOTED,
2672         .clkr = {
2673                 .enable_reg = 0x45004,
2674                 .enable_mask = BIT(0),
2675                 .hw.init = &(struct clk_init_data){
2676                         .name = "gcc_crypto_ahb_clk",
2677                         .parent_data = &(const struct clk_parent_data){
2678                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2679                         },
2680                         .num_parents = 1,
2681                         .flags = CLK_SET_RATE_PARENT,
2682                         .ops = &clk_branch2_ops,
2683                 },
2684         },
2685 };
2686
2687 static struct clk_branch gcc_crypto_axi_clk = {
2688         .halt_reg = 0x16020,
2689         .halt_check = BRANCH_HALT_VOTED,
2690         .clkr = {
2691                 .enable_reg = 0x45004,
2692                 .enable_mask = BIT(1),
2693                 .hw.init = &(struct clk_init_data){
2694                         .name = "gcc_crypto_axi_clk",
2695                         .parent_data = &(const struct clk_parent_data){
2696                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2697                         },
2698                         .num_parents = 1,
2699                         .flags = CLK_SET_RATE_PARENT,
2700                         .ops = &clk_branch2_ops,
2701                 },
2702         },
2703 };
2704
2705 static struct clk_branch gcc_crypto_clk = {
2706         .halt_reg = 0x1601c,
2707         .halt_check = BRANCH_HALT_VOTED,
2708         .clkr = {
2709                 .enable_reg = 0x45004,
2710                 .enable_mask = BIT(2),
2711                 .hw.init = &(struct clk_init_data){
2712                         .name = "gcc_crypto_clk",
2713                         .parent_data = &(const struct clk_parent_data){
2714                                 .hw = &crypto_clk_src.clkr.hw,
2715                         },
2716                         .num_parents = 1,
2717                         .flags = CLK_SET_RATE_PARENT,
2718                         .ops = &clk_branch2_ops,
2719                 },
2720         },
2721 };
2722
2723 static struct clk_branch gcc_oxili_gmem_clk = {
2724         .halt_reg = 0x59024,
2725         .clkr = {
2726                 .enable_reg = 0x59024,
2727                 .enable_mask = BIT(0),
2728                 .hw.init = &(struct clk_init_data){
2729                         .name = "gcc_oxili_gmem_clk",
2730                         .parent_data = &(const struct clk_parent_data){
2731                                 .hw = &gfx3d_clk_src.clkr.hw,
2732                         },
2733                         .num_parents = 1,
2734                         .flags = CLK_SET_RATE_PARENT,
2735                         .ops = &clk_branch2_ops,
2736                 },
2737         },
2738 };
2739
2740 static struct clk_branch gcc_gp1_clk = {
2741         .halt_reg = 0x08000,
2742         .clkr = {
2743                 .enable_reg = 0x08000,
2744                 .enable_mask = BIT(0),
2745                 .hw.init = &(struct clk_init_data){
2746                         .name = "gcc_gp1_clk",
2747                         .parent_data = &(const struct clk_parent_data){
2748                                 .hw = &gp1_clk_src.clkr.hw,
2749                         },
2750                         .num_parents = 1,
2751                         .flags = CLK_SET_RATE_PARENT,
2752                         .ops = &clk_branch2_ops,
2753                 },
2754         },
2755 };
2756
2757 static struct clk_branch gcc_gp2_clk = {
2758         .halt_reg = 0x09000,
2759         .clkr = {
2760                 .enable_reg = 0x09000,
2761                 .enable_mask = BIT(0),
2762                 .hw.init = &(struct clk_init_data){
2763                         .name = "gcc_gp2_clk",
2764                         .parent_data = &(const struct clk_parent_data){
2765                                 .hw = &gp2_clk_src.clkr.hw,
2766                         },
2767                         .num_parents = 1,
2768                         .flags = CLK_SET_RATE_PARENT,
2769                         .ops = &clk_branch2_ops,
2770                 },
2771         },
2772 };
2773
2774 static struct clk_branch gcc_gp3_clk = {
2775         .halt_reg = 0x0a000,
2776         .clkr = {
2777                 .enable_reg = 0x0a000,
2778                 .enable_mask = BIT(0),
2779                 .hw.init = &(struct clk_init_data){
2780                         .name = "gcc_gp3_clk",
2781                         .parent_data = &(const struct clk_parent_data){
2782                                 .hw = &gp3_clk_src.clkr.hw,
2783                         },
2784                         .num_parents = 1,
2785                         .flags = CLK_SET_RATE_PARENT,
2786                         .ops = &clk_branch2_ops,
2787                 },
2788         },
2789 };
2790
2791 static struct clk_branch gcc_mdss_ahb_clk = {
2792         .halt_reg = 0x4d07c,
2793         .clkr = {
2794                 .enable_reg = 0x4d07c,
2795                 .enable_mask = BIT(0),
2796                 .hw.init = &(struct clk_init_data){
2797                         .name = "gcc_mdss_ahb_clk",
2798                         .parent_data = &(const struct clk_parent_data){
2799                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2800                         },
2801                         .num_parents = 1,
2802                         .flags = CLK_SET_RATE_PARENT,
2803                         .ops = &clk_branch2_ops,
2804                 },
2805         },
2806 };
2807
2808 static struct clk_branch gcc_mdss_axi_clk = {
2809         .halt_reg = 0x4d080,
2810         .clkr = {
2811                 .enable_reg = 0x4d080,
2812                 .enable_mask = BIT(0),
2813                 .hw.init = &(struct clk_init_data){
2814                         .name = "gcc_mdss_axi_clk",
2815                         .parent_data = &(const struct clk_parent_data){
2816                                 .hw = &system_noc_bfdcd_clk_src.clkr.hw,
2817                         },
2818                         .num_parents = 1,
2819                         .flags = CLK_SET_RATE_PARENT,
2820                         .ops = &clk_branch2_ops,
2821                 },
2822         },
2823 };
2824
2825 static struct clk_branch gcc_mdss_byte0_clk = {
2826         .halt_reg = 0x4d094,
2827         .clkr = {
2828                 .enable_reg = 0x4d094,
2829                 .enable_mask = BIT(0),
2830                 .hw.init = &(struct clk_init_data){
2831                         .name = "gcc_mdss_byte0_clk",
2832                         .parent_data = &(const struct clk_parent_data){
2833                                 .hw = &byte0_clk_src.clkr.hw,
2834                         },
2835                         .num_parents = 1,
2836                         .flags = CLK_SET_RATE_PARENT,
2837                         .ops = &clk_branch2_ops,
2838                 },
2839         },
2840 };
2841
2842 static struct clk_branch gcc_mdss_byte1_clk = {
2843         .halt_reg = 0x4d0a0,
2844         .clkr = {
2845                 .enable_reg = 0x4d0a0,
2846                 .enable_mask = BIT(0),
2847                 .hw.init = &(struct clk_init_data){
2848                         .name = "gcc_mdss_byte1_clk",
2849                         .parent_data = &(const struct clk_parent_data){
2850                                 .hw = &byte1_clk_src.clkr.hw,
2851                         },
2852                         .num_parents = 1,
2853                         .flags = CLK_SET_RATE_PARENT,
2854                         .ops = &clk_branch2_ops,
2855                 },
2856         },
2857 };
2858
2859 static struct clk_branch gcc_mdss_esc0_clk = {
2860         .halt_reg = 0x4d098,
2861         .clkr = {
2862                 .enable_reg = 0x4d098,
2863                 .enable_mask = BIT(0),
2864                 .hw.init = &(struct clk_init_data){
2865                         .name = "gcc_mdss_esc0_clk",
2866                         .parent_data = &(const struct clk_parent_data){
2867                                 .hw = &esc0_clk_src.clkr.hw,
2868                         },
2869                         .num_parents = 1,
2870                         .flags = CLK_SET_RATE_PARENT,
2871                         .ops = &clk_branch2_ops,
2872                 },
2873         },
2874 };
2875
2876 static struct clk_branch gcc_mdss_esc1_clk = {
2877         .halt_reg = 0x4d09c,
2878         .clkr = {
2879                 .enable_reg = 0x4d09c,
2880                 .enable_mask = BIT(0),
2881                 .hw.init = &(struct clk_init_data){
2882                         .name = "gcc_mdss_esc1_clk",
2883                         .parent_data = &(const struct clk_parent_data){
2884                                 .hw = &esc1_clk_src.clkr.hw,
2885                         },
2886                         .num_parents = 1,
2887                         .flags = CLK_SET_RATE_PARENT,
2888                         .ops = &clk_branch2_ops,
2889                 },
2890         },
2891 };
2892
2893 static struct clk_branch gcc_mdss_mdp_clk = {
2894         .halt_reg = 0x4D088,
2895         .clkr = {
2896                 .enable_reg = 0x4D088,
2897                 .enable_mask = BIT(0),
2898                 .hw.init = &(struct clk_init_data){
2899                         .name = "gcc_mdss_mdp_clk",
2900                         .parent_data = &(const struct clk_parent_data){
2901                                 .hw = &mdp_clk_src.clkr.hw,
2902                         },
2903                         .num_parents = 1,
2904                         .flags = CLK_SET_RATE_PARENT,
2905                         .ops = &clk_branch2_ops,
2906                 },
2907         },
2908 };
2909
2910 static struct clk_branch gcc_mdss_pclk0_clk = {
2911         .halt_reg = 0x4d084,
2912         .clkr = {
2913                 .enable_reg = 0x4d084,
2914                 .enable_mask = BIT(0),
2915                 .hw.init = &(struct clk_init_data){
2916                         .name = "gcc_mdss_pclk0_clk",
2917                         .parent_data = &(const struct clk_parent_data){
2918                                 .hw = &pclk0_clk_src.clkr.hw,
2919                         },
2920                         .num_parents = 1,
2921                         .flags = CLK_SET_RATE_PARENT,
2922                         .ops = &clk_branch2_ops,
2923                 },
2924         },
2925 };
2926
2927 static struct clk_branch gcc_mdss_pclk1_clk = {
2928         .halt_reg = 0x4d0a4,
2929         .clkr = {
2930                 .enable_reg = 0x4d0a4,
2931                 .enable_mask = BIT(0),
2932                 .hw.init = &(struct clk_init_data){
2933                         .name = "gcc_mdss_pclk1_clk",
2934                         .parent_data = &(const struct clk_parent_data){
2935                                 .hw = &pclk1_clk_src.clkr.hw,
2936                         },
2937                         .num_parents = 1,
2938                         .flags = CLK_SET_RATE_PARENT,
2939                         .ops = &clk_branch2_ops,
2940                 },
2941         },
2942 };
2943
2944 static struct clk_branch gcc_mdss_vsync_clk = {
2945         .halt_reg = 0x4d090,
2946         .clkr = {
2947                 .enable_reg = 0x4d090,
2948                 .enable_mask = BIT(0),
2949                 .hw.init = &(struct clk_init_data){
2950                         .name = "gcc_mdss_vsync_clk",
2951                         .parent_data = &(const struct clk_parent_data){
2952                                 .hw = &vsync_clk_src.clkr.hw,
2953                         },
2954                         .num_parents = 1,
2955                         .flags = CLK_SET_RATE_PARENT,
2956                         .ops = &clk_branch2_ops,
2957                 },
2958         },
2959 };
2960
2961 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2962         .halt_reg = 0x49000,
2963         .clkr = {
2964                 .enable_reg = 0x49000,
2965                 .enable_mask = BIT(0),
2966                 .hw.init = &(struct clk_init_data){
2967                         .name = "gcc_mss_cfg_ahb_clk",
2968                         .parent_data = &(const struct clk_parent_data){
2969                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
2970                         },
2971                         .num_parents = 1,
2972                         .flags = CLK_SET_RATE_PARENT,
2973                         .ops = &clk_branch2_ops,
2974                 },
2975         },
2976 };
2977
2978 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
2979         .halt_reg = 0x49004,
2980         .clkr = {
2981                 .enable_reg = 0x49004,
2982                 .enable_mask = BIT(0),
2983                 .hw.init = &(struct clk_init_data){
2984                         .name = "gcc_mss_q6_bimc_axi_clk",
2985                         .parent_data = &(const struct clk_parent_data){
2986                                 .hw = &bimc_ddr_clk_src.clkr.hw,
2987                         },
2988                         .num_parents = 1,
2989                         .flags = CLK_SET_RATE_PARENT,
2990                         .ops = &clk_branch2_ops,
2991                 },
2992         },
2993 };
2994
2995 static struct clk_branch gcc_oxili_ahb_clk = {
2996         .halt_reg = 0x59028,
2997         .clkr = {
2998                 .enable_reg = 0x59028,
2999                 .enable_mask = BIT(0),
3000                 .hw.init = &(struct clk_init_data){
3001                         .name = "gcc_oxili_ahb_clk",
3002                         .parent_data = &(const struct clk_parent_data){
3003                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3004                         },
3005                         .num_parents = 1,
3006                         .flags = CLK_SET_RATE_PARENT,
3007                         .ops = &clk_branch2_ops,
3008                 },
3009         },
3010 };
3011
3012 static struct clk_branch gcc_oxili_gfx3d_clk = {
3013         .halt_reg = 0x59020,
3014         .clkr = {
3015                 .enable_reg = 0x59020,
3016                 .enable_mask = BIT(0),
3017                 .hw.init = &(struct clk_init_data){
3018                         .name = "gcc_oxili_gfx3d_clk",
3019                         .parent_data = &(const struct clk_parent_data){
3020                                 .hw = &gfx3d_clk_src.clkr.hw,
3021                         },
3022                         .num_parents = 1,
3023                         .flags = CLK_SET_RATE_PARENT,
3024                         .ops = &clk_branch2_ops,
3025                 },
3026         },
3027 };
3028
3029 static struct clk_branch gcc_pdm2_clk = {
3030         .halt_reg = 0x4400c,
3031         .clkr = {
3032                 .enable_reg = 0x4400c,
3033                 .enable_mask = BIT(0),
3034                 .hw.init = &(struct clk_init_data){
3035                         .name = "gcc_pdm2_clk",
3036                         .parent_data = &(const struct clk_parent_data){
3037                                 .hw = &pdm2_clk_src.clkr.hw,
3038                         },
3039                         .num_parents = 1,
3040                         .flags = CLK_SET_RATE_PARENT,
3041                         .ops = &clk_branch2_ops,
3042                 },
3043         },
3044 };
3045
3046 static struct clk_branch gcc_pdm_ahb_clk = {
3047         .halt_reg = 0x44004,
3048         .clkr = {
3049                 .enable_reg = 0x44004,
3050                 .enable_mask = BIT(0),
3051                 .hw.init = &(struct clk_init_data){
3052                         .name = "gcc_pdm_ahb_clk",
3053                         .parent_data = &(const struct clk_parent_data){
3054                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3055                         },
3056                         .num_parents = 1,
3057                         .flags = CLK_SET_RATE_PARENT,
3058                         .ops = &clk_branch2_ops,
3059                 },
3060         },
3061 };
3062
3063 static struct clk_branch gcc_prng_ahb_clk = {
3064         .halt_reg = 0x13004,
3065         .halt_check = BRANCH_HALT_VOTED,
3066         .clkr = {
3067                 .enable_reg = 0x45004,
3068                 .enable_mask = BIT(8),
3069                 .hw.init = &(struct clk_init_data){
3070                         .name = "gcc_prng_ahb_clk",
3071                         .parent_data = &(const struct clk_parent_data){
3072                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3073                         },
3074                         .num_parents = 1,
3075                         .ops = &clk_branch2_ops,
3076                 },
3077         },
3078 };
3079
3080 static struct clk_branch gcc_sdcc1_ahb_clk = {
3081         .halt_reg = 0x4201c,
3082         .clkr = {
3083                 .enable_reg = 0x4201c,
3084                 .enable_mask = BIT(0),
3085                 .hw.init = &(struct clk_init_data){
3086                         .name = "gcc_sdcc1_ahb_clk",
3087                         .parent_data = &(const struct clk_parent_data){
3088                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3089                         },
3090                         .num_parents = 1,
3091                         .flags = CLK_SET_RATE_PARENT,
3092                         .ops = &clk_branch2_ops,
3093                 },
3094         },
3095 };
3096
3097 static struct clk_branch gcc_sdcc1_apps_clk = {
3098         .halt_reg = 0x42018,
3099         .clkr = {
3100                 .enable_reg = 0x42018,
3101                 .enable_mask = BIT(0),
3102                 .hw.init = &(struct clk_init_data){
3103                         .name = "gcc_sdcc1_apps_clk",
3104                         .parent_data = &(const struct clk_parent_data){
3105                                 .hw = &sdcc1_apps_clk_src.clkr.hw,
3106                         },
3107                         .num_parents = 1,
3108                         .flags = CLK_SET_RATE_PARENT,
3109                         .ops = &clk_branch2_ops,
3110                 },
3111         },
3112 };
3113
3114 static struct clk_branch gcc_sdcc2_ahb_clk = {
3115         .halt_reg = 0x4301c,
3116         .clkr = {
3117                 .enable_reg = 0x4301c,
3118                 .enable_mask = BIT(0),
3119                 .hw.init = &(struct clk_init_data){
3120                         .name = "gcc_sdcc2_ahb_clk",
3121                         .parent_data = &(const struct clk_parent_data){
3122                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3123                         },
3124                         .num_parents = 1,
3125                         .flags = CLK_SET_RATE_PARENT,
3126                         .ops = &clk_branch2_ops,
3127                 },
3128         },
3129 };
3130
3131 static struct clk_branch gcc_sdcc2_apps_clk = {
3132         .halt_reg = 0x43018,
3133         .clkr = {
3134                 .enable_reg = 0x43018,
3135                 .enable_mask = BIT(0),
3136                 .hw.init = &(struct clk_init_data){
3137                         .name = "gcc_sdcc2_apps_clk",
3138                         .parent_data = &(const struct clk_parent_data){
3139                                 .hw = &sdcc2_apps_clk_src.clkr.hw,
3140                         },
3141                         .num_parents = 1,
3142                         .flags = CLK_SET_RATE_PARENT,
3143                         .ops = &clk_branch2_ops,
3144                 },
3145         },
3146 };
3147
3148 static struct clk_branch gcc_apss_tcu_clk = {
3149         .halt_reg = 0x12018,
3150         .halt_check = BRANCH_HALT_VOTED,
3151         .clkr = {
3152                 .enable_reg = 0x4500c,
3153                 .enable_mask = BIT(1),
3154                 .hw.init = &(struct clk_init_data){
3155                         .name = "gcc_apss_tcu_clk",
3156                         .parent_data = &(const struct clk_parent_data){
3157                                 .hw = &bimc_ddr_clk_src.clkr.hw,
3158                         },
3159                         .num_parents = 1,
3160                         .ops = &clk_branch2_ops,
3161                 },
3162         },
3163 };
3164
3165 static struct clk_branch gcc_gfx_tcu_clk = {
3166         .halt_reg = 0x12020,
3167         .halt_check = BRANCH_HALT_VOTED,
3168         .clkr = {
3169                 .enable_reg = 0x4500c,
3170                 .enable_mask = BIT(2),
3171                 .hw.init = &(struct clk_init_data){
3172                         .name = "gcc_gfx_tcu_clk",
3173                         .parent_data = &(const struct clk_parent_data){
3174                                 .hw = &bimc_ddr_clk_src.clkr.hw,
3175                         },
3176                         .num_parents = 1,
3177                         .ops = &clk_branch2_ops,
3178                 },
3179         },
3180 };
3181
3182 static struct clk_branch gcc_gfx_tbu_clk = {
3183         .halt_reg = 0x12010,
3184         .halt_check = BRANCH_HALT_VOTED,
3185         .clkr = {
3186                 .enable_reg = 0x4500c,
3187                 .enable_mask = BIT(3),
3188                 .hw.init = &(struct clk_init_data){
3189                         .name = "gcc_gfx_tbu_clk",
3190                         .parent_data = &(const struct clk_parent_data){
3191                                 .hw = &bimc_ddr_clk_src.clkr.hw,
3192                         },
3193                         .num_parents = 1,
3194                         .ops = &clk_branch2_ops,
3195                 },
3196         },
3197 };
3198
3199 static struct clk_branch gcc_mdp_tbu_clk = {
3200         .halt_reg = 0x1201c,
3201         .halt_check = BRANCH_HALT_VOTED,
3202         .clkr = {
3203                 .enable_reg = 0x4500c,
3204                 .enable_mask = BIT(4),
3205                 .hw.init = &(struct clk_init_data){
3206                         .name = "gcc_mdp_tbu_clk",
3207                         .parent_data = &(const struct clk_parent_data){
3208                                 .hw = &system_noc_bfdcd_clk_src.clkr.hw,
3209                         },
3210                         .num_parents = 1,
3211                         .flags = CLK_SET_RATE_PARENT,
3212                         .ops = &clk_branch2_ops,
3213                 },
3214         },
3215 };
3216
3217 static struct clk_branch gcc_venus_tbu_clk = {
3218         .halt_reg = 0x12014,
3219         .halt_check = BRANCH_HALT_VOTED,
3220         .clkr = {
3221                 .enable_reg = 0x4500c,
3222                 .enable_mask = BIT(5),
3223                 .hw.init = &(struct clk_init_data){
3224                         .name = "gcc_venus_tbu_clk",
3225                         .parent_data = &(const struct clk_parent_data){
3226                                 .hw = &system_noc_bfdcd_clk_src.clkr.hw,
3227                         },
3228                         .num_parents = 1,
3229                         .flags = CLK_SET_RATE_PARENT,
3230                         .ops = &clk_branch2_ops,
3231                 },
3232         },
3233 };
3234
3235 static struct clk_branch gcc_vfe_tbu_clk = {
3236         .halt_reg = 0x1203c,
3237         .halt_check = BRANCH_HALT_VOTED,
3238         .clkr = {
3239                 .enable_reg = 0x4500c,
3240                 .enable_mask = BIT(9),
3241                 .hw.init = &(struct clk_init_data){
3242                         .name = "gcc_vfe_tbu_clk",
3243                         .parent_data = &(const struct clk_parent_data){
3244                                 .hw = &system_noc_bfdcd_clk_src.clkr.hw,
3245                         },
3246                         .num_parents = 1,
3247                         .flags = CLK_SET_RATE_PARENT,
3248                         .ops = &clk_branch2_ops,
3249                 },
3250         },
3251 };
3252
3253 static struct clk_branch gcc_jpeg_tbu_clk = {
3254         .halt_reg = 0x12034,
3255         .halt_check = BRANCH_HALT_VOTED,
3256         .clkr = {
3257                 .enable_reg = 0x4500c,
3258                 .enable_mask = BIT(10),
3259                 .hw.init = &(struct clk_init_data){
3260                         .name = "gcc_jpeg_tbu_clk",
3261                         .parent_data = &(const struct clk_parent_data){
3262                                 .hw = &system_noc_bfdcd_clk_src.clkr.hw,
3263                         },
3264                         .num_parents = 1,
3265                         .flags = CLK_SET_RATE_PARENT,
3266                         .ops = &clk_branch2_ops,
3267                 },
3268         },
3269 };
3270
3271 static struct clk_branch gcc_smmu_cfg_clk = {
3272         .halt_reg = 0x12038,
3273         .halt_check = BRANCH_HALT_VOTED,
3274         .clkr = {
3275                 .enable_reg = 0x4500c,
3276                 .enable_mask = BIT(12),
3277                 .hw.init = &(struct clk_init_data){
3278                         .name = "gcc_smmu_cfg_clk",
3279                         .parent_data = &(const struct clk_parent_data){
3280                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3281                         },
3282                         .num_parents = 1,
3283                         .flags = CLK_SET_RATE_PARENT,
3284                         .ops = &clk_branch2_ops,
3285                 },
3286         },
3287 };
3288
3289 static struct clk_branch gcc_gtcu_ahb_clk = {
3290         .halt_reg = 0x12044,
3291         .halt_check = BRANCH_HALT_VOTED,
3292         .clkr = {
3293                 .enable_reg = 0x4500c,
3294                 .enable_mask = BIT(13),
3295                 .hw.init = &(struct clk_init_data){
3296                         .name = "gcc_gtcu_ahb_clk",
3297                         .parent_data = &(const struct clk_parent_data){
3298                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3299                         },
3300                         .num_parents = 1,
3301                         .flags = CLK_SET_RATE_PARENT,
3302                         .ops = &clk_branch2_ops,
3303                 },
3304         },
3305 };
3306
3307 static struct clk_branch gcc_cpp_tbu_clk = {
3308         .halt_reg = 0x12040,
3309         .halt_check = BRANCH_HALT_VOTED,
3310         .clkr = {
3311                 .enable_reg = 0x4500c,
3312                 .enable_mask = BIT(14),
3313                 .hw.init = &(struct clk_init_data){
3314                         .name = "gcc_cpp_tbu_clk",
3315                         .parent_data = &(const struct clk_parent_data){
3316                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3317                         },
3318                         .num_parents = 1,
3319                         .flags = CLK_SET_RATE_PARENT,
3320                         .ops = &clk_branch2_ops,
3321                 },
3322         },
3323 };
3324
3325 static struct clk_branch gcc_mdp_rt_tbu_clk = {
3326         .halt_reg = 0x1201c,
3327         .halt_check = BRANCH_HALT_VOTED,
3328         .clkr = {
3329                 .enable_reg = 0x4500c,
3330                 .enable_mask = BIT(15),
3331                 .hw.init = &(struct clk_init_data){
3332                         .name = "gcc_mdp_rt_tbu_clk",
3333                         .parent_data = &(const struct clk_parent_data){
3334                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3335                         },
3336                         .num_parents = 1,
3337                         .flags = CLK_SET_RATE_PARENT,
3338                         .ops = &clk_branch2_ops,
3339                 },
3340         },
3341 };
3342
3343 static struct clk_branch gcc_bimc_gfx_clk = {
3344         .halt_reg = 0x31024,
3345         .clkr = {
3346                 .enable_reg = 0x31024,
3347                 .enable_mask = BIT(0),
3348                 .hw.init = &(struct clk_init_data){
3349                         .name = "gcc_bimc_gfx_clk",
3350                         .parent_data = &(const struct clk_parent_data){
3351                                 .hw = &bimc_gpu_clk_src.clkr.hw,
3352                         },
3353                         .num_parents = 1,
3354                         .flags = CLK_SET_RATE_PARENT,
3355                         .ops = &clk_branch2_ops,
3356                 },
3357         },
3358 };
3359
3360 static struct clk_branch gcc_bimc_gpu_clk = {
3361         .halt_reg = 0x31040,
3362         .clkr = {
3363                 .enable_reg = 0x31040,
3364                 .enable_mask = BIT(0),
3365                 .hw.init = &(struct clk_init_data){
3366                         .name = "gcc_bimc_gpu_clk",
3367                         .parent_data = &(const struct clk_parent_data){
3368                                 .hw = &bimc_gpu_clk_src.clkr.hw,
3369                         },
3370                         .num_parents = 1,
3371                         .flags = CLK_SET_RATE_PARENT,
3372                         .ops = &clk_branch2_ops,
3373                 },
3374         },
3375 };
3376
3377 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
3378         .halt_reg = 0x4102c,
3379         .clkr = {
3380                 .enable_reg = 0x4102c,
3381                 .enable_mask = BIT(0),
3382                 .hw.init = &(struct clk_init_data){
3383                         .name = "gcc_usb2a_phy_sleep_clk",
3384                         .ops = &clk_branch2_ops,
3385                 },
3386         },
3387 };
3388
3389 static struct clk_branch gcc_usb_fs_ahb_clk = {
3390         .halt_reg = 0x3f008,
3391         .clkr = {
3392                 .enable_reg = 0x3f008,
3393                 .enable_mask = BIT(0),
3394                 .hw.init = &(struct clk_init_data){
3395                         .name = "gcc_usb_fs_ahb_clk",
3396                         .parent_data = &(const struct clk_parent_data){
3397                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3398                         },
3399                         .num_parents = 1,
3400                         .flags = CLK_SET_RATE_PARENT,
3401                         .ops = &clk_branch2_ops,
3402                 },
3403         },
3404 };
3405
3406 static struct clk_branch gcc_usb_fs_ic_clk = {
3407         .halt_reg = 0x3f030,
3408         .clkr = {
3409                 .enable_reg = 0x3f030,
3410                 .enable_mask = BIT(0),
3411                 .hw.init = &(struct clk_init_data){
3412                         .name = "gcc_usb_fs_ic_clk",
3413                         .parent_data = &(const struct clk_parent_data){
3414                                 .hw = &usb_fs_ic_clk_src.clkr.hw,
3415                         },
3416                         .num_parents = 1,
3417                         .flags = CLK_SET_RATE_PARENT,
3418                         .ops = &clk_branch2_ops,
3419                 },
3420         },
3421 };
3422
3423 static struct clk_branch gcc_usb_fs_system_clk = {
3424         .halt_reg = 0x3f004,
3425         .clkr = {
3426                 .enable_reg = 0x3f004,
3427                 .enable_mask = BIT(0),
3428                 .hw.init = &(struct clk_init_data){
3429                         .name = "gcc_usb_fs_system_clk",
3430                         .parent_data = &(const struct clk_parent_data){
3431                                 .hw = &usb_fs_system_clk_src.clkr.hw,
3432                         },
3433                         .num_parents = 1,
3434                         .flags = CLK_SET_RATE_PARENT,
3435                         .ops = &clk_branch2_ops,
3436                 },
3437         },
3438 };
3439
3440 static struct clk_branch gcc_usb_hs_ahb_clk = {
3441         .halt_reg = 0x41008,
3442         .clkr = {
3443                 .enable_reg = 0x41008,
3444                 .enable_mask = BIT(0),
3445                 .hw.init = &(struct clk_init_data){
3446                         .name = "gcc_usb_hs_ahb_clk",
3447                         .parent_data = &(const struct clk_parent_data){
3448                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3449                         },
3450                         .num_parents = 1,
3451                         .flags = CLK_SET_RATE_PARENT,
3452                         .ops = &clk_branch2_ops,
3453                 },
3454         },
3455 };
3456
3457 static struct clk_branch gcc_usb_hs_system_clk = {
3458         .halt_reg = 0x41004,
3459         .clkr = {
3460                 .enable_reg = 0x41004,
3461                 .enable_mask = BIT(0),
3462                 .hw.init = &(struct clk_init_data){
3463                         .name = "gcc_usb_hs_system_clk",
3464                         .parent_data = &(const struct clk_parent_data){
3465                                 .hw = &usb_hs_system_clk_src.clkr.hw,
3466                         },
3467                         .num_parents = 1,
3468                         .flags = CLK_SET_RATE_PARENT,
3469                         .ops = &clk_branch2_ops,
3470                 },
3471         },
3472 };
3473
3474 static struct clk_branch gcc_venus0_ahb_clk = {
3475         .halt_reg = 0x4c020,
3476         .clkr = {
3477                 .enable_reg = 0x4c020,
3478                 .enable_mask = BIT(0),
3479                 .hw.init = &(struct clk_init_data){
3480                         .name = "gcc_venus0_ahb_clk",
3481                         .parent_data = &(const struct clk_parent_data){
3482                                 .hw = &pcnoc_bfdcd_clk_src.clkr.hw,
3483                         },
3484                         .num_parents = 1,
3485                         .flags = CLK_SET_RATE_PARENT,
3486                         .ops = &clk_branch2_ops,
3487                 },
3488         },
3489 };
3490
3491 static struct clk_branch gcc_venus0_axi_clk = {
3492         .halt_reg = 0x4c024,
3493         .clkr = {
3494                 .enable_reg = 0x4c024,
3495                 .enable_mask = BIT(0),
3496                 .hw.init = &(struct clk_init_data){
3497                         .name = "gcc_venus0_axi_clk",
3498                         .parent_data = &(const struct clk_parent_data){
3499                                 .hw = &system_noc_bfdcd_clk_src.clkr.hw,
3500                         },
3501                         .num_parents = 1,
3502                         .flags = CLK_SET_RATE_PARENT,
3503                         .ops = &clk_branch2_ops,
3504                 },
3505         },
3506 };
3507
3508 static struct clk_branch gcc_venus0_vcodec0_clk = {
3509         .halt_reg = 0x4c01c,
3510         .clkr = {
3511                 .enable_reg = 0x4c01c,
3512                 .enable_mask = BIT(0),
3513                 .hw.init = &(struct clk_init_data){
3514                         .name = "gcc_venus0_vcodec0_clk",
3515                         .parent_data = &(const struct clk_parent_data){
3516                                 .hw = &vcodec0_clk_src.clkr.hw,
3517                         },
3518                         .num_parents = 1,
3519                         .flags = CLK_SET_RATE_PARENT,
3520                         .ops = &clk_branch2_ops,
3521                 },
3522         },
3523 };
3524
3525 static struct clk_branch gcc_venus0_core0_vcodec0_clk = {
3526         .halt_reg = 0x4c02c,
3527         .clkr = {
3528                 .enable_reg = 0x4c02c,
3529                 .enable_mask = BIT(0),
3530                 .hw.init = &(struct clk_init_data){
3531                         .name = "gcc_venus0_core0_vcodec0_clk",
3532                         .parent_data = &(const struct clk_parent_data){
3533                                 .hw = &vcodec0_clk_src.clkr.hw,
3534                         },
3535                         .num_parents = 1,
3536                         .flags = CLK_SET_RATE_PARENT,
3537                         .ops = &clk_branch2_ops,
3538                 },
3539         },
3540 };
3541
3542 static struct clk_branch gcc_venus0_core1_vcodec0_clk = {
3543         .halt_reg = 0x4c034,
3544         .clkr = {
3545                 .enable_reg = 0x4c034,
3546                 .enable_mask = BIT(0),
3547                 .hw.init = &(struct clk_init_data){
3548                         .name = "gcc_venus0_core1_vcodec0_clk",
3549                         .parent_data = &(const struct clk_parent_data){
3550                                 .hw = &vcodec0_clk_src.clkr.hw,
3551                         },
3552                         .num_parents = 1,
3553                         .flags = CLK_SET_RATE_PARENT,
3554                         .ops = &clk_branch2_ops,
3555                 },
3556         },
3557 };
3558
3559 static struct clk_branch gcc_oxili_timer_clk = {
3560         .halt_reg = 0x59040,
3561         .clkr = {
3562                 .enable_reg = 0x59040,
3563                 .enable_mask = BIT(0),
3564                 .hw.init = &(struct clk_init_data){
3565                         .name = "gcc_oxili_timer_clk",
3566                         .ops = &clk_branch2_ops,
3567                 },
3568         },
3569 };
3570
3571 static struct gdsc venus_gdsc = {
3572         .gdscr = 0x4c018,
3573         .pd = {
3574                 .name = "venus",
3575         },
3576         .pwrsts = PWRSTS_OFF_ON,
3577 };
3578
3579 static struct gdsc mdss_gdsc = {
3580         .gdscr = 0x4d078,
3581         .pd = {
3582                 .name = "mdss",
3583         },
3584         .pwrsts = PWRSTS_OFF_ON,
3585 };
3586
3587 static struct gdsc jpeg_gdsc = {
3588         .gdscr = 0x5701c,
3589         .pd = {
3590                 .name = "jpeg",
3591         },
3592         .pwrsts = PWRSTS_OFF_ON,
3593 };
3594
3595 static struct gdsc vfe_gdsc = {
3596         .gdscr = 0x58034,
3597         .pd = {
3598                 .name = "vfe",
3599         },
3600         .pwrsts = PWRSTS_OFF_ON,
3601 };
3602
3603 static struct gdsc oxili_gdsc = {
3604         .gdscr = 0x5901c,
3605         .pd = {
3606                 .name = "oxili",
3607         },
3608         .pwrsts = PWRSTS_OFF_ON,
3609 };
3610
3611 static struct gdsc venus_core0_gdsc = {
3612         .gdscr = 0x4c028,
3613         .pd = {
3614                 .name = "venus_core0",
3615         },
3616         .pwrsts = PWRSTS_OFF_ON,
3617 };
3618
3619 static struct gdsc venus_core1_gdsc = {
3620         .gdscr = 0x4c030,
3621         .pd = {
3622                 .name = "venus_core1",
3623         },
3624         .pwrsts = PWRSTS_OFF_ON,
3625 };
3626
3627 static struct clk_regmap *gcc_msm8939_clocks[] = {
3628         [GPLL0] = &gpll0.clkr,
3629         [GPLL0_VOTE] = &gpll0_vote,
3630         [BIMC_PLL] = &bimc_pll.clkr,
3631         [BIMC_PLL_VOTE] = &bimc_pll_vote,
3632         [GPLL1] = &gpll1.clkr,
3633         [GPLL1_VOTE] = &gpll1_vote,
3634         [GPLL2] = &gpll2.clkr,
3635         [GPLL2_VOTE] = &gpll2_vote,
3636         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3637         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3638         [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
3639         [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3640         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3641         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3642         [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3643         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3644         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3645         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3646         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3647         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3648         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3649         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3650         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3651         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3652         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3653         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3654         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3655         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3656         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3657         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3658         [CCI_CLK_SRC] = &cci_clk_src.clkr,
3659         [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3660         [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3661         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3662         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3663         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3664         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3665         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3666         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3667         [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
3668         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3669         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3670         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3671         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3672         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3673         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3674         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3675         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3676         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3677         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3678         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3679         [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
3680         [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3681         [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3682         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3683         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3684         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3685         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3686         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3687         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3688         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3689         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3690         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3691         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3692         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3693         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3694         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3695         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3696         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3697         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3698         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3699         [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3700         [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3701         [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3702         [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3703         [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
3704         [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3705         [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3706         [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3707         [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3708         [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
3709         [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3710         [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3711         [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3712         [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3713         [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3714         [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3715         [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
3716         [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3717         [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3718         [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3719         [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3720         [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3721         [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3722         [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3723         [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
3724         [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3725         [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3726         [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3727         [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3728         [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
3729         [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
3730         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3731         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3732         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3733         [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
3734         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3735         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3736         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3737         [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
3738         [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
3739         [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
3740         [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
3741         [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
3742         [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
3743         [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
3744         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3745         [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
3746         [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
3747         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3748         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3749         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3750         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3751         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3752         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3753         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3754         [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
3755         [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
3756         [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
3757         [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
3758         [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
3759         [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
3760         [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3761         [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3762         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3763         [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
3764         [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
3765         [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
3766         [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
3767         [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
3768         [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
3769         [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
3770         [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3771         [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
3772         [ULTAUDIO_AHBFABRIC_CLK_SRC] = &ultaudio_ahbfabric_clk_src.clkr,
3773         [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC] = &ultaudio_lpaif_pri_i2s_clk_src.clkr,
3774         [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC] = &ultaudio_lpaif_sec_i2s_clk_src.clkr,
3775         [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC] = &ultaudio_lpaif_aux_i2s_clk_src.clkr,
3776         [ULTAUDIO_XO_CLK_SRC] = &ultaudio_xo_clk_src.clkr,
3777         [CODEC_DIGCODEC_CLK_SRC] = &codec_digcodec_clk_src.clkr,
3778         [GCC_ULTAUDIO_PCNOC_MPORT_CLK] = &gcc_ultaudio_pcnoc_mport_clk.clkr,
3779         [GCC_ULTAUDIO_PCNOC_SWAY_CLK] = &gcc_ultaudio_pcnoc_sway_clk.clkr,
3780         [GCC_ULTAUDIO_AVSYNC_XO_CLK] = &gcc_ultaudio_avsync_xo_clk.clkr,
3781         [GCC_ULTAUDIO_STC_XO_CLK] = &gcc_ultaudio_stc_xo_clk.clkr,
3782         [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_clk.clkr,
3783         [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk.clkr,
3784         [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK] = &gcc_ultaudio_lpaif_pri_i2s_clk.clkr,
3785         [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK] = &gcc_ultaudio_lpaif_sec_i2s_clk.clkr,
3786         [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK] = &gcc_ultaudio_lpaif_aux_i2s_clk.clkr,
3787         [GCC_CODEC_DIGCODEC_CLK] = &gcc_codec_digcodec_clk.clkr,
3788         [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3789         [GPLL3] = &gpll3.clkr,
3790         [GPLL3_VOTE] = &gpll3_vote,
3791         [GPLL4] = &gpll4.clkr,
3792         [GPLL4_VOTE] = &gpll4_vote,
3793         [GPLL5] = &gpll5.clkr,
3794         [GPLL5_VOTE] = &gpll5_vote,
3795         [GPLL6] = &gpll6.clkr,
3796         [GPLL6_VOTE] = &gpll6_vote,
3797         [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3798         [GCC_MDSS_BYTE1_CLK] = &gcc_mdss_byte1_clk.clkr,
3799         [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3800         [GCC_MDSS_ESC1_CLK] = &gcc_mdss_esc1_clk.clkr,
3801         [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3802         [GCC_MDSS_PCLK1_CLK] = &gcc_mdss_pclk1_clk.clkr,
3803         [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
3804         [GCC_CPP_TBU_CLK] = &gcc_cpp_tbu_clk.clkr,
3805         [GCC_MDP_RT_TBU_CLK] = &gcc_mdp_rt_tbu_clk.clkr,
3806         [USB_FS_SYSTEM_CLK_SRC] = &usb_fs_system_clk_src.clkr,
3807         [USB_FS_IC_CLK_SRC] = &usb_fs_ic_clk_src.clkr,
3808         [GCC_USB_FS_AHB_CLK] = &gcc_usb_fs_ahb_clk.clkr,
3809         [GCC_USB_FS_IC_CLK] = &gcc_usb_fs_ic_clk.clkr,
3810         [GCC_USB_FS_SYSTEM_CLK] = &gcc_usb_fs_system_clk.clkr,
3811         [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr,
3812         [GCC_VENUS0_CORE1_VCODEC0_CLK] = &gcc_venus0_core1_vcodec0_clk.clkr,
3813         [GCC_OXILI_TIMER_CLK] = &gcc_oxili_timer_clk.clkr,
3814 };
3815
3816 static struct gdsc *gcc_msm8939_gdscs[] = {
3817         [VENUS_GDSC] = &venus_gdsc,
3818         [MDSS_GDSC] = &mdss_gdsc,
3819         [JPEG_GDSC] = &jpeg_gdsc,
3820         [VFE_GDSC] = &vfe_gdsc,
3821         [OXILI_GDSC] = &oxili_gdsc,
3822         [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
3823         [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
3824 };
3825
3826 static const struct qcom_reset_map gcc_msm8939_resets[] = {
3827         [GCC_BLSP1_BCR] = { 0x01000 },
3828         [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3829         [GCC_BLSP1_UART1_BCR] = { 0x02038 },
3830         [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3831         [GCC_BLSP1_UART2_BCR] = { 0x03028 },
3832         [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3833         [GCC_BLSP1_UART3_BCR] = { 0x04038 },
3834         [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3835         [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3836         [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3837         [GCC_IMEM_BCR] = { 0x0e000 },
3838         [GCC_SMMU_BCR] = { 0x12000 },
3839         [GCC_APSS_TCU_BCR] = { 0x12050 },
3840         [GCC_SMMU_XPU_BCR] = { 0x12054 },
3841         [GCC_PCNOC_TBU_BCR] = { 0x12058 },
3842         [GCC_PRNG_BCR] = { 0x13000 },
3843         [GCC_BOOT_ROM_BCR] = { 0x13008 },
3844         [GCC_CRYPTO_BCR] = { 0x16000 },
3845         [GCC_SEC_CTRL_BCR] = { 0x1a000 },
3846         [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3847         [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3848         [GCC_DEHR_BCR] = { 0x1f000 },
3849         [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3850         [GCC_PCNOC_BCR] = { 0x27018 },
3851         [GCC_TCSR_BCR] = { 0x28000 },
3852         [GCC_QDSS_BCR] = { 0x29000 },
3853         [GCC_DCD_BCR] = { 0x2a000 },
3854         [GCC_MSG_RAM_BCR] = { 0x2b000 },
3855         [GCC_MPM_BCR] = { 0x2c000 },
3856         [GCC_SPMI_BCR] = { 0x2e000 },
3857         [GCC_SPDM_BCR] = { 0x2f000 },
3858         [GCC_MM_SPDM_BCR] = { 0x2f024 },
3859         [GCC_BIMC_BCR] = { 0x31000 },
3860         [GCC_RBCPR_BCR] = { 0x33000 },
3861         [GCC_TLMM_BCR] = { 0x34000 },
3862         [GCC_CAMSS_CSI2_BCR] = { 0x3c038 },
3863         [GCC_CAMSS_CSI2PHY_BCR] = { 0x3c044 },
3864         [GCC_CAMSS_CSI2RDI_BCR] = { 0x3c04c },
3865         [GCC_CAMSS_CSI2PIX_BCR] = { 0x3c054 },
3866         [GCC_USB_FS_BCR] = { 0x3f000 },
3867         [GCC_USB_HS_BCR] = { 0x41000 },
3868         [GCC_USB2A_PHY_BCR] = { 0x41028 },
3869         [GCC_SDCC1_BCR] = { 0x42000 },
3870         [GCC_SDCC2_BCR] = { 0x43000 },
3871         [GCC_PDM_BCR] = { 0x44000 },
3872         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3873         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3874         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3875         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3876         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3877         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3878         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3879         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3880         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3881         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3882         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3883         [GCC_MMSS_BCR] = { 0x4b000 },
3884         [GCC_VENUS0_BCR] = { 0x4c014 },
3885         [GCC_MDSS_BCR] = { 0x4d074 },
3886         [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3887         [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3888         [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3889         [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3890         [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3891         [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3892         [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3893         [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3894         [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3895         [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3896         [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3897         [GCC_BLSP1_QUP4_SPI_APPS_CBCR] = { 0x0501c },
3898         [GCC_CAMSS_CCI_BCR] = { 0x51014 },
3899         [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3900         [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3901         [GCC_CAMSS_GP0_BCR] = { 0x54014 },
3902         [GCC_CAMSS_GP1_BCR] = { 0x55014 },
3903         [GCC_CAMSS_TOP_BCR] = { 0x56000 },
3904         [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3905         [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3906         [GCC_CAMSS_VFE_BCR] = { 0x58030 },
3907         [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3908         [GCC_OXILI_BCR] = { 0x59018 },
3909         [GCC_GMEM_BCR] = { 0x5902c },
3910         [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3911         [GCC_CAMSS_MCLK2_BCR] = { 0x5c014 },
3912         [GCC_MDP_TBU_BCR] = { 0x62000 },
3913         [GCC_GFX_TBU_BCR] = { 0x63000 },
3914         [GCC_GFX_TCU_BCR] = { 0x64000 },
3915         [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3916         [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3917         [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3918         [GCC_GTCU_AHB_BCR] = { 0x68000 },
3919         [GCC_SMMU_CFG_BCR] = { 0x69000 },
3920         [GCC_VFE_TBU_BCR] = { 0x6a000 },
3921         [GCC_VENUS_TBU_BCR] = { 0x6b000 },
3922         [GCC_JPEG_TBU_BCR] = { 0x6c000 },
3923         [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3924         [GCC_CPP_TBU_BCR] = { 0x6e000 },
3925         [GCC_MDP_RT_TBU_BCR] = { 0x6f000 },
3926         [GCC_SMMU_CATS_BCR] = { 0x7c000 },
3927 };
3928
3929 static const struct regmap_config gcc_msm8939_regmap_config = {
3930         .reg_bits       = 32,
3931         .reg_stride     = 4,
3932         .val_bits       = 32,
3933         .max_register   = 0x80000,
3934         .fast_io        = true,
3935 };
3936
3937 static const struct qcom_cc_desc gcc_msm8939_desc = {
3938         .config = &gcc_msm8939_regmap_config,
3939         .clks = gcc_msm8939_clocks,
3940         .num_clks = ARRAY_SIZE(gcc_msm8939_clocks),
3941         .resets = gcc_msm8939_resets,
3942         .num_resets = ARRAY_SIZE(gcc_msm8939_resets),
3943         .gdscs = gcc_msm8939_gdscs,
3944         .num_gdscs = ARRAY_SIZE(gcc_msm8939_gdscs),
3945 };
3946
3947 static const struct of_device_id gcc_msm8939_match_table[] = {
3948         { .compatible = "qcom,gcc-msm8939" },
3949         { }
3950 };
3951 MODULE_DEVICE_TABLE(of, gcc_msm8939_match_table);
3952
3953 static int gcc_msm8939_probe(struct platform_device *pdev)
3954 {
3955         struct regmap *regmap;
3956
3957         regmap = qcom_cc_map(pdev, &gcc_msm8939_desc);
3958         if (IS_ERR(regmap))
3959                 return PTR_ERR(regmap);
3960
3961         clk_pll_configure_sr_hpm_lp(&gpll3, regmap, &gpll3_config, true);
3962         clk_pll_configure_sr_hpm_lp(&gpll4, regmap, &gpll4_config, true);
3963
3964         return qcom_cc_really_probe(pdev, &gcc_msm8939_desc, regmap);
3965 }
3966
3967 static struct platform_driver gcc_msm8939_driver = {
3968         .probe          = gcc_msm8939_probe,
3969         .driver         = {
3970                 .name   = "gcc-msm8939",
3971                 .of_match_table = gcc_msm8939_match_table,
3972         },
3973 };
3974
3975 static int __init gcc_msm8939_init(void)
3976 {
3977         return platform_driver_register(&gcc_msm8939_driver);
3978 }
3979 core_initcall(gcc_msm8939_init);
3980
3981 static void __exit gcc_msm8939_exit(void)
3982 {
3983         platform_driver_unregister(&gcc_msm8939_driver);
3984 }
3985 module_exit(gcc_msm8939_exit);
3986
3987 MODULE_DESCRIPTION("Qualcomm GCC MSM8939 Driver");
3988 MODULE_LICENSE("GPL v2");