drivers/clk/qcom/clk-alpha-pll.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved.
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/export.h>
   9 #include <linux/clk-provider.h>
  10 #include <linux/regmap.h>
  11 #include <linux/delay.h>
  12
  13 #include "clk-alpha-pll.h"
  14 #include "common.h"
  15
  16 #define PLL_MODE(p)             ((p)->offset + 0x0)
  17 # define PLL_OUTCTRL            BIT(0)
  18 # define PLL_BYPASSNL           BIT(1)
  19 # define PLL_RESET_N            BIT(2)
  20 # define PLL_OFFLINE_REQ        BIT(7)
  21 # define PLL_LOCK_COUNT_SHIFT   8
  22 # define PLL_LOCK_COUNT_MASK    0x3f
  23 # define PLL_BIAS_COUNT_SHIFT   14
  24 # define PLL_BIAS_COUNT_MASK    0x3f
  25 # define PLL_VOTE_FSM_ENA       BIT(20)
  26 # define PLL_FSM_ENA            BIT(20)
  27 # define PLL_VOTE_FSM_RESET     BIT(21)
  28 # define PLL_UPDATE             BIT(22)
  29 # define PLL_UPDATE_BYPASS      BIT(23)
  30 # define PLL_FSM_LEGACY_MODE    BIT(24)
  31 # define PLL_OFFLINE_ACK        BIT(28)
  32 # define ALPHA_PLL_ACK_LATCH    BIT(29)
  33 # define PLL_ACTIVE_FLAG        BIT(30)
  34 # define PLL_LOCK_DET           BIT(31)
  35
  36 #define PLL_L_VAL(p)            ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
  37 #define PLL_CAL_L_VAL(p)        ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
  38 #define PLL_ALPHA_VAL(p)        ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
  39 #define PLL_ALPHA_VAL_U(p)      ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
  40
  41 #define PLL_USER_CTL(p)         ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
  42 # define PLL_POST_DIV_SHIFT     8
  43 # define PLL_POST_DIV_MASK(p)   GENMASK((p)->width, 0)
  44 # define PLL_ALPHA_EN           BIT(24)
  45 # define PLL_ALPHA_MODE         BIT(25)
  46 # define PLL_VCO_SHIFT          20
  47 # define PLL_VCO_MASK           0x3
  48
  49 #define PLL_USER_CTL_U(p)       ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
  50 #define PLL_USER_CTL_U1(p)      ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
  51
  52 #define PLL_CONFIG_CTL(p)       ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
  53 #define PLL_CONFIG_CTL_U(p)     ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
  54 #define PLL_CONFIG_CTL_U1(p)    ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
  55 #define PLL_TEST_CTL(p)         ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
  56 #define PLL_TEST_CTL_U(p)       ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
  57 #define PLL_TEST_CTL_U1(p)     ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
  58 #define PLL_STATUS(p)           ((p)->offset + (p)->regs[PLL_OFF_STATUS])
  59 #define PLL_OPMODE(p)           ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
  60 #define PLL_FRAC(p)             ((p)->offset + (p)->regs[PLL_OFF_FRAC])
  61
  62 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
  63         [CLK_ALPHA_PLL_TYPE_DEFAULT] =  {
  64                 [PLL_OFF_L_VAL] = 0x04,
  65                 [PLL_OFF_ALPHA_VAL] = 0x08,
  66                 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
  67                 [PLL_OFF_USER_CTL] = 0x10,
  68                 [PLL_OFF_USER_CTL_U] = 0x14,
  69                 [PLL_OFF_CONFIG_CTL] = 0x18,
  70                 [PLL_OFF_TEST_CTL] = 0x1c,
  71                 [PLL_OFF_TEST_CTL_U] = 0x20,
  72                 [PLL_OFF_STATUS] = 0x24,
  73         },
  74         [CLK_ALPHA_PLL_TYPE_HUAYRA] =  {
  75                 [PLL_OFF_L_VAL] = 0x04,
  76                 [PLL_OFF_ALPHA_VAL] = 0x08,
  77                 [PLL_OFF_USER_CTL] = 0x10,
  78                 [PLL_OFF_CONFIG_CTL] = 0x14,
  79                 [PLL_OFF_CONFIG_CTL_U] = 0x18,
  80                 [PLL_OFF_TEST_CTL] = 0x1c,
  81                 [PLL_OFF_TEST_CTL_U] = 0x20,
  82                 [PLL_OFF_STATUS] = 0x24,
  83         },
  84         [CLK_ALPHA_PLL_TYPE_BRAMMO] =  {
  85                 [PLL_OFF_L_VAL] = 0x04,
  86                 [PLL_OFF_ALPHA_VAL] = 0x08,
  87                 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
  88                 [PLL_OFF_USER_CTL] = 0x10,
  89                 [PLL_OFF_CONFIG_CTL] = 0x18,
  90                 [PLL_OFF_TEST_CTL] = 0x1c,
  91                 [PLL_OFF_STATUS] = 0x24,
  92         },
  93         [CLK_ALPHA_PLL_TYPE_FABIA] =  {
  94                 [PLL_OFF_L_VAL] = 0x04,
  95                 [PLL_OFF_USER_CTL] = 0x0c,
  96                 [PLL_OFF_USER_CTL_U] = 0x10,
  97                 [PLL_OFF_CONFIG_CTL] = 0x14,
  98                 [PLL_OFF_CONFIG_CTL_U] = 0x18,
  99                 [PLL_OFF_TEST_CTL] = 0x1c,
 100                 [PLL_OFF_TEST_CTL_U] = 0x20,
 101                 [PLL_OFF_STATUS] = 0x24,
 102                 [PLL_OFF_OPMODE] = 0x2c,
 103                 [PLL_OFF_FRAC] = 0x38,
 104         },
 105         [CLK_ALPHA_PLL_TYPE_TRION] = {
 106                 [PLL_OFF_L_VAL] = 0x04,
 107                 [PLL_OFF_CAL_L_VAL] = 0x08,
 108                 [PLL_OFF_USER_CTL] = 0x0c,
 109                 [PLL_OFF_USER_CTL_U] = 0x10,
 110                 [PLL_OFF_USER_CTL_U1] = 0x14,
 111                 [PLL_OFF_CONFIG_CTL] = 0x18,
 112                 [PLL_OFF_CONFIG_CTL_U] = 0x1c,
 113                 [PLL_OFF_CONFIG_CTL_U1] = 0x20,
 114                 [PLL_OFF_TEST_CTL] = 0x24,
 115                 [PLL_OFF_TEST_CTL_U] = 0x28,
 116                 [PLL_OFF_TEST_CTL_U1] = 0x2c,
 117                 [PLL_OFF_STATUS] = 0x30,
 118                 [PLL_OFF_OPMODE] = 0x38,
 119                 [PLL_OFF_ALPHA_VAL] = 0x40,
 120         },
 121         [CLK_ALPHA_PLL_TYPE_AGERA] =  {
 122                 [PLL_OFF_L_VAL] = 0x04,
 123                 [PLL_OFF_ALPHA_VAL] = 0x08,
 124                 [PLL_OFF_USER_CTL] = 0x0c,
 125                 [PLL_OFF_CONFIG_CTL] = 0x10,
 126                 [PLL_OFF_CONFIG_CTL_U] = 0x14,
 127                 [PLL_OFF_TEST_CTL] = 0x18,
 128                 [PLL_OFF_TEST_CTL_U] = 0x1c,
 129                 [PLL_OFF_STATUS] = 0x2c,
 130         },
 131         [CLK_ALPHA_PLL_TYPE_ZONDA] =  {
 132                 [PLL_OFF_L_VAL] = 0x04,
 133                 [PLL_OFF_ALPHA_VAL] = 0x08,
 134                 [PLL_OFF_USER_CTL] = 0x0c,
 135                 [PLL_OFF_CONFIG_CTL] = 0x10,
 136                 [PLL_OFF_CONFIG_CTL_U] = 0x14,
 137                 [PLL_OFF_CONFIG_CTL_U1] = 0x18,
 138                 [PLL_OFF_TEST_CTL] = 0x1c,
 139                 [PLL_OFF_TEST_CTL_U] = 0x20,
 140                 [PLL_OFF_TEST_CTL_U1] = 0x24,
 141                 [PLL_OFF_OPMODE] = 0x28,
 142                 [PLL_OFF_STATUS] = 0x38,
 143         },
 144         [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = {
 145                 [PLL_OFF_OPMODE] = 0x04,
 146                 [PLL_OFF_STATUS] = 0x0c,
 147                 [PLL_OFF_L_VAL] = 0x10,
 148                 [PLL_OFF_ALPHA_VAL] = 0x14,
 149                 [PLL_OFF_USER_CTL] = 0x18,
 150                 [PLL_OFF_USER_CTL_U] = 0x1c,
 151                 [PLL_OFF_CONFIG_CTL] = 0x20,
 152                 [PLL_OFF_CONFIG_CTL_U] = 0x24,
 153                 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
 154                 [PLL_OFF_TEST_CTL] = 0x2c,
 155                 [PLL_OFF_TEST_CTL_U] = 0x30,
 156                 [PLL_OFF_TEST_CTL_U1] = 0x34,
 157         },
 158         [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = {
 159                 [PLL_OFF_OPMODE] = 0x04,
 160                 [PLL_OFF_STATE] = 0x08,
 161                 [PLL_OFF_STATUS] = 0x0c,
 162                 [PLL_OFF_L_VAL] = 0x10,
 163                 [PLL_OFF_ALPHA_VAL] = 0x14,
 164                 [PLL_OFF_USER_CTL] = 0x18,
 165                 [PLL_OFF_USER_CTL_U] = 0x1c,
 166                 [PLL_OFF_CONFIG_CTL] = 0x20,
 167                 [PLL_OFF_CONFIG_CTL_U] = 0x24,
 168                 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
 169                 [PLL_OFF_TEST_CTL] = 0x2c,
 170                 [PLL_OFF_TEST_CTL_U] = 0x30,
 171                 [PLL_OFF_TEST_CTL_U1] = 0x34,
 172                 [PLL_OFF_TEST_CTL_U2] = 0x38,
 173         },
 174         [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {
 175                 [PLL_OFF_OPMODE] = 0x04,
 176                 [PLL_OFF_STATUS] = 0x0c,
 177                 [PLL_OFF_L_VAL] = 0x10,
 178                 [PLL_OFF_USER_CTL] = 0x14,
 179                 [PLL_OFF_USER_CTL_U] = 0x18,
 180                 [PLL_OFF_CONFIG_CTL] = 0x1c,
 181                 [PLL_OFF_CONFIG_CTL_U] = 0x20,
 182                 [PLL_OFF_CONFIG_CTL_U1] = 0x24,
 183                 [PLL_OFF_TEST_CTL] = 0x28,
 184                 [PLL_OFF_TEST_CTL_U] = 0x2c,
 185         },
 186         [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] =  {
 187                 [PLL_OFF_L_VAL] = 0x04,
 188                 [PLL_OFF_ALPHA_VAL] = 0x08,
 189                 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
 190                 [PLL_OFF_TEST_CTL] = 0x10,
 191                 [PLL_OFF_TEST_CTL_U] = 0x14,
 192                 [PLL_OFF_USER_CTL] = 0x18,
 193                 [PLL_OFF_USER_CTL_U] = 0x1c,
 194                 [PLL_OFF_CONFIG_CTL] = 0x20,
 195                 [PLL_OFF_STATUS] = 0x24,
 196         },
 197         [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] =  {
 198                 [PLL_OFF_L_VAL] = 0x04,
 199                 [PLL_OFF_ALPHA_VAL] = 0x08,
 200                 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
 201                 [PLL_OFF_TEST_CTL] = 0x10,
 202                 [PLL_OFF_TEST_CTL_U] = 0x14,
 203                 [PLL_OFF_USER_CTL] = 0x18,
 204                 [PLL_OFF_CONFIG_CTL] = 0x1C,
 205                 [PLL_OFF_STATUS] = 0x20,
 206         },
 207         [CLK_ALPHA_PLL_TYPE_STROMER] = {
 208                 [PLL_OFF_L_VAL] = 0x08,
 209                 [PLL_OFF_ALPHA_VAL] = 0x10,
 210                 [PLL_OFF_ALPHA_VAL_U] = 0x14,
 211                 [PLL_OFF_USER_CTL] = 0x18,
 212                 [PLL_OFF_USER_CTL_U] = 0x1c,
 213                 [PLL_OFF_CONFIG_CTL] = 0x20,
 214                 [PLL_OFF_CONFIG_CTL_U] = 0xff,
 215                 [PLL_OFF_TEST_CTL] = 0x30,
 216                 [PLL_OFF_TEST_CTL_U] = 0x34,
 217                 [PLL_OFF_STATUS] = 0x28,
 218         },
 219         [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] =  {
 220                 [PLL_OFF_L_VAL] = 0x04,
 221                 [PLL_OFF_USER_CTL] = 0x08,
 222                 [PLL_OFF_USER_CTL_U] = 0x0c,
 223                 [PLL_OFF_CONFIG_CTL] = 0x10,
 224                 [PLL_OFF_TEST_CTL] = 0x14,
 225                 [PLL_OFF_TEST_CTL_U] = 0x18,
 226                 [PLL_OFF_STATUS] = 0x1c,
 227                 [PLL_OFF_ALPHA_VAL] = 0x24,
 228                 [PLL_OFF_ALPHA_VAL_U] = 0x28,
 229         },
 230 };
 231 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 232
 233 /*
 234  * Even though 40 bits are present, use only 32 for ease of calculation.
 235  */
 236 #define ALPHA_REG_BITWIDTH      40
 237 #define ALPHA_REG_16BIT_WIDTH   16
 238 #define ALPHA_BITWIDTH          32U
 239 #define ALPHA_SHIFT(w)          min(w, ALPHA_BITWIDTH)
 240
 241 #define ALPHA_PLL_STATUS_REG_SHIFT      8
 242
 243 #define PLL_HUAYRA_M_WIDTH              8
 244 #define PLL_HUAYRA_M_SHIFT              8
 245 #define PLL_HUAYRA_M_MASK               0xff
 246 #define PLL_HUAYRA_N_SHIFT              0
 247 #define PLL_HUAYRA_N_MASK               0xff
 248 #define PLL_HUAYRA_ALPHA_WIDTH          16
 249
 250 #define PLL_STANDBY             0x0
 251 #define PLL_RUN                 0x1
 252 #define PLL_OUT_MASK            0x7
 253 #define PLL_RATE_MARGIN         500
 254
 255 /* TRION PLL specific settings and offsets */
 256 #define TRION_PLL_CAL_VAL       0x44
 257 #define TRION_PCAL_DONE         BIT(26)
 258
 259 /* LUCID PLL specific settings and offsets */
 260 #define LUCID_PCAL_DONE         BIT(27)
 261
 262 /* LUCID 5LPE PLL specific settings and offsets */
 263 #define LUCID_5LPE_PCAL_DONE            BIT(11)
 264 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH  BIT(13)
 265 #define LUCID_5LPE_PLL_LATCH_INPUT      BIT(14)
 266 #define LUCID_5LPE_ENABLE_VOTE_RUN      BIT(21)
 267
 268 /* LUCID EVO PLL specific settings and offsets */
 269 #define LUCID_EVO_PCAL_NOT_DONE         BIT(8)
 270 #define LUCID_EVO_ENABLE_VOTE_RUN       BIT(25)
 271 #define LUCID_EVO_PLL_L_VAL_MASK        GENMASK(15, 0)
 272 #define LUCID_EVO_PLL_CAL_L_VAL_SHIFT   16
 273
 274 /* ZONDA PLL specific */
 275 #define ZONDA_PLL_OUT_MASK      0xf
 276 #define ZONDA_STAY_IN_CFA       BIT(16)
 277 #define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
 278
 279 #define pll_alpha_width(p)                                      \
 280                 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
 281                                  ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
 282
 283 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
 284
 285 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
 286                                            struct clk_alpha_pll, clkr)
 287
 288 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
 289                                            struct clk_alpha_pll_postdiv, clkr)
 290
 291 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
 292                         const char *action)
 293 {
 294         u32 val;
 295         int count;
 296         int ret;
 297         const char *name = clk_hw_get_name(&pll->clkr.hw);
 298
 299         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 300         if (ret)
 301                 return ret;
 302
 303         for (count = 200; count > 0; count--) {
 304                 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 305                 if (ret)
 306                         return ret;
 307                 if (inverse && !(val & mask))
 308                         return 0;
 309                 else if ((val & mask) == mask)
 310                         return 0;
 311
 312                 udelay(1);
 313         }
 314
 315         WARN(1, "%s failed to %s!\n", name, action);
 316         return -ETIMEDOUT;
 317 }
 318
 319 #define wait_for_pll_enable_active(pll) \
 320         wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
 321
 322 #define wait_for_pll_enable_lock(pll) \
 323         wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
 324
 325 #define wait_for_zonda_pll_freq_lock(pll) \
 326         wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
 327
 328 #define wait_for_pll_disable(pll) \
 329         wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
 330
 331 #define wait_for_pll_offline(pll) \
 332         wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
 333
 334 #define wait_for_pll_update(pll) \
 335         wait_for_pll(pll, PLL_UPDATE, 1, "update")
 336
 337 #define wait_for_pll_update_ack_set(pll) \
 338         wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
 339
 340 #define wait_for_pll_update_ack_clear(pll) \
 341         wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
 342
 343 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg,
 344                                         unsigned int val)
 345 {
 346         if (val)
 347                 regmap_write(regmap, reg, val);
 348 }
 349
 350 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 351                              const struct alpha_pll_config *config)
 352 {
 353         u32 val, mask;
 354
 355         regmap_write(regmap, PLL_L_VAL(pll), config->l);
 356         regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
 357         regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
 358
 359         if (pll_has_64bit_config(pll))
 360                 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
 361                              config->config_ctl_hi_val);
 362
 363         if (pll_alpha_width(pll) > 32)
 364                 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
 365
 366         val = config->main_output_mask;
 367         val |= config->aux_output_mask;
 368         val |= config->aux2_output_mask;
 369         val |= config->early_output_mask;
 370         val |= config->pre_div_val;
 371         val |= config->post_div_val;
 372         val |= config->vco_val;
 373         val |= config->alpha_en_mask;
 374         val |= config->alpha_mode_mask;
 375
 376         mask = config->main_output_mask;
 377         mask |= config->aux_output_mask;
 378         mask |= config->aux2_output_mask;
 379         mask |= config->early_output_mask;
 380         mask |= config->pre_div_mask;
 381         mask |= config->post_div_mask;
 382         mask |= config->vco_mask;
 383
 384         regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
 385
 386         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
 387                                                 config->test_ctl_val);
 388         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
 389                                                 config->test_ctl_hi_val);
 390
 391         if (pll->flags & SUPPORTS_FSM_MODE)
 392                 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
 393 }
 394 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
 395
 396 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
 397 {
 398         int ret;
 399         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 400         u32 val;
 401
 402         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 403         if (ret)
 404                 return ret;
 405
 406         val |= PLL_FSM_ENA;
 407
 408         if (pll->flags & SUPPORTS_OFFLINE_REQ)
 409                 val &= ~PLL_OFFLINE_REQ;
 410
 411         ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
 412         if (ret)
 413                 return ret;
 414
 415         /* Make sure enable request goes through before waiting for update */
 416         mb();
 417
 418         return wait_for_pll_enable_active(pll);
 419 }
 420
 421 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
 422 {
 423         int ret;
 424         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 425         u32 val;
 426
 427         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 428         if (ret)
 429                 return;
 430
 431         if (pll->flags & SUPPORTS_OFFLINE_REQ) {
 432                 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 433                                          PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
 434                 if (ret)
 435                         return;
 436
 437                 ret = wait_for_pll_offline(pll);
 438                 if (ret)
 439                         return;
 440         }
 441
 442         /* Disable hwfsm */
 443         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 444                                  PLL_FSM_ENA, 0);
 445         if (ret)
 446                 return;
 447
 448         wait_for_pll_disable(pll);
 449 }
 450
 451 static int pll_is_enabled(struct clk_hw *hw, u32 mask)
 452 {
 453         int ret;
 454         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 455         u32 val;
 456
 457         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 458         if (ret)
 459                 return ret;
 460
 461         return !!(val & mask);
 462 }
 463
 464 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
 465 {
 466         return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
 467 }
 468
 469 static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
 470 {
 471         return pll_is_enabled(hw, PLL_LOCK_DET);
 472 }
 473
 474 static int clk_alpha_pll_enable(struct clk_hw *hw)
 475 {
 476         int ret;
 477         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 478         u32 val, mask;
 479
 480         mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
 481         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 482         if (ret)
 483                 return ret;
 484
 485         /* If in FSM mode, just vote for it */
 486         if (val & PLL_VOTE_FSM_ENA) {
 487                 ret = clk_enable_regmap(hw);
 488                 if (ret)
 489                         return ret;
 490                 return wait_for_pll_enable_active(pll);
 491         }
 492
 493         /* Skip if already enabled */
 494         if ((val & mask) == mask)
 495                 return 0;
 496
 497         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 498                                  PLL_BYPASSNL, PLL_BYPASSNL);
 499         if (ret)
 500                 return ret;
 501
 502         /*
 503          * H/W requires a 5us delay between disabling the bypass and
 504          * de-asserting the reset.
 505          */
 506         mb();
 507         udelay(5);
 508
 509         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 510                                  PLL_RESET_N, PLL_RESET_N);
 511         if (ret)
 512                 return ret;
 513
 514         ret = wait_for_pll_enable_lock(pll);
 515         if (ret)
 516                 return ret;
 517
 518         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 519                                  PLL_OUTCTRL, PLL_OUTCTRL);
 520
 521         /* Ensure that the write above goes through before returning. */
 522         mb();
 523         return ret;
 524 }
 525
 526 static void clk_alpha_pll_disable(struct clk_hw *hw)
 527 {
 528         int ret;
 529         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 530         u32 val, mask;
 531
 532         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 533         if (ret)
 534                 return;
 535
 536         /* If in FSM mode, just unvote it */
 537         if (val & PLL_VOTE_FSM_ENA) {
 538                 clk_disable_regmap(hw);
 539                 return;
 540         }
 541
 542         mask = PLL_OUTCTRL;
 543         regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
 544
 545         /* Delay of 2 output clock ticks required until output is disabled */
 546         mb();
 547         udelay(1);
 548
 549         mask = PLL_RESET_N | PLL_BYPASSNL;
 550         regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
 551 }
 552
 553 static unsigned long
 554 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
 555 {
 556         return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
 557 }
 558
 559 static unsigned long
 560 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
 561                      u32 alpha_width)
 562 {
 563         u64 remainder;
 564         u64 quotient;
 565
 566         quotient = rate;
 567         remainder = do_div(quotient, prate);
 568         *l = quotient;
 569
 570         if (!remainder) {
 571                 *a = 0;
 572                 return rate;
 573         }
 574
 575         /* Upper ALPHA_BITWIDTH bits of Alpha */
 576         quotient = remainder << ALPHA_SHIFT(alpha_width);
 577
 578         remainder = do_div(quotient, prate);
 579
 580         if (remainder)
 581                 quotient++;
 582
 583         *a = quotient;
 584         return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
 585 }
 586
 587 static const struct pll_vco *
 588 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
 589 {
 590         const struct pll_vco *v = pll->vco_table;
 591         const struct pll_vco *end = v + pll->num_vco;
 592
 593         for (; v < end; v++)
 594                 if (rate >= v->min_freq && rate <= v->max_freq)
 595                         return v;
 596
 597         return NULL;
 598 }
 599
 600 static unsigned long
 601 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 602 {
 603         u32 l, low, high, ctl;
 604         u64 a = 0, prate = parent_rate;
 605         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 606         u32 alpha_width = pll_alpha_width(pll);
 607
 608         regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
 609
 610         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 611         if (ctl & PLL_ALPHA_EN) {
 612                 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
 613                 if (alpha_width > 32) {
 614                         regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
 615                                     &high);
 616                         a = (u64)high << 32 | low;
 617                 } else {
 618                         a = low & GENMASK(alpha_width - 1, 0);
 619                 }
 620
 621                 if (alpha_width > ALPHA_BITWIDTH)
 622                         a >>= alpha_width - ALPHA_BITWIDTH;
 623         }
 624
 625         return alpha_pll_calc_rate(prate, l, a, alpha_width);
 626 }
 627
 628
 629 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
 630 {
 631         int ret;
 632         u32 mode;
 633
 634         regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
 635
 636         /* Latch the input to the PLL */
 637         regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
 638                            PLL_UPDATE);
 639
 640         /* Wait for 2 reference cycle before checking ACK bit */
 641         udelay(1);
 642
 643         /*
 644          * PLL will latch the new L, Alpha and freq control word.
 645          * PLL will respond by raising PLL_ACK_LATCH output when new programming
 646          * has been latched in and PLL is being updated. When
 647          * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared
 648          * automatically by hardware when PLL_ACK_LATCH is asserted by PLL.
 649          */
 650         if (mode & PLL_UPDATE_BYPASS) {
 651                 ret = wait_for_pll_update_ack_set(pll);
 652                 if (ret)
 653                         return ret;
 654
 655                 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
 656         } else {
 657                 ret = wait_for_pll_update(pll);
 658                 if (ret)
 659                         return ret;
 660         }
 661
 662         ret = wait_for_pll_update_ack_clear(pll);
 663         if (ret)
 664                 return ret;
 665
 666         /* Wait for PLL output to stabilize */
 667         udelay(10);
 668
 669         return 0;
 670 }
 671
 672 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
 673                                       int (*is_enabled)(struct clk_hw *))
 674 {
 675         if (!is_enabled(&pll->clkr.hw) ||
 676             !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
 677                 return 0;
 678
 679         return __clk_alpha_pll_update_latch(pll);
 680 }
 681
 682 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 683                                     unsigned long prate,
 684                                     int (*is_enabled)(struct clk_hw *))
 685 {
 686         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 687         const struct pll_vco *vco;
 688         u32 l, alpha_width = pll_alpha_width(pll);
 689         u64 a;
 690
 691         rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
 692         vco = alpha_pll_find_vco(pll, rate);
 693         if (pll->vco_table && !vco) {
 694                 pr_err("%s: alpha pll not in a valid vco range\n",
 695                        clk_hw_get_name(hw));
 696                 return -EINVAL;
 697         }
 698
 699         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
 700
 701         if (alpha_width > ALPHA_BITWIDTH)
 702                 a <<= alpha_width - ALPHA_BITWIDTH;
 703
 704         if (alpha_width > 32)
 705                 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
 706
 707         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
 708
 709         if (vco) {
 710                 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 711                                    PLL_VCO_MASK << PLL_VCO_SHIFT,
 712                                    vco->val << PLL_VCO_SHIFT);
 713         }
 714
 715         regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 716                            PLL_ALPHA_EN, PLL_ALPHA_EN);
 717
 718         return clk_alpha_pll_update_latch(pll, is_enabled);
 719 }
 720
 721 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 722                                   unsigned long prate)
 723 {
 724         return __clk_alpha_pll_set_rate(hw, rate, prate,
 725                                         clk_alpha_pll_is_enabled);
 726 }
 727
 728 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
 729                                         unsigned long prate)
 730 {
 731         return __clk_alpha_pll_set_rate(hw, rate, prate,
 732                                         clk_alpha_pll_hwfsm_is_enabled);
 733 }
 734
 735 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 736                                      unsigned long *prate)
 737 {
 738         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 739         u32 l, alpha_width = pll_alpha_width(pll);
 740         u64 a;
 741         unsigned long min_freq, max_freq;
 742
 743         rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
 744         if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
 745                 return rate;
 746
 747         min_freq = pll->vco_table[0].min_freq;
 748         max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
 749
 750         return clamp(rate, min_freq, max_freq);
 751 }
 752
 753 static unsigned long
 754 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
 755 {
 756         /*
 757          * a contains 16 bit alpha_val in two’s complement number in the range
 758          * of [-0.5, 0.5).
 759          */
 760         if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
 761                 l -= 1;
 762
 763         return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
 764 }
 765
 766 static unsigned long
 767 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
 768                             u32 *l, u32 *a)
 769 {
 770         u64 remainder;
 771         u64 quotient;
 772
 773         quotient = rate;
 774         remainder = do_div(quotient, prate);
 775         *l = quotient;
 776
 777         if (!remainder) {
 778                 *a = 0;
 779                 return rate;
 780         }
 781
 782         quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
 783         remainder = do_div(quotient, prate);
 784
 785         if (remainder)
 786                 quotient++;
 787
 788         /*
 789          * alpha_val should be in two’s complement number in the range
 790          * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value
 791          * since alpha value will be subtracted in this case.
 792          */
 793         if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
 794                 *l += 1;
 795
 796         *a = quotient;
 797         return alpha_huayra_pll_calc_rate(prate, *l, *a);
 798 }
 799
 800 static unsigned long
 801 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 802 {
 803         u64 rate = parent_rate, tmp;
 804         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 805         u32 l, alpha = 0, ctl, alpha_m, alpha_n;
 806
 807         regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
 808         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 809
 810         if (ctl & PLL_ALPHA_EN) {
 811                 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
 812                 /*
 813                  * Depending upon alpha_mode, it can be treated as M/N value or
 814                  * as a two’s complement number. When alpha_mode=1,
 815                  * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N
 816                  *
 817                  *              Fout=FIN*(L+(M/N))
 818                  *
 819                  * M is a signed number (-128 to 127) and N is unsigned
 820                  * (0 to 255). M/N has to be within +/-0.5.
 821                  *
 822                  * When alpha_mode=0, it is a two’s complement number in the
 823                  * range [-0.5, 0.5).
 824                  *
 825                  *              Fout=FIN*(L+(alpha_val)/2^16)
 826                  *
 827                  * where alpha_val is two’s complement number.
 828                  */
 829                 if (!(ctl & PLL_ALPHA_MODE))
 830                         return alpha_huayra_pll_calc_rate(rate, l, alpha);
 831
 832                 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
 833                 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
 834
 835                 rate *= l;
 836                 tmp = parent_rate;
 837                 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
 838                         alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
 839                         tmp *= alpha_m;
 840                         do_div(tmp, alpha_n);
 841                         rate -= tmp;
 842                 } else {
 843                         tmp *= alpha_m;
 844                         do_div(tmp, alpha_n);
 845                         rate += tmp;
 846                 }
 847
 848                 return rate;
 849         }
 850
 851         return alpha_huayra_pll_calc_rate(rate, l, alpha);
 852 }
 853
 854 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
 855                                      unsigned long prate)
 856 {
 857         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 858         u32 l, a, ctl, cur_alpha = 0;
 859
 860         rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
 861
 862         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 863
 864         if (ctl & PLL_ALPHA_EN)
 865                 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
 866
 867         /*
 868          * Huayra PLL supports PLL dynamic programming. User can change L_VAL,
 869          * without having to go through the power on sequence.
 870          */
 871         if (clk_alpha_pll_is_enabled(hw)) {
 872                 if (cur_alpha != a) {
 873                         pr_err("%s: clock needs to be gated\n",
 874                                clk_hw_get_name(hw));
 875                         return -EBUSY;
 876                 }
 877
 878                 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
 879                 /* Ensure that the write above goes to detect L val change. */
 880                 mb();
 881                 return wait_for_pll_enable_lock(pll);
 882         }
 883
 884         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
 885         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
 886
 887         if (a == 0)
 888                 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 889                                    PLL_ALPHA_EN, 0x0);
 890         else
 891                 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 892                                    PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
 893
 894         return 0;
 895 }
 896
 897 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
 898                                         unsigned long *prate)
 899 {
 900         u32 l, a;
 901
 902         return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
 903 }
 904
 905 static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
 906                                 struct regmap *regmap)
 907 {
 908         u32 mode_val, opmode_val;
 909         int ret;
 910
 911         ret = regmap_read(regmap, PLL_MODE(pll), &mode_val);
 912         ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
 913         if (ret)
 914                 return 0;
 915
 916         return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL));
 917 }
 918
 919 static int clk_trion_pll_is_enabled(struct clk_hw *hw)
 920 {
 921         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 922
 923         return trion_pll_is_enabled(pll, pll->clkr.regmap);
 924 }
 925
 926 static int clk_trion_pll_enable(struct clk_hw *hw)
 927 {
 928         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 929         struct regmap *regmap = pll->clkr.regmap;
 930         u32 val;
 931         int ret;
 932
 933         ret = regmap_read(regmap, PLL_MODE(pll), &val);
 934         if (ret)
 935                 return ret;
 936
 937         /* If in FSM mode, just vote for it */
 938         if (val & PLL_VOTE_FSM_ENA) {
 939                 ret = clk_enable_regmap(hw);
 940                 if (ret)
 941                         return ret;
 942                 return wait_for_pll_enable_active(pll);
 943         }
 944
 945         /* Set operation mode to RUN */
 946         regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
 947
 948         ret = wait_for_pll_enable_lock(pll);
 949         if (ret)
 950                 return ret;
 951
 952         /* Enable the PLL outputs */
 953         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
 954                                  PLL_OUT_MASK, PLL_OUT_MASK);
 955         if (ret)
 956                 return ret;
 957
 958         /* Enable the global PLL outputs */
 959         return regmap_update_bits(regmap, PLL_MODE(pll),
 960                                  PLL_OUTCTRL, PLL_OUTCTRL);
 961 }
 962
 963 static void clk_trion_pll_disable(struct clk_hw *hw)
 964 {
 965         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 966         struct regmap *regmap = pll->clkr.regmap;
 967         u32 val;
 968         int ret;
 969
 970         ret = regmap_read(regmap, PLL_MODE(pll), &val);
 971         if (ret)
 972                 return;
 973
 974         /* If in FSM mode, just unvote it */
 975         if (val & PLL_VOTE_FSM_ENA) {
 976                 clk_disable_regmap(hw);
 977                 return;
 978         }
 979
 980         /* Disable the global PLL output */
 981         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
 982         if (ret)
 983                 return;
 984
 985         /* Disable the PLL outputs */
 986         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
 987                                  PLL_OUT_MASK, 0);
 988         if (ret)
 989                 return;
 990
 991         /* Place the PLL mode in STANDBY */
 992         regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
 993         regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
 994 }
 995
 996 static unsigned long
 997 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 998 {
 999         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1000         u32 l, frac, alpha_width = pll_alpha_width(pll);
1001
1002         regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1003         regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
1004
1005         return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1006 }
1007
1008 const struct clk_ops clk_alpha_pll_fixed_ops = {
1009         .enable = clk_alpha_pll_enable,
1010         .disable = clk_alpha_pll_disable,
1011         .is_enabled = clk_alpha_pll_is_enabled,
1012         .recalc_rate = clk_alpha_pll_recalc_rate,
1013 };
1014 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops);
1015
1016 const struct clk_ops clk_alpha_pll_ops = {
1017         .enable = clk_alpha_pll_enable,
1018         .disable = clk_alpha_pll_disable,
1019         .is_enabled = clk_alpha_pll_is_enabled,
1020         .recalc_rate = clk_alpha_pll_recalc_rate,
1021         .round_rate = clk_alpha_pll_round_rate,
1022         .set_rate = clk_alpha_pll_set_rate,
1023 };
1024 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
1025
1026 const struct clk_ops clk_alpha_pll_huayra_ops = {
1027         .enable = clk_alpha_pll_enable,
1028         .disable = clk_alpha_pll_disable,
1029         .is_enabled = clk_alpha_pll_is_enabled,
1030         .recalc_rate = alpha_pll_huayra_recalc_rate,
1031         .round_rate = alpha_pll_huayra_round_rate,
1032         .set_rate = alpha_pll_huayra_set_rate,
1033 };
1034 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
1035
1036 const struct clk_ops clk_alpha_pll_hwfsm_ops = {
1037         .enable = clk_alpha_pll_hwfsm_enable,
1038         .disable = clk_alpha_pll_hwfsm_disable,
1039         .is_enabled = clk_alpha_pll_hwfsm_is_enabled,
1040         .recalc_rate = clk_alpha_pll_recalc_rate,
1041         .round_rate = clk_alpha_pll_round_rate,
1042         .set_rate = clk_alpha_pll_hwfsm_set_rate,
1043 };
1044 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
1045
1046 const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
1047         .enable = clk_trion_pll_enable,
1048         .disable = clk_trion_pll_disable,
1049         .is_enabled = clk_trion_pll_is_enabled,
1050         .recalc_rate = clk_trion_pll_recalc_rate,
1051         .round_rate = clk_alpha_pll_round_rate,
1052 };
1053 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
1054
1055 static unsigned long
1056 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1057 {
1058         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1059         u32 ctl;
1060
1061         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1062
1063         ctl >>= PLL_POST_DIV_SHIFT;
1064         ctl &= PLL_POST_DIV_MASK(pll);
1065
1066         return parent_rate >> fls(ctl);
1067 }
1068
1069 static const struct clk_div_table clk_alpha_div_table[] = {
1070         { 0x0, 1 },
1071         { 0x1, 2 },
1072         { 0x3, 4 },
1073         { 0x7, 8 },
1074         { 0xf, 16 },
1075         { }
1076 };
1077
1078 static const struct clk_div_table clk_alpha_2bit_div_table[] = {
1079         { 0x0, 1 },
1080         { 0x1, 2 },
1081         { 0x3, 4 },
1082         { }
1083 };
1084
1085 static long
1086 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1087                                  unsigned long *prate)
1088 {
1089         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1090         const struct clk_div_table *table;
1091
1092         if (pll->width == 2)
1093                 table = clk_alpha_2bit_div_table;
1094         else
1095                 table = clk_alpha_div_table;
1096
1097         return divider_round_rate(hw, rate, prate, table,
1098                                   pll->width, CLK_DIVIDER_POWER_OF_TWO);
1099 }
1100
1101 static long
1102 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
1103                                     unsigned long *prate)
1104 {
1105         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1106         u32 ctl, div;
1107
1108         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1109
1110         ctl >>= PLL_POST_DIV_SHIFT;
1111         ctl &= BIT(pll->width) - 1;
1112         div = 1 << fls(ctl);
1113
1114         if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
1115                 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
1116
1117         return DIV_ROUND_UP_ULL((u64)*prate, div);
1118 }
1119
1120 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1121                                           unsigned long parent_rate)
1122 {
1123         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1124         int div;
1125
1126         /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
1127         div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
1128
1129         return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1130                                   PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1131                                   div << PLL_POST_DIV_SHIFT);
1132 }
1133
1134 const struct clk_ops clk_alpha_pll_postdiv_ops = {
1135         .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1136         .round_rate = clk_alpha_pll_postdiv_round_rate,
1137         .set_rate = clk_alpha_pll_postdiv_set_rate,
1138 };
1139 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
1140
1141 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
1142         .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
1143         .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1144 };
1145 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
1146
1147 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1148                              const struct alpha_pll_config *config)
1149 {
1150         u32 val, mask;
1151
1152         clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1153         clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha);
1154         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1155                                                 config->config_ctl_val);
1156         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1157                                                 config->config_ctl_hi_val);
1158         clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1159                                                 config->user_ctl_val);
1160         clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1161                                                 config->user_ctl_hi_val);
1162         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1163                                                 config->test_ctl_val);
1164         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1165                                                 config->test_ctl_hi_val);
1166
1167         if (config->post_div_mask) {
1168                 mask = config->post_div_mask;
1169                 val = config->post_div_val;
1170                 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
1171         }
1172
1173         if (pll->flags & SUPPORTS_FSM_LEGACY_MODE)
1174                 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE,
1175                                                         PLL_FSM_LEGACY_MODE);
1176
1177         regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1178                                                         PLL_UPDATE_BYPASS);
1179
1180         regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1181 }
1182 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
1183
1184 static int alpha_pll_fabia_enable(struct clk_hw *hw)
1185 {
1186         int ret;
1187         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1188         u32 val, opmode_val;
1189         struct regmap *regmap = pll->clkr.regmap;
1190
1191         ret = regmap_read(regmap, PLL_MODE(pll), &val);
1192         if (ret)
1193                 return ret;
1194
1195         /* If in FSM mode, just vote for it */
1196         if (val & PLL_VOTE_FSM_ENA) {
1197                 ret = clk_enable_regmap(hw);
1198                 if (ret)
1199                         return ret;
1200                 return wait_for_pll_enable_active(pll);
1201         }
1202
1203         ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
1204         if (ret)
1205                 return ret;
1206
1207         /* Skip If PLL is already running */
1208         if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
1209                 return 0;
1210
1211         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1212         if (ret)
1213                 return ret;
1214
1215         ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1216         if (ret)
1217                 return ret;
1218
1219         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
1220                                  PLL_RESET_N);
1221         if (ret)
1222                 return ret;
1223
1224         ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1225         if (ret)
1226                 return ret;
1227
1228         ret = wait_for_pll_enable_lock(pll);
1229         if (ret)
1230                 return ret;
1231
1232         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1233                                  PLL_OUT_MASK, PLL_OUT_MASK);
1234         if (ret)
1235                 return ret;
1236
1237         return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
1238                                  PLL_OUTCTRL);
1239 }
1240
1241 static void alpha_pll_fabia_disable(struct clk_hw *hw)
1242 {
1243         int ret;
1244         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1245         u32 val;
1246         struct regmap *regmap = pll->clkr.regmap;
1247
1248         ret = regmap_read(regmap, PLL_MODE(pll), &val);
1249         if (ret)
1250                 return;
1251
1252         /* If in FSM mode, just unvote it */
1253         if (val & PLL_FSM_ENA) {
1254                 clk_disable_regmap(hw);
1255                 return;
1256         }
1257
1258         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1259         if (ret)
1260                 return;
1261
1262         /* Disable main outputs */
1263         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1264         if (ret)
1265                 return;
1266
1267         /* Place the PLL in STANDBY */
1268         regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1269 }
1270
1271 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
1272                                                 unsigned long parent_rate)
1273 {
1274         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1275         u32 l, frac, alpha_width = pll_alpha_width(pll);
1276
1277         regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1278         regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
1279
1280         return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1281 }
1282
1283 /*
1284  * Due to limited number of bits for fractional rate programming, the
1285  * rounded up rate could be marginally higher than the requested rate.
1286  */
1287 static int alpha_pll_check_rate_margin(struct clk_hw *hw,
1288                         unsigned long rrate, unsigned long rate)
1289 {
1290         unsigned long rate_margin = rate + PLL_RATE_MARGIN;
1291
1292         if (rrate > rate_margin || rrate < rate) {
1293                 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
1294                        clk_hw_get_name(hw), rrate, rate, rate_margin);
1295                 return -EINVAL;
1296         }
1297
1298         return 0;
1299 }
1300
1301 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
1302                                                 unsigned long prate)
1303 {
1304         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1305         u32 l, alpha_width = pll_alpha_width(pll);
1306         unsigned long rrate;
1307         int ret;
1308         u64 a;
1309
1310         rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1311
1312         ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1313         if (ret < 0)
1314                 return ret;
1315
1316         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1317         regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
1318
1319         return __clk_alpha_pll_update_latch(pll);
1320 }
1321
1322 static int alpha_pll_fabia_prepare(struct clk_hw *hw)
1323 {
1324         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1325         const struct pll_vco *vco;
1326         struct clk_hw *parent_hw;
1327         unsigned long cal_freq, rrate;
1328         u32 cal_l, val, alpha_width = pll_alpha_width(pll);
1329         const char *name = clk_hw_get_name(hw);
1330         u64 a;
1331         int ret;
1332
1333         /* Check if calibration needs to be done i.e. PLL is in reset */
1334         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1335         if (ret)
1336                 return ret;
1337
1338         /* Return early if calibration is not needed. */
1339         if (val & PLL_RESET_N)
1340                 return 0;
1341
1342         vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
1343         if (!vco) {
1344                 pr_err("%s: alpha pll not in a valid vco range\n", name);
1345                 return -EINVAL;
1346         }
1347
1348         cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq +
1349                                 pll->vco_table[0].max_freq) * 54, 100);
1350
1351         parent_hw = clk_hw_get_parent(hw);
1352         if (!parent_hw)
1353                 return -EINVAL;
1354
1355         rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw),
1356                                         &cal_l, &a, alpha_width);
1357
1358         ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq);
1359         if (ret < 0)
1360                 return ret;
1361
1362         /* Setup PLL for calibration frequency */
1363         regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l);
1364
1365         /* Bringup the PLL at calibration frequency */
1366         ret = clk_alpha_pll_enable(hw);
1367         if (ret) {
1368                 pr_err("%s: alpha pll calibration failed\n", name);
1369                 return ret;
1370         }
1371
1372         clk_alpha_pll_disable(hw);
1373
1374         return 0;
1375 }
1376
1377 const struct clk_ops clk_alpha_pll_fabia_ops = {
1378         .prepare = alpha_pll_fabia_prepare,
1379         .enable = alpha_pll_fabia_enable,
1380         .disable = alpha_pll_fabia_disable,
1381         .is_enabled = clk_alpha_pll_is_enabled,
1382         .set_rate = alpha_pll_fabia_set_rate,
1383         .recalc_rate = alpha_pll_fabia_recalc_rate,
1384         .round_rate = clk_alpha_pll_round_rate,
1385 };
1386 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
1387
1388 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
1389         .enable = alpha_pll_fabia_enable,
1390         .disable = alpha_pll_fabia_disable,
1391         .is_enabled = clk_alpha_pll_is_enabled,
1392         .recalc_rate = alpha_pll_fabia_recalc_rate,
1393         .round_rate = clk_alpha_pll_round_rate,
1394 };
1395 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
1396
1397 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1398                                         unsigned long parent_rate)
1399 {
1400         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1401         u32 i, div = 1, val;
1402         int ret;
1403
1404         ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1405         if (ret)
1406                 return ret;
1407
1408         val >>= pll->post_div_shift;
1409         val &= BIT(pll->width) - 1;
1410
1411         for (i = 0; i < pll->num_post_div; i++) {
1412                 if (pll->post_div_table[i].val == val) {
1413                         div = pll->post_div_table[i].div;
1414                         break;
1415                 }
1416         }
1417
1418         return (parent_rate / div);
1419 }
1420
1421 static unsigned long
1422 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1423 {
1424         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1425         struct regmap *regmap = pll->clkr.regmap;
1426         u32 i, div = 1, val;
1427
1428         regmap_read(regmap, PLL_USER_CTL(pll), &val);
1429
1430         val >>= pll->post_div_shift;
1431         val &= PLL_POST_DIV_MASK(pll);
1432
1433         for (i = 0; i < pll->num_post_div; i++) {
1434                 if (pll->post_div_table[i].val == val) {
1435                         div = pll->post_div_table[i].div;
1436                         break;
1437                 }
1438         }
1439
1440         return (parent_rate / div);
1441 }
1442
1443 static long
1444 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1445                                  unsigned long *prate)
1446 {
1447         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1448
1449         return divider_round_rate(hw, rate, prate, pll->post_div_table,
1450                                   pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1451 };
1452
1453 static int
1454 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1455                                unsigned long parent_rate)
1456 {
1457         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1458         struct regmap *regmap = pll->clkr.regmap;
1459         int i, val = 0, div;
1460
1461         div = DIV_ROUND_UP_ULL(parent_rate, rate);
1462         for (i = 0; i < pll->num_post_div; i++) {
1463                 if (pll->post_div_table[i].div == div) {
1464                         val = pll->post_div_table[i].val;
1465                         break;
1466                 }
1467         }
1468
1469         return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1470                                   PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1471                                   val << PLL_POST_DIV_SHIFT);
1472 }
1473
1474 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
1475         .recalc_rate = clk_trion_pll_postdiv_recalc_rate,
1476         .round_rate = clk_trion_pll_postdiv_round_rate,
1477         .set_rate = clk_trion_pll_postdiv_set_rate,
1478 };
1479 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
1480
1481 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1482                                 unsigned long rate, unsigned long *prate)
1483 {
1484         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1485
1486         return divider_round_rate(hw, rate, prate, pll->post_div_table,
1487                                 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1488 }
1489
1490 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1491                                 unsigned long rate, unsigned long parent_rate)
1492 {
1493         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1494         int i, val = 0, div, ret;
1495
1496         /*
1497          * If the PLL is in FSM mode, then treat set_rate callback as a
1498          * no-operation.
1499          */
1500         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1501         if (ret)
1502                 return ret;
1503
1504         if (val & PLL_VOTE_FSM_ENA)
1505                 return 0;
1506
1507         div = DIV_ROUND_UP_ULL(parent_rate, rate);
1508         for (i = 0; i < pll->num_post_div; i++) {
1509                 if (pll->post_div_table[i].div == div) {
1510                         val = pll->post_div_table[i].val;
1511                         break;
1512                 }
1513         }
1514
1515         return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1516                                 (BIT(pll->width) - 1) << pll->post_div_shift,
1517                                 val << pll->post_div_shift);
1518 }
1519
1520 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
1521         .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1522         .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1523         .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1524 };
1525 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
1526
1527 /**
1528  * clk_trion_pll_configure - configure the trion pll
1529  *
1530  * @pll: clk alpha pll
1531  * @regmap: register map
1532  * @config: configuration to apply for pll
1533  */
1534 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1535                              const struct alpha_pll_config *config)
1536 {
1537         /*
1538          * If the bootloader left the PLL enabled it's likely that there are
1539          * RCGs that will lock up if we disable the PLL below.
1540          */
1541         if (trion_pll_is_enabled(pll, regmap)) {
1542                 pr_debug("Trion PLL is already enabled, skipping configuration\n");
1543                 return;
1544         }
1545
1546         clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1547         regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
1548         clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1549         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1550                                      config->config_ctl_val);
1551         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1552                                      config->config_ctl_hi_val);
1553         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
1554                                      config->config_ctl_hi1_val);
1555         clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1556                                         config->user_ctl_val);
1557         clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1558                                         config->user_ctl_hi_val);
1559         clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
1560                                         config->user_ctl_hi1_val);
1561         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1562                                         config->test_ctl_val);
1563         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1564                                         config->test_ctl_hi_val);
1565         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
1566                                         config->test_ctl_hi1_val);
1567
1568         regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1569                            PLL_UPDATE_BYPASS);
1570
1571         /* Disable PLL output */
1572         regmap_update_bits(regmap, PLL_MODE(pll),  PLL_OUTCTRL, 0);
1573
1574         /* Set operation mode to OFF */
1575         regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1576
1577         /* Place the PLL in STANDBY mode */
1578         regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1579 }
1580 EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
1581
1582 /*
1583  * The TRION PLL requires a power-on self-calibration which happens when the
1584  * PLL comes out of reset. Calibrate in case it is not completed.
1585  */
1586 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done)
1587 {
1588         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1589         u32 val;
1590         int ret;
1591
1592         /* Return early if calibration is not needed. */
1593         regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val);
1594         if (val & pcal_done)
1595                 return 0;
1596
1597         /* On/off to calibrate */
1598         ret = clk_trion_pll_enable(hw);
1599         if (!ret)
1600                 clk_trion_pll_disable(hw);
1601
1602         return ret;
1603 }
1604
1605 static int alpha_pll_trion_prepare(struct clk_hw *hw)
1606 {
1607         return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE);
1608 }
1609
1610 static int alpha_pll_lucid_prepare(struct clk_hw *hw)
1611 {
1612         return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE);
1613 }
1614
1615 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1616                                       unsigned long prate, u32 latch_bit, u32 latch_ack)
1617 {
1618         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1619         unsigned long rrate;
1620         u32 val, l, alpha_width = pll_alpha_width(pll);
1621         u64 a;
1622         int ret;
1623
1624         rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1625
1626         ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1627         if (ret < 0)
1628                 return ret;
1629
1630         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1631         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1632
1633         /* Latch the PLL input */
1634         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit);
1635         if (ret)
1636                 return ret;
1637
1638         /* Wait for 2 reference cycles before checking the ACK bit. */
1639         udelay(1);
1640         regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1641         if (!(val & latch_ack)) {
1642                 pr_err("Lucid PLL latch failed. Output may be unstable!\n");
1643                 return -EINVAL;
1644         }
1645
1646         /* Return the latch input to 0 */
1647         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0);
1648         if (ret)
1649                 return ret;
1650
1651         if (clk_hw_is_enabled(hw)) {
1652                 ret = wait_for_pll_enable_lock(pll);
1653                 if (ret)
1654                         return ret;
1655         }
1656
1657         /* Wait for PLL output to stabilize */
1658         udelay(100);
1659         return 0;
1660 }
1661
1662 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1663                                     unsigned long prate)
1664 {
1665         return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH);
1666 }
1667
1668 const struct clk_ops clk_alpha_pll_trion_ops = {
1669         .prepare = alpha_pll_trion_prepare,
1670         .enable = clk_trion_pll_enable,
1671         .disable = clk_trion_pll_disable,
1672         .is_enabled = clk_trion_pll_is_enabled,
1673         .recalc_rate = clk_trion_pll_recalc_rate,
1674         .round_rate = clk_alpha_pll_round_rate,
1675         .set_rate = alpha_pll_trion_set_rate,
1676 };
1677 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);
1678
1679 const struct clk_ops clk_alpha_pll_lucid_ops = {
1680         .prepare = alpha_pll_lucid_prepare,
1681         .enable = clk_trion_pll_enable,
1682         .disable = clk_trion_pll_disable,
1683         .is_enabled = clk_trion_pll_is_enabled,
1684         .recalc_rate = clk_trion_pll_recalc_rate,
1685         .round_rate = clk_alpha_pll_round_rate,
1686         .set_rate = alpha_pll_trion_set_rate,
1687 };
1688 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
1689
1690 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
1691         .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1692         .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1693         .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1694 };
1695 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
1696
1697 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1698                         const struct alpha_pll_config *config)
1699 {
1700         clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1701         clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1702         clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1703                                                         config->user_ctl_val);
1704         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1705                                                 config->config_ctl_val);
1706         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1707                                                 config->config_ctl_hi_val);
1708         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1709                                                 config->test_ctl_val);
1710         clk_alpha_pll_write_config(regmap,  PLL_TEST_CTL_U(pll),
1711                                                 config->test_ctl_hi_val);
1712 }
1713 EXPORT_SYMBOL_GPL(clk_agera_pll_configure);
1714
1715 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate,
1716                                                         unsigned long prate)
1717 {
1718         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1719         u32 l, alpha_width = pll_alpha_width(pll);
1720         int ret;
1721         unsigned long rrate;
1722         u64 a;
1723
1724         rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1725         ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1726         if (ret < 0)
1727                 return ret;
1728
1729         /* change L_VAL without having to go through the power on sequence */
1730         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1731         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1732
1733         if (clk_hw_is_enabled(hw))
1734                 return wait_for_pll_enable_lock(pll);
1735
1736         return 0;
1737 }
1738
1739 const struct clk_ops clk_alpha_pll_agera_ops = {
1740         .enable = clk_alpha_pll_enable,
1741         .disable = clk_alpha_pll_disable,
1742         .is_enabled = clk_alpha_pll_is_enabled,
1743         .recalc_rate = alpha_pll_fabia_recalc_rate,
1744         .round_rate = clk_alpha_pll_round_rate,
1745         .set_rate = clk_alpha_pll_agera_set_rate,
1746 };
1747 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
1748
1749 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
1750 {
1751         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1752         u32 val;
1753         int ret;
1754
1755         ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1756         if (ret)
1757                 return ret;
1758
1759         /* If in FSM mode, just vote for it */
1760         if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1761                 ret = clk_enable_regmap(hw);
1762                 if (ret)
1763                         return ret;
1764                 return wait_for_pll_enable_lock(pll);
1765         }
1766
1767         /* Check if PLL is already enabled, return if enabled */
1768         ret = trion_pll_is_enabled(pll, pll->clkr.regmap);
1769         if (ret < 0)
1770                 return ret;
1771
1772         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1773         if (ret)
1774                 return ret;
1775
1776         regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
1777
1778         ret = wait_for_pll_enable_lock(pll);
1779         if (ret)
1780                 return ret;
1781
1782         /* Enable the PLL outputs */
1783         ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
1784         if (ret)
1785                 return ret;
1786
1787         /* Enable the global PLL outputs */
1788         return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
1789 }
1790
1791 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw)
1792 {
1793         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1794         u32 val;
1795         int ret;
1796
1797         ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1798         if (ret)
1799                 return;
1800
1801         /* If in FSM mode, just unvote it */
1802         if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1803                 clk_disable_regmap(hw);
1804                 return;
1805         }
1806
1807         /* Disable the global PLL output */
1808         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1809         if (ret)
1810                 return;
1811
1812         /* Disable the PLL outputs */
1813         ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1814         if (ret)
1815                 return;
1816
1817         /* Place the PLL mode in STANDBY */
1818         regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
1819 }
1820
1821 /*
1822  * The Lucid 5LPE PLL requires a power-on self-calibration which happens
1823  * when the PLL comes out of reset. Calibrate in case it is not completed.
1824  */
1825 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw)
1826 {
1827         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1828         struct clk_hw *p;
1829         u32 val = 0;
1830         int ret;
1831
1832         /* Return early if calibration is not needed. */
1833         regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1834         if (val & LUCID_5LPE_PCAL_DONE)
1835                 return 0;
1836
1837         p = clk_hw_get_parent(hw);
1838         if (!p)
1839                 return -EINVAL;
1840
1841         ret = alpha_pll_lucid_5lpe_enable(hw);
1842         if (ret)
1843                 return ret;
1844
1845         alpha_pll_lucid_5lpe_disable(hw);
1846
1847         return 0;
1848 }
1849
1850 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
1851                                          unsigned long prate)
1852 {
1853         return __alpha_pll_trion_set_rate(hw, rate, prate,
1854                                           LUCID_5LPE_PLL_LATCH_INPUT,
1855                                           LUCID_5LPE_ALPHA_PLL_ACK_LATCH);
1856 }
1857
1858 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1859                                             unsigned long parent_rate,
1860                                             unsigned long enable_vote_run)
1861 {
1862         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1863         struct regmap *regmap = pll->clkr.regmap;
1864         int i, val, div, ret;
1865         u32 mask;
1866
1867         /*
1868          * If the PLL is in FSM mode, then treat set_rate callback as a
1869          * no-operation.
1870          */
1871         ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
1872         if (ret)
1873                 return ret;
1874
1875         if (val & enable_vote_run)
1876                 return 0;
1877
1878         if (!pll->post_div_table) {
1879                 pr_err("Missing the post_div_table for the %s PLL\n",
1880                        clk_hw_get_name(&pll->clkr.hw));
1881                 return -EINVAL;
1882         }
1883
1884         div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
1885         for (i = 0; i < pll->num_post_div; i++) {
1886                 if (pll->post_div_table[i].div == div) {
1887                         val = pll->post_div_table[i].val;
1888                         break;
1889                 }
1890         }
1891
1892         mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift);
1893         return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1894                                   mask, val << pll->post_div_shift);
1895 }
1896
1897 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1898                                                unsigned long parent_rate)
1899 {
1900         return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN);
1901 }
1902
1903 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
1904         .prepare = alpha_pll_lucid_5lpe_prepare,
1905         .enable = alpha_pll_lucid_5lpe_enable,
1906         .disable = alpha_pll_lucid_5lpe_disable,
1907         .is_enabled = clk_trion_pll_is_enabled,
1908         .recalc_rate = clk_trion_pll_recalc_rate,
1909         .round_rate = clk_alpha_pll_round_rate,
1910         .set_rate = alpha_pll_lucid_5lpe_set_rate,
1911 };
1912 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops);
1913
1914 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
1915         .enable = alpha_pll_lucid_5lpe_enable,
1916         .disable = alpha_pll_lucid_5lpe_disable,
1917         .is_enabled = clk_trion_pll_is_enabled,
1918         .recalc_rate = clk_trion_pll_recalc_rate,
1919         .round_rate = clk_alpha_pll_round_rate,
1920 };
1921 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops);
1922
1923 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
1924         .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1925         .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1926         .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
1927 };
1928 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
1929
1930 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1931                              const struct alpha_pll_config *config)
1932 {
1933         clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1934         clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1935         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
1936         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
1937         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
1938         clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
1939         clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
1940         clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
1941         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
1942         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
1943         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
1944
1945         regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0);
1946
1947         /* Disable PLL output */
1948         regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1949
1950         /* Set operation mode to OFF */
1951         regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1952
1953         /* Place the PLL in STANDBY mode */
1954         regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1955 }
1956 EXPORT_SYMBOL_GPL(clk_zonda_pll_configure);
1957
1958 static int clk_zonda_pll_enable(struct clk_hw *hw)
1959 {
1960         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1961         struct regmap *regmap = pll->clkr.regmap;
1962         u32 val;
1963         int ret;
1964
1965         regmap_read(regmap, PLL_MODE(pll), &val);
1966
1967         /* If in FSM mode, just vote for it */
1968         if (val & PLL_VOTE_FSM_ENA) {
1969                 ret = clk_enable_regmap(hw);
1970                 if (ret)
1971                         return ret;
1972                 return wait_for_pll_enable_active(pll);
1973         }
1974
1975         /* Get the PLL out of bypass mode */
1976         regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
1977
1978         /*
1979          * H/W requires a 1us delay between disabling the bypass and
1980          * de-asserting the reset.
1981          */
1982         udelay(1);
1983
1984         regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1985
1986         /* Set operation mode to RUN */
1987         regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1988
1989         regmap_read(regmap, PLL_TEST_CTL(pll), &val);
1990
1991         /* If cfa mode then poll for freq lock */
1992         if (val & ZONDA_STAY_IN_CFA)
1993                 ret = wait_for_zonda_pll_freq_lock(pll);
1994         else
1995                 ret = wait_for_pll_enable_lock(pll);
1996         if (ret)
1997                 return ret;
1998
1999         /* Enable the PLL outputs */
2000         regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
2001
2002         /* Enable the global PLL outputs */
2003         regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2004
2005         return 0;
2006 }
2007
2008 static void clk_zonda_pll_disable(struct clk_hw *hw)
2009 {
2010         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2011         struct regmap *regmap = pll->clkr.regmap;
2012         u32 val;
2013
2014         regmap_read(regmap, PLL_MODE(pll), &val);
2015
2016         /* If in FSM mode, just unvote it */
2017         if (val & PLL_VOTE_FSM_ENA) {
2018                 clk_disable_regmap(hw);
2019                 return;
2020         }
2021
2022         /* Disable the global PLL output */
2023         regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2024
2025         /* Disable the PLL outputs */
2026         regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);
2027
2028         /* Put the PLL in bypass and reset */
2029         regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);
2030
2031         /* Place the PLL mode in OFF state */
2032         regmap_write(regmap, PLL_OPMODE(pll), 0x0);
2033 }
2034
2035 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
2036                                   unsigned long prate)
2037 {
2038         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2039         unsigned long rrate;
2040         u32 test_ctl_val;
2041         u32 l, alpha_width = pll_alpha_width(pll);
2042         u64 a;
2043         int ret;
2044
2045         rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
2046
2047         ret = alpha_pll_check_rate_margin(hw, rrate, rate);
2048         if (ret < 0)
2049                 return ret;
2050
2051         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2052         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2053
2054         /* Wait before polling for the frequency latch */
2055         udelay(5);
2056
2057         /* Read stay in cfa mode */
2058         regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
2059
2060         /* If cfa mode then poll for freq lock */
2061         if (test_ctl_val & ZONDA_STAY_IN_CFA)
2062                 ret = wait_for_zonda_pll_freq_lock(pll);
2063         else
2064                 ret = wait_for_pll_enable_lock(pll);
2065         if (ret)
2066                 return ret;
2067
2068         /* Wait for PLL output to stabilize */
2069         udelay(100);
2070         return 0;
2071 }
2072
2073 const struct clk_ops clk_alpha_pll_zonda_ops = {
2074         .enable = clk_zonda_pll_enable,
2075         .disable = clk_zonda_pll_disable,
2076         .is_enabled = clk_trion_pll_is_enabled,
2077         .recalc_rate = clk_trion_pll_recalc_rate,
2078         .round_rate = clk_alpha_pll_round_rate,
2079         .set_rate = clk_zonda_pll_set_rate,
2080 };
2081 EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
2082
2083 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2084                                  const struct alpha_pll_config *config)
2085 {
2086         u32 lval = config->l;
2087
2088         lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
2089         clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
2090         clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2091         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2092         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2093         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2094         clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2095         clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2096         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2097         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2098         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2099
2100         /* Disable PLL output */
2101         regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2102
2103         /* Set operation mode to STANDBY and de-assert the reset */
2104         regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2105         regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2106 }
2107 EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);
2108
2109 static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
2110 {
2111         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2112         struct regmap *regmap = pll->clkr.regmap;
2113         u32 val;
2114         int ret;
2115
2116         ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2117         if (ret)
2118                 return ret;
2119
2120         /* If in FSM mode, just vote for it */
2121         if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2122                 ret = clk_enable_regmap(hw);
2123                 if (ret)
2124                         return ret;
2125                 return wait_for_pll_enable_lock(pll);
2126         }
2127
2128         /* Check if PLL is already enabled */
2129         ret = trion_pll_is_enabled(pll, regmap);
2130         if (ret < 0) {
2131                 return ret;
2132         } else if (ret) {
2133                 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw));
2134                 return 0;
2135         }
2136
2137         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2138         if (ret)
2139                 return ret;
2140
2141         /* Set operation mode to RUN */
2142         regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2143
2144         ret = wait_for_pll_enable_lock(pll);
2145         if (ret)
2146                 return ret;
2147
2148         /* Enable the PLL outputs */
2149         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
2150         if (ret)
2151                 return ret;
2152
2153         /* Enable the global PLL outputs */
2154         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2155         if (ret)
2156                 return ret;
2157
2158         /* Ensure that the write above goes through before returning. */
2159         mb();
2160         return ret;
2161 }
2162
2163 static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset)
2164 {
2165         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2166         struct regmap *regmap = pll->clkr.regmap;
2167         u32 val;
2168         int ret;
2169
2170         ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2171         if (ret)
2172                 return;
2173
2174         /* If in FSM mode, just unvote it */
2175         if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2176                 clk_disable_regmap(hw);
2177                 return;
2178         }
2179
2180         /* Disable the global PLL output */
2181         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2182         if (ret)
2183                 return;
2184
2185         /* Disable the PLL outputs */
2186         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
2187         if (ret)
2188                 return;
2189
2190         /* Place the PLL mode in STANDBY */
2191         regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2192
2193         if (reset)
2194                 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0);
2195 }
2196
2197 static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset)
2198 {
2199         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2200         struct clk_hw *p;
2201         u32 val = 0;
2202         int ret;
2203
2204         /* Return early if calibration is not needed. */
2205         regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
2206         if (!(val & LUCID_EVO_PCAL_NOT_DONE))
2207                 return 0;
2208
2209         p = clk_hw_get_parent(hw);
2210         if (!p)
2211                 return -EINVAL;
2212
2213         ret = alpha_pll_lucid_evo_enable(hw);
2214         if (ret)
2215                 return ret;
2216
2217         _alpha_pll_lucid_evo_disable(hw, reset);
2218
2219         return 0;
2220 }
2221
2222 static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
2223 {
2224         _alpha_pll_lucid_evo_disable(hw, false);
2225 }
2226
2227 static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw)
2228 {
2229         return _alpha_pll_lucid_evo_prepare(hw, false);
2230 }
2231
2232 static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw)
2233 {
2234         _alpha_pll_lucid_evo_disable(hw, true);
2235 }
2236
2237 static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw)
2238 {
2239         return _alpha_pll_lucid_evo_prepare(hw, true);
2240 }
2241
2242 static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw,
2243                                                      unsigned long parent_rate)
2244 {
2245         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2246         struct regmap *regmap = pll->clkr.regmap;
2247         u32 l, frac;
2248
2249         regmap_read(regmap, PLL_L_VAL(pll), &l);
2250         l &= LUCID_EVO_PLL_L_VAL_MASK;
2251         regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
2252
2253         return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll));
2254 }
2255
2256 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2257                                               unsigned long parent_rate)
2258 {
2259         return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN);
2260 }
2261
2262 const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = {
2263         .enable = alpha_pll_lucid_evo_enable,
2264         .disable = alpha_pll_lucid_evo_disable,
2265         .is_enabled = clk_trion_pll_is_enabled,
2266         .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2267         .round_rate = clk_alpha_pll_round_rate,
2268 };
2269 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops);
2270
2271 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
2272         .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
2273         .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
2274         .set_rate = clk_lucid_evo_pll_postdiv_set_rate,
2275 };
2276 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);
2277
2278 const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
2279         .prepare = alpha_pll_lucid_evo_prepare,
2280         .enable = alpha_pll_lucid_evo_enable,
2281         .disable = alpha_pll_lucid_evo_disable,
2282         .is_enabled = clk_trion_pll_is_enabled,
2283         .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2284         .round_rate = clk_alpha_pll_round_rate,
2285         .set_rate = alpha_pll_lucid_5lpe_set_rate,
2286 };
2287 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);
2288
2289 const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = {
2290         .prepare = alpha_pll_reset_lucid_evo_prepare,
2291         .enable = alpha_pll_lucid_evo_enable,
2292         .disable = alpha_pll_reset_lucid_evo_disable,
2293         .is_enabled = clk_trion_pll_is_enabled,
2294         .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2295         .round_rate = clk_alpha_pll_round_rate,
2296         .set_rate = alpha_pll_lucid_5lpe_set_rate,
2297 };
2298 EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops);
2299
2300 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2301                                   const struct alpha_pll_config *config)
2302 {
2303         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2304         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2305         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2306         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2307         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2308         clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2309         clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2310         clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2311
2312         regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2313
2314         regmap_update_bits(regmap, PLL_MODE(pll),
2315                            PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL,
2316                            PLL_RESET_N | PLL_BYPASSNL);
2317 }
2318 EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure);
2319
2320 static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw,
2321                                                     unsigned long parent_rate)
2322 {
2323         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2324         u32 l;
2325
2326         regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
2327
2328         return parent_rate * l;
2329 }
2330
2331 static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
2332                                           unsigned long *prate)
2333 {
2334         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2335         unsigned long min_freq, max_freq;
2336         u32 l;
2337         u64 a;
2338
2339         rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);
2340         if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
2341                 return rate;
2342
2343         min_freq = pll->vco_table[0].min_freq;
2344         max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
2345
2346         return clamp(rate, min_freq, max_freq);
2347 }
2348
2349 const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
2350         .enable = alpha_pll_lucid_5lpe_enable,
2351         .disable = alpha_pll_lucid_5lpe_disable,
2352         .is_enabled = clk_trion_pll_is_enabled,
2353         .recalc_rate = clk_rivian_evo_pll_recalc_rate,
2354         .round_rate = clk_rivian_evo_pll_round_rate,
2355 };
2356 EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);
2357
2358 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2359                                const struct alpha_pll_config *config)
2360 {
2361         u32 val, val_u, mask, mask_u;
2362
2363         regmap_write(regmap, PLL_L_VAL(pll), config->l);
2364         regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2365         regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2366
2367         if (pll_has_64bit_config(pll))
2368                 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
2369                              config->config_ctl_hi_val);
2370
2371         if (pll_alpha_width(pll) > 32)
2372                 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
2373
2374         val = config->main_output_mask;
2375         val |= config->aux_output_mask;
2376         val |= config->aux2_output_mask;
2377         val |= config->early_output_mask;
2378         val |= config->pre_div_val;
2379         val |= config->post_div_val;
2380         val |= config->vco_val;
2381         val |= config->alpha_en_mask;
2382         val |= config->alpha_mode_mask;
2383
2384         mask = config->main_output_mask;
2385         mask |= config->aux_output_mask;
2386         mask |= config->aux2_output_mask;
2387         mask |= config->early_output_mask;
2388         mask |= config->pre_div_mask;
2389         mask |= config->post_div_mask;
2390         mask |= config->vco_mask;
2391         mask |= config->alpha_en_mask;
2392         mask |= config->alpha_mode_mask;
2393
2394         regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
2395
2396         /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */
2397         val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT;
2398         val_u |= config->lock_det;
2399
2400         mask_u = config->status_mask;
2401         mask_u |= config->lock_det;
2402
2403         regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u);
2404         regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2405         regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2406
2407         if (pll->flags & SUPPORTS_FSM_MODE)
2408                 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
2409 }
2410 EXPORT_SYMBOL_GPL(clk_stromer_pll_configure);
2411
2412 static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw,
2413                                                 struct clk_rate_request *req)
2414 {
2415         u32 l;
2416         u64 a;
2417
2418         req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate,
2419                                          &l, &a, ALPHA_REG_BITWIDTH);
2420
2421         return 0;
2422 }
2423
2424 static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate,
2425                                           unsigned long prate)
2426 {
2427         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2428         int ret;
2429         u32 l;
2430         u64 a;
2431
2432         rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH);
2433
2434         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2435         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2436         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
2437                      a >> ALPHA_BITWIDTH);
2438
2439         regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
2440                            PLL_ALPHA_EN, PLL_ALPHA_EN);
2441
2442         if (!clk_hw_is_enabled(hw))
2443                 return 0;
2444
2445         /*
2446          * Stromer PLL supports Dynamic programming.
2447          * It allows the PLL frequency to be changed on-the-fly without first
2448          * execution of a shutdown procedure followed by a bring up procedure.
2449          */
2450         regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
2451                            PLL_UPDATE);
2452
2453         ret = wait_for_pll_update(pll);
2454         if (ret)
2455                 return ret;
2456
2457         return wait_for_pll_enable_lock(pll);
2458 }
2459
2460 const struct clk_ops clk_alpha_pll_stromer_ops = {
2461         .enable = clk_alpha_pll_enable,
2462         .disable = clk_alpha_pll_disable,
2463         .is_enabled = clk_alpha_pll_is_enabled,
2464         .recalc_rate = clk_alpha_pll_recalc_rate,
2465         .determine_rate = clk_alpha_pll_stromer_determine_rate,
2466         .set_rate = clk_alpha_pll_stromer_set_rate,
2467 };
2468 EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops);