drivers/clk/mediatek/clk-mt6797.c

   1 /*
   2  * Copyright (c) 2016 MediaTek Inc.
   3  * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_device.h>
  18 #include <linux/platform_device.h>
  19
  20 #include "clk-mtk.h"
  21 #include "clk-gate.h"
  22
  23 #include <dt-bindings/clock/mt6797-clk.h>
  24
  25 /*
  26  * For some clocks, we don't care what their actual rates are. And these
  27  * clocks may change their rate on different products or different scenarios.
  28  * So we model these clocks' rate as 0, to denote it's not an actual rate.
  29  */
  30
  31 static DEFINE_SPINLOCK(mt6797_clk_lock);
  32
  33 static const struct mtk_fixed_factor top_fixed_divs[] = {
  34         FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1),
  35         FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
  36         FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
  37         FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
  38         FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
  39         FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
  40         FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
  41         FACTOR(CLK_TOP_SYSPLL_D3_D3, "syspll_d3_d3", "syspll_d3", 1, 3),
  42         FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
  43         FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
  44         FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
  45         FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
  46         FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
  47         FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
  48         FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
  49         FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
  50         FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
  51         FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1),
  52         FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
  53         FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
  54         FACTOR(CLK_TOP_SSUSB_PHY_48M_CK, "ssusb_phy_48m_ck", "univpll", 1, 1),
  55         FACTOR(CLK_TOP_USB_PHY48M_CK, "usb_phy48m_ck", "univpll", 1, 1),
  56         FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
  57         FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
  58         FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
  59         FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
  60         FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
  61         FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 2),
  62         FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 4),
  63         FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 8),
  64         FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
  65         FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
  66         FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
  67         FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
  68         FACTOR(CLK_TOP_ULPOSC_CK_ORG, "ulposc_ck_org", "ulposc", 1, 1),
  69         FACTOR(CLK_TOP_ULPOSC_CK, "ulposc_ck", "ulposc_ck_org", 1, 3),
  70         FACTOR(CLK_TOP_ULPOSC_D2, "ulposc_d2", "ulposc_ck", 1, 2),
  71         FACTOR(CLK_TOP_ULPOSC_D3, "ulposc_d3", "ulposc_ck", 1, 4),
  72         FACTOR(CLK_TOP_ULPOSC_D4, "ulposc_d4", "ulposc_ck", 1, 8),
  73         FACTOR(CLK_TOP_ULPOSC_D8, "ulposc_d8", "ulposc_ck", 1, 10),
  74         FACTOR(CLK_TOP_ULPOSC_D10, "ulposc_d10", "ulposc_ck_org", 1, 1),
  75         FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
  76         FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
  77         FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
  78         FACTOR(CLK_TOP_MFGPLL_D2, "mfgpll_d2", "mfgpll_ck", 1, 2),
  79         FACTOR(CLK_TOP_IMGPLL_CK, "imgpll_ck", "imgpll", 1, 1),
  80         FACTOR(CLK_TOP_IMGPLL_D2, "imgpll_d2", "imgpll_ck", 1, 2),
  81         FACTOR(CLK_TOP_IMGPLL_D4, "imgpll_d4", "imgpll_ck", 1, 4),
  82         FACTOR(CLK_TOP_CODECPLL_CK, "codecpll_ck", "codecpll", 1, 1),
  83         FACTOR(CLK_TOP_CODECPLL_D2, "codecpll_d2", "codecpll_ck", 1, 2),
  84         FACTOR(CLK_TOP_VDECPLL_CK, "vdecpll_ck", "vdecpll", 1, 1),
  85         FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
  86         FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
  87         FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4),
  88         FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8),
  89         FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_ck", 1, 16),
  90         FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
  91         FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
  92         FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4),
  93         FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll_ck", 1, 8),
  94 };
  95
  96 static const char * const axi_parents[] = {
  97         "clk26m",
  98         "syspll_d7",
  99         "ulposc_axi_ck_mux",
 100 };
 101
 102 static const char * const ulposc_axi_ck_mux_parents[] = {
 103         "syspll1_d4",
 104         "ulposc_axi_ck_mux_pre",
 105 };
 106
 107 static const char * const ulposc_axi_ck_mux_pre_parents[] = {
 108         "ulposc_d2",
 109         "ulposc_d3",
 110 };
 111
 112 static const char * const ddrphycfg_parents[] = {
 113         "clk26m",
 114         "syspll3_d2",
 115         "syspll2_d4",
 116         "syspll1_d8",
 117 };
 118
 119 static const char * const mm_parents[] = {
 120         "clk26m",
 121         "imgpll_ck",
 122         "univpll1_d2",
 123         "syspll1_d2",
 124 };
 125
 126 static const char * const pwm_parents[] = {
 127         "clk26m",
 128         "univpll2_d4",
 129         "ulposc_d2",
 130         "ulposc_d3",
 131         "ulposc_d8",
 132         "ulposc_d10",
 133         "ulposc_d4",
 134 };
 135
 136 static const char * const vdec_parents[] = {
 137         "clk26m",
 138         "vdecpll_ck",
 139         "imgpll_ck",
 140         "syspll_d3",
 141         "univpll_d5",
 142         "clk26m",
 143         "clk26m",
 144 };
 145
 146 static const char * const venc_parents[] = {
 147         "clk26m",
 148         "codecpll_ck",
 149         "syspll_d3",
 150 };
 151
 152 static const char * const mfg_parents[] = {
 153         "clk26m",
 154         "mfgpll_ck",
 155         "syspll_d3",
 156         "univpll_d3",
 157 };
 158
 159 static const char * const camtg[] = {
 160         "clk26m",
 161         "univpll_d26",
 162         "univpll2_d2",
 163 };
 164
 165 static const char * const uart_parents[] = {
 166         "clk26m",
 167         "univpll2_d8",
 168 };
 169
 170 static const char * const spi_parents[] = {
 171         "clk26m",
 172         "syspll3_d2",
 173         "syspll2_d4",
 174         "ulposc_spi_ck_mux",
 175 };
 176
 177 static const char * const ulposc_spi_ck_mux_parents[] = {
 178         "ulposc_d2",
 179         "ulposc_d3",
 180 };
 181
 182 static const char * const usb20_parents[] = {
 183         "clk26m",
 184         "univpll1_d8",
 185         "syspll4_d2",
 186 };
 187
 188 static const char * const msdc50_0_hclk_parents[] = {
 189         "clk26m",
 190         "syspll1_d2",
 191         "syspll2_d2",
 192         "syspll4_d2",
 193 };
 194
 195 static const char * const msdc50_0_parents[] = {
 196         "clk26m",
 197         "msdcpll",
 198         "syspll_d3",
 199         "univpll1_d4",
 200         "syspll2_d2",
 201         "syspll_d7",
 202         "msdcpll_d2",
 203         "univpll1_d2",
 204         "univpll_d3",
 205 };
 206
 207 static const char * const msdc30_1_parents[] = {
 208         "clk26m",
 209         "univpll2_d2",
 210         "msdcpll_d2",
 211         "univpll1_d4",
 212         "syspll2_d2",
 213         "syspll_d7",
 214         "univpll_d7",
 215 };
 216
 217 static const char * const msdc30_2_parents[] = {
 218         "clk26m",
 219         "univpll2_d8",
 220         "syspll2_d8",
 221         "syspll1_d8",
 222         "msdcpll_d8",
 223         "syspll3_d4",
 224         "univpll_d26",
 225 };
 226
 227 static const char * const audio_parents[] = {
 228         "clk26m",
 229         "syspll3_d4",
 230         "syspll4_d4",
 231         "syspll1_d16",
 232 };
 233
 234 static const char * const aud_intbus_parents[] = {
 235         "clk26m",
 236         "syspll1_d4",
 237         "syspll4_d2",
 238 };
 239
 240 static const char * const pmicspi_parents[] = {
 241         "clk26m",
 242         "univpll_d26",
 243         "syspll3_d4",
 244         "syspll1_d8",
 245         "ulposc_d4",
 246         "ulposc_d8",
 247         "syspll2_d8",
 248 };
 249
 250 static const char * const scp_parents[] = {
 251         "clk26m",
 252         "syspll_d3",
 253         "ulposc_ck",
 254         "univpll_d5",
 255 };
 256
 257 static const char * const atb_parents[] = {
 258         "clk26m",
 259         "syspll1_d2",
 260         "syspll_d5",
 261 };
 262
 263 static const char * const mjc_parents[] = {
 264         "clk26m",
 265         "imgpll_ck",
 266         "univpll_d5",
 267         "syspll1_d2",
 268 };
 269
 270 static const char * const dpi0_parents[] = {
 271         "clk26m",
 272         "tvdpll_d2",
 273         "tvdpll_d4",
 274         "tvdpll_d8",
 275         "tvdpll_d16",
 276         "clk26m",
 277         "clk26m",
 278 };
 279
 280 static const char * const aud_1_parents[] = {
 281         "clk26m",
 282         "apll1_ck",
 283 };
 284
 285 static const char * const aud_2_parents[] = {
 286         "clk26m",
 287         "apll2_ck",
 288 };
 289
 290 static const char * const ssusb_top_sys_parents[] = {
 291         "clk26m",
 292         "univpll3_d2",
 293 };
 294
 295 static const char * const spm_parents[] = {
 296         "clk26m",
 297         "syspll1_d8",
 298 };
 299
 300 static const char * const bsi_spi_parents[] = {
 301         "clk26m",
 302         "syspll_d3_d3",
 303         "syspll1_d4",
 304         "syspll_d7",
 305 };
 306
 307 static const char * const audio_h_parents[] = {
 308         "clk26m",
 309         "apll2_ck",
 310         "apll1_ck",
 311         "univpll_d7",
 312 };
 313
 314 static const char * const mfg_52m_parents[] = {
 315         "clk26m",
 316         "univpll2_d8",
 317         "univpll2_d4",
 318         "univpll2_d4",
 319 };
 320
 321 static const char * const anc_md32_parents[] = {
 322         "clk26m",
 323         "syspll1_d2",
 324         "univpll_d5",
 325 };
 326
 327 /*
 328  * Clock mux ddrphycfg is needed by the DRAM controller. We mark it as
 329  * critical as otherwise the system will hang after boot.
 330  */
 331 static const struct mtk_composite top_muxes[] = {
 332         MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE, "ulposc_axi_ck_mux_pre",
 333             ulposc_axi_ck_mux_pre_parents, 0x0040, 3, 1),
 334         MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX, "ulposc_axi_ck_mux",
 335             ulposc_axi_ck_mux_parents, 0x0040, 2, 1),
 336         MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
 337             0x0040, 0, 2),
 338         MUX_FLAGS(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
 339                   0x0040, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
 340         MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
 341             0x0040, 24, 2),
 342         MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
 343         MUX_GATE(CLK_TOP_MUX_VDEC, "vdec_sel", vdec_parents, 0x0050, 8, 3, 15),
 344         MUX_GATE(CLK_TOP_MUX_VENC, "venc_sel", venc_parents, 0x0050, 16, 2, 23),
 345         MUX_GATE(CLK_TOP_MUX_MFG, "mfg_sel", mfg_parents, 0x0050, 24, 2, 31),
 346         MUX_GATE(CLK_TOP_MUX_CAMTG, "camtg_sel", camtg, 0x0060, 0, 2, 7),
 347         MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
 348         MUX_GATE(CLK_TOP_MUX_SPI, "spi_sel", spi_parents, 0x0060, 16, 2, 23),
 349         MUX(CLK_TOP_MUX_ULPOSC_SPI_CK_MUX, "ulposc_spi_ck_mux",
 350             ulposc_spi_ck_mux_parents, 0x0060, 18, 1),
 351         MUX_GATE(CLK_TOP_MUX_USB20, "usb20_sel", usb20_parents,
 352                  0x0060, 24, 2, 31),
 353         MUX(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_0_hclk_sel",
 354             msdc50_0_hclk_parents, 0x0070, 8, 2),
 355         MUX_GATE(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", msdc50_0_parents,
 356                  0x0070, 16, 4, 23),
 357         MUX_GATE(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", msdc30_1_parents,
 358                  0x0070, 24, 3, 31),
 359         MUX_GATE(CLK_TOP_MUX_MSDC30_2, "msdc30_2_sel", msdc30_2_parents,
 360                  0x0080, 0, 3, 7),
 361         MUX_GATE(CLK_TOP_MUX_AUDIO, "audio_sel", audio_parents,
 362                  0x0080, 16, 2, 23),
 363         MUX(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", aud_intbus_parents,
 364             0x0080, 24, 2),
 365         MUX(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", pmicspi_parents,
 366             0x0090, 0, 3),
 367         MUX(CLK_TOP_MUX_SCP, "scp_sel", scp_parents,
 368             0x0090, 8, 2),
 369         MUX(CLK_TOP_MUX_ATB, "atb_sel", atb_parents,
 370             0x0090, 16, 2),
 371         MUX_GATE(CLK_TOP_MUX_MJC, "mjc_sel", mjc_parents, 0x0090, 24, 2, 31),
 372         MUX_GATE(CLK_TOP_MUX_DPI0, "dpi0_sel", dpi0_parents, 0x00A0, 0, 3, 7),
 373         MUX_GATE(CLK_TOP_MUX_AUD_1, "aud_1_sel", aud_1_parents,
 374                  0x00A0, 16, 1, 23),
 375         MUX_GATE(CLK_TOP_MUX_AUD_2, "aud_2_sel", aud_2_parents,
 376                  0x00A0, 24, 1, 31),
 377         MUX(CLK_TOP_MUX_SSUSB_TOP_SYS, "ssusb_top_sys_sel",
 378             ssusb_top_sys_parents, 0x00B0, 8, 1),
 379         MUX(CLK_TOP_MUX_SPM, "spm_sel", spm_parents,
 380             0x00C0, 0, 1),
 381         MUX(CLK_TOP_MUX_BSI_SPI, "bsi_spi_sel", bsi_spi_parents,
 382             0x00C0, 8, 2),
 383         MUX_GATE(CLK_TOP_MUX_AUDIO_H, "audio_h_sel", audio_h_parents,
 384                  0x00C0, 16, 2, 23),
 385         MUX_GATE(CLK_TOP_MUX_ANC_MD32, "anc_md32_sel", anc_md32_parents,
 386                  0x00C0, 24, 2, 31),
 387         MUX(CLK_TOP_MUX_MFG_52M, "mfg_52m_sel", mfg_52m_parents,
 388             0x0104, 1, 2),
 389 };
 390
 391 static int mtk_topckgen_init(struct platform_device *pdev)
 392 {
 393         struct clk_onecell_data *clk_data;
 394         void __iomem *base;
 395         struct device_node *node = pdev->dev.of_node;
 396         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 397
 398         base = devm_ioremap_resource(&pdev->dev, res);
 399         if (IS_ERR(base))
 400                 return PTR_ERR(base);
 401
 402         clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
 403
 404         mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
 405                                  clk_data);
 406
 407         mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
 408                                     &mt6797_clk_lock, clk_data);
 409
 410         return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 411 }
 412
 413 static const struct mtk_gate_regs infra0_cg_regs = {
 414         .set_ofs = 0x0080,
 415         .clr_ofs = 0x0084,
 416         .sta_ofs = 0x0090,
 417 };
 418
 419 static const struct mtk_gate_regs infra1_cg_regs = {
 420         .set_ofs = 0x0088,
 421         .clr_ofs = 0x008c,
 422         .sta_ofs = 0x0094,
 423 };
 424
 425 static const struct mtk_gate_regs infra2_cg_regs = {
 426         .set_ofs = 0x00a8,
 427         .clr_ofs = 0x00ac,
 428         .sta_ofs = 0x00b0,
 429 };
 430
 431 #define GATE_ICG0(_id, _name, _parent, _shift) {                \
 432         .id = _id,                                              \
 433         .name = _name,                                          \
 434         .parent_name = _parent,                                 \
 435         .regs = &infra0_cg_regs,                                \
 436         .shift = _shift,                                        \
 437         .ops = &mtk_clk_gate_ops_setclr,                        \
 438 }
 439
 440 #define GATE_ICG1(_id, _name, _parent, _shift)                  \
 441         GATE_ICG1_FLAGS(_id, _name, _parent, _shift, 0)
 442
 443 #define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) {  \
 444         .id = _id,                                              \
 445         .name = _name,                                          \
 446         .parent_name = _parent,                                 \
 447         .regs = &infra1_cg_regs,                                \
 448         .shift = _shift,                                        \
 449         .ops = &mtk_clk_gate_ops_setclr,                        \
 450         .flags = _flags,                                        \
 451 }
 452
 453 #define GATE_ICG2(_id, _name, _parent, _shift)                  \
 454         GATE_ICG2_FLAGS(_id, _name, _parent, _shift, 0)
 455
 456 #define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) {  \
 457         .id = _id,                                              \
 458         .name = _name,                                          \
 459         .parent_name = _parent,                                 \
 460         .regs = &infra2_cg_regs,                                \
 461         .shift = _shift,                                        \
 462         .ops = &mtk_clk_gate_ops_setclr,                        \
 463         .flags = _flags,                                        \
 464 }
 465
 466 /*
 467  * Clock gates dramc and dramc_b are needed by the DRAM controller.
 468  * We mark them as critical as otherwise the system will hang after boot.
 469  */
 470 static const struct mtk_gate infra_clks[] = {
 471         GATE_ICG0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "ulposc", 0),
 472         GATE_ICG0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pmicspi_sel", 1),
 473         GATE_ICG0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pmicspi_sel", 2),
 474         GATE_ICG0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pmicspi_sel", 3),
 475         GATE_ICG0(CLK_INFRA_SCP, "infra_scp", "scp_sel", 4),
 476         GATE_ICG0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
 477         GATE_ICG0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
 478         GATE_ICG0(CLK_INFRA_SEJ_13M, "infra_sej_13m", "clk26m", 7),
 479         GATE_ICG0(CLK_INFRA_ICUSB, "infra_icusb", "usb20_sel", 8),
 480         GATE_ICG0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 9),
 481         GATE_ICG0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
 482         GATE_ICG0(CLK_INFRA_I2C0, "infra_i2c0", "axi_sel", 11),
 483         GATE_ICG0(CLK_INFRA_I2C1, "infra_i2c1", "axi_sel", 12),
 484         GATE_ICG0(CLK_INFRA_I2C2, "infra_i2c2", "axi_sel", 13),
 485         GATE_ICG0(CLK_INFRA_I2C3, "infra_i2c3", "axi_sel", 14),
 486         GATE_ICG0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk", "axi_sel", 15),
 487         GATE_ICG0(CLK_INFRA_PWM1, "infra_pwm1", "axi_sel", 16),
 488         GATE_ICG0(CLK_INFRA_PWM2, "infra_pwm2", "axi_sel", 17),
 489         GATE_ICG0(CLK_INFRA_PWM3, "infra_pwm3", "axi_sel", 18),
 490         GATE_ICG0(CLK_INFRA_PWM4, "infra_pwm4", "axi_sel", 19),
 491         GATE_ICG0(CLK_INFRA_PWM, "infra_pwm", "axi_sel", 21),
 492         GATE_ICG0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
 493         GATE_ICG0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
 494         GATE_ICG0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
 495         GATE_ICG0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
 496         GATE_ICG0(CLK_INFRA_MD2MD_CCIF_0, "infra_md2md_ccif_0", "axi_sel", 27),
 497         GATE_ICG0(CLK_INFRA_MD2MD_CCIF_1, "infra_md2md_ccif_1", "axi_sel", 28),
 498         GATE_ICG0(CLK_INFRA_MD2MD_CCIF_2, "infra_md2md_ccif_2", "axi_sel", 29),
 499         GATE_ICG0(CLK_INFRA_FHCTL, "infra_fhctl", "clk26m", 30),
 500         GATE_ICG0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31),
 501         GATE_ICG1(CLK_INFRA_MD2MD_CCIF_3, "infra_md2md_ccif_3", "axi_sel", 0),
 502         GATE_ICG1(CLK_INFRA_SPI, "infra_spi", "spi_sel", 1),
 503         GATE_ICG1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_sel", 2),
 504         GATE_ICG1(CLK_INFRA_MD2MD_CCIF_4, "infra_md2md_ccif_4", "axi_sel", 3),
 505         GATE_ICG1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc30_1_sel", 4),
 506         GATE_ICG1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc30_2_sel", 5),
 507         GATE_ICG1(CLK_INFRA_MD2MD_CCIF_5, "infra_md2md_ccif_5", "axi_sel", 7),
 508         GATE_ICG1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8),
 509         GATE_ICG1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9),
 510         GATE_ICG1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10),
 511         GATE_ICG1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11),
 512         GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_0, "infra_ap_c2k_ccif_0",
 513                   "axi_sel", 12),
 514         GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_1, "infra_ap_c2k_ccif_1",
 515                   "axi_sel", 13),
 516         GATE_ICG1(CLK_INFRA_CLDMA, "infra_cldma", "axi_sel", 16),
 517         GATE_ICG1(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "pwm_sel", 17),
 518         GATE_ICG1(CLK_INFRA_AP_DMA, "infra_ap_dma", "axi_sel", 18),
 519         GATE_ICG1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20),
 520         GATE_ICG1(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "mm_sel", 22),
 521         GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
 522         GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
 523         GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
 524         GATE_ICG1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
 525                         "clk26m", 31, CLK_IS_CRITICAL),
 526         GATE_ICG2(CLK_INFRA_I2C4, "infra_i2c4", "axi_sel", 0),
 527         GATE_ICG2(CLK_INFRA_I2C_APPM, "infra_i2c_appm", "axi_sel", 1),
 528         GATE_ICG2(CLK_INFRA_I2C_GPUPM, "infra_i2c_gpupm", "axi_sel", 2),
 529         GATE_ICG2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "axi_sel", 3),
 530         GATE_ICG2(CLK_INFRA_I2C2_ARB, "infra_i2c2_arb", "axi_sel", 4),
 531         GATE_ICG2(CLK_INFRA_I2C3_IMM, "infra_i2c3_imm", "axi_sel", 5),
 532         GATE_ICG2(CLK_INFRA_I2C3_ARB, "infra_i2c3_arb", "axi_sel", 6),
 533         GATE_ICG2(CLK_INFRA_I2C5, "infra_i2c5", "axi_sel", 7),
 534         GATE_ICG2(CLK_INFRA_SYS_CIRQ, "infra_sys_cirq", "axi_sel", 8),
 535         GATE_ICG2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 10),
 536         GATE_ICG2_FLAGS(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m",
 537                         "clk26m", 11, CLK_IS_CRITICAL),
 538         GATE_ICG2(CLK_INFRA_ANC_MD32, "infra_anc_md32", "anc_md32_sel", 12),
 539         GATE_ICG2(CLK_INFRA_ANC_MD32_32K, "infra_anc_md32_32k", "clk26m", 13),
 540         GATE_ICG2(CLK_INFRA_DVFS_SPM1, "infra_dvfs_spm1", "axi_sel", 15),
 541         GATE_ICG2(CLK_INFRA_AES_TOP0, "infra_aes_top0", "axi_sel", 16),
 542         GATE_ICG2(CLK_INFRA_AES_TOP1, "infra_aes_top1", "axi_sel", 17),
 543         GATE_ICG2(CLK_INFRA_SSUSB_BUS, "infra_ssusb_bus", "axi_sel", 18),
 544         GATE_ICG2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 19),
 545         GATE_ICG2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 20),
 546         GATE_ICG2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 21),
 547         GATE_ICG2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 22),
 548         GATE_ICG2(CLK_INFRA_IRTX, "infra_irtx", "spi_sel", 23),
 549         GATE_ICG2(CLK_INFRA_SSUSB_SYS, "infra_ssusb_sys",
 550                   "ssusb_top_sys_sel", 24),
 551         GATE_ICG2(CLK_INFRA_SSUSB_REF, "infra_ssusb_ref", "clk26m", 9),
 552         GATE_ICG2(CLK_INFRA_AUDIO_26M, "infra_audio_26m", "clk26m", 26),
 553         GATE_ICG2(CLK_INFRA_AUDIO_26M_PAD_TOP, "infra_audio_26m_pad_top",
 554                   "clk26m", 27),
 555         GATE_ICG2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share",
 556                   "axi_sel", 28),
 557         GATE_ICG2(CLK_INFRA_VAD_WRAP_SOC, "infra_vad_wrap_soc", "axi_sel", 29),
 558         GATE_ICG2(CLK_INFRA_DRAMC_CONF, "infra_dramc_conf", "axi_sel", 30),
 559         GATE_ICG2(CLK_INFRA_DRAMC_B_CONF, "infra_dramc_b_conf", "axi_sel", 31),
 560         GATE_ICG1(CLK_INFRA_MFG_VCG, "infra_mfg_vcg", "mfg_52m_sel", 14),
 561 };
 562
 563 static const struct mtk_fixed_factor infra_fixed_divs[] = {
 564         FACTOR(CLK_INFRA_13M, "clk13m", "clk26m", 1, 2),
 565 };
 566
 567 static struct clk_onecell_data *infra_clk_data;
 568
 569 static void mtk_infrasys_init_early(struct device_node *node)
 570 {
 571         int r, i;
 572
 573         if (!infra_clk_data) {
 574                 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
 575
 576                 for (i = 0; i < CLK_INFRA_NR; i++)
 577                         infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
 578         }
 579
 580         mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
 581                                  infra_clk_data);
 582
 583         r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
 584         if (r)
 585                 pr_err("%s(): could not register clock provider: %d\n",
 586                        __func__, r);
 587 }
 588
 589 CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt6797-infracfg",
 590                       mtk_infrasys_init_early);
 591
 592 static int mtk_infrasys_init(struct platform_device *pdev)
 593 {
 594         int r, i;
 595         struct device_node *node = pdev->dev.of_node;
 596
 597         if (!infra_clk_data) {
 598                 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
 599         } else {
 600                 for (i = 0; i < CLK_INFRA_NR; i++) {
 601                         if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
 602                                 infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
 603                 }
 604         }
 605
 606         mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
 607                                infra_clk_data);
 608         mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
 609                                  infra_clk_data);
 610
 611         r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
 612         if (r)
 613                 return r;
 614
 615         return 0;
 616 }
 617
 618 #define MT6797_PLL_FMAX         (3000UL * MHZ)
 619
 620 #define CON0_MT6797_RST_BAR     BIT(24)
 621
 622 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,   \
 623                         _pd_reg, _pd_shift, _tuner_reg, _pcw_reg,       \
 624                         _pcw_shift, _div_table) {                       \
 625         .id = _id,                                              \
 626         .name = _name,                                          \
 627         .reg = _reg,                                            \
 628         .pwr_reg = _pwr_reg,                                    \
 629         .en_mask = _en_mask,                                    \
 630         .flags = _flags,                                        \
 631         .rst_bar_mask = CON0_MT6797_RST_BAR,                    \
 632         .fmax = MT6797_PLL_FMAX,                                \
 633         .pcwbits = _pcwbits,                                    \
 634         .pd_reg = _pd_reg,                                      \
 635         .pd_shift = _pd_shift,                                  \
 636         .tuner_reg = _tuner_reg,                                \
 637         .pcw_reg = _pcw_reg,                                    \
 638         .pcw_shift = _pcw_shift,                                \
 639         .div_table = _div_table,                                \
 640 }
 641
 642 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,     \
 643                         _pd_reg, _pd_shift, _tuner_reg, _pcw_reg,       \
 644                         _pcw_shift)                                     \
 645                 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
 646                         _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
 647                         NULL)
 648
 649 static const struct mtk_pll_data plls[] = {
 650         PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000101, PLL_AO,
 651             21, 0x220, 4, 0x0, 0x224, 0),
 652         PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000011, 0, 7,
 653             0x230, 4, 0x0, 0x234, 14),
 654         PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000101, 0, 21,
 655             0x244, 24, 0x0, 0x244, 0),
 656         PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000121, 0, 21,
 657             0x250, 4, 0x0, 0x254, 0),
 658         PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000121, 0, 21,
 659             0x260, 4, 0x0, 0x264, 0),
 660         PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000121, 0, 21,
 661             0x270, 4, 0x0, 0x274, 0),
 662         PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000121, 0, 21,
 663             0x290, 4, 0x0, 0x294, 0),
 664         PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000121, 0, 21,
 665             0x2E4, 4, 0x0, 0x2E8, 0),
 666         PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000131, 0, 31,
 667             0x2A0, 4, 0x2A8, 0x2A4, 0),
 668         PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000131, 0, 31,
 669             0x2B4, 4, 0x2BC, 0x2B8, 0),
 670 };
 671
 672 static int mtk_apmixedsys_init(struct platform_device *pdev)
 673 {
 674         struct clk_onecell_data *clk_data;
 675         struct device_node *node = pdev->dev.of_node;
 676
 677         clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
 678         if (!clk_data)
 679                 return -ENOMEM;
 680
 681         mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
 682
 683         return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 684 }
 685
 686 static const struct of_device_id of_match_clk_mt6797[] = {
 687         {
 688                 .compatible = "mediatek,mt6797-topckgen",
 689                 .data = mtk_topckgen_init,
 690         }, {
 691                 .compatible = "mediatek,mt6797-infracfg",
 692                 .data = mtk_infrasys_init,
 693         }, {
 694                 .compatible = "mediatek,mt6797-apmixedsys",
 695                 .data = mtk_apmixedsys_init,
 696         }, {
 697                 /* sentinel */
 698         }
 699 };
 700
 701 static int clk_mt6797_probe(struct platform_device *pdev)
 702 {
 703         int (*clk_init)(struct platform_device *);
 704         int r;
 705
 706         clk_init = of_device_get_match_data(&pdev->dev);
 707         if (!clk_init)
 708                 return -EINVAL;
 709
 710         r = clk_init(pdev);
 711         if (r)
 712                 dev_err(&pdev->dev,
 713                         "could not register clock provider: %s: %d\n",
 714                         pdev->name, r);
 715
 716         return r;
 717 }
 718
 719 static struct platform_driver clk_mt6797_drv = {
 720         .probe = clk_mt6797_probe,
 721         .driver = {
 722                 .name = "clk-mt6797",
 723                 .of_match_table = of_match_clk_mt6797,
 724         },
 725 };
 726
 727 static int __init clk_mt6797_init(void)
 728 {
 729         return platform_driver_register(&clk_mt6797_drv);
 730 }
 731
 732 arch_initcall(clk_mt6797_init);