2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/mfd/syscon.h>
19 #include <linux/of_address.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
27 #include <dt-bindings/clock/mt2712-clk.h>
29 static DEFINE_SPINLOCK(mt2712_clk_lock);
31 static const struct mtk_fixed_clk top_fixed_clks[] = {
32 FIXED_CLK(CLK_TOP_VPLL3_DPIX, "vpll3_dpix", NULL, 200000000),
33 FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", NULL, 200000000),
34 FIXED_CLK(CLK_TOP_LTEPLL_FS26M, "ltepll_fs26m", NULL, 26000000),
35 FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000),
36 FIXED_CLK(CLK_TOP_DSI0_LNTC, "dsi0_lntc", NULL, 143000000),
37 FIXED_CLK(CLK_TOP_DSI1_LNTC, "dsi1_lntc", NULL, 143000000),
38 FIXED_CLK(CLK_TOP_LVDSTX3_CLKDIG_CTS, "lvdstx3", NULL, 140000000),
39 FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx", NULL, 140000000),
40 FIXED_CLK(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", NULL, 32768),
41 FIXED_CLK(CLK_TOP_CLKRTC_INT, "clkrtc_int", NULL, 32747),
42 FIXED_CLK(CLK_TOP_CSI0, "csi0", NULL, 26000000),
43 FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000),
46 static const struct mtk_fixed_factor top_early_divs[] = {
47 FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1,
49 FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1,
53 static const struct mtk_fixed_factor top_divs[] = {
54 FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1,
56 FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1,
58 FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1,
60 FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1,
62 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1,
64 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
66 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1,
68 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1,
70 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1,
72 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1,
74 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1,
76 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1,
78 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1,
80 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1,
82 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1,
84 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1,
86 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1,
88 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1,
90 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1,
92 FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1,
94 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1,
96 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1,
98 FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1,
100 FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1,
102 FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1,
104 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
106 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1,
108 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1,
110 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1,
112 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1,
114 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1,
116 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1,
118 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1,
120 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1,
122 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1,
124 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1,
126 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1,
128 FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1,
130 FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1,
132 FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1,
134 FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1,
136 FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1,
138 FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1,
140 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1,
142 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1,
144 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1,
146 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1,
148 FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1,
150 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1,
152 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1,
154 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1,
156 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1,
158 FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1,
160 FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1,
162 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1,
164 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1,
166 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1,
168 FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1,
170 FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1,
172 FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1,
174 FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1,
176 FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1,
178 FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1,
180 FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1,
182 FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1,
184 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1,
186 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1,
188 FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1,
190 FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1,
192 FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1,
194 FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1,
196 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1,
198 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
200 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1,
202 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1,
204 FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1,
206 FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1,
208 FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1,
210 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1,
212 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1,
214 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1,
216 FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1,
218 FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1,
220 FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1,
222 FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1,
224 FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1,
226 FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1,
230 static const char * const axi_parents[] = {
240 static const char * const mem_parents[] = {
245 static const char * const mm_parents[] = {
256 static const char * const pwm_parents[] = {
263 static const char * const vdec_parents[] = {
276 static const char * const venc_parents[] = {
288 static const char * const mfg_parents[] = {
307 static const char * const camtg_parents[] = {
321 static const char * const uart_parents[] = {
326 static const char * const spi_parents[] = {
335 static const char * const usb20_parents[] = {
341 static const char * const usb30_parents[] = {
348 static const char * const msdc50_0_h_parents[] = {
357 static const char * const msdc50_0_parents[] = {
371 static const char * const msdc30_1_parents[] = {
381 static const char * const msdc30_3_parents[] = {
397 static const char * const audio_parents[] = {
404 static const char * const aud_intbus_parents[] = {
414 static const char * const pmicspi_parents[] = {
424 static const char * const dpilvds1_parents[] = {
433 static const char * const atb_parents[] = {
440 static const char * const nr_parents[] = {
451 static const char * const nfi2x_parents[] = {
465 static const char * const irda_parents[] = {
472 static const char * const cci400_parents[] = {
483 static const char * const aud_1_parents[] = {
490 static const char * const aud_2_parents[] = {
497 static const char * const mem_mfg_parents[] = {
503 static const char * const axi_mfg_parents[] = {
509 static const char * const scam_parents[] = {
516 static const char * const nfiecc_parents[] = {
526 static const char * const pe2_mac_p0_parents[] = {
535 static const char * const dpilvds_parents[] = {
544 static const char * const hdcp_parents[] = {
551 static const char * const hdcp_24m_parents[] = {
558 static const char * const rtc_parents[] = {
565 static const char * const spinor_parents[] = {
578 static const char * const apll_parents[] = {
594 static const char * const a1sys_hp_parents[] = {
603 static const char * const a2sys_hp_parents[] = {
612 static const char * const asm_l_parents[] = {
619 static const char * const i2so1_parents[] = {
625 static const char * const ether_125m_parents[] = {
631 static const char * const ether_50m_parents[] = {
638 static const char * const jpgdec_parents[] = {
651 static const char * const spislv_parents[] = {
662 static const char * const ether_parents[] = {
668 static const char * const di_parents[] = {
679 static const char * const tvd_parents[] = {
685 static const char * const i2c_parents[] = {
693 static const char * const msdc0p_aes_parents[] = {
700 static const char * const cmsys_parents[] = {
708 static const char * const gcpu_parents[] = {
718 static const char * const aud_apll1_parents[] = {
723 static const char * const aud_apll2_parents[] = {
728 static const char * const apll1_ref_parents[] = {
739 static const char * const audull_vtx_parents[] = {
744 static struct mtk_composite top_muxes[] = {
746 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
748 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
749 15, CLK_IS_CRITICAL),
750 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel",
751 mm_parents, 0x040, 24, 3, 31),
753 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel",
754 pwm_parents, 0x050, 0, 2, 7),
755 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel",
756 vdec_parents, 0x050, 8, 4, 15),
757 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel",
758 venc_parents, 0x050, 16, 4, 23),
759 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel",
760 mfg_parents, 0x050, 24, 4, 31),
762 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel",
763 camtg_parents, 0x060, 0, 4, 7),
764 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel",
765 uart_parents, 0x060, 8, 1, 15),
766 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel",
767 spi_parents, 0x060, 16, 3, 23),
768 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel",
769 usb20_parents, 0x060, 24, 2, 31),
771 MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel",
772 usb30_parents, 0x070, 0, 2, 7),
773 MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel",
774 msdc50_0_h_parents, 0x070, 8, 3, 15),
775 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
776 msdc50_0_parents, 0x070, 16, 4, 23),
777 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
778 msdc30_1_parents, 0x070, 24, 3, 31),
780 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
781 msdc30_1_parents, 0x080, 0, 3, 7),
782 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel",
783 msdc30_3_parents, 0x080, 8, 4, 15),
784 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel",
785 audio_parents, 0x080, 16, 2, 23),
786 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
787 aud_intbus_parents, 0x080, 24, 3, 31),
789 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel",
790 pmicspi_parents, 0x090, 0, 3, 7),
791 MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel",
792 dpilvds1_parents, 0x090, 8, 3, 15),
793 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel",
794 atb_parents, 0x090, 16, 2, 23),
795 MUX_GATE(CLK_TOP_NR_SEL, "nr_sel",
796 nr_parents, 0x090, 24, 3, 31),
798 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel",
799 nfi2x_parents, 0x0a0, 0, 4, 7),
800 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel",
801 irda_parents, 0x0a0, 8, 2, 15),
802 MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel",
803 cci400_parents, 0x0a0, 16, 3, 23),
804 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel",
805 aud_1_parents, 0x0a0, 24, 2, 31),
807 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel",
808 aud_2_parents, 0x0b0, 0, 2, 7),
809 MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel",
810 mem_mfg_parents, 0x0b0, 8, 2, 15),
811 MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel",
812 axi_mfg_parents, 0x0b0, 16, 2, 23),
813 MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel",
814 scam_parents, 0x0b0, 24, 2, 31),
816 MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel",
817 nfiecc_parents, 0x0c0, 0, 3, 7),
818 MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel",
819 pe2_mac_p0_parents, 0x0c0, 8, 3, 15),
820 MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel",
821 pe2_mac_p0_parents, 0x0c0, 16, 3, 23),
822 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel",
823 dpilvds_parents, 0x0c0, 24, 3, 31),
825 MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel",
826 msdc50_0_h_parents, 0x0d0, 0, 3, 7),
827 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel",
828 hdcp_parents, 0x0d0, 8, 2, 15),
829 MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel",
830 hdcp_24m_parents, 0x0d0, 16, 2, 23),
831 MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x0d0, 24, 2,
832 31, CLK_IS_CRITICAL),
834 MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel",
835 spinor_parents, 0x500, 0, 4, 7),
836 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel",
837 apll_parents, 0x500, 8, 4, 15),
838 MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel",
839 apll_parents, 0x500, 16, 4, 23),
840 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel",
841 a1sys_hp_parents, 0x500, 24, 3, 31),
843 MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel",
844 a2sys_hp_parents, 0x510, 0, 3, 7),
845 MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel",
846 asm_l_parents, 0x510, 8, 2, 15),
847 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel",
848 asm_l_parents, 0x510, 16, 2, 23),
849 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel",
850 asm_l_parents, 0x510, 24, 2, 31),
852 MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel",
853 i2so1_parents, 0x520, 0, 2, 7),
854 MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel",
855 i2so1_parents, 0x520, 8, 2, 15),
856 MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel",
857 i2so1_parents, 0x520, 16, 2, 23),
858 MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel",
859 i2so1_parents, 0x520, 24, 2, 31),
861 MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel",
862 i2so1_parents, 0x530, 0, 2, 7),
863 MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel",
864 i2so1_parents, 0x530, 8, 2, 15),
865 MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel",
866 i2so1_parents, 0x530, 16, 2, 23),
867 MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel",
868 i2so1_parents, 0x530, 24, 2, 31),
870 MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel",
871 ether_125m_parents, 0x540, 0, 2, 7),
872 MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel",
873 ether_50m_parents, 0x540, 8, 2, 15),
874 MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel",
875 jpgdec_parents, 0x540, 16, 4, 23),
876 MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel",
877 spislv_parents, 0x540, 24, 3, 31),
879 MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel",
880 ether_parents, 0x550, 0, 2, 7),
881 MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel",
882 camtg_parents, 0x550, 8, 4, 15),
883 MUX_GATE(CLK_TOP_DI_SEL, "di_sel",
884 di_parents, 0x550, 16, 3, 23),
885 MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel",
886 tvd_parents, 0x550, 24, 2, 31),
888 MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel",
889 i2c_parents, 0x560, 0, 3, 7),
890 MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel",
891 pwm_parents, 0x560, 8, 2, 15),
892 MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel",
893 msdc0p_aes_parents, 0x560, 16, 2, 23),
894 MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel",
895 cmsys_parents, 0x560, 24, 3, 31),
897 MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel",
898 gcpu_parents, 0x570, 0, 3, 7),
900 MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel",
901 aud_apll1_parents, 0x134, 0, 1),
902 MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel",
903 aud_apll2_parents, 0x134, 1, 1),
904 MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel",
905 audull_vtx_parents, 0x134, 31, 1),
906 MUX(CLK_TOP_APLL1_REF_SEL, "apll1_ref_sel",
907 apll1_ref_parents, 0x134, 4, 3),
908 MUX(CLK_TOP_APLL2_REF_SEL, "apll2_ref_sel",
909 apll1_ref_parents, 0x134, 7, 3),
912 static const char * const mcu_mp0_parents[] = {
919 static const char * const mcu_mp2_parents[] = {
926 static const char * const mcu_bus_parents[] = {
933 static struct mtk_composite mcu_muxes[] = {
934 /* mp0_pll_divider_cfg */
935 MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0,
936 9, 2, -1, CLK_IS_CRITICAL),
937 /* mp2_pll_divider_cfg */
938 MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8,
939 9, 2, -1, CLK_IS_CRITICAL),
940 /* bus_pll_divider_cfg */
941 MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0,
942 9, 2, -1, CLK_IS_CRITICAL),
945 static const struct mtk_clk_divider top_adj_divs[] = {
946 DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8),
947 DIV_ADJ(CLK_TOP_APLL_DIV1, "apll_div1", "i2so2_sel", 0x124, 8, 8),
948 DIV_ADJ(CLK_TOP_APLL_DIV2, "apll_div2", "i2so3_sel", 0x124, 16, 8),
949 DIV_ADJ(CLK_TOP_APLL_DIV3, "apll_div3", "tdmo0_sel", 0x124, 24, 8),
950 DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8),
951 DIV_ADJ(CLK_TOP_APLL_DIV5, "apll_div5", "i2si1_sel", 0x128, 8, 8),
952 DIV_ADJ(CLK_TOP_APLL_DIV6, "apll_div6", "i2si2_sel", 0x128, 16, 8),
953 DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8),
956 static const struct mtk_gate_regs top0_cg_regs = {
962 static const struct mtk_gate_regs top1_cg_regs = {
968 #define GATE_TOP0(_id, _name, _parent, _shift) { \
971 .parent_name = _parent, \
972 .regs = &top0_cg_regs, \
974 .ops = &mtk_clk_gate_ops_no_setclr, \
977 #define GATE_TOP1(_id, _name, _parent, _shift) { \
980 .parent_name = _parent, \
981 .regs = &top1_cg_regs, \
983 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
986 static const struct mtk_gate top_clks[] = {
988 GATE_TOP0(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0),
989 GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),
990 GATE_TOP0(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),
991 GATE_TOP0(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3),
992 GATE_TOP0(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4),
993 GATE_TOP0(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5),
994 GATE_TOP0(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6),
995 GATE_TOP0(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7),
997 GATE_TOP1(CLK_TOP_NFI2X_EN, "nfi2x_en", "nfi2x_sel", 0),
998 GATE_TOP1(CLK_TOP_NFIECC_EN, "nfiecc_en", "nfiecc_sel", 1),
999 GATE_TOP1(CLK_TOP_NFI1X_CK_EN, "nfi1x_ck_en", "nfi2x_sel", 2),
1002 static const struct mtk_gate_regs infra_cg_regs = {
1008 #define GATE_INFRA(_id, _name, _parent, _shift) { \
1011 .parent_name = _parent, \
1012 .regs = &infra_cg_regs, \
1014 .ops = &mtk_clk_gate_ops_setclr, \
1017 static const struct mtk_gate infra_clks[] = {
1018 GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
1019 GATE_INFRA(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
1020 GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
1021 GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
1022 GATE_INFRA(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 24),
1023 GATE_INFRA(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spislv_sel", 25),
1024 GATE_INFRA(CLK_INFRA_AO_UART5, "infra_ao_uart5", "axi_sel", 26),
1027 static const struct mtk_gate_regs peri0_cg_regs = {
1033 static const struct mtk_gate_regs peri1_cg_regs = {
1039 static const struct mtk_gate_regs peri2_cg_regs = {
1045 #define GATE_PERI0(_id, _name, _parent, _shift) { \
1048 .parent_name = _parent, \
1049 .regs = &peri0_cg_regs, \
1051 .ops = &mtk_clk_gate_ops_setclr, \
1054 #define GATE_PERI1(_id, _name, _parent, _shift) { \
1057 .parent_name = _parent, \
1058 .regs = &peri1_cg_regs, \
1060 .ops = &mtk_clk_gate_ops_setclr, \
1063 #define GATE_PERI2(_id, _name, _parent, _shift) { \
1066 .parent_name = _parent, \
1067 .regs = &peri2_cg_regs, \
1069 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
1072 static const struct mtk_gate peri_clks[] = {
1074 GATE_PERI0(CLK_PERI_NFI, "per_nfi",
1076 GATE_PERI0(CLK_PERI_THERM, "per_therm",
1078 GATE_PERI0(CLK_PERI_PWM0, "per_pwm0",
1080 GATE_PERI0(CLK_PERI_PWM1, "per_pwm1",
1082 GATE_PERI0(CLK_PERI_PWM2, "per_pwm2",
1084 GATE_PERI0(CLK_PERI_PWM3, "per_pwm3",
1086 GATE_PERI0(CLK_PERI_PWM4, "per_pwm4",
1088 GATE_PERI0(CLK_PERI_PWM5, "per_pwm5",
1090 GATE_PERI0(CLK_PERI_PWM6, "per_pwm6",
1092 GATE_PERI0(CLK_PERI_PWM7, "per_pwm7",
1094 GATE_PERI0(CLK_PERI_PWM, "per_pwm",
1096 GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma",
1098 GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0",
1099 "msdc50_0_sel", 14),
1100 GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1",
1101 "msdc30_1_sel", 15),
1102 GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2",
1103 "msdc30_2_sel", 16),
1104 GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3",
1105 "msdc30_3_sel", 17),
1106 GATE_PERI0(CLK_PERI_UART0, "per_uart0",
1108 GATE_PERI0(CLK_PERI_UART1, "per_uart1",
1110 GATE_PERI0(CLK_PERI_UART2, "per_uart2",
1112 GATE_PERI0(CLK_PERI_UART3, "per_uart3",
1114 GATE_PERI0(CLK_PERI_I2C0, "per_i2c0",
1116 GATE_PERI0(CLK_PERI_I2C1, "per_i2c1",
1118 GATE_PERI0(CLK_PERI_I2C2, "per_i2c2",
1120 GATE_PERI0(CLK_PERI_I2C3, "per_i2c3",
1122 GATE_PERI0(CLK_PERI_I2C4, "per_i2c4",
1124 GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc",
1125 "ltepll_fs26m", 29),
1126 GATE_PERI0(CLK_PERI_SPI0, "per_spi0",
1129 GATE_PERI1(CLK_PERI_SPI, "per_spi",
1131 GATE_PERI1(CLK_PERI_I2C5, "per_i2c5",
1133 GATE_PERI1(CLK_PERI_SPI2, "per_spi2",
1135 GATE_PERI1(CLK_PERI_SPI3, "per_spi3",
1137 GATE_PERI1(CLK_PERI_SPI5, "per_spi5",
1139 GATE_PERI1(CLK_PERI_UART4, "per_uart4",
1141 GATE_PERI1(CLK_PERI_SFLASH, "per_sflash",
1143 GATE_PERI1(CLK_PERI_GMAC, "per_gmac",
1145 GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0",
1147 GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1",
1149 GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk",
1152 GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en",
1154 GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en",
1156 GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en",
1158 GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en",
1160 GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h",
1161 "msdc50_0_h_sel", 4),
1162 GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h",
1163 "msdc50_3_h_sel", 5),
1164 GATE_PERI2(CLK_PERI_MSDC30_0_QTR_EN, "per_msdc30_0_q",
1166 GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q",
1170 #define MT2712_PLL_FMAX (3000UL * MHZ)
1172 #define CON0_MT2712_RST_BAR BIT(24)
1174 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
1175 _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
1176 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1181 .pwr_reg = _pwr_reg, \
1182 .en_mask = _en_mask, \
1184 .rst_bar_mask = CON0_MT2712_RST_BAR, \
1185 .fmax = MT2712_PLL_FMAX, \
1186 .pcwbits = _pcwbits, \
1187 .pd_reg = _pd_reg, \
1188 .pd_shift = _pd_shift, \
1189 .tuner_reg = _tuner_reg, \
1190 .tuner_en_reg = _tuner_en_reg, \
1191 .tuner_en_bit = _tuner_en_bit, \
1192 .pcw_reg = _pcw_reg, \
1193 .pcw_shift = _pcw_shift, \
1194 .div_table = _div_table, \
1197 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
1198 _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
1199 _tuner_en_bit, _pcw_reg, _pcw_shift) \
1200 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1201 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, \
1202 _tuner_en_reg, _tuner_en_bit, _pcw_reg, \
1205 static const struct mtk_pll_div_table armca35pll_div_table[] = {
1206 { .div = 0, .freq = MT2712_PLL_FMAX },
1207 { .div = 1, .freq = 1202500000 },
1208 { .div = 2, .freq = 500500000 },
1209 { .div = 3, .freq = 315250000 },
1210 { .div = 4, .freq = 157625000 },
1214 static const struct mtk_pll_div_table armca72pll_div_table[] = {
1215 { .div = 0, .freq = MT2712_PLL_FMAX },
1216 { .div = 1, .freq = 994500000 },
1217 { .div = 2, .freq = 520000000 },
1218 { .div = 3, .freq = 315250000 },
1219 { .div = 4, .freq = 157625000 },
1223 static const struct mtk_pll_div_table mmpll_div_table[] = {
1224 { .div = 0, .freq = MT2712_PLL_FMAX },
1225 { .div = 1, .freq = 1001000000 },
1226 { .div = 2, .freq = 601250000 },
1227 { .div = 3, .freq = 250250000 },
1228 { .div = 4, .freq = 125125000 },
1232 static const struct mtk_pll_data plls[] = {
1233 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000101,
1234 HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
1235 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000101,
1236 HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
1237 PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000101,
1238 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
1239 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000101,
1240 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
1241 PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000101,
1242 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
1243 PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000101,
1244 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
1245 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000101,
1246 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
1247 PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000101,
1248 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
1249 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000101,
1250 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
1251 PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000101,
1252 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
1253 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000101,
1254 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
1255 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000101,
1256 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0,
1258 PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000101,
1259 HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0,
1260 armca35pll_div_table),
1261 PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000101,
1262 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0,
1263 armca72pll_div_table),
1264 PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000101,
1265 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
1268 static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
1270 struct clk_onecell_data *clk_data;
1272 struct device_node *node = pdev->dev.of_node;
1274 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1276 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1278 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1281 pr_err("%s(): could not register clock provider: %d\n",
1287 static struct clk_onecell_data *top_clk_data;
1289 static void clk_mt2712_top_init_early(struct device_node *node)
1293 if (!top_clk_data) {
1294 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1296 for (i = 0; i < CLK_TOP_NR_CLK; i++)
1297 top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
1300 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
1303 r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
1305 pr_err("%s(): could not register clock provider: %d\n",
1309 CLK_OF_DECLARE_DRIVER(mt2712_topckgen, "mediatek,mt2712-topckgen",
1310 clk_mt2712_top_init_early);
1312 static int clk_mt2712_top_probe(struct platform_device *pdev)
1315 struct device_node *node = pdev->dev.of_node;
1317 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1319 base = devm_ioremap_resource(&pdev->dev, res);
1321 pr_err("%s(): ioremap failed\n", __func__);
1322 return PTR_ERR(base);
1325 if (!top_clk_data) {
1326 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1328 for (i = 0; i < CLK_TOP_NR_CLK; i++) {
1329 if (top_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
1330 top_clk_data->clks[i] = ERR_PTR(-ENOENT);
1334 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1336 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
1338 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1339 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
1340 &mt2712_clk_lock, top_clk_data);
1341 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
1342 &mt2712_clk_lock, top_clk_data);
1343 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
1346 r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
1349 pr_err("%s(): could not register clock provider: %d\n",
1355 static int clk_mt2712_infra_probe(struct platform_device *pdev)
1357 struct clk_onecell_data *clk_data;
1359 struct device_node *node = pdev->dev.of_node;
1361 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1363 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1366 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1369 pr_err("%s(): could not register clock provider: %d\n",
1372 mtk_register_reset_controller(node, 2, 0x30);
1377 static int clk_mt2712_peri_probe(struct platform_device *pdev)
1379 struct clk_onecell_data *clk_data;
1381 struct device_node *node = pdev->dev.of_node;
1383 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
1385 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
1388 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1391 pr_err("%s(): could not register clock provider: %d\n",
1394 mtk_register_reset_controller(node, 2, 0);
1399 static int clk_mt2712_mcu_probe(struct platform_device *pdev)
1401 struct clk_onecell_data *clk_data;
1403 struct device_node *node = pdev->dev.of_node;
1405 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1407 base = devm_ioremap_resource(&pdev->dev, res);
1409 pr_err("%s(): ioremap failed\n", __func__);
1410 return PTR_ERR(base);
1413 clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
1415 mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
1416 &mt2712_clk_lock, clk_data);
1418 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1421 pr_err("%s(): could not register clock provider: %d\n",
1427 static const struct of_device_id of_match_clk_mt2712[] = {
1429 .compatible = "mediatek,mt2712-apmixedsys",
1430 .data = clk_mt2712_apmixed_probe,
1432 .compatible = "mediatek,mt2712-topckgen",
1433 .data = clk_mt2712_top_probe,
1435 .compatible = "mediatek,mt2712-infracfg",
1436 .data = clk_mt2712_infra_probe,
1438 .compatible = "mediatek,mt2712-pericfg",
1439 .data = clk_mt2712_peri_probe,
1441 .compatible = "mediatek,mt2712-mcucfg",
1442 .data = clk_mt2712_mcu_probe,
1448 static int clk_mt2712_probe(struct platform_device *pdev)
1450 int (*clk_probe)(struct platform_device *);
1453 clk_probe = of_device_get_match_data(&pdev->dev);
1457 r = clk_probe(pdev);
1460 "could not register clock provider: %s: %d\n",
1466 static struct platform_driver clk_mt2712_drv = {
1467 .probe = clk_mt2712_probe,
1469 .name = "clk-mt2712",
1470 .of_match_table = of_match_clk_mt2712,
1474 static int __init clk_mt2712_init(void)
1476 return platform_driver_register(&clk_mt2712_drv);
1479 arch_initcall(clk_mt2712_init);