1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ahci.c - AHCI SATA support
5 * Maintained by: Tejun Heo <tj@kernel.org>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
11 * libata documentation is available via 'make {ps|pdf}docs',
12 * as Documentation/driver-api/libata.rst
14 * AHCI hardware documentation:
15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/dmi.h>
28 #include <linux/gfp.h>
29 #include <scsi/scsi_host.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <linux/libata.h>
32 #include <linux/ahci-remap.h>
33 #include <linux/io-64-nonatomic-lo-hi.h>
36 #define DRV_NAME "ahci"
37 #define DRV_VERSION "3.0"
40 AHCI_PCI_BAR_STA2X11 = 0,
41 AHCI_PCI_BAR_CAVIUM = 0,
42 AHCI_PCI_BAR_LOONGSON = 0,
43 AHCI_PCI_BAR_ENMOTUS = 2,
44 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
45 AHCI_PCI_BAR_STANDARD = 5,
49 /* board IDs by feature in alphabetical order */
54 board_ahci_no_debounce_delay,
60 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_sb700, /* for SB700 and SB800 */
72 * board IDs for Intel chipsets that support more than 6 ports
73 * *and* end up needing the PCS quirk.
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85 static void ahci_remove_one(struct pci_dev *dev);
86 static void ahci_shutdown_one(struct pci_dev *dev);
87 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv);
88 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
91 unsigned long deadline);
92 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
93 static bool is_mcp89_apple(struct pci_dev *pdev);
94 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
95 unsigned long deadline);
97 static int ahci_pci_device_runtime_suspend(struct device *dev);
98 static int ahci_pci_device_runtime_resume(struct device *dev);
99 #ifdef CONFIG_PM_SLEEP
100 static int ahci_pci_device_suspend(struct device *dev);
101 static int ahci_pci_device_resume(struct device *dev);
103 #endif /* CONFIG_PM */
105 static const struct scsi_host_template ahci_sht = {
109 static struct ata_port_operations ahci_vt8251_ops = {
110 .inherits = &ahci_ops,
111 .hardreset = ahci_vt8251_hardreset,
114 static struct ata_port_operations ahci_p5wdh_ops = {
115 .inherits = &ahci_ops,
116 .hardreset = ahci_p5wdh_hardreset,
119 static struct ata_port_operations ahci_avn_ops = {
120 .inherits = &ahci_ops,
121 .hardreset = ahci_avn_hardreset,
124 static const struct ata_port_info ahci_port_info[] = {
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
132 [board_ahci_43bit_dma] = {
133 AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
139 [board_ahci_ign_iferr] = {
140 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
141 .flags = AHCI_FLAG_COMMON,
142 .pio_mask = ATA_PIO4,
143 .udma_mask = ATA_UDMA6,
144 .port_ops = &ahci_ops,
146 [board_ahci_low_power] = {
147 AHCI_HFLAGS (AHCI_HFLAG_USE_LPM_POLICY),
148 .flags = AHCI_FLAG_COMMON,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
153 [board_ahci_no_debounce_delay] = {
154 .flags = AHCI_FLAG_COMMON,
155 .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
160 [board_ahci_nomsi] = {
161 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
162 .flags = AHCI_FLAG_COMMON,
163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
167 [board_ahci_noncq] = {
168 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
169 .flags = AHCI_FLAG_COMMON,
170 .pio_mask = ATA_PIO4,
171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
174 [board_ahci_nosntf] = {
175 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
176 .flags = AHCI_FLAG_COMMON,
177 .pio_mask = ATA_PIO4,
178 .udma_mask = ATA_UDMA6,
179 .port_ops = &ahci_ops,
181 [board_ahci_yes_fbs] = {
182 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
183 .flags = AHCI_FLAG_COMMON,
184 .pio_mask = ATA_PIO4,
185 .udma_mask = ATA_UDMA6,
186 .port_ops = &ahci_ops,
190 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
191 .flags = AHCI_FLAG_COMMON,
192 .pio_mask = ATA_PIO4,
193 .udma_mask = ATA_UDMA6,
194 .port_ops = &ahci_ops,
197 .flags = AHCI_FLAG_COMMON,
198 .pio_mask = ATA_PIO4,
199 .udma_mask = ATA_UDMA6,
200 .port_ops = &ahci_avn_ops,
202 [board_ahci_mcp65] = {
203 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
205 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
206 .pio_mask = ATA_PIO4,
207 .udma_mask = ATA_UDMA6,
208 .port_ops = &ahci_ops,
210 [board_ahci_mcp77] = {
211 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
212 .flags = AHCI_FLAG_COMMON,
213 .pio_mask = ATA_PIO4,
214 .udma_mask = ATA_UDMA6,
215 .port_ops = &ahci_ops,
217 [board_ahci_mcp89] = {
218 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
219 .flags = AHCI_FLAG_COMMON,
220 .pio_mask = ATA_PIO4,
221 .udma_mask = ATA_UDMA6,
222 .port_ops = &ahci_ops,
225 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
226 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
227 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
230 .port_ops = &ahci_ops,
232 [board_ahci_sb600] = {
233 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
234 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
235 AHCI_HFLAG_32BIT_ONLY),
236 .flags = AHCI_FLAG_COMMON,
237 .pio_mask = ATA_PIO4,
238 .udma_mask = ATA_UDMA6,
239 .port_ops = &ahci_pmp_retry_srst_ops,
241 [board_ahci_sb700] = { /* for SB700 and SB800 */
242 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
243 .flags = AHCI_FLAG_COMMON,
244 .pio_mask = ATA_PIO4,
245 .udma_mask = ATA_UDMA6,
246 .port_ops = &ahci_pmp_retry_srst_ops,
248 [board_ahci_vt8251] = {
249 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
250 .flags = AHCI_FLAG_COMMON,
251 .pio_mask = ATA_PIO4,
252 .udma_mask = ATA_UDMA6,
253 .port_ops = &ahci_vt8251_ops,
255 [board_ahci_pcs7] = {
256 .flags = AHCI_FLAG_COMMON,
257 .pio_mask = ATA_PIO4,
258 .udma_mask = ATA_UDMA6,
259 .port_ops = &ahci_ops,
263 static const struct pci_device_id ahci_pci_tbl[] = {
265 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
266 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
267 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
268 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
269 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
270 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
271 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
272 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
273 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
274 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
275 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
276 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
277 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8/Lewisburg RAID*/
278 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
279 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
280 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
281 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
282 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
283 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
284 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
285 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
286 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */
287 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */
288 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */
289 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */
290 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */
291 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
292 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */
293 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
294 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
295 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
296 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
297 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
298 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
299 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
300 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
301 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
302 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */
303 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
304 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */
305 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
306 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
307 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
308 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
309 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
310 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
311 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
312 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
313 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
314 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
315 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
316 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
317 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
318 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
319 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
320 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
321 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
322 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
323 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
324 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
325 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
326 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
327 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */
328 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
329 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */
330 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
331 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
332 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
333 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
334 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
335 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
336 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
337 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */
338 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
339 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
340 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
341 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */
342 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
343 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
344 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */
345 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
346 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */
347 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
348 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */
349 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
350 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */
351 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */
352 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */
353 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */
354 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */
355 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */
356 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */
357 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */
358 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */
359 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */
360 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
361 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
362 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
363 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
364 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
365 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
366 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
367 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
368 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
369 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
370 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
371 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
372 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
373 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
374 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
375 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
376 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg/Lewisburg AHCI*/
377 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* *burg SATA0 'RAID' */
378 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* *burg SATA1 'RAID' */
379 { PCI_VDEVICE(INTEL, 0x282f), board_ahci }, /* *burg SATA2 'RAID' */
380 { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
381 { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
382 { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
383 { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
384 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
385 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
386 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
387 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
388 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
389 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
390 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
391 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
392 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
393 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */
394 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */
395 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */
396 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */
397 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
398 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */
399 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
400 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */
401 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
402 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */
403 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
404 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */
405 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */
406 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */
407 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */
408 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
409 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */
410 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
411 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
412 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */
413 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
414 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
415 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
416 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
417 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
418 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
419 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
420 { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
421 { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
422 { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
423 { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
424 { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
425 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */
426 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */
427 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */
428 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */
429 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */
430 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */
431 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */
432 /* Elkhart Lake IDs 0x4b60 & 0x4b62 https://sata-io.org/product/8803 not tested yet */
433 { PCI_VDEVICE(INTEL, 0x4b63), board_ahci_low_power }, /* Elkhart Lake AHCI */
434 { PCI_VDEVICE(INTEL, 0x7ae2), board_ahci_low_power }, /* Alder Lake-P AHCI */
436 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
437 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
438 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
439 /* JMicron 362B and 362C have an AHCI function with IDE class code */
440 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
441 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
442 /* May need to update quirk_jmicron_async_suspend() for additions */
445 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
446 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
447 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
448 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
449 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
450 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
451 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
453 /* Amazon's Annapurna Labs support */
454 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
455 .class = PCI_CLASS_STORAGE_SATA_AHCI,
456 .class_mask = 0xffffff,
459 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
460 { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
461 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
462 { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */
463 /* AMD is using RAID class only for ahci controllers */
464 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
465 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
468 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
469 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
472 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
473 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
476 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
477 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
478 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
479 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
480 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
481 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
482 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
483 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
484 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
485 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
486 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
487 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
488 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
489 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
490 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
491 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
492 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
493 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
494 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
495 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
496 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
497 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
498 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
499 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
500 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
501 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
502 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
503 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
504 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
505 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
506 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
507 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
508 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
509 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
510 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
511 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
512 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
513 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
514 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
515 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
516 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
517 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
518 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
519 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
520 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
521 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
522 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
523 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
524 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
525 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
526 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
527 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
528 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
529 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
530 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
531 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
532 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
533 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
534 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
535 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
536 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
537 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
538 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
539 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
540 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
541 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
542 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
543 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
544 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
545 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
546 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
547 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
548 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
549 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
550 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
551 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
552 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
553 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
554 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
555 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
556 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
557 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
558 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
559 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
562 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
563 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
564 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
566 /* ST Microelectronics */
567 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
570 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
571 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
572 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
573 .class = PCI_CLASS_STORAGE_SATA_AHCI,
574 .class_mask = 0xffffff,
575 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
576 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
577 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
578 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
579 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
580 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
581 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
582 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
583 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
584 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
585 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
586 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
587 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
588 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
589 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
590 .driver_data = board_ahci_yes_fbs },
591 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
592 .driver_data = board_ahci_yes_fbs },
593 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
594 .driver_data = board_ahci_yes_fbs },
595 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
596 .driver_data = board_ahci_yes_fbs },
597 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235),
598 .driver_data = board_ahci_no_debounce_delay },
599 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
600 .driver_data = board_ahci_yes_fbs },
601 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
602 .driver_data = board_ahci_yes_fbs },
605 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
606 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
609 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
610 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
611 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci_43bit_dma }, /* ASM1061 */
612 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci_43bit_dma }, /* ASM1061/1062 */
613 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci }, /* ASM1061R */
614 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci }, /* ASM1062R */
615 { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci }, /* ASM1062+JMB575 */
616 { PCI_VDEVICE(ASMEDIA, 0x1062), board_ahci }, /* ASM1062A */
617 { PCI_VDEVICE(ASMEDIA, 0x1064), board_ahci }, /* ASM1064 */
618 { PCI_VDEVICE(ASMEDIA, 0x1164), board_ahci }, /* ASM1164 */
619 { PCI_VDEVICE(ASMEDIA, 0x1165), board_ahci }, /* ASM1165 */
620 { PCI_VDEVICE(ASMEDIA, 0x1166), board_ahci }, /* ASM1166 */
623 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
624 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
626 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
627 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
630 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
633 { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
635 /* Generic, PCI class code for AHCI */
636 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
637 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
639 { } /* terminate list */
642 static const struct dev_pm_ops ahci_pci_pm_ops = {
643 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
644 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
645 ahci_pci_device_runtime_resume, NULL)
648 static struct pci_driver ahci_pci_driver = {
650 .id_table = ahci_pci_tbl,
651 .probe = ahci_init_one,
652 .remove = ahci_remove_one,
653 .shutdown = ahci_shutdown_one,
655 .pm = &ahci_pci_pm_ops,
659 #if IS_ENABLED(CONFIG_PATA_MARVELL)
660 static int marvell_enable;
662 static int marvell_enable = 1;
664 module_param(marvell_enable, int, 0644);
665 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
667 static int mobile_lpm_policy = -1;
668 module_param(mobile_lpm_policy, int, 0644);
669 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
671 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
672 struct ahci_host_priv *hpriv)
674 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA && pdev->device == 0x1166) {
675 dev_info(&pdev->dev, "ASM1166 has only six ports\n");
676 hpriv->saved_port_map = 0x3f;
679 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
680 dev_info(&pdev->dev, "JMB361 has only one port\n");
681 hpriv->saved_port_map = 1;
685 * Temporary Marvell 6145 hack: PATA port presence
686 * is asserted through the standard AHCI port
687 * presence register, as bit 4 (counting from 0)
689 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
690 if (pdev->device == 0x6121)
691 hpriv->mask_port_map = 0x3;
693 hpriv->mask_port_map = 0xf;
695 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
698 ahci_save_initial_config(&pdev->dev, hpriv);
701 static int ahci_pci_reset_controller(struct ata_host *host)
703 struct pci_dev *pdev = to_pci_dev(host->dev);
704 struct ahci_host_priv *hpriv = host->private_data;
707 rc = ahci_reset_controller(host);
712 * If platform firmware failed to enable ports, try to enable
715 ahci_intel_pcs_quirk(pdev, hpriv);
720 static void ahci_pci_init_controller(struct ata_host *host)
722 struct ahci_host_priv *hpriv = host->private_data;
723 struct pci_dev *pdev = to_pci_dev(host->dev);
724 void __iomem *port_mmio;
728 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
729 if (pdev->device == 0x6121)
733 port_mmio = __ahci_port_base(hpriv, mv);
735 writel(0, port_mmio + PORT_IRQ_MASK);
738 tmp = readl(port_mmio + PORT_IRQ_STAT);
739 dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
741 writel(tmp, port_mmio + PORT_IRQ_STAT);
744 ahci_init_controller(host);
747 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
748 unsigned long deadline)
750 struct ata_port *ap = link->ap;
751 struct ahci_host_priv *hpriv = ap->host->private_data;
755 hpriv->stop_engine(ap);
757 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
758 deadline, &online, NULL);
760 hpriv->start_engine(ap);
762 /* vt8251 doesn't clear BSY on signature FIS reception,
763 * request follow-up softreset.
765 return online ? -EAGAIN : rc;
768 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
769 unsigned long deadline)
771 struct ata_port *ap = link->ap;
772 struct ahci_port_priv *pp = ap->private_data;
773 struct ahci_host_priv *hpriv = ap->host->private_data;
774 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
775 struct ata_taskfile tf;
779 hpriv->stop_engine(ap);
781 /* clear D2H reception area to properly wait for D2H FIS */
782 ata_tf_init(link->device, &tf);
783 tf.status = ATA_BUSY;
784 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
786 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
787 deadline, &online, NULL);
789 hpriv->start_engine(ap);
791 /* The pseudo configuration device on SIMG4726 attached to
792 * ASUS P5W-DH Deluxe doesn't send signature FIS after
793 * hardreset if no device is attached to the first downstream
794 * port && the pseudo device locks up on SRST w/ PMP==0. To
795 * work around this, wait for !BSY only briefly. If BSY isn't
796 * cleared, perform CLO and proceed to IDENTIFY (achieved by
797 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
799 * Wait for two seconds. Devices attached to downstream port
800 * which can't process the following IDENTIFY after this will
801 * have to be reset again. For most cases, this should
802 * suffice while making probing snappish enough.
805 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
808 ahci_kick_engine(ap);
814 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
816 * It has been observed with some SSDs that the timing of events in the
817 * link synchronization phase can leave the port in a state that can not
818 * be recovered by a SATA-hard-reset alone. The failing signature is
819 * SStatus.DET stuck at 1 ("Device presence detected but Phy
820 * communication not established"). It was found that unloading and
821 * reloading the driver when this problem occurs allows the drive
822 * connection to be recovered (DET advanced to 0x3). The critical
823 * component of reloading the driver is that the port state machines are
824 * reset by bouncing "port enable" in the AHCI PCS configuration
825 * register. So, reproduce that effect by bouncing a port whenever we
826 * see DET==1 after a reset.
828 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
829 unsigned long deadline)
831 const unsigned int *timing = sata_ehc_deb_timing(&link->eh_context);
832 struct ata_port *ap = link->ap;
833 struct ahci_port_priv *pp = ap->private_data;
834 struct ahci_host_priv *hpriv = ap->host->private_data;
835 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
836 unsigned long tmo = deadline - jiffies;
837 struct ata_taskfile tf;
841 hpriv->stop_engine(ap);
843 for (i = 0; i < 2; i++) {
846 int port = ap->port_no;
847 struct ata_host *host = ap->host;
848 struct pci_dev *pdev = to_pci_dev(host->dev);
850 /* clear D2H reception area to properly wait for D2H FIS */
851 ata_tf_init(link->device, &tf);
852 tf.status = ATA_BUSY;
853 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
855 rc = sata_link_hardreset(link, timing, deadline, &online,
858 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
859 (sstatus & 0xf) != 1)
862 ata_link_info(link, "avn bounce port%d\n", port);
864 pci_read_config_word(pdev, 0x92, &val);
866 pci_write_config_word(pdev, 0x92, val);
867 ata_msleep(ap, 1000);
869 pci_write_config_word(pdev, 0x92, val);
873 hpriv->start_engine(ap);
876 *class = ahci_dev_classify(ap);
883 static void ahci_pci_disable_interrupts(struct ata_host *host)
885 struct ahci_host_priv *hpriv = host->private_data;
886 void __iomem *mmio = hpriv->mmio;
889 /* AHCI spec rev1.1 section 8.3.3:
890 * Software must disable interrupts prior to requesting a
891 * transition of the HBA to D3 state.
893 ctl = readl(mmio + HOST_CTL);
895 writel(ctl, mmio + HOST_CTL);
896 readl(mmio + HOST_CTL); /* flush */
899 static int ahci_pci_device_runtime_suspend(struct device *dev)
901 struct pci_dev *pdev = to_pci_dev(dev);
902 struct ata_host *host = pci_get_drvdata(pdev);
904 ahci_pci_disable_interrupts(host);
908 static int ahci_pci_device_runtime_resume(struct device *dev)
910 struct pci_dev *pdev = to_pci_dev(dev);
911 struct ata_host *host = pci_get_drvdata(pdev);
914 rc = ahci_pci_reset_controller(host);
917 ahci_pci_init_controller(host);
921 #ifdef CONFIG_PM_SLEEP
922 static int ahci_pci_device_suspend(struct device *dev)
924 struct pci_dev *pdev = to_pci_dev(dev);
925 struct ata_host *host = pci_get_drvdata(pdev);
926 struct ahci_host_priv *hpriv = host->private_data;
928 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
930 "BIOS update required for suspend/resume\n");
934 ahci_pci_disable_interrupts(host);
935 ata_host_suspend(host, PMSG_SUSPEND);
939 static int ahci_pci_device_resume(struct device *dev)
941 struct pci_dev *pdev = to_pci_dev(dev);
942 struct ata_host *host = pci_get_drvdata(pdev);
945 /* Apple BIOS helpfully mangles the registers on resume */
946 if (is_mcp89_apple(pdev))
947 ahci_mcp89_apple_enable(pdev);
949 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
950 rc = ahci_pci_reset_controller(host);
954 ahci_pci_init_controller(host);
957 ata_host_resume(host);
963 #endif /* CONFIG_PM */
965 static int ahci_configure_dma_masks(struct pci_dev *pdev,
966 struct ahci_host_priv *hpriv)
971 if (hpriv->cap & HOST_CAP_64) {
973 if (hpriv->flags & AHCI_HFLAG_43BIT_ONLY)
980 * If the device fixup already set the dma_mask to some non-standard
981 * value, don't extend it here. This happens on STA2X11, for example.
983 * XXX: manipulating the DMA mask from platform code is completely
984 * bogus, platform code should use dev->bus_dma_limit instead..
986 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
989 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
991 dev_err(&pdev->dev, "DMA enable failed\n");
995 static void ahci_pci_print_info(struct ata_host *host)
997 struct pci_dev *pdev = to_pci_dev(host->dev);
1001 pci_read_config_word(pdev, 0x0a, &cc);
1002 if (cc == PCI_CLASS_STORAGE_IDE)
1004 else if (cc == PCI_CLASS_STORAGE_SATA)
1006 else if (cc == PCI_CLASS_STORAGE_RAID)
1011 ahci_print_info(host, scc_s);
1014 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
1015 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
1016 * support PMP and the 4726 either directly exports the device
1017 * attached to the first downstream port or acts as a hardware storage
1018 * controller and emulate a single ATA device (can be RAID 0/1 or some
1019 * other configuration).
1021 * When there's no device attached to the first downstream port of the
1022 * 4726, "Config Disk" appears, which is a pseudo ATA device to
1023 * configure the 4726. However, ATA emulation of the device is very
1024 * lame. It doesn't send signature D2H Reg FIS after the initial
1025 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
1027 * The following function works around the problem by always using
1028 * hardreset on the port and not depending on receiving signature FIS
1029 * afterward. If signature FIS isn't received soon, ATA class is
1030 * assumed without follow-up softreset.
1032 static void ahci_p5wdh_workaround(struct ata_host *host)
1034 static const struct dmi_system_id sysids[] = {
1036 .ident = "P5W DH Deluxe",
1038 DMI_MATCH(DMI_SYS_VENDOR,
1039 "ASUSTEK COMPUTER INC"),
1040 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1045 struct pci_dev *pdev = to_pci_dev(host->dev);
1047 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1048 dmi_check_system(sysids)) {
1049 struct ata_port *ap = host->ports[1];
1051 dev_info(&pdev->dev,
1052 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1054 ap->ops = &ahci_p5wdh_ops;
1055 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1060 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1061 * booting in BIOS compatibility mode. We restore the registers but not ID.
1063 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1067 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1069 pci_read_config_dword(pdev, 0xf8, &val);
1071 /* the following changes the device ID, but appears not to affect function */
1072 /* val = (val & ~0xf0000000) | 0x80000000; */
1073 pci_write_config_dword(pdev, 0xf8, val);
1075 pci_read_config_dword(pdev, 0x54c, &val);
1077 pci_write_config_dword(pdev, 0x54c, val);
1079 pci_read_config_dword(pdev, 0x4a4, &val);
1082 pci_write_config_dword(pdev, 0x4a4, val);
1084 pci_read_config_dword(pdev, 0x54c, &val);
1086 pci_write_config_dword(pdev, 0x54c, val);
1088 pci_read_config_dword(pdev, 0xf8, &val);
1089 val &= ~(1 << 0x1b);
1090 pci_write_config_dword(pdev, 0xf8, val);
1093 static bool is_mcp89_apple(struct pci_dev *pdev)
1095 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1096 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1097 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1098 pdev->subsystem_device == 0xcb89;
1101 /* only some SB600 ahci controllers can do 64bit DMA */
1102 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1104 static const struct dmi_system_id sysids[] = {
1106 * The oldest version known to be broken is 0901 and
1107 * working is 1501 which was released on 2007-10-26.
1108 * Enable 64bit DMA on 1501 and anything newer.
1110 * Please read bko#9412 for more info.
1113 .ident = "ASUS M2A-VM",
1115 DMI_MATCH(DMI_BOARD_VENDOR,
1116 "ASUSTeK Computer INC."),
1117 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1119 .driver_data = "20071026", /* yyyymmdd */
1122 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1123 * support 64bit DMA.
1125 * BIOS versions earlier than 1.5 had the Manufacturer DMI
1126 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1127 * This spelling mistake was fixed in BIOS version 1.5, so
1128 * 1.5 and later have the Manufacturer as
1129 * "MICRO-STAR INTERNATIONAL CO.,LTD".
1130 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1132 * BIOS versions earlier than 1.9 had a Board Product Name
1133 * DMI field of "MS-7376". This was changed to be
1134 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1135 * match on DMI_BOARD_NAME of "MS-7376".
1138 .ident = "MSI K9A2 Platinum",
1140 DMI_MATCH(DMI_BOARD_VENDOR,
1141 "MICRO-STAR INTER"),
1142 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1146 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1149 * This board also had the typo mentioned above in the
1150 * Manufacturer DMI field (fixed in BIOS version 1.5), so
1151 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1154 .ident = "MSI K9AGM2",
1156 DMI_MATCH(DMI_BOARD_VENDOR,
1157 "MICRO-STAR INTER"),
1158 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1162 * All BIOS versions for the Asus M3A support 64bit DMA.
1163 * (all release versions from 0301 to 1206 were tested)
1166 .ident = "ASUS M3A",
1168 DMI_MATCH(DMI_BOARD_VENDOR,
1169 "ASUSTeK Computer INC."),
1170 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1175 const struct dmi_system_id *match;
1176 int year, month, date;
1179 match = dmi_first_match(sysids);
1180 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1184 if (!match->driver_data)
1187 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1188 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1190 if (strcmp(buf, match->driver_data) >= 0)
1193 dev_warn(&pdev->dev,
1194 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1200 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1204 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1206 static const struct dmi_system_id broken_systems[] = {
1208 .ident = "HP Compaq nx6310",
1210 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1211 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1213 /* PCI slot number of the controller */
1214 .driver_data = (void *)0x1FUL,
1217 .ident = "HP Compaq 6720s",
1219 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1220 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1222 /* PCI slot number of the controller */
1223 .driver_data = (void *)0x1FUL,
1226 { } /* terminate list */
1228 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1231 unsigned long slot = (unsigned long)dmi->driver_data;
1232 /* apply the quirk only to on-board controllers */
1233 return slot == PCI_SLOT(pdev->devfn);
1239 static bool ahci_broken_suspend(struct pci_dev *pdev)
1241 static const struct dmi_system_id sysids[] = {
1243 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1244 * to the harddisk doesn't become online after
1245 * resuming from STR. Warn and fail suspend.
1247 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1249 * Use dates instead of versions to match as HP is
1250 * apparently recycling both product and version
1253 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1258 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1259 DMI_MATCH(DMI_PRODUCT_NAME,
1260 "HP Pavilion dv4 Notebook PC"),
1262 .driver_data = "20090105", /* F.30 */
1267 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1268 DMI_MATCH(DMI_PRODUCT_NAME,
1269 "HP Pavilion dv5 Notebook PC"),
1271 .driver_data = "20090506", /* F.16 */
1276 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1277 DMI_MATCH(DMI_PRODUCT_NAME,
1278 "HP Pavilion dv6 Notebook PC"),
1280 .driver_data = "20090423", /* F.21 */
1285 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1286 DMI_MATCH(DMI_PRODUCT_NAME,
1287 "HP HDX18 Notebook PC"),
1289 .driver_data = "20090430", /* F.23 */
1292 * Acer eMachines G725 has the same problem. BIOS
1293 * V1.03 is known to be broken. V3.04 is known to
1294 * work. Between, there are V1.06, V2.06 and V3.03
1295 * that we don't have much idea about. For now,
1296 * blacklist anything older than V3.04.
1298 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1303 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1304 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1306 .driver_data = "20091216", /* V3.04 */
1308 { } /* terminate list */
1310 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1311 int year, month, date;
1314 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1317 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1318 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1320 return strcmp(buf, dmi->driver_data) < 0;
1323 static bool ahci_broken_lpm(struct pci_dev *pdev)
1325 static const struct dmi_system_id sysids[] = {
1326 /* Various Lenovo 50 series have LPM issues with older BIOSen */
1329 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1330 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1332 .driver_data = "20180406", /* 1.31 */
1336 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1337 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1339 .driver_data = "20180420", /* 1.28 */
1343 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1344 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1346 .driver_data = "20180315", /* 1.33 */
1350 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1351 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1354 * Note date based on release notes, 2.35 has been
1355 * reported to be good, but I've been unable to get
1356 * a hold of the reporter to get the DMI BIOS date.
1359 .driver_data = "20180310", /* 2.35 */
1361 { } /* terminate list */
1363 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1364 int year, month, date;
1370 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1371 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1373 return strcmp(buf, dmi->driver_data) < 0;
1376 static bool ahci_broken_online(struct pci_dev *pdev)
1378 #define ENCODE_BUSDEVFN(bus, slot, func) \
1379 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1380 static const struct dmi_system_id sysids[] = {
1382 * There are several gigabyte boards which use
1383 * SIMG5723s configured as hardware RAID. Certain
1384 * 5723 firmware revisions shipped there keep the link
1385 * online but fail to answer properly to SRST or
1386 * IDENTIFY when no device is attached downstream
1387 * causing libata to retry quite a few times leading
1388 * to excessive detection delay.
1390 * As these firmwares respond to the second reset try
1391 * with invalid device signature, considering unknown
1392 * sig as offline works around the problem acceptably.
1395 .ident = "EP45-DQ6",
1397 DMI_MATCH(DMI_BOARD_VENDOR,
1398 "Gigabyte Technology Co., Ltd."),
1399 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1401 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1404 .ident = "EP45-DS5",
1406 DMI_MATCH(DMI_BOARD_VENDOR,
1407 "Gigabyte Technology Co., Ltd."),
1408 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1410 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1412 { } /* terminate list */
1414 #undef ENCODE_BUSDEVFN
1415 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1421 val = (unsigned long)dmi->driver_data;
1423 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1426 static bool ahci_broken_devslp(struct pci_dev *pdev)
1428 /* device with broken DEVSLP but still showing SDS capability */
1429 static const struct pci_device_id ids[] = {
1430 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1434 return pci_match_id(ids, pdev);
1437 #ifdef CONFIG_ATA_ACPI
1438 static void ahci_gtf_filter_workaround(struct ata_host *host)
1440 static const struct dmi_system_id sysids[] = {
1442 * Aspire 3810T issues a bunch of SATA enable commands
1443 * via _GTF including an invalid one and one which is
1444 * rejected by the device. Among the successful ones
1445 * is FPDMA non-zero offset enable which when enabled
1446 * only on the drive side leads to NCQ command
1447 * failures. Filter it out.
1450 .ident = "Aspire 3810T",
1452 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1453 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1455 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1459 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1460 unsigned int filter;
1466 filter = (unsigned long)dmi->driver_data;
1467 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1468 filter, dmi->ident);
1470 for (i = 0; i < host->n_ports; i++) {
1471 struct ata_port *ap = host->ports[i];
1472 struct ata_link *link;
1473 struct ata_device *dev;
1475 ata_for_each_link(link, ap, EDGE)
1476 ata_for_each_dev(dev, link, ALL)
1477 dev->gtf_filter |= filter;
1481 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1486 * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1487 * as DUMMY, or detected but eventually get a "link down" and never get up
1488 * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1489 * port_map may hold a value of 0x00.
1491 * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1492 * and can significantly reduce the occurrence of the problem.
1494 * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1496 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1497 struct pci_dev *pdev)
1499 static const struct dmi_system_id sysids[] = {
1501 .ident = "Acer Switch Alpha 12",
1503 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1504 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1510 if (dmi_check_system(sysids)) {
1511 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1512 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1513 hpriv->port_map = 0x7;
1514 hpriv->cap = 0xC734FF02;
1521 * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1522 * Workaround is to make sure all pending IRQs are served before leaving
1525 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1527 struct ata_host *host = dev_instance;
1528 struct ahci_host_priv *hpriv;
1529 unsigned int rc = 0;
1531 u32 irq_stat, irq_masked;
1532 unsigned int handled = 1;
1534 hpriv = host->private_data;
1536 irq_stat = readl(mmio + HOST_IRQ_STAT);
1541 irq_masked = irq_stat & hpriv->port_map;
1542 spin_lock(&host->lock);
1543 rc = ahci_handle_port_intr(host, irq_masked);
1546 writel(irq_stat, mmio + HOST_IRQ_STAT);
1547 irq_stat = readl(mmio + HOST_IRQ_STAT);
1548 spin_unlock(&host->lock);
1551 return IRQ_RETVAL(handled);
1555 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1556 struct ahci_host_priv *hpriv)
1562 * Check if this device might have remapped nvme devices.
1564 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1565 pci_resource_len(pdev, bar) < SZ_512K ||
1566 bar != AHCI_PCI_BAR_STANDARD ||
1567 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1570 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1571 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1572 if ((cap & (1 << i)) == 0)
1574 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1575 != PCI_CLASS_STORAGE_EXPRESS)
1578 /* We've found a remapped device */
1579 hpriv->remapped_nvme++;
1582 if (!hpriv->remapped_nvme)
1585 dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1586 hpriv->remapped_nvme);
1587 dev_warn(&pdev->dev,
1588 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1591 * Don't rely on the msi-x capability in the remap case,
1592 * share the legacy interrupt across ahci and remapped devices.
1594 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1597 static int ahci_get_irq_vector(struct ata_host *host, int port)
1599 return pci_irq_vector(to_pci_dev(host->dev), port);
1602 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1603 struct ahci_host_priv *hpriv)
1607 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1611 * If number of MSIs is less than number of ports then Sharing Last
1612 * Message mode could be enforced. In this case assume that advantage
1613 * of multipe MSIs is negated and use single MSI mode instead.
1616 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1617 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1619 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1620 hpriv->get_irq_vector = ahci_get_irq_vector;
1621 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1626 * Fallback to single MSI mode if the controller
1627 * enforced MRSM mode.
1630 "ahci: MRSM is on, fallback to single MSI\n");
1631 pci_free_irq_vectors(pdev);
1636 * If the host is not capable of supporting per-port vectors, fall
1637 * back to single MSI before finally attempting single MSI-X.
1639 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1642 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1645 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1646 struct ahci_host_priv *hpriv)
1648 int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1651 /* Ignore processing for chipsets that don't use policy */
1652 if (!(hpriv->flags & AHCI_HFLAG_USE_LPM_POLICY))
1655 /* user modified policy via module param */
1656 if (mobile_lpm_policy != -1) {
1657 policy = mobile_lpm_policy;
1661 if (policy > ATA_LPM_MED_POWER && pm_suspend_default_s2idle()) {
1662 if (hpriv->cap & HOST_CAP_PART)
1663 policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1664 else if (hpriv->cap & HOST_CAP_SSC)
1665 policy = ATA_LPM_MIN_POWER;
1669 if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1670 ap->target_lpm_policy = policy;
1673 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1675 const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1679 * Only apply the 6-port PCS quirk for known legacy platforms.
1681 if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1684 /* Skip applying the quirk on Denverton and beyond */
1685 if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1689 * port_map is determined from PORTS_IMPL PCI register which is
1690 * implemented as write or write-once register. If the register
1691 * isn't programmed, ahci automatically generates it from number
1692 * of ports, which is good enough for PCS programming. It is
1693 * otherwise expected that platform firmware enables the ports
1694 * before the OS boots.
1696 pci_read_config_word(pdev, PCS_6, &tmp16);
1697 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1698 tmp16 |= hpriv->port_map;
1699 pci_write_config_word(pdev, PCS_6, tmp16);
1703 static ssize_t remapped_nvme_show(struct device *dev,
1704 struct device_attribute *attr,
1707 struct ata_host *host = dev_get_drvdata(dev);
1708 struct ahci_host_priv *hpriv = host->private_data;
1710 return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme);
1713 static DEVICE_ATTR_RO(remapped_nvme);
1715 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1717 unsigned int board_id = ent->driver_data;
1718 struct ata_port_info pi = ahci_port_info[board_id];
1719 const struct ata_port_info *ppi[] = { &pi, NULL };
1720 struct device *dev = &pdev->dev;
1721 struct ahci_host_priv *hpriv;
1722 struct ata_host *host;
1724 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1726 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1728 ata_print_version_once(&pdev->dev, DRV_VERSION);
1730 /* The AHCI driver can only drive the SATA ports, the PATA driver
1731 can drive them all so if both drivers are selected make sure
1732 AHCI stays out of the way */
1733 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1736 /* Apple BIOS on MCP89 prevents us using AHCI */
1737 if (is_mcp89_apple(pdev))
1738 ahci_mcp89_apple_enable(pdev);
1740 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1741 * At the moment, we can only use the AHCI mode. Let the users know
1742 * that for SAS drives they're out of luck.
1744 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1745 dev_info(&pdev->dev,
1746 "PDC42819 can only drive SATA devices with this driver\n");
1748 /* Some devices use non-standard BARs */
1749 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1750 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1751 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1752 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1753 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1754 if (pdev->device == 0xa01c)
1755 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1756 if (pdev->device == 0xa084)
1757 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1758 } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1759 if (pdev->device == 0x7a08)
1760 ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1763 /* acquire resources */
1764 rc = pcim_enable_device(pdev);
1768 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1769 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1772 /* ICH6s share the same PCI ID for both piix and ahci
1773 * modes. Enabling ahci mode while MAP indicates
1774 * combined mode is a bad idea. Yield to ata_piix.
1776 pci_read_config_byte(pdev, ICH_MAP, &map);
1778 dev_info(&pdev->dev,
1779 "controller is in combined mode, can't enable AHCI mode\n");
1784 /* AHCI controllers often implement SFF compatible interface.
1785 * Grab all PCI BARs just in case.
1787 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1789 pcim_pin_device(pdev);
1793 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1796 hpriv->flags |= (unsigned long)pi.private_data;
1798 /* MCP65 revision A1 and A2 can't do MSI */
1799 if (board_id == board_ahci_mcp65 &&
1800 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1801 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1803 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1804 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1805 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1807 /* only some SB600s can do 64bit DMA */
1808 if (ahci_sb600_enable_64bit(pdev))
1809 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1811 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1813 /* detect remapped nvme devices */
1814 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1816 sysfs_add_file_to_group(&pdev->dev.kobj,
1817 &dev_attr_remapped_nvme.attr,
1820 /* must set flag prior to save config in order to take effect */
1821 if (ahci_broken_devslp(pdev))
1822 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1825 if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1826 pdev->device == 0xa235 &&
1827 pdev->revision < 0x30)
1828 hpriv->flags |= AHCI_HFLAG_NO_SXS;
1830 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1831 hpriv->irq_handler = ahci_thunderx_irq_handler;
1834 /* save initial config */
1835 ahci_pci_save_initial_config(pdev, hpriv);
1838 if (hpriv->cap & HOST_CAP_NCQ) {
1839 pi.flags |= ATA_FLAG_NCQ;
1841 * Auto-activate optimization is supposed to be
1842 * supported on all AHCI controllers indicating NCQ
1843 * capability, but it seems to be broken on some
1844 * chipsets including NVIDIAs.
1846 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1847 pi.flags |= ATA_FLAG_FPDMA_AA;
1850 * All AHCI controllers should be forward-compatible
1851 * with the new auxiliary field. This code should be
1852 * conditionalized if any buggy AHCI controllers are
1855 pi.flags |= ATA_FLAG_FPDMA_AUX;
1858 if (hpriv->cap & HOST_CAP_PMP)
1859 pi.flags |= ATA_FLAG_PMP;
1861 ahci_set_em_messages(hpriv, &pi);
1863 if (ahci_broken_system_poweroff(pdev)) {
1864 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1865 dev_info(&pdev->dev,
1866 "quirky BIOS, skipping spindown on poweroff\n");
1869 if (ahci_broken_lpm(pdev)) {
1870 pi.flags |= ATA_FLAG_NO_LPM;
1871 dev_warn(&pdev->dev,
1872 "BIOS update required for Link Power Management support\n");
1875 if (ahci_broken_suspend(pdev)) {
1876 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1877 dev_warn(&pdev->dev,
1878 "BIOS update required for suspend/resume\n");
1881 if (ahci_broken_online(pdev)) {
1882 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1883 dev_info(&pdev->dev,
1884 "online status unreliable, applying workaround\n");
1888 /* Acer SA5-271 workaround modifies private_data */
1889 acer_sa5_271_workaround(hpriv, pdev);
1891 /* CAP.NP sometimes indicate the index of the last enabled
1892 * port, at other times, that of the last possible port, so
1893 * determining the maximum port number requires looking at
1894 * both CAP.NP and port_map.
1896 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1898 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1901 host->private_data = hpriv;
1903 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1904 /* legacy intx interrupts */
1907 hpriv->irq = pci_irq_vector(pdev, 0);
1909 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1910 host->flags |= ATA_HOST_PARALLEL_SCAN;
1912 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1914 if (!(hpriv->cap & HOST_CAP_PART))
1915 host->flags |= ATA_HOST_NO_PART;
1917 if (!(hpriv->cap & HOST_CAP_SSC))
1918 host->flags |= ATA_HOST_NO_SSC;
1920 if (!(hpriv->cap2 & HOST_CAP2_SDS))
1921 host->flags |= ATA_HOST_NO_DEVSLP;
1923 if (pi.flags & ATA_FLAG_EM)
1924 ahci_reset_em(host);
1926 for (i = 0; i < host->n_ports; i++) {
1927 struct ata_port *ap = host->ports[i];
1929 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1930 ata_port_pbar_desc(ap, ahci_pci_bar,
1931 0x100 + ap->port_no * 0x80, "port");
1933 /* set enclosure management message type */
1934 if (ap->flags & ATA_FLAG_EM)
1935 ap->em_message_type = hpriv->em_msg_type;
1937 ahci_update_initial_lpm_policy(ap, hpriv);
1939 /* disabled/not-implemented port */
1940 if (!(hpriv->port_map & (1 << i)))
1941 ap->ops = &ata_dummy_port_ops;
1944 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1945 ahci_p5wdh_workaround(host);
1947 /* apply gtf filter quirk */
1948 ahci_gtf_filter_workaround(host);
1950 /* initialize adapter */
1951 rc = ahci_configure_dma_masks(pdev, hpriv);
1955 rc = ahci_pci_reset_controller(host);
1959 ahci_pci_init_controller(host);
1960 ahci_pci_print_info(host);
1962 pci_set_master(pdev);
1964 rc = ahci_host_activate(host, &ahci_sht);
1968 pm_runtime_put_noidle(&pdev->dev);
1972 static void ahci_shutdown_one(struct pci_dev *pdev)
1974 ata_pci_shutdown_one(pdev);
1977 static void ahci_remove_one(struct pci_dev *pdev)
1979 sysfs_remove_file_from_group(&pdev->dev.kobj,
1980 &dev_attr_remapped_nvme.attr,
1982 pm_runtime_get_noresume(&pdev->dev);
1983 ata_pci_remove_one(pdev);
1986 module_pci_driver(ahci_pci_driver);
1988 MODULE_AUTHOR("Jeff Garzik");
1989 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1990 MODULE_LICENSE("GPL");
1991 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1992 MODULE_VERSION(DRV_VERSION);