1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
38 #include <linux/vmalloc.h>
39 #include <linux/export.h>
40 #include <linux/moduleparam.h>
41 #include <linux/mman.h>
42 #include <linux/highmem.h>
43 #include <linux/iommu.h>
44 #include <linux/intel-iommu.h>
45 #include <linux/cpufreq.h>
46 #include <linux/user-return-notifier.h>
47 #include <linux/srcu.h>
48 #include <linux/slab.h>
49 #include <linux/perf_event.h>
50 #include <linux/uaccess.h>
51 #include <linux/hash.h>
52 #include <linux/pci.h>
53 #include <linux/timekeeper_internal.h>
54 #include <linux/pvclock_gtod.h>
55 #include <linux/kvm_irqfd.h>
56 #include <linux/irqbypass.h>
57 #include <linux/sched/stat.h>
58 #include <linux/sched/isolation.h>
59 #include <linux/mem_encrypt.h>
60 #include <linux/entry-kvm.h>
61 #include <linux/suspend.h>
63 #include <trace/events/kvm.h>
65 #include <asm/debugreg.h>
70 #include <linux/kernel_stat.h>
71 #include <asm/fpu/api.h>
72 #include <asm/fpu/xcr.h>
73 #include <asm/fpu/xstate.h>
74 #include <asm/pvclock.h>
75 #include <asm/div64.h>
76 #include <asm/irq_remapping.h>
77 #include <asm/mshyperv.h>
78 #include <asm/hypervisor.h>
79 #include <asm/tlbflush.h>
80 #include <asm/intel_pt.h>
81 #include <asm/emulate_prefix.h>
83 #include <clocksource/hyperv_timer.h>
85 #define CREATE_TRACE_POINTS
88 #define MAX_IO_MSRS 256
89 #define KVM_MAX_MCE_BANKS 32
90 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
91 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
93 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
95 #define emul_to_vcpu(ctxt) \
96 ((struct kvm_vcpu *)(ctxt)->vcpu)
99 * - enable syscall per default because its emulated by KVM
100 * - enable LME and LMA per default on 64 bit KVM
104 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
106 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
109 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
111 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE)
113 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE
115 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
116 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
118 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
119 static void process_nmi(struct kvm_vcpu *vcpu);
120 static void process_smi(struct kvm_vcpu *vcpu);
121 static void enter_smm(struct kvm_vcpu *vcpu);
122 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
123 static void store_regs(struct kvm_vcpu *vcpu);
124 static int sync_regs(struct kvm_vcpu *vcpu);
125 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu);
127 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
128 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
130 struct kvm_x86_ops kvm_x86_ops __read_mostly;
132 #define KVM_X86_OP(func) \
133 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \
134 *(((struct kvm_x86_ops *)0)->func));
135 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
136 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
137 #include <asm/kvm-x86-ops.h>
138 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
139 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg);
141 static bool __read_mostly ignore_msrs = 0;
142 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
144 bool __read_mostly report_ignored_msrs = true;
145 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
146 EXPORT_SYMBOL_GPL(report_ignored_msrs);
148 unsigned int min_timer_period_us = 200;
149 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
151 static bool __read_mostly kvmclock_periodic_sync = true;
152 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
154 bool __read_mostly kvm_has_tsc_control;
155 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
156 u32 __read_mostly kvm_max_guest_tsc_khz;
157 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
158 u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
159 EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
160 u64 __read_mostly kvm_max_tsc_scaling_ratio;
161 EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
162 u64 __read_mostly kvm_default_tsc_scaling_ratio;
163 EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
164 bool __read_mostly kvm_has_bus_lock_exit;
165 EXPORT_SYMBOL_GPL(kvm_has_bus_lock_exit);
167 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
168 static u32 __read_mostly tsc_tolerance_ppm = 250;
169 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
172 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
173 * adaptive tuning starting from default advancement of 1000ns. '0' disables
174 * advancement entirely. Any other value is used as-is and disables adaptive
175 * tuning, i.e. allows privileged userspace to set an exact advancement time.
177 static int __read_mostly lapic_timer_advance_ns = -1;
178 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
180 static bool __read_mostly vector_hashing = true;
181 module_param(vector_hashing, bool, S_IRUGO);
183 bool __read_mostly enable_vmware_backdoor = false;
184 module_param(enable_vmware_backdoor, bool, S_IRUGO);
185 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
187 static bool __read_mostly force_emulation_prefix = false;
188 module_param(force_emulation_prefix, bool, S_IRUGO);
190 int __read_mostly pi_inject_timer = -1;
191 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
193 /* Enable/disable PMU virtualization */
194 bool __read_mostly enable_pmu = true;
195 EXPORT_SYMBOL_GPL(enable_pmu);
196 module_param(enable_pmu, bool, 0444);
198 bool __read_mostly eager_page_split = true;
199 module_param(eager_page_split, bool, 0644);
202 * Restoring the host value for MSRs that are only consumed when running in
203 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
204 * returns to userspace, i.e. the kernel can run with the guest's value.
206 #define KVM_MAX_NR_USER_RETURN_MSRS 16
208 struct kvm_user_return_msrs {
209 struct user_return_notifier urn;
211 struct kvm_user_return_msr_values {
214 } values[KVM_MAX_NR_USER_RETURN_MSRS];
217 u32 __read_mostly kvm_nr_uret_msrs;
218 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs);
219 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS];
220 static struct kvm_user_return_msrs __percpu *user_return_msrs;
222 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
223 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
224 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
225 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE)
227 u64 __read_mostly host_efer;
228 EXPORT_SYMBOL_GPL(host_efer);
230 bool __read_mostly allow_smaller_maxphyaddr = 0;
231 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
233 bool __read_mostly enable_apicv = true;
234 EXPORT_SYMBOL_GPL(enable_apicv);
236 u64 __read_mostly host_xss;
237 EXPORT_SYMBOL_GPL(host_xss);
238 u64 __read_mostly supported_xss;
239 EXPORT_SYMBOL_GPL(supported_xss);
241 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
242 KVM_GENERIC_VM_STATS(),
243 STATS_DESC_COUNTER(VM, mmu_shadow_zapped),
244 STATS_DESC_COUNTER(VM, mmu_pte_write),
245 STATS_DESC_COUNTER(VM, mmu_pde_zapped),
246 STATS_DESC_COUNTER(VM, mmu_flooded),
247 STATS_DESC_COUNTER(VM, mmu_recycled),
248 STATS_DESC_COUNTER(VM, mmu_cache_miss),
249 STATS_DESC_ICOUNTER(VM, mmu_unsync),
250 STATS_DESC_ICOUNTER(VM, pages_4k),
251 STATS_DESC_ICOUNTER(VM, pages_2m),
252 STATS_DESC_ICOUNTER(VM, pages_1g),
253 STATS_DESC_ICOUNTER(VM, nx_lpage_splits),
254 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size),
255 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions)
258 const struct kvm_stats_header kvm_vm_stats_header = {
259 .name_size = KVM_STATS_NAME_SIZE,
260 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
261 .id_offset = sizeof(struct kvm_stats_header),
262 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
263 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
264 sizeof(kvm_vm_stats_desc),
267 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
268 KVM_GENERIC_VCPU_STATS(),
269 STATS_DESC_COUNTER(VCPU, pf_fixed),
270 STATS_DESC_COUNTER(VCPU, pf_guest),
271 STATS_DESC_COUNTER(VCPU, tlb_flush),
272 STATS_DESC_COUNTER(VCPU, invlpg),
273 STATS_DESC_COUNTER(VCPU, exits),
274 STATS_DESC_COUNTER(VCPU, io_exits),
275 STATS_DESC_COUNTER(VCPU, mmio_exits),
276 STATS_DESC_COUNTER(VCPU, signal_exits),
277 STATS_DESC_COUNTER(VCPU, irq_window_exits),
278 STATS_DESC_COUNTER(VCPU, nmi_window_exits),
279 STATS_DESC_COUNTER(VCPU, l1d_flush),
280 STATS_DESC_COUNTER(VCPU, halt_exits),
281 STATS_DESC_COUNTER(VCPU, request_irq_exits),
282 STATS_DESC_COUNTER(VCPU, irq_exits),
283 STATS_DESC_COUNTER(VCPU, host_state_reload),
284 STATS_DESC_COUNTER(VCPU, fpu_reload),
285 STATS_DESC_COUNTER(VCPU, insn_emulation),
286 STATS_DESC_COUNTER(VCPU, insn_emulation_fail),
287 STATS_DESC_COUNTER(VCPU, hypercalls),
288 STATS_DESC_COUNTER(VCPU, irq_injections),
289 STATS_DESC_COUNTER(VCPU, nmi_injections),
290 STATS_DESC_COUNTER(VCPU, req_event),
291 STATS_DESC_COUNTER(VCPU, nested_run),
292 STATS_DESC_COUNTER(VCPU, directed_yield_attempted),
293 STATS_DESC_COUNTER(VCPU, directed_yield_successful),
294 STATS_DESC_ICOUNTER(VCPU, guest_mode)
297 const struct kvm_stats_header kvm_vcpu_stats_header = {
298 .name_size = KVM_STATS_NAME_SIZE,
299 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
300 .id_offset = sizeof(struct kvm_stats_header),
301 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
302 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
303 sizeof(kvm_vcpu_stats_desc),
306 u64 __read_mostly host_xcr0;
307 u64 __read_mostly supported_xcr0;
308 EXPORT_SYMBOL_GPL(supported_xcr0);
310 static struct kmem_cache *x86_emulator_cache;
313 * When called, it means the previous get/set msr reached an invalid msr.
314 * Return true if we want to ignore/silent this failed msr access.
316 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write)
318 const char *op = write ? "wrmsr" : "rdmsr";
321 if (report_ignored_msrs)
322 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
327 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
333 static struct kmem_cache *kvm_alloc_emulator_cache(void)
335 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
336 unsigned int size = sizeof(struct x86_emulate_ctxt);
338 return kmem_cache_create_usercopy("x86_emulator", size,
339 __alignof__(struct x86_emulate_ctxt),
340 SLAB_ACCOUNT, useroffset,
341 size - useroffset, NULL);
344 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
346 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
349 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
350 vcpu->arch.apf.gfns[i] = ~0;
353 static void kvm_on_user_return(struct user_return_notifier *urn)
356 struct kvm_user_return_msrs *msrs
357 = container_of(urn, struct kvm_user_return_msrs, urn);
358 struct kvm_user_return_msr_values *values;
362 * Disabling irqs at this point since the following code could be
363 * interrupted and executed through kvm_arch_hardware_disable()
365 local_irq_save(flags);
366 if (msrs->registered) {
367 msrs->registered = false;
368 user_return_notifier_unregister(urn);
370 local_irq_restore(flags);
371 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) {
372 values = &msrs->values[slot];
373 if (values->host != values->curr) {
374 wrmsrl(kvm_uret_msrs_list[slot], values->host);
375 values->curr = values->host;
380 static int kvm_probe_user_return_msr(u32 msr)
386 ret = rdmsrl_safe(msr, &val);
389 ret = wrmsrl_safe(msr, val);
395 int kvm_add_user_return_msr(u32 msr)
397 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS);
399 if (kvm_probe_user_return_msr(msr))
402 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr;
403 return kvm_nr_uret_msrs++;
405 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr);
407 int kvm_find_user_return_msr(u32 msr)
411 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
412 if (kvm_uret_msrs_list[i] == msr)
417 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr);
419 static void kvm_user_return_msr_cpu_online(void)
421 unsigned int cpu = smp_processor_id();
422 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
426 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
427 rdmsrl_safe(kvm_uret_msrs_list[i], &value);
428 msrs->values[i].host = value;
429 msrs->values[i].curr = value;
433 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
435 unsigned int cpu = smp_processor_id();
436 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
439 value = (value & mask) | (msrs->values[slot].host & ~mask);
440 if (value == msrs->values[slot].curr)
442 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value);
446 msrs->values[slot].curr = value;
447 if (!msrs->registered) {
448 msrs->urn.on_user_return = kvm_on_user_return;
449 user_return_notifier_register(&msrs->urn);
450 msrs->registered = true;
454 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
456 static void drop_user_return_notifiers(void)
458 unsigned int cpu = smp_processor_id();
459 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
461 if (msrs->registered)
462 kvm_on_user_return(&msrs->urn);
465 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
467 return vcpu->arch.apic_base;
469 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
471 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
473 return kvm_apic_mode(kvm_get_apic_base(vcpu));
475 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
477 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
479 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
480 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
481 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
482 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
484 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
486 if (!msr_info->host_initiated) {
487 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
489 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
493 kvm_lapic_set_base(vcpu, msr_info->data);
494 kvm_recalculate_apic_map(vcpu->kvm);
497 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
500 * Handle a fault on a hardware virtualization (VMX or SVM) instruction.
502 * Hardware virtualization extension instructions may fault if a reboot turns
503 * off virtualization while processes are running. Usually after catching the
504 * fault we just panic; during reboot instead the instruction is ignored.
506 noinstr void kvm_spurious_fault(void)
508 /* Fault while not rebooting. We want the trace. */
509 BUG_ON(!kvm_rebooting);
511 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
513 #define EXCPT_BENIGN 0
514 #define EXCPT_CONTRIBUTORY 1
517 static int exception_class(int vector)
527 return EXCPT_CONTRIBUTORY;
534 #define EXCPT_FAULT 0
536 #define EXCPT_ABORT 2
537 #define EXCPT_INTERRUPT 3
539 static int exception_type(int vector)
543 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
544 return EXCPT_INTERRUPT;
548 /* #DB is trap, as instruction watchpoints are handled elsewhere */
549 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
552 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
555 /* Reserved exceptions will result in fault */
559 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
561 unsigned nr = vcpu->arch.exception.nr;
562 bool has_payload = vcpu->arch.exception.has_payload;
563 unsigned long payload = vcpu->arch.exception.payload;
571 * "Certain debug exceptions may clear bit 0-3. The
572 * remaining contents of the DR6 register are never
573 * cleared by the processor".
575 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
577 * In order to reflect the #DB exception payload in guest
578 * dr6, three components need to be considered: active low
579 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
581 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
582 * In the target guest dr6:
583 * FIXED_1 bits should always be set.
584 * Active low bits should be cleared if 1-setting in payload.
585 * Active high bits should be set if 1-setting in payload.
587 * Note, the payload is compatible with the pending debug
588 * exceptions/exit qualification under VMX, that active_low bits
589 * are active high in payload.
590 * So they need to be flipped for DR6.
592 vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
593 vcpu->arch.dr6 |= payload;
594 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW;
597 * The #DB payload is defined as compatible with the 'pending
598 * debug exceptions' field under VMX, not DR6. While bit 12 is
599 * defined in the 'pending debug exceptions' field (enabled
600 * breakpoint), it is reserved and must be zero in DR6.
602 vcpu->arch.dr6 &= ~BIT(12);
605 vcpu->arch.cr2 = payload;
609 vcpu->arch.exception.has_payload = false;
610 vcpu->arch.exception.payload = 0;
612 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
614 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
615 unsigned nr, bool has_error, u32 error_code,
616 bool has_payload, unsigned long payload, bool reinject)
621 kvm_make_request(KVM_REQ_EVENT, vcpu);
623 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
627 * On vmentry, vcpu->arch.exception.pending is only
628 * true if an event injection was blocked by
629 * nested_run_pending. In that case, however,
630 * vcpu_enter_guest requests an immediate exit,
631 * and the guest shouldn't proceed far enough to
634 WARN_ON_ONCE(vcpu->arch.exception.pending);
635 vcpu->arch.exception.injected = true;
636 if (WARN_ON_ONCE(has_payload)) {
638 * A reinjected event has already
639 * delivered its payload.
645 vcpu->arch.exception.pending = true;
646 vcpu->arch.exception.injected = false;
648 vcpu->arch.exception.has_error_code = has_error;
649 vcpu->arch.exception.nr = nr;
650 vcpu->arch.exception.error_code = error_code;
651 vcpu->arch.exception.has_payload = has_payload;
652 vcpu->arch.exception.payload = payload;
653 if (!is_guest_mode(vcpu))
654 kvm_deliver_exception_payload(vcpu);
658 /* to check exception */
659 prev_nr = vcpu->arch.exception.nr;
660 if (prev_nr == DF_VECTOR) {
661 /* triple fault -> shutdown */
662 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
665 class1 = exception_class(prev_nr);
666 class2 = exception_class(nr);
667 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
668 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
670 * Generate double fault per SDM Table 5-5. Set
671 * exception.pending = true so that the double fault
672 * can trigger a nested vmexit.
674 vcpu->arch.exception.pending = true;
675 vcpu->arch.exception.injected = false;
676 vcpu->arch.exception.has_error_code = true;
677 vcpu->arch.exception.nr = DF_VECTOR;
678 vcpu->arch.exception.error_code = 0;
679 vcpu->arch.exception.has_payload = false;
680 vcpu->arch.exception.payload = 0;
682 /* replace previous exception with a new one in a hope
683 that instruction re-execution will regenerate lost
688 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
690 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
692 EXPORT_SYMBOL_GPL(kvm_queue_exception);
694 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
696 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
698 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
700 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
701 unsigned long payload)
703 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
705 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
707 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
708 u32 error_code, unsigned long payload)
710 kvm_multiple_exception(vcpu, nr, true, error_code,
711 true, payload, false);
714 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
717 kvm_inject_gp(vcpu, 0);
719 return kvm_skip_emulated_instruction(vcpu);
723 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
725 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err)
728 kvm_inject_gp(vcpu, 0);
732 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
733 EMULTYPE_COMPLETE_USER_EXIT);
736 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
738 ++vcpu->stat.pf_guest;
739 vcpu->arch.exception.nested_apf =
740 is_guest_mode(vcpu) && fault->async_page_fault;
741 if (vcpu->arch.exception.nested_apf) {
742 vcpu->arch.apf.nested_apf_token = fault->address;
743 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
745 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
749 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
751 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
752 struct x86_exception *fault)
754 struct kvm_mmu *fault_mmu;
755 WARN_ON_ONCE(fault->vector != PF_VECTOR);
757 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
761 * Invalidate the TLB entry for the faulting address, if it exists,
762 * else the access will fault indefinitely (and to emulate hardware).
764 if ((fault->error_code & PFERR_PRESENT_MASK) &&
765 !(fault->error_code & PFERR_RSVD_MASK))
766 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
767 fault_mmu->root.hpa);
769 fault_mmu->inject_page_fault(vcpu, fault);
770 return fault->nested_page_fault;
772 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
774 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
776 atomic_inc(&vcpu->arch.nmi_queued);
777 kvm_make_request(KVM_REQ_NMI, vcpu);
779 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
781 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
783 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
785 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
787 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
789 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
791 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
794 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
795 * a #GP and return false.
797 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
799 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl)
801 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
804 EXPORT_SYMBOL_GPL(kvm_require_cpl);
806 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
808 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
811 kvm_queue_exception(vcpu, UD_VECTOR);
814 EXPORT_SYMBOL_GPL(kvm_require_dr);
816 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
818 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2);
822 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
824 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
826 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
827 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
831 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
834 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated
837 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn),
838 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL);
839 if (real_gpa == UNMAPPED_GVA)
842 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */
843 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte,
844 cr3 & GENMASK(11, 5), sizeof(pdpte));
848 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
849 if ((pdpte[i] & PT_PRESENT_MASK) &&
850 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
856 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled.
857 * Shadow page roots need to be reconstructed instead.
859 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)))
860 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT);
862 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
863 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
864 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
865 vcpu->arch.pdptrs_from_userspace = false;
869 EXPORT_SYMBOL_GPL(load_pdptrs);
871 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
873 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
874 kvm_clear_async_pf_completion_queue(vcpu);
875 kvm_async_pf_hash_reset(vcpu);
878 * Clearing CR0.PG is defined to flush the TLB from the guest's
881 if (!(cr0 & X86_CR0_PG))
882 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
885 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS)
886 kvm_mmu_reset_context(vcpu);
888 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
889 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
890 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
891 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
893 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
895 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
897 unsigned long old_cr0 = kvm_read_cr0(vcpu);
902 if (cr0 & 0xffffffff00000000UL)
906 cr0 &= ~CR0_RESERVED_BITS;
908 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
911 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
915 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
916 (cr0 & X86_CR0_PG)) {
921 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
926 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
927 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) &&
928 !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
931 if (!(cr0 & X86_CR0_PG) &&
932 (is_64_bit_mode(vcpu) || kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)))
935 static_call(kvm_x86_set_cr0)(vcpu, cr0);
937 kvm_post_set_cr0(vcpu, old_cr0, cr0);
941 EXPORT_SYMBOL_GPL(kvm_set_cr0);
943 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
945 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
947 EXPORT_SYMBOL_GPL(kvm_lmsw);
949 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
951 if (vcpu->arch.guest_state_protected)
954 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
956 if (vcpu->arch.xcr0 != host_xcr0)
957 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
959 if (vcpu->arch.xsaves_enabled &&
960 vcpu->arch.ia32_xss != host_xss)
961 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
964 if (static_cpu_has(X86_FEATURE_PKU) &&
965 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
966 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU)) &&
967 vcpu->arch.pkru != vcpu->arch.host_pkru)
968 write_pkru(vcpu->arch.pkru);
970 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
972 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
974 if (vcpu->arch.guest_state_protected)
977 if (static_cpu_has(X86_FEATURE_PKU) &&
978 (kvm_read_cr4_bits(vcpu, X86_CR4_PKE) ||
979 (vcpu->arch.xcr0 & XFEATURE_MASK_PKRU))) {
980 vcpu->arch.pkru = rdpkru();
981 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
982 write_pkru(vcpu->arch.host_pkru);
985 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
987 if (vcpu->arch.xcr0 != host_xcr0)
988 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
990 if (vcpu->arch.xsaves_enabled &&
991 vcpu->arch.ia32_xss != host_xss)
992 wrmsrl(MSR_IA32_XSS, host_xss);
996 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
998 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
1001 u64 old_xcr0 = vcpu->arch.xcr0;
1004 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
1005 if (index != XCR_XFEATURE_ENABLED_MASK)
1007 if (!(xcr0 & XFEATURE_MASK_FP))
1009 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
1013 * Do not allow the guest to set bits that we do not support
1014 * saving. However, xcr0 bit 0 is always set, even if the
1015 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()).
1017 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
1018 if (xcr0 & ~valid_bits)
1021 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
1022 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
1025 if (xcr0 & XFEATURE_MASK_AVX512) {
1026 if (!(xcr0 & XFEATURE_MASK_YMM))
1028 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
1032 if ((xcr0 & XFEATURE_MASK_XTILE) &&
1033 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE))
1036 vcpu->arch.xcr0 = xcr0;
1038 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
1039 kvm_update_cpuid_runtime(vcpu);
1043 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu)
1045 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 ||
1046 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) {
1047 kvm_inject_gp(vcpu, 0);
1051 return kvm_skip_emulated_instruction(vcpu);
1053 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv);
1055 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1057 if (cr4 & cr4_reserved_bits)
1060 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
1063 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4);
1065 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4);
1067 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
1069 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
1070 kvm_mmu_reset_context(vcpu);
1073 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB
1074 * according to the SDM; however, stale prev_roots could be reused
1075 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we
1076 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST
1077 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed,
1081 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE))
1082 kvm_make_request(KVM_REQ_MMU_RELOAD, vcpu);
1085 * The TLB has to be flushed for all PCIDs if any of the following
1086 * (architecturally required) changes happen:
1087 * - CR4.PCIDE is changed from 1 to 0
1088 * - CR4.PGE is toggled
1090 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT.
1092 if (((cr4 ^ old_cr4) & X86_CR4_PGE) ||
1093 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1094 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1097 * The TLB has to be flushed for the current PCID if any of the
1098 * following (architecturally required) changes happen:
1099 * - CR4.SMEP is changed from 0 to 1
1100 * - CR4.PAE is toggled
1102 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) ||
1103 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP)))
1104 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1107 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1109 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1111 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1113 if (!kvm_is_valid_cr4(vcpu, cr4))
1116 if (is_long_mode(vcpu)) {
1117 if (!(cr4 & X86_CR4_PAE))
1119 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1121 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1122 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS)
1123 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
1126 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1127 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1130 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1131 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1135 static_call(kvm_x86_set_cr4)(vcpu, cr4);
1137 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1141 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1143 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid)
1145 struct kvm_mmu *mmu = vcpu->arch.mmu;
1146 unsigned long roots_to_free = 0;
1150 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but
1151 * this is reachable when running EPT=1 and unrestricted_guest=0, and
1152 * also via the emulator. KVM's TDP page tables are not in the scope of
1153 * the invalidation, but the guest's TLB entries need to be flushed as
1154 * the CPU may have cached entries in its TLB for the target PCID.
1156 if (unlikely(tdp_enabled)) {
1157 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1162 * If neither the current CR3 nor any of the prev_roots use the given
1163 * PCID, then nothing needs to be done here because a resync will
1164 * happen anyway before switching to any other CR3.
1166 if (kvm_get_active_pcid(vcpu) == pcid) {
1167 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1168 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1172 * If PCID is disabled, there is no need to free prev_roots even if the
1173 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB
1176 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
1179 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
1180 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid)
1181 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
1183 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
1186 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1188 bool skip_tlb_flush = false;
1189 unsigned long pcid = 0;
1190 #ifdef CONFIG_X86_64
1191 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1194 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1195 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1196 pcid = cr3 & X86_CR3_PCID_MASK;
1200 /* PDPTRs are always reloaded for PAE paging. */
1201 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu))
1202 goto handle_tlb_flush;
1205 * Do not condition the GPA check on long mode, this helper is used to
1206 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that
1207 * the current vCPU mode is accurate.
1209 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3))
1212 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3))
1215 if (cr3 != kvm_read_cr3(vcpu))
1216 kvm_mmu_new_pgd(vcpu, cr3);
1218 vcpu->arch.cr3 = cr3;
1219 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
1220 /* Do not call post_set_cr3, we do not get here for confidential guests. */
1224 * A load of CR3 that flushes the TLB flushes only the current PCID,
1225 * even if PCID is disabled, in which case PCID=0 is flushed. It's a
1226 * moot point in the end because _disabling_ PCID will flush all PCIDs,
1227 * and it's impossible to use a non-zero PCID when PCID is disabled,
1228 * i.e. only PCID=0 can be relevant.
1230 if (!skip_tlb_flush)
1231 kvm_invalidate_pcid(vcpu, pcid);
1235 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1237 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1239 if (cr8 & CR8_RESERVED_BITS)
1241 if (lapic_in_kernel(vcpu))
1242 kvm_lapic_set_tpr(vcpu, cr8);
1244 vcpu->arch.cr8 = cr8;
1247 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1249 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1251 if (lapic_in_kernel(vcpu))
1252 return kvm_lapic_get_cr8(vcpu);
1254 return vcpu->arch.cr8;
1256 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1258 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1262 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1263 for (i = 0; i < KVM_NR_DB_REGS; i++)
1264 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1268 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1272 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1273 dr7 = vcpu->arch.guest_debug_dr7;
1275 dr7 = vcpu->arch.dr7;
1276 static_call(kvm_x86_set_dr7)(vcpu, dr7);
1277 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1278 if (dr7 & DR7_BP_EN_MASK)
1279 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1281 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1283 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1285 u64 fixed = DR6_FIXED_1;
1287 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1290 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1291 fixed |= DR6_BUS_LOCK;
1295 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1297 size_t size = ARRAY_SIZE(vcpu->arch.db);
1301 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1302 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1303 vcpu->arch.eff_db[dr] = val;
1307 if (!kvm_dr6_valid(val))
1309 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1313 if (!kvm_dr7_valid(val))
1315 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1316 kvm_update_dr7(vcpu);
1322 EXPORT_SYMBOL_GPL(kvm_set_dr);
1324 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1326 size_t size = ARRAY_SIZE(vcpu->arch.db);
1330 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1334 *val = vcpu->arch.dr6;
1338 *val = vcpu->arch.dr7;
1342 EXPORT_SYMBOL_GPL(kvm_get_dr);
1344 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu)
1346 u32 ecx = kvm_rcx_read(vcpu);
1349 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) {
1350 kvm_inject_gp(vcpu, 0);
1354 kvm_rax_write(vcpu, (u32)data);
1355 kvm_rdx_write(vcpu, data >> 32);
1356 return kvm_skip_emulated_instruction(vcpu);
1358 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc);
1361 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1362 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1364 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1365 * extract the supported MSRs from the related const lists.
1366 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1367 * capabilities of the host cpu. This capabilities test skips MSRs that are
1368 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1369 * may depend on host virtualization features rather than host cpu features.
1372 static const u32 msrs_to_save_all[] = {
1373 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1375 #ifdef CONFIG_X86_64
1376 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1378 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1379 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1381 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1382 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1383 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1384 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1385 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1386 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1387 MSR_IA32_UMWAIT_CONTROL,
1389 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1390 MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
1391 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1392 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1393 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1394 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1395 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1396 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1397 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1398 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1399 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1400 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1401 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1402 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1403 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1404 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1405 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1406 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1407 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1408 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1409 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1410 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1412 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
1413 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
1414 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
1415 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
1416 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
1417 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
1418 MSR_IA32_XFD, MSR_IA32_XFD_ERR,
1421 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1422 static unsigned num_msrs_to_save;
1424 static const u32 emulated_msrs_all[] = {
1425 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1426 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1427 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1428 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1429 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1430 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1431 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1433 HV_X64_MSR_VP_INDEX,
1434 HV_X64_MSR_VP_RUNTIME,
1435 HV_X64_MSR_SCONTROL,
1436 HV_X64_MSR_STIMER0_CONFIG,
1437 HV_X64_MSR_VP_ASSIST_PAGE,
1438 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1439 HV_X64_MSR_TSC_EMULATION_STATUS,
1440 HV_X64_MSR_SYNDBG_OPTIONS,
1441 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1442 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1443 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1445 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1446 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1448 MSR_IA32_TSC_ADJUST,
1449 MSR_IA32_TSC_DEADLINE,
1450 MSR_IA32_ARCH_CAPABILITIES,
1451 MSR_IA32_PERF_CAPABILITIES,
1452 MSR_IA32_MISC_ENABLE,
1453 MSR_IA32_MCG_STATUS,
1455 MSR_IA32_MCG_EXT_CTL,
1459 MSR_MISC_FEATURES_ENABLES,
1460 MSR_AMD64_VIRT_SPEC_CTRL,
1461 MSR_AMD64_TSC_RATIO,
1466 * The following list leaves out MSRs whose values are determined
1467 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1468 * We always support the "true" VMX control MSRs, even if the host
1469 * processor does not, so I am putting these registers here rather
1470 * than in msrs_to_save_all.
1473 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1474 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1475 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1476 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1478 MSR_IA32_VMX_CR0_FIXED0,
1479 MSR_IA32_VMX_CR4_FIXED0,
1480 MSR_IA32_VMX_VMCS_ENUM,
1481 MSR_IA32_VMX_PROCBASED_CTLS2,
1482 MSR_IA32_VMX_EPT_VPID_CAP,
1483 MSR_IA32_VMX_VMFUNC,
1486 MSR_KVM_POLL_CONTROL,
1489 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1490 static unsigned num_emulated_msrs;
1493 * List of msr numbers which are used to expose MSR-based features that
1494 * can be used by a hypervisor to validate requested CPU features.
1496 static const u32 msr_based_features_all[] = {
1498 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1499 MSR_IA32_VMX_PINBASED_CTLS,
1500 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1501 MSR_IA32_VMX_PROCBASED_CTLS,
1502 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1503 MSR_IA32_VMX_EXIT_CTLS,
1504 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1505 MSR_IA32_VMX_ENTRY_CTLS,
1507 MSR_IA32_VMX_CR0_FIXED0,
1508 MSR_IA32_VMX_CR0_FIXED1,
1509 MSR_IA32_VMX_CR4_FIXED0,
1510 MSR_IA32_VMX_CR4_FIXED1,
1511 MSR_IA32_VMX_VMCS_ENUM,
1512 MSR_IA32_VMX_PROCBASED_CTLS2,
1513 MSR_IA32_VMX_EPT_VPID_CAP,
1514 MSR_IA32_VMX_VMFUNC,
1518 MSR_IA32_ARCH_CAPABILITIES,
1519 MSR_IA32_PERF_CAPABILITIES,
1522 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1523 static unsigned int num_msr_based_features;
1525 static u64 kvm_get_arch_capabilities(void)
1529 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1530 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1533 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1534 * the nested hypervisor runs with NX huge pages. If it is not,
1535 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other
1536 * L1 guests, so it need not worry about its own (L2) guests.
1538 data |= ARCH_CAP_PSCHANGE_MC_NO;
1541 * If we're doing cache flushes (either "always" or "cond")
1542 * we will do one whenever the guest does a vmlaunch/vmresume.
1543 * If an outer hypervisor is doing the cache flush for us
1544 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1545 * capability to the guest too, and if EPT is disabled we're not
1546 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1547 * require a nested hypervisor to do a flush of its own.
1549 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1550 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1552 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1553 data |= ARCH_CAP_RDCL_NO;
1554 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1555 data |= ARCH_CAP_SSB_NO;
1556 if (!boot_cpu_has_bug(X86_BUG_MDS))
1557 data |= ARCH_CAP_MDS_NO;
1559 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1561 * If RTM=0 because the kernel has disabled TSX, the host might
1562 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1563 * and therefore knows that there cannot be TAA) but keep
1564 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1565 * and we want to allow migrating those guests to tsx=off hosts.
1567 data &= ~ARCH_CAP_TAA_NO;
1568 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1569 data |= ARCH_CAP_TAA_NO;
1572 * Nothing to do here; we emulate TSX_CTRL if present on the
1573 * host so the guest can choose between disabling TSX or
1574 * using VERW to clear CPU buffers.
1581 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1583 switch (msr->index) {
1584 case MSR_IA32_ARCH_CAPABILITIES:
1585 msr->data = kvm_get_arch_capabilities();
1587 case MSR_IA32_UCODE_REV:
1588 rdmsrl_safe(msr->index, &msr->data);
1591 return static_call(kvm_x86_get_msr_feature)(msr);
1596 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1598 struct kvm_msr_entry msr;
1602 r = kvm_get_msr_feature(&msr);
1604 if (r == KVM_MSR_RET_INVALID) {
1605 /* Unconditionally clear the output for simplicity */
1607 if (kvm_msr_ignored_check(index, 0, false))
1619 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1621 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1624 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1627 if (efer & (EFER_LME | EFER_LMA) &&
1628 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1631 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1637 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1639 if (efer & efer_reserved_bits)
1642 return __kvm_valid_efer(vcpu, efer);
1644 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1646 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1648 u64 old_efer = vcpu->arch.efer;
1649 u64 efer = msr_info->data;
1652 if (efer & efer_reserved_bits)
1655 if (!msr_info->host_initiated) {
1656 if (!__kvm_valid_efer(vcpu, efer))
1659 if (is_paging(vcpu) &&
1660 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1665 efer |= vcpu->arch.efer & EFER_LMA;
1667 r = static_call(kvm_x86_set_efer)(vcpu, efer);
1673 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
1674 kvm_mmu_reset_context(vcpu);
1679 void kvm_enable_efer_bits(u64 mask)
1681 efer_reserved_bits &= ~mask;
1683 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1685 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1687 struct kvm_x86_msr_filter *msr_filter;
1688 struct msr_bitmap_range *ranges;
1689 struct kvm *kvm = vcpu->kvm;
1694 /* x2APIC MSRs do not support filtering. */
1695 if (index >= 0x800 && index <= 0x8ff)
1698 idx = srcu_read_lock(&kvm->srcu);
1700 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu);
1706 allowed = msr_filter->default_allow;
1707 ranges = msr_filter->ranges;
1709 for (i = 0; i < msr_filter->count; i++) {
1710 u32 start = ranges[i].base;
1711 u32 end = start + ranges[i].nmsrs;
1712 u32 flags = ranges[i].flags;
1713 unsigned long *bitmap = ranges[i].bitmap;
1715 if ((index >= start) && (index < end) && (flags & type)) {
1716 allowed = !!test_bit(index - start, bitmap);
1722 srcu_read_unlock(&kvm->srcu, idx);
1726 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1729 * Write @data into the MSR specified by @index. Select MSR specific fault
1730 * checks are bypassed if @host_initiated is %true.
1731 * Returns 0 on success, non-0 otherwise.
1732 * Assumes vcpu_load() was already called.
1734 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1735 bool host_initiated)
1737 struct msr_data msr;
1739 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1740 return KVM_MSR_RET_FILTERED;
1745 case MSR_KERNEL_GS_BASE:
1748 if (is_noncanonical_address(data, vcpu))
1751 case MSR_IA32_SYSENTER_EIP:
1752 case MSR_IA32_SYSENTER_ESP:
1754 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1755 * non-canonical address is written on Intel but not on
1756 * AMD (which ignores the top 32-bits, because it does
1757 * not implement 64-bit SYSENTER).
1759 * 64-bit code should hence be able to write a non-canonical
1760 * value on AMD. Making the address canonical ensures that
1761 * vmentry does not fail on Intel after writing a non-canonical
1762 * value, and that something deterministic happens if the guest
1763 * invokes 64-bit SYSENTER.
1765 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
1768 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1771 if (!host_initiated &&
1772 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1773 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1777 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
1778 * incomplete and conflicting architectural behavior. Current
1779 * AMD CPUs completely ignore bits 63:32, i.e. they aren't
1780 * reserved and always read as zeros. Enforce Intel's reserved
1781 * bits check if and only if the guest CPU is Intel, and clear
1782 * the bits in all other cases. This ensures cross-vendor
1783 * migration will provide consistent behavior for the guest.
1785 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0)
1794 msr.host_initiated = host_initiated;
1796 return static_call(kvm_x86_set_msr)(vcpu, &msr);
1799 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1800 u32 index, u64 data, bool host_initiated)
1802 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1804 if (ret == KVM_MSR_RET_INVALID)
1805 if (kvm_msr_ignored_check(index, data, true))
1812 * Read the MSR specified by @index into @data. Select MSR specific fault
1813 * checks are bypassed if @host_initiated is %true.
1814 * Returns 0 on success, non-0 otherwise.
1815 * Assumes vcpu_load() was already called.
1817 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1818 bool host_initiated)
1820 struct msr_data msr;
1823 if (!host_initiated && !kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1824 return KVM_MSR_RET_FILTERED;
1828 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1831 if (!host_initiated &&
1832 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1833 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1839 msr.host_initiated = host_initiated;
1841 ret = static_call(kvm_x86_get_msr)(vcpu, &msr);
1847 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1848 u32 index, u64 *data, bool host_initiated)
1850 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1852 if (ret == KVM_MSR_RET_INVALID) {
1853 /* Unconditionally clear *data for simplicity */
1855 if (kvm_msr_ignored_check(index, 0, false))
1862 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1864 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1866 EXPORT_SYMBOL_GPL(kvm_get_msr);
1868 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1870 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1872 EXPORT_SYMBOL_GPL(kvm_set_msr);
1874 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu)
1876 if (!vcpu->run->msr.error) {
1877 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1878 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1882 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu)
1884 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error);
1887 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1889 complete_userspace_rdmsr(vcpu);
1890 return complete_emulated_msr_access(vcpu);
1893 static int complete_fast_msr_access(struct kvm_vcpu *vcpu)
1895 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error);
1898 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu)
1900 complete_userspace_rdmsr(vcpu);
1901 return complete_fast_msr_access(vcpu);
1904 static u64 kvm_msr_reason(int r)
1907 case KVM_MSR_RET_INVALID:
1908 return KVM_MSR_EXIT_REASON_UNKNOWN;
1909 case KVM_MSR_RET_FILTERED:
1910 return KVM_MSR_EXIT_REASON_FILTER;
1912 return KVM_MSR_EXIT_REASON_INVAL;
1916 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1917 u32 exit_reason, u64 data,
1918 int (*completion)(struct kvm_vcpu *vcpu),
1921 u64 msr_reason = kvm_msr_reason(r);
1923 /* Check if the user wanted to know about this MSR fault */
1924 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
1927 vcpu->run->exit_reason = exit_reason;
1928 vcpu->run->msr.error = 0;
1929 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
1930 vcpu->run->msr.reason = msr_reason;
1931 vcpu->run->msr.index = index;
1932 vcpu->run->msr.data = data;
1933 vcpu->arch.complete_userspace_io = completion;
1938 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1940 u32 ecx = kvm_rcx_read(vcpu);
1944 r = kvm_get_msr(vcpu, ecx, &data);
1947 trace_kvm_msr_read(ecx, data);
1949 kvm_rax_write(vcpu, data & -1u);
1950 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1952 /* MSR read failed? See if we should ask user space */
1953 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0,
1954 complete_fast_rdmsr, r))
1956 trace_kvm_msr_read_ex(ecx);
1959 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
1961 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1963 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1965 u32 ecx = kvm_rcx_read(vcpu);
1966 u64 data = kvm_read_edx_eax(vcpu);
1969 r = kvm_set_msr(vcpu, ecx, data);
1972 trace_kvm_msr_write(ecx, data);
1974 /* MSR write failed? See if we should ask user space */
1975 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data,
1976 complete_fast_msr_access, r))
1978 /* Signal all other negative errors to userspace */
1981 trace_kvm_msr_write_ex(ecx, data);
1984 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
1986 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1988 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu)
1990 return kvm_skip_emulated_instruction(vcpu);
1992 EXPORT_SYMBOL_GPL(kvm_emulate_as_nop);
1994 int kvm_emulate_invd(struct kvm_vcpu *vcpu)
1996 /* Treat an INVD instruction as a NOP and just skip it. */
1997 return kvm_emulate_as_nop(vcpu);
1999 EXPORT_SYMBOL_GPL(kvm_emulate_invd);
2001 int kvm_emulate_mwait(struct kvm_vcpu *vcpu)
2003 pr_warn_once("kvm: MWAIT instruction emulated as NOP!\n");
2004 return kvm_emulate_as_nop(vcpu);
2006 EXPORT_SYMBOL_GPL(kvm_emulate_mwait);
2008 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu)
2010 kvm_queue_exception(vcpu, UD_VECTOR);
2013 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op);
2015 int kvm_emulate_monitor(struct kvm_vcpu *vcpu)
2017 pr_warn_once("kvm: MONITOR instruction emulated as NOP!\n");
2018 return kvm_emulate_as_nop(vcpu);
2020 EXPORT_SYMBOL_GPL(kvm_emulate_monitor);
2022 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
2024 xfer_to_guest_mode_prepare();
2025 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
2026 xfer_to_guest_mode_work_pending();
2030 * The fast path for frequent and performance sensitive wrmsr emulation,
2031 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
2032 * the latency of virtual IPI by avoiding the expensive bits of transitioning
2033 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
2034 * other cases which must be called after interrupts are enabled on the host.
2036 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
2038 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
2041 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
2042 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
2043 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
2044 ((u32)(data >> 32) != X2APIC_BROADCAST)) {
2047 kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32));
2048 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
2049 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);
2050 trace_kvm_apic_write(APIC_ICR, (u32)data);
2057 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
2059 if (!kvm_can_use_hv_timer(vcpu))
2062 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2066 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
2068 u32 msr = kvm_rcx_read(vcpu);
2070 fastpath_t ret = EXIT_FASTPATH_NONE;
2073 case APIC_BASE_MSR + (APIC_ICR >> 4):
2074 data = kvm_read_edx_eax(vcpu);
2075 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
2076 kvm_skip_emulated_instruction(vcpu);
2077 ret = EXIT_FASTPATH_EXIT_HANDLED;
2080 case MSR_IA32_TSC_DEADLINE:
2081 data = kvm_read_edx_eax(vcpu);
2082 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
2083 kvm_skip_emulated_instruction(vcpu);
2084 ret = EXIT_FASTPATH_REENTER_GUEST;
2091 if (ret != EXIT_FASTPATH_NONE)
2092 trace_kvm_msr_write(msr, data);
2096 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
2099 * Adapt set_msr() to msr_io()'s calling convention
2101 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2103 return kvm_get_msr_ignored_check(vcpu, index, data, true);
2106 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2108 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
2111 #ifdef CONFIG_X86_64
2112 struct pvclock_clock {
2122 struct pvclock_gtod_data {
2125 struct pvclock_clock clock; /* extract of a clocksource struct */
2126 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
2132 static struct pvclock_gtod_data pvclock_gtod_data;
2134 static void update_pvclock_gtod(struct timekeeper *tk)
2136 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
2138 write_seqcount_begin(&vdata->seq);
2140 /* copy pvclock gtod data */
2141 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
2142 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
2143 vdata->clock.mask = tk->tkr_mono.mask;
2144 vdata->clock.mult = tk->tkr_mono.mult;
2145 vdata->clock.shift = tk->tkr_mono.shift;
2146 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
2147 vdata->clock.offset = tk->tkr_mono.base;
2149 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
2150 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
2151 vdata->raw_clock.mask = tk->tkr_raw.mask;
2152 vdata->raw_clock.mult = tk->tkr_raw.mult;
2153 vdata->raw_clock.shift = tk->tkr_raw.shift;
2154 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
2155 vdata->raw_clock.offset = tk->tkr_raw.base;
2157 vdata->wall_time_sec = tk->xtime_sec;
2159 vdata->offs_boot = tk->offs_boot;
2161 write_seqcount_end(&vdata->seq);
2164 static s64 get_kvmclock_base_ns(void)
2166 /* Count up from boot time, but with the frequency of the raw clock. */
2167 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
2170 static s64 get_kvmclock_base_ns(void)
2172 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
2173 return ktime_get_boottime_ns();
2177 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs)
2181 struct pvclock_wall_clock wc;
2188 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
2193 ++version; /* first time write, random junk */
2197 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
2201 * The guest calculates current wall clock time by adding
2202 * system time (updated by kvm_guest_time_update below) to the
2203 * wall clock specified here. We do the reverse here.
2205 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
2207 wc.nsec = do_div(wall_nsec, 1000000000);
2208 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
2209 wc.version = version;
2211 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
2214 wc_sec_hi = wall_nsec >> 32;
2215 kvm_write_guest(kvm, wall_clock + sec_hi_ofs,
2216 &wc_sec_hi, sizeof(wc_sec_hi));
2220 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
2223 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
2224 bool old_msr, bool host_initiated)
2226 struct kvm_arch *ka = &vcpu->kvm->arch;
2228 if (vcpu->vcpu_id == 0 && !host_initiated) {
2229 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
2230 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2232 ka->boot_vcpu_runs_old_kvmclock = old_msr;
2235 vcpu->arch.time = system_time;
2236 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2238 /* we verify if the enable bit is set... */
2239 vcpu->arch.pv_time_enabled = false;
2240 if (!(system_time & 1))
2243 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
2244 &vcpu->arch.pv_time, system_time & ~1ULL,
2245 sizeof(struct pvclock_vcpu_time_info)))
2246 vcpu->arch.pv_time_enabled = true;
2251 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2253 do_shl32_div32(dividend, divisor);
2257 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2258 s8 *pshift, u32 *pmultiplier)
2266 scaled64 = scaled_hz;
2267 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2272 tps32 = (uint32_t)tps64;
2273 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2274 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2282 *pmultiplier = div_frac(scaled64, tps32);
2285 #ifdef CONFIG_X86_64
2286 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2289 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2290 static unsigned long max_tsc_khz;
2292 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2294 u64 v = (u64)khz * (1000000 + ppm);
2299 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier);
2301 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2305 /* Guest TSC same frequency as host TSC? */
2307 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio);
2311 /* TSC scaling supported? */
2312 if (!kvm_has_tsc_control) {
2313 if (user_tsc_khz > tsc_khz) {
2314 vcpu->arch.tsc_catchup = 1;
2315 vcpu->arch.tsc_always_catchup = 1;
2318 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2323 /* TSC scaling required - calculate ratio */
2324 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
2325 user_tsc_khz, tsc_khz);
2327 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
2328 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2333 kvm_vcpu_write_tsc_multiplier(vcpu, ratio);
2337 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2339 u32 thresh_lo, thresh_hi;
2340 int use_scaling = 0;
2342 /* tsc_khz can be zero if TSC calibration fails */
2343 if (user_tsc_khz == 0) {
2344 /* set tsc_scaling_ratio to a safe value */
2345 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_default_tsc_scaling_ratio);
2349 /* Compute a scale to convert nanoseconds in TSC cycles */
2350 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2351 &vcpu->arch.virtual_tsc_shift,
2352 &vcpu->arch.virtual_tsc_mult);
2353 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2356 * Compute the variation in TSC rate which is acceptable
2357 * within the range of tolerance and decide if the
2358 * rate being applied is within that bounds of the hardware
2359 * rate. If so, no scaling or compensation need be done.
2361 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2362 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2363 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2364 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2367 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2370 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2372 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2373 vcpu->arch.virtual_tsc_mult,
2374 vcpu->arch.virtual_tsc_shift);
2375 tsc += vcpu->arch.this_tsc_write;
2379 static inline int gtod_is_based_on_tsc(int mode)
2381 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2384 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2386 #ifdef CONFIG_X86_64
2388 struct kvm_arch *ka = &vcpu->kvm->arch;
2389 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2391 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2392 atomic_read(&vcpu->kvm->online_vcpus));
2395 * Once the masterclock is enabled, always perform request in
2396 * order to update it.
2398 * In order to enable masterclock, the host clocksource must be TSC
2399 * and the vcpus need to have matched TSCs. When that happens,
2400 * perform request to enable masterclock.
2402 if (ka->use_master_clock ||
2403 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2404 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2406 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2407 atomic_read(&vcpu->kvm->online_vcpus),
2408 ka->use_master_clock, gtod->clock.vclock_mode);
2413 * Multiply tsc by a fixed point number represented by ratio.
2415 * The most significant 64-N bits (mult) of ratio represent the
2416 * integral part of the fixed point number; the remaining N bits
2417 * (frac) represent the fractional part, ie. ratio represents a fixed
2418 * point number (mult + frac * 2^(-N)).
2420 * N equals to kvm_tsc_scaling_ratio_frac_bits.
2422 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2424 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
2427 u64 kvm_scale_tsc(u64 tsc, u64 ratio)
2431 if (ratio != kvm_default_tsc_scaling_ratio)
2432 _tsc = __scale_tsc(ratio, tsc);
2436 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2438 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2442 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio);
2444 return target_tsc - tsc;
2447 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2449 return vcpu->arch.l1_tsc_offset +
2450 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio);
2452 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2454 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier)
2458 if (l2_multiplier == kvm_default_tsc_scaling_ratio)
2459 nested_offset = l1_offset;
2461 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier,
2462 kvm_tsc_scaling_ratio_frac_bits);
2464 nested_offset += l2_offset;
2465 return nested_offset;
2467 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset);
2469 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier)
2471 if (l2_multiplier != kvm_default_tsc_scaling_ratio)
2472 return mul_u64_u64_shr(l1_multiplier, l2_multiplier,
2473 kvm_tsc_scaling_ratio_frac_bits);
2475 return l1_multiplier;
2477 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier);
2479 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset)
2481 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2482 vcpu->arch.l1_tsc_offset,
2485 vcpu->arch.l1_tsc_offset = l1_offset;
2488 * If we are here because L1 chose not to trap WRMSR to TSC then
2489 * according to the spec this should set L1's TSC (as opposed to
2490 * setting L1's offset for L2).
2492 if (is_guest_mode(vcpu))
2493 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2495 static_call(kvm_x86_get_l2_tsc_offset)(vcpu),
2496 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2498 vcpu->arch.tsc_offset = l1_offset;
2500 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset);
2503 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier)
2505 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier;
2507 /* Userspace is changing the multiplier while L2 is active */
2508 if (is_guest_mode(vcpu))
2509 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2511 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2513 vcpu->arch.tsc_scaling_ratio = l1_multiplier;
2515 if (kvm_has_tsc_control)
2516 static_call(kvm_x86_write_tsc_multiplier)(
2517 vcpu, vcpu->arch.tsc_scaling_ratio);
2520 static inline bool kvm_check_tsc_unstable(void)
2522 #ifdef CONFIG_X86_64
2524 * TSC is marked unstable when we're running on Hyper-V,
2525 * 'TSC page' clocksource is good.
2527 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2530 return check_tsc_unstable();
2534 * Infers attempts to synchronize the guest's tsc from host writes. Sets the
2535 * offset for the vcpu and tracks the TSC matching generation that the vcpu
2538 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc,
2539 u64 ns, bool matched)
2541 struct kvm *kvm = vcpu->kvm;
2543 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2546 * We also track th most recent recorded KHZ, write and time to
2547 * allow the matching interval to be extended at each write.
2549 kvm->arch.last_tsc_nsec = ns;
2550 kvm->arch.last_tsc_write = tsc;
2551 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2552 kvm->arch.last_tsc_offset = offset;
2554 vcpu->arch.last_guest_tsc = tsc;
2556 kvm_vcpu_write_tsc_offset(vcpu, offset);
2560 * We split periods of matched TSC writes into generations.
2561 * For each generation, we track the original measured
2562 * nanosecond time, offset, and write, so if TSCs are in
2563 * sync, we can match exact offset, and if not, we can match
2564 * exact software computation in compute_guest_tsc()
2566 * These values are tracked in kvm->arch.cur_xxx variables.
2568 kvm->arch.cur_tsc_generation++;
2569 kvm->arch.cur_tsc_nsec = ns;
2570 kvm->arch.cur_tsc_write = tsc;
2571 kvm->arch.cur_tsc_offset = offset;
2572 kvm->arch.nr_vcpus_matched_tsc = 0;
2573 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) {
2574 kvm->arch.nr_vcpus_matched_tsc++;
2577 /* Keep track of which generation this VCPU has synchronized to */
2578 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2579 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2580 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2582 kvm_track_tsc_matching(vcpu);
2585 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2587 struct kvm *kvm = vcpu->kvm;
2588 u64 offset, ns, elapsed;
2589 unsigned long flags;
2590 bool matched = false;
2591 bool synchronizing = false;
2593 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2594 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2595 ns = get_kvmclock_base_ns();
2596 elapsed = ns - kvm->arch.last_tsc_nsec;
2598 if (vcpu->arch.virtual_tsc_khz) {
2601 * detection of vcpu initialization -- need to sync
2602 * with other vCPUs. This particularly helps to keep
2603 * kvm_clock stable after CPU hotplug
2605 synchronizing = true;
2607 u64 tsc_exp = kvm->arch.last_tsc_write +
2608 nsec_to_cycles(vcpu, elapsed);
2609 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2611 * Special case: TSC write with a small delta (1 second)
2612 * of virtual cycle time against real time is
2613 * interpreted as an attempt to synchronize the CPU.
2615 synchronizing = data < tsc_exp + tsc_hz &&
2616 data + tsc_hz > tsc_exp;
2621 * For a reliable TSC, we can match TSC offsets, and for an unstable
2622 * TSC, we add elapsed time in this computation. We could let the
2623 * compensation code attempt to catch up if we fall behind, but
2624 * it's better to try to match offsets from the beginning.
2626 if (synchronizing &&
2627 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2628 if (!kvm_check_tsc_unstable()) {
2629 offset = kvm->arch.cur_tsc_offset;
2631 u64 delta = nsec_to_cycles(vcpu, elapsed);
2633 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2638 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched);
2639 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2642 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2645 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2646 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2649 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2651 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2652 WARN_ON(adjustment < 0);
2653 adjustment = kvm_scale_tsc((u64) adjustment,
2654 vcpu->arch.l1_tsc_scaling_ratio);
2655 adjust_tsc_offset_guest(vcpu, adjustment);
2658 #ifdef CONFIG_X86_64
2660 static u64 read_tsc(void)
2662 u64 ret = (u64)rdtsc_ordered();
2663 u64 last = pvclock_gtod_data.clock.cycle_last;
2665 if (likely(ret >= last))
2669 * GCC likes to generate cmov here, but this branch is extremely
2670 * predictable (it's just a function of time and the likely is
2671 * very likely) and there's a data dependence, so force GCC
2672 * to generate a branch instead. I don't barrier() because
2673 * we don't actually need a barrier, and if this function
2674 * ever gets inlined it will generate worse code.
2680 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2686 switch (clock->vclock_mode) {
2687 case VDSO_CLOCKMODE_HVCLOCK:
2688 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2690 if (tsc_pg_val != U64_MAX) {
2691 /* TSC page valid */
2692 *mode = VDSO_CLOCKMODE_HVCLOCK;
2693 v = (tsc_pg_val - clock->cycle_last) &
2696 /* TSC page invalid */
2697 *mode = VDSO_CLOCKMODE_NONE;
2700 case VDSO_CLOCKMODE_TSC:
2701 *mode = VDSO_CLOCKMODE_TSC;
2702 *tsc_timestamp = read_tsc();
2703 v = (*tsc_timestamp - clock->cycle_last) &
2707 *mode = VDSO_CLOCKMODE_NONE;
2710 if (*mode == VDSO_CLOCKMODE_NONE)
2711 *tsc_timestamp = v = 0;
2713 return v * clock->mult;
2716 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2718 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2724 seq = read_seqcount_begin(>od->seq);
2725 ns = gtod->raw_clock.base_cycles;
2726 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2727 ns >>= gtod->raw_clock.shift;
2728 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2729 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2735 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2737 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2743 seq = read_seqcount_begin(>od->seq);
2744 ts->tv_sec = gtod->wall_time_sec;
2745 ns = gtod->clock.base_cycles;
2746 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2747 ns >>= gtod->clock.shift;
2748 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2750 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2756 /* returns true if host is using TSC based clocksource */
2757 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2759 /* checked again under seqlock below */
2760 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2763 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2767 /* returns true if host is using TSC based clocksource */
2768 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2771 /* checked again under seqlock below */
2772 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2775 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2781 * Assuming a stable TSC across physical CPUS, and a stable TSC
2782 * across virtual CPUs, the following condition is possible.
2783 * Each numbered line represents an event visible to both
2784 * CPUs at the next numbered event.
2786 * "timespecX" represents host monotonic time. "tscX" represents
2789 * VCPU0 on CPU0 | VCPU1 on CPU1
2791 * 1. read timespec0,tsc0
2792 * 2. | timespec1 = timespec0 + N
2794 * 3. transition to guest | transition to guest
2795 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2796 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2797 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2799 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2802 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2804 * - 0 < N - M => M < N
2806 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2807 * always the case (the difference between two distinct xtime instances
2808 * might be smaller then the difference between corresponding TSC reads,
2809 * when updating guest vcpus pvclock areas).
2811 * To avoid that problem, do not allow visibility of distinct
2812 * system_timestamp/tsc_timestamp values simultaneously: use a master
2813 * copy of host monotonic time values. Update that master copy
2816 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2820 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2822 #ifdef CONFIG_X86_64
2823 struct kvm_arch *ka = &kvm->arch;
2825 bool host_tsc_clocksource, vcpus_matched;
2827 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2828 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2829 atomic_read(&kvm->online_vcpus));
2832 * If the host uses TSC clock, then passthrough TSC as stable
2835 host_tsc_clocksource = kvm_get_time_and_clockread(
2836 &ka->master_kernel_ns,
2837 &ka->master_cycle_now);
2839 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2840 && !ka->backwards_tsc_observed
2841 && !ka->boot_vcpu_runs_old_kvmclock;
2843 if (ka->use_master_clock)
2844 atomic_set(&kvm_guest_has_master_clock, 1);
2846 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2847 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2852 static void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2854 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2857 static void __kvm_start_pvclock_update(struct kvm *kvm)
2859 raw_spin_lock_irq(&kvm->arch.tsc_write_lock);
2860 write_seqcount_begin(&kvm->arch.pvclock_sc);
2863 static void kvm_start_pvclock_update(struct kvm *kvm)
2865 kvm_make_mclock_inprogress_request(kvm);
2867 /* no guest entries from this point */
2868 __kvm_start_pvclock_update(kvm);
2871 static void kvm_end_pvclock_update(struct kvm *kvm)
2873 struct kvm_arch *ka = &kvm->arch;
2874 struct kvm_vcpu *vcpu;
2877 write_seqcount_end(&ka->pvclock_sc);
2878 raw_spin_unlock_irq(&ka->tsc_write_lock);
2879 kvm_for_each_vcpu(i, vcpu, kvm)
2880 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2882 /* guest entries allowed */
2883 kvm_for_each_vcpu(i, vcpu, kvm)
2884 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2887 static void kvm_update_masterclock(struct kvm *kvm)
2889 kvm_hv_invalidate_tsc_page(kvm);
2890 kvm_start_pvclock_update(kvm);
2891 pvclock_update_vm_gtod_copy(kvm);
2892 kvm_end_pvclock_update(kvm);
2895 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */
2896 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
2898 struct kvm_arch *ka = &kvm->arch;
2899 struct pvclock_vcpu_time_info hv_clock;
2901 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2905 if (ka->use_master_clock && __this_cpu_read(cpu_tsc_khz)) {
2906 #ifdef CONFIG_X86_64
2907 struct timespec64 ts;
2909 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) {
2910 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec;
2911 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC;
2914 data->host_tsc = rdtsc();
2916 data->flags |= KVM_CLOCK_TSC_STABLE;
2917 hv_clock.tsc_timestamp = ka->master_cycle_now;
2918 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2919 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2920 &hv_clock.tsc_shift,
2921 &hv_clock.tsc_to_system_mul);
2922 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc);
2924 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset;
2930 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
2932 struct kvm_arch *ka = &kvm->arch;
2936 seq = read_seqcount_begin(&ka->pvclock_sc);
2937 __get_kvmclock(kvm, data);
2938 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
2941 u64 get_kvmclock_ns(struct kvm *kvm)
2943 struct kvm_clock_data data;
2945 get_kvmclock(kvm, &data);
2949 static void kvm_setup_pvclock_page(struct kvm_vcpu *v,
2950 struct gfn_to_hva_cache *cache,
2951 unsigned int offset)
2953 struct kvm_vcpu_arch *vcpu = &v->arch;
2954 struct pvclock_vcpu_time_info guest_hv_clock;
2956 if (unlikely(kvm_read_guest_offset_cached(v->kvm, cache,
2957 &guest_hv_clock, offset, sizeof(guest_hv_clock))))
2960 /* This VCPU is paused, but it's legal for a guest to read another
2961 * VCPU's kvmclock, so we really have to follow the specification where
2962 * it says that version is odd if data is being modified, and even after
2965 * Version field updates must be kept separate. This is because
2966 * kvm_write_guest_cached might use a "rep movs" instruction, and
2967 * writes within a string instruction are weakly ordered. So there
2968 * are three writes overall.
2970 * As a small optimization, only write the version field in the first
2971 * and third write. The vcpu->pv_time cache is still valid, because the
2972 * version field is the first in the struct.
2974 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2976 if (guest_hv_clock.version & 1)
2977 ++guest_hv_clock.version; /* first time write, random junk */
2979 vcpu->hv_clock.version = guest_hv_clock.version + 1;
2980 kvm_write_guest_offset_cached(v->kvm, cache,
2981 &vcpu->hv_clock, offset,
2982 sizeof(vcpu->hv_clock.version));
2986 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2987 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2989 if (vcpu->pvclock_set_guest_stopped_request) {
2990 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2991 vcpu->pvclock_set_guest_stopped_request = false;
2994 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2996 kvm_write_guest_offset_cached(v->kvm, cache,
2997 &vcpu->hv_clock, offset,
2998 sizeof(vcpu->hv_clock));
3002 vcpu->hv_clock.version++;
3003 kvm_write_guest_offset_cached(v->kvm, cache,
3004 &vcpu->hv_clock, offset,
3005 sizeof(vcpu->hv_clock.version));
3008 static int kvm_guest_time_update(struct kvm_vcpu *v)
3010 unsigned long flags, tgt_tsc_khz;
3012 struct kvm_vcpu_arch *vcpu = &v->arch;
3013 struct kvm_arch *ka = &v->kvm->arch;
3015 u64 tsc_timestamp, host_tsc;
3017 bool use_master_clock;
3023 * If the host uses TSC clock, then passthrough TSC as stable
3027 seq = read_seqcount_begin(&ka->pvclock_sc);
3028 use_master_clock = ka->use_master_clock;
3029 if (use_master_clock) {
3030 host_tsc = ka->master_cycle_now;
3031 kernel_ns = ka->master_kernel_ns;
3033 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3035 /* Keep irq disabled to prevent changes to the clock */
3036 local_irq_save(flags);
3037 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
3038 if (unlikely(tgt_tsc_khz == 0)) {
3039 local_irq_restore(flags);
3040 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3043 if (!use_master_clock) {
3045 kernel_ns = get_kvmclock_base_ns();
3048 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
3051 * We may have to catch up the TSC to match elapsed wall clock
3052 * time for two reasons, even if kvmclock is used.
3053 * 1) CPU could have been running below the maximum TSC rate
3054 * 2) Broken TSC compensation resets the base at each VCPU
3055 * entry to avoid unknown leaps of TSC even when running
3056 * again on the same CPU. This may cause apparent elapsed
3057 * time to disappear, and the guest to stand still or run
3060 if (vcpu->tsc_catchup) {
3061 u64 tsc = compute_guest_tsc(v, kernel_ns);
3062 if (tsc > tsc_timestamp) {
3063 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
3064 tsc_timestamp = tsc;
3068 local_irq_restore(flags);
3070 /* With all the info we got, fill in the values */
3072 if (kvm_has_tsc_control)
3073 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz,
3074 v->arch.l1_tsc_scaling_ratio);
3076 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3077 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
3078 &vcpu->hv_clock.tsc_shift,
3079 &vcpu->hv_clock.tsc_to_system_mul);
3080 vcpu->hw_tsc_khz = tgt_tsc_khz;
3083 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
3084 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
3085 vcpu->last_guest_tsc = tsc_timestamp;
3087 /* If the host uses TSC clocksource, then it is stable */
3089 if (use_master_clock)
3090 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
3092 vcpu->hv_clock.flags = pvclock_flags;
3094 if (vcpu->pv_time_enabled)
3095 kvm_setup_pvclock_page(v, &vcpu->pv_time, 0);
3096 if (vcpu->xen.vcpu_info_set)
3097 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_info_cache,
3098 offsetof(struct compat_vcpu_info, time));
3099 if (vcpu->xen.vcpu_time_info_set)
3100 kvm_setup_pvclock_page(v, &vcpu->xen.vcpu_time_info_cache, 0);
3102 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
3107 * kvmclock updates which are isolated to a given vcpu, such as
3108 * vcpu->cpu migration, should not allow system_timestamp from
3109 * the rest of the vcpus to remain static. Otherwise ntp frequency
3110 * correction applies to one vcpu's system_timestamp but not
3113 * So in those cases, request a kvmclock update for all vcpus.
3114 * We need to rate-limit these requests though, as they can
3115 * considerably slow guests that have a large number of vcpus.
3116 * The time for a remote vcpu to update its kvmclock is bound
3117 * by the delay we use to rate-limit the updates.
3120 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
3122 static void kvmclock_update_fn(struct work_struct *work)
3125 struct delayed_work *dwork = to_delayed_work(work);
3126 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3127 kvmclock_update_work);
3128 struct kvm *kvm = container_of(ka, struct kvm, arch);
3129 struct kvm_vcpu *vcpu;
3131 kvm_for_each_vcpu(i, vcpu, kvm) {
3132 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3133 kvm_vcpu_kick(vcpu);
3137 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
3139 struct kvm *kvm = v->kvm;
3141 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3142 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
3143 KVMCLOCK_UPDATE_DELAY);
3146 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
3148 static void kvmclock_sync_fn(struct work_struct *work)
3150 struct delayed_work *dwork = to_delayed_work(work);
3151 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3152 kvmclock_sync_work);
3153 struct kvm *kvm = container_of(ka, struct kvm, arch);
3155 if (!kvmclock_periodic_sync)
3158 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
3159 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
3160 KVMCLOCK_SYNC_PERIOD);
3164 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
3166 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
3168 /* McStatusWrEn enabled? */
3169 if (guest_cpuid_is_amd_or_hygon(vcpu))
3170 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
3175 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3177 u64 mcg_cap = vcpu->arch.mcg_cap;
3178 unsigned bank_num = mcg_cap & 0xff;
3179 u32 msr = msr_info->index;
3180 u64 data = msr_info->data;
3183 case MSR_IA32_MCG_STATUS:
3184 vcpu->arch.mcg_status = data;
3186 case MSR_IA32_MCG_CTL:
3187 if (!(mcg_cap & MCG_CTL_P) &&
3188 (data || !msr_info->host_initiated))
3190 if (data != 0 && data != ~(u64)0)
3192 vcpu->arch.mcg_ctl = data;
3195 if (msr >= MSR_IA32_MC0_CTL &&
3196 msr < MSR_IA32_MCx_CTL(bank_num)) {
3197 u32 offset = array_index_nospec(
3198 msr - MSR_IA32_MC0_CTL,
3199 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3201 /* only 0 or all 1s can be written to IA32_MCi_CTL
3202 * some Linux kernels though clear bit 10 in bank 4 to
3203 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
3204 * this to avoid an uncatched #GP in the guest
3206 if ((offset & 0x3) == 0 &&
3207 data != 0 && (data | (1 << 10)) != ~(u64)0)
3211 if (!msr_info->host_initiated &&
3212 (offset & 0x3) == 1 && data != 0) {
3213 if (!can_set_mci_status(vcpu))
3217 vcpu->arch.mce_banks[offset] = data;
3225 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
3227 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
3229 return (vcpu->arch.apf.msr_en_val & mask) == mask;
3232 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
3234 gpa_t gpa = data & ~0x3f;
3236 /* Bits 4:5 are reserved, Should be zero */
3240 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
3241 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
3244 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
3245 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
3248 if (!lapic_in_kernel(vcpu))
3249 return data ? 1 : 0;
3251 vcpu->arch.apf.msr_en_val = data;
3253 if (!kvm_pv_async_pf_enabled(vcpu)) {
3254 kvm_clear_async_pf_completion_queue(vcpu);
3255 kvm_async_pf_hash_reset(vcpu);
3259 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
3263 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
3264 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
3266 kvm_async_pf_wakeup_all(vcpu);
3271 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
3273 /* Bits 8-63 are reserved */
3277 if (!lapic_in_kernel(vcpu))
3280 vcpu->arch.apf.msr_int_val = data;
3282 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
3287 static void kvmclock_reset(struct kvm_vcpu *vcpu)
3289 vcpu->arch.pv_time_enabled = false;
3290 vcpu->arch.time = 0;
3293 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
3295 ++vcpu->stat.tlb_flush;
3296 static_call(kvm_x86_flush_tlb_all)(vcpu);
3299 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
3301 ++vcpu->stat.tlb_flush;
3305 * A TLB flush on behalf of the guest is equivalent to
3306 * INVPCID(all), toggling CR4.PGE, etc., which requires
3307 * a forced sync of the shadow page tables. Ensure all the
3308 * roots are synced and the guest TLB in hardware is clean.
3310 kvm_mmu_sync_roots(vcpu);
3311 kvm_mmu_sync_prev_roots(vcpu);
3314 static_call(kvm_x86_flush_tlb_guest)(vcpu);
3318 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
3320 ++vcpu->stat.tlb_flush;
3321 static_call(kvm_x86_flush_tlb_current)(vcpu);
3325 * Service "local" TLB flush requests, which are specific to the current MMU
3326 * context. In addition to the generic event handling in vcpu_enter_guest(),
3327 * TLB flushes that are targeted at an MMU context also need to be serviced
3328 * prior before nested VM-Enter/VM-Exit.
3330 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu)
3332 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
3333 kvm_vcpu_flush_tlb_current(vcpu);
3335 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu))
3336 kvm_vcpu_flush_tlb_guest(vcpu);
3338 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests);
3340 static void record_steal_time(struct kvm_vcpu *vcpu)
3342 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
3343 struct kvm_steal_time __user *st;
3344 struct kvm_memslots *slots;
3348 if (kvm_xen_msr_enabled(vcpu->kvm)) {
3349 kvm_xen_runstate_set_running(vcpu);
3353 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3356 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm))
3359 slots = kvm_memslots(vcpu->kvm);
3361 if (unlikely(slots->generation != ghc->generation ||
3362 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) {
3363 gfn_t gfn = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
3365 /* We rely on the fact that it fits in a single page. */
3366 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS);
3368 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gfn, sizeof(*st)) ||
3369 kvm_is_error_hva(ghc->hva) || !ghc->memslot)
3373 st = (struct kvm_steal_time __user *)ghc->hva;
3375 * Doing a TLB flush here, on the guest's behalf, can avoid
3378 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
3379 u8 st_preempted = 0;
3382 if (!user_access_begin(st, sizeof(*st)))
3385 asm volatile("1: xchgb %0, %2\n"
3388 _ASM_EXTABLE_UA(1b, 2b)
3389 : "+q" (st_preempted),
3391 "+m" (st->preempted));
3397 vcpu->arch.st.preempted = 0;
3399 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
3400 st_preempted & KVM_VCPU_FLUSH_TLB);
3401 if (st_preempted & KVM_VCPU_FLUSH_TLB)
3402 kvm_vcpu_flush_tlb_guest(vcpu);
3404 if (!user_access_begin(st, sizeof(*st)))
3407 if (!user_access_begin(st, sizeof(*st)))
3410 unsafe_put_user(0, &st->preempted, out);
3411 vcpu->arch.st.preempted = 0;
3414 unsafe_get_user(version, &st->version, out);
3416 version += 1; /* first time write, random junk */
3419 unsafe_put_user(version, &st->version, out);
3423 unsafe_get_user(steal, &st->steal, out);
3424 steal += current->sched_info.run_delay -
3425 vcpu->arch.st.last_steal;
3426 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3427 unsafe_put_user(steal, &st->steal, out);
3430 unsafe_put_user(version, &st->version, out);
3435 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
3438 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3441 u32 msr = msr_info->index;
3442 u64 data = msr_info->data;
3444 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr)
3445 return kvm_xen_write_hypercall_page(vcpu, data);
3448 case MSR_AMD64_NB_CFG:
3449 case MSR_IA32_UCODE_WRITE:
3450 case MSR_VM_HSAVE_PA:
3451 case MSR_AMD64_PATCH_LOADER:
3452 case MSR_AMD64_BU_CFG2:
3453 case MSR_AMD64_DC_CFG:
3454 case MSR_F15H_EX_CFG:
3457 case MSR_IA32_UCODE_REV:
3458 if (msr_info->host_initiated)
3459 vcpu->arch.microcode_version = data;
3461 case MSR_IA32_ARCH_CAPABILITIES:
3462 if (!msr_info->host_initiated)
3464 vcpu->arch.arch_capabilities = data;
3466 case MSR_IA32_PERF_CAPABILITIES: {
3467 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
3469 if (!msr_info->host_initiated)
3471 if (kvm_get_msr_feature(&msr_ent))
3473 if (data & ~msr_ent.data)
3476 vcpu->arch.perf_capabilities = data;
3481 return set_efer(vcpu, msr_info);
3483 data &= ~(u64)0x40; /* ignore flush filter disable */
3484 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3485 data &= ~(u64)0x8; /* ignore TLB cache disable */
3487 /* Handle McStatusWrEn */
3488 if (data == BIT_ULL(18)) {
3489 vcpu->arch.msr_hwcr = data;
3490 } else if (data != 0) {
3491 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3496 case MSR_FAM10H_MMIO_CONF_BASE:
3498 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3503 case 0x200 ... 0x2ff:
3504 return kvm_mtrr_set_msr(vcpu, msr, data);
3505 case MSR_IA32_APICBASE:
3506 return kvm_set_apic_base(vcpu, msr_info);
3507 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3508 return kvm_x2apic_msr_write(vcpu, msr, data);
3509 case MSR_IA32_TSC_DEADLINE:
3510 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3512 case MSR_IA32_TSC_ADJUST:
3513 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3514 if (!msr_info->host_initiated) {
3515 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3516 adjust_tsc_offset_guest(vcpu, adj);
3517 /* Before back to guest, tsc_timestamp must be adjusted
3518 * as well, otherwise guest's percpu pvclock time could jump.
3520 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3522 vcpu->arch.ia32_tsc_adjust_msr = data;
3525 case MSR_IA32_MISC_ENABLE:
3526 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3527 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3528 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3530 vcpu->arch.ia32_misc_enable_msr = data;
3531 kvm_update_cpuid_runtime(vcpu);
3533 vcpu->arch.ia32_misc_enable_msr = data;
3536 case MSR_IA32_SMBASE:
3537 if (!msr_info->host_initiated)
3539 vcpu->arch.smbase = data;
3541 case MSR_IA32_POWER_CTL:
3542 vcpu->arch.msr_ia32_power_ctl = data;
3545 if (msr_info->host_initiated) {
3546 kvm_synchronize_tsc(vcpu, data);
3548 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3549 adjust_tsc_offset_guest(vcpu, adj);
3550 vcpu->arch.ia32_tsc_adjust_msr += adj;
3554 if (!msr_info->host_initiated &&
3555 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3558 * KVM supports exposing PT to the guest, but does not support
3559 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3560 * XSAVES/XRSTORS to save/restore PT MSRs.
3562 if (data & ~supported_xss)
3564 vcpu->arch.ia32_xss = data;
3565 kvm_update_cpuid_runtime(vcpu);
3568 if (!msr_info->host_initiated)
3570 vcpu->arch.smi_count = data;
3572 case MSR_KVM_WALL_CLOCK_NEW:
3573 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3576 vcpu->kvm->arch.wall_clock = data;
3577 kvm_write_wall_clock(vcpu->kvm, data, 0);
3579 case MSR_KVM_WALL_CLOCK:
3580 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3583 vcpu->kvm->arch.wall_clock = data;
3584 kvm_write_wall_clock(vcpu->kvm, data, 0);
3586 case MSR_KVM_SYSTEM_TIME_NEW:
3587 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3590 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3592 case MSR_KVM_SYSTEM_TIME:
3593 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3596 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3598 case MSR_KVM_ASYNC_PF_EN:
3599 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3602 if (kvm_pv_enable_async_pf(vcpu, data))
3605 case MSR_KVM_ASYNC_PF_INT:
3606 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3609 if (kvm_pv_enable_async_pf_int(vcpu, data))
3612 case MSR_KVM_ASYNC_PF_ACK:
3613 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3616 vcpu->arch.apf.pageready_pending = false;
3617 kvm_check_async_pf_completion(vcpu);
3620 case MSR_KVM_STEAL_TIME:
3621 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3624 if (unlikely(!sched_info_on()))
3627 if (data & KVM_STEAL_RESERVED_MASK)
3630 vcpu->arch.st.msr_val = data;
3632 if (!(data & KVM_MSR_ENABLED))
3635 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3638 case MSR_KVM_PV_EOI_EN:
3639 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3642 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8)))
3646 case MSR_KVM_POLL_CONTROL:
3647 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3650 /* only enable bit supported */
3651 if (data & (-1ULL << 1))
3654 vcpu->arch.msr_kvm_poll_control = data;
3657 case MSR_IA32_MCG_CTL:
3658 case MSR_IA32_MCG_STATUS:
3659 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3660 return set_msr_mce(vcpu, msr_info);
3662 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3663 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3666 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3667 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3668 if (kvm_pmu_is_valid_msr(vcpu, msr))
3669 return kvm_pmu_set_msr(vcpu, msr_info);
3671 if (pr || data != 0)
3672 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3673 "0x%x data 0x%llx\n", msr, data);
3675 case MSR_K7_CLK_CTL:
3677 * Ignore all writes to this no longer documented MSR.
3678 * Writes are only relevant for old K7 processors,
3679 * all pre-dating SVM, but a recommended workaround from
3680 * AMD for these chips. It is possible to specify the
3681 * affected processor models on the command line, hence
3682 * the need to ignore the workaround.
3685 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3686 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3687 case HV_X64_MSR_SYNDBG_OPTIONS:
3688 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3689 case HV_X64_MSR_CRASH_CTL:
3690 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3691 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3692 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3693 case HV_X64_MSR_TSC_EMULATION_STATUS:
3694 return kvm_hv_set_msr_common(vcpu, msr, data,
3695 msr_info->host_initiated);
3696 case MSR_IA32_BBL_CR_CTL3:
3697 /* Drop writes to this legacy MSR -- see rdmsr
3698 * counterpart for further detail.
3700 if (report_ignored_msrs)
3701 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3704 case MSR_AMD64_OSVW_ID_LENGTH:
3705 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3707 vcpu->arch.osvw.length = data;
3709 case MSR_AMD64_OSVW_STATUS:
3710 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3712 vcpu->arch.osvw.status = data;
3714 case MSR_PLATFORM_INFO:
3715 if (!msr_info->host_initiated ||
3716 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3717 cpuid_fault_enabled(vcpu)))
3719 vcpu->arch.msr_platform_info = data;
3721 case MSR_MISC_FEATURES_ENABLES:
3722 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3723 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3724 !supports_cpuid_fault(vcpu)))
3726 vcpu->arch.msr_misc_features_enables = data;
3728 #ifdef CONFIG_X86_64
3730 if (!msr_info->host_initiated &&
3731 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3734 if (data & ~(XFEATURE_MASK_USER_DYNAMIC &
3735 vcpu->arch.guest_supported_xcr0))
3738 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data);
3740 case MSR_IA32_XFD_ERR:
3741 if (!msr_info->host_initiated &&
3742 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3745 if (data & ~(XFEATURE_MASK_USER_DYNAMIC &
3746 vcpu->arch.guest_supported_xcr0))
3749 vcpu->arch.guest_fpu.xfd_err = data;
3753 if (kvm_pmu_is_valid_msr(vcpu, msr))
3754 return kvm_pmu_set_msr(vcpu, msr_info);
3755 return KVM_MSR_RET_INVALID;
3759 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3761 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3764 u64 mcg_cap = vcpu->arch.mcg_cap;
3765 unsigned bank_num = mcg_cap & 0xff;
3768 case MSR_IA32_P5_MC_ADDR:
3769 case MSR_IA32_P5_MC_TYPE:
3772 case MSR_IA32_MCG_CAP:
3773 data = vcpu->arch.mcg_cap;
3775 case MSR_IA32_MCG_CTL:
3776 if (!(mcg_cap & MCG_CTL_P) && !host)
3778 data = vcpu->arch.mcg_ctl;
3780 case MSR_IA32_MCG_STATUS:
3781 data = vcpu->arch.mcg_status;
3784 if (msr >= MSR_IA32_MC0_CTL &&
3785 msr < MSR_IA32_MCx_CTL(bank_num)) {
3786 u32 offset = array_index_nospec(
3787 msr - MSR_IA32_MC0_CTL,
3788 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
3790 data = vcpu->arch.mce_banks[offset];
3799 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3801 switch (msr_info->index) {
3802 case MSR_IA32_PLATFORM_ID:
3803 case MSR_IA32_EBL_CR_POWERON:
3804 case MSR_IA32_LASTBRANCHFROMIP:
3805 case MSR_IA32_LASTBRANCHTOIP:
3806 case MSR_IA32_LASTINTFROMIP:
3807 case MSR_IA32_LASTINTTOIP:
3808 case MSR_AMD64_SYSCFG:
3809 case MSR_K8_TSEG_ADDR:
3810 case MSR_K8_TSEG_MASK:
3811 case MSR_VM_HSAVE_PA:
3812 case MSR_K8_INT_PENDING_MSG:
3813 case MSR_AMD64_NB_CFG:
3814 case MSR_FAM10H_MMIO_CONF_BASE:
3815 case MSR_AMD64_BU_CFG2:
3816 case MSR_IA32_PERF_CTL:
3817 case MSR_AMD64_DC_CFG:
3818 case MSR_F15H_EX_CFG:
3820 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3821 * limit) MSRs. Just return 0, as we do not want to expose the host
3822 * data here. Do not conditionalize this on CPUID, as KVM does not do
3823 * so for existing CPU-specific MSRs.
3825 case MSR_RAPL_POWER_UNIT:
3826 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3827 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3828 case MSR_PKG_ENERGY_STATUS: /* Total package */
3829 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3832 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3833 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3834 return kvm_pmu_get_msr(vcpu, msr_info);
3835 if (!msr_info->host_initiated)
3839 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3840 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3841 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3842 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3843 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3844 return kvm_pmu_get_msr(vcpu, msr_info);
3847 case MSR_IA32_UCODE_REV:
3848 msr_info->data = vcpu->arch.microcode_version;
3850 case MSR_IA32_ARCH_CAPABILITIES:
3851 if (!msr_info->host_initiated &&
3852 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3854 msr_info->data = vcpu->arch.arch_capabilities;
3856 case MSR_IA32_PERF_CAPABILITIES:
3857 if (!msr_info->host_initiated &&
3858 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3860 msr_info->data = vcpu->arch.perf_capabilities;
3862 case MSR_IA32_POWER_CTL:
3863 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3865 case MSR_IA32_TSC: {
3867 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
3868 * even when not intercepted. AMD manual doesn't explicitly
3869 * state this but appears to behave the same.
3871 * On userspace reads and writes, however, we unconditionally
3872 * return L1's TSC value to ensure backwards-compatible
3873 * behavior for migration.
3877 if (msr_info->host_initiated) {
3878 offset = vcpu->arch.l1_tsc_offset;
3879 ratio = vcpu->arch.l1_tsc_scaling_ratio;
3881 offset = vcpu->arch.tsc_offset;
3882 ratio = vcpu->arch.tsc_scaling_ratio;
3885 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset;
3889 case 0x200 ... 0x2ff:
3890 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3891 case 0xcd: /* fsb frequency */
3895 * MSR_EBC_FREQUENCY_ID
3896 * Conservative value valid for even the basic CPU models.
3897 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3898 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3899 * and 266MHz for model 3, or 4. Set Core Clock
3900 * Frequency to System Bus Frequency Ratio to 1 (bits
3901 * 31:24) even though these are only valid for CPU
3902 * models > 2, however guests may end up dividing or
3903 * multiplying by zero otherwise.
3905 case MSR_EBC_FREQUENCY_ID:
3906 msr_info->data = 1 << 24;
3908 case MSR_IA32_APICBASE:
3909 msr_info->data = kvm_get_apic_base(vcpu);
3911 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3912 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
3913 case MSR_IA32_TSC_DEADLINE:
3914 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
3916 case MSR_IA32_TSC_ADJUST:
3917 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
3919 case MSR_IA32_MISC_ENABLE:
3920 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
3922 case MSR_IA32_SMBASE:
3923 if (!msr_info->host_initiated)
3925 msr_info->data = vcpu->arch.smbase;
3928 msr_info->data = vcpu->arch.smi_count;
3930 case MSR_IA32_PERF_STATUS:
3931 /* TSC increment by tick */
3932 msr_info->data = 1000ULL;
3933 /* CPU multiplier */
3934 msr_info->data |= (((uint64_t)4ULL) << 40);
3937 msr_info->data = vcpu->arch.efer;
3939 case MSR_KVM_WALL_CLOCK:
3940 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3943 msr_info->data = vcpu->kvm->arch.wall_clock;
3945 case MSR_KVM_WALL_CLOCK_NEW:
3946 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3949 msr_info->data = vcpu->kvm->arch.wall_clock;
3951 case MSR_KVM_SYSTEM_TIME:
3952 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3955 msr_info->data = vcpu->arch.time;
3957 case MSR_KVM_SYSTEM_TIME_NEW:
3958 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3961 msr_info->data = vcpu->arch.time;
3963 case MSR_KVM_ASYNC_PF_EN:
3964 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3967 msr_info->data = vcpu->arch.apf.msr_en_val;
3969 case MSR_KVM_ASYNC_PF_INT:
3970 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3973 msr_info->data = vcpu->arch.apf.msr_int_val;
3975 case MSR_KVM_ASYNC_PF_ACK:
3976 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3981 case MSR_KVM_STEAL_TIME:
3982 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3985 msr_info->data = vcpu->arch.st.msr_val;
3987 case MSR_KVM_PV_EOI_EN:
3988 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3991 msr_info->data = vcpu->arch.pv_eoi.msr_val;
3993 case MSR_KVM_POLL_CONTROL:
3994 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3997 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3999 case MSR_IA32_P5_MC_ADDR:
4000 case MSR_IA32_P5_MC_TYPE:
4001 case MSR_IA32_MCG_CAP:
4002 case MSR_IA32_MCG_CTL:
4003 case MSR_IA32_MCG_STATUS:
4004 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4005 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
4006 msr_info->host_initiated);
4008 if (!msr_info->host_initiated &&
4009 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
4011 msr_info->data = vcpu->arch.ia32_xss;
4013 case MSR_K7_CLK_CTL:
4015 * Provide expected ramp-up count for K7. All other
4016 * are set to zero, indicating minimum divisors for
4019 * This prevents guest kernels on AMD host with CPU
4020 * type 6, model 8 and higher from exploding due to
4021 * the rdmsr failing.
4023 msr_info->data = 0x20000000;
4025 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4026 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4027 case HV_X64_MSR_SYNDBG_OPTIONS:
4028 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4029 case HV_X64_MSR_CRASH_CTL:
4030 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4031 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4032 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4033 case HV_X64_MSR_TSC_EMULATION_STATUS:
4034 return kvm_hv_get_msr_common(vcpu,
4035 msr_info->index, &msr_info->data,
4036 msr_info->host_initiated);
4037 case MSR_IA32_BBL_CR_CTL3:
4038 /* This legacy MSR exists but isn't fully documented in current
4039 * silicon. It is however accessed by winxp in very narrow
4040 * scenarios where it sets bit #19, itself documented as
4041 * a "reserved" bit. Best effort attempt to source coherent
4042 * read data here should the balance of the register be
4043 * interpreted by the guest:
4045 * L2 cache control register 3: 64GB range, 256KB size,
4046 * enabled, latency 0x1, configured
4048 msr_info->data = 0xbe702111;
4050 case MSR_AMD64_OSVW_ID_LENGTH:
4051 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4053 msr_info->data = vcpu->arch.osvw.length;
4055 case MSR_AMD64_OSVW_STATUS:
4056 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4058 msr_info->data = vcpu->arch.osvw.status;
4060 case MSR_PLATFORM_INFO:
4061 if (!msr_info->host_initiated &&
4062 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
4064 msr_info->data = vcpu->arch.msr_platform_info;
4066 case MSR_MISC_FEATURES_ENABLES:
4067 msr_info->data = vcpu->arch.msr_misc_features_enables;
4070 msr_info->data = vcpu->arch.msr_hwcr;
4072 #ifdef CONFIG_X86_64
4074 if (!msr_info->host_initiated &&
4075 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4078 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd;
4080 case MSR_IA32_XFD_ERR:
4081 if (!msr_info->host_initiated &&
4082 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4085 msr_info->data = vcpu->arch.guest_fpu.xfd_err;
4089 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4090 return kvm_pmu_get_msr(vcpu, msr_info);
4091 return KVM_MSR_RET_INVALID;
4095 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
4098 * Read or write a bunch of msrs. All parameters are kernel addresses.
4100 * @return number of msrs set successfully.
4102 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
4103 struct kvm_msr_entry *entries,
4104 int (*do_msr)(struct kvm_vcpu *vcpu,
4105 unsigned index, u64 *data))
4109 for (i = 0; i < msrs->nmsrs; ++i)
4110 if (do_msr(vcpu, entries[i].index, &entries[i].data))
4117 * Read or write a bunch of msrs. Parameters are user addresses.
4119 * @return number of msrs set successfully.
4121 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
4122 int (*do_msr)(struct kvm_vcpu *vcpu,
4123 unsigned index, u64 *data),
4126 struct kvm_msrs msrs;
4127 struct kvm_msr_entry *entries;
4132 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
4136 if (msrs.nmsrs >= MAX_IO_MSRS)
4139 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
4140 entries = memdup_user(user_msrs->entries, size);
4141 if (IS_ERR(entries)) {
4142 r = PTR_ERR(entries);
4146 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
4151 if (writeback && copy_to_user(user_msrs->entries, entries, size))
4162 static inline bool kvm_can_mwait_in_guest(void)
4164 return boot_cpu_has(X86_FEATURE_MWAIT) &&
4165 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
4166 boot_cpu_has(X86_FEATURE_ARAT);
4169 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
4170 struct kvm_cpuid2 __user *cpuid_arg)
4172 struct kvm_cpuid2 cpuid;
4176 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4179 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4184 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4190 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
4195 case KVM_CAP_IRQCHIP:
4197 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
4198 case KVM_CAP_SET_TSS_ADDR:
4199 case KVM_CAP_EXT_CPUID:
4200 case KVM_CAP_EXT_EMUL_CPUID:
4201 case KVM_CAP_CLOCKSOURCE:
4203 case KVM_CAP_NOP_IO_DELAY:
4204 case KVM_CAP_MP_STATE:
4205 case KVM_CAP_SYNC_MMU:
4206 case KVM_CAP_USER_NMI:
4207 case KVM_CAP_REINJECT_CONTROL:
4208 case KVM_CAP_IRQ_INJECT_STATUS:
4209 case KVM_CAP_IOEVENTFD:
4210 case KVM_CAP_IOEVENTFD_NO_LENGTH:
4212 case KVM_CAP_PIT_STATE2:
4213 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
4214 case KVM_CAP_VCPU_EVENTS:
4215 case KVM_CAP_HYPERV:
4216 case KVM_CAP_HYPERV_VAPIC:
4217 case KVM_CAP_HYPERV_SPIN:
4218 case KVM_CAP_HYPERV_SYNIC:
4219 case KVM_CAP_HYPERV_SYNIC2:
4220 case KVM_CAP_HYPERV_VP_INDEX:
4221 case KVM_CAP_HYPERV_EVENTFD:
4222 case KVM_CAP_HYPERV_TLBFLUSH:
4223 case KVM_CAP_HYPERV_SEND_IPI:
4224 case KVM_CAP_HYPERV_CPUID:
4225 case KVM_CAP_HYPERV_ENFORCE_CPUID:
4226 case KVM_CAP_SYS_HYPERV_CPUID:
4227 case KVM_CAP_PCI_SEGMENT:
4228 case KVM_CAP_DEBUGREGS:
4229 case KVM_CAP_X86_ROBUST_SINGLESTEP:
4231 case KVM_CAP_ASYNC_PF:
4232 case KVM_CAP_ASYNC_PF_INT:
4233 case KVM_CAP_GET_TSC_KHZ:
4234 case KVM_CAP_KVMCLOCK_CTRL:
4235 case KVM_CAP_READONLY_MEM:
4236 case KVM_CAP_HYPERV_TIME:
4237 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
4238 case KVM_CAP_TSC_DEADLINE_TIMER:
4239 case KVM_CAP_DISABLE_QUIRKS:
4240 case KVM_CAP_SET_BOOT_CPU_ID:
4241 case KVM_CAP_SPLIT_IRQCHIP:
4242 case KVM_CAP_IMMEDIATE_EXIT:
4243 case KVM_CAP_PMU_EVENT_FILTER:
4244 case KVM_CAP_GET_MSR_FEATURES:
4245 case KVM_CAP_MSR_PLATFORM_INFO:
4246 case KVM_CAP_EXCEPTION_PAYLOAD:
4247 case KVM_CAP_SET_GUEST_DEBUG:
4248 case KVM_CAP_LAST_CPU:
4249 case KVM_CAP_X86_USER_SPACE_MSR:
4250 case KVM_CAP_X86_MSR_FILTER:
4251 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4252 #ifdef CONFIG_X86_SGX_KVM
4253 case KVM_CAP_SGX_ATTRIBUTE:
4255 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
4256 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
4257 case KVM_CAP_SREGS2:
4258 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
4259 case KVM_CAP_VCPU_ATTRIBUTES:
4260 case KVM_CAP_SYS_ATTRIBUTES:
4264 case KVM_CAP_EXIT_HYPERCALL:
4265 r = KVM_EXIT_HYPERCALL_VALID_MASK;
4267 case KVM_CAP_SET_GUEST_DEBUG2:
4268 return KVM_GUESTDBG_VALID_MASK;
4269 #ifdef CONFIG_KVM_XEN
4270 case KVM_CAP_XEN_HVM:
4271 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR |
4272 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL |
4273 KVM_XEN_HVM_CONFIG_SHARED_INFO |
4274 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL;
4275 if (sched_info_on())
4276 r |= KVM_XEN_HVM_CONFIG_RUNSTATE;
4279 case KVM_CAP_SYNC_REGS:
4280 r = KVM_SYNC_X86_VALID_FIELDS;
4282 case KVM_CAP_ADJUST_CLOCK:
4283 r = KVM_CLOCK_VALID_FLAGS;
4285 case KVM_CAP_X86_DISABLE_EXITS:
4286 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
4287 KVM_X86_DISABLE_EXITS_CSTATE;
4288 if(kvm_can_mwait_in_guest())
4289 r |= KVM_X86_DISABLE_EXITS_MWAIT;
4291 case KVM_CAP_X86_SMM:
4292 /* SMBASE is usually relocated above 1M on modern chipsets,
4293 * and SMM handlers might indeed rely on 4G segment limits,
4294 * so do not report SMM to be available if real mode is
4295 * emulated via vm86 mode. Still, do not go to great lengths
4296 * to avoid userspace's usage of the feature, because it is a
4297 * fringe case that is not enabled except via specific settings
4298 * of the module parameters.
4300 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE);
4302 case KVM_CAP_NR_VCPUS:
4303 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
4305 case KVM_CAP_MAX_VCPUS:
4308 case KVM_CAP_MAX_VCPU_ID:
4309 r = KVM_MAX_VCPU_IDS;
4311 case KVM_CAP_PV_MMU: /* obsolete */
4315 r = KVM_MAX_MCE_BANKS;
4318 r = boot_cpu_has(X86_FEATURE_XSAVE);
4320 case KVM_CAP_TSC_CONTROL:
4321 r = kvm_has_tsc_control;
4323 case KVM_CAP_X2APIC_API:
4324 r = KVM_X2APIC_API_VALID_FLAGS;
4326 case KVM_CAP_NESTED_STATE:
4327 r = kvm_x86_ops.nested_ops->get_state ?
4328 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
4330 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4331 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
4333 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4334 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
4336 case KVM_CAP_SMALLER_MAXPHYADDR:
4337 r = (int) allow_smaller_maxphyaddr;
4339 case KVM_CAP_STEAL_TIME:
4340 r = sched_info_on();
4342 case KVM_CAP_X86_BUS_LOCK_EXIT:
4343 if (kvm_has_bus_lock_exit)
4344 r = KVM_BUS_LOCK_DETECTION_OFF |
4345 KVM_BUS_LOCK_DETECTION_EXIT;
4349 case KVM_CAP_XSAVE2: {
4350 u64 guest_perm = xstate_get_guest_group_perm();
4352 r = xstate_required_size(supported_xcr0 & guest_perm, false);
4353 if (r < sizeof(struct kvm_xsave))
4354 r = sizeof(struct kvm_xsave);
4356 case KVM_CAP_PMU_CAPABILITY:
4357 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0;
4366 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr)
4368 void __user *uaddr = (void __user*)(unsigned long)attr->addr;
4370 if ((u64)(unsigned long)uaddr != attr->addr)
4371 return ERR_PTR_USR(-EFAULT);
4375 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr)
4377 u64 __user *uaddr = kvm_get_attr_addr(attr);
4383 return PTR_ERR(uaddr);
4385 switch (attr->attr) {
4386 case KVM_X86_XCOMP_GUEST_SUPP:
4387 if (put_user(supported_xcr0, uaddr))
4396 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr)
4401 switch (attr->attr) {
4402 case KVM_X86_XCOMP_GUEST_SUPP:
4409 long kvm_arch_dev_ioctl(struct file *filp,
4410 unsigned int ioctl, unsigned long arg)
4412 void __user *argp = (void __user *)arg;
4416 case KVM_GET_MSR_INDEX_LIST: {
4417 struct kvm_msr_list __user *user_msr_list = argp;
4418 struct kvm_msr_list msr_list;
4422 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4425 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
4426 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4429 if (n < msr_list.nmsrs)
4432 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
4433 num_msrs_to_save * sizeof(u32)))
4435 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
4437 num_emulated_msrs * sizeof(u32)))
4442 case KVM_GET_SUPPORTED_CPUID:
4443 case KVM_GET_EMULATED_CPUID: {
4444 struct kvm_cpuid2 __user *cpuid_arg = argp;
4445 struct kvm_cpuid2 cpuid;
4448 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4451 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
4457 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4462 case KVM_X86_GET_MCE_CAP_SUPPORTED:
4464 if (copy_to_user(argp, &kvm_mce_cap_supported,
4465 sizeof(kvm_mce_cap_supported)))
4469 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
4470 struct kvm_msr_list __user *user_msr_list = argp;
4471 struct kvm_msr_list msr_list;
4475 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4478 msr_list.nmsrs = num_msr_based_features;
4479 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4482 if (n < msr_list.nmsrs)
4485 if (copy_to_user(user_msr_list->indices, &msr_based_features,
4486 num_msr_based_features * sizeof(u32)))
4492 r = msr_io(NULL, argp, do_get_msr_feature, 1);
4494 case KVM_GET_SUPPORTED_HV_CPUID:
4495 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
4497 case KVM_GET_DEVICE_ATTR: {
4498 struct kvm_device_attr attr;
4500 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4502 r = kvm_x86_dev_get_attr(&attr);
4505 case KVM_HAS_DEVICE_ATTR: {
4506 struct kvm_device_attr attr;
4508 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4510 r = kvm_x86_dev_has_attr(&attr);
4521 static void wbinvd_ipi(void *garbage)
4526 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
4528 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
4531 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
4533 /* Address WBINVD may be executed by guest */
4534 if (need_emulate_wbinvd(vcpu)) {
4535 if (static_call(kvm_x86_has_wbinvd_exit)())
4536 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4537 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
4538 smp_call_function_single(vcpu->cpu,
4539 wbinvd_ipi, NULL, 1);
4542 static_call(kvm_x86_vcpu_load)(vcpu, cpu);
4544 /* Save host pkru register if supported */
4545 vcpu->arch.host_pkru = read_pkru();
4547 /* Apply any externally detected TSC adjustments (due to suspend) */
4548 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
4549 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
4550 vcpu->arch.tsc_offset_adjustment = 0;
4551 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4554 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
4555 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4556 rdtsc() - vcpu->arch.last_host_tsc;
4558 mark_tsc_unstable("KVM discovered backwards TSC");
4560 if (kvm_check_tsc_unstable()) {
4561 u64 offset = kvm_compute_l1_tsc_offset(vcpu,
4562 vcpu->arch.last_guest_tsc);
4563 kvm_vcpu_write_tsc_offset(vcpu, offset);
4564 vcpu->arch.tsc_catchup = 1;
4567 if (kvm_lapic_hv_timer_in_use(vcpu))
4568 kvm_lapic_restart_hv_timer(vcpu);
4571 * On a host with synchronized TSC, there is no need to update
4572 * kvmclock on vcpu->cpu migration
4574 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
4575 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
4576 if (vcpu->cpu != cpu)
4577 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
4581 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4584 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4586 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
4587 struct kvm_steal_time __user *st;
4588 struct kvm_memslots *slots;
4589 static const u8 preempted = KVM_VCPU_PREEMPTED;
4591 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4594 if (vcpu->arch.st.preempted)
4597 /* This happens on process exit */
4598 if (unlikely(current->mm != vcpu->kvm->mm))
4601 slots = kvm_memslots(vcpu->kvm);
4603 if (unlikely(slots->generation != ghc->generation ||
4604 kvm_is_error_hva(ghc->hva) || !ghc->memslot))
4607 st = (struct kvm_steal_time __user *)ghc->hva;
4608 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted));
4610 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted)))
4611 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4613 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
4616 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4620 if (vcpu->preempted && !vcpu->arch.guest_state_protected)
4621 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu);
4624 * Take the srcu lock as memslots will be accessed to check the gfn
4625 * cache generation against the memslots generation.
4627 idx = srcu_read_lock(&vcpu->kvm->srcu);
4628 if (kvm_xen_msr_enabled(vcpu->kvm))
4629 kvm_xen_runstate_set_preempted(vcpu);
4631 kvm_steal_time_set_preempted(vcpu);
4632 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4634 static_call(kvm_x86_vcpu_put)(vcpu);
4635 vcpu->arch.last_host_tsc = rdtsc();
4638 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4639 struct kvm_lapic_state *s)
4641 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
4643 return kvm_apic_get_state(vcpu, s);
4646 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4647 struct kvm_lapic_state *s)
4651 r = kvm_apic_set_state(vcpu, s);
4654 update_cr8_intercept(vcpu);
4659 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4662 * We can accept userspace's request for interrupt injection
4663 * as long as we have a place to store the interrupt number.
4664 * The actual injection will happen when the CPU is able to
4665 * deliver the interrupt.
4667 if (kvm_cpu_has_extint(vcpu))
4670 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
4671 return (!lapic_in_kernel(vcpu) ||
4672 kvm_apic_accept_pic_intr(vcpu));
4675 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4678 * Do not cause an interrupt window exit if an exception
4679 * is pending or an event needs reinjection; userspace
4680 * might want to inject the interrupt manually using KVM_SET_REGS
4681 * or KVM_SET_SREGS. For that to work, we must be at an
4682 * instruction boundary and with no events half-injected.
4684 return (kvm_arch_interrupt_allowed(vcpu) &&
4685 kvm_cpu_accept_dm_intr(vcpu) &&
4686 !kvm_event_needs_reinjection(vcpu) &&
4687 !vcpu->arch.exception.pending);
4690 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4691 struct kvm_interrupt *irq)
4693 if (irq->irq >= KVM_NR_INTERRUPTS)
4696 if (!irqchip_in_kernel(vcpu->kvm)) {
4697 kvm_queue_interrupt(vcpu, irq->irq, false);
4698 kvm_make_request(KVM_REQ_EVENT, vcpu);
4703 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4704 * fail for in-kernel 8259.
4706 if (pic_in_kernel(vcpu->kvm))
4709 if (vcpu->arch.pending_external_vector != -1)
4712 vcpu->arch.pending_external_vector = irq->irq;
4713 kvm_make_request(KVM_REQ_EVENT, vcpu);
4717 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4719 kvm_inject_nmi(vcpu);
4724 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
4726 kvm_make_request(KVM_REQ_SMI, vcpu);
4731 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4732 struct kvm_tpr_access_ctl *tac)
4736 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4740 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4744 unsigned bank_num = mcg_cap & 0xff, bank;
4747 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4749 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
4752 vcpu->arch.mcg_cap = mcg_cap;
4753 /* Init IA32_MCG_CTL to all 1s */
4754 if (mcg_cap & MCG_CTL_P)
4755 vcpu->arch.mcg_ctl = ~(u64)0;
4756 /* Init IA32_MCi_CTL to all 1s */
4757 for (bank = 0; bank < bank_num; bank++)
4758 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4760 static_call(kvm_x86_setup_mce)(vcpu);
4765 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4766 struct kvm_x86_mce *mce)
4768 u64 mcg_cap = vcpu->arch.mcg_cap;
4769 unsigned bank_num = mcg_cap & 0xff;
4770 u64 *banks = vcpu->arch.mce_banks;
4772 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
4775 * if IA32_MCG_CTL is not all 1s, the uncorrected error
4776 * reporting is disabled
4778 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
4779 vcpu->arch.mcg_ctl != ~(u64)0)
4781 banks += 4 * mce->bank;
4783 * if IA32_MCi_CTL is not all 1s, the uncorrected error
4784 * reporting is disabled for the bank
4786 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
4788 if (mce->status & MCI_STATUS_UC) {
4789 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
4790 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
4791 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4794 if (banks[1] & MCI_STATUS_VAL)
4795 mce->status |= MCI_STATUS_OVER;
4796 banks[2] = mce->addr;
4797 banks[3] = mce->misc;
4798 vcpu->arch.mcg_status = mce->mcg_status;
4799 banks[1] = mce->status;
4800 kvm_queue_exception(vcpu, MC_VECTOR);
4801 } else if (!(banks[1] & MCI_STATUS_VAL)
4802 || !(banks[1] & MCI_STATUS_UC)) {
4803 if (banks[1] & MCI_STATUS_VAL)
4804 mce->status |= MCI_STATUS_OVER;
4805 banks[2] = mce->addr;
4806 banks[3] = mce->misc;
4807 banks[1] = mce->status;
4809 banks[1] |= MCI_STATUS_OVER;
4813 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
4814 struct kvm_vcpu_events *events)
4818 if (kvm_check_request(KVM_REQ_SMI, vcpu))
4822 * In guest mode, payload delivery should be deferred,
4823 * so that the L1 hypervisor can intercept #PF before
4824 * CR2 is modified (or intercept #DB before DR6 is
4825 * modified under nVMX). Unless the per-VM capability,
4826 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
4827 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
4828 * opportunistically defer the exception payload, deliver it if the
4829 * capability hasn't been requested before processing a
4830 * KVM_GET_VCPU_EVENTS.
4832 if (!vcpu->kvm->arch.exception_payload_enabled &&
4833 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
4834 kvm_deliver_exception_payload(vcpu);
4837 * The API doesn't provide the instruction length for software
4838 * exceptions, so don't report them. As long as the guest RIP
4839 * isn't advanced, we should expect to encounter the exception
4842 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
4843 events->exception.injected = 0;
4844 events->exception.pending = 0;
4846 events->exception.injected = vcpu->arch.exception.injected;
4847 events->exception.pending = vcpu->arch.exception.pending;
4849 * For ABI compatibility, deliberately conflate
4850 * pending and injected exceptions when
4851 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
4853 if (!vcpu->kvm->arch.exception_payload_enabled)
4854 events->exception.injected |=
4855 vcpu->arch.exception.pending;
4857 events->exception.nr = vcpu->arch.exception.nr;
4858 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
4859 events->exception.error_code = vcpu->arch.exception.error_code;
4860 events->exception_has_payload = vcpu->arch.exception.has_payload;
4861 events->exception_payload = vcpu->arch.exception.payload;
4863 events->interrupt.injected =
4864 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
4865 events->interrupt.nr = vcpu->arch.interrupt.nr;
4866 events->interrupt.soft = 0;
4867 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
4869 events->nmi.injected = vcpu->arch.nmi_injected;
4870 events->nmi.pending = vcpu->arch.nmi_pending != 0;
4871 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu);
4872 events->nmi.pad = 0;
4874 events->sipi_vector = 0; /* never valid when reporting to user space */
4876 events->smi.smm = is_smm(vcpu);
4877 events->smi.pending = vcpu->arch.smi_pending;
4878 events->smi.smm_inside_nmi =
4879 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
4880 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
4882 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
4883 | KVM_VCPUEVENT_VALID_SHADOW
4884 | KVM_VCPUEVENT_VALID_SMM);
4885 if (vcpu->kvm->arch.exception_payload_enabled)
4886 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4888 memset(&events->reserved, 0, sizeof(events->reserved));
4891 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm);
4893 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
4894 struct kvm_vcpu_events *events)
4896 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
4897 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
4898 | KVM_VCPUEVENT_VALID_SHADOW
4899 | KVM_VCPUEVENT_VALID_SMM
4900 | KVM_VCPUEVENT_VALID_PAYLOAD))
4903 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4904 if (!vcpu->kvm->arch.exception_payload_enabled)
4906 if (events->exception.pending)
4907 events->exception.injected = 0;
4909 events->exception_has_payload = 0;
4911 events->exception.pending = 0;
4912 events->exception_has_payload = 0;
4915 if ((events->exception.injected || events->exception.pending) &&
4916 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
4919 /* INITs are latched while in SMM */
4920 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
4921 (events->smi.smm || events->smi.pending) &&
4922 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
4926 vcpu->arch.exception.injected = events->exception.injected;
4927 vcpu->arch.exception.pending = events->exception.pending;
4928 vcpu->arch.exception.nr = events->exception.nr;
4929 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
4930 vcpu->arch.exception.error_code = events->exception.error_code;
4931 vcpu->arch.exception.has_payload = events->exception_has_payload;
4932 vcpu->arch.exception.payload = events->exception_payload;
4934 vcpu->arch.interrupt.injected = events->interrupt.injected;
4935 vcpu->arch.interrupt.nr = events->interrupt.nr;
4936 vcpu->arch.interrupt.soft = events->interrupt.soft;
4937 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
4938 static_call(kvm_x86_set_interrupt_shadow)(vcpu,
4939 events->interrupt.shadow);
4941 vcpu->arch.nmi_injected = events->nmi.injected;
4942 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
4943 vcpu->arch.nmi_pending = events->nmi.pending;
4944 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked);
4946 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
4947 lapic_in_kernel(vcpu))
4948 vcpu->arch.apic->sipi_vector = events->sipi_vector;
4950 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
4951 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
4952 kvm_x86_ops.nested_ops->leave_nested(vcpu);
4953 kvm_smm_changed(vcpu, events->smi.smm);
4956 vcpu->arch.smi_pending = events->smi.pending;
4958 if (events->smi.smm) {
4959 if (events->smi.smm_inside_nmi)
4960 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
4962 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
4965 if (lapic_in_kernel(vcpu)) {
4966 if (events->smi.latched_init)
4967 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4969 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
4973 kvm_make_request(KVM_REQ_EVENT, vcpu);
4978 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
4979 struct kvm_debugregs *dbgregs)
4983 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
4984 kvm_get_dr(vcpu, 6, &val);
4986 dbgregs->dr7 = vcpu->arch.dr7;
4988 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
4991 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
4992 struct kvm_debugregs *dbgregs)
4997 if (!kvm_dr6_valid(dbgregs->dr6))
4999 if (!kvm_dr7_valid(dbgregs->dr7))
5002 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
5003 kvm_update_dr0123(vcpu);
5004 vcpu->arch.dr6 = dbgregs->dr6;
5005 vcpu->arch.dr7 = dbgregs->dr7;
5006 kvm_update_dr7(vcpu);
5011 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
5012 struct kvm_xsave *guest_xsave)
5014 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5017 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5018 guest_xsave->region,
5019 sizeof(guest_xsave->region),
5023 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu,
5024 u8 *state, unsigned int size)
5026 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5029 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5030 state, size, vcpu->arch.pkru);
5033 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
5034 struct kvm_xsave *guest_xsave)
5036 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5039 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu,
5040 guest_xsave->region,
5041 supported_xcr0, &vcpu->arch.pkru);
5044 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
5045 struct kvm_xcrs *guest_xcrs)
5047 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
5048 guest_xcrs->nr_xcrs = 0;
5052 guest_xcrs->nr_xcrs = 1;
5053 guest_xcrs->flags = 0;
5054 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
5055 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
5058 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
5059 struct kvm_xcrs *guest_xcrs)
5063 if (!boot_cpu_has(X86_FEATURE_XSAVE))
5066 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
5069 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
5070 /* Only support XCR0 currently */
5071 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
5072 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
5073 guest_xcrs->xcrs[i].value);
5082 * kvm_set_guest_paused() indicates to the guest kernel that it has been
5083 * stopped by the hypervisor. This function will be called from the host only.
5084 * EINVAL is returned when the host attempts to set the flag for a guest that
5085 * does not support pv clocks.
5087 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
5089 if (!vcpu->arch.pv_time_enabled)
5091 vcpu->arch.pvclock_set_guest_stopped_request = true;
5092 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5096 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu,
5097 struct kvm_device_attr *attr)
5101 switch (attr->attr) {
5102 case KVM_VCPU_TSC_OFFSET:
5112 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu,
5113 struct kvm_device_attr *attr)
5115 u64 __user *uaddr = kvm_get_attr_addr(attr);
5119 return PTR_ERR(uaddr);
5121 switch (attr->attr) {
5122 case KVM_VCPU_TSC_OFFSET:
5124 if (put_user(vcpu->arch.l1_tsc_offset, uaddr))
5135 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu,
5136 struct kvm_device_attr *attr)
5138 u64 __user *uaddr = kvm_get_attr_addr(attr);
5139 struct kvm *kvm = vcpu->kvm;
5143 return PTR_ERR(uaddr);
5145 switch (attr->attr) {
5146 case KVM_VCPU_TSC_OFFSET: {
5147 u64 offset, tsc, ns;
5148 unsigned long flags;
5152 if (get_user(offset, uaddr))
5155 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
5157 matched = (vcpu->arch.virtual_tsc_khz &&
5158 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz &&
5159 kvm->arch.last_tsc_offset == offset);
5161 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset;
5162 ns = get_kvmclock_base_ns();
5164 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched);
5165 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
5177 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu,
5181 struct kvm_device_attr attr;
5184 if (copy_from_user(&attr, argp, sizeof(attr)))
5187 if (attr.group != KVM_VCPU_TSC_CTRL)
5191 case KVM_HAS_DEVICE_ATTR:
5192 r = kvm_arch_tsc_has_attr(vcpu, &attr);
5194 case KVM_GET_DEVICE_ATTR:
5195 r = kvm_arch_tsc_get_attr(vcpu, &attr);
5197 case KVM_SET_DEVICE_ATTR:
5198 r = kvm_arch_tsc_set_attr(vcpu, &attr);
5205 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
5206 struct kvm_enable_cap *cap)
5209 uint16_t vmcs_version;
5210 void __user *user_ptr;
5216 case KVM_CAP_HYPERV_SYNIC2:
5221 case KVM_CAP_HYPERV_SYNIC:
5222 if (!irqchip_in_kernel(vcpu->kvm))
5224 return kvm_hv_activate_synic(vcpu, cap->cap ==
5225 KVM_CAP_HYPERV_SYNIC2);
5226 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5227 if (!kvm_x86_ops.nested_ops->enable_evmcs)
5229 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
5231 user_ptr = (void __user *)(uintptr_t)cap->args[0];
5232 if (copy_to_user(user_ptr, &vmcs_version,
5233 sizeof(vmcs_version)))
5237 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5238 if (!kvm_x86_ops.enable_direct_tlbflush)
5241 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu);
5243 case KVM_CAP_HYPERV_ENFORCE_CPUID:
5244 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]);
5246 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
5247 vcpu->arch.pv_cpuid.enforce = cap->args[0];
5248 if (vcpu->arch.pv_cpuid.enforce)
5249 kvm_update_pv_runtime(vcpu);
5257 long kvm_arch_vcpu_ioctl(struct file *filp,
5258 unsigned int ioctl, unsigned long arg)
5260 struct kvm_vcpu *vcpu = filp->private_data;
5261 void __user *argp = (void __user *)arg;
5264 struct kvm_sregs2 *sregs2;
5265 struct kvm_lapic_state *lapic;
5266 struct kvm_xsave *xsave;
5267 struct kvm_xcrs *xcrs;
5275 case KVM_GET_LAPIC: {
5277 if (!lapic_in_kernel(vcpu))
5279 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
5280 GFP_KERNEL_ACCOUNT);
5285 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
5289 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
5294 case KVM_SET_LAPIC: {
5296 if (!lapic_in_kernel(vcpu))
5298 u.lapic = memdup_user(argp, sizeof(*u.lapic));
5299 if (IS_ERR(u.lapic)) {
5300 r = PTR_ERR(u.lapic);
5304 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
5307 case KVM_INTERRUPT: {
5308 struct kvm_interrupt irq;
5311 if (copy_from_user(&irq, argp, sizeof(irq)))
5313 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
5317 r = kvm_vcpu_ioctl_nmi(vcpu);
5321 r = kvm_vcpu_ioctl_smi(vcpu);
5324 case KVM_SET_CPUID: {
5325 struct kvm_cpuid __user *cpuid_arg = argp;
5326 struct kvm_cpuid cpuid;
5329 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5331 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
5334 case KVM_SET_CPUID2: {
5335 struct kvm_cpuid2 __user *cpuid_arg = argp;
5336 struct kvm_cpuid2 cpuid;
5339 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5341 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
5342 cpuid_arg->entries);
5345 case KVM_GET_CPUID2: {
5346 struct kvm_cpuid2 __user *cpuid_arg = argp;
5347 struct kvm_cpuid2 cpuid;
5350 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5352 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
5353 cpuid_arg->entries);
5357 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
5362 case KVM_GET_MSRS: {
5363 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5364 r = msr_io(vcpu, argp, do_get_msr, 1);
5365 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5368 case KVM_SET_MSRS: {
5369 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5370 r = msr_io(vcpu, argp, do_set_msr, 0);
5371 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5374 case KVM_TPR_ACCESS_REPORTING: {
5375 struct kvm_tpr_access_ctl tac;
5378 if (copy_from_user(&tac, argp, sizeof(tac)))
5380 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
5384 if (copy_to_user(argp, &tac, sizeof(tac)))
5389 case KVM_SET_VAPIC_ADDR: {
5390 struct kvm_vapic_addr va;
5394 if (!lapic_in_kernel(vcpu))
5397 if (copy_from_user(&va, argp, sizeof(va)))
5399 idx = srcu_read_lock(&vcpu->kvm->srcu);
5400 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
5401 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5404 case KVM_X86_SETUP_MCE: {
5408 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
5410 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
5413 case KVM_X86_SET_MCE: {
5414 struct kvm_x86_mce mce;
5417 if (copy_from_user(&mce, argp, sizeof(mce)))
5419 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
5422 case KVM_GET_VCPU_EVENTS: {
5423 struct kvm_vcpu_events events;
5425 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
5428 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
5433 case KVM_SET_VCPU_EVENTS: {
5434 struct kvm_vcpu_events events;
5437 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
5440 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
5443 case KVM_GET_DEBUGREGS: {
5444 struct kvm_debugregs dbgregs;
5446 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
5449 if (copy_to_user(argp, &dbgregs,
5450 sizeof(struct kvm_debugregs)))
5455 case KVM_SET_DEBUGREGS: {
5456 struct kvm_debugregs dbgregs;
5459 if (copy_from_user(&dbgregs, argp,
5460 sizeof(struct kvm_debugregs)))
5463 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
5466 case KVM_GET_XSAVE: {
5468 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave))
5471 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
5476 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
5479 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
5484 case KVM_SET_XSAVE: {
5485 int size = vcpu->arch.guest_fpu.uabi_size;
5487 u.xsave = memdup_user(argp, size);
5488 if (IS_ERR(u.xsave)) {
5489 r = PTR_ERR(u.xsave);
5493 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
5497 case KVM_GET_XSAVE2: {
5498 int size = vcpu->arch.guest_fpu.uabi_size;
5500 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT);
5505 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size);
5508 if (copy_to_user(argp, u.xsave, size))
5515 case KVM_GET_XCRS: {
5516 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
5521 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
5524 if (copy_to_user(argp, u.xcrs,
5525 sizeof(struct kvm_xcrs)))
5530 case KVM_SET_XCRS: {
5531 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
5532 if (IS_ERR(u.xcrs)) {
5533 r = PTR_ERR(u.xcrs);
5537 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
5540 case KVM_SET_TSC_KHZ: {
5544 user_tsc_khz = (u32)arg;
5546 if (kvm_has_tsc_control &&
5547 user_tsc_khz >= kvm_max_guest_tsc_khz)
5550 if (user_tsc_khz == 0)
5551 user_tsc_khz = tsc_khz;
5553 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
5558 case KVM_GET_TSC_KHZ: {
5559 r = vcpu->arch.virtual_tsc_khz;
5562 case KVM_KVMCLOCK_CTRL: {
5563 r = kvm_set_guest_paused(vcpu);
5566 case KVM_ENABLE_CAP: {
5567 struct kvm_enable_cap cap;
5570 if (copy_from_user(&cap, argp, sizeof(cap)))
5572 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
5575 case KVM_GET_NESTED_STATE: {
5576 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5580 if (!kvm_x86_ops.nested_ops->get_state)
5583 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
5585 if (get_user(user_data_size, &user_kvm_nested_state->size))
5588 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
5593 if (r > user_data_size) {
5594 if (put_user(r, &user_kvm_nested_state->size))
5604 case KVM_SET_NESTED_STATE: {
5605 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5606 struct kvm_nested_state kvm_state;
5610 if (!kvm_x86_ops.nested_ops->set_state)
5614 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
5618 if (kvm_state.size < sizeof(kvm_state))
5621 if (kvm_state.flags &
5622 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
5623 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
5624 | KVM_STATE_NESTED_GIF_SET))
5627 /* nested_run_pending implies guest_mode. */
5628 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
5629 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
5632 idx = srcu_read_lock(&vcpu->kvm->srcu);
5633 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
5634 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5637 case KVM_GET_SUPPORTED_HV_CPUID:
5638 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5640 #ifdef CONFIG_KVM_XEN
5641 case KVM_XEN_VCPU_GET_ATTR: {
5642 struct kvm_xen_vcpu_attr xva;
5645 if (copy_from_user(&xva, argp, sizeof(xva)))
5647 r = kvm_xen_vcpu_get_attr(vcpu, &xva);
5648 if (!r && copy_to_user(argp, &xva, sizeof(xva)))
5652 case KVM_XEN_VCPU_SET_ATTR: {
5653 struct kvm_xen_vcpu_attr xva;
5656 if (copy_from_user(&xva, argp, sizeof(xva)))
5658 r = kvm_xen_vcpu_set_attr(vcpu, &xva);
5662 case KVM_GET_SREGS2: {
5663 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL);
5667 __get_sregs2(vcpu, u.sregs2);
5669 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2)))
5674 case KVM_SET_SREGS2: {
5675 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2));
5676 if (IS_ERR(u.sregs2)) {
5677 r = PTR_ERR(u.sregs2);
5681 r = __set_sregs2(vcpu, u.sregs2);
5684 case KVM_HAS_DEVICE_ATTR:
5685 case KVM_GET_DEVICE_ATTR:
5686 case KVM_SET_DEVICE_ATTR:
5687 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp);
5699 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5701 return VM_FAULT_SIGBUS;
5704 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
5708 if (addr > (unsigned int)(-3 * PAGE_SIZE))
5710 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr);
5714 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
5717 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr);
5720 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
5721 unsigned long kvm_nr_mmu_pages)
5723 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
5726 mutex_lock(&kvm->slots_lock);
5728 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
5729 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
5731 mutex_unlock(&kvm->slots_lock);
5735 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
5737 return kvm->arch.n_max_mmu_pages;
5740 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5742 struct kvm_pic *pic = kvm->arch.vpic;
5746 switch (chip->chip_id) {
5747 case KVM_IRQCHIP_PIC_MASTER:
5748 memcpy(&chip->chip.pic, &pic->pics[0],
5749 sizeof(struct kvm_pic_state));
5751 case KVM_IRQCHIP_PIC_SLAVE:
5752 memcpy(&chip->chip.pic, &pic->pics[1],
5753 sizeof(struct kvm_pic_state));
5755 case KVM_IRQCHIP_IOAPIC:
5756 kvm_get_ioapic(kvm, &chip->chip.ioapic);
5765 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5767 struct kvm_pic *pic = kvm->arch.vpic;
5771 switch (chip->chip_id) {
5772 case KVM_IRQCHIP_PIC_MASTER:
5773 spin_lock(&pic->lock);
5774 memcpy(&pic->pics[0], &chip->chip.pic,
5775 sizeof(struct kvm_pic_state));
5776 spin_unlock(&pic->lock);
5778 case KVM_IRQCHIP_PIC_SLAVE:
5779 spin_lock(&pic->lock);
5780 memcpy(&pic->pics[1], &chip->chip.pic,
5781 sizeof(struct kvm_pic_state));
5782 spin_unlock(&pic->lock);
5784 case KVM_IRQCHIP_IOAPIC:
5785 kvm_set_ioapic(kvm, &chip->chip.ioapic);
5791 kvm_pic_update_irq(pic);
5795 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5797 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
5799 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
5801 mutex_lock(&kps->lock);
5802 memcpy(ps, &kps->channels, sizeof(*ps));
5803 mutex_unlock(&kps->lock);
5807 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5810 struct kvm_pit *pit = kvm->arch.vpit;
5812 mutex_lock(&pit->pit_state.lock);
5813 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
5814 for (i = 0; i < 3; i++)
5815 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
5816 mutex_unlock(&pit->pit_state.lock);
5820 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5822 mutex_lock(&kvm->arch.vpit->pit_state.lock);
5823 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
5824 sizeof(ps->channels));
5825 ps->flags = kvm->arch.vpit->pit_state.flags;
5826 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
5827 memset(&ps->reserved, 0, sizeof(ps->reserved));
5831 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
5835 u32 prev_legacy, cur_legacy;
5836 struct kvm_pit *pit = kvm->arch.vpit;
5838 mutex_lock(&pit->pit_state.lock);
5839 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
5840 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
5841 if (!prev_legacy && cur_legacy)
5843 memcpy(&pit->pit_state.channels, &ps->channels,
5844 sizeof(pit->pit_state.channels));
5845 pit->pit_state.flags = ps->flags;
5846 for (i = 0; i < 3; i++)
5847 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
5849 mutex_unlock(&pit->pit_state.lock);
5853 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
5854 struct kvm_reinject_control *control)
5856 struct kvm_pit *pit = kvm->arch.vpit;
5858 /* pit->pit_state.lock was overloaded to prevent userspace from getting
5859 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
5860 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
5862 mutex_lock(&pit->pit_state.lock);
5863 kvm_pit_set_reinject(pit, control->pit_reinject);
5864 mutex_unlock(&pit->pit_state.lock);
5869 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
5873 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called
5874 * before reporting dirty_bitmap to userspace. KVM flushes the buffers
5875 * on all VM-Exits, thus we only need to kick running vCPUs to force a
5878 struct kvm_vcpu *vcpu;
5881 kvm_for_each_vcpu(i, vcpu, kvm)
5882 kvm_vcpu_kick(vcpu);
5885 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
5888 if (!irqchip_in_kernel(kvm))
5891 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
5892 irq_event->irq, irq_event->level,
5897 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
5898 struct kvm_enable_cap *cap)
5906 case KVM_CAP_DISABLE_QUIRKS:
5907 kvm->arch.disabled_quirks = cap->args[0];
5910 case KVM_CAP_SPLIT_IRQCHIP: {
5911 mutex_lock(&kvm->lock);
5913 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
5914 goto split_irqchip_unlock;
5916 if (irqchip_in_kernel(kvm))
5917 goto split_irqchip_unlock;
5918 if (kvm->created_vcpus)
5919 goto split_irqchip_unlock;
5920 r = kvm_setup_empty_irq_routing(kvm);
5922 goto split_irqchip_unlock;
5923 /* Pairs with irqchip_in_kernel. */
5925 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
5926 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
5927 kvm_request_apicv_update(kvm, true, APICV_INHIBIT_REASON_ABSENT);
5929 split_irqchip_unlock:
5930 mutex_unlock(&kvm->lock);
5933 case KVM_CAP_X2APIC_API:
5935 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
5938 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
5939 kvm->arch.x2apic_format = true;
5940 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
5941 kvm->arch.x2apic_broadcast_quirk_disabled = true;
5945 case KVM_CAP_X86_DISABLE_EXITS:
5947 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
5950 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
5951 kvm_can_mwait_in_guest())
5952 kvm->arch.mwait_in_guest = true;
5953 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
5954 kvm->arch.hlt_in_guest = true;
5955 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
5956 kvm->arch.pause_in_guest = true;
5957 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
5958 kvm->arch.cstate_in_guest = true;
5961 case KVM_CAP_MSR_PLATFORM_INFO:
5962 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
5965 case KVM_CAP_EXCEPTION_PAYLOAD:
5966 kvm->arch.exception_payload_enabled = cap->args[0];
5969 case KVM_CAP_X86_USER_SPACE_MSR:
5970 kvm->arch.user_space_msr_mask = cap->args[0];
5973 case KVM_CAP_X86_BUS_LOCK_EXIT:
5975 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE)
5978 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) &&
5979 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
5982 if (kvm_has_bus_lock_exit &&
5983 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
5984 kvm->arch.bus_lock_detection_enabled = true;
5987 #ifdef CONFIG_X86_SGX_KVM
5988 case KVM_CAP_SGX_ATTRIBUTE: {
5989 unsigned long allowed_attributes = 0;
5991 r = sgx_set_attribute(&allowed_attributes, cap->args[0]);
5995 /* KVM only supports the PROVISIONKEY privileged attribute. */
5996 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) &&
5997 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY))
5998 kvm->arch.sgx_provisioning_allowed = true;
6004 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
6006 if (!kvm_x86_ops.vm_copy_enc_context_from)
6009 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]);
6011 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
6013 if (!kvm_x86_ops.vm_move_enc_context_from)
6016 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]);
6018 case KVM_CAP_EXIT_HYPERCALL:
6019 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) {
6023 kvm->arch.hypercall_exit_enabled = cap->args[0];
6026 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
6028 if (cap->args[0] & ~1)
6030 kvm->arch.exit_on_emulation_error = cap->args[0];
6033 case KVM_CAP_PMU_CAPABILITY:
6035 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK))
6038 mutex_lock(&kvm->lock);
6039 if (!kvm->created_vcpus) {
6040 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE);
6043 mutex_unlock(&kvm->lock);
6052 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow)
6054 struct kvm_x86_msr_filter *msr_filter;
6056 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT);
6060 msr_filter->default_allow = default_allow;
6064 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter)
6071 for (i = 0; i < msr_filter->count; i++)
6072 kfree(msr_filter->ranges[i].bitmap);
6077 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter,
6078 struct kvm_msr_filter_range *user_range)
6080 unsigned long *bitmap = NULL;
6083 if (!user_range->nmsrs)
6086 if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE))
6089 if (!user_range->flags)
6092 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
6093 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
6096 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
6098 return PTR_ERR(bitmap);
6100 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) {
6101 .flags = user_range->flags,
6102 .base = user_range->base,
6103 .nmsrs = user_range->nmsrs,
6107 msr_filter->count++;
6111 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp)
6113 struct kvm_msr_filter __user *user_msr_filter = argp;
6114 struct kvm_x86_msr_filter *new_filter, *old_filter;
6115 struct kvm_msr_filter filter;
6121 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
6124 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++)
6125 empty &= !filter.ranges[i].nmsrs;
6127 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY);
6128 if (empty && !default_allow)
6131 new_filter = kvm_alloc_msr_filter(default_allow);
6135 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
6136 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]);
6138 kvm_free_msr_filter(new_filter);
6143 mutex_lock(&kvm->lock);
6145 /* The per-VM filter is protected by kvm->lock... */
6146 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1);
6148 rcu_assign_pointer(kvm->arch.msr_filter, new_filter);
6149 synchronize_srcu(&kvm->srcu);
6151 kvm_free_msr_filter(old_filter);
6153 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
6154 mutex_unlock(&kvm->lock);
6159 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER
6160 static int kvm_arch_suspend_notifier(struct kvm *kvm)
6162 struct kvm_vcpu *vcpu;
6166 mutex_lock(&kvm->lock);
6167 kvm_for_each_vcpu(i, vcpu, kvm) {
6168 if (!vcpu->arch.pv_time_enabled)
6171 ret = kvm_set_guest_paused(vcpu);
6173 kvm_err("Failed to pause guest VCPU%d: %d\n",
6174 vcpu->vcpu_id, ret);
6178 mutex_unlock(&kvm->lock);
6180 return ret ? NOTIFY_BAD : NOTIFY_DONE;
6183 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state)
6186 case PM_HIBERNATION_PREPARE:
6187 case PM_SUSPEND_PREPARE:
6188 return kvm_arch_suspend_notifier(kvm);
6193 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */
6195 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp)
6197 struct kvm_clock_data data = { 0 };
6199 get_kvmclock(kvm, &data);
6200 if (copy_to_user(argp, &data, sizeof(data)))
6206 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp)
6208 struct kvm_arch *ka = &kvm->arch;
6209 struct kvm_clock_data data;
6212 if (copy_from_user(&data, argp, sizeof(data)))
6216 * Only KVM_CLOCK_REALTIME is used, but allow passing the
6217 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK.
6219 if (data.flags & ~KVM_CLOCK_VALID_FLAGS)
6222 kvm_hv_invalidate_tsc_page(kvm);
6223 kvm_start_pvclock_update(kvm);
6224 pvclock_update_vm_gtod_copy(kvm);
6227 * This pairs with kvm_guest_time_update(): when masterclock is
6228 * in use, we use master_kernel_ns + kvmclock_offset to set
6229 * unsigned 'system_time' so if we use get_kvmclock_ns() (which
6230 * is slightly ahead) here we risk going negative on unsigned
6231 * 'system_time' when 'data.clock' is very small.
6233 if (data.flags & KVM_CLOCK_REALTIME) {
6234 u64 now_real_ns = ktime_get_real_ns();
6237 * Avoid stepping the kvmclock backwards.
6239 if (now_real_ns > data.realtime)
6240 data.clock += now_real_ns - data.realtime;
6243 if (ka->use_master_clock)
6244 now_raw_ns = ka->master_kernel_ns;
6246 now_raw_ns = get_kvmclock_base_ns();
6247 ka->kvmclock_offset = data.clock - now_raw_ns;
6248 kvm_end_pvclock_update(kvm);
6252 long kvm_arch_vm_ioctl(struct file *filp,
6253 unsigned int ioctl, unsigned long arg)
6255 struct kvm *kvm = filp->private_data;
6256 void __user *argp = (void __user *)arg;
6259 * This union makes it completely explicit to gcc-3.x
6260 * that these two variables' stack usage should be
6261 * combined, not added together.
6264 struct kvm_pit_state ps;
6265 struct kvm_pit_state2 ps2;
6266 struct kvm_pit_config pit_config;
6270 case KVM_SET_TSS_ADDR:
6271 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
6273 case KVM_SET_IDENTITY_MAP_ADDR: {
6276 mutex_lock(&kvm->lock);
6278 if (kvm->created_vcpus)
6279 goto set_identity_unlock;
6281 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
6282 goto set_identity_unlock;
6283 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
6284 set_identity_unlock:
6285 mutex_unlock(&kvm->lock);
6288 case KVM_SET_NR_MMU_PAGES:
6289 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
6291 case KVM_GET_NR_MMU_PAGES:
6292 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
6294 case KVM_CREATE_IRQCHIP: {
6295 mutex_lock(&kvm->lock);
6298 if (irqchip_in_kernel(kvm))
6299 goto create_irqchip_unlock;
6302 if (kvm->created_vcpus)
6303 goto create_irqchip_unlock;
6305 r = kvm_pic_init(kvm);
6307 goto create_irqchip_unlock;
6309 r = kvm_ioapic_init(kvm);
6311 kvm_pic_destroy(kvm);
6312 goto create_irqchip_unlock;
6315 r = kvm_setup_default_irq_routing(kvm);
6317 kvm_ioapic_destroy(kvm);
6318 kvm_pic_destroy(kvm);
6319 goto create_irqchip_unlock;
6321 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
6323 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
6324 kvm_request_apicv_update(kvm, true, APICV_INHIBIT_REASON_ABSENT);
6325 create_irqchip_unlock:
6326 mutex_unlock(&kvm->lock);
6329 case KVM_CREATE_PIT:
6330 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
6332 case KVM_CREATE_PIT2:
6334 if (copy_from_user(&u.pit_config, argp,
6335 sizeof(struct kvm_pit_config)))
6338 mutex_lock(&kvm->lock);
6341 goto create_pit_unlock;
6343 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
6347 mutex_unlock(&kvm->lock);
6349 case KVM_GET_IRQCHIP: {
6350 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6351 struct kvm_irqchip *chip;
6353 chip = memdup_user(argp, sizeof(*chip));
6360 if (!irqchip_kernel(kvm))
6361 goto get_irqchip_out;
6362 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
6364 goto get_irqchip_out;
6366 if (copy_to_user(argp, chip, sizeof(*chip)))
6367 goto get_irqchip_out;
6373 case KVM_SET_IRQCHIP: {
6374 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6375 struct kvm_irqchip *chip;
6377 chip = memdup_user(argp, sizeof(*chip));
6384 if (!irqchip_kernel(kvm))
6385 goto set_irqchip_out;
6386 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
6393 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
6396 if (!kvm->arch.vpit)
6398 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
6402 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
6409 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
6411 mutex_lock(&kvm->lock);
6413 if (!kvm->arch.vpit)
6415 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
6417 mutex_unlock(&kvm->lock);
6420 case KVM_GET_PIT2: {
6422 if (!kvm->arch.vpit)
6424 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
6428 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
6433 case KVM_SET_PIT2: {
6435 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
6437 mutex_lock(&kvm->lock);
6439 if (!kvm->arch.vpit)
6441 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
6443 mutex_unlock(&kvm->lock);
6446 case KVM_REINJECT_CONTROL: {
6447 struct kvm_reinject_control control;
6449 if (copy_from_user(&control, argp, sizeof(control)))
6452 if (!kvm->arch.vpit)
6454 r = kvm_vm_ioctl_reinject(kvm, &control);
6457 case KVM_SET_BOOT_CPU_ID:
6459 mutex_lock(&kvm->lock);
6460 if (kvm->created_vcpus)
6463 kvm->arch.bsp_vcpu_id = arg;
6464 mutex_unlock(&kvm->lock);
6466 #ifdef CONFIG_KVM_XEN
6467 case KVM_XEN_HVM_CONFIG: {
6468 struct kvm_xen_hvm_config xhc;
6470 if (copy_from_user(&xhc, argp, sizeof(xhc)))
6472 r = kvm_xen_hvm_config(kvm, &xhc);
6475 case KVM_XEN_HVM_GET_ATTR: {
6476 struct kvm_xen_hvm_attr xha;
6479 if (copy_from_user(&xha, argp, sizeof(xha)))
6481 r = kvm_xen_hvm_get_attr(kvm, &xha);
6482 if (!r && copy_to_user(argp, &xha, sizeof(xha)))
6486 case KVM_XEN_HVM_SET_ATTR: {
6487 struct kvm_xen_hvm_attr xha;
6490 if (copy_from_user(&xha, argp, sizeof(xha)))
6492 r = kvm_xen_hvm_set_attr(kvm, &xha);
6497 r = kvm_vm_ioctl_set_clock(kvm, argp);
6500 r = kvm_vm_ioctl_get_clock(kvm, argp);
6502 case KVM_MEMORY_ENCRYPT_OP: {
6504 if (!kvm_x86_ops.mem_enc_ioctl)
6507 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp);
6510 case KVM_MEMORY_ENCRYPT_REG_REGION: {
6511 struct kvm_enc_region region;
6514 if (copy_from_user(®ion, argp, sizeof(region)))
6518 if (!kvm_x86_ops.mem_enc_register_region)
6521 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion);
6524 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
6525 struct kvm_enc_region region;
6528 if (copy_from_user(®ion, argp, sizeof(region)))
6532 if (!kvm_x86_ops.mem_enc_unregister_region)
6535 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion);
6538 case KVM_HYPERV_EVENTFD: {
6539 struct kvm_hyperv_eventfd hvevfd;
6542 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
6544 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
6547 case KVM_SET_PMU_EVENT_FILTER:
6548 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
6550 case KVM_X86_SET_MSR_FILTER:
6551 r = kvm_vm_ioctl_set_msr_filter(kvm, argp);
6560 static void kvm_init_msr_list(void)
6562 struct x86_pmu_capability x86_pmu;
6566 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
6567 "Please update the fixed PMCs in msrs_to_saved_all[]");
6569 perf_get_x86_pmu_capability(&x86_pmu);
6571 num_msrs_to_save = 0;
6572 num_emulated_msrs = 0;
6573 num_msr_based_features = 0;
6575 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
6576 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
6580 * Even MSRs that are valid in the host may not be exposed
6581 * to the guests in some cases.
6583 switch (msrs_to_save_all[i]) {
6584 case MSR_IA32_BNDCFGS:
6585 if (!kvm_mpx_supported())
6589 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) &&
6590 !kvm_cpu_cap_has(X86_FEATURE_RDPID))
6593 case MSR_IA32_UMWAIT_CONTROL:
6594 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
6597 case MSR_IA32_RTIT_CTL:
6598 case MSR_IA32_RTIT_STATUS:
6599 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
6602 case MSR_IA32_RTIT_CR3_MATCH:
6603 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
6604 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
6607 case MSR_IA32_RTIT_OUTPUT_BASE:
6608 case MSR_IA32_RTIT_OUTPUT_MASK:
6609 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
6610 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
6611 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
6614 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
6615 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
6616 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
6617 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
6620 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
6621 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
6622 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
6625 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
6626 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
6627 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
6631 case MSR_IA32_XFD_ERR:
6632 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
6639 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
6642 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
6643 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i]))
6646 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
6649 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
6650 struct kvm_msr_entry msr;
6652 msr.index = msr_based_features_all[i];
6653 if (kvm_get_msr_feature(&msr))
6656 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
6660 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
6668 if (!(lapic_in_kernel(vcpu) &&
6669 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
6670 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
6681 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
6688 if (!(lapic_in_kernel(vcpu) &&
6689 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
6691 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
6693 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
6703 static void kvm_set_segment(struct kvm_vcpu *vcpu,
6704 struct kvm_segment *var, int seg)
6706 static_call(kvm_x86_set_segment)(vcpu, var, seg);
6709 void kvm_get_segment(struct kvm_vcpu *vcpu,
6710 struct kvm_segment *var, int seg)
6712 static_call(kvm_x86_get_segment)(vcpu, var, seg);
6715 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
6716 struct x86_exception *exception)
6718 struct kvm_mmu *mmu = vcpu->arch.mmu;
6721 BUG_ON(!mmu_is_nested(vcpu));
6723 /* NPT walks are always user-walks */
6724 access |= PFERR_USER_MASK;
6725 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception);
6730 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
6731 struct x86_exception *exception)
6733 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6735 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6736 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
6738 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read);
6740 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
6741 struct x86_exception *exception)
6743 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6745 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6746 access |= PFERR_FETCH_MASK;
6747 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
6750 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
6751 struct x86_exception *exception)
6753 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6755 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6756 access |= PFERR_WRITE_MASK;
6757 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
6759 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write);
6761 /* uses this to access any guest's mapped memory without checking CPL */
6762 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
6763 struct x86_exception *exception)
6765 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6767 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception);
6770 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
6771 struct kvm_vcpu *vcpu, u32 access,
6772 struct x86_exception *exception)
6774 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6776 int r = X86EMUL_CONTINUE;
6779 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
6780 unsigned offset = addr & (PAGE_SIZE-1);
6781 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
6784 if (gpa == UNMAPPED_GVA)
6785 return X86EMUL_PROPAGATE_FAULT;
6786 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
6789 r = X86EMUL_IO_NEEDED;
6801 /* used for instruction fetching */
6802 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
6803 gva_t addr, void *val, unsigned int bytes,
6804 struct x86_exception *exception)
6806 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6807 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6808 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6812 /* Inline kvm_read_guest_virt_helper for speed. */
6813 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK,
6815 if (unlikely(gpa == UNMAPPED_GVA))
6816 return X86EMUL_PROPAGATE_FAULT;
6818 offset = addr & (PAGE_SIZE-1);
6819 if (WARN_ON(offset + bytes > PAGE_SIZE))
6820 bytes = (unsigned)PAGE_SIZE - offset;
6821 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
6823 if (unlikely(ret < 0))
6824 return X86EMUL_IO_NEEDED;
6826 return X86EMUL_CONTINUE;
6829 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
6830 gva_t addr, void *val, unsigned int bytes,
6831 struct x86_exception *exception)
6833 u32 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
6836 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
6837 * is returned, but our callers are not ready for that and they blindly
6838 * call kvm_inject_page_fault. Ensure that they at least do not leak
6839 * uninitialized kernel stack memory into cr2 and error code.
6841 memset(exception, 0, sizeof(*exception));
6842 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
6845 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
6847 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
6848 gva_t addr, void *val, unsigned int bytes,
6849 struct x86_exception *exception, bool system)
6851 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6854 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3)
6855 access |= PFERR_USER_MASK;
6857 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
6860 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
6861 unsigned long addr, void *val, unsigned int bytes)
6863 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6864 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
6866 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
6869 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
6870 struct kvm_vcpu *vcpu, u32 access,
6871 struct x86_exception *exception)
6873 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6875 int r = X86EMUL_CONTINUE;
6878 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
6879 unsigned offset = addr & (PAGE_SIZE-1);
6880 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
6883 if (gpa == UNMAPPED_GVA)
6884 return X86EMUL_PROPAGATE_FAULT;
6885 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
6887 r = X86EMUL_IO_NEEDED;
6899 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
6900 unsigned int bytes, struct x86_exception *exception,
6903 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6904 u32 access = PFERR_WRITE_MASK;
6906 if (!system && static_call(kvm_x86_get_cpl)(vcpu) == 3)
6907 access |= PFERR_USER_MASK;
6909 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6913 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
6914 unsigned int bytes, struct x86_exception *exception)
6916 /* kvm_write_guest_virt_system can pull in tons of pages. */
6917 vcpu->arch.l1tf_flush_l1d = true;
6919 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
6920 PFERR_WRITE_MASK, exception);
6922 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
6924 static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type,
6925 void *insn, int insn_len)
6927 return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type,
6931 int handle_ud(struct kvm_vcpu *vcpu)
6933 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
6934 int emul_type = EMULTYPE_TRAP_UD;
6935 char sig[5]; /* ud2; .ascii "kvm" */
6936 struct x86_exception e;
6938 if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0)))
6941 if (force_emulation_prefix &&
6942 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
6943 sig, sizeof(sig), &e) == 0 &&
6944 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
6945 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
6946 emul_type = EMULTYPE_TRAP_UD_FORCED;
6949 return kvm_emulate_instruction(vcpu, emul_type);
6951 EXPORT_SYMBOL_GPL(handle_ud);
6953 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6954 gpa_t gpa, bool write)
6956 /* For APIC access vmexit */
6957 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
6960 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
6961 trace_vcpu_match_mmio(gva, gpa, write, true);
6968 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
6969 gpa_t *gpa, struct x86_exception *exception,
6972 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
6973 u32 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0)
6974 | (write ? PFERR_WRITE_MASK : 0);
6977 * currently PKRU is only applied to ept enabled guest so
6978 * there is no pkey in EPT page table for L1 guest or EPT
6979 * shadow page table for L2 guest.
6981 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) ||
6982 !permission_fault(vcpu, vcpu->arch.walk_mmu,
6983 vcpu->arch.mmio_access, 0, access))) {
6984 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
6985 (gva & (PAGE_SIZE - 1));
6986 trace_vcpu_match_mmio(gva, *gpa, write, false);
6990 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
6992 if (*gpa == UNMAPPED_GVA)
6995 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
6998 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
6999 const void *val, int bytes)
7003 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
7006 kvm_page_track_write(vcpu, gpa, val, bytes);
7010 struct read_write_emulator_ops {
7011 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
7013 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
7014 void *val, int bytes);
7015 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7016 int bytes, void *val);
7017 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7018 void *val, int bytes);
7022 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
7024 if (vcpu->mmio_read_completed) {
7025 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
7026 vcpu->mmio_fragments[0].gpa, val);
7027 vcpu->mmio_read_completed = 0;
7034 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7035 void *val, int bytes)
7037 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
7040 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7041 void *val, int bytes)
7043 return emulator_write_phys(vcpu, gpa, val, bytes);
7046 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
7048 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
7049 return vcpu_mmio_write(vcpu, gpa, bytes, val);
7052 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7053 void *val, int bytes)
7055 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
7056 return X86EMUL_IO_NEEDED;
7059 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7060 void *val, int bytes)
7062 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
7064 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
7065 return X86EMUL_CONTINUE;
7068 static const struct read_write_emulator_ops read_emultor = {
7069 .read_write_prepare = read_prepare,
7070 .read_write_emulate = read_emulate,
7071 .read_write_mmio = vcpu_mmio_read,
7072 .read_write_exit_mmio = read_exit_mmio,
7075 static const struct read_write_emulator_ops write_emultor = {
7076 .read_write_emulate = write_emulate,
7077 .read_write_mmio = write_mmio,
7078 .read_write_exit_mmio = write_exit_mmio,
7082 static int emulator_read_write_onepage(unsigned long addr, void *val,
7084 struct x86_exception *exception,
7085 struct kvm_vcpu *vcpu,
7086 const struct read_write_emulator_ops *ops)
7090 bool write = ops->write;
7091 struct kvm_mmio_fragment *frag;
7092 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7095 * If the exit was due to a NPF we may already have a GPA.
7096 * If the GPA is present, use it to avoid the GVA to GPA table walk.
7097 * Note, this cannot be used on string operations since string
7098 * operation using rep will only have the initial GPA from the NPF
7101 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
7102 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
7103 gpa = ctxt->gpa_val;
7104 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
7106 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
7108 return X86EMUL_PROPAGATE_FAULT;
7111 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
7112 return X86EMUL_CONTINUE;
7115 * Is this MMIO handled locally?
7117 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
7118 if (handled == bytes)
7119 return X86EMUL_CONTINUE;
7125 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
7126 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
7130 return X86EMUL_CONTINUE;
7133 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
7135 void *val, unsigned int bytes,
7136 struct x86_exception *exception,
7137 const struct read_write_emulator_ops *ops)
7139 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7143 if (ops->read_write_prepare &&
7144 ops->read_write_prepare(vcpu, val, bytes))
7145 return X86EMUL_CONTINUE;
7147 vcpu->mmio_nr_fragments = 0;
7149 /* Crossing a page boundary? */
7150 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
7153 now = -addr & ~PAGE_MASK;
7154 rc = emulator_read_write_onepage(addr, val, now, exception,
7157 if (rc != X86EMUL_CONTINUE)
7160 if (ctxt->mode != X86EMUL_MODE_PROT64)
7166 rc = emulator_read_write_onepage(addr, val, bytes, exception,
7168 if (rc != X86EMUL_CONTINUE)
7171 if (!vcpu->mmio_nr_fragments)
7174 gpa = vcpu->mmio_fragments[0].gpa;
7176 vcpu->mmio_needed = 1;
7177 vcpu->mmio_cur_fragment = 0;
7179 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
7180 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
7181 vcpu->run->exit_reason = KVM_EXIT_MMIO;
7182 vcpu->run->mmio.phys_addr = gpa;
7184 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
7187 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
7191 struct x86_exception *exception)
7193 return emulator_read_write(ctxt, addr, val, bytes,
7194 exception, &read_emultor);
7197 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
7201 struct x86_exception *exception)
7203 return emulator_read_write(ctxt, addr, (void *)val, bytes,
7204 exception, &write_emultor);
7207 #define CMPXCHG_TYPE(t, ptr, old, new) \
7208 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
7210 #ifdef CONFIG_X86_64
7211 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
7213 # define CMPXCHG64(ptr, old, new) \
7214 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
7217 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
7222 struct x86_exception *exception)
7224 struct kvm_host_map map;
7225 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7231 /* guests cmpxchg8b have to be emulated atomically */
7232 if (bytes > 8 || (bytes & (bytes - 1)))
7235 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
7237 if (gpa == UNMAPPED_GVA ||
7238 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7242 * Emulate the atomic as a straight write to avoid #AC if SLD is
7243 * enabled in the host and the access splits a cache line.
7245 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
7246 page_line_mask = ~(cache_line_size() - 1);
7248 page_line_mask = PAGE_MASK;
7250 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
7253 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
7256 kaddr = map.hva + offset_in_page(gpa);
7260 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
7263 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
7266 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
7269 exchanged = CMPXCHG64(kaddr, old, new);
7275 kvm_vcpu_unmap(vcpu, &map, true);
7278 return X86EMUL_CMPXCHG_FAILED;
7280 kvm_page_track_write(vcpu, gpa, new, bytes);
7282 return X86EMUL_CONTINUE;
7285 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
7287 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
7290 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
7294 for (i = 0; i < vcpu->arch.pio.count; i++) {
7295 if (vcpu->arch.pio.in)
7296 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
7297 vcpu->arch.pio.size, pd);
7299 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
7300 vcpu->arch.pio.port, vcpu->arch.pio.size,
7304 pd += vcpu->arch.pio.size;
7309 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
7310 unsigned short port,
7311 unsigned int count, bool in)
7313 vcpu->arch.pio.port = port;
7314 vcpu->arch.pio.in = in;
7315 vcpu->arch.pio.count = count;
7316 vcpu->arch.pio.size = size;
7318 if (!kernel_pio(vcpu, vcpu->arch.pio_data))
7321 vcpu->run->exit_reason = KVM_EXIT_IO;
7322 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
7323 vcpu->run->io.size = size;
7324 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
7325 vcpu->run->io.count = count;
7326 vcpu->run->io.port = port;
7331 static int __emulator_pio_in(struct kvm_vcpu *vcpu, int size,
7332 unsigned short port, unsigned int count)
7334 WARN_ON(vcpu->arch.pio.count);
7335 memset(vcpu->arch.pio_data, 0, size * count);
7336 return emulator_pio_in_out(vcpu, size, port, count, true);
7339 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val)
7341 int size = vcpu->arch.pio.size;
7342 unsigned count = vcpu->arch.pio.count;
7343 memcpy(val, vcpu->arch.pio_data, size * count);
7344 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data);
7345 vcpu->arch.pio.count = 0;
7348 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
7349 unsigned short port, void *val, unsigned int count)
7351 if (vcpu->arch.pio.count) {
7353 * Complete a previous iteration that required userspace I/O.
7354 * Note, @count isn't guaranteed to match pio.count as userspace
7355 * can modify ECX before rerunning the vCPU. Ignore any such
7356 * shenanigans as KVM doesn't support modifying the rep count,
7357 * and the emulator ensures @count doesn't overflow the buffer.
7360 int r = __emulator_pio_in(vcpu, size, port, count);
7364 /* Results already available, fall through. */
7367 complete_emulator_pio_in(vcpu, val);
7371 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
7372 int size, unsigned short port, void *val,
7375 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
7379 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
7380 unsigned short port, const void *val,
7385 memcpy(vcpu->arch.pio_data, val, size * count);
7386 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
7387 ret = emulator_pio_in_out(vcpu, size, port, count, false);
7389 vcpu->arch.pio.count = 0;
7394 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
7395 int size, unsigned short port,
7396 const void *val, unsigned int count)
7398 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
7401 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
7403 return static_call(kvm_x86_get_segment_base)(vcpu, seg);
7406 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
7408 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
7411 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
7413 if (!need_emulate_wbinvd(vcpu))
7414 return X86EMUL_CONTINUE;
7416 if (static_call(kvm_x86_has_wbinvd_exit)()) {
7417 int cpu = get_cpu();
7419 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
7420 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask,
7421 wbinvd_ipi, NULL, 1);
7423 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
7426 return X86EMUL_CONTINUE;
7429 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
7431 kvm_emulate_wbinvd_noskip(vcpu);
7432 return kvm_skip_emulated_instruction(vcpu);
7434 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
7438 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
7440 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
7443 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
7444 unsigned long *dest)
7446 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
7449 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
7450 unsigned long value)
7453 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
7456 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
7458 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
7461 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
7463 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7464 unsigned long value;
7468 value = kvm_read_cr0(vcpu);
7471 value = vcpu->arch.cr2;
7474 value = kvm_read_cr3(vcpu);
7477 value = kvm_read_cr4(vcpu);
7480 value = kvm_get_cr8(vcpu);
7483 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7490 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
7492 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7497 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
7500 vcpu->arch.cr2 = val;
7503 res = kvm_set_cr3(vcpu, val);
7506 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
7509 res = kvm_set_cr8(vcpu, val);
7512 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7519 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
7521 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt));
7524 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7526 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt);
7529 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7531 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt);
7534 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7536 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt);
7539 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7541 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt);
7544 static unsigned long emulator_get_cached_segment_base(
7545 struct x86_emulate_ctxt *ctxt, int seg)
7547 return get_segment_base(emul_to_vcpu(ctxt), seg);
7550 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
7551 struct desc_struct *desc, u32 *base3,
7554 struct kvm_segment var;
7556 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
7557 *selector = var.selector;
7560 memset(desc, 0, sizeof(*desc));
7568 set_desc_limit(desc, var.limit);
7569 set_desc_base(desc, (unsigned long)var.base);
7570 #ifdef CONFIG_X86_64
7572 *base3 = var.base >> 32;
7574 desc->type = var.type;
7576 desc->dpl = var.dpl;
7577 desc->p = var.present;
7578 desc->avl = var.avl;
7586 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
7587 struct desc_struct *desc, u32 base3,
7590 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7591 struct kvm_segment var;
7593 var.selector = selector;
7594 var.base = get_desc_base(desc);
7595 #ifdef CONFIG_X86_64
7596 var.base |= ((u64)base3) << 32;
7598 var.limit = get_desc_limit(desc);
7600 var.limit = (var.limit << 12) | 0xfff;
7601 var.type = desc->type;
7602 var.dpl = desc->dpl;
7607 var.avl = desc->avl;
7608 var.present = desc->p;
7609 var.unusable = !var.present;
7612 kvm_set_segment(vcpu, &var, seg);
7616 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
7617 u32 msr_index, u64 *pdata)
7619 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7622 r = kvm_get_msr(vcpu, msr_index, pdata);
7624 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0,
7625 complete_emulated_rdmsr, r)) {
7626 /* Bounce to user space */
7627 return X86EMUL_IO_NEEDED;
7633 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
7634 u32 msr_index, u64 data)
7636 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7639 r = kvm_set_msr(vcpu, msr_index, data);
7641 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data,
7642 complete_emulated_msr_access, r)) {
7643 /* Bounce to user space */
7644 return X86EMUL_IO_NEEDED;
7650 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
7652 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7654 return vcpu->arch.smbase;
7657 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
7659 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7661 vcpu->arch.smbase = smbase;
7664 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
7667 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc))
7672 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
7673 u32 pmc, u64 *pdata)
7675 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
7678 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
7680 emul_to_vcpu(ctxt)->arch.halt_request = 1;
7683 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
7684 struct x86_instruction_info *info,
7685 enum x86_intercept_stage stage)
7687 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage,
7691 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
7692 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
7695 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
7698 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
7700 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
7703 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
7705 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
7708 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
7710 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
7713 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
7715 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg);
7718 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
7720 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val);
7723 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
7725 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked);
7728 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
7730 return emul_to_vcpu(ctxt)->arch.hflags;
7733 static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt)
7735 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7737 kvm_smm_changed(vcpu, false);
7740 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt,
7741 const char *smstate)
7743 return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate);
7746 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt)
7748 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt));
7751 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
7753 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
7756 static const struct x86_emulate_ops emulate_ops = {
7757 .read_gpr = emulator_read_gpr,
7758 .write_gpr = emulator_write_gpr,
7759 .read_std = emulator_read_std,
7760 .write_std = emulator_write_std,
7761 .read_phys = kvm_read_guest_phys_system,
7762 .fetch = kvm_fetch_guest_virt,
7763 .read_emulated = emulator_read_emulated,
7764 .write_emulated = emulator_write_emulated,
7765 .cmpxchg_emulated = emulator_cmpxchg_emulated,
7766 .invlpg = emulator_invlpg,
7767 .pio_in_emulated = emulator_pio_in_emulated,
7768 .pio_out_emulated = emulator_pio_out_emulated,
7769 .get_segment = emulator_get_segment,
7770 .set_segment = emulator_set_segment,
7771 .get_cached_segment_base = emulator_get_cached_segment_base,
7772 .get_gdt = emulator_get_gdt,
7773 .get_idt = emulator_get_idt,
7774 .set_gdt = emulator_set_gdt,
7775 .set_idt = emulator_set_idt,
7776 .get_cr = emulator_get_cr,
7777 .set_cr = emulator_set_cr,
7778 .cpl = emulator_get_cpl,
7779 .get_dr = emulator_get_dr,
7780 .set_dr = emulator_set_dr,
7781 .get_smbase = emulator_get_smbase,
7782 .set_smbase = emulator_set_smbase,
7783 .set_msr = emulator_set_msr,
7784 .get_msr = emulator_get_msr,
7785 .check_pmc = emulator_check_pmc,
7786 .read_pmc = emulator_read_pmc,
7787 .halt = emulator_halt,
7788 .wbinvd = emulator_wbinvd,
7789 .fix_hypercall = emulator_fix_hypercall,
7790 .intercept = emulator_intercept,
7791 .get_cpuid = emulator_get_cpuid,
7792 .guest_has_long_mode = emulator_guest_has_long_mode,
7793 .guest_has_movbe = emulator_guest_has_movbe,
7794 .guest_has_fxsr = emulator_guest_has_fxsr,
7795 .set_nmi_mask = emulator_set_nmi_mask,
7796 .get_hflags = emulator_get_hflags,
7797 .exiting_smm = emulator_exiting_smm,
7798 .leave_smm = emulator_leave_smm,
7799 .triple_fault = emulator_triple_fault,
7800 .set_xcr = emulator_set_xcr,
7803 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
7805 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
7807 * an sti; sti; sequence only disable interrupts for the first
7808 * instruction. So, if the last instruction, be it emulated or
7809 * not, left the system with the INT_STI flag enabled, it
7810 * means that the last instruction is an sti. We should not
7811 * leave the flag on in this case. The same goes for mov ss
7813 if (int_shadow & mask)
7815 if (unlikely(int_shadow || mask)) {
7816 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask);
7818 kvm_make_request(KVM_REQ_EVENT, vcpu);
7822 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
7824 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7825 if (ctxt->exception.vector == PF_VECTOR)
7826 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
7828 if (ctxt->exception.error_code_valid)
7829 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
7830 ctxt->exception.error_code);
7832 kvm_queue_exception(vcpu, ctxt->exception.vector);
7836 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
7838 struct x86_emulate_ctxt *ctxt;
7840 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
7842 pr_err("kvm: failed to allocate vcpu's emulator\n");
7847 ctxt->ops = &emulate_ops;
7848 vcpu->arch.emulate_ctxt = ctxt;
7853 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
7855 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7858 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
7860 ctxt->gpa_available = false;
7861 ctxt->eflags = kvm_get_rflags(vcpu);
7862 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
7864 ctxt->eip = kvm_rip_read(vcpu);
7865 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
7866 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
7867 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
7868 cs_db ? X86EMUL_MODE_PROT32 :
7869 X86EMUL_MODE_PROT16;
7870 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
7871 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
7872 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
7874 ctxt->interruptibility = 0;
7875 ctxt->have_exception = false;
7876 ctxt->exception.vector = -1;
7877 ctxt->perm_ok = false;
7879 init_decode_cache(ctxt);
7880 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
7883 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
7885 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7888 init_emulate_ctxt(vcpu);
7892 ctxt->_eip = ctxt->eip + inc_eip;
7893 ret = emulate_int_real(ctxt, irq);
7895 if (ret != X86EMUL_CONTINUE) {
7896 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
7898 ctxt->eip = ctxt->_eip;
7899 kvm_rip_write(vcpu, ctxt->eip);
7900 kvm_set_rflags(vcpu, ctxt->eflags);
7903 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
7905 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
7906 u8 ndata, u8 *insn_bytes, u8 insn_size)
7908 struct kvm_run *run = vcpu->run;
7913 * Zero the whole array used to retrieve the exit info, as casting to
7914 * u32 for select entries will leave some chunks uninitialized.
7916 memset(&info, 0, sizeof(info));
7918 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1],
7919 &info[2], (u32 *)&info[3],
7922 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7923 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION;
7926 * There's currently space for 13 entries, but 5 are used for the exit
7927 * reason and info. Restrict to 4 to reduce the maintenance burden
7928 * when expanding kvm_run.emulation_failure in the future.
7930 if (WARN_ON_ONCE(ndata > 4))
7933 /* Always include the flags as a 'data' entry. */
7935 run->emulation_failure.flags = 0;
7938 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) +
7939 sizeof(run->emulation_failure.insn_bytes) != 16));
7941 run->emulation_failure.flags |=
7942 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES;
7943 run->emulation_failure.insn_size = insn_size;
7944 memset(run->emulation_failure.insn_bytes, 0x90,
7945 sizeof(run->emulation_failure.insn_bytes));
7946 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size);
7949 memcpy(&run->internal.data[info_start], info, sizeof(info));
7950 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data,
7951 ndata * sizeof(data[0]));
7953 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata;
7956 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu)
7958 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7960 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data,
7961 ctxt->fetch.end - ctxt->fetch.data);
7964 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
7967 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0);
7969 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit);
7971 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu)
7973 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0);
7975 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit);
7977 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
7979 struct kvm *kvm = vcpu->kvm;
7981 ++vcpu->stat.insn_emulation_fail;
7982 trace_kvm_emulate_insn_failed(vcpu);
7984 if (emulation_type & EMULTYPE_VMWARE_GP) {
7985 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
7989 if (kvm->arch.exit_on_emulation_error ||
7990 (emulation_type & EMULTYPE_SKIP)) {
7991 prepare_emulation_ctxt_failure_exit(vcpu);
7995 kvm_queue_exception(vcpu, UD_VECTOR);
7997 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) {
7998 prepare_emulation_ctxt_failure_exit(vcpu);
8005 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8006 bool write_fault_to_shadow_pgtable,
8009 gpa_t gpa = cr2_or_gpa;
8012 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8015 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8016 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8019 if (!vcpu->arch.mmu->direct_map) {
8021 * Write permission should be allowed since only
8022 * write access need to be emulated.
8024 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8027 * If the mapping is invalid in guest, let cpu retry
8028 * it to generate fault.
8030 if (gpa == UNMAPPED_GVA)
8035 * Do not retry the unhandleable instruction if it faults on the
8036 * readonly host memory, otherwise it will goto a infinite loop:
8037 * retry instruction -> write #PF -> emulation fail -> retry
8038 * instruction -> ...
8040 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
8043 * If the instruction failed on the error pfn, it can not be fixed,
8044 * report the error to userspace.
8046 if (is_error_noslot_pfn(pfn))
8049 kvm_release_pfn_clean(pfn);
8051 /* The instructions are well-emulated on direct mmu. */
8052 if (vcpu->arch.mmu->direct_map) {
8053 unsigned int indirect_shadow_pages;
8055 write_lock(&vcpu->kvm->mmu_lock);
8056 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
8057 write_unlock(&vcpu->kvm->mmu_lock);
8059 if (indirect_shadow_pages)
8060 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8066 * if emulation was due to access to shadowed page table
8067 * and it failed try to unshadow page and re-enter the
8068 * guest to let CPU execute the instruction.
8070 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8073 * If the access faults on its page table, it can not
8074 * be fixed by unprotecting shadow page and it should
8075 * be reported to userspace.
8077 return !write_fault_to_shadow_pgtable;
8080 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
8081 gpa_t cr2_or_gpa, int emulation_type)
8083 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8084 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
8086 last_retry_eip = vcpu->arch.last_retry_eip;
8087 last_retry_addr = vcpu->arch.last_retry_addr;
8090 * If the emulation is caused by #PF and it is non-page_table
8091 * writing instruction, it means the VM-EXIT is caused by shadow
8092 * page protected, we can zap the shadow page and retry this
8093 * instruction directly.
8095 * Note: if the guest uses a non-page-table modifying instruction
8096 * on the PDE that points to the instruction, then we will unmap
8097 * the instruction and go to an infinite loop. So, we cache the
8098 * last retried eip and the last fault address, if we meet the eip
8099 * and the address again, we can break out of the potential infinite
8102 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
8104 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8107 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8108 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8111 if (x86_page_table_writing_insn(ctxt))
8114 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
8117 vcpu->arch.last_retry_eip = ctxt->eip;
8118 vcpu->arch.last_retry_addr = cr2_or_gpa;
8120 if (!vcpu->arch.mmu->direct_map)
8121 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8123 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8128 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
8129 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
8131 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm)
8133 trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm);
8136 vcpu->arch.hflags |= HF_SMM_MASK;
8138 vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK);
8140 /* Process a latched INIT or SMI, if any. */
8141 kvm_make_request(KVM_REQ_EVENT, vcpu);
8144 * Even if KVM_SET_SREGS2 loaded PDPTRs out of band,
8145 * on SMM exit we still need to reload them from
8148 vcpu->arch.pdptrs_from_userspace = false;
8151 kvm_mmu_reset_context(vcpu);
8154 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
8163 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
8164 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
8169 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
8171 struct kvm_run *kvm_run = vcpu->run;
8173 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
8174 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW;
8175 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
8176 kvm_run->debug.arch.exception = DB_VECTOR;
8177 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8180 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
8184 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
8186 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8189 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu);
8193 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8196 * rflags is the old, "raw" value of the flags. The new value has
8197 * not been saved yet.
8199 * This is correct even for TF set by the guest, because "the
8200 * processor will not generate this exception after the instruction
8201 * that sets the TF flag".
8203 if (unlikely(rflags & X86_EFLAGS_TF))
8204 r = kvm_vcpu_do_singlestep(vcpu);
8207 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
8209 static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
8211 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
8212 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
8213 struct kvm_run *kvm_run = vcpu->run;
8214 unsigned long eip = kvm_get_linear_rip(vcpu);
8215 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8216 vcpu->arch.guest_debug_dr7,
8220 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
8221 kvm_run->debug.arch.pc = eip;
8222 kvm_run->debug.arch.exception = DB_VECTOR;
8223 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8229 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
8230 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
8231 unsigned long eip = kvm_get_linear_rip(vcpu);
8232 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8237 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
8246 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
8248 switch (ctxt->opcode_len) {
8255 case 0xe6: /* OUT */
8259 case 0x6c: /* INS */
8261 case 0x6e: /* OUTS */
8268 case 0x33: /* RDPMC */
8278 * Decode to be emulated instruction. Return EMULATION_OK if success.
8280 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
8281 void *insn, int insn_len)
8283 int r = EMULATION_OK;
8284 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8286 init_emulate_ctxt(vcpu);
8289 * We will reenter on the same instruction since we do not set
8290 * complete_userspace_io. This does not handle watchpoints yet,
8291 * those would be handled in the emulate_ops.
8293 if (!(emulation_type & EMULTYPE_SKIP) &&
8294 kvm_vcpu_check_breakpoint(vcpu, &r))
8297 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type);
8299 trace_kvm_emulate_insn_start(vcpu);
8300 ++vcpu->stat.insn_emulation;
8304 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction);
8306 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8307 int emulation_type, void *insn, int insn_len)
8310 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8311 bool writeback = true;
8312 bool write_fault_to_spt;
8314 if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len)))
8317 vcpu->arch.l1tf_flush_l1d = true;
8320 * Clear write_fault_to_shadow_pgtable here to ensure it is
8323 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
8324 vcpu->arch.write_fault_to_shadow_pgtable = false;
8326 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8327 kvm_clear_exception_queue(vcpu);
8329 r = x86_decode_emulated_instruction(vcpu, emulation_type,
8331 if (r != EMULATION_OK) {
8332 if ((emulation_type & EMULTYPE_TRAP_UD) ||
8333 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
8334 kvm_queue_exception(vcpu, UD_VECTOR);
8337 if (reexecute_instruction(vcpu, cr2_or_gpa,
8341 if (ctxt->have_exception) {
8343 * #UD should result in just EMULATION_FAILED, and trap-like
8344 * exception should not be encountered during decode.
8346 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
8347 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8348 inject_emulated_exception(vcpu);
8351 return handle_emulation_failure(vcpu, emulation_type);
8355 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
8356 !is_vmware_backdoor_opcode(ctxt)) {
8357 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8362 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for
8363 * use *only* by vendor callbacks for kvm_skip_emulated_instruction().
8364 * The caller is responsible for updating interruptibility state and
8365 * injecting single-step #DBs.
8367 if (emulation_type & EMULTYPE_SKIP) {
8368 if (ctxt->mode != X86EMUL_MODE_PROT64)
8369 ctxt->eip = (u32)ctxt->_eip;
8371 ctxt->eip = ctxt->_eip;
8373 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) {
8378 kvm_rip_write(vcpu, ctxt->eip);
8379 if (ctxt->eflags & X86_EFLAGS_RF)
8380 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
8384 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
8387 /* this is needed for vmware backdoor interface to work since it
8388 changes registers values during IO operation */
8389 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
8390 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8391 emulator_invalidate_register_cache(ctxt);
8395 if (emulation_type & EMULTYPE_PF) {
8396 /* Save the faulting GPA (cr2) in the address field */
8397 ctxt->exception.address = cr2_or_gpa;
8399 /* With shadow page tables, cr2 contains a GVA or nGPA. */
8400 if (vcpu->arch.mmu->direct_map) {
8401 ctxt->gpa_available = true;
8402 ctxt->gpa_val = cr2_or_gpa;
8405 /* Sanitize the address out of an abundance of paranoia. */
8406 ctxt->exception.address = 0;
8409 r = x86_emulate_insn(ctxt);
8411 if (r == EMULATION_INTERCEPTED)
8414 if (r == EMULATION_FAILED) {
8415 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
8419 return handle_emulation_failure(vcpu, emulation_type);
8422 if (ctxt->have_exception) {
8424 if (inject_emulated_exception(vcpu))
8426 } else if (vcpu->arch.pio.count) {
8427 if (!vcpu->arch.pio.in) {
8428 /* FIXME: return into emulator if single-stepping. */
8429 vcpu->arch.pio.count = 0;
8432 vcpu->arch.complete_userspace_io = complete_emulated_pio;
8435 } else if (vcpu->mmio_needed) {
8436 ++vcpu->stat.mmio_exits;
8438 if (!vcpu->mmio_is_write)
8441 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8442 } else if (vcpu->arch.complete_userspace_io) {
8445 } else if (r == EMULATION_RESTART)
8452 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8453 toggle_interruptibility(vcpu, ctxt->interruptibility);
8454 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8455 if (!ctxt->have_exception ||
8456 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
8457 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8458 if (ctxt->is_branch)
8459 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
8460 kvm_rip_write(vcpu, ctxt->eip);
8461 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
8462 r = kvm_vcpu_do_singlestep(vcpu);
8463 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu);
8464 __kvm_set_rflags(vcpu, ctxt->eflags);
8468 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
8469 * do nothing, and it will be requested again as soon as
8470 * the shadow expires. But we still need to check here,
8471 * because POPF has no interrupt shadow.
8473 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
8474 kvm_make_request(KVM_REQ_EVENT, vcpu);
8476 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
8481 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
8483 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
8485 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
8487 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
8488 void *insn, int insn_len)
8490 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
8492 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
8494 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
8496 vcpu->arch.pio.count = 0;
8500 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
8502 vcpu->arch.pio.count = 0;
8504 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
8507 return kvm_skip_emulated_instruction(vcpu);
8510 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
8511 unsigned short port)
8513 unsigned long val = kvm_rax_read(vcpu);
8514 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
8520 * Workaround userspace that relies on old KVM behavior of %rip being
8521 * incremented prior to exiting to userspace to handle "OUT 0x7e".
8524 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
8525 vcpu->arch.complete_userspace_io =
8526 complete_fast_pio_out_port_0x7e;
8527 kvm_skip_emulated_instruction(vcpu);
8529 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8530 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
8535 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
8539 /* We should only ever be called with arch.pio.count equal to 1 */
8540 BUG_ON(vcpu->arch.pio.count != 1);
8542 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
8543 vcpu->arch.pio.count = 0;
8547 /* For size less than 4 we merge, else we zero extend */
8548 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
8551 * Since vcpu->arch.pio.count == 1 let emulator_pio_in perform
8552 * the copy and tracing
8554 emulator_pio_in(vcpu, vcpu->arch.pio.size, vcpu->arch.pio.port, &val, 1);
8555 kvm_rax_write(vcpu, val);
8557 return kvm_skip_emulated_instruction(vcpu);
8560 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
8561 unsigned short port)
8566 /* For size less than 4 we merge, else we zero extend */
8567 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
8569 ret = emulator_pio_in(vcpu, size, port, &val, 1);
8571 kvm_rax_write(vcpu, val);
8575 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8576 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
8581 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
8586 ret = kvm_fast_pio_in(vcpu, size, port);
8588 ret = kvm_fast_pio_out(vcpu, size, port);
8589 return ret && kvm_skip_emulated_instruction(vcpu);
8591 EXPORT_SYMBOL_GPL(kvm_fast_pio);
8593 static int kvmclock_cpu_down_prep(unsigned int cpu)
8595 __this_cpu_write(cpu_tsc_khz, 0);
8599 static void tsc_khz_changed(void *data)
8601 struct cpufreq_freqs *freq = data;
8602 unsigned long khz = 0;
8606 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
8607 khz = cpufreq_quick_get(raw_smp_processor_id());
8610 __this_cpu_write(cpu_tsc_khz, khz);
8613 #ifdef CONFIG_X86_64
8614 static void kvm_hyperv_tsc_notifier(void)
8619 mutex_lock(&kvm_lock);
8620 list_for_each_entry(kvm, &vm_list, vm_list)
8621 kvm_make_mclock_inprogress_request(kvm);
8623 /* no guest entries from this point */
8624 hyperv_stop_tsc_emulation();
8626 /* TSC frequency always matches when on Hyper-V */
8627 for_each_present_cpu(cpu)
8628 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
8629 kvm_max_guest_tsc_khz = tsc_khz;
8631 list_for_each_entry(kvm, &vm_list, vm_list) {
8632 __kvm_start_pvclock_update(kvm);
8633 pvclock_update_vm_gtod_copy(kvm);
8634 kvm_end_pvclock_update(kvm);
8637 mutex_unlock(&kvm_lock);
8641 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
8644 struct kvm_vcpu *vcpu;
8649 * We allow guests to temporarily run on slowing clocks,
8650 * provided we notify them after, or to run on accelerating
8651 * clocks, provided we notify them before. Thus time never
8654 * However, we have a problem. We can't atomically update
8655 * the frequency of a given CPU from this function; it is
8656 * merely a notifier, which can be called from any CPU.
8657 * Changing the TSC frequency at arbitrary points in time
8658 * requires a recomputation of local variables related to
8659 * the TSC for each VCPU. We must flag these local variables
8660 * to be updated and be sure the update takes place with the
8661 * new frequency before any guests proceed.
8663 * Unfortunately, the combination of hotplug CPU and frequency
8664 * change creates an intractable locking scenario; the order
8665 * of when these callouts happen is undefined with respect to
8666 * CPU hotplug, and they can race with each other. As such,
8667 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
8668 * undefined; you can actually have a CPU frequency change take
8669 * place in between the computation of X and the setting of the
8670 * variable. To protect against this problem, all updates of
8671 * the per_cpu tsc_khz variable are done in an interrupt
8672 * protected IPI, and all callers wishing to update the value
8673 * must wait for a synchronous IPI to complete (which is trivial
8674 * if the caller is on the CPU already). This establishes the
8675 * necessary total order on variable updates.
8677 * Note that because a guest time update may take place
8678 * anytime after the setting of the VCPU's request bit, the
8679 * correct TSC value must be set before the request. However,
8680 * to ensure the update actually makes it to any guest which
8681 * starts running in hardware virtualization between the set
8682 * and the acquisition of the spinlock, we must also ping the
8683 * CPU after setting the request bit.
8687 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
8689 mutex_lock(&kvm_lock);
8690 list_for_each_entry(kvm, &vm_list, vm_list) {
8691 kvm_for_each_vcpu(i, vcpu, kvm) {
8692 if (vcpu->cpu != cpu)
8694 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
8695 if (vcpu->cpu != raw_smp_processor_id())
8699 mutex_unlock(&kvm_lock);
8701 if (freq->old < freq->new && send_ipi) {
8703 * We upscale the frequency. Must make the guest
8704 * doesn't see old kvmclock values while running with
8705 * the new frequency, otherwise we risk the guest sees
8706 * time go backwards.
8708 * In case we update the frequency for another cpu
8709 * (which might be in guest context) send an interrupt
8710 * to kick the cpu out of guest context. Next time
8711 * guest context is entered kvmclock will be updated,
8712 * so the guest will not see stale values.
8714 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
8718 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
8721 struct cpufreq_freqs *freq = data;
8724 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
8726 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
8729 for_each_cpu(cpu, freq->policy->cpus)
8730 __kvmclock_cpufreq_notifier(freq, cpu);
8735 static struct notifier_block kvmclock_cpufreq_notifier_block = {
8736 .notifier_call = kvmclock_cpufreq_notifier
8739 static int kvmclock_cpu_online(unsigned int cpu)
8741 tsc_khz_changed(NULL);
8745 static void kvm_timer_init(void)
8747 max_tsc_khz = tsc_khz;
8749 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
8750 #ifdef CONFIG_CPU_FREQ
8751 struct cpufreq_policy *policy;
8755 policy = cpufreq_cpu_get(cpu);
8757 if (policy->cpuinfo.max_freq)
8758 max_tsc_khz = policy->cpuinfo.max_freq;
8759 cpufreq_cpu_put(policy);
8763 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
8764 CPUFREQ_TRANSITION_NOTIFIER);
8767 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
8768 kvmclock_cpu_online, kvmclock_cpu_down_prep);
8771 #ifdef CONFIG_X86_64
8772 static void pvclock_gtod_update_fn(struct work_struct *work)
8775 struct kvm_vcpu *vcpu;
8778 mutex_lock(&kvm_lock);
8779 list_for_each_entry(kvm, &vm_list, vm_list)
8780 kvm_for_each_vcpu(i, vcpu, kvm)
8781 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
8782 atomic_set(&kvm_guest_has_master_clock, 0);
8783 mutex_unlock(&kvm_lock);
8786 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
8789 * Indirection to move queue_work() out of the tk_core.seq write held
8790 * region to prevent possible deadlocks against time accessors which
8791 * are invoked with work related locks held.
8793 static void pvclock_irq_work_fn(struct irq_work *w)
8795 queue_work(system_long_wq, &pvclock_gtod_work);
8798 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn);
8801 * Notification about pvclock gtod data update.
8803 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
8806 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
8807 struct timekeeper *tk = priv;
8809 update_pvclock_gtod(tk);
8812 * Disable master clock if host does not trust, or does not use,
8813 * TSC based clocksource. Delegate queue_work() to irq_work as
8814 * this is invoked with tk_core.seq write held.
8816 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
8817 atomic_read(&kvm_guest_has_master_clock) != 0)
8818 irq_work_queue(&pvclock_irq_work);
8822 static struct notifier_block pvclock_gtod_notifier = {
8823 .notifier_call = pvclock_gtod_notify,
8827 int kvm_arch_init(void *opaque)
8829 struct kvm_x86_init_ops *ops = opaque;
8832 if (kvm_x86_ops.hardware_enable) {
8833 pr_err("kvm: already loaded vendor module '%s'\n", kvm_x86_ops.name);
8838 if (!ops->cpu_has_kvm_support()) {
8839 pr_err_ratelimited("kvm: no hardware support for '%s'\n",
8840 ops->runtime_ops->name);
8844 if (ops->disabled_by_bios()) {
8845 pr_err_ratelimited("kvm: support for '%s' disabled by bios\n",
8846 ops->runtime_ops->name);
8852 * KVM explicitly assumes that the guest has an FPU and
8853 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
8854 * vCPU's FPU state as a fxregs_state struct.
8856 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
8857 printk(KERN_ERR "kvm: inadequate fpu\n");
8864 x86_emulator_cache = kvm_alloc_emulator_cache();
8865 if (!x86_emulator_cache) {
8866 pr_err("kvm: failed to allocate cache for x86 emulator\n");
8870 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
8871 if (!user_return_msrs) {
8872 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
8873 goto out_free_x86_emulator_cache;
8875 kvm_nr_uret_msrs = 0;
8877 r = kvm_mmu_module_init();
8879 goto out_free_percpu;
8883 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
8884 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
8885 supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
8888 if (pi_inject_timer == -1)
8889 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
8890 #ifdef CONFIG_X86_64
8891 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
8893 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
8894 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
8900 free_percpu(user_return_msrs);
8901 out_free_x86_emulator_cache:
8902 kmem_cache_destroy(x86_emulator_cache);
8907 void kvm_arch_exit(void)
8909 #ifdef CONFIG_X86_64
8910 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
8911 clear_hv_tscchange_cb();
8915 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
8916 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
8917 CPUFREQ_TRANSITION_NOTIFIER);
8918 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
8919 #ifdef CONFIG_X86_64
8920 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
8921 irq_work_sync(&pvclock_irq_work);
8922 cancel_work_sync(&pvclock_gtod_work);
8924 kvm_x86_ops.hardware_enable = NULL;
8925 kvm_mmu_module_exit();
8926 free_percpu(user_return_msrs);
8927 kmem_cache_destroy(x86_emulator_cache);
8928 #ifdef CONFIG_KVM_XEN
8929 static_key_deferred_flush(&kvm_xen_enabled);
8930 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key));
8934 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason)
8937 * The vCPU has halted, e.g. executed HLT. Update the run state if the
8938 * local APIC is in-kernel, the run loop will detect the non-runnable
8939 * state and halt the vCPU. Exit to userspace if the local APIC is
8940 * managed by userspace, in which case userspace is responsible for
8941 * handling wake events.
8943 ++vcpu->stat.halt_exits;
8944 if (lapic_in_kernel(vcpu)) {
8945 vcpu->arch.mp_state = state;
8948 vcpu->run->exit_reason = reason;
8953 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu)
8955 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
8957 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip);
8959 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
8961 int ret = kvm_skip_emulated_instruction(vcpu);
8963 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
8964 * KVM_EXIT_DEBUG here.
8966 return kvm_emulate_halt_noskip(vcpu) && ret;
8968 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
8970 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
8972 int ret = kvm_skip_emulated_instruction(vcpu);
8974 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD,
8975 KVM_EXIT_AP_RESET_HOLD) && ret;
8977 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
8979 #ifdef CONFIG_X86_64
8980 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
8981 unsigned long clock_type)
8983 struct kvm_clock_pairing clock_pairing;
8984 struct timespec64 ts;
8988 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
8989 return -KVM_EOPNOTSUPP;
8991 if (!kvm_get_walltime_and_clockread(&ts, &cycle))
8992 return -KVM_EOPNOTSUPP;
8994 clock_pairing.sec = ts.tv_sec;
8995 clock_pairing.nsec = ts.tv_nsec;
8996 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
8997 clock_pairing.flags = 0;
8998 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
9001 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
9002 sizeof(struct kvm_clock_pairing)))
9010 * kvm_pv_kick_cpu_op: Kick a vcpu.
9012 * @apicid - apicid of vcpu to be kicked.
9014 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid)
9016 struct kvm_lapic_irq lapic_irq;
9018 lapic_irq.shorthand = APIC_DEST_NOSHORT;
9019 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
9020 lapic_irq.level = 0;
9021 lapic_irq.dest_id = apicid;
9022 lapic_irq.msi_redir_hint = false;
9024 lapic_irq.delivery_mode = APIC_DM_REMRD;
9025 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
9028 bool kvm_apicv_activated(struct kvm *kvm)
9030 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
9032 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
9034 static void kvm_apicv_init(struct kvm *kvm)
9036 init_rwsem(&kvm->arch.apicv_update_lock);
9038 set_bit(APICV_INHIBIT_REASON_ABSENT,
9039 &kvm->arch.apicv_inhibit_reasons);
9041 set_bit(APICV_INHIBIT_REASON_DISABLE,
9042 &kvm->arch.apicv_inhibit_reasons);
9045 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id)
9047 struct kvm_vcpu *target = NULL;
9048 struct kvm_apic_map *map;
9050 vcpu->stat.directed_yield_attempted++;
9052 if (single_task_running())
9056 map = rcu_dereference(vcpu->kvm->arch.apic_map);
9058 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
9059 target = map->phys_map[dest_id]->vcpu;
9063 if (!target || !READ_ONCE(target->ready))
9066 /* Ignore requests to yield to self */
9070 if (kvm_vcpu_yield_to(target) <= 0)
9073 vcpu->stat.directed_yield_successful++;
9079 static int complete_hypercall_exit(struct kvm_vcpu *vcpu)
9081 u64 ret = vcpu->run->hypercall.ret;
9083 if (!is_64_bit_mode(vcpu))
9085 kvm_rax_write(vcpu, ret);
9086 ++vcpu->stat.hypercalls;
9087 return kvm_skip_emulated_instruction(vcpu);
9090 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
9092 unsigned long nr, a0, a1, a2, a3, ret;
9095 if (kvm_xen_hypercall_enabled(vcpu->kvm))
9096 return kvm_xen_hypercall(vcpu);
9098 if (kvm_hv_hypercall_enabled(vcpu))
9099 return kvm_hv_hypercall(vcpu);
9101 nr = kvm_rax_read(vcpu);
9102 a0 = kvm_rbx_read(vcpu);
9103 a1 = kvm_rcx_read(vcpu);
9104 a2 = kvm_rdx_read(vcpu);
9105 a3 = kvm_rsi_read(vcpu);
9107 trace_kvm_hypercall(nr, a0, a1, a2, a3);
9109 op_64_bit = is_64_bit_hypercall(vcpu);
9118 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) {
9126 case KVM_HC_VAPIC_POLL_IRQ:
9129 case KVM_HC_KICK_CPU:
9130 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
9133 kvm_pv_kick_cpu_op(vcpu->kvm, a1);
9134 kvm_sched_yield(vcpu, a1);
9137 #ifdef CONFIG_X86_64
9138 case KVM_HC_CLOCK_PAIRING:
9139 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
9142 case KVM_HC_SEND_IPI:
9143 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
9146 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
9148 case KVM_HC_SCHED_YIELD:
9149 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
9152 kvm_sched_yield(vcpu, a0);
9155 case KVM_HC_MAP_GPA_RANGE: {
9156 u64 gpa = a0, npages = a1, attrs = a2;
9159 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE)))
9162 if (!PAGE_ALIGNED(gpa) || !npages ||
9163 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) {
9168 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL;
9169 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE;
9170 vcpu->run->hypercall.args[0] = gpa;
9171 vcpu->run->hypercall.args[1] = npages;
9172 vcpu->run->hypercall.args[2] = attrs;
9173 vcpu->run->hypercall.longmode = op_64_bit;
9174 vcpu->arch.complete_userspace_io = complete_hypercall_exit;
9184 kvm_rax_write(vcpu, ret);
9186 ++vcpu->stat.hypercalls;
9187 return kvm_skip_emulated_instruction(vcpu);
9189 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
9191 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
9193 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
9194 char instruction[3];
9195 unsigned long rip = kvm_rip_read(vcpu);
9197 static_call(kvm_x86_patch_hypercall)(vcpu, instruction);
9199 return emulator_write_emulated(ctxt, rip, instruction, 3,
9203 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
9205 return vcpu->run->request_interrupt_window &&
9206 likely(!pic_in_kernel(vcpu->kvm));
9209 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
9211 struct kvm_run *kvm_run = vcpu->run;
9213 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu);
9214 kvm_run->cr8 = kvm_get_cr8(vcpu);
9215 kvm_run->apic_base = kvm_get_apic_base(vcpu);
9218 * The call to kvm_ready_for_interrupt_injection() may end up in
9219 * kvm_xen_has_interrupt() which may require the srcu lock to be
9220 * held, to protect against changes in the vcpu_info address.
9222 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
9223 kvm_run->ready_for_interrupt_injection =
9224 pic_in_kernel(vcpu->kvm) ||
9225 kvm_vcpu_ready_for_interrupt_injection(vcpu);
9226 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
9229 kvm_run->flags |= KVM_RUN_X86_SMM;
9232 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
9236 if (!kvm_x86_ops.update_cr8_intercept)
9239 if (!lapic_in_kernel(vcpu))
9242 if (vcpu->arch.apicv_active)
9245 if (!vcpu->arch.apic->vapic_addr)
9246 max_irr = kvm_lapic_find_highest_irr(vcpu);
9253 tpr = kvm_lapic_get_cr8(vcpu);
9255 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr);
9259 int kvm_check_nested_events(struct kvm_vcpu *vcpu)
9261 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
9262 kvm_x86_ops.nested_ops->triple_fault(vcpu);
9266 return kvm_x86_ops.nested_ops->check_events(vcpu);
9269 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
9271 if (vcpu->arch.exception.error_code && !is_protmode(vcpu))
9272 vcpu->arch.exception.error_code = false;
9273 static_call(kvm_x86_queue_exception)(vcpu);
9276 static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
9279 bool can_inject = true;
9281 /* try to reinject previous events if any */
9283 if (vcpu->arch.exception.injected) {
9284 kvm_inject_exception(vcpu);
9288 * Do not inject an NMI or interrupt if there is a pending
9289 * exception. Exceptions and interrupts are recognized at
9290 * instruction boundaries, i.e. the start of an instruction.
9291 * Trap-like exceptions, e.g. #DB, have higher priority than
9292 * NMIs and interrupts, i.e. traps are recognized before an
9293 * NMI/interrupt that's pending on the same instruction.
9294 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
9295 * priority, but are only generated (pended) during instruction
9296 * execution, i.e. a pending fault-like exception means the
9297 * fault occurred on the *previous* instruction and must be
9298 * serviced prior to recognizing any new events in order to
9299 * fully complete the previous instruction.
9301 else if (!vcpu->arch.exception.pending) {
9302 if (vcpu->arch.nmi_injected) {
9303 static_call(kvm_x86_inject_nmi)(vcpu);
9305 } else if (vcpu->arch.interrupt.injected) {
9306 static_call(kvm_x86_inject_irq)(vcpu);
9311 WARN_ON_ONCE(vcpu->arch.exception.injected &&
9312 vcpu->arch.exception.pending);
9315 * Call check_nested_events() even if we reinjected a previous event
9316 * in order for caller to determine if it should require immediate-exit
9317 * from L2 to L1 due to pending L1 events which require exit
9320 if (is_guest_mode(vcpu)) {
9321 r = kvm_check_nested_events(vcpu);
9326 /* try to inject new event if pending */
9327 if (vcpu->arch.exception.pending) {
9328 trace_kvm_inj_exception(vcpu->arch.exception.nr,
9329 vcpu->arch.exception.has_error_code,
9330 vcpu->arch.exception.error_code);
9332 vcpu->arch.exception.pending = false;
9333 vcpu->arch.exception.injected = true;
9335 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
9336 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
9339 if (vcpu->arch.exception.nr == DB_VECTOR) {
9340 kvm_deliver_exception_payload(vcpu);
9341 if (vcpu->arch.dr7 & DR7_GD) {
9342 vcpu->arch.dr7 &= ~DR7_GD;
9343 kvm_update_dr7(vcpu);
9347 kvm_inject_exception(vcpu);
9351 /* Don't inject interrupts if the user asked to avoid doing so */
9352 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ)
9356 * Finally, inject interrupt events. If an event cannot be injected
9357 * due to architectural conditions (e.g. IF=0) a window-open exit
9358 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
9359 * and can architecturally be injected, but we cannot do it right now:
9360 * an interrupt could have arrived just now and we have to inject it
9361 * as a vmexit, or there could already an event in the queue, which is
9362 * indicated by can_inject. In that case we request an immediate exit
9363 * in order to make progress and get back here for another iteration.
9364 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
9366 if (vcpu->arch.smi_pending) {
9367 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY;
9371 vcpu->arch.smi_pending = false;
9372 ++vcpu->arch.smi_count;
9376 static_call(kvm_x86_enable_smi_window)(vcpu);
9379 if (vcpu->arch.nmi_pending) {
9380 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY;
9384 --vcpu->arch.nmi_pending;
9385 vcpu->arch.nmi_injected = true;
9386 static_call(kvm_x86_inject_nmi)(vcpu);
9388 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0);
9390 if (vcpu->arch.nmi_pending)
9391 static_call(kvm_x86_enable_nmi_window)(vcpu);
9394 if (kvm_cpu_has_injectable_intr(vcpu)) {
9395 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY;
9399 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
9400 static_call(kvm_x86_inject_irq)(vcpu);
9401 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
9403 if (kvm_cpu_has_injectable_intr(vcpu))
9404 static_call(kvm_x86_enable_irq_window)(vcpu);
9407 if (is_guest_mode(vcpu) &&
9408 kvm_x86_ops.nested_ops->hv_timer_pending &&
9409 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
9410 *req_immediate_exit = true;
9412 WARN_ON(vcpu->arch.exception.pending);
9417 *req_immediate_exit = true;
9423 static void process_nmi(struct kvm_vcpu *vcpu)
9428 * x86 is limited to one NMI running, and one NMI pending after it.
9429 * If an NMI is already in progress, limit further NMIs to just one.
9430 * Otherwise, allow two (and we'll inject the first one immediately).
9432 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected)
9435 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
9436 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
9437 kvm_make_request(KVM_REQ_EVENT, vcpu);
9440 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
9443 flags |= seg->g << 23;
9444 flags |= seg->db << 22;
9445 flags |= seg->l << 21;
9446 flags |= seg->avl << 20;
9447 flags |= seg->present << 15;
9448 flags |= seg->dpl << 13;
9449 flags |= seg->s << 12;
9450 flags |= seg->type << 8;
9454 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
9456 struct kvm_segment seg;
9459 kvm_get_segment(vcpu, &seg, n);
9460 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
9463 offset = 0x7f84 + n * 12;
9465 offset = 0x7f2c + (n - 3) * 12;
9467 put_smstate(u32, buf, offset + 8, seg.base);
9468 put_smstate(u32, buf, offset + 4, seg.limit);
9469 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
9472 #ifdef CONFIG_X86_64
9473 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
9475 struct kvm_segment seg;
9479 kvm_get_segment(vcpu, &seg, n);
9480 offset = 0x7e00 + n * 16;
9482 flags = enter_smm_get_segment_flags(&seg) >> 8;
9483 put_smstate(u16, buf, offset, seg.selector);
9484 put_smstate(u16, buf, offset + 2, flags);
9485 put_smstate(u32, buf, offset + 4, seg.limit);
9486 put_smstate(u64, buf, offset + 8, seg.base);
9490 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
9493 struct kvm_segment seg;
9497 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
9498 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
9499 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
9500 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
9502 for (i = 0; i < 8; i++)
9503 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i));
9505 kvm_get_dr(vcpu, 6, &val);
9506 put_smstate(u32, buf, 0x7fcc, (u32)val);
9507 kvm_get_dr(vcpu, 7, &val);
9508 put_smstate(u32, buf, 0x7fc8, (u32)val);
9510 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
9511 put_smstate(u32, buf, 0x7fc4, seg.selector);
9512 put_smstate(u32, buf, 0x7f64, seg.base);
9513 put_smstate(u32, buf, 0x7f60, seg.limit);
9514 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
9516 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
9517 put_smstate(u32, buf, 0x7fc0, seg.selector);
9518 put_smstate(u32, buf, 0x7f80, seg.base);
9519 put_smstate(u32, buf, 0x7f7c, seg.limit);
9520 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
9522 static_call(kvm_x86_get_gdt)(vcpu, &dt);
9523 put_smstate(u32, buf, 0x7f74, dt.address);
9524 put_smstate(u32, buf, 0x7f70, dt.size);
9526 static_call(kvm_x86_get_idt)(vcpu, &dt);
9527 put_smstate(u32, buf, 0x7f58, dt.address);
9528 put_smstate(u32, buf, 0x7f54, dt.size);
9530 for (i = 0; i < 6; i++)
9531 enter_smm_save_seg_32(vcpu, buf, i);
9533 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
9536 put_smstate(u32, buf, 0x7efc, 0x00020000);
9537 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
9540 #ifdef CONFIG_X86_64
9541 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
9544 struct kvm_segment seg;
9548 for (i = 0; i < 16; i++)
9549 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i));
9551 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
9552 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
9554 kvm_get_dr(vcpu, 6, &val);
9555 put_smstate(u64, buf, 0x7f68, val);
9556 kvm_get_dr(vcpu, 7, &val);
9557 put_smstate(u64, buf, 0x7f60, val);
9559 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
9560 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
9561 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
9563 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
9566 put_smstate(u32, buf, 0x7efc, 0x00020064);
9568 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
9570 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
9571 put_smstate(u16, buf, 0x7e90, seg.selector);
9572 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
9573 put_smstate(u32, buf, 0x7e94, seg.limit);
9574 put_smstate(u64, buf, 0x7e98, seg.base);
9576 static_call(kvm_x86_get_idt)(vcpu, &dt);
9577 put_smstate(u32, buf, 0x7e84, dt.size);
9578 put_smstate(u64, buf, 0x7e88, dt.address);
9580 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
9581 put_smstate(u16, buf, 0x7e70, seg.selector);
9582 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
9583 put_smstate(u32, buf, 0x7e74, seg.limit);
9584 put_smstate(u64, buf, 0x7e78, seg.base);
9586 static_call(kvm_x86_get_gdt)(vcpu, &dt);
9587 put_smstate(u32, buf, 0x7e64, dt.size);
9588 put_smstate(u64, buf, 0x7e68, dt.address);
9590 for (i = 0; i < 6; i++)
9591 enter_smm_save_seg_64(vcpu, buf, i);
9595 static void enter_smm(struct kvm_vcpu *vcpu)
9597 struct kvm_segment cs, ds;
9602 memset(buf, 0, 512);
9603 #ifdef CONFIG_X86_64
9604 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
9605 enter_smm_save_state_64(vcpu, buf);
9608 enter_smm_save_state_32(vcpu, buf);
9611 * Give enter_smm() a chance to make ISA-specific changes to the vCPU
9612 * state (e.g. leave guest mode) after we've saved the state into the
9613 * SMM state-save area.
9615 static_call(kvm_x86_enter_smm)(vcpu, buf);
9617 kvm_smm_changed(vcpu, true);
9618 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
9620 if (static_call(kvm_x86_get_nmi_mask)(vcpu))
9621 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
9623 static_call(kvm_x86_set_nmi_mask)(vcpu, true);
9625 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
9626 kvm_rip_write(vcpu, 0x8000);
9628 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
9629 static_call(kvm_x86_set_cr0)(vcpu, cr0);
9630 vcpu->arch.cr0 = cr0;
9632 static_call(kvm_x86_set_cr4)(vcpu, 0);
9634 /* Undocumented: IDT limit is set to zero on entry to SMM. */
9635 dt.address = dt.size = 0;
9636 static_call(kvm_x86_set_idt)(vcpu, &dt);
9638 kvm_set_dr(vcpu, 7, DR7_FIXED_1);
9640 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
9641 cs.base = vcpu->arch.smbase;
9646 cs.limit = ds.limit = 0xffffffff;
9647 cs.type = ds.type = 0x3;
9648 cs.dpl = ds.dpl = 0;
9653 cs.avl = ds.avl = 0;
9654 cs.present = ds.present = 1;
9655 cs.unusable = ds.unusable = 0;
9656 cs.padding = ds.padding = 0;
9658 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9659 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
9660 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
9661 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
9662 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
9663 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
9665 #ifdef CONFIG_X86_64
9666 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
9667 static_call(kvm_x86_set_efer)(vcpu, 0);
9670 kvm_update_cpuid_runtime(vcpu);
9671 kvm_mmu_reset_context(vcpu);
9674 static void process_smi(struct kvm_vcpu *vcpu)
9676 vcpu->arch.smi_pending = true;
9677 kvm_make_request(KVM_REQ_EVENT, vcpu);
9680 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
9681 unsigned long *vcpu_bitmap)
9683 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap);
9686 void kvm_make_scan_ioapic_request(struct kvm *kvm)
9688 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
9691 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
9695 if (!lapic_in_kernel(vcpu))
9698 down_read(&vcpu->kvm->arch.apicv_update_lock);
9700 activate = kvm_apicv_activated(vcpu->kvm);
9701 if (vcpu->arch.apicv_active == activate)
9704 vcpu->arch.apicv_active = activate;
9705 kvm_apic_update_apicv(vcpu);
9706 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
9709 * When APICv gets disabled, we may still have injected interrupts
9710 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was
9711 * still active when the interrupt got accepted. Make sure
9712 * inject_pending_event() is called to check for that.
9714 if (!vcpu->arch.apicv_active)
9715 kvm_make_request(KVM_REQ_EVENT, vcpu);
9718 up_read(&vcpu->kvm->arch.apicv_update_lock);
9720 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
9722 void __kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
9724 unsigned long old, new;
9726 lockdep_assert_held_write(&kvm->arch.apicv_update_lock);
9728 if (!static_call(kvm_x86_check_apicv_inhibit_reasons)(bit))
9731 old = new = kvm->arch.apicv_inhibit_reasons;
9734 __clear_bit(bit, &new);
9736 __set_bit(bit, &new);
9738 if (!!old != !!new) {
9739 trace_kvm_apicv_update_request(activate, bit);
9741 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid
9742 * false positives in the sanity check WARN in svm_vcpu_run().
9743 * This task will wait for all vCPUs to ack the kick IRQ before
9744 * updating apicv_inhibit_reasons, and all other vCPUs will
9745 * block on acquiring apicv_update_lock so that vCPUs can't
9746 * redo svm_vcpu_run() without seeing the new inhibit state.
9748 * Note, holding apicv_update_lock and taking it in the read
9749 * side (handling the request) also prevents other vCPUs from
9750 * servicing the request with a stale apicv_inhibit_reasons.
9752 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
9753 kvm->arch.apicv_inhibit_reasons = new;
9755 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE);
9756 kvm_zap_gfn_range(kvm, gfn, gfn+1);
9759 kvm->arch.apicv_inhibit_reasons = new;
9762 void kvm_request_apicv_update(struct kvm *kvm, bool activate, ulong bit)
9767 down_write(&kvm->arch.apicv_update_lock);
9768 __kvm_request_apicv_update(kvm, activate, bit);
9769 up_write(&kvm->arch.apicv_update_lock);
9771 EXPORT_SYMBOL_GPL(kvm_request_apicv_update);
9773 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
9775 if (!kvm_apic_present(vcpu))
9778 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
9780 if (irqchip_split(vcpu->kvm))
9781 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
9783 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
9784 if (ioapic_in_kernel(vcpu->kvm))
9785 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
9788 if (is_guest_mode(vcpu))
9789 vcpu->arch.load_eoi_exitmap_pending = true;
9791 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
9794 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
9796 u64 eoi_exit_bitmap[4];
9798 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
9801 if (to_hv_vcpu(vcpu)) {
9802 bitmap_or((ulong *)eoi_exit_bitmap,
9803 vcpu->arch.ioapic_handled_vectors,
9804 to_hv_synic(vcpu)->vec_bitmap, 256);
9805 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap);
9809 static_call_cond(kvm_x86_load_eoi_exitmap)(
9810 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors);
9813 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
9814 unsigned long start, unsigned long end)
9816 unsigned long apic_address;
9819 * The physical address of apic access page is stored in the VMCS.
9820 * Update it when it becomes invalid.
9822 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
9823 if (start <= apic_address && apic_address < end)
9824 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
9827 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
9829 if (!lapic_in_kernel(vcpu))
9832 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu);
9835 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
9837 smp_send_reschedule(vcpu->cpu);
9839 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
9842 * Returns 1 to let vcpu_run() continue the guest execution loop without
9843 * exiting to the userspace. Otherwise, the value will be returned to the
9846 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
9850 dm_request_for_irq_injection(vcpu) &&
9851 kvm_cpu_accept_dm_intr(vcpu);
9852 fastpath_t exit_fastpath;
9854 bool req_immediate_exit = false;
9856 /* Forbid vmenter if vcpu dirty ring is soft-full */
9857 if (unlikely(vcpu->kvm->dirty_ring_size &&
9858 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) {
9859 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL;
9860 trace_kvm_dirty_ring_exit(vcpu);
9865 if (kvm_request_pending(vcpu)) {
9866 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) {
9870 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
9871 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
9876 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
9877 kvm_mmu_unload(vcpu);
9878 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
9879 __kvm_migrate_timers(vcpu);
9880 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
9881 kvm_update_masterclock(vcpu->kvm);
9882 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
9883 kvm_gen_kvmclock_update(vcpu);
9884 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
9885 r = kvm_guest_time_update(vcpu);
9889 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
9890 kvm_mmu_sync_roots(vcpu);
9891 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
9892 kvm_mmu_load_pgd(vcpu);
9893 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
9894 kvm_vcpu_flush_tlb_all(vcpu);
9896 /* Flushing all ASIDs flushes the current ASID... */
9897 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
9899 kvm_service_local_tlb_flush_requests(vcpu);
9901 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
9902 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
9906 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
9907 if (is_guest_mode(vcpu)) {
9908 kvm_x86_ops.nested_ops->triple_fault(vcpu);
9910 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
9911 vcpu->mmio_needed = 0;
9916 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
9917 /* Page is swapped out. Do synthetic halt */
9918 vcpu->arch.apf.halted = true;
9922 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
9923 record_steal_time(vcpu);
9924 if (kvm_check_request(KVM_REQ_SMI, vcpu))
9926 if (kvm_check_request(KVM_REQ_NMI, vcpu))
9928 if (kvm_check_request(KVM_REQ_PMU, vcpu))
9929 kvm_pmu_handle_event(vcpu);
9930 if (kvm_check_request(KVM_REQ_PMI, vcpu))
9931 kvm_pmu_deliver_pmi(vcpu);
9932 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
9933 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
9934 if (test_bit(vcpu->arch.pending_ioapic_eoi,
9935 vcpu->arch.ioapic_handled_vectors)) {
9936 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
9937 vcpu->run->eoi.vector =
9938 vcpu->arch.pending_ioapic_eoi;
9943 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
9944 vcpu_scan_ioapic(vcpu);
9945 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
9946 vcpu_load_eoi_exitmap(vcpu);
9947 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
9948 kvm_vcpu_reload_apic_access_page(vcpu);
9949 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
9950 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
9951 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
9955 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
9956 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
9957 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
9961 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
9962 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
9964 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
9965 vcpu->run->hyperv = hv_vcpu->exit;
9971 * KVM_REQ_HV_STIMER has to be processed after
9972 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
9973 * depend on the guest clock being up-to-date
9975 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
9976 kvm_hv_process_stimers(vcpu);
9977 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
9978 kvm_vcpu_update_apicv(vcpu);
9979 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
9980 kvm_check_async_pf_completion(vcpu);
9981 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
9982 static_call(kvm_x86_msr_filter_changed)(vcpu);
9984 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
9985 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu);
9988 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win ||
9989 kvm_xen_has_interrupt(vcpu)) {
9990 ++vcpu->stat.req_event;
9991 r = kvm_apic_accept_events(vcpu);
9996 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
10001 r = inject_pending_event(vcpu, &req_immediate_exit);
10007 static_call(kvm_x86_enable_irq_window)(vcpu);
10009 if (kvm_lapic_enabled(vcpu)) {
10010 update_cr8_intercept(vcpu);
10011 kvm_lapic_sync_to_vapic(vcpu);
10015 r = kvm_mmu_reload(vcpu);
10017 goto cancel_injection;
10022 static_call(kvm_x86_prepare_switch_to_guest)(vcpu);
10025 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
10026 * IPI are then delayed after guest entry, which ensures that they
10027 * result in virtual interrupt delivery.
10029 local_irq_disable();
10031 /* Store vcpu->apicv_active before vcpu->mode. */
10032 smp_store_release(&vcpu->mode, IN_GUEST_MODE);
10034 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
10037 * 1) We should set ->mode before checking ->requests. Please see
10038 * the comment in kvm_vcpu_exiting_guest_mode().
10040 * 2) For APICv, we should set ->mode before checking PID.ON. This
10041 * pairs with the memory barrier implicit in pi_test_and_set_on
10042 * (see vmx_deliver_posted_interrupt).
10044 * 3) This also orders the write to mode from any reads to the page
10045 * tables done while the VCPU is running. Please see the comment
10046 * in kvm_flush_remote_tlbs.
10048 smp_mb__after_srcu_read_unlock();
10051 * Process pending posted interrupts to handle the case where the
10052 * notification IRQ arrived in the host, or was never sent (because the
10053 * target vCPU wasn't running). Do this regardless of the vCPU's APICv
10054 * status, KVM doesn't update assigned devices when APICv is inhibited,
10055 * i.e. they can post interrupts even if APICv is temporarily disabled.
10057 if (kvm_lapic_enabled(vcpu))
10058 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10060 if (kvm_vcpu_exit_request(vcpu)) {
10061 vcpu->mode = OUTSIDE_GUEST_MODE;
10063 local_irq_enable();
10065 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
10067 goto cancel_injection;
10070 if (req_immediate_exit) {
10071 kvm_make_request(KVM_REQ_EVENT, vcpu);
10072 static_call(kvm_x86_request_immediate_exit)(vcpu);
10075 fpregs_assert_state_consistent();
10076 if (test_thread_flag(TIF_NEED_FPU_LOAD))
10077 switch_fpu_return();
10079 if (vcpu->arch.guest_fpu.xfd_err)
10080 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);
10082 if (unlikely(vcpu->arch.switch_db_regs)) {
10083 set_debugreg(0, 7);
10084 set_debugreg(vcpu->arch.eff_db[0], 0);
10085 set_debugreg(vcpu->arch.eff_db[1], 1);
10086 set_debugreg(vcpu->arch.eff_db[2], 2);
10087 set_debugreg(vcpu->arch.eff_db[3], 3);
10088 } else if (unlikely(hw_breakpoint_active())) {
10089 set_debugreg(0, 7);
10092 guest_timing_enter_irqoff();
10096 * Assert that vCPU vs. VM APICv state is consistent. An APICv
10097 * update must kick and wait for all vCPUs before toggling the
10098 * per-VM state, and responsing vCPUs must wait for the update
10099 * to complete before servicing KVM_REQ_APICV_UPDATE.
10101 WARN_ON_ONCE(kvm_apicv_activated(vcpu->kvm) != kvm_vcpu_apicv_active(vcpu));
10103 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu);
10104 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST))
10107 if (kvm_lapic_enabled(vcpu))
10108 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10110 if (unlikely(kvm_vcpu_exit_request(vcpu))) {
10111 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
10117 * Do this here before restoring debug registers on the host. And
10118 * since we do this before handling the vmexit, a DR access vmexit
10119 * can (a) read the correct value of the debug registers, (b) set
10120 * KVM_DEBUGREG_WONT_EXIT again.
10122 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
10123 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
10124 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu);
10125 kvm_update_dr0123(vcpu);
10126 kvm_update_dr7(vcpu);
10130 * If the guest has used debug registers, at least dr7
10131 * will be disabled while returning to the host.
10132 * If we don't have active breakpoints in the host, we don't
10133 * care about the messed up debug address registers. But if
10134 * we have some of them active, restore the old state.
10136 if (hw_breakpoint_active())
10137 hw_breakpoint_restore();
10139 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
10140 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
10142 vcpu->mode = OUTSIDE_GUEST_MODE;
10146 * Sync xfd before calling handle_exit_irqoff() which may
10147 * rely on the fact that guest_fpu::xfd is up-to-date (e.g.
10148 * in #NM irqoff handler).
10150 if (vcpu->arch.xfd_no_write_intercept)
10151 fpu_sync_guest_vmexit_xfd_state();
10153 static_call(kvm_x86_handle_exit_irqoff)(vcpu);
10155 if (vcpu->arch.guest_fpu.xfd_err)
10156 wrmsrl(MSR_IA32_XFD_ERR, 0);
10159 * Consume any pending interrupts, including the possible source of
10160 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
10161 * An instruction is required after local_irq_enable() to fully unblock
10162 * interrupts on processors that implement an interrupt shadow, the
10163 * stat.exits increment will do nicely.
10165 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ);
10166 local_irq_enable();
10167 ++vcpu->stat.exits;
10168 local_irq_disable();
10169 kvm_after_interrupt(vcpu);
10172 * Wait until after servicing IRQs to account guest time so that any
10173 * ticks that occurred while running the guest are properly accounted
10174 * to the guest. Waiting until IRQs are enabled degrades the accuracy
10175 * of accounting via context tracking, but the loss of accuracy is
10176 * acceptable for all known use cases.
10178 guest_timing_exit_irqoff();
10180 if (lapic_in_kernel(vcpu)) {
10181 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
10182 if (delta != S64_MIN) {
10183 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
10184 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
10188 local_irq_enable();
10191 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
10194 * Profile KVM exit RIPs:
10196 if (unlikely(prof_on == KVM_PROFILING)) {
10197 unsigned long rip = kvm_rip_read(vcpu);
10198 profile_hit(KVM_PROFILING, (void *)rip);
10201 if (unlikely(vcpu->arch.tsc_always_catchup))
10202 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10204 if (vcpu->arch.apic_attention)
10205 kvm_lapic_sync_from_vapic(vcpu);
10207 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath);
10211 if (req_immediate_exit)
10212 kvm_make_request(KVM_REQ_EVENT, vcpu);
10213 static_call(kvm_x86_cancel_injection)(vcpu);
10214 if (unlikely(vcpu->arch.apic_attention))
10215 kvm_lapic_sync_from_vapic(vcpu);
10220 static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
10224 if (!kvm_arch_vcpu_runnable(vcpu)) {
10226 * Switch to the software timer before halt-polling/blocking as
10227 * the guest's timer may be a break event for the vCPU, and the
10228 * hypervisor timer runs only when the CPU is in guest mode.
10229 * Switch before halt-polling so that KVM recognizes an expired
10230 * timer before blocking.
10232 hv_timer = kvm_lapic_hv_timer_in_use(vcpu);
10234 kvm_lapic_switch_to_sw_timer(vcpu);
10236 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
10237 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10238 kvm_vcpu_halt(vcpu);
10240 kvm_vcpu_block(vcpu);
10241 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
10244 kvm_lapic_switch_to_hv_timer(vcpu);
10246 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
10250 if (kvm_apic_accept_events(vcpu) < 0)
10252 switch(vcpu->arch.mp_state) {
10253 case KVM_MP_STATE_HALTED:
10254 case KVM_MP_STATE_AP_RESET_HOLD:
10255 vcpu->arch.pv.pv_unhalted = false;
10256 vcpu->arch.mp_state =
10257 KVM_MP_STATE_RUNNABLE;
10259 case KVM_MP_STATE_RUNNABLE:
10260 vcpu->arch.apf.halted = false;
10262 case KVM_MP_STATE_INIT_RECEIVED:
10270 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
10272 if (is_guest_mode(vcpu))
10273 kvm_check_nested_events(vcpu);
10275 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
10276 !vcpu->arch.apf.halted);
10279 static int vcpu_run(struct kvm_vcpu *vcpu)
10282 struct kvm *kvm = vcpu->kvm;
10284 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
10285 vcpu->arch.l1tf_flush_l1d = true;
10288 if (kvm_vcpu_running(vcpu)) {
10289 r = vcpu_enter_guest(vcpu);
10291 r = vcpu_block(kvm, vcpu);
10297 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu);
10298 if (kvm_cpu_has_pending_timer(vcpu))
10299 kvm_inject_pending_timer_irqs(vcpu);
10301 if (dm_request_for_irq_injection(vcpu) &&
10302 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
10304 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
10305 ++vcpu->stat.request_irq_exits;
10309 if (__xfer_to_guest_mode_work_pending()) {
10310 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
10311 r = xfer_to_guest_mode_handle_work(vcpu);
10314 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
10318 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
10323 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
10327 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
10328 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
10329 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
10333 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
10335 BUG_ON(!vcpu->arch.pio.count);
10337 return complete_emulated_io(vcpu);
10341 * Implements the following, as a state machine:
10344 * for each fragment
10345 * for each mmio piece in the fragment
10352 * for each fragment
10353 * for each mmio piece in the fragment
10358 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
10360 struct kvm_run *run = vcpu->run;
10361 struct kvm_mmio_fragment *frag;
10364 BUG_ON(!vcpu->mmio_needed);
10366 /* Complete previous fragment */
10367 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
10368 len = min(8u, frag->len);
10369 if (!vcpu->mmio_is_write)
10370 memcpy(frag->data, run->mmio.data, len);
10372 if (frag->len <= 8) {
10373 /* Switch to the next fragment. */
10375 vcpu->mmio_cur_fragment++;
10377 /* Go forward to the next mmio piece. */
10383 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
10384 vcpu->mmio_needed = 0;
10386 /* FIXME: return into emulator if single-stepping. */
10387 if (vcpu->mmio_is_write)
10389 vcpu->mmio_read_completed = 1;
10390 return complete_emulated_io(vcpu);
10393 run->exit_reason = KVM_EXIT_MMIO;
10394 run->mmio.phys_addr = frag->gpa;
10395 if (vcpu->mmio_is_write)
10396 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
10397 run->mmio.len = min(8u, frag->len);
10398 run->mmio.is_write = vcpu->mmio_is_write;
10399 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
10403 /* Swap (qemu) user FPU context for the guest FPU context. */
10404 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
10406 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */
10407 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true);
10411 /* When vcpu_run ends, restore user space FPU context. */
10412 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
10414 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false);
10415 ++vcpu->stat.fpu_reload;
10419 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
10421 struct kvm_run *kvm_run = vcpu->run;
10425 kvm_sigset_activate(vcpu);
10426 kvm_run->flags = 0;
10427 kvm_load_guest_fpu(vcpu);
10429 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
10430 if (kvm_run->immediate_exit) {
10435 * It should be impossible for the hypervisor timer to be in
10436 * use before KVM has ever run the vCPU.
10438 WARN_ON_ONCE(kvm_lapic_hv_timer_in_use(vcpu));
10439 kvm_vcpu_block(vcpu);
10440 if (kvm_apic_accept_events(vcpu) < 0) {
10444 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
10446 if (signal_pending(current)) {
10448 kvm_run->exit_reason = KVM_EXIT_INTR;
10449 ++vcpu->stat.signal_exits;
10454 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) ||
10455 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) {
10460 if (kvm_run->kvm_dirty_regs) {
10461 r = sync_regs(vcpu);
10466 /* re-sync apic's tpr */
10467 if (!lapic_in_kernel(vcpu)) {
10468 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
10474 if (unlikely(vcpu->arch.complete_userspace_io)) {
10475 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
10476 vcpu->arch.complete_userspace_io = NULL;
10481 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
10483 if (kvm_run->immediate_exit) {
10488 r = static_call(kvm_x86_vcpu_pre_run)(vcpu);
10492 r = vcpu_run(vcpu);
10495 kvm_put_guest_fpu(vcpu);
10496 if (kvm_run->kvm_valid_regs)
10498 post_kvm_run_save(vcpu);
10499 kvm_sigset_deactivate(vcpu);
10505 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10507 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
10509 * We are here if userspace calls get_regs() in the middle of
10510 * instruction emulation. Registers state needs to be copied
10511 * back from emulation context to vcpu. Userspace shouldn't do
10512 * that usually, but some bad designed PV devices (vmware
10513 * backdoor interface) need this to work
10515 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
10516 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
10518 regs->rax = kvm_rax_read(vcpu);
10519 regs->rbx = kvm_rbx_read(vcpu);
10520 regs->rcx = kvm_rcx_read(vcpu);
10521 regs->rdx = kvm_rdx_read(vcpu);
10522 regs->rsi = kvm_rsi_read(vcpu);
10523 regs->rdi = kvm_rdi_read(vcpu);
10524 regs->rsp = kvm_rsp_read(vcpu);
10525 regs->rbp = kvm_rbp_read(vcpu);
10526 #ifdef CONFIG_X86_64
10527 regs->r8 = kvm_r8_read(vcpu);
10528 regs->r9 = kvm_r9_read(vcpu);
10529 regs->r10 = kvm_r10_read(vcpu);
10530 regs->r11 = kvm_r11_read(vcpu);
10531 regs->r12 = kvm_r12_read(vcpu);
10532 regs->r13 = kvm_r13_read(vcpu);
10533 regs->r14 = kvm_r14_read(vcpu);
10534 regs->r15 = kvm_r15_read(vcpu);
10537 regs->rip = kvm_rip_read(vcpu);
10538 regs->rflags = kvm_get_rflags(vcpu);
10541 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10544 __get_regs(vcpu, regs);
10549 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10551 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
10552 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
10554 kvm_rax_write(vcpu, regs->rax);
10555 kvm_rbx_write(vcpu, regs->rbx);
10556 kvm_rcx_write(vcpu, regs->rcx);
10557 kvm_rdx_write(vcpu, regs->rdx);
10558 kvm_rsi_write(vcpu, regs->rsi);
10559 kvm_rdi_write(vcpu, regs->rdi);
10560 kvm_rsp_write(vcpu, regs->rsp);
10561 kvm_rbp_write(vcpu, regs->rbp);
10562 #ifdef CONFIG_X86_64
10563 kvm_r8_write(vcpu, regs->r8);
10564 kvm_r9_write(vcpu, regs->r9);
10565 kvm_r10_write(vcpu, regs->r10);
10566 kvm_r11_write(vcpu, regs->r11);
10567 kvm_r12_write(vcpu, regs->r12);
10568 kvm_r13_write(vcpu, regs->r13);
10569 kvm_r14_write(vcpu, regs->r14);
10570 kvm_r15_write(vcpu, regs->r15);
10573 kvm_rip_write(vcpu, regs->rip);
10574 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
10576 vcpu->arch.exception.pending = false;
10578 kvm_make_request(KVM_REQ_EVENT, vcpu);
10581 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10584 __set_regs(vcpu, regs);
10589 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
10591 struct desc_ptr dt;
10593 if (vcpu->arch.guest_state_protected)
10594 goto skip_protected_regs;
10596 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
10597 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
10598 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
10599 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
10600 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
10601 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
10603 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
10604 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
10606 static_call(kvm_x86_get_idt)(vcpu, &dt);
10607 sregs->idt.limit = dt.size;
10608 sregs->idt.base = dt.address;
10609 static_call(kvm_x86_get_gdt)(vcpu, &dt);
10610 sregs->gdt.limit = dt.size;
10611 sregs->gdt.base = dt.address;
10613 sregs->cr2 = vcpu->arch.cr2;
10614 sregs->cr3 = kvm_read_cr3(vcpu);
10616 skip_protected_regs:
10617 sregs->cr0 = kvm_read_cr0(vcpu);
10618 sregs->cr4 = kvm_read_cr4(vcpu);
10619 sregs->cr8 = kvm_get_cr8(vcpu);
10620 sregs->efer = vcpu->arch.efer;
10621 sregs->apic_base = kvm_get_apic_base(vcpu);
10624 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
10626 __get_sregs_common(vcpu, sregs);
10628 if (vcpu->arch.guest_state_protected)
10631 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
10632 set_bit(vcpu->arch.interrupt.nr,
10633 (unsigned long *)sregs->interrupt_bitmap);
10636 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
10640 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2);
10642 if (vcpu->arch.guest_state_protected)
10645 if (is_pae_paging(vcpu)) {
10646 for (i = 0 ; i < 4 ; i++)
10647 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i);
10648 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
10652 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
10653 struct kvm_sregs *sregs)
10656 __get_sregs(vcpu, sregs);
10661 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
10662 struct kvm_mp_state *mp_state)
10667 if (kvm_mpx_supported())
10668 kvm_load_guest_fpu(vcpu);
10670 r = kvm_apic_accept_events(vcpu);
10675 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
10676 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
10677 vcpu->arch.pv.pv_unhalted)
10678 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
10680 mp_state->mp_state = vcpu->arch.mp_state;
10683 if (kvm_mpx_supported())
10684 kvm_put_guest_fpu(vcpu);
10689 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
10690 struct kvm_mp_state *mp_state)
10696 if (!lapic_in_kernel(vcpu) &&
10697 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
10701 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
10702 * INIT state; latched init should be reported using
10703 * KVM_SET_VCPU_EVENTS, so reject it here.
10705 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
10706 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
10707 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
10710 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
10711 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
10712 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
10714 vcpu->arch.mp_state = mp_state->mp_state;
10715 kvm_make_request(KVM_REQ_EVENT, vcpu);
10723 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
10724 int reason, bool has_error_code, u32 error_code)
10726 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
10729 init_emulate_ctxt(vcpu);
10731 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
10732 has_error_code, error_code);
10734 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
10735 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
10736 vcpu->run->internal.ndata = 0;
10740 kvm_rip_write(vcpu, ctxt->eip);
10741 kvm_set_rflags(vcpu, ctxt->eflags);
10744 EXPORT_SYMBOL_GPL(kvm_task_switch);
10746 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
10748 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
10750 * When EFER.LME and CR0.PG are set, the processor is in
10751 * 64-bit mode (though maybe in a 32-bit code segment).
10752 * CR4.PAE and EFER.LMA must be set.
10754 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
10756 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3))
10760 * Not in 64-bit mode: EFER.LMA is clear and the code
10761 * segment cannot be 64-bit.
10763 if (sregs->efer & EFER_LMA || sregs->cs.l)
10767 return kvm_is_valid_cr4(vcpu, sregs->cr4);
10770 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs,
10771 int *mmu_reset_needed, bool update_pdptrs)
10773 struct msr_data apic_base_msr;
10775 struct desc_ptr dt;
10777 if (!kvm_is_valid_sregs(vcpu, sregs))
10780 apic_base_msr.data = sregs->apic_base;
10781 apic_base_msr.host_initiated = true;
10782 if (kvm_set_apic_base(vcpu, &apic_base_msr))
10785 if (vcpu->arch.guest_state_protected)
10788 dt.size = sregs->idt.limit;
10789 dt.address = sregs->idt.base;
10790 static_call(kvm_x86_set_idt)(vcpu, &dt);
10791 dt.size = sregs->gdt.limit;
10792 dt.address = sregs->gdt.base;
10793 static_call(kvm_x86_set_gdt)(vcpu, &dt);
10795 vcpu->arch.cr2 = sregs->cr2;
10796 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
10797 vcpu->arch.cr3 = sregs->cr3;
10798 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
10799 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3);
10801 kvm_set_cr8(vcpu, sregs->cr8);
10803 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
10804 static_call(kvm_x86_set_efer)(vcpu, sregs->efer);
10806 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
10807 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0);
10808 vcpu->arch.cr0 = sregs->cr0;
10810 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
10811 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4);
10813 if (update_pdptrs) {
10814 idx = srcu_read_lock(&vcpu->kvm->srcu);
10815 if (is_pae_paging(vcpu)) {
10816 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
10817 *mmu_reset_needed = 1;
10819 srcu_read_unlock(&vcpu->kvm->srcu, idx);
10822 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
10823 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
10824 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
10825 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
10826 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
10827 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
10829 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
10830 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
10832 update_cr8_intercept(vcpu);
10834 /* Older userspace won't unhalt the vcpu on reset. */
10835 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
10836 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
10837 !is_protmode(vcpu))
10838 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10843 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
10845 int pending_vec, max_bits;
10846 int mmu_reset_needed = 0;
10847 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true);
10852 if (mmu_reset_needed)
10853 kvm_mmu_reset_context(vcpu);
10855 max_bits = KVM_NR_INTERRUPTS;
10856 pending_vec = find_first_bit(
10857 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
10859 if (pending_vec < max_bits) {
10860 kvm_queue_interrupt(vcpu, pending_vec, false);
10861 pr_debug("Set back pending irq %d\n", pending_vec);
10862 kvm_make_request(KVM_REQ_EVENT, vcpu);
10867 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
10869 int mmu_reset_needed = 0;
10870 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
10871 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) &&
10872 !(sregs2->efer & EFER_LMA);
10875 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID)
10878 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected))
10881 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2,
10882 &mmu_reset_needed, !valid_pdptrs);
10886 if (valid_pdptrs) {
10887 for (i = 0; i < 4 ; i++)
10888 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]);
10890 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
10891 mmu_reset_needed = 1;
10892 vcpu->arch.pdptrs_from_userspace = true;
10894 if (mmu_reset_needed)
10895 kvm_mmu_reset_context(vcpu);
10899 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
10900 struct kvm_sregs *sregs)
10905 ret = __set_sregs(vcpu, sregs);
10910 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm)
10912 bool inhibit = false;
10913 struct kvm_vcpu *vcpu;
10916 down_write(&kvm->arch.apicv_update_lock);
10918 kvm_for_each_vcpu(i, vcpu, kvm) {
10919 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) {
10924 __kvm_request_apicv_update(kvm, !inhibit, APICV_INHIBIT_REASON_BLOCKIRQ);
10925 up_write(&kvm->arch.apicv_update_lock);
10928 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
10929 struct kvm_guest_debug *dbg)
10931 unsigned long rflags;
10934 if (vcpu->arch.guest_state_protected)
10939 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
10941 if (vcpu->arch.exception.pending)
10943 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
10944 kvm_queue_exception(vcpu, DB_VECTOR);
10946 kvm_queue_exception(vcpu, BP_VECTOR);
10950 * Read rflags as long as potentially injected trace flags are still
10953 rflags = kvm_get_rflags(vcpu);
10955 vcpu->guest_debug = dbg->control;
10956 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
10957 vcpu->guest_debug = 0;
10959 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
10960 for (i = 0; i < KVM_NR_DB_REGS; ++i)
10961 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
10962 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
10964 for (i = 0; i < KVM_NR_DB_REGS; i++)
10965 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
10967 kvm_update_dr7(vcpu);
10969 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
10970 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu);
10973 * Trigger an rflags update that will inject or remove the trace
10976 kvm_set_rflags(vcpu, rflags);
10978 static_call(kvm_x86_update_exception_bitmap)(vcpu);
10980 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm);
10990 * Translate a guest virtual address to a guest physical address.
10992 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
10993 struct kvm_translation *tr)
10995 unsigned long vaddr = tr->linear_address;
11001 idx = srcu_read_lock(&vcpu->kvm->srcu);
11002 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
11003 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11004 tr->physical_address = gpa;
11005 tr->valid = gpa != UNMAPPED_GVA;
11013 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11015 struct fxregs_state *fxsave;
11017 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11022 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11023 memcpy(fpu->fpr, fxsave->st_space, 128);
11024 fpu->fcw = fxsave->cwd;
11025 fpu->fsw = fxsave->swd;
11026 fpu->ftwx = fxsave->twd;
11027 fpu->last_opcode = fxsave->fop;
11028 fpu->last_ip = fxsave->rip;
11029 fpu->last_dp = fxsave->rdp;
11030 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
11036 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11038 struct fxregs_state *fxsave;
11040 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11045 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11047 memcpy(fxsave->st_space, fpu->fpr, 128);
11048 fxsave->cwd = fpu->fcw;
11049 fxsave->swd = fpu->fsw;
11050 fxsave->twd = fpu->ftwx;
11051 fxsave->fop = fpu->last_opcode;
11052 fxsave->rip = fpu->last_ip;
11053 fxsave->rdp = fpu->last_dp;
11054 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
11060 static void store_regs(struct kvm_vcpu *vcpu)
11062 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
11064 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
11065 __get_regs(vcpu, &vcpu->run->s.regs.regs);
11067 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
11068 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
11070 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
11071 kvm_vcpu_ioctl_x86_get_vcpu_events(
11072 vcpu, &vcpu->run->s.regs.events);
11075 static int sync_regs(struct kvm_vcpu *vcpu)
11077 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
11078 __set_regs(vcpu, &vcpu->run->s.regs.regs);
11079 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
11081 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
11082 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
11084 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
11086 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
11087 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
11088 vcpu, &vcpu->run->s.regs.events))
11090 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
11096 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
11098 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
11099 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
11100 "guest TSC will not be reliable\n");
11105 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
11110 vcpu->arch.last_vmentry_cpu = -1;
11111 vcpu->arch.regs_avail = ~0;
11112 vcpu->arch.regs_dirty = ~0;
11114 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
11115 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11117 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
11119 r = kvm_mmu_create(vcpu);
11123 if (irqchip_in_kernel(vcpu->kvm)) {
11124 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
11126 goto fail_mmu_destroy;
11127 if (kvm_apicv_activated(vcpu->kvm))
11128 vcpu->arch.apicv_active = true;
11130 static_branch_inc(&kvm_has_noapic_vcpu);
11134 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
11136 goto fail_free_lapic;
11137 vcpu->arch.pio_data = page_address(page);
11139 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
11140 GFP_KERNEL_ACCOUNT);
11141 if (!vcpu->arch.mce_banks)
11142 goto fail_free_pio_data;
11143 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
11145 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
11146 GFP_KERNEL_ACCOUNT))
11147 goto fail_free_mce_banks;
11149 if (!alloc_emulate_ctxt(vcpu))
11150 goto free_wbinvd_dirty_mask;
11152 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) {
11153 pr_err("kvm: failed to allocate vcpu's fpu\n");
11154 goto free_emulate_ctxt;
11157 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
11158 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
11160 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
11162 kvm_async_pf_hash_reset(vcpu);
11163 kvm_pmu_init(vcpu);
11165 vcpu->arch.pending_external_vector = -1;
11166 vcpu->arch.preempted_in_kernel = false;
11168 #if IS_ENABLED(CONFIG_HYPERV)
11169 vcpu->arch.hv_root_tdp = INVALID_PAGE;
11172 r = static_call(kvm_x86_vcpu_create)(vcpu);
11174 goto free_guest_fpu;
11176 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
11177 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
11178 kvm_vcpu_mtrr_init(vcpu);
11180 kvm_set_tsc_khz(vcpu, max_tsc_khz);
11181 kvm_vcpu_reset(vcpu, false);
11182 kvm_init_mmu(vcpu);
11187 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11189 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11190 free_wbinvd_dirty_mask:
11191 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11192 fail_free_mce_banks:
11193 kfree(vcpu->arch.mce_banks);
11194 fail_free_pio_data:
11195 free_page((unsigned long)vcpu->arch.pio_data);
11197 kvm_free_lapic(vcpu);
11199 kvm_mmu_destroy(vcpu);
11203 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
11205 struct kvm *kvm = vcpu->kvm;
11207 if (mutex_lock_killable(&vcpu->mutex))
11210 kvm_synchronize_tsc(vcpu, 0);
11213 /* poll control enabled by default */
11214 vcpu->arch.msr_kvm_poll_control = 1;
11216 mutex_unlock(&vcpu->mutex);
11218 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
11219 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
11220 KVMCLOCK_SYNC_PERIOD);
11223 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
11227 kvmclock_reset(vcpu);
11229 static_call(kvm_x86_vcpu_free)(vcpu);
11231 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11232 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11233 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11235 kvm_hv_vcpu_uninit(vcpu);
11236 kvm_pmu_destroy(vcpu);
11237 kfree(vcpu->arch.mce_banks);
11238 kvm_free_lapic(vcpu);
11239 idx = srcu_read_lock(&vcpu->kvm->srcu);
11240 kvm_mmu_destroy(vcpu);
11241 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11242 free_page((unsigned long)vcpu->arch.pio_data);
11243 kvfree(vcpu->arch.cpuid_entries);
11244 if (!lapic_in_kernel(vcpu))
11245 static_branch_dec(&kvm_has_noapic_vcpu);
11248 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
11250 struct kvm_cpuid_entry2 *cpuid_0x1;
11251 unsigned long old_cr0 = kvm_read_cr0(vcpu);
11252 unsigned long new_cr0;
11255 * Several of the "set" flows, e.g. ->set_cr0(), read other registers
11256 * to handle side effects. RESET emulation hits those flows and relies
11257 * on emulated/virtualized registers, including those that are loaded
11258 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel
11259 * to detect improper or missing initialization.
11261 WARN_ON_ONCE(!init_event &&
11262 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu)));
11264 kvm_lapic_reset(vcpu, init_event);
11266 vcpu->arch.hflags = 0;
11268 vcpu->arch.smi_pending = 0;
11269 vcpu->arch.smi_count = 0;
11270 atomic_set(&vcpu->arch.nmi_queued, 0);
11271 vcpu->arch.nmi_pending = 0;
11272 vcpu->arch.nmi_injected = false;
11273 kvm_clear_interrupt_queue(vcpu);
11274 kvm_clear_exception_queue(vcpu);
11276 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
11277 kvm_update_dr0123(vcpu);
11278 vcpu->arch.dr6 = DR6_ACTIVE_LOW;
11279 vcpu->arch.dr7 = DR7_FIXED_1;
11280 kvm_update_dr7(vcpu);
11282 vcpu->arch.cr2 = 0;
11284 kvm_make_request(KVM_REQ_EVENT, vcpu);
11285 vcpu->arch.apf.msr_en_val = 0;
11286 vcpu->arch.apf.msr_int_val = 0;
11287 vcpu->arch.st.msr_val = 0;
11289 kvmclock_reset(vcpu);
11291 kvm_clear_async_pf_completion_queue(vcpu);
11292 kvm_async_pf_hash_reset(vcpu);
11293 vcpu->arch.apf.halted = false;
11295 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) {
11296 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate;
11299 * To avoid have the INIT path from kvm_apic_has_events() that be
11300 * called with loaded FPU and does not let userspace fix the state.
11303 kvm_put_guest_fpu(vcpu);
11305 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS);
11306 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR);
11309 kvm_load_guest_fpu(vcpu);
11313 kvm_pmu_reset(vcpu);
11314 vcpu->arch.smbase = 0x30000;
11316 vcpu->arch.msr_misc_features_enables = 0;
11318 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP);
11319 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true);
11322 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */
11323 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
11324 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP);
11327 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon)
11328 * if no CPUID match is found. Note, it's impossible to get a match at
11329 * RESET since KVM emulates RESET before exposing the vCPU to userspace,
11330 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry
11331 * on RESET. But, go through the motions in case that's ever remedied.
11333 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1, 0);
11334 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600);
11336 static_call(kvm_x86_vcpu_reset)(vcpu, init_event);
11338 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
11339 kvm_rip_write(vcpu, 0xfff0);
11341 vcpu->arch.cr3 = 0;
11342 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11345 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions
11346 * of Intel's SDM list CD/NW as being set on INIT, but they contradict
11347 * (or qualify) that with a footnote stating that CD/NW are preserved.
11349 new_cr0 = X86_CR0_ET;
11351 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD));
11353 new_cr0 |= X86_CR0_NW | X86_CR0_CD;
11355 static_call(kvm_x86_set_cr0)(vcpu, new_cr0);
11356 static_call(kvm_x86_set_cr4)(vcpu, 0);
11357 static_call(kvm_x86_set_efer)(vcpu, 0);
11358 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11361 * On the standard CR0/CR4/EFER modification paths, there are several
11362 * complex conditions determining whether the MMU has to be reset and/or
11363 * which PCIDs have to be flushed. However, CR0.WP and the paging-related
11364 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush
11365 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as
11366 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here.
11368 if (old_cr0 & X86_CR0_PG) {
11369 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11370 kvm_mmu_reset_context(vcpu);
11374 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's
11375 * APM states the TLBs are untouched by INIT, but it also states that
11376 * the TLBs are flushed on "External initialization of the processor."
11377 * Flush the guest TLB regardless of vendor, there is no meaningful
11378 * benefit in relying on the guest to flush the TLB immediately after
11379 * INIT. A spurious TLB flush is benign and likely negligible from a
11380 * performance perspective.
11383 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11385 EXPORT_SYMBOL_GPL(kvm_vcpu_reset);
11387 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
11389 struct kvm_segment cs;
11391 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
11392 cs.selector = vector << 8;
11393 cs.base = vector << 12;
11394 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
11395 kvm_rip_write(vcpu, 0);
11397 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
11399 int kvm_arch_hardware_enable(void)
11402 struct kvm_vcpu *vcpu;
11407 bool stable, backwards_tsc = false;
11409 kvm_user_return_msr_cpu_online();
11410 ret = static_call(kvm_x86_hardware_enable)();
11414 local_tsc = rdtsc();
11415 stable = !kvm_check_tsc_unstable();
11416 list_for_each_entry(kvm, &vm_list, vm_list) {
11417 kvm_for_each_vcpu(i, vcpu, kvm) {
11418 if (!stable && vcpu->cpu == smp_processor_id())
11419 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
11420 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
11421 backwards_tsc = true;
11422 if (vcpu->arch.last_host_tsc > max_tsc)
11423 max_tsc = vcpu->arch.last_host_tsc;
11429 * Sometimes, even reliable TSCs go backwards. This happens on
11430 * platforms that reset TSC during suspend or hibernate actions, but
11431 * maintain synchronization. We must compensate. Fortunately, we can
11432 * detect that condition here, which happens early in CPU bringup,
11433 * before any KVM threads can be running. Unfortunately, we can't
11434 * bring the TSCs fully up to date with real time, as we aren't yet far
11435 * enough into CPU bringup that we know how much real time has actually
11436 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
11437 * variables that haven't been updated yet.
11439 * So we simply find the maximum observed TSC above, then record the
11440 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
11441 * the adjustment will be applied. Note that we accumulate
11442 * adjustments, in case multiple suspend cycles happen before some VCPU
11443 * gets a chance to run again. In the event that no KVM threads get a
11444 * chance to run, we will miss the entire elapsed period, as we'll have
11445 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
11446 * loose cycle time. This isn't too big a deal, since the loss will be
11447 * uniform across all VCPUs (not to mention the scenario is extremely
11448 * unlikely). It is possible that a second hibernate recovery happens
11449 * much faster than a first, causing the observed TSC here to be
11450 * smaller; this would require additional padding adjustment, which is
11451 * why we set last_host_tsc to the local tsc observed here.
11453 * N.B. - this code below runs only on platforms with reliable TSC,
11454 * as that is the only way backwards_tsc is set above. Also note
11455 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
11456 * have the same delta_cyc adjustment applied if backwards_tsc
11457 * is detected. Note further, this adjustment is only done once,
11458 * as we reset last_host_tsc on all VCPUs to stop this from being
11459 * called multiple times (one for each physical CPU bringup).
11461 * Platforms with unreliable TSCs don't have to deal with this, they
11462 * will be compensated by the logic in vcpu_load, which sets the TSC to
11463 * catchup mode. This will catchup all VCPUs to real time, but cannot
11464 * guarantee that they stay in perfect synchronization.
11466 if (backwards_tsc) {
11467 u64 delta_cyc = max_tsc - local_tsc;
11468 list_for_each_entry(kvm, &vm_list, vm_list) {
11469 kvm->arch.backwards_tsc_observed = true;
11470 kvm_for_each_vcpu(i, vcpu, kvm) {
11471 vcpu->arch.tsc_offset_adjustment += delta_cyc;
11472 vcpu->arch.last_host_tsc = local_tsc;
11473 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
11477 * We have to disable TSC offset matching.. if you were
11478 * booting a VM while issuing an S4 host suspend....
11479 * you may have some problem. Solving this issue is
11480 * left as an exercise to the reader.
11482 kvm->arch.last_tsc_nsec = 0;
11483 kvm->arch.last_tsc_write = 0;
11490 void kvm_arch_hardware_disable(void)
11492 static_call(kvm_x86_hardware_disable)();
11493 drop_user_return_notifiers();
11496 int kvm_arch_hardware_setup(void *opaque)
11498 struct kvm_x86_init_ops *ops = opaque;
11501 rdmsrl_safe(MSR_EFER, &host_efer);
11503 if (boot_cpu_has(X86_FEATURE_XSAVES))
11504 rdmsrl(MSR_IA32_XSS, host_xss);
11506 r = ops->hardware_setup();
11510 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
11511 kvm_ops_static_call_update();
11513 kvm_register_perf_callbacks(ops->handle_intel_pt_intr);
11515 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
11518 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
11519 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
11520 #undef __kvm_cpu_cap_has
11522 if (kvm_has_tsc_control) {
11524 * Make sure the user can only configure tsc_khz values that
11525 * fit into a signed integer.
11526 * A min value is not calculated because it will always
11527 * be 1 on all machines.
11529 u64 max = min(0x7fffffffULL,
11530 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
11531 kvm_max_guest_tsc_khz = max;
11533 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
11536 kvm_init_msr_list();
11540 void kvm_arch_hardware_unsetup(void)
11542 kvm_unregister_perf_callbacks();
11544 static_call(kvm_x86_hardware_unsetup)();
11547 int kvm_arch_check_processor_compat(void *opaque)
11549 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
11550 struct kvm_x86_init_ops *ops = opaque;
11552 WARN_ON(!irqs_disabled());
11554 if (__cr4_reserved_bits(cpu_has, c) !=
11555 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
11558 return ops->check_processor_compatibility();
11561 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
11563 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
11565 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
11567 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
11569 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
11572 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
11573 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu);
11575 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
11577 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
11579 vcpu->arch.l1tf_flush_l1d = true;
11580 if (pmu->version && unlikely(pmu->event_count)) {
11581 pmu->need_cleanup = true;
11582 kvm_make_request(KVM_REQ_PMU, vcpu);
11584 static_call(kvm_x86_sched_in)(vcpu, cpu);
11587 void kvm_arch_free_vm(struct kvm *kvm)
11589 kfree(to_kvm_hv(kvm)->hv_pa_pg);
11590 __kvm_arch_free_vm(kvm);
11594 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
11597 unsigned long flags;
11602 ret = kvm_page_track_init(kvm);
11606 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
11607 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
11608 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
11609 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
11610 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
11611 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
11613 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
11614 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
11615 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
11616 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
11617 &kvm->arch.irq_sources_bitmap);
11619 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
11620 mutex_init(&kvm->arch.apic_map_lock);
11621 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock);
11622 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
11624 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
11625 pvclock_update_vm_gtod_copy(kvm);
11626 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
11628 kvm->arch.guest_can_read_msr_platform_info = true;
11629 kvm->arch.enable_pmu = enable_pmu;
11631 #if IS_ENABLED(CONFIG_HYPERV)
11632 spin_lock_init(&kvm->arch.hv_root_tdp_lock);
11633 kvm->arch.hv_root_tdp = INVALID_PAGE;
11636 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
11637 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
11639 kvm_apicv_init(kvm);
11640 kvm_hv_init_vm(kvm);
11641 kvm_mmu_init_vm(kvm);
11642 kvm_xen_init_vm(kvm);
11644 return static_call(kvm_x86_vm_init)(kvm);
11647 int kvm_arch_post_init_vm(struct kvm *kvm)
11649 return kvm_mmu_post_init_vm(kvm);
11652 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
11655 kvm_mmu_unload(vcpu);
11659 static void kvm_free_vcpus(struct kvm *kvm)
11662 struct kvm_vcpu *vcpu;
11665 * Unpin any mmu pages first.
11667 kvm_for_each_vcpu(i, vcpu, kvm) {
11668 kvm_clear_async_pf_completion_queue(vcpu);
11669 kvm_unload_vcpu_mmu(vcpu);
11672 kvm_destroy_vcpus(kvm);
11675 void kvm_arch_sync_events(struct kvm *kvm)
11677 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
11678 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
11683 * __x86_set_memory_region: Setup KVM internal memory slot
11685 * @kvm: the kvm pointer to the VM.
11686 * @id: the slot ID to setup.
11687 * @gpa: the GPA to install the slot (unused when @size == 0).
11688 * @size: the size of the slot. Set to zero to uninstall a slot.
11690 * This function helps to setup a KVM internal memory slot. Specify
11691 * @size > 0 to install a new slot, while @size == 0 to uninstall a
11692 * slot. The return code can be one of the following:
11694 * HVA: on success (uninstall will return a bogus HVA)
11697 * The caller should always use IS_ERR() to check the return value
11698 * before use. Note, the KVM internal memory slots are guaranteed to
11699 * remain valid and unchanged until the VM is destroyed, i.e., the
11700 * GPA->HVA translation will not change. However, the HVA is a user
11701 * address, i.e. its accessibility is not guaranteed, and must be
11702 * accessed via __copy_{to,from}_user().
11704 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
11708 unsigned long hva, old_npages;
11709 struct kvm_memslots *slots = kvm_memslots(kvm);
11710 struct kvm_memory_slot *slot;
11712 /* Called with kvm->slots_lock held. */
11713 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
11714 return ERR_PTR_USR(-EINVAL);
11716 slot = id_to_memslot(slots, id);
11718 if (slot && slot->npages)
11719 return ERR_PTR_USR(-EEXIST);
11722 * MAP_SHARED to prevent internal slot pages from being moved
11725 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
11726 MAP_SHARED | MAP_ANONYMOUS, 0);
11727 if (IS_ERR((void *)hva))
11728 return (void __user *)hva;
11730 if (!slot || !slot->npages)
11733 old_npages = slot->npages;
11734 hva = slot->userspace_addr;
11737 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
11738 struct kvm_userspace_memory_region m;
11740 m.slot = id | (i << 16);
11742 m.guest_phys_addr = gpa;
11743 m.userspace_addr = hva;
11744 m.memory_size = size;
11745 r = __kvm_set_memory_region(kvm, &m);
11747 return ERR_PTR_USR(r);
11751 vm_munmap(hva, old_npages * PAGE_SIZE);
11753 return (void __user *)hva;
11755 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
11757 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
11759 kvm_mmu_pre_destroy_vm(kvm);
11762 void kvm_arch_destroy_vm(struct kvm *kvm)
11764 if (current->mm == kvm->mm) {
11766 * Free memory regions allocated on behalf of userspace,
11767 * unless the the memory map has changed due to process exit
11770 mutex_lock(&kvm->slots_lock);
11771 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
11773 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
11775 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
11776 mutex_unlock(&kvm->slots_lock);
11778 static_call_cond(kvm_x86_vm_destroy)(kvm);
11779 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1));
11780 kvm_pic_destroy(kvm);
11781 kvm_ioapic_destroy(kvm);
11782 kvm_free_vcpus(kvm);
11783 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
11784 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
11785 kvm_mmu_uninit_vm(kvm);
11786 kvm_page_track_cleanup(kvm);
11787 kvm_xen_destroy_vm(kvm);
11788 kvm_hv_destroy_vm(kvm);
11791 static void memslot_rmap_free(struct kvm_memory_slot *slot)
11795 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
11796 kvfree(slot->arch.rmap[i]);
11797 slot->arch.rmap[i] = NULL;
11801 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
11805 memslot_rmap_free(slot);
11807 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
11808 kvfree(slot->arch.lpage_info[i - 1]);
11809 slot->arch.lpage_info[i - 1] = NULL;
11812 kvm_page_track_free_memslot(slot);
11815 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages)
11817 const int sz = sizeof(*slot->arch.rmap[0]);
11820 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
11822 int lpages = __kvm_mmu_slot_lpages(slot, npages, level);
11824 if (slot->arch.rmap[i])
11827 slot->arch.rmap[i] = kvcalloc(lpages, sz, GFP_KERNEL_ACCOUNT);
11828 if (!slot->arch.rmap[i]) {
11829 memslot_rmap_free(slot);
11837 static int kvm_alloc_memslot_metadata(struct kvm *kvm,
11838 struct kvm_memory_slot *slot)
11840 unsigned long npages = slot->npages;
11844 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
11845 * old arrays will be freed by __kvm_set_memory_region() if installing
11846 * the new memslot is successful.
11848 memset(&slot->arch, 0, sizeof(slot->arch));
11850 if (kvm_memslots_have_rmaps(kvm)) {
11851 r = memslot_rmap_alloc(slot, npages);
11856 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
11857 struct kvm_lpage_info *linfo;
11858 unsigned long ugfn;
11862 lpages = __kvm_mmu_slot_lpages(slot, npages, level);
11864 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
11868 slot->arch.lpage_info[i - 1] = linfo;
11870 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
11871 linfo[0].disallow_lpage = 1;
11872 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
11873 linfo[lpages - 1].disallow_lpage = 1;
11874 ugfn = slot->userspace_addr >> PAGE_SHIFT;
11876 * If the gfn and userspace address are not aligned wrt each
11877 * other, disable large page support for this slot.
11879 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
11882 for (j = 0; j < lpages; ++j)
11883 linfo[j].disallow_lpage = 1;
11887 if (kvm_page_track_create_memslot(kvm, slot, npages))
11893 memslot_rmap_free(slot);
11895 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
11896 kvfree(slot->arch.lpage_info[i - 1]);
11897 slot->arch.lpage_info[i - 1] = NULL;
11902 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
11904 struct kvm_vcpu *vcpu;
11908 * memslots->generation has been incremented.
11909 * mmio generation may have reached its maximum value.
11911 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
11913 /* Force re-initialization of steal_time cache */
11914 kvm_for_each_vcpu(i, vcpu, kvm)
11915 kvm_vcpu_kick(vcpu);
11918 int kvm_arch_prepare_memory_region(struct kvm *kvm,
11919 const struct kvm_memory_slot *old,
11920 struct kvm_memory_slot *new,
11921 enum kvm_mr_change change)
11923 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE)
11924 return kvm_alloc_memslot_metadata(kvm, new);
11926 if (change == KVM_MR_FLAGS_ONLY)
11927 memcpy(&new->arch, &old->arch, sizeof(old->arch));
11928 else if (WARN_ON_ONCE(change != KVM_MR_DELETE))
11935 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable)
11937 struct kvm_arch *ka = &kvm->arch;
11939 if (!kvm_x86_ops.cpu_dirty_log_size)
11942 if ((enable && ++ka->cpu_dirty_logging_count == 1) ||
11943 (!enable && --ka->cpu_dirty_logging_count == 0))
11944 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING);
11946 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0);
11949 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
11950 struct kvm_memory_slot *old,
11951 const struct kvm_memory_slot *new,
11952 enum kvm_mr_change change)
11954 u32 old_flags = old ? old->flags : 0;
11955 u32 new_flags = new ? new->flags : 0;
11956 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES;
11959 * Update CPU dirty logging if dirty logging is being toggled. This
11960 * applies to all operations.
11962 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)
11963 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages);
11966 * Nothing more to do for RO slots (which can't be dirtied and can't be
11967 * made writable) or CREATE/MOVE/DELETE of a slot.
11969 * For a memslot with dirty logging disabled:
11970 * CREATE: No dirty mappings will already exist.
11971 * MOVE/DELETE: The old mappings will already have been cleaned up by
11972 * kvm_arch_flush_shadow_memslot()
11974 * For a memslot with dirty logging enabled:
11975 * CREATE: No shadow pages exist, thus nothing to write-protect
11976 * and no dirty bits to clear.
11977 * MOVE/DELETE: The old mappings will already have been cleaned up by
11978 * kvm_arch_flush_shadow_memslot().
11980 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY))
11984 * READONLY and non-flags changes were filtered out above, and the only
11985 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty
11986 * logging isn't being toggled on or off.
11988 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)))
11991 if (!log_dirty_pages) {
11993 * Dirty logging tracks sptes in 4k granularity, meaning that
11994 * large sptes have to be split. If live migration succeeds,
11995 * the guest in the source machine will be destroyed and large
11996 * sptes will be created in the destination. However, if the
11997 * guest continues to run in the source machine (for example if
11998 * live migration fails), small sptes will remain around and
11999 * cause bad performance.
12001 * Scan sptes if dirty logging has been stopped, dropping those
12002 * which can be collapsed into a single large-page spte. Later
12003 * page faults will create the large-page sptes.
12005 kvm_mmu_zap_collapsible_sptes(kvm, new);
12008 * Initially-all-set does not require write protecting any page,
12009 * because they're all assumed to be dirty.
12011 if (kvm_dirty_log_manual_protect_and_init_set(kvm))
12014 if (READ_ONCE(eager_page_split))
12015 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K);
12017 if (kvm_x86_ops.cpu_dirty_log_size) {
12018 kvm_mmu_slot_leaf_clear_dirty(kvm, new);
12019 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M);
12021 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K);
12026 void kvm_arch_commit_memory_region(struct kvm *kvm,
12027 struct kvm_memory_slot *old,
12028 const struct kvm_memory_slot *new,
12029 enum kvm_mr_change change)
12031 if (!kvm->arch.n_requested_mmu_pages &&
12032 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) {
12033 unsigned long nr_mmu_pages;
12035 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO;
12036 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
12037 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
12040 kvm_mmu_slot_apply_flags(kvm, old, new, change);
12042 /* Free the arrays associated with the old memslot. */
12043 if (change == KVM_MR_MOVE)
12044 kvm_arch_free_memslot(kvm, old);
12047 void kvm_arch_flush_shadow_all(struct kvm *kvm)
12049 kvm_mmu_zap_all(kvm);
12052 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
12053 struct kvm_memory_slot *slot)
12055 kvm_page_track_flush_slot(kvm, slot);
12058 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
12060 return (is_guest_mode(vcpu) &&
12061 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu));
12064 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
12066 if (!list_empty_careful(&vcpu->async_pf.done))
12069 if (kvm_apic_has_events(vcpu))
12072 if (vcpu->arch.pv.pv_unhalted)
12075 if (vcpu->arch.exception.pending)
12078 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12079 (vcpu->arch.nmi_pending &&
12080 static_call(kvm_x86_nmi_allowed)(vcpu, false)))
12083 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
12084 (vcpu->arch.smi_pending &&
12085 static_call(kvm_x86_smi_allowed)(vcpu, false)))
12088 if (kvm_arch_interrupt_allowed(vcpu) &&
12089 (kvm_cpu_has_interrupt(vcpu) ||
12090 kvm_guest_apic_has_interrupt(vcpu)))
12093 if (kvm_hv_has_stimer_pending(vcpu))
12096 if (is_guest_mode(vcpu) &&
12097 kvm_x86_ops.nested_ops->hv_timer_pending &&
12098 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
12104 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
12106 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
12109 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu)
12111 if (vcpu->arch.apicv_active && static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
12117 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
12119 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
12122 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12123 kvm_test_request(KVM_REQ_SMI, vcpu) ||
12124 kvm_test_request(KVM_REQ_EVENT, vcpu))
12127 return kvm_arch_dy_has_pending_interrupt(vcpu);
12130 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
12132 if (vcpu->arch.guest_state_protected)
12135 return vcpu->arch.preempted_in_kernel;
12138 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu)
12140 return kvm_rip_read(vcpu);
12143 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
12145 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
12148 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
12150 return static_call(kvm_x86_interrupt_allowed)(vcpu, false);
12153 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
12155 /* Can't read the RIP when guest state is protected, just return 0 */
12156 if (vcpu->arch.guest_state_protected)
12159 if (is_64_bit_mode(vcpu))
12160 return kvm_rip_read(vcpu);
12161 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
12162 kvm_rip_read(vcpu));
12164 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
12166 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
12168 return kvm_get_linear_rip(vcpu) == linear_rip;
12170 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
12172 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
12174 unsigned long rflags;
12176 rflags = static_call(kvm_x86_get_rflags)(vcpu);
12177 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
12178 rflags &= ~X86_EFLAGS_TF;
12181 EXPORT_SYMBOL_GPL(kvm_get_rflags);
12183 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12185 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
12186 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
12187 rflags |= X86_EFLAGS_TF;
12188 static_call(kvm_x86_set_rflags)(vcpu, rflags);
12191 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12193 __kvm_set_rflags(vcpu, rflags);
12194 kvm_make_request(KVM_REQ_EVENT, vcpu);
12196 EXPORT_SYMBOL_GPL(kvm_set_rflags);
12198 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
12202 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
12206 r = kvm_mmu_reload(vcpu);
12210 if (!vcpu->arch.mmu->direct_map &&
12211 work->arch.cr3 != vcpu->arch.mmu->get_guest_pgd(vcpu))
12214 kvm_mmu_do_page_fault(vcpu, work->cr2_or_gpa, 0, true);
12217 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
12219 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
12221 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
12224 static inline u32 kvm_async_pf_next_probe(u32 key)
12226 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
12229 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12231 u32 key = kvm_async_pf_hash_fn(gfn);
12233 while (vcpu->arch.apf.gfns[key] != ~0)
12234 key = kvm_async_pf_next_probe(key);
12236 vcpu->arch.apf.gfns[key] = gfn;
12239 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
12242 u32 key = kvm_async_pf_hash_fn(gfn);
12244 for (i = 0; i < ASYNC_PF_PER_VCPU &&
12245 (vcpu->arch.apf.gfns[key] != gfn &&
12246 vcpu->arch.apf.gfns[key] != ~0); i++)
12247 key = kvm_async_pf_next_probe(key);
12252 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12254 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
12257 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12261 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
12263 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
12267 vcpu->arch.apf.gfns[i] = ~0;
12269 j = kvm_async_pf_next_probe(j);
12270 if (vcpu->arch.apf.gfns[j] == ~0)
12272 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
12274 * k lies cyclically in ]i,j]
12276 * |....j i.k.| or |.k..j i...|
12278 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
12279 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
12284 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
12286 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
12288 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
12292 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
12294 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
12296 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
12297 &token, offset, sizeof(token));
12300 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
12302 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
12305 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
12306 &val, offset, sizeof(val)))
12312 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
12315 if (!kvm_pv_async_pf_enabled(vcpu))
12318 if (vcpu->arch.apf.send_user_only &&
12319 static_call(kvm_x86_get_cpl)(vcpu) == 0)
12322 if (is_guest_mode(vcpu)) {
12324 * L1 needs to opt into the special #PF vmexits that are
12325 * used to deliver async page faults.
12327 return vcpu->arch.apf.delivery_as_pf_vmexit;
12330 * Play it safe in case the guest temporarily disables paging.
12331 * The real mode IDT in particular is unlikely to have a #PF
12334 return is_paging(vcpu);
12338 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
12340 if (unlikely(!lapic_in_kernel(vcpu) ||
12341 kvm_event_needs_reinjection(vcpu) ||
12342 vcpu->arch.exception.pending))
12345 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
12349 * If interrupts are off we cannot even use an artificial
12352 return kvm_arch_interrupt_allowed(vcpu);
12355 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
12356 struct kvm_async_pf *work)
12358 struct x86_exception fault;
12360 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
12361 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
12363 if (kvm_can_deliver_async_pf(vcpu) &&
12364 !apf_put_user_notpresent(vcpu)) {
12365 fault.vector = PF_VECTOR;
12366 fault.error_code_valid = true;
12367 fault.error_code = 0;
12368 fault.nested_page_fault = false;
12369 fault.address = work->arch.token;
12370 fault.async_page_fault = true;
12371 kvm_inject_page_fault(vcpu, &fault);
12375 * It is not possible to deliver a paravirtualized asynchronous
12376 * page fault, but putting the guest in an artificial halt state
12377 * can be beneficial nevertheless: if an interrupt arrives, we
12378 * can deliver it timely and perhaps the guest will schedule
12379 * another process. When the instruction that triggered a page
12380 * fault is retried, hopefully the page will be ready in the host.
12382 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
12387 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
12388 struct kvm_async_pf *work)
12390 struct kvm_lapic_irq irq = {
12391 .delivery_mode = APIC_DM_FIXED,
12392 .vector = vcpu->arch.apf.vec
12395 if (work->wakeup_all)
12396 work->arch.token = ~0; /* broadcast wakeup */
12398 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
12399 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
12401 if ((work->wakeup_all || work->notpresent_injected) &&
12402 kvm_pv_async_pf_enabled(vcpu) &&
12403 !apf_put_user_ready(vcpu, work->arch.token)) {
12404 vcpu->arch.apf.pageready_pending = true;
12405 kvm_apic_set_irq(vcpu, &irq, NULL);
12408 vcpu->arch.apf.halted = false;
12409 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
12412 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
12414 kvm_make_request(KVM_REQ_APF_READY, vcpu);
12415 if (!vcpu->arch.apf.pageready_pending)
12416 kvm_vcpu_kick(vcpu);
12419 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
12421 if (!kvm_pv_async_pf_enabled(vcpu))
12424 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu);
12427 void kvm_arch_start_assignment(struct kvm *kvm)
12429 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1)
12430 static_call_cond(kvm_x86_pi_start_assignment)(kvm);
12432 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
12434 void kvm_arch_end_assignment(struct kvm *kvm)
12436 atomic_dec(&kvm->arch.assigned_device_count);
12438 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
12440 bool kvm_arch_has_assigned_device(struct kvm *kvm)
12442 return atomic_read(&kvm->arch.assigned_device_count);
12444 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
12446 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
12448 atomic_inc(&kvm->arch.noncoherent_dma_count);
12450 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
12452 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
12454 atomic_dec(&kvm->arch.noncoherent_dma_count);
12456 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
12458 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
12460 return atomic_read(&kvm->arch.noncoherent_dma_count);
12462 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
12464 bool kvm_arch_has_irq_bypass(void)
12469 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
12470 struct irq_bypass_producer *prod)
12472 struct kvm_kernel_irqfd *irqfd =
12473 container_of(cons, struct kvm_kernel_irqfd, consumer);
12476 irqfd->producer = prod;
12477 kvm_arch_start_assignment(irqfd->kvm);
12478 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm,
12479 prod->irq, irqfd->gsi, 1);
12482 kvm_arch_end_assignment(irqfd->kvm);
12487 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
12488 struct irq_bypass_producer *prod)
12491 struct kvm_kernel_irqfd *irqfd =
12492 container_of(cons, struct kvm_kernel_irqfd, consumer);
12494 WARN_ON(irqfd->producer != prod);
12495 irqfd->producer = NULL;
12498 * When producer of consumer is unregistered, we change back to
12499 * remapped mode, so we can re-use the current implementation
12500 * when the irq is masked/disabled or the consumer side (KVM
12501 * int this case doesn't want to receive the interrupts.
12503 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0);
12505 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
12506 " fails: %d\n", irqfd->consumer.token, ret);
12508 kvm_arch_end_assignment(irqfd->kvm);
12511 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
12512 uint32_t guest_irq, bool set)
12514 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set);
12517 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old,
12518 struct kvm_kernel_irq_routing_entry *new)
12520 if (new->type != KVM_IRQ_ROUTING_MSI)
12523 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi));
12526 bool kvm_vector_hashing_enabled(void)
12528 return vector_hashing;
12531 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
12533 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
12535 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
12538 int kvm_spec_ctrl_test_value(u64 value)
12541 * test that setting IA32_SPEC_CTRL to given value
12542 * is allowed by the host processor
12546 unsigned long flags;
12549 local_irq_save(flags);
12551 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
12553 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
12556 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
12558 local_irq_restore(flags);
12562 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
12564 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
12566 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
12567 struct x86_exception fault;
12568 u32 access = error_code &
12569 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
12571 if (!(error_code & PFERR_PRESENT_MASK) ||
12572 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != UNMAPPED_GVA) {
12574 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
12575 * tables probably do not match the TLB. Just proceed
12576 * with the error code that the processor gave.
12578 fault.vector = PF_VECTOR;
12579 fault.error_code_valid = true;
12580 fault.error_code = error_code;
12581 fault.nested_page_fault = false;
12582 fault.address = gva;
12584 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
12586 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
12589 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
12590 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
12591 * indicates whether exit to userspace is needed.
12593 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
12594 struct x86_exception *e)
12596 if (r == X86EMUL_PROPAGATE_FAULT) {
12597 kvm_inject_emulated_page_fault(vcpu, e);
12602 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
12603 * while handling a VMX instruction KVM could've handled the request
12604 * correctly by exiting to userspace and performing I/O but there
12605 * doesn't seem to be a real use-case behind such requests, just return
12606 * KVM_EXIT_INTERNAL_ERROR for now.
12608 kvm_prepare_emulation_failure_exit(vcpu);
12612 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
12614 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
12617 struct x86_exception e;
12624 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
12625 if (r != X86EMUL_CONTINUE)
12626 return kvm_handle_memory_failure(vcpu, r, &e);
12628 if (operand.pcid >> 12 != 0) {
12629 kvm_inject_gp(vcpu, 0);
12633 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
12636 case INVPCID_TYPE_INDIV_ADDR:
12637 if ((!pcid_enabled && (operand.pcid != 0)) ||
12638 is_noncanonical_address(operand.gla, vcpu)) {
12639 kvm_inject_gp(vcpu, 0);
12642 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
12643 return kvm_skip_emulated_instruction(vcpu);
12645 case INVPCID_TYPE_SINGLE_CTXT:
12646 if (!pcid_enabled && (operand.pcid != 0)) {
12647 kvm_inject_gp(vcpu, 0);
12651 kvm_invalidate_pcid(vcpu, operand.pcid);
12652 return kvm_skip_emulated_instruction(vcpu);
12654 case INVPCID_TYPE_ALL_NON_GLOBAL:
12656 * Currently, KVM doesn't mark global entries in the shadow
12657 * page tables, so a non-global flush just degenerates to a
12658 * global flush. If needed, we could optimize this later by
12659 * keeping track of global entries in shadow page tables.
12663 case INVPCID_TYPE_ALL_INCL_GLOBAL:
12664 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12665 return kvm_skip_emulated_instruction(vcpu);
12668 kvm_inject_gp(vcpu, 0);
12672 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
12674 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
12676 struct kvm_run *run = vcpu->run;
12677 struct kvm_mmio_fragment *frag;
12680 BUG_ON(!vcpu->mmio_needed);
12682 /* Complete previous fragment */
12683 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
12684 len = min(8u, frag->len);
12685 if (!vcpu->mmio_is_write)
12686 memcpy(frag->data, run->mmio.data, len);
12688 if (frag->len <= 8) {
12689 /* Switch to the next fragment. */
12691 vcpu->mmio_cur_fragment++;
12693 /* Go forward to the next mmio piece. */
12699 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
12700 vcpu->mmio_needed = 0;
12702 // VMG change, at this point, we're always done
12703 // RIP has already been advanced
12707 // More MMIO is needed
12708 run->mmio.phys_addr = frag->gpa;
12709 run->mmio.len = min(8u, frag->len);
12710 run->mmio.is_write = vcpu->mmio_is_write;
12711 if (run->mmio.is_write)
12712 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
12713 run->exit_reason = KVM_EXIT_MMIO;
12715 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
12720 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
12724 struct kvm_mmio_fragment *frag;
12729 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
12730 if (handled == bytes)
12737 /*TODO: Check if need to increment number of frags */
12738 frag = vcpu->mmio_fragments;
12739 vcpu->mmio_nr_fragments = 1;
12744 vcpu->mmio_needed = 1;
12745 vcpu->mmio_cur_fragment = 0;
12747 vcpu->run->mmio.phys_addr = gpa;
12748 vcpu->run->mmio.len = min(8u, frag->len);
12749 vcpu->run->mmio.is_write = 1;
12750 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
12751 vcpu->run->exit_reason = KVM_EXIT_MMIO;
12753 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
12757 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
12759 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
12763 struct kvm_mmio_fragment *frag;
12768 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
12769 if (handled == bytes)
12776 /*TODO: Check if need to increment number of frags */
12777 frag = vcpu->mmio_fragments;
12778 vcpu->mmio_nr_fragments = 1;
12783 vcpu->mmio_needed = 1;
12784 vcpu->mmio_cur_fragment = 0;
12786 vcpu->run->mmio.phys_addr = gpa;
12787 vcpu->run->mmio.len = min(8u, frag->len);
12788 vcpu->run->mmio.is_write = 0;
12789 vcpu->run->exit_reason = KVM_EXIT_MMIO;
12791 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
12795 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
12797 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
12798 unsigned int port);
12800 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu)
12802 int size = vcpu->arch.pio.size;
12803 int port = vcpu->arch.pio.port;
12805 vcpu->arch.pio.count = 0;
12806 if (vcpu->arch.sev_pio_count)
12807 return kvm_sev_es_outs(vcpu, size, port);
12811 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
12815 unsigned int count =
12816 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
12817 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count);
12819 /* memcpy done already by emulator_pio_out. */
12820 vcpu->arch.sev_pio_count -= count;
12821 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size;
12825 /* Emulation done by the kernel. */
12826 if (!vcpu->arch.sev_pio_count)
12830 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs;
12834 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
12835 unsigned int port);
12837 static void advance_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
12839 unsigned count = vcpu->arch.pio.count;
12840 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data);
12841 vcpu->arch.sev_pio_count -= count;
12842 vcpu->arch.sev_pio_data += count * vcpu->arch.pio.size;
12845 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
12847 int size = vcpu->arch.pio.size;
12848 int port = vcpu->arch.pio.port;
12850 advance_sev_es_emulated_ins(vcpu);
12851 if (vcpu->arch.sev_pio_count)
12852 return kvm_sev_es_ins(vcpu, size, port);
12856 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
12860 unsigned int count =
12861 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
12862 if (!__emulator_pio_in(vcpu, size, port, count))
12865 /* Emulation done by the kernel. */
12866 advance_sev_es_emulated_ins(vcpu);
12867 if (!vcpu->arch.sev_pio_count)
12871 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
12875 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
12876 unsigned int port, void *data, unsigned int count,
12879 vcpu->arch.sev_pio_data = data;
12880 vcpu->arch.sev_pio_count = count;
12881 return in ? kvm_sev_es_ins(vcpu, size, port)
12882 : kvm_sev_es_outs(vcpu, size, port);
12884 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
12886 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
12887 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
12888 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
12889 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
12890 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
12891 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
12892 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
12893 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
12894 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
12895 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
12896 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
12897 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
12898 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
12899 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
12900 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
12901 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
12902 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
12903 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
12904 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
12905 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
12906 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
12907 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
12908 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_update_request);
12909 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq);
12910 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
12911 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
12912 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
12913 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);