1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * derived from drivers/kvm/kvm_main.c
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
19 #include <linux/kvm_host.h>
25 #include "kvm_cache_regs.h"
26 #include "kvm_emulate.h"
34 #include <linux/clocksource.h>
35 #include <linux/interrupt.h>
36 #include <linux/kvm.h>
38 #include <linux/vmalloc.h>
39 #include <linux/export.h>
40 #include <linux/moduleparam.h>
41 #include <linux/mman.h>
42 #include <linux/highmem.h>
43 #include <linux/iommu.h>
44 #include <linux/intel-iommu.h>
45 #include <linux/cpufreq.h>
46 #include <linux/user-return-notifier.h>
47 #include <linux/srcu.h>
48 #include <linux/slab.h>
49 #include <linux/perf_event.h>
50 #include <linux/uaccess.h>
51 #include <linux/hash.h>
52 #include <linux/pci.h>
53 #include <linux/timekeeper_internal.h>
54 #include <linux/pvclock_gtod.h>
55 #include <linux/kvm_irqfd.h>
56 #include <linux/irqbypass.h>
57 #include <linux/sched/stat.h>
58 #include <linux/sched/isolation.h>
59 #include <linux/mem_encrypt.h>
60 #include <linux/entry-kvm.h>
61 #include <linux/suspend.h>
63 #include <trace/events/kvm.h>
65 #include <asm/debugreg.h>
70 #include <linux/kernel_stat.h>
71 #include <asm/fpu/api.h>
72 #include <asm/fpu/xcr.h>
73 #include <asm/fpu/xstate.h>
74 #include <asm/pvclock.h>
75 #include <asm/div64.h>
76 #include <asm/irq_remapping.h>
77 #include <asm/mshyperv.h>
78 #include <asm/hypervisor.h>
79 #include <asm/tlbflush.h>
80 #include <asm/intel_pt.h>
81 #include <asm/emulate_prefix.h>
83 #include <clocksource/hyperv_timer.h>
85 #define CREATE_TRACE_POINTS
88 #define MAX_IO_MSRS 256
89 #define KVM_MAX_MCE_BANKS 32
91 struct kvm_caps kvm_caps __read_mostly = {
92 .supported_mce_cap = MCG_CTL_P | MCG_SER_P,
94 EXPORT_SYMBOL_GPL(kvm_caps);
96 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
98 #define emul_to_vcpu(ctxt) \
99 ((struct kvm_vcpu *)(ctxt)->vcpu)
102 * - enable syscall per default because its emulated by KVM
103 * - enable LME and LMA per default on 64 bit KVM
107 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
109 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
112 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
114 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE)
116 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE
118 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
119 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
121 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
122 static void process_nmi(struct kvm_vcpu *vcpu);
123 static void process_smi(struct kvm_vcpu *vcpu);
124 static void enter_smm(struct kvm_vcpu *vcpu);
125 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
126 static void store_regs(struct kvm_vcpu *vcpu);
127 static int sync_regs(struct kvm_vcpu *vcpu);
128 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu);
130 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
131 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
133 struct kvm_x86_ops kvm_x86_ops __read_mostly;
135 #define KVM_X86_OP(func) \
136 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \
137 *(((struct kvm_x86_ops *)0)->func));
138 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
139 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
140 #include <asm/kvm-x86-ops.h>
141 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
142 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg);
144 static bool __read_mostly ignore_msrs = 0;
145 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
147 bool __read_mostly report_ignored_msrs = true;
148 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
149 EXPORT_SYMBOL_GPL(report_ignored_msrs);
151 unsigned int min_timer_period_us = 200;
152 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
154 static bool __read_mostly kvmclock_periodic_sync = true;
155 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
157 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
158 static u32 __read_mostly tsc_tolerance_ppm = 250;
159 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
162 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
163 * adaptive tuning starting from default advancement of 1000ns. '0' disables
164 * advancement entirely. Any other value is used as-is and disables adaptive
165 * tuning, i.e. allows privileged userspace to set an exact advancement time.
167 static int __read_mostly lapic_timer_advance_ns = -1;
168 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
170 static bool __read_mostly vector_hashing = true;
171 module_param(vector_hashing, bool, S_IRUGO);
173 bool __read_mostly enable_vmware_backdoor = false;
174 module_param(enable_vmware_backdoor, bool, S_IRUGO);
175 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
177 static bool __read_mostly force_emulation_prefix = false;
178 module_param(force_emulation_prefix, bool, S_IRUGO);
180 int __read_mostly pi_inject_timer = -1;
181 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
183 /* Enable/disable PMU virtualization */
184 bool __read_mostly enable_pmu = true;
185 EXPORT_SYMBOL_GPL(enable_pmu);
186 module_param(enable_pmu, bool, 0444);
188 bool __read_mostly eager_page_split = true;
189 module_param(eager_page_split, bool, 0644);
192 * Restoring the host value for MSRs that are only consumed when running in
193 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
194 * returns to userspace, i.e. the kernel can run with the guest's value.
196 #define KVM_MAX_NR_USER_RETURN_MSRS 16
198 struct kvm_user_return_msrs {
199 struct user_return_notifier urn;
201 struct kvm_user_return_msr_values {
204 } values[KVM_MAX_NR_USER_RETURN_MSRS];
207 u32 __read_mostly kvm_nr_uret_msrs;
208 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs);
209 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS];
210 static struct kvm_user_return_msrs __percpu *user_return_msrs;
212 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
213 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
214 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
215 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE)
217 u64 __read_mostly host_efer;
218 EXPORT_SYMBOL_GPL(host_efer);
220 bool __read_mostly allow_smaller_maxphyaddr = 0;
221 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
223 bool __read_mostly enable_apicv = true;
224 EXPORT_SYMBOL_GPL(enable_apicv);
226 u64 __read_mostly host_xss;
227 EXPORT_SYMBOL_GPL(host_xss);
229 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
230 KVM_GENERIC_VM_STATS(),
231 STATS_DESC_COUNTER(VM, mmu_shadow_zapped),
232 STATS_DESC_COUNTER(VM, mmu_pte_write),
233 STATS_DESC_COUNTER(VM, mmu_pde_zapped),
234 STATS_DESC_COUNTER(VM, mmu_flooded),
235 STATS_DESC_COUNTER(VM, mmu_recycled),
236 STATS_DESC_COUNTER(VM, mmu_cache_miss),
237 STATS_DESC_ICOUNTER(VM, mmu_unsync),
238 STATS_DESC_ICOUNTER(VM, pages_4k),
239 STATS_DESC_ICOUNTER(VM, pages_2m),
240 STATS_DESC_ICOUNTER(VM, pages_1g),
241 STATS_DESC_ICOUNTER(VM, nx_lpage_splits),
242 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size),
243 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions)
246 const struct kvm_stats_header kvm_vm_stats_header = {
247 .name_size = KVM_STATS_NAME_SIZE,
248 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
249 .id_offset = sizeof(struct kvm_stats_header),
250 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
251 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
252 sizeof(kvm_vm_stats_desc),
255 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
256 KVM_GENERIC_VCPU_STATS(),
257 STATS_DESC_COUNTER(VCPU, pf_taken),
258 STATS_DESC_COUNTER(VCPU, pf_fixed),
259 STATS_DESC_COUNTER(VCPU, pf_emulate),
260 STATS_DESC_COUNTER(VCPU, pf_spurious),
261 STATS_DESC_COUNTER(VCPU, pf_fast),
262 STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created),
263 STATS_DESC_COUNTER(VCPU, pf_guest),
264 STATS_DESC_COUNTER(VCPU, tlb_flush),
265 STATS_DESC_COUNTER(VCPU, invlpg),
266 STATS_DESC_COUNTER(VCPU, exits),
267 STATS_DESC_COUNTER(VCPU, io_exits),
268 STATS_DESC_COUNTER(VCPU, mmio_exits),
269 STATS_DESC_COUNTER(VCPU, signal_exits),
270 STATS_DESC_COUNTER(VCPU, irq_window_exits),
271 STATS_DESC_COUNTER(VCPU, nmi_window_exits),
272 STATS_DESC_COUNTER(VCPU, l1d_flush),
273 STATS_DESC_COUNTER(VCPU, halt_exits),
274 STATS_DESC_COUNTER(VCPU, request_irq_exits),
275 STATS_DESC_COUNTER(VCPU, irq_exits),
276 STATS_DESC_COUNTER(VCPU, host_state_reload),
277 STATS_DESC_COUNTER(VCPU, fpu_reload),
278 STATS_DESC_COUNTER(VCPU, insn_emulation),
279 STATS_DESC_COUNTER(VCPU, insn_emulation_fail),
280 STATS_DESC_COUNTER(VCPU, hypercalls),
281 STATS_DESC_COUNTER(VCPU, irq_injections),
282 STATS_DESC_COUNTER(VCPU, nmi_injections),
283 STATS_DESC_COUNTER(VCPU, req_event),
284 STATS_DESC_COUNTER(VCPU, nested_run),
285 STATS_DESC_COUNTER(VCPU, directed_yield_attempted),
286 STATS_DESC_COUNTER(VCPU, directed_yield_successful),
287 STATS_DESC_COUNTER(VCPU, preemption_reported),
288 STATS_DESC_COUNTER(VCPU, preemption_other),
289 STATS_DESC_ICOUNTER(VCPU, guest_mode),
290 STATS_DESC_COUNTER(VCPU, notify_window_exits),
293 const struct kvm_stats_header kvm_vcpu_stats_header = {
294 .name_size = KVM_STATS_NAME_SIZE,
295 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
296 .id_offset = sizeof(struct kvm_stats_header),
297 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
298 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
299 sizeof(kvm_vcpu_stats_desc),
302 u64 __read_mostly host_xcr0;
304 static struct kmem_cache *x86_emulator_cache;
307 * When called, it means the previous get/set msr reached an invalid msr.
308 * Return true if we want to ignore/silent this failed msr access.
310 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write)
312 const char *op = write ? "wrmsr" : "rdmsr";
315 if (report_ignored_msrs)
316 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
321 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
327 static struct kmem_cache *kvm_alloc_emulator_cache(void)
329 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
330 unsigned int size = sizeof(struct x86_emulate_ctxt);
332 return kmem_cache_create_usercopy("x86_emulator", size,
333 __alignof__(struct x86_emulate_ctxt),
334 SLAB_ACCOUNT, useroffset,
335 size - useroffset, NULL);
338 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
340 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
343 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
344 vcpu->arch.apf.gfns[i] = ~0;
347 static void kvm_on_user_return(struct user_return_notifier *urn)
350 struct kvm_user_return_msrs *msrs
351 = container_of(urn, struct kvm_user_return_msrs, urn);
352 struct kvm_user_return_msr_values *values;
356 * Disabling irqs at this point since the following code could be
357 * interrupted and executed through kvm_arch_hardware_disable()
359 local_irq_save(flags);
360 if (msrs->registered) {
361 msrs->registered = false;
362 user_return_notifier_unregister(urn);
364 local_irq_restore(flags);
365 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) {
366 values = &msrs->values[slot];
367 if (values->host != values->curr) {
368 wrmsrl(kvm_uret_msrs_list[slot], values->host);
369 values->curr = values->host;
374 static int kvm_probe_user_return_msr(u32 msr)
380 ret = rdmsrl_safe(msr, &val);
383 ret = wrmsrl_safe(msr, val);
389 int kvm_add_user_return_msr(u32 msr)
391 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS);
393 if (kvm_probe_user_return_msr(msr))
396 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr;
397 return kvm_nr_uret_msrs++;
399 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr);
401 int kvm_find_user_return_msr(u32 msr)
405 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
406 if (kvm_uret_msrs_list[i] == msr)
411 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr);
413 static void kvm_user_return_msr_cpu_online(void)
415 unsigned int cpu = smp_processor_id();
416 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
420 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
421 rdmsrl_safe(kvm_uret_msrs_list[i], &value);
422 msrs->values[i].host = value;
423 msrs->values[i].curr = value;
427 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
429 unsigned int cpu = smp_processor_id();
430 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
433 value = (value & mask) | (msrs->values[slot].host & ~mask);
434 if (value == msrs->values[slot].curr)
436 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value);
440 msrs->values[slot].curr = value;
441 if (!msrs->registered) {
442 msrs->urn.on_user_return = kvm_on_user_return;
443 user_return_notifier_register(&msrs->urn);
444 msrs->registered = true;
448 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
450 static void drop_user_return_notifiers(void)
452 unsigned int cpu = smp_processor_id();
453 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
455 if (msrs->registered)
456 kvm_on_user_return(&msrs->urn);
459 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
461 return vcpu->arch.apic_base;
463 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
465 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
467 return kvm_apic_mode(kvm_get_apic_base(vcpu));
469 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
471 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
473 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
474 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
475 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
476 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
478 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
480 if (!msr_info->host_initiated) {
481 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
483 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
487 kvm_lapic_set_base(vcpu, msr_info->data);
488 kvm_recalculate_apic_map(vcpu->kvm);
491 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
494 * Handle a fault on a hardware virtualization (VMX or SVM) instruction.
496 * Hardware virtualization extension instructions may fault if a reboot turns
497 * off virtualization while processes are running. Usually after catching the
498 * fault we just panic; during reboot instead the instruction is ignored.
500 noinstr void kvm_spurious_fault(void)
502 /* Fault while not rebooting. We want the trace. */
503 BUG_ON(!kvm_rebooting);
505 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
507 #define EXCPT_BENIGN 0
508 #define EXCPT_CONTRIBUTORY 1
511 static int exception_class(int vector)
521 return EXCPT_CONTRIBUTORY;
528 #define EXCPT_FAULT 0
530 #define EXCPT_ABORT 2
531 #define EXCPT_INTERRUPT 3
533 static int exception_type(int vector)
537 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
538 return EXCPT_INTERRUPT;
542 /* #DB is trap, as instruction watchpoints are handled elsewhere */
543 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
546 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
549 /* Reserved exceptions will result in fault */
553 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
555 unsigned nr = vcpu->arch.exception.nr;
556 bool has_payload = vcpu->arch.exception.has_payload;
557 unsigned long payload = vcpu->arch.exception.payload;
565 * "Certain debug exceptions may clear bit 0-3. The
566 * remaining contents of the DR6 register are never
567 * cleared by the processor".
569 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
571 * In order to reflect the #DB exception payload in guest
572 * dr6, three components need to be considered: active low
573 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
575 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
576 * In the target guest dr6:
577 * FIXED_1 bits should always be set.
578 * Active low bits should be cleared if 1-setting in payload.
579 * Active high bits should be set if 1-setting in payload.
581 * Note, the payload is compatible with the pending debug
582 * exceptions/exit qualification under VMX, that active_low bits
583 * are active high in payload.
584 * So they need to be flipped for DR6.
586 vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
587 vcpu->arch.dr6 |= payload;
588 vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW;
591 * The #DB payload is defined as compatible with the 'pending
592 * debug exceptions' field under VMX, not DR6. While bit 12 is
593 * defined in the 'pending debug exceptions' field (enabled
594 * breakpoint), it is reserved and must be zero in DR6.
596 vcpu->arch.dr6 &= ~BIT(12);
599 vcpu->arch.cr2 = payload;
603 vcpu->arch.exception.has_payload = false;
604 vcpu->arch.exception.payload = 0;
606 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
608 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
609 unsigned nr, bool has_error, u32 error_code,
610 bool has_payload, unsigned long payload, bool reinject)
615 kvm_make_request(KVM_REQ_EVENT, vcpu);
617 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
621 * On vmentry, vcpu->arch.exception.pending is only
622 * true if an event injection was blocked by
623 * nested_run_pending. In that case, however,
624 * vcpu_enter_guest requests an immediate exit,
625 * and the guest shouldn't proceed far enough to
628 WARN_ON_ONCE(vcpu->arch.exception.pending);
629 vcpu->arch.exception.injected = true;
630 if (WARN_ON_ONCE(has_payload)) {
632 * A reinjected event has already
633 * delivered its payload.
639 vcpu->arch.exception.pending = true;
640 vcpu->arch.exception.injected = false;
642 vcpu->arch.exception.has_error_code = has_error;
643 vcpu->arch.exception.nr = nr;
644 vcpu->arch.exception.error_code = error_code;
645 vcpu->arch.exception.has_payload = has_payload;
646 vcpu->arch.exception.payload = payload;
647 if (!is_guest_mode(vcpu))
648 kvm_deliver_exception_payload(vcpu);
652 /* to check exception */
653 prev_nr = vcpu->arch.exception.nr;
654 if (prev_nr == DF_VECTOR) {
655 /* triple fault -> shutdown */
656 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
659 class1 = exception_class(prev_nr);
660 class2 = exception_class(nr);
661 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
662 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664 * Generate double fault per SDM Table 5-5. Set
665 * exception.pending = true so that the double fault
666 * can trigger a nested vmexit.
668 vcpu->arch.exception.pending = true;
669 vcpu->arch.exception.injected = false;
670 vcpu->arch.exception.has_error_code = true;
671 vcpu->arch.exception.nr = DF_VECTOR;
672 vcpu->arch.exception.error_code = 0;
673 vcpu->arch.exception.has_payload = false;
674 vcpu->arch.exception.payload = 0;
676 /* replace previous exception with a new one in a hope
677 that instruction re-execution will regenerate lost
682 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
684 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
686 EXPORT_SYMBOL_GPL(kvm_queue_exception);
688 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
690 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
692 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
694 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
695 unsigned long payload)
697 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
699 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
701 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
702 u32 error_code, unsigned long payload)
704 kvm_multiple_exception(vcpu, nr, true, error_code,
705 true, payload, false);
708 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
711 kvm_inject_gp(vcpu, 0);
713 return kvm_skip_emulated_instruction(vcpu);
717 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
719 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err)
722 kvm_inject_gp(vcpu, 0);
726 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
727 EMULTYPE_COMPLETE_USER_EXIT);
730 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
732 ++vcpu->stat.pf_guest;
733 vcpu->arch.exception.nested_apf =
734 is_guest_mode(vcpu) && fault->async_page_fault;
735 if (vcpu->arch.exception.nested_apf) {
736 vcpu->arch.apf.nested_apf_token = fault->address;
737 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
739 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
743 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
745 /* Returns true if the page fault was immediately morphed into a VM-Exit. */
746 bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
747 struct x86_exception *fault)
749 struct kvm_mmu *fault_mmu;
750 WARN_ON_ONCE(fault->vector != PF_VECTOR);
752 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
756 * Invalidate the TLB entry for the faulting address, if it exists,
757 * else the access will fault indefinitely (and to emulate hardware).
759 if ((fault->error_code & PFERR_PRESENT_MASK) &&
760 !(fault->error_code & PFERR_RSVD_MASK))
761 kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address,
762 fault_mmu->root.hpa);
765 * A workaround for KVM's bad exception handling. If KVM injected an
766 * exception into L2, and L2 encountered a #PF while vectoring the
767 * injected exception, manually check to see if L1 wants to intercept
768 * #PF, otherwise queuing the #PF will lead to #DF or a lost exception.
769 * In all other cases, defer the check to nested_ops->check_events(),
770 * which will correctly handle priority (this does not). Note, other
771 * exceptions, e.g. #GP, are theoretically affected, #PF is simply the
772 * most problematic, e.g. when L0 and L1 are both intercepting #PF for
775 * TODO: Rewrite exception handling to track injected and pending
776 * (VM-Exit) exceptions separately.
778 if (unlikely(vcpu->arch.exception.injected && is_guest_mode(vcpu)) &&
779 kvm_x86_ops.nested_ops->handle_page_fault_workaround(vcpu, fault))
782 fault_mmu->inject_page_fault(vcpu, fault);
785 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
787 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
789 atomic_inc(&vcpu->arch.nmi_queued);
790 kvm_make_request(KVM_REQ_NMI, vcpu);
792 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
794 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
796 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
798 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
800 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
802 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
804 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
807 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
808 * a #GP and return false.
810 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
812 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl)
814 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
817 EXPORT_SYMBOL_GPL(kvm_require_cpl);
819 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
821 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
824 kvm_queue_exception(vcpu, UD_VECTOR);
827 EXPORT_SYMBOL_GPL(kvm_require_dr);
829 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
831 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2);
835 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
837 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
839 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
840 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
844 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
847 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated
850 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn),
851 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL);
852 if (real_gpa == UNMAPPED_GVA)
855 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */
856 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte,
857 cr3 & GENMASK(11, 5), sizeof(pdpte));
861 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
862 if ((pdpte[i] & PT_PRESENT_MASK) &&
863 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
869 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled.
870 * Shadow page roots need to be reconstructed instead.
872 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)))
873 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT);
875 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
876 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
877 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
878 vcpu->arch.pdptrs_from_userspace = false;
882 EXPORT_SYMBOL_GPL(load_pdptrs);
884 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
886 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
887 kvm_clear_async_pf_completion_queue(vcpu);
888 kvm_async_pf_hash_reset(vcpu);
891 * Clearing CR0.PG is defined to flush the TLB from the guest's
894 if (!(cr0 & X86_CR0_PG))
895 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
898 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS)
899 kvm_mmu_reset_context(vcpu);
901 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
902 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
903 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
904 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
906 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
908 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
910 unsigned long old_cr0 = kvm_read_cr0(vcpu);
915 if (cr0 & 0xffffffff00000000UL)
919 cr0 &= ~CR0_RESERVED_BITS;
921 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
924 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
928 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
929 (cr0 & X86_CR0_PG)) {
934 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
939 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
940 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) &&
941 !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
944 if (!(cr0 & X86_CR0_PG) &&
945 (is_64_bit_mode(vcpu) || kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)))
948 static_call(kvm_x86_set_cr0)(vcpu, cr0);
950 kvm_post_set_cr0(vcpu, old_cr0, cr0);
954 EXPORT_SYMBOL_GPL(kvm_set_cr0);
956 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
958 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
960 EXPORT_SYMBOL_GPL(kvm_lmsw);
962 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
964 if (vcpu->arch.guest_state_protected)
967 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
969 if (vcpu->arch.xcr0 != host_xcr0)
970 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
972 if (vcpu->arch.xsaves_enabled &&
973 vcpu->arch.ia32_xss != host_xss)
974 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
977 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
978 if (static_cpu_has(X86_FEATURE_PKU) &&
979 vcpu->arch.pkru != vcpu->arch.host_pkru &&
980 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
981 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)))
982 write_pkru(vcpu->arch.pkru);
983 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
985 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
987 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
989 if (vcpu->arch.guest_state_protected)
992 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
993 if (static_cpu_has(X86_FEATURE_PKU) &&
994 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
995 kvm_read_cr4_bits(vcpu, X86_CR4_PKE))) {
996 vcpu->arch.pkru = rdpkru();
997 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
998 write_pkru(vcpu->arch.host_pkru);
1000 #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
1002 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
1004 if (vcpu->arch.xcr0 != host_xcr0)
1005 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
1007 if (vcpu->arch.xsaves_enabled &&
1008 vcpu->arch.ia32_xss != host_xss)
1009 wrmsrl(MSR_IA32_XSS, host_xss);
1013 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
1015 static inline u64 kvm_guest_supported_xcr0(struct kvm_vcpu *vcpu)
1017 return vcpu->arch.guest_fpu.fpstate->user_xfeatures;
1020 #ifdef CONFIG_X86_64
1021 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu)
1023 return kvm_guest_supported_xcr0(vcpu) & XFEATURE_MASK_USER_DYNAMIC;
1027 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
1030 u64 old_xcr0 = vcpu->arch.xcr0;
1033 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
1034 if (index != XCR_XFEATURE_ENABLED_MASK)
1036 if (!(xcr0 & XFEATURE_MASK_FP))
1038 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
1042 * Do not allow the guest to set bits that we do not support
1043 * saving. However, xcr0 bit 0 is always set, even if the
1044 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()).
1046 valid_bits = kvm_guest_supported_xcr0(vcpu) | XFEATURE_MASK_FP;
1047 if (xcr0 & ~valid_bits)
1050 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
1051 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
1054 if (xcr0 & XFEATURE_MASK_AVX512) {
1055 if (!(xcr0 & XFEATURE_MASK_YMM))
1057 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
1061 if ((xcr0 & XFEATURE_MASK_XTILE) &&
1062 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE))
1065 vcpu->arch.xcr0 = xcr0;
1067 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
1068 kvm_update_cpuid_runtime(vcpu);
1072 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu)
1074 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 ||
1075 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) {
1076 kvm_inject_gp(vcpu, 0);
1080 return kvm_skip_emulated_instruction(vcpu);
1082 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv);
1084 bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1086 if (cr4 & cr4_reserved_bits)
1089 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
1092 return static_call(kvm_x86_is_valid_cr4)(vcpu, cr4);
1094 EXPORT_SYMBOL_GPL(kvm_is_valid_cr4);
1096 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
1098 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
1099 kvm_mmu_reset_context(vcpu);
1102 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB
1103 * according to the SDM; however, stale prev_roots could be reused
1104 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we
1105 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST
1106 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed,
1110 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE))
1111 kvm_mmu_unload(vcpu);
1114 * The TLB has to be flushed for all PCIDs if any of the following
1115 * (architecturally required) changes happen:
1116 * - CR4.PCIDE is changed from 1 to 0
1117 * - CR4.PGE is toggled
1119 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT.
1121 if (((cr4 ^ old_cr4) & X86_CR4_PGE) ||
1122 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1123 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1126 * The TLB has to be flushed for the current PCID if any of the
1127 * following (architecturally required) changes happen:
1128 * - CR4.SMEP is changed from 0 to 1
1129 * - CR4.PAE is toggled
1131 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) ||
1132 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP)))
1133 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1136 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1138 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1140 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1142 if (!kvm_is_valid_cr4(vcpu, cr4))
1145 if (is_long_mode(vcpu)) {
1146 if (!(cr4 & X86_CR4_PAE))
1148 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1150 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1151 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS)
1152 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
1155 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1156 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
1159 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1160 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1164 static_call(kvm_x86_set_cr4)(vcpu, cr4);
1166 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1170 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1172 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid)
1174 struct kvm_mmu *mmu = vcpu->arch.mmu;
1175 unsigned long roots_to_free = 0;
1179 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but
1180 * this is reachable when running EPT=1 and unrestricted_guest=0, and
1181 * also via the emulator. KVM's TDP page tables are not in the scope of
1182 * the invalidation, but the guest's TLB entries need to be flushed as
1183 * the CPU may have cached entries in its TLB for the target PCID.
1185 if (unlikely(tdp_enabled)) {
1186 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1191 * If neither the current CR3 nor any of the prev_roots use the given
1192 * PCID, then nothing needs to be done here because a resync will
1193 * happen anyway before switching to any other CR3.
1195 if (kvm_get_active_pcid(vcpu) == pcid) {
1196 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1197 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1201 * If PCID is disabled, there is no need to free prev_roots even if the
1202 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB
1205 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
1208 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
1209 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid)
1210 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
1212 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
1215 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1217 bool skip_tlb_flush = false;
1218 unsigned long pcid = 0;
1219 #ifdef CONFIG_X86_64
1220 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
1223 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1224 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1225 pcid = cr3 & X86_CR3_PCID_MASK;
1229 /* PDPTRs are always reloaded for PAE paging. */
1230 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu))
1231 goto handle_tlb_flush;
1234 * Do not condition the GPA check on long mode, this helper is used to
1235 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that
1236 * the current vCPU mode is accurate.
1238 if (kvm_vcpu_is_illegal_gpa(vcpu, cr3))
1241 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3))
1244 if (cr3 != kvm_read_cr3(vcpu))
1245 kvm_mmu_new_pgd(vcpu, cr3);
1247 vcpu->arch.cr3 = cr3;
1248 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
1249 /* Do not call post_set_cr3, we do not get here for confidential guests. */
1253 * A load of CR3 that flushes the TLB flushes only the current PCID,
1254 * even if PCID is disabled, in which case PCID=0 is flushed. It's a
1255 * moot point in the end because _disabling_ PCID will flush all PCIDs,
1256 * and it's impossible to use a non-zero PCID when PCID is disabled,
1257 * i.e. only PCID=0 can be relevant.
1259 if (!skip_tlb_flush)
1260 kvm_invalidate_pcid(vcpu, pcid);
1264 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1266 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1268 if (cr8 & CR8_RESERVED_BITS)
1270 if (lapic_in_kernel(vcpu))
1271 kvm_lapic_set_tpr(vcpu, cr8);
1273 vcpu->arch.cr8 = cr8;
1276 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1278 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1280 if (lapic_in_kernel(vcpu))
1281 return kvm_lapic_get_cr8(vcpu);
1283 return vcpu->arch.cr8;
1285 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1287 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1291 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1292 for (i = 0; i < KVM_NR_DB_REGS; i++)
1293 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1297 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1301 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1302 dr7 = vcpu->arch.guest_debug_dr7;
1304 dr7 = vcpu->arch.dr7;
1305 static_call(kvm_x86_set_dr7)(vcpu, dr7);
1306 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1307 if (dr7 & DR7_BP_EN_MASK)
1308 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1310 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1312 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1314 u64 fixed = DR6_FIXED_1;
1316 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1319 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1320 fixed |= DR6_BUS_LOCK;
1324 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1326 size_t size = ARRAY_SIZE(vcpu->arch.db);
1330 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1331 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1332 vcpu->arch.eff_db[dr] = val;
1336 if (!kvm_dr6_valid(val))
1338 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1342 if (!kvm_dr7_valid(val))
1344 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1345 kvm_update_dr7(vcpu);
1351 EXPORT_SYMBOL_GPL(kvm_set_dr);
1353 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1355 size_t size = ARRAY_SIZE(vcpu->arch.db);
1359 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1363 *val = vcpu->arch.dr6;
1367 *val = vcpu->arch.dr7;
1371 EXPORT_SYMBOL_GPL(kvm_get_dr);
1373 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu)
1375 u32 ecx = kvm_rcx_read(vcpu);
1378 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) {
1379 kvm_inject_gp(vcpu, 0);
1383 kvm_rax_write(vcpu, (u32)data);
1384 kvm_rdx_write(vcpu, data >> 32);
1385 return kvm_skip_emulated_instruction(vcpu);
1387 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc);
1390 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1391 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1393 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1394 * extract the supported MSRs from the related const lists.
1395 * msrs_to_save is selected from the msrs_to_save_all to reflect the
1396 * capabilities of the host cpu. This capabilities test skips MSRs that are
1397 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
1398 * may depend on host virtualization features rather than host cpu features.
1401 static const u32 msrs_to_save_all[] = {
1402 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1404 #ifdef CONFIG_X86_64
1405 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1407 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1408 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1410 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1411 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1412 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1413 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1414 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1415 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1416 MSR_IA32_UMWAIT_CONTROL,
1418 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1419 MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
1420 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1421 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1422 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1423 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1424 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1425 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1426 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1427 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1428 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1429 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1430 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1431 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1432 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1433 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1434 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1435 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1436 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1437 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1438 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1439 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1440 MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
1442 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
1443 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
1444 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
1445 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
1446 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
1447 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
1448 MSR_IA32_XFD, MSR_IA32_XFD_ERR,
1451 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
1452 static unsigned num_msrs_to_save;
1454 static const u32 emulated_msrs_all[] = {
1455 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1456 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1457 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1458 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1459 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1460 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1461 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1463 HV_X64_MSR_VP_INDEX,
1464 HV_X64_MSR_VP_RUNTIME,
1465 HV_X64_MSR_SCONTROL,
1466 HV_X64_MSR_STIMER0_CONFIG,
1467 HV_X64_MSR_VP_ASSIST_PAGE,
1468 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1469 HV_X64_MSR_TSC_EMULATION_STATUS,
1470 HV_X64_MSR_SYNDBG_OPTIONS,
1471 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1472 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1473 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1475 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1476 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1478 MSR_IA32_TSC_ADJUST,
1479 MSR_IA32_TSC_DEADLINE,
1480 MSR_IA32_ARCH_CAPABILITIES,
1481 MSR_IA32_PERF_CAPABILITIES,
1482 MSR_IA32_MISC_ENABLE,
1483 MSR_IA32_MCG_STATUS,
1485 MSR_IA32_MCG_EXT_CTL,
1489 MSR_MISC_FEATURES_ENABLES,
1490 MSR_AMD64_VIRT_SPEC_CTRL,
1491 MSR_AMD64_TSC_RATIO,
1496 * The following list leaves out MSRs whose values are determined
1497 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1498 * We always support the "true" VMX control MSRs, even if the host
1499 * processor does not, so I am putting these registers here rather
1500 * than in msrs_to_save_all.
1503 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1504 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1505 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1506 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1508 MSR_IA32_VMX_CR0_FIXED0,
1509 MSR_IA32_VMX_CR4_FIXED0,
1510 MSR_IA32_VMX_VMCS_ENUM,
1511 MSR_IA32_VMX_PROCBASED_CTLS2,
1512 MSR_IA32_VMX_EPT_VPID_CAP,
1513 MSR_IA32_VMX_VMFUNC,
1516 MSR_KVM_POLL_CONTROL,
1519 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1520 static unsigned num_emulated_msrs;
1523 * List of msr numbers which are used to expose MSR-based features that
1524 * can be used by a hypervisor to validate requested CPU features.
1526 static const u32 msr_based_features_all[] = {
1528 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1529 MSR_IA32_VMX_PINBASED_CTLS,
1530 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1531 MSR_IA32_VMX_PROCBASED_CTLS,
1532 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1533 MSR_IA32_VMX_EXIT_CTLS,
1534 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1535 MSR_IA32_VMX_ENTRY_CTLS,
1537 MSR_IA32_VMX_CR0_FIXED0,
1538 MSR_IA32_VMX_CR0_FIXED1,
1539 MSR_IA32_VMX_CR4_FIXED0,
1540 MSR_IA32_VMX_CR4_FIXED1,
1541 MSR_IA32_VMX_VMCS_ENUM,
1542 MSR_IA32_VMX_PROCBASED_CTLS2,
1543 MSR_IA32_VMX_EPT_VPID_CAP,
1544 MSR_IA32_VMX_VMFUNC,
1548 MSR_IA32_ARCH_CAPABILITIES,
1549 MSR_IA32_PERF_CAPABILITIES,
1552 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
1553 static unsigned int num_msr_based_features;
1555 static u64 kvm_get_arch_capabilities(void)
1559 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1560 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
1563 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1564 * the nested hypervisor runs with NX huge pages. If it is not,
1565 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other
1566 * L1 guests, so it need not worry about its own (L2) guests.
1568 data |= ARCH_CAP_PSCHANGE_MC_NO;
1571 * If we're doing cache flushes (either "always" or "cond")
1572 * we will do one whenever the guest does a vmlaunch/vmresume.
1573 * If an outer hypervisor is doing the cache flush for us
1574 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1575 * capability to the guest too, and if EPT is disabled we're not
1576 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1577 * require a nested hypervisor to do a flush of its own.
1579 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1580 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1582 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1583 data |= ARCH_CAP_RDCL_NO;
1584 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1585 data |= ARCH_CAP_SSB_NO;
1586 if (!boot_cpu_has_bug(X86_BUG_MDS))
1587 data |= ARCH_CAP_MDS_NO;
1589 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1591 * If RTM=0 because the kernel has disabled TSX, the host might
1592 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1593 * and therefore knows that there cannot be TAA) but keep
1594 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1595 * and we want to allow migrating those guests to tsx=off hosts.
1597 data &= ~ARCH_CAP_TAA_NO;
1598 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1599 data |= ARCH_CAP_TAA_NO;
1602 * Nothing to do here; we emulate TSX_CTRL if present on the
1603 * host so the guest can choose between disabling TSX or
1604 * using VERW to clear CPU buffers.
1611 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1613 switch (msr->index) {
1614 case MSR_IA32_ARCH_CAPABILITIES:
1615 msr->data = kvm_get_arch_capabilities();
1617 case MSR_IA32_UCODE_REV:
1618 rdmsrl_safe(msr->index, &msr->data);
1621 return static_call(kvm_x86_get_msr_feature)(msr);
1626 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1628 struct kvm_msr_entry msr;
1632 r = kvm_get_msr_feature(&msr);
1634 if (r == KVM_MSR_RET_INVALID) {
1635 /* Unconditionally clear the output for simplicity */
1637 if (kvm_msr_ignored_check(index, 0, false))
1649 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1651 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1654 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1657 if (efer & (EFER_LME | EFER_LMA) &&
1658 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1661 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1667 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1669 if (efer & efer_reserved_bits)
1672 return __kvm_valid_efer(vcpu, efer);
1674 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1676 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1678 u64 old_efer = vcpu->arch.efer;
1679 u64 efer = msr_info->data;
1682 if (efer & efer_reserved_bits)
1685 if (!msr_info->host_initiated) {
1686 if (!__kvm_valid_efer(vcpu, efer))
1689 if (is_paging(vcpu) &&
1690 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1695 efer |= vcpu->arch.efer & EFER_LMA;
1697 r = static_call(kvm_x86_set_efer)(vcpu, efer);
1703 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
1704 kvm_mmu_reset_context(vcpu);
1709 void kvm_enable_efer_bits(u64 mask)
1711 efer_reserved_bits &= ~mask;
1713 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1715 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1717 struct kvm_x86_msr_filter *msr_filter;
1718 struct msr_bitmap_range *ranges;
1719 struct kvm *kvm = vcpu->kvm;
1724 /* x2APIC MSRs do not support filtering. */
1725 if (index >= 0x800 && index <= 0x8ff)
1728 idx = srcu_read_lock(&kvm->srcu);
1730 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu);
1736 allowed = msr_filter->default_allow;
1737 ranges = msr_filter->ranges;
1739 for (i = 0; i < msr_filter->count; i++) {
1740 u32 start = ranges[i].base;
1741 u32 end = start + ranges[i].nmsrs;
1742 u32 flags = ranges[i].flags;
1743 unsigned long *bitmap = ranges[i].bitmap;
1745 if ((index >= start) && (index < end) && (flags & type)) {
1746 allowed = !!test_bit(index - start, bitmap);
1752 srcu_read_unlock(&kvm->srcu, idx);
1756 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1759 * Write @data into the MSR specified by @index. Select MSR specific fault
1760 * checks are bypassed if @host_initiated is %true.
1761 * Returns 0 on success, non-0 otherwise.
1762 * Assumes vcpu_load() was already called.
1764 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1765 bool host_initiated)
1767 struct msr_data msr;
1772 case MSR_KERNEL_GS_BASE:
1775 if (is_noncanonical_address(data, vcpu))
1778 case MSR_IA32_SYSENTER_EIP:
1779 case MSR_IA32_SYSENTER_ESP:
1781 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1782 * non-canonical address is written on Intel but not on
1783 * AMD (which ignores the top 32-bits, because it does
1784 * not implement 64-bit SYSENTER).
1786 * 64-bit code should hence be able to write a non-canonical
1787 * value on AMD. Making the address canonical ensures that
1788 * vmentry does not fail on Intel after writing a non-canonical
1789 * value, and that something deterministic happens if the guest
1790 * invokes 64-bit SYSENTER.
1792 data = __canonical_address(data, vcpu_virt_addr_bits(vcpu));
1795 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1798 if (!host_initiated &&
1799 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1800 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1804 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
1805 * incomplete and conflicting architectural behavior. Current
1806 * AMD CPUs completely ignore bits 63:32, i.e. they aren't
1807 * reserved and always read as zeros. Enforce Intel's reserved
1808 * bits check if and only if the guest CPU is Intel, and clear
1809 * the bits in all other cases. This ensures cross-vendor
1810 * migration will provide consistent behavior for the guest.
1812 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0)
1821 msr.host_initiated = host_initiated;
1823 return static_call(kvm_x86_set_msr)(vcpu, &msr);
1826 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1827 u32 index, u64 data, bool host_initiated)
1829 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1831 if (ret == KVM_MSR_RET_INVALID)
1832 if (kvm_msr_ignored_check(index, data, true))
1839 * Read the MSR specified by @index into @data. Select MSR specific fault
1840 * checks are bypassed if @host_initiated is %true.
1841 * Returns 0 on success, non-0 otherwise.
1842 * Assumes vcpu_load() was already called.
1844 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1845 bool host_initiated)
1847 struct msr_data msr;
1852 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1855 if (!host_initiated &&
1856 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1857 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1863 msr.host_initiated = host_initiated;
1865 ret = static_call(kvm_x86_get_msr)(vcpu, &msr);
1871 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1872 u32 index, u64 *data, bool host_initiated)
1874 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1876 if (ret == KVM_MSR_RET_INVALID) {
1877 /* Unconditionally clear *data for simplicity */
1879 if (kvm_msr_ignored_check(index, 0, false))
1886 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1888 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1889 return KVM_MSR_RET_FILTERED;
1890 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1893 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data)
1895 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1896 return KVM_MSR_RET_FILTERED;
1897 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1900 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1902 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1904 EXPORT_SYMBOL_GPL(kvm_get_msr);
1906 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1908 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1910 EXPORT_SYMBOL_GPL(kvm_set_msr);
1912 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu)
1914 if (!vcpu->run->msr.error) {
1915 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1916 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1920 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu)
1922 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error);
1925 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
1927 complete_userspace_rdmsr(vcpu);
1928 return complete_emulated_msr_access(vcpu);
1931 static int complete_fast_msr_access(struct kvm_vcpu *vcpu)
1933 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error);
1936 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu)
1938 complete_userspace_rdmsr(vcpu);
1939 return complete_fast_msr_access(vcpu);
1942 static u64 kvm_msr_reason(int r)
1945 case KVM_MSR_RET_INVALID:
1946 return KVM_MSR_EXIT_REASON_UNKNOWN;
1947 case KVM_MSR_RET_FILTERED:
1948 return KVM_MSR_EXIT_REASON_FILTER;
1950 return KVM_MSR_EXIT_REASON_INVAL;
1954 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
1955 u32 exit_reason, u64 data,
1956 int (*completion)(struct kvm_vcpu *vcpu),
1959 u64 msr_reason = kvm_msr_reason(r);
1961 /* Check if the user wanted to know about this MSR fault */
1962 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
1965 vcpu->run->exit_reason = exit_reason;
1966 vcpu->run->msr.error = 0;
1967 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
1968 vcpu->run->msr.reason = msr_reason;
1969 vcpu->run->msr.index = index;
1970 vcpu->run->msr.data = data;
1971 vcpu->arch.complete_userspace_io = completion;
1976 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1978 u32 ecx = kvm_rcx_read(vcpu);
1982 r = kvm_get_msr_with_filter(vcpu, ecx, &data);
1985 trace_kvm_msr_read(ecx, data);
1987 kvm_rax_write(vcpu, data & -1u);
1988 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1990 /* MSR read failed? See if we should ask user space */
1991 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0,
1992 complete_fast_rdmsr, r))
1994 trace_kvm_msr_read_ex(ecx);
1997 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
1999 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
2001 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
2003 u32 ecx = kvm_rcx_read(vcpu);
2004 u64 data = kvm_read_edx_eax(vcpu);
2007 r = kvm_set_msr_with_filter(vcpu, ecx, data);
2010 trace_kvm_msr_write(ecx, data);
2012 /* MSR write failed? See if we should ask user space */
2013 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data,
2014 complete_fast_msr_access, r))
2016 /* Signal all other negative errors to userspace */
2019 trace_kvm_msr_write_ex(ecx, data);
2022 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2024 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
2026 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu)
2028 return kvm_skip_emulated_instruction(vcpu);
2030 EXPORT_SYMBOL_GPL(kvm_emulate_as_nop);
2032 int kvm_emulate_invd(struct kvm_vcpu *vcpu)
2034 /* Treat an INVD instruction as a NOP and just skip it. */
2035 return kvm_emulate_as_nop(vcpu);
2037 EXPORT_SYMBOL_GPL(kvm_emulate_invd);
2039 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu)
2041 kvm_queue_exception(vcpu, UD_VECTOR);
2044 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op);
2047 static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn)
2049 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_FAULTS) &&
2050 !guest_cpuid_has(vcpu, X86_FEATURE_MWAIT))
2051 return kvm_handle_invalid_op(vcpu);
2053 pr_warn_once("kvm: %s instruction emulated as NOP!\n", insn);
2054 return kvm_emulate_as_nop(vcpu);
2056 int kvm_emulate_mwait(struct kvm_vcpu *vcpu)
2058 return kvm_emulate_monitor_mwait(vcpu, "MWAIT");
2060 EXPORT_SYMBOL_GPL(kvm_emulate_mwait);
2062 int kvm_emulate_monitor(struct kvm_vcpu *vcpu)
2064 return kvm_emulate_monitor_mwait(vcpu, "MONITOR");
2066 EXPORT_SYMBOL_GPL(kvm_emulate_monitor);
2068 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
2070 xfer_to_guest_mode_prepare();
2071 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
2072 xfer_to_guest_mode_work_pending();
2076 * The fast path for frequent and performance sensitive wrmsr emulation,
2077 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
2078 * the latency of virtual IPI by avoiding the expensive bits of transitioning
2079 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
2080 * other cases which must be called after interrupts are enabled on the host.
2082 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
2084 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
2087 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
2088 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
2089 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
2090 ((u32)(data >> 32) != X2APIC_BROADCAST))
2091 return kvm_x2apic_icr_write(vcpu->arch.apic, data);
2096 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
2098 if (!kvm_can_use_hv_timer(vcpu))
2101 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2105 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
2107 u32 msr = kvm_rcx_read(vcpu);
2109 fastpath_t ret = EXIT_FASTPATH_NONE;
2112 case APIC_BASE_MSR + (APIC_ICR >> 4):
2113 data = kvm_read_edx_eax(vcpu);
2114 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
2115 kvm_skip_emulated_instruction(vcpu);
2116 ret = EXIT_FASTPATH_EXIT_HANDLED;
2119 case MSR_IA32_TSC_DEADLINE:
2120 data = kvm_read_edx_eax(vcpu);
2121 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
2122 kvm_skip_emulated_instruction(vcpu);
2123 ret = EXIT_FASTPATH_REENTER_GUEST;
2130 if (ret != EXIT_FASTPATH_NONE)
2131 trace_kvm_msr_write(msr, data);
2135 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
2138 * Adapt set_msr() to msr_io()'s calling convention
2140 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2142 return kvm_get_msr_ignored_check(vcpu, index, data, true);
2145 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2147 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
2150 #ifdef CONFIG_X86_64
2151 struct pvclock_clock {
2161 struct pvclock_gtod_data {
2164 struct pvclock_clock clock; /* extract of a clocksource struct */
2165 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
2171 static struct pvclock_gtod_data pvclock_gtod_data;
2173 static void update_pvclock_gtod(struct timekeeper *tk)
2175 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
2177 write_seqcount_begin(&vdata->seq);
2179 /* copy pvclock gtod data */
2180 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
2181 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
2182 vdata->clock.mask = tk->tkr_mono.mask;
2183 vdata->clock.mult = tk->tkr_mono.mult;
2184 vdata->clock.shift = tk->tkr_mono.shift;
2185 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
2186 vdata->clock.offset = tk->tkr_mono.base;
2188 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
2189 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
2190 vdata->raw_clock.mask = tk->tkr_raw.mask;
2191 vdata->raw_clock.mult = tk->tkr_raw.mult;
2192 vdata->raw_clock.shift = tk->tkr_raw.shift;
2193 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
2194 vdata->raw_clock.offset = tk->tkr_raw.base;
2196 vdata->wall_time_sec = tk->xtime_sec;
2198 vdata->offs_boot = tk->offs_boot;
2200 write_seqcount_end(&vdata->seq);
2203 static s64 get_kvmclock_base_ns(void)
2205 /* Count up from boot time, but with the frequency of the raw clock. */
2206 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
2209 static s64 get_kvmclock_base_ns(void)
2211 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
2212 return ktime_get_boottime_ns();
2216 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs)
2220 struct pvclock_wall_clock wc;
2227 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
2232 ++version; /* first time write, random junk */
2236 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
2240 * The guest calculates current wall clock time by adding
2241 * system time (updated by kvm_guest_time_update below) to the
2242 * wall clock specified here. We do the reverse here.
2244 wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
2246 wc.nsec = do_div(wall_nsec, 1000000000);
2247 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
2248 wc.version = version;
2250 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
2253 wc_sec_hi = wall_nsec >> 32;
2254 kvm_write_guest(kvm, wall_clock + sec_hi_ofs,
2255 &wc_sec_hi, sizeof(wc_sec_hi));
2259 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
2262 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
2263 bool old_msr, bool host_initiated)
2265 struct kvm_arch *ka = &vcpu->kvm->arch;
2267 if (vcpu->vcpu_id == 0 && !host_initiated) {
2268 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
2269 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2271 ka->boot_vcpu_runs_old_kvmclock = old_msr;
2274 vcpu->arch.time = system_time;
2275 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2277 /* we verify if the enable bit is set... */
2278 if (system_time & 1) {
2279 kvm_gfn_to_pfn_cache_init(vcpu->kvm, &vcpu->arch.pv_time, vcpu,
2280 KVM_HOST_USES_PFN, system_time & ~1ULL,
2281 sizeof(struct pvclock_vcpu_time_info));
2283 kvm_gfn_to_pfn_cache_destroy(vcpu->kvm, &vcpu->arch.pv_time);
2289 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2291 do_shl32_div32(dividend, divisor);
2295 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2296 s8 *pshift, u32 *pmultiplier)
2304 scaled64 = scaled_hz;
2305 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2310 tps32 = (uint32_t)tps64;
2311 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2312 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2320 *pmultiplier = div_frac(scaled64, tps32);
2323 #ifdef CONFIG_X86_64
2324 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2327 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2328 static unsigned long max_tsc_khz;
2330 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2332 u64 v = (u64)khz * (1000000 + ppm);
2337 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier);
2339 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2343 /* Guest TSC same frequency as host TSC? */
2345 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2349 /* TSC scaling supported? */
2350 if (!kvm_caps.has_tsc_control) {
2351 if (user_tsc_khz > tsc_khz) {
2352 vcpu->arch.tsc_catchup = 1;
2353 vcpu->arch.tsc_always_catchup = 1;
2356 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2361 /* TSC scaling required - calculate ratio */
2362 ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits,
2363 user_tsc_khz, tsc_khz);
2365 if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) {
2366 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2371 kvm_vcpu_write_tsc_multiplier(vcpu, ratio);
2375 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2377 u32 thresh_lo, thresh_hi;
2378 int use_scaling = 0;
2380 /* tsc_khz can be zero if TSC calibration fails */
2381 if (user_tsc_khz == 0) {
2382 /* set tsc_scaling_ratio to a safe value */
2383 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2387 /* Compute a scale to convert nanoseconds in TSC cycles */
2388 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2389 &vcpu->arch.virtual_tsc_shift,
2390 &vcpu->arch.virtual_tsc_mult);
2391 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2394 * Compute the variation in TSC rate which is acceptable
2395 * within the range of tolerance and decide if the
2396 * rate being applied is within that bounds of the hardware
2397 * rate. If so, no scaling or compensation need be done.
2399 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2400 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2401 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2402 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
2405 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2408 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2410 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2411 vcpu->arch.virtual_tsc_mult,
2412 vcpu->arch.virtual_tsc_shift);
2413 tsc += vcpu->arch.this_tsc_write;
2417 #ifdef CONFIG_X86_64
2418 static inline int gtod_is_based_on_tsc(int mode)
2420 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2424 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2426 #ifdef CONFIG_X86_64
2428 struct kvm_arch *ka = &vcpu->kvm->arch;
2429 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2431 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2432 atomic_read(&vcpu->kvm->online_vcpus));
2435 * Once the masterclock is enabled, always perform request in
2436 * order to update it.
2438 * In order to enable masterclock, the host clocksource must be TSC
2439 * and the vcpus need to have matched TSCs. When that happens,
2440 * perform request to enable masterclock.
2442 if (ka->use_master_clock ||
2443 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2444 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2446 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2447 atomic_read(&vcpu->kvm->online_vcpus),
2448 ka->use_master_clock, gtod->clock.vclock_mode);
2453 * Multiply tsc by a fixed point number represented by ratio.
2455 * The most significant 64-N bits (mult) of ratio represent the
2456 * integral part of the fixed point number; the remaining N bits
2457 * (frac) represent the fractional part, ie. ratio represents a fixed
2458 * point number (mult + frac * 2^(-N)).
2460 * N equals to kvm_caps.tsc_scaling_ratio_frac_bits.
2462 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2464 return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits);
2467 u64 kvm_scale_tsc(u64 tsc, u64 ratio)
2471 if (ratio != kvm_caps.default_tsc_scaling_ratio)
2472 _tsc = __scale_tsc(ratio, tsc);
2476 EXPORT_SYMBOL_GPL(kvm_scale_tsc);
2478 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2482 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio);
2484 return target_tsc - tsc;
2487 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2489 return vcpu->arch.l1_tsc_offset +
2490 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio);
2492 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2494 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier)
2498 if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio)
2499 nested_offset = l1_offset;
2501 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier,
2502 kvm_caps.tsc_scaling_ratio_frac_bits);
2504 nested_offset += l2_offset;
2505 return nested_offset;
2507 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset);
2509 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier)
2511 if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio)
2512 return mul_u64_u64_shr(l1_multiplier, l2_multiplier,
2513 kvm_caps.tsc_scaling_ratio_frac_bits);
2515 return l1_multiplier;
2517 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier);
2519 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset)
2521 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2522 vcpu->arch.l1_tsc_offset,
2525 vcpu->arch.l1_tsc_offset = l1_offset;
2528 * If we are here because L1 chose not to trap WRMSR to TSC then
2529 * according to the spec this should set L1's TSC (as opposed to
2530 * setting L1's offset for L2).
2532 if (is_guest_mode(vcpu))
2533 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2535 static_call(kvm_x86_get_l2_tsc_offset)(vcpu),
2536 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2538 vcpu->arch.tsc_offset = l1_offset;
2540 static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset);
2543 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier)
2545 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier;
2547 /* Userspace is changing the multiplier while L2 is active */
2548 if (is_guest_mode(vcpu))
2549 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2551 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2553 vcpu->arch.tsc_scaling_ratio = l1_multiplier;
2555 if (kvm_caps.has_tsc_control)
2556 static_call(kvm_x86_write_tsc_multiplier)(
2557 vcpu, vcpu->arch.tsc_scaling_ratio);
2560 static inline bool kvm_check_tsc_unstable(void)
2562 #ifdef CONFIG_X86_64
2564 * TSC is marked unstable when we're running on Hyper-V,
2565 * 'TSC page' clocksource is good.
2567 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2570 return check_tsc_unstable();
2574 * Infers attempts to synchronize the guest's tsc from host writes. Sets the
2575 * offset for the vcpu and tracks the TSC matching generation that the vcpu
2578 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc,
2579 u64 ns, bool matched)
2581 struct kvm *kvm = vcpu->kvm;
2583 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2586 * We also track th most recent recorded KHZ, write and time to
2587 * allow the matching interval to be extended at each write.
2589 kvm->arch.last_tsc_nsec = ns;
2590 kvm->arch.last_tsc_write = tsc;
2591 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2592 kvm->arch.last_tsc_offset = offset;
2594 vcpu->arch.last_guest_tsc = tsc;
2596 kvm_vcpu_write_tsc_offset(vcpu, offset);
2600 * We split periods of matched TSC writes into generations.
2601 * For each generation, we track the original measured
2602 * nanosecond time, offset, and write, so if TSCs are in
2603 * sync, we can match exact offset, and if not, we can match
2604 * exact software computation in compute_guest_tsc()
2606 * These values are tracked in kvm->arch.cur_xxx variables.
2608 kvm->arch.cur_tsc_generation++;
2609 kvm->arch.cur_tsc_nsec = ns;
2610 kvm->arch.cur_tsc_write = tsc;
2611 kvm->arch.cur_tsc_offset = offset;
2612 kvm->arch.nr_vcpus_matched_tsc = 0;
2613 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) {
2614 kvm->arch.nr_vcpus_matched_tsc++;
2617 /* Keep track of which generation this VCPU has synchronized to */
2618 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2619 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2620 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2622 kvm_track_tsc_matching(vcpu);
2625 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2627 struct kvm *kvm = vcpu->kvm;
2628 u64 offset, ns, elapsed;
2629 unsigned long flags;
2630 bool matched = false;
2631 bool synchronizing = false;
2633 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2634 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2635 ns = get_kvmclock_base_ns();
2636 elapsed = ns - kvm->arch.last_tsc_nsec;
2638 if (vcpu->arch.virtual_tsc_khz) {
2641 * detection of vcpu initialization -- need to sync
2642 * with other vCPUs. This particularly helps to keep
2643 * kvm_clock stable after CPU hotplug
2645 synchronizing = true;
2647 u64 tsc_exp = kvm->arch.last_tsc_write +
2648 nsec_to_cycles(vcpu, elapsed);
2649 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2651 * Special case: TSC write with a small delta (1 second)
2652 * of virtual cycle time against real time is
2653 * interpreted as an attempt to synchronize the CPU.
2655 synchronizing = data < tsc_exp + tsc_hz &&
2656 data + tsc_hz > tsc_exp;
2661 * For a reliable TSC, we can match TSC offsets, and for an unstable
2662 * TSC, we add elapsed time in this computation. We could let the
2663 * compensation code attempt to catch up if we fall behind, but
2664 * it's better to try to match offsets from the beginning.
2666 if (synchronizing &&
2667 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2668 if (!kvm_check_tsc_unstable()) {
2669 offset = kvm->arch.cur_tsc_offset;
2671 u64 delta = nsec_to_cycles(vcpu, elapsed);
2673 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2678 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched);
2679 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2682 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2685 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2686 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2689 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2691 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio)
2692 WARN_ON(adjustment < 0);
2693 adjustment = kvm_scale_tsc((u64) adjustment,
2694 vcpu->arch.l1_tsc_scaling_ratio);
2695 adjust_tsc_offset_guest(vcpu, adjustment);
2698 #ifdef CONFIG_X86_64
2700 static u64 read_tsc(void)
2702 u64 ret = (u64)rdtsc_ordered();
2703 u64 last = pvclock_gtod_data.clock.cycle_last;
2705 if (likely(ret >= last))
2709 * GCC likes to generate cmov here, but this branch is extremely
2710 * predictable (it's just a function of time and the likely is
2711 * very likely) and there's a data dependence, so force GCC
2712 * to generate a branch instead. I don't barrier() because
2713 * we don't actually need a barrier, and if this function
2714 * ever gets inlined it will generate worse code.
2720 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2726 switch (clock->vclock_mode) {
2727 case VDSO_CLOCKMODE_HVCLOCK:
2728 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2730 if (tsc_pg_val != U64_MAX) {
2731 /* TSC page valid */
2732 *mode = VDSO_CLOCKMODE_HVCLOCK;
2733 v = (tsc_pg_val - clock->cycle_last) &
2736 /* TSC page invalid */
2737 *mode = VDSO_CLOCKMODE_NONE;
2740 case VDSO_CLOCKMODE_TSC:
2741 *mode = VDSO_CLOCKMODE_TSC;
2742 *tsc_timestamp = read_tsc();
2743 v = (*tsc_timestamp - clock->cycle_last) &
2747 *mode = VDSO_CLOCKMODE_NONE;
2750 if (*mode == VDSO_CLOCKMODE_NONE)
2751 *tsc_timestamp = v = 0;
2753 return v * clock->mult;
2756 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2758 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2764 seq = read_seqcount_begin(>od->seq);
2765 ns = gtod->raw_clock.base_cycles;
2766 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2767 ns >>= gtod->raw_clock.shift;
2768 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2769 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2775 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2777 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2783 seq = read_seqcount_begin(>od->seq);
2784 ts->tv_sec = gtod->wall_time_sec;
2785 ns = gtod->clock.base_cycles;
2786 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2787 ns >>= gtod->clock.shift;
2788 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2790 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2796 /* returns true if host is using TSC based clocksource */
2797 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2799 /* checked again under seqlock below */
2800 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2803 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2807 /* returns true if host is using TSC based clocksource */
2808 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2811 /* checked again under seqlock below */
2812 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2815 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2821 * Assuming a stable TSC across physical CPUS, and a stable TSC
2822 * across virtual CPUs, the following condition is possible.
2823 * Each numbered line represents an event visible to both
2824 * CPUs at the next numbered event.
2826 * "timespecX" represents host monotonic time. "tscX" represents
2829 * VCPU0 on CPU0 | VCPU1 on CPU1
2831 * 1. read timespec0,tsc0
2832 * 2. | timespec1 = timespec0 + N
2834 * 3. transition to guest | transition to guest
2835 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2836 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2837 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2839 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2842 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2844 * - 0 < N - M => M < N
2846 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2847 * always the case (the difference between two distinct xtime instances
2848 * might be smaller then the difference between corresponding TSC reads,
2849 * when updating guest vcpus pvclock areas).
2851 * To avoid that problem, do not allow visibility of distinct
2852 * system_timestamp/tsc_timestamp values simultaneously: use a master
2853 * copy of host monotonic time values. Update that master copy
2856 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2860 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2862 #ifdef CONFIG_X86_64
2863 struct kvm_arch *ka = &kvm->arch;
2865 bool host_tsc_clocksource, vcpus_matched;
2867 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2868 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2869 atomic_read(&kvm->online_vcpus));
2872 * If the host uses TSC clock, then passthrough TSC as stable
2875 host_tsc_clocksource = kvm_get_time_and_clockread(
2876 &ka->master_kernel_ns,
2877 &ka->master_cycle_now);
2879 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2880 && !ka->backwards_tsc_observed
2881 && !ka->boot_vcpu_runs_old_kvmclock;
2883 if (ka->use_master_clock)
2884 atomic_set(&kvm_guest_has_master_clock, 1);
2886 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2887 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2892 static void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2894 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2897 static void __kvm_start_pvclock_update(struct kvm *kvm)
2899 raw_spin_lock_irq(&kvm->arch.tsc_write_lock);
2900 write_seqcount_begin(&kvm->arch.pvclock_sc);
2903 static void kvm_start_pvclock_update(struct kvm *kvm)
2905 kvm_make_mclock_inprogress_request(kvm);
2907 /* no guest entries from this point */
2908 __kvm_start_pvclock_update(kvm);
2911 static void kvm_end_pvclock_update(struct kvm *kvm)
2913 struct kvm_arch *ka = &kvm->arch;
2914 struct kvm_vcpu *vcpu;
2917 write_seqcount_end(&ka->pvclock_sc);
2918 raw_spin_unlock_irq(&ka->tsc_write_lock);
2919 kvm_for_each_vcpu(i, vcpu, kvm)
2920 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2922 /* guest entries allowed */
2923 kvm_for_each_vcpu(i, vcpu, kvm)
2924 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2927 static void kvm_update_masterclock(struct kvm *kvm)
2929 kvm_hv_request_tsc_page_update(kvm);
2930 kvm_start_pvclock_update(kvm);
2931 pvclock_update_vm_gtod_copy(kvm);
2932 kvm_end_pvclock_update(kvm);
2935 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */
2936 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
2938 struct kvm_arch *ka = &kvm->arch;
2939 struct pvclock_vcpu_time_info hv_clock;
2941 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2945 if (ka->use_master_clock && __this_cpu_read(cpu_tsc_khz)) {
2946 #ifdef CONFIG_X86_64
2947 struct timespec64 ts;
2949 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) {
2950 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec;
2951 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC;
2954 data->host_tsc = rdtsc();
2956 data->flags |= KVM_CLOCK_TSC_STABLE;
2957 hv_clock.tsc_timestamp = ka->master_cycle_now;
2958 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2959 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2960 &hv_clock.tsc_shift,
2961 &hv_clock.tsc_to_system_mul);
2962 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc);
2964 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset;
2970 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
2972 struct kvm_arch *ka = &kvm->arch;
2976 seq = read_seqcount_begin(&ka->pvclock_sc);
2977 __get_kvmclock(kvm, data);
2978 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
2981 u64 get_kvmclock_ns(struct kvm *kvm)
2983 struct kvm_clock_data data;
2985 get_kvmclock(kvm, &data);
2989 static void kvm_setup_guest_pvclock(struct kvm_vcpu *v,
2990 struct gfn_to_pfn_cache *gpc,
2991 unsigned int offset)
2993 struct kvm_vcpu_arch *vcpu = &v->arch;
2994 struct pvclock_vcpu_time_info *guest_hv_clock;
2995 unsigned long flags;
2997 read_lock_irqsave(&gpc->lock, flags);
2998 while (!kvm_gfn_to_pfn_cache_check(v->kvm, gpc, gpc->gpa,
2999 offset + sizeof(*guest_hv_clock))) {
3000 read_unlock_irqrestore(&gpc->lock, flags);
3002 if (kvm_gfn_to_pfn_cache_refresh(v->kvm, gpc, gpc->gpa,
3003 offset + sizeof(*guest_hv_clock)))
3006 read_lock_irqsave(&gpc->lock, flags);
3009 guest_hv_clock = (void *)(gpc->khva + offset);
3012 * This VCPU is paused, but it's legal for a guest to read another
3013 * VCPU's kvmclock, so we really have to follow the specification where
3014 * it says that version is odd if data is being modified, and even after
3018 guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1;
3021 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
3022 vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
3024 if (vcpu->pvclock_set_guest_stopped_request) {
3025 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
3026 vcpu->pvclock_set_guest_stopped_request = false;
3029 memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock));
3032 guest_hv_clock->version = ++vcpu->hv_clock.version;
3034 mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT);
3035 read_unlock_irqrestore(&gpc->lock, flags);
3037 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
3040 static int kvm_guest_time_update(struct kvm_vcpu *v)
3042 unsigned long flags, tgt_tsc_khz;
3044 struct kvm_vcpu_arch *vcpu = &v->arch;
3045 struct kvm_arch *ka = &v->kvm->arch;
3047 u64 tsc_timestamp, host_tsc;
3049 bool use_master_clock;
3055 * If the host uses TSC clock, then passthrough TSC as stable
3059 seq = read_seqcount_begin(&ka->pvclock_sc);
3060 use_master_clock = ka->use_master_clock;
3061 if (use_master_clock) {
3062 host_tsc = ka->master_cycle_now;
3063 kernel_ns = ka->master_kernel_ns;
3065 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3067 /* Keep irq disabled to prevent changes to the clock */
3068 local_irq_save(flags);
3069 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
3070 if (unlikely(tgt_tsc_khz == 0)) {
3071 local_irq_restore(flags);
3072 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3075 if (!use_master_clock) {
3077 kernel_ns = get_kvmclock_base_ns();
3080 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
3083 * We may have to catch up the TSC to match elapsed wall clock
3084 * time for two reasons, even if kvmclock is used.
3085 * 1) CPU could have been running below the maximum TSC rate
3086 * 2) Broken TSC compensation resets the base at each VCPU
3087 * entry to avoid unknown leaps of TSC even when running
3088 * again on the same CPU. This may cause apparent elapsed
3089 * time to disappear, and the guest to stand still or run
3092 if (vcpu->tsc_catchup) {
3093 u64 tsc = compute_guest_tsc(v, kernel_ns);
3094 if (tsc > tsc_timestamp) {
3095 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
3096 tsc_timestamp = tsc;
3100 local_irq_restore(flags);
3102 /* With all the info we got, fill in the values */
3104 if (kvm_caps.has_tsc_control)
3105 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz,
3106 v->arch.l1_tsc_scaling_ratio);
3108 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3109 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
3110 &vcpu->hv_clock.tsc_shift,
3111 &vcpu->hv_clock.tsc_to_system_mul);
3112 vcpu->hw_tsc_khz = tgt_tsc_khz;
3115 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
3116 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
3117 vcpu->last_guest_tsc = tsc_timestamp;
3119 /* If the host uses TSC clocksource, then it is stable */
3121 if (use_master_clock)
3122 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
3124 vcpu->hv_clock.flags = pvclock_flags;
3126 if (vcpu->pv_time.active)
3127 kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0);
3128 if (vcpu->xen.vcpu_info_cache.active)
3129 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache,
3130 offsetof(struct compat_vcpu_info, time));
3131 if (vcpu->xen.vcpu_time_info_cache.active)
3132 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0);
3133 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
3138 * kvmclock updates which are isolated to a given vcpu, such as
3139 * vcpu->cpu migration, should not allow system_timestamp from
3140 * the rest of the vcpus to remain static. Otherwise ntp frequency
3141 * correction applies to one vcpu's system_timestamp but not
3144 * So in those cases, request a kvmclock update for all vcpus.
3145 * We need to rate-limit these requests though, as they can
3146 * considerably slow guests that have a large number of vcpus.
3147 * The time for a remote vcpu to update its kvmclock is bound
3148 * by the delay we use to rate-limit the updates.
3151 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
3153 static void kvmclock_update_fn(struct work_struct *work)
3156 struct delayed_work *dwork = to_delayed_work(work);
3157 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3158 kvmclock_update_work);
3159 struct kvm *kvm = container_of(ka, struct kvm, arch);
3160 struct kvm_vcpu *vcpu;
3162 kvm_for_each_vcpu(i, vcpu, kvm) {
3163 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3164 kvm_vcpu_kick(vcpu);
3168 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
3170 struct kvm *kvm = v->kvm;
3172 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3173 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
3174 KVMCLOCK_UPDATE_DELAY);
3177 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
3179 static void kvmclock_sync_fn(struct work_struct *work)
3181 struct delayed_work *dwork = to_delayed_work(work);
3182 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3183 kvmclock_sync_work);
3184 struct kvm *kvm = container_of(ka, struct kvm, arch);
3186 if (!kvmclock_periodic_sync)
3189 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
3190 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
3191 KVMCLOCK_SYNC_PERIOD);
3194 /* These helpers are safe iff @msr is known to be an MCx bank MSR. */
3195 static bool is_mci_control_msr(u32 msr)
3197 return (msr & 3) == 0;
3199 static bool is_mci_status_msr(u32 msr)
3201 return (msr & 3) == 1;
3205 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
3207 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
3209 /* McStatusWrEn enabled? */
3210 if (guest_cpuid_is_amd_or_hygon(vcpu))
3211 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
3216 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3218 u64 mcg_cap = vcpu->arch.mcg_cap;
3219 unsigned bank_num = mcg_cap & 0xff;
3220 u32 msr = msr_info->index;
3221 u64 data = msr_info->data;
3222 u32 offset, last_msr;
3225 case MSR_IA32_MCG_STATUS:
3226 vcpu->arch.mcg_status = data;
3228 case MSR_IA32_MCG_CTL:
3229 if (!(mcg_cap & MCG_CTL_P) &&
3230 (data || !msr_info->host_initiated))
3232 if (data != 0 && data != ~(u64)0)
3234 vcpu->arch.mcg_ctl = data;
3236 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3237 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
3241 if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated))
3243 /* An attempt to write a 1 to a reserved bit raises #GP */
3244 if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK))
3246 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
3247 last_msr + 1 - MSR_IA32_MC0_CTL2);
3248 vcpu->arch.mci_ctl2_banks[offset] = data;
3250 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3251 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
3256 * Only 0 or all 1s can be written to IA32_MCi_CTL, all other
3257 * values are architecturally undefined. But, some Linux
3258 * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB
3259 * issue on AMD K8s, allow bit 10 to be clear when setting all
3260 * other bits in order to avoid an uncaught #GP in the guest.
3262 * UNIXWARE clears bit 0 of MC1_CTL to ignore
3263 * correctable, single-bit ECC data errors.
3265 if (is_mci_control_msr(msr) &&
3266 data != 0 && (data | (1 << 10) | 1) != ~(u64)0)
3270 * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR.
3271 * AMD-based CPUs allow non-zero values, but if and only if
3272 * HWCR[McStatusWrEn] is set.
3274 if (!msr_info->host_initiated && is_mci_status_msr(msr) &&
3275 data != 0 && !can_set_mci_status(vcpu))
3278 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
3279 last_msr + 1 - MSR_IA32_MC0_CTL);
3280 vcpu->arch.mce_banks[offset] = data;
3288 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
3290 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
3292 return (vcpu->arch.apf.msr_en_val & mask) == mask;
3295 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
3297 gpa_t gpa = data & ~0x3f;
3299 /* Bits 4:5 are reserved, Should be zero */
3303 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
3304 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
3307 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
3308 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
3311 if (!lapic_in_kernel(vcpu))
3312 return data ? 1 : 0;
3314 vcpu->arch.apf.msr_en_val = data;
3316 if (!kvm_pv_async_pf_enabled(vcpu)) {
3317 kvm_clear_async_pf_completion_queue(vcpu);
3318 kvm_async_pf_hash_reset(vcpu);
3322 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
3326 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
3327 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
3329 kvm_async_pf_wakeup_all(vcpu);
3334 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
3336 /* Bits 8-63 are reserved */
3340 if (!lapic_in_kernel(vcpu))
3343 vcpu->arch.apf.msr_int_val = data;
3345 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
3350 static void kvmclock_reset(struct kvm_vcpu *vcpu)
3352 kvm_gfn_to_pfn_cache_destroy(vcpu->kvm, &vcpu->arch.pv_time);
3353 vcpu->arch.time = 0;
3356 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
3358 ++vcpu->stat.tlb_flush;
3359 static_call(kvm_x86_flush_tlb_all)(vcpu);
3362 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
3364 ++vcpu->stat.tlb_flush;
3368 * A TLB flush on behalf of the guest is equivalent to
3369 * INVPCID(all), toggling CR4.PGE, etc., which requires
3370 * a forced sync of the shadow page tables. Ensure all the
3371 * roots are synced and the guest TLB in hardware is clean.
3373 kvm_mmu_sync_roots(vcpu);
3374 kvm_mmu_sync_prev_roots(vcpu);
3377 static_call(kvm_x86_flush_tlb_guest)(vcpu);
3381 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
3383 ++vcpu->stat.tlb_flush;
3384 static_call(kvm_x86_flush_tlb_current)(vcpu);
3388 * Service "local" TLB flush requests, which are specific to the current MMU
3389 * context. In addition to the generic event handling in vcpu_enter_guest(),
3390 * TLB flushes that are targeted at an MMU context also need to be serviced
3391 * prior before nested VM-Enter/VM-Exit.
3393 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu)
3395 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
3396 kvm_vcpu_flush_tlb_current(vcpu);
3398 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu))
3399 kvm_vcpu_flush_tlb_guest(vcpu);
3401 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests);
3403 static void record_steal_time(struct kvm_vcpu *vcpu)
3405 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
3406 struct kvm_steal_time __user *st;
3407 struct kvm_memslots *slots;
3411 if (kvm_xen_msr_enabled(vcpu->kvm)) {
3412 kvm_xen_runstate_set_running(vcpu);
3416 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3419 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm))
3422 slots = kvm_memslots(vcpu->kvm);
3424 if (unlikely(slots->generation != ghc->generation ||
3425 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) {
3426 gfn_t gfn = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
3428 /* We rely on the fact that it fits in a single page. */
3429 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS);
3431 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gfn, sizeof(*st)) ||
3432 kvm_is_error_hva(ghc->hva) || !ghc->memslot)
3436 st = (struct kvm_steal_time __user *)ghc->hva;
3438 * Doing a TLB flush here, on the guest's behalf, can avoid
3441 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
3442 u8 st_preempted = 0;
3445 if (!user_access_begin(st, sizeof(*st)))
3448 asm volatile("1: xchgb %0, %2\n"
3451 _ASM_EXTABLE_UA(1b, 2b)
3452 : "+q" (st_preempted),
3454 "+m" (st->preempted));
3460 vcpu->arch.st.preempted = 0;
3462 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
3463 st_preempted & KVM_VCPU_FLUSH_TLB);
3464 if (st_preempted & KVM_VCPU_FLUSH_TLB)
3465 kvm_vcpu_flush_tlb_guest(vcpu);
3467 if (!user_access_begin(st, sizeof(*st)))
3470 if (!user_access_begin(st, sizeof(*st)))
3473 unsafe_put_user(0, &st->preempted, out);
3474 vcpu->arch.st.preempted = 0;
3477 unsafe_get_user(version, &st->version, out);
3479 version += 1; /* first time write, random junk */
3482 unsafe_put_user(version, &st->version, out);
3486 unsafe_get_user(steal, &st->steal, out);
3487 steal += current->sched_info.run_delay -
3488 vcpu->arch.st.last_steal;
3489 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3490 unsafe_put_user(steal, &st->steal, out);
3493 unsafe_put_user(version, &st->version, out);
3498 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
3501 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3504 u32 msr = msr_info->index;
3505 u64 data = msr_info->data;
3507 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr)
3508 return kvm_xen_write_hypercall_page(vcpu, data);
3511 case MSR_AMD64_NB_CFG:
3512 case MSR_IA32_UCODE_WRITE:
3513 case MSR_VM_HSAVE_PA:
3514 case MSR_AMD64_PATCH_LOADER:
3515 case MSR_AMD64_BU_CFG2:
3516 case MSR_AMD64_DC_CFG:
3517 case MSR_F15H_EX_CFG:
3520 case MSR_IA32_UCODE_REV:
3521 if (msr_info->host_initiated)
3522 vcpu->arch.microcode_version = data;
3524 case MSR_IA32_ARCH_CAPABILITIES:
3525 if (!msr_info->host_initiated)
3527 vcpu->arch.arch_capabilities = data;
3529 case MSR_IA32_PERF_CAPABILITIES: {
3530 struct kvm_msr_entry msr_ent = {.index = msr, .data = 0};
3532 if (!msr_info->host_initiated)
3534 if (kvm_get_msr_feature(&msr_ent))
3536 if (data & ~msr_ent.data)
3539 vcpu->arch.perf_capabilities = data;
3544 return set_efer(vcpu, msr_info);
3546 data &= ~(u64)0x40; /* ignore flush filter disable */
3547 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3548 data &= ~(u64)0x8; /* ignore TLB cache disable */
3550 /* Handle McStatusWrEn */
3551 if (data == BIT_ULL(18)) {
3552 vcpu->arch.msr_hwcr = data;
3553 } else if (data != 0) {
3554 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
3559 case MSR_FAM10H_MMIO_CONF_BASE:
3561 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
3566 case 0x200 ... MSR_IA32_MC0_CTL2 - 1:
3567 case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff:
3568 return kvm_mtrr_set_msr(vcpu, msr, data);
3569 case MSR_IA32_APICBASE:
3570 return kvm_set_apic_base(vcpu, msr_info);
3571 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3572 return kvm_x2apic_msr_write(vcpu, msr, data);
3573 case MSR_IA32_TSC_DEADLINE:
3574 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3576 case MSR_IA32_TSC_ADJUST:
3577 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3578 if (!msr_info->host_initiated) {
3579 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3580 adjust_tsc_offset_guest(vcpu, adj);
3581 /* Before back to guest, tsc_timestamp must be adjusted
3582 * as well, otherwise guest's percpu pvclock time could jump.
3584 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3586 vcpu->arch.ia32_tsc_adjust_msr = data;
3589 case MSR_IA32_MISC_ENABLE: {
3590 u64 old_val = vcpu->arch.ia32_misc_enable_msr;
3592 if (!msr_info->host_initiated) {
3594 if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK)
3597 /* R bits, i.e. writes are ignored, but don't fault. */
3598 data = data & ~MSR_IA32_MISC_ENABLE_EMON;
3599 data |= old_val & MSR_IA32_MISC_ENABLE_EMON;
3602 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3603 ((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3604 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3606 vcpu->arch.ia32_misc_enable_msr = data;
3607 kvm_update_cpuid_runtime(vcpu);
3609 vcpu->arch.ia32_misc_enable_msr = data;
3613 case MSR_IA32_SMBASE:
3614 if (!msr_info->host_initiated)
3616 vcpu->arch.smbase = data;
3618 case MSR_IA32_POWER_CTL:
3619 vcpu->arch.msr_ia32_power_ctl = data;
3622 if (msr_info->host_initiated) {
3623 kvm_synchronize_tsc(vcpu, data);
3625 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3626 adjust_tsc_offset_guest(vcpu, adj);
3627 vcpu->arch.ia32_tsc_adjust_msr += adj;
3631 if (!msr_info->host_initiated &&
3632 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3635 * KVM supports exposing PT to the guest, but does not support
3636 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3637 * XSAVES/XRSTORS to save/restore PT MSRs.
3639 if (data & ~kvm_caps.supported_xss)
3641 vcpu->arch.ia32_xss = data;
3642 kvm_update_cpuid_runtime(vcpu);
3645 if (!msr_info->host_initiated)
3647 vcpu->arch.smi_count = data;
3649 case MSR_KVM_WALL_CLOCK_NEW:
3650 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3653 vcpu->kvm->arch.wall_clock = data;
3654 kvm_write_wall_clock(vcpu->kvm, data, 0);
3656 case MSR_KVM_WALL_CLOCK:
3657 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3660 vcpu->kvm->arch.wall_clock = data;
3661 kvm_write_wall_clock(vcpu->kvm, data, 0);
3663 case MSR_KVM_SYSTEM_TIME_NEW:
3664 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3667 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3669 case MSR_KVM_SYSTEM_TIME:
3670 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3673 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3675 case MSR_KVM_ASYNC_PF_EN:
3676 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3679 if (kvm_pv_enable_async_pf(vcpu, data))
3682 case MSR_KVM_ASYNC_PF_INT:
3683 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3686 if (kvm_pv_enable_async_pf_int(vcpu, data))
3689 case MSR_KVM_ASYNC_PF_ACK:
3690 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3693 vcpu->arch.apf.pageready_pending = false;
3694 kvm_check_async_pf_completion(vcpu);
3697 case MSR_KVM_STEAL_TIME:
3698 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3701 if (unlikely(!sched_info_on()))
3704 if (data & KVM_STEAL_RESERVED_MASK)
3707 vcpu->arch.st.msr_val = data;
3709 if (!(data & KVM_MSR_ENABLED))
3712 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3715 case MSR_KVM_PV_EOI_EN:
3716 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3719 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8)))
3723 case MSR_KVM_POLL_CONTROL:
3724 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3727 /* only enable bit supported */
3728 if (data & (-1ULL << 1))
3731 vcpu->arch.msr_kvm_poll_control = data;
3734 case MSR_IA32_MCG_CTL:
3735 case MSR_IA32_MCG_STATUS:
3736 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3737 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3738 return set_msr_mce(vcpu, msr_info);
3740 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3741 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3744 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3745 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3746 if (kvm_pmu_is_valid_msr(vcpu, msr))
3747 return kvm_pmu_set_msr(vcpu, msr_info);
3749 if (pr || data != 0)
3750 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
3751 "0x%x data 0x%llx\n", msr, data);
3753 case MSR_K7_CLK_CTL:
3755 * Ignore all writes to this no longer documented MSR.
3756 * Writes are only relevant for old K7 processors,
3757 * all pre-dating SVM, but a recommended workaround from
3758 * AMD for these chips. It is possible to specify the
3759 * affected processor models on the command line, hence
3760 * the need to ignore the workaround.
3763 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3764 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3765 case HV_X64_MSR_SYNDBG_OPTIONS:
3766 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3767 case HV_X64_MSR_CRASH_CTL:
3768 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3769 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3770 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3771 case HV_X64_MSR_TSC_EMULATION_STATUS:
3772 return kvm_hv_set_msr_common(vcpu, msr, data,
3773 msr_info->host_initiated);
3774 case MSR_IA32_BBL_CR_CTL3:
3775 /* Drop writes to this legacy MSR -- see rdmsr
3776 * counterpart for further detail.
3778 if (report_ignored_msrs)
3779 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
3782 case MSR_AMD64_OSVW_ID_LENGTH:
3783 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3785 vcpu->arch.osvw.length = data;
3787 case MSR_AMD64_OSVW_STATUS:
3788 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3790 vcpu->arch.osvw.status = data;
3792 case MSR_PLATFORM_INFO:
3793 if (!msr_info->host_initiated ||
3794 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3795 cpuid_fault_enabled(vcpu)))
3797 vcpu->arch.msr_platform_info = data;
3799 case MSR_MISC_FEATURES_ENABLES:
3800 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3801 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3802 !supports_cpuid_fault(vcpu)))
3804 vcpu->arch.msr_misc_features_enables = data;
3806 #ifdef CONFIG_X86_64
3808 if (!msr_info->host_initiated &&
3809 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3812 if (data & ~kvm_guest_supported_xfd(vcpu))
3815 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data);
3817 case MSR_IA32_XFD_ERR:
3818 if (!msr_info->host_initiated &&
3819 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3822 if (data & ~kvm_guest_supported_xfd(vcpu))
3825 vcpu->arch.guest_fpu.xfd_err = data;
3828 case MSR_IA32_PEBS_ENABLE:
3829 case MSR_IA32_DS_AREA:
3830 case MSR_PEBS_DATA_CFG:
3831 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3832 if (kvm_pmu_is_valid_msr(vcpu, msr))
3833 return kvm_pmu_set_msr(vcpu, msr_info);
3835 * Userspace is allowed to write '0' to MSRs that KVM reports
3836 * as to-be-saved, even if an MSRs isn't fully supported.
3838 return !msr_info->host_initiated || data;
3840 if (kvm_pmu_is_valid_msr(vcpu, msr))
3841 return kvm_pmu_set_msr(vcpu, msr_info);
3842 return KVM_MSR_RET_INVALID;
3846 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
3848 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
3851 u64 mcg_cap = vcpu->arch.mcg_cap;
3852 unsigned bank_num = mcg_cap & 0xff;
3853 u32 offset, last_msr;
3856 case MSR_IA32_P5_MC_ADDR:
3857 case MSR_IA32_P5_MC_TYPE:
3860 case MSR_IA32_MCG_CAP:
3861 data = vcpu->arch.mcg_cap;
3863 case MSR_IA32_MCG_CTL:
3864 if (!(mcg_cap & MCG_CTL_P) && !host)
3866 data = vcpu->arch.mcg_ctl;
3868 case MSR_IA32_MCG_STATUS:
3869 data = vcpu->arch.mcg_status;
3871 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3872 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
3876 if (!(mcg_cap & MCG_CMCI_P) && !host)
3878 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
3879 last_msr + 1 - MSR_IA32_MC0_CTL2);
3880 data = vcpu->arch.mci_ctl2_banks[offset];
3882 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3883 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
3887 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
3888 last_msr + 1 - MSR_IA32_MC0_CTL);
3889 data = vcpu->arch.mce_banks[offset];
3898 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3900 switch (msr_info->index) {
3901 case MSR_IA32_PLATFORM_ID:
3902 case MSR_IA32_EBL_CR_POWERON:
3903 case MSR_IA32_LASTBRANCHFROMIP:
3904 case MSR_IA32_LASTBRANCHTOIP:
3905 case MSR_IA32_LASTINTFROMIP:
3906 case MSR_IA32_LASTINTTOIP:
3907 case MSR_AMD64_SYSCFG:
3908 case MSR_K8_TSEG_ADDR:
3909 case MSR_K8_TSEG_MASK:
3910 case MSR_VM_HSAVE_PA:
3911 case MSR_K8_INT_PENDING_MSG:
3912 case MSR_AMD64_NB_CFG:
3913 case MSR_FAM10H_MMIO_CONF_BASE:
3914 case MSR_AMD64_BU_CFG2:
3915 case MSR_IA32_PERF_CTL:
3916 case MSR_AMD64_DC_CFG:
3917 case MSR_F15H_EX_CFG:
3919 * Intel Sandy Bridge CPUs must support the RAPL (running average power
3920 * limit) MSRs. Just return 0, as we do not want to expose the host
3921 * data here. Do not conditionalize this on CPUID, as KVM does not do
3922 * so for existing CPU-specific MSRs.
3924 case MSR_RAPL_POWER_UNIT:
3925 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
3926 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
3927 case MSR_PKG_ENERGY_STATUS: /* Total package */
3928 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
3931 case MSR_IA32_PEBS_ENABLE:
3932 case MSR_IA32_DS_AREA:
3933 case MSR_PEBS_DATA_CFG:
3934 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
3935 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3936 return kvm_pmu_get_msr(vcpu, msr_info);
3938 * Userspace is allowed to read MSRs that KVM reports as
3939 * to-be-saved, even if an MSR isn't fully supported.
3941 if (!msr_info->host_initiated)
3945 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3946 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3947 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3948 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3949 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
3950 return kvm_pmu_get_msr(vcpu, msr_info);
3953 case MSR_IA32_UCODE_REV:
3954 msr_info->data = vcpu->arch.microcode_version;
3956 case MSR_IA32_ARCH_CAPABILITIES:
3957 if (!msr_info->host_initiated &&
3958 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3960 msr_info->data = vcpu->arch.arch_capabilities;
3962 case MSR_IA32_PERF_CAPABILITIES:
3963 if (!msr_info->host_initiated &&
3964 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
3966 msr_info->data = vcpu->arch.perf_capabilities;
3968 case MSR_IA32_POWER_CTL:
3969 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3971 case MSR_IA32_TSC: {
3973 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
3974 * even when not intercepted. AMD manual doesn't explicitly
3975 * state this but appears to behave the same.
3977 * On userspace reads and writes, however, we unconditionally
3978 * return L1's TSC value to ensure backwards-compatible
3979 * behavior for migration.
3983 if (msr_info->host_initiated) {
3984 offset = vcpu->arch.l1_tsc_offset;
3985 ratio = vcpu->arch.l1_tsc_scaling_ratio;
3987 offset = vcpu->arch.tsc_offset;
3988 ratio = vcpu->arch.tsc_scaling_ratio;
3991 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset;
3995 case 0x200 ... MSR_IA32_MC0_CTL2 - 1:
3996 case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff:
3997 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
3998 case 0xcd: /* fsb frequency */
4002 * MSR_EBC_FREQUENCY_ID
4003 * Conservative value valid for even the basic CPU models.
4004 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
4005 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
4006 * and 266MHz for model 3, or 4. Set Core Clock
4007 * Frequency to System Bus Frequency Ratio to 1 (bits
4008 * 31:24) even though these are only valid for CPU
4009 * models > 2, however guests may end up dividing or
4010 * multiplying by zero otherwise.
4012 case MSR_EBC_FREQUENCY_ID:
4013 msr_info->data = 1 << 24;
4015 case MSR_IA32_APICBASE:
4016 msr_info->data = kvm_get_apic_base(vcpu);
4018 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
4019 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
4020 case MSR_IA32_TSC_DEADLINE:
4021 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
4023 case MSR_IA32_TSC_ADJUST:
4024 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
4026 case MSR_IA32_MISC_ENABLE:
4027 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
4029 case MSR_IA32_SMBASE:
4030 if (!msr_info->host_initiated)
4032 msr_info->data = vcpu->arch.smbase;
4035 msr_info->data = vcpu->arch.smi_count;
4037 case MSR_IA32_PERF_STATUS:
4038 /* TSC increment by tick */
4039 msr_info->data = 1000ULL;
4040 /* CPU multiplier */
4041 msr_info->data |= (((uint64_t)4ULL) << 40);
4044 msr_info->data = vcpu->arch.efer;
4046 case MSR_KVM_WALL_CLOCK:
4047 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4050 msr_info->data = vcpu->kvm->arch.wall_clock;
4052 case MSR_KVM_WALL_CLOCK_NEW:
4053 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4056 msr_info->data = vcpu->kvm->arch.wall_clock;
4058 case MSR_KVM_SYSTEM_TIME:
4059 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4062 msr_info->data = vcpu->arch.time;
4064 case MSR_KVM_SYSTEM_TIME_NEW:
4065 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4068 msr_info->data = vcpu->arch.time;
4070 case MSR_KVM_ASYNC_PF_EN:
4071 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
4074 msr_info->data = vcpu->arch.apf.msr_en_val;
4076 case MSR_KVM_ASYNC_PF_INT:
4077 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4080 msr_info->data = vcpu->arch.apf.msr_int_val;
4082 case MSR_KVM_ASYNC_PF_ACK:
4083 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4088 case MSR_KVM_STEAL_TIME:
4089 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
4092 msr_info->data = vcpu->arch.st.msr_val;
4094 case MSR_KVM_PV_EOI_EN:
4095 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
4098 msr_info->data = vcpu->arch.pv_eoi.msr_val;
4100 case MSR_KVM_POLL_CONTROL:
4101 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
4104 msr_info->data = vcpu->arch.msr_kvm_poll_control;
4106 case MSR_IA32_P5_MC_ADDR:
4107 case MSR_IA32_P5_MC_TYPE:
4108 case MSR_IA32_MCG_CAP:
4109 case MSR_IA32_MCG_CTL:
4110 case MSR_IA32_MCG_STATUS:
4111 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4112 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4113 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
4114 msr_info->host_initiated);
4116 if (!msr_info->host_initiated &&
4117 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
4119 msr_info->data = vcpu->arch.ia32_xss;
4121 case MSR_K7_CLK_CTL:
4123 * Provide expected ramp-up count for K7. All other
4124 * are set to zero, indicating minimum divisors for
4127 * This prevents guest kernels on AMD host with CPU
4128 * type 6, model 8 and higher from exploding due to
4129 * the rdmsr failing.
4131 msr_info->data = 0x20000000;
4133 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4134 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4135 case HV_X64_MSR_SYNDBG_OPTIONS:
4136 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4137 case HV_X64_MSR_CRASH_CTL:
4138 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4139 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4140 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4141 case HV_X64_MSR_TSC_EMULATION_STATUS:
4142 return kvm_hv_get_msr_common(vcpu,
4143 msr_info->index, &msr_info->data,
4144 msr_info->host_initiated);
4145 case MSR_IA32_BBL_CR_CTL3:
4146 /* This legacy MSR exists but isn't fully documented in current
4147 * silicon. It is however accessed by winxp in very narrow
4148 * scenarios where it sets bit #19, itself documented as
4149 * a "reserved" bit. Best effort attempt to source coherent
4150 * read data here should the balance of the register be
4151 * interpreted by the guest:
4153 * L2 cache control register 3: 64GB range, 256KB size,
4154 * enabled, latency 0x1, configured
4156 msr_info->data = 0xbe702111;
4158 case MSR_AMD64_OSVW_ID_LENGTH:
4159 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4161 msr_info->data = vcpu->arch.osvw.length;
4163 case MSR_AMD64_OSVW_STATUS:
4164 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4166 msr_info->data = vcpu->arch.osvw.status;
4168 case MSR_PLATFORM_INFO:
4169 if (!msr_info->host_initiated &&
4170 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
4172 msr_info->data = vcpu->arch.msr_platform_info;
4174 case MSR_MISC_FEATURES_ENABLES:
4175 msr_info->data = vcpu->arch.msr_misc_features_enables;
4178 msr_info->data = vcpu->arch.msr_hwcr;
4180 #ifdef CONFIG_X86_64
4182 if (!msr_info->host_initiated &&
4183 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4186 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd;
4188 case MSR_IA32_XFD_ERR:
4189 if (!msr_info->host_initiated &&
4190 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4193 msr_info->data = vcpu->arch.guest_fpu.xfd_err;
4197 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4198 return kvm_pmu_get_msr(vcpu, msr_info);
4199 return KVM_MSR_RET_INVALID;
4203 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
4206 * Read or write a bunch of msrs. All parameters are kernel addresses.
4208 * @return number of msrs set successfully.
4210 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
4211 struct kvm_msr_entry *entries,
4212 int (*do_msr)(struct kvm_vcpu *vcpu,
4213 unsigned index, u64 *data))
4217 for (i = 0; i < msrs->nmsrs; ++i)
4218 if (do_msr(vcpu, entries[i].index, &entries[i].data))
4225 * Read or write a bunch of msrs. Parameters are user addresses.
4227 * @return number of msrs set successfully.
4229 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
4230 int (*do_msr)(struct kvm_vcpu *vcpu,
4231 unsigned index, u64 *data),
4234 struct kvm_msrs msrs;
4235 struct kvm_msr_entry *entries;
4240 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
4244 if (msrs.nmsrs >= MAX_IO_MSRS)
4247 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
4248 entries = memdup_user(user_msrs->entries, size);
4249 if (IS_ERR(entries)) {
4250 r = PTR_ERR(entries);
4254 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
4259 if (writeback && copy_to_user(user_msrs->entries, entries, size))
4270 static inline bool kvm_can_mwait_in_guest(void)
4272 return boot_cpu_has(X86_FEATURE_MWAIT) &&
4273 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
4274 boot_cpu_has(X86_FEATURE_ARAT);
4277 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
4278 struct kvm_cpuid2 __user *cpuid_arg)
4280 struct kvm_cpuid2 cpuid;
4284 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4287 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4292 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4298 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
4303 case KVM_CAP_IRQCHIP:
4305 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
4306 case KVM_CAP_SET_TSS_ADDR:
4307 case KVM_CAP_EXT_CPUID:
4308 case KVM_CAP_EXT_EMUL_CPUID:
4309 case KVM_CAP_CLOCKSOURCE:
4311 case KVM_CAP_NOP_IO_DELAY:
4312 case KVM_CAP_MP_STATE:
4313 case KVM_CAP_SYNC_MMU:
4314 case KVM_CAP_USER_NMI:
4315 case KVM_CAP_REINJECT_CONTROL:
4316 case KVM_CAP_IRQ_INJECT_STATUS:
4317 case KVM_CAP_IOEVENTFD:
4318 case KVM_CAP_IOEVENTFD_NO_LENGTH:
4320 case KVM_CAP_PIT_STATE2:
4321 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
4322 case KVM_CAP_VCPU_EVENTS:
4323 case KVM_CAP_HYPERV:
4324 case KVM_CAP_HYPERV_VAPIC:
4325 case KVM_CAP_HYPERV_SPIN:
4326 case KVM_CAP_HYPERV_SYNIC:
4327 case KVM_CAP_HYPERV_SYNIC2:
4328 case KVM_CAP_HYPERV_VP_INDEX:
4329 case KVM_CAP_HYPERV_EVENTFD:
4330 case KVM_CAP_HYPERV_TLBFLUSH:
4331 case KVM_CAP_HYPERV_SEND_IPI:
4332 case KVM_CAP_HYPERV_CPUID:
4333 case KVM_CAP_HYPERV_ENFORCE_CPUID:
4334 case KVM_CAP_SYS_HYPERV_CPUID:
4335 case KVM_CAP_PCI_SEGMENT:
4336 case KVM_CAP_DEBUGREGS:
4337 case KVM_CAP_X86_ROBUST_SINGLESTEP:
4339 case KVM_CAP_ASYNC_PF:
4340 case KVM_CAP_ASYNC_PF_INT:
4341 case KVM_CAP_GET_TSC_KHZ:
4342 case KVM_CAP_KVMCLOCK_CTRL:
4343 case KVM_CAP_READONLY_MEM:
4344 case KVM_CAP_HYPERV_TIME:
4345 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
4346 case KVM_CAP_TSC_DEADLINE_TIMER:
4347 case KVM_CAP_DISABLE_QUIRKS:
4348 case KVM_CAP_SET_BOOT_CPU_ID:
4349 case KVM_CAP_SPLIT_IRQCHIP:
4350 case KVM_CAP_IMMEDIATE_EXIT:
4351 case KVM_CAP_PMU_EVENT_FILTER:
4352 case KVM_CAP_GET_MSR_FEATURES:
4353 case KVM_CAP_MSR_PLATFORM_INFO:
4354 case KVM_CAP_EXCEPTION_PAYLOAD:
4355 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
4356 case KVM_CAP_SET_GUEST_DEBUG:
4357 case KVM_CAP_LAST_CPU:
4358 case KVM_CAP_X86_USER_SPACE_MSR:
4359 case KVM_CAP_X86_MSR_FILTER:
4360 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4361 #ifdef CONFIG_X86_SGX_KVM
4362 case KVM_CAP_SGX_ATTRIBUTE:
4364 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
4365 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
4366 case KVM_CAP_SREGS2:
4367 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
4368 case KVM_CAP_VCPU_ATTRIBUTES:
4369 case KVM_CAP_SYS_ATTRIBUTES:
4371 case KVM_CAP_ENABLE_CAP:
4372 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
4375 case KVM_CAP_EXIT_HYPERCALL:
4376 r = KVM_EXIT_HYPERCALL_VALID_MASK;
4378 case KVM_CAP_SET_GUEST_DEBUG2:
4379 return KVM_GUESTDBG_VALID_MASK;
4380 #ifdef CONFIG_KVM_XEN
4381 case KVM_CAP_XEN_HVM:
4382 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR |
4383 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL |
4384 KVM_XEN_HVM_CONFIG_SHARED_INFO |
4385 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL |
4386 KVM_XEN_HVM_CONFIG_EVTCHN_SEND;
4387 if (sched_info_on())
4388 r |= KVM_XEN_HVM_CONFIG_RUNSTATE;
4391 case KVM_CAP_SYNC_REGS:
4392 r = KVM_SYNC_X86_VALID_FIELDS;
4394 case KVM_CAP_ADJUST_CLOCK:
4395 r = KVM_CLOCK_VALID_FLAGS;
4397 case KVM_CAP_X86_DISABLE_EXITS:
4398 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
4399 KVM_X86_DISABLE_EXITS_CSTATE;
4400 if(kvm_can_mwait_in_guest())
4401 r |= KVM_X86_DISABLE_EXITS_MWAIT;
4403 case KVM_CAP_X86_SMM:
4404 /* SMBASE is usually relocated above 1M on modern chipsets,
4405 * and SMM handlers might indeed rely on 4G segment limits,
4406 * so do not report SMM to be available if real mode is
4407 * emulated via vm86 mode. Still, do not go to great lengths
4408 * to avoid userspace's usage of the feature, because it is a
4409 * fringe case that is not enabled except via specific settings
4410 * of the module parameters.
4412 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE);
4414 case KVM_CAP_NR_VCPUS:
4415 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
4417 case KVM_CAP_MAX_VCPUS:
4420 case KVM_CAP_MAX_VCPU_ID:
4421 r = KVM_MAX_VCPU_IDS;
4423 case KVM_CAP_PV_MMU: /* obsolete */
4427 r = KVM_MAX_MCE_BANKS;
4430 r = boot_cpu_has(X86_FEATURE_XSAVE);
4432 case KVM_CAP_TSC_CONTROL:
4433 case KVM_CAP_VM_TSC_CONTROL:
4434 r = kvm_caps.has_tsc_control;
4436 case KVM_CAP_X2APIC_API:
4437 r = KVM_X2APIC_API_VALID_FLAGS;
4439 case KVM_CAP_NESTED_STATE:
4440 r = kvm_x86_ops.nested_ops->get_state ?
4441 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
4443 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4444 r = kvm_x86_ops.enable_direct_tlbflush != NULL;
4446 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4447 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
4449 case KVM_CAP_SMALLER_MAXPHYADDR:
4450 r = (int) allow_smaller_maxphyaddr;
4452 case KVM_CAP_STEAL_TIME:
4453 r = sched_info_on();
4455 case KVM_CAP_X86_BUS_LOCK_EXIT:
4456 if (kvm_caps.has_bus_lock_exit)
4457 r = KVM_BUS_LOCK_DETECTION_OFF |
4458 KVM_BUS_LOCK_DETECTION_EXIT;
4462 case KVM_CAP_XSAVE2: {
4463 u64 guest_perm = xstate_get_guest_group_perm();
4465 r = xstate_required_size(kvm_caps.supported_xcr0 & guest_perm, false);
4466 if (r < sizeof(struct kvm_xsave))
4467 r = sizeof(struct kvm_xsave);
4470 case KVM_CAP_PMU_CAPABILITY:
4471 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0;
4473 case KVM_CAP_DISABLE_QUIRKS2:
4474 r = KVM_X86_VALID_QUIRKS;
4476 case KVM_CAP_X86_NOTIFY_VMEXIT:
4477 r = kvm_caps.has_notify_vmexit;
4485 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr)
4487 void __user *uaddr = (void __user*)(unsigned long)attr->addr;
4489 if ((u64)(unsigned long)uaddr != attr->addr)
4490 return ERR_PTR_USR(-EFAULT);
4494 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr)
4496 u64 __user *uaddr = kvm_get_attr_addr(attr);
4502 return PTR_ERR(uaddr);
4504 switch (attr->attr) {
4505 case KVM_X86_XCOMP_GUEST_SUPP:
4506 if (put_user(kvm_caps.supported_xcr0, uaddr))
4515 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr)
4520 switch (attr->attr) {
4521 case KVM_X86_XCOMP_GUEST_SUPP:
4528 long kvm_arch_dev_ioctl(struct file *filp,
4529 unsigned int ioctl, unsigned long arg)
4531 void __user *argp = (void __user *)arg;
4535 case KVM_GET_MSR_INDEX_LIST: {
4536 struct kvm_msr_list __user *user_msr_list = argp;
4537 struct kvm_msr_list msr_list;
4541 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4544 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
4545 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4548 if (n < msr_list.nmsrs)
4551 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
4552 num_msrs_to_save * sizeof(u32)))
4554 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
4556 num_emulated_msrs * sizeof(u32)))
4561 case KVM_GET_SUPPORTED_CPUID:
4562 case KVM_GET_EMULATED_CPUID: {
4563 struct kvm_cpuid2 __user *cpuid_arg = argp;
4564 struct kvm_cpuid2 cpuid;
4567 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4570 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
4576 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4581 case KVM_X86_GET_MCE_CAP_SUPPORTED:
4583 if (copy_to_user(argp, &kvm_caps.supported_mce_cap,
4584 sizeof(kvm_caps.supported_mce_cap)))
4588 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
4589 struct kvm_msr_list __user *user_msr_list = argp;
4590 struct kvm_msr_list msr_list;
4594 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4597 msr_list.nmsrs = num_msr_based_features;
4598 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4601 if (n < msr_list.nmsrs)
4604 if (copy_to_user(user_msr_list->indices, &msr_based_features,
4605 num_msr_based_features * sizeof(u32)))
4611 r = msr_io(NULL, argp, do_get_msr_feature, 1);
4613 case KVM_GET_SUPPORTED_HV_CPUID:
4614 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
4616 case KVM_GET_DEVICE_ATTR: {
4617 struct kvm_device_attr attr;
4619 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4621 r = kvm_x86_dev_get_attr(&attr);
4624 case KVM_HAS_DEVICE_ATTR: {
4625 struct kvm_device_attr attr;
4627 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4629 r = kvm_x86_dev_has_attr(&attr);
4640 static void wbinvd_ipi(void *garbage)
4645 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
4647 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
4650 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
4652 /* Address WBINVD may be executed by guest */
4653 if (need_emulate_wbinvd(vcpu)) {
4654 if (static_call(kvm_x86_has_wbinvd_exit)())
4655 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4656 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
4657 smp_call_function_single(vcpu->cpu,
4658 wbinvd_ipi, NULL, 1);
4661 static_call(kvm_x86_vcpu_load)(vcpu, cpu);
4663 /* Save host pkru register if supported */
4664 vcpu->arch.host_pkru = read_pkru();
4666 /* Apply any externally detected TSC adjustments (due to suspend) */
4667 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
4668 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
4669 vcpu->arch.tsc_offset_adjustment = 0;
4670 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4673 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
4674 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4675 rdtsc() - vcpu->arch.last_host_tsc;
4677 mark_tsc_unstable("KVM discovered backwards TSC");
4679 if (kvm_check_tsc_unstable()) {
4680 u64 offset = kvm_compute_l1_tsc_offset(vcpu,
4681 vcpu->arch.last_guest_tsc);
4682 kvm_vcpu_write_tsc_offset(vcpu, offset);
4683 vcpu->arch.tsc_catchup = 1;
4686 if (kvm_lapic_hv_timer_in_use(vcpu))
4687 kvm_lapic_restart_hv_timer(vcpu);
4690 * On a host with synchronized TSC, there is no need to update
4691 * kvmclock on vcpu->cpu migration
4693 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
4694 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
4695 if (vcpu->cpu != cpu)
4696 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
4700 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4703 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4705 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
4706 struct kvm_steal_time __user *st;
4707 struct kvm_memslots *slots;
4708 static const u8 preempted = KVM_VCPU_PREEMPTED;
4711 * The vCPU can be marked preempted if and only if the VM-Exit was on
4712 * an instruction boundary and will not trigger guest emulation of any
4713 * kind (see vcpu_run). Vendor specific code controls (conservatively)
4714 * when this is true, for example allowing the vCPU to be marked
4715 * preempted if and only if the VM-Exit was due to a host interrupt.
4717 if (!vcpu->arch.at_instruction_boundary) {
4718 vcpu->stat.preemption_other++;
4722 vcpu->stat.preemption_reported++;
4723 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4726 if (vcpu->arch.st.preempted)
4729 /* This happens on process exit */
4730 if (unlikely(current->mm != vcpu->kvm->mm))
4733 slots = kvm_memslots(vcpu->kvm);
4735 if (unlikely(slots->generation != ghc->generation ||
4736 kvm_is_error_hva(ghc->hva) || !ghc->memslot))
4739 st = (struct kvm_steal_time __user *)ghc->hva;
4740 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted));
4742 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted)))
4743 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4745 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
4748 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4752 if (vcpu->preempted) {
4753 if (!vcpu->arch.guest_state_protected)
4754 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu);
4757 * Take the srcu lock as memslots will be accessed to check the gfn
4758 * cache generation against the memslots generation.
4760 idx = srcu_read_lock(&vcpu->kvm->srcu);
4761 if (kvm_xen_msr_enabled(vcpu->kvm))
4762 kvm_xen_runstate_set_preempted(vcpu);
4764 kvm_steal_time_set_preempted(vcpu);
4765 srcu_read_unlock(&vcpu->kvm->srcu, idx);
4768 static_call(kvm_x86_vcpu_put)(vcpu);
4769 vcpu->arch.last_host_tsc = rdtsc();
4772 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4773 struct kvm_lapic_state *s)
4775 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
4777 return kvm_apic_get_state(vcpu, s);
4780 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4781 struct kvm_lapic_state *s)
4785 r = kvm_apic_set_state(vcpu, s);
4788 update_cr8_intercept(vcpu);
4793 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4796 * We can accept userspace's request for interrupt injection
4797 * as long as we have a place to store the interrupt number.
4798 * The actual injection will happen when the CPU is able to
4799 * deliver the interrupt.
4801 if (kvm_cpu_has_extint(vcpu))
4804 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
4805 return (!lapic_in_kernel(vcpu) ||
4806 kvm_apic_accept_pic_intr(vcpu));
4809 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4812 * Do not cause an interrupt window exit if an exception
4813 * is pending or an event needs reinjection; userspace
4814 * might want to inject the interrupt manually using KVM_SET_REGS
4815 * or KVM_SET_SREGS. For that to work, we must be at an
4816 * instruction boundary and with no events half-injected.
4818 return (kvm_arch_interrupt_allowed(vcpu) &&
4819 kvm_cpu_accept_dm_intr(vcpu) &&
4820 !kvm_event_needs_reinjection(vcpu) &&
4821 !vcpu->arch.exception.pending);
4824 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4825 struct kvm_interrupt *irq)
4827 if (irq->irq >= KVM_NR_INTERRUPTS)
4830 if (!irqchip_in_kernel(vcpu->kvm)) {
4831 kvm_queue_interrupt(vcpu, irq->irq, false);
4832 kvm_make_request(KVM_REQ_EVENT, vcpu);
4837 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4838 * fail for in-kernel 8259.
4840 if (pic_in_kernel(vcpu->kvm))
4843 if (vcpu->arch.pending_external_vector != -1)
4846 vcpu->arch.pending_external_vector = irq->irq;
4847 kvm_make_request(KVM_REQ_EVENT, vcpu);
4851 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
4853 kvm_inject_nmi(vcpu);
4858 static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
4860 kvm_make_request(KVM_REQ_SMI, vcpu);
4865 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
4866 struct kvm_tpr_access_ctl *tac)
4870 vcpu->arch.tpr_access_reporting = !!tac->enabled;
4874 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
4878 unsigned bank_num = mcg_cap & 0xff, bank;
4881 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
4883 if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000))
4886 vcpu->arch.mcg_cap = mcg_cap;
4887 /* Init IA32_MCG_CTL to all 1s */
4888 if (mcg_cap & MCG_CTL_P)
4889 vcpu->arch.mcg_ctl = ~(u64)0;
4890 /* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */
4891 for (bank = 0; bank < bank_num; bank++) {
4892 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
4893 if (mcg_cap & MCG_CMCI_P)
4894 vcpu->arch.mci_ctl2_banks[bank] = 0;
4896 vcpu->arch.apic->nr_lvt_entries =
4897 KVM_APIC_MAX_NR_LVT_ENTRIES - !(mcg_cap & MCG_CMCI_P);
4899 static_call(kvm_x86_setup_mce)(vcpu);
4905 * Validate this is an UCNA (uncorrectable no action) error by checking the
4906 * MCG_STATUS and MCi_STATUS registers:
4907 * - none of the bits for Machine Check Exceptions are set
4908 * - both the VAL (valid) and UC (uncorrectable) bits are set
4909 * MCI_STATUS_PCC - Processor Context Corrupted
4910 * MCI_STATUS_S - Signaled as a Machine Check Exception
4911 * MCI_STATUS_AR - Software recoverable Action Required
4913 static bool is_ucna(struct kvm_x86_mce *mce)
4915 return !mce->mcg_status &&
4916 !(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) &&
4917 (mce->status & MCI_STATUS_VAL) &&
4918 (mce->status & MCI_STATUS_UC);
4921 static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks)
4923 u64 mcg_cap = vcpu->arch.mcg_cap;
4925 banks[1] = mce->status;
4926 banks[2] = mce->addr;
4927 banks[3] = mce->misc;
4928 vcpu->arch.mcg_status = mce->mcg_status;
4930 if (!(mcg_cap & MCG_CMCI_P) ||
4931 !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN))
4934 if (lapic_in_kernel(vcpu))
4935 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI);
4940 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
4941 struct kvm_x86_mce *mce)
4943 u64 mcg_cap = vcpu->arch.mcg_cap;
4944 unsigned bank_num = mcg_cap & 0xff;
4945 u64 *banks = vcpu->arch.mce_banks;
4947 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
4950 banks += array_index_nospec(4 * mce->bank, 4 * bank_num);
4953 return kvm_vcpu_x86_set_ucna(vcpu, mce, banks);
4956 * if IA32_MCG_CTL is not all 1s, the uncorrected error
4957 * reporting is disabled
4959 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
4960 vcpu->arch.mcg_ctl != ~(u64)0)
4963 * if IA32_MCi_CTL is not all 1s, the uncorrected error
4964 * reporting is disabled for the bank
4966 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
4968 if (mce->status & MCI_STATUS_UC) {
4969 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
4970 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
4971 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4974 if (banks[1] & MCI_STATUS_VAL)
4975 mce->status |= MCI_STATUS_OVER;
4976 banks[2] = mce->addr;
4977 banks[3] = mce->misc;
4978 vcpu->arch.mcg_status = mce->mcg_status;
4979 banks[1] = mce->status;
4980 kvm_queue_exception(vcpu, MC_VECTOR);
4981 } else if (!(banks[1] & MCI_STATUS_VAL)
4982 || !(banks[1] & MCI_STATUS_UC)) {
4983 if (banks[1] & MCI_STATUS_VAL)
4984 mce->status |= MCI_STATUS_OVER;
4985 banks[2] = mce->addr;
4986 banks[3] = mce->misc;
4987 banks[1] = mce->status;
4989 banks[1] |= MCI_STATUS_OVER;
4993 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
4994 struct kvm_vcpu_events *events)
4998 if (kvm_check_request(KVM_REQ_SMI, vcpu))
5002 * In guest mode, payload delivery should be deferred,
5003 * so that the L1 hypervisor can intercept #PF before
5004 * CR2 is modified (or intercept #DB before DR6 is
5005 * modified under nVMX). Unless the per-VM capability,
5006 * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of
5007 * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we
5008 * opportunistically defer the exception payload, deliver it if the
5009 * capability hasn't been requested before processing a
5010 * KVM_GET_VCPU_EVENTS.
5012 if (!vcpu->kvm->arch.exception_payload_enabled &&
5013 vcpu->arch.exception.pending && vcpu->arch.exception.has_payload)
5014 kvm_deliver_exception_payload(vcpu);
5017 * The API doesn't provide the instruction length for software
5018 * exceptions, so don't report them. As long as the guest RIP
5019 * isn't advanced, we should expect to encounter the exception
5022 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
5023 events->exception.injected = 0;
5024 events->exception.pending = 0;
5026 events->exception.injected = vcpu->arch.exception.injected;
5027 events->exception.pending = vcpu->arch.exception.pending;
5029 * For ABI compatibility, deliberately conflate
5030 * pending and injected exceptions when
5031 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
5033 if (!vcpu->kvm->arch.exception_payload_enabled)
5034 events->exception.injected |=
5035 vcpu->arch.exception.pending;
5037 events->exception.nr = vcpu->arch.exception.nr;
5038 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
5039 events->exception.error_code = vcpu->arch.exception.error_code;
5040 events->exception_has_payload = vcpu->arch.exception.has_payload;
5041 events->exception_payload = vcpu->arch.exception.payload;
5043 events->interrupt.injected =
5044 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
5045 events->interrupt.nr = vcpu->arch.interrupt.nr;
5046 events->interrupt.soft = 0;
5047 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
5049 events->nmi.injected = vcpu->arch.nmi_injected;
5050 events->nmi.pending = vcpu->arch.nmi_pending != 0;
5051 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu);
5052 events->nmi.pad = 0;
5054 events->sipi_vector = 0; /* never valid when reporting to user space */
5056 events->smi.smm = is_smm(vcpu);
5057 events->smi.pending = vcpu->arch.smi_pending;
5058 events->smi.smm_inside_nmi =
5059 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
5060 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
5062 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
5063 | KVM_VCPUEVENT_VALID_SHADOW
5064 | KVM_VCPUEVENT_VALID_SMM);
5065 if (vcpu->kvm->arch.exception_payload_enabled)
5066 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
5067 if (vcpu->kvm->arch.triple_fault_event) {
5068 events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5069 events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
5072 memset(&events->reserved, 0, sizeof(events->reserved));
5075 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm);
5077 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
5078 struct kvm_vcpu_events *events)
5080 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
5081 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
5082 | KVM_VCPUEVENT_VALID_SHADOW
5083 | KVM_VCPUEVENT_VALID_SMM
5084 | KVM_VCPUEVENT_VALID_PAYLOAD
5085 | KVM_VCPUEVENT_VALID_TRIPLE_FAULT))
5088 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
5089 if (!vcpu->kvm->arch.exception_payload_enabled)
5091 if (events->exception.pending)
5092 events->exception.injected = 0;
5094 events->exception_has_payload = 0;
5096 events->exception.pending = 0;
5097 events->exception_has_payload = 0;
5100 if ((events->exception.injected || events->exception.pending) &&
5101 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
5104 /* INITs are latched while in SMM */
5105 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
5106 (events->smi.smm || events->smi.pending) &&
5107 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
5111 vcpu->arch.exception.injected = events->exception.injected;
5112 vcpu->arch.exception.pending = events->exception.pending;
5113 vcpu->arch.exception.nr = events->exception.nr;
5114 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
5115 vcpu->arch.exception.error_code = events->exception.error_code;
5116 vcpu->arch.exception.has_payload = events->exception_has_payload;
5117 vcpu->arch.exception.payload = events->exception_payload;
5119 vcpu->arch.interrupt.injected = events->interrupt.injected;
5120 vcpu->arch.interrupt.nr = events->interrupt.nr;
5121 vcpu->arch.interrupt.soft = events->interrupt.soft;
5122 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
5123 static_call(kvm_x86_set_interrupt_shadow)(vcpu,
5124 events->interrupt.shadow);
5126 vcpu->arch.nmi_injected = events->nmi.injected;
5127 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
5128 vcpu->arch.nmi_pending = events->nmi.pending;
5129 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked);
5131 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
5132 lapic_in_kernel(vcpu))
5133 vcpu->arch.apic->sipi_vector = events->sipi_vector;
5135 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
5136 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
5137 kvm_x86_ops.nested_ops->leave_nested(vcpu);
5138 kvm_smm_changed(vcpu, events->smi.smm);
5141 vcpu->arch.smi_pending = events->smi.pending;
5143 if (events->smi.smm) {
5144 if (events->smi.smm_inside_nmi)
5145 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
5147 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
5150 if (lapic_in_kernel(vcpu)) {
5151 if (events->smi.latched_init)
5152 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5154 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5158 if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
5159 if (!vcpu->kvm->arch.triple_fault_event)
5161 if (events->triple_fault.pending)
5162 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5164 kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5167 kvm_make_request(KVM_REQ_EVENT, vcpu);
5172 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
5173 struct kvm_debugregs *dbgregs)
5177 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
5178 kvm_get_dr(vcpu, 6, &val);
5180 dbgregs->dr7 = vcpu->arch.dr7;
5182 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
5185 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
5186 struct kvm_debugregs *dbgregs)
5191 if (!kvm_dr6_valid(dbgregs->dr6))
5193 if (!kvm_dr7_valid(dbgregs->dr7))
5196 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
5197 kvm_update_dr0123(vcpu);
5198 vcpu->arch.dr6 = dbgregs->dr6;
5199 vcpu->arch.dr7 = dbgregs->dr7;
5200 kvm_update_dr7(vcpu);
5205 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
5206 struct kvm_xsave *guest_xsave)
5208 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5211 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5212 guest_xsave->region,
5213 sizeof(guest_xsave->region),
5217 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu,
5218 u8 *state, unsigned int size)
5220 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5223 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu,
5224 state, size, vcpu->arch.pkru);
5227 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
5228 struct kvm_xsave *guest_xsave)
5230 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5233 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu,
5234 guest_xsave->region,
5235 kvm_caps.supported_xcr0,
5239 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
5240 struct kvm_xcrs *guest_xcrs)
5242 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
5243 guest_xcrs->nr_xcrs = 0;
5247 guest_xcrs->nr_xcrs = 1;
5248 guest_xcrs->flags = 0;
5249 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
5250 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
5253 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
5254 struct kvm_xcrs *guest_xcrs)
5258 if (!boot_cpu_has(X86_FEATURE_XSAVE))
5261 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
5264 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
5265 /* Only support XCR0 currently */
5266 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
5267 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
5268 guest_xcrs->xcrs[i].value);
5277 * kvm_set_guest_paused() indicates to the guest kernel that it has been
5278 * stopped by the hypervisor. This function will be called from the host only.
5279 * EINVAL is returned when the host attempts to set the flag for a guest that
5280 * does not support pv clocks.
5282 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
5284 if (!vcpu->arch.pv_time.active)
5286 vcpu->arch.pvclock_set_guest_stopped_request = true;
5287 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5291 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu,
5292 struct kvm_device_attr *attr)
5296 switch (attr->attr) {
5297 case KVM_VCPU_TSC_OFFSET:
5307 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu,
5308 struct kvm_device_attr *attr)
5310 u64 __user *uaddr = kvm_get_attr_addr(attr);
5314 return PTR_ERR(uaddr);
5316 switch (attr->attr) {
5317 case KVM_VCPU_TSC_OFFSET:
5319 if (put_user(vcpu->arch.l1_tsc_offset, uaddr))
5330 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu,
5331 struct kvm_device_attr *attr)
5333 u64 __user *uaddr = kvm_get_attr_addr(attr);
5334 struct kvm *kvm = vcpu->kvm;
5338 return PTR_ERR(uaddr);
5340 switch (attr->attr) {
5341 case KVM_VCPU_TSC_OFFSET: {
5342 u64 offset, tsc, ns;
5343 unsigned long flags;
5347 if (get_user(offset, uaddr))
5350 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
5352 matched = (vcpu->arch.virtual_tsc_khz &&
5353 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz &&
5354 kvm->arch.last_tsc_offset == offset);
5356 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset;
5357 ns = get_kvmclock_base_ns();
5359 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched);
5360 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
5372 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu,
5376 struct kvm_device_attr attr;
5379 if (copy_from_user(&attr, argp, sizeof(attr)))
5382 if (attr.group != KVM_VCPU_TSC_CTRL)
5386 case KVM_HAS_DEVICE_ATTR:
5387 r = kvm_arch_tsc_has_attr(vcpu, &attr);
5389 case KVM_GET_DEVICE_ATTR:
5390 r = kvm_arch_tsc_get_attr(vcpu, &attr);
5392 case KVM_SET_DEVICE_ATTR:
5393 r = kvm_arch_tsc_set_attr(vcpu, &attr);
5400 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
5401 struct kvm_enable_cap *cap)
5404 uint16_t vmcs_version;
5405 void __user *user_ptr;
5411 case KVM_CAP_HYPERV_SYNIC2:
5416 case KVM_CAP_HYPERV_SYNIC:
5417 if (!irqchip_in_kernel(vcpu->kvm))
5419 return kvm_hv_activate_synic(vcpu, cap->cap ==
5420 KVM_CAP_HYPERV_SYNIC2);
5421 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5422 if (!kvm_x86_ops.nested_ops->enable_evmcs)
5424 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
5426 user_ptr = (void __user *)(uintptr_t)cap->args[0];
5427 if (copy_to_user(user_ptr, &vmcs_version,
5428 sizeof(vmcs_version)))
5432 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5433 if (!kvm_x86_ops.enable_direct_tlbflush)
5436 return static_call(kvm_x86_enable_direct_tlbflush)(vcpu);
5438 case KVM_CAP_HYPERV_ENFORCE_CPUID:
5439 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]);
5441 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
5442 vcpu->arch.pv_cpuid.enforce = cap->args[0];
5443 if (vcpu->arch.pv_cpuid.enforce)
5444 kvm_update_pv_runtime(vcpu);
5452 long kvm_arch_vcpu_ioctl(struct file *filp,
5453 unsigned int ioctl, unsigned long arg)
5455 struct kvm_vcpu *vcpu = filp->private_data;
5456 void __user *argp = (void __user *)arg;
5459 struct kvm_sregs2 *sregs2;
5460 struct kvm_lapic_state *lapic;
5461 struct kvm_xsave *xsave;
5462 struct kvm_xcrs *xcrs;
5470 case KVM_GET_LAPIC: {
5472 if (!lapic_in_kernel(vcpu))
5474 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
5475 GFP_KERNEL_ACCOUNT);
5480 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
5484 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
5489 case KVM_SET_LAPIC: {
5491 if (!lapic_in_kernel(vcpu))
5493 u.lapic = memdup_user(argp, sizeof(*u.lapic));
5494 if (IS_ERR(u.lapic)) {
5495 r = PTR_ERR(u.lapic);
5499 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
5502 case KVM_INTERRUPT: {
5503 struct kvm_interrupt irq;
5506 if (copy_from_user(&irq, argp, sizeof(irq)))
5508 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
5512 r = kvm_vcpu_ioctl_nmi(vcpu);
5516 r = kvm_vcpu_ioctl_smi(vcpu);
5519 case KVM_SET_CPUID: {
5520 struct kvm_cpuid __user *cpuid_arg = argp;
5521 struct kvm_cpuid cpuid;
5524 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5526 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
5529 case KVM_SET_CPUID2: {
5530 struct kvm_cpuid2 __user *cpuid_arg = argp;
5531 struct kvm_cpuid2 cpuid;
5534 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5536 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
5537 cpuid_arg->entries);
5540 case KVM_GET_CPUID2: {
5541 struct kvm_cpuid2 __user *cpuid_arg = argp;
5542 struct kvm_cpuid2 cpuid;
5545 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5547 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
5548 cpuid_arg->entries);
5552 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
5557 case KVM_GET_MSRS: {
5558 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5559 r = msr_io(vcpu, argp, do_get_msr, 1);
5560 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5563 case KVM_SET_MSRS: {
5564 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5565 r = msr_io(vcpu, argp, do_set_msr, 0);
5566 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5569 case KVM_TPR_ACCESS_REPORTING: {
5570 struct kvm_tpr_access_ctl tac;
5573 if (copy_from_user(&tac, argp, sizeof(tac)))
5575 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
5579 if (copy_to_user(argp, &tac, sizeof(tac)))
5584 case KVM_SET_VAPIC_ADDR: {
5585 struct kvm_vapic_addr va;
5589 if (!lapic_in_kernel(vcpu))
5592 if (copy_from_user(&va, argp, sizeof(va)))
5594 idx = srcu_read_lock(&vcpu->kvm->srcu);
5595 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
5596 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5599 case KVM_X86_SETUP_MCE: {
5603 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
5605 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
5608 case KVM_X86_SET_MCE: {
5609 struct kvm_x86_mce mce;
5612 if (copy_from_user(&mce, argp, sizeof(mce)))
5614 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
5617 case KVM_GET_VCPU_EVENTS: {
5618 struct kvm_vcpu_events events;
5620 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
5623 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
5628 case KVM_SET_VCPU_EVENTS: {
5629 struct kvm_vcpu_events events;
5632 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
5635 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
5638 case KVM_GET_DEBUGREGS: {
5639 struct kvm_debugregs dbgregs;
5641 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
5644 if (copy_to_user(argp, &dbgregs,
5645 sizeof(struct kvm_debugregs)))
5650 case KVM_SET_DEBUGREGS: {
5651 struct kvm_debugregs dbgregs;
5654 if (copy_from_user(&dbgregs, argp,
5655 sizeof(struct kvm_debugregs)))
5658 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
5661 case KVM_GET_XSAVE: {
5663 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave))
5666 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
5671 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
5674 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
5679 case KVM_SET_XSAVE: {
5680 int size = vcpu->arch.guest_fpu.uabi_size;
5682 u.xsave = memdup_user(argp, size);
5683 if (IS_ERR(u.xsave)) {
5684 r = PTR_ERR(u.xsave);
5688 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
5692 case KVM_GET_XSAVE2: {
5693 int size = vcpu->arch.guest_fpu.uabi_size;
5695 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT);
5700 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size);
5703 if (copy_to_user(argp, u.xsave, size))
5710 case KVM_GET_XCRS: {
5711 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
5716 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
5719 if (copy_to_user(argp, u.xcrs,
5720 sizeof(struct kvm_xcrs)))
5725 case KVM_SET_XCRS: {
5726 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
5727 if (IS_ERR(u.xcrs)) {
5728 r = PTR_ERR(u.xcrs);
5732 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
5735 case KVM_SET_TSC_KHZ: {
5739 user_tsc_khz = (u32)arg;
5741 if (kvm_caps.has_tsc_control &&
5742 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
5745 if (user_tsc_khz == 0)
5746 user_tsc_khz = tsc_khz;
5748 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
5753 case KVM_GET_TSC_KHZ: {
5754 r = vcpu->arch.virtual_tsc_khz;
5757 case KVM_KVMCLOCK_CTRL: {
5758 r = kvm_set_guest_paused(vcpu);
5761 case KVM_ENABLE_CAP: {
5762 struct kvm_enable_cap cap;
5765 if (copy_from_user(&cap, argp, sizeof(cap)))
5767 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
5770 case KVM_GET_NESTED_STATE: {
5771 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5775 if (!kvm_x86_ops.nested_ops->get_state)
5778 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
5780 if (get_user(user_data_size, &user_kvm_nested_state->size))
5783 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
5788 if (r > user_data_size) {
5789 if (put_user(r, &user_kvm_nested_state->size))
5799 case KVM_SET_NESTED_STATE: {
5800 struct kvm_nested_state __user *user_kvm_nested_state = argp;
5801 struct kvm_nested_state kvm_state;
5805 if (!kvm_x86_ops.nested_ops->set_state)
5809 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
5813 if (kvm_state.size < sizeof(kvm_state))
5816 if (kvm_state.flags &
5817 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
5818 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
5819 | KVM_STATE_NESTED_GIF_SET))
5822 /* nested_run_pending implies guest_mode. */
5823 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
5824 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
5827 idx = srcu_read_lock(&vcpu->kvm->srcu);
5828 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
5829 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5832 case KVM_GET_SUPPORTED_HV_CPUID:
5833 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
5835 #ifdef CONFIG_KVM_XEN
5836 case KVM_XEN_VCPU_GET_ATTR: {
5837 struct kvm_xen_vcpu_attr xva;
5840 if (copy_from_user(&xva, argp, sizeof(xva)))
5842 r = kvm_xen_vcpu_get_attr(vcpu, &xva);
5843 if (!r && copy_to_user(argp, &xva, sizeof(xva)))
5847 case KVM_XEN_VCPU_SET_ATTR: {
5848 struct kvm_xen_vcpu_attr xva;
5851 if (copy_from_user(&xva, argp, sizeof(xva)))
5853 r = kvm_xen_vcpu_set_attr(vcpu, &xva);
5857 case KVM_GET_SREGS2: {
5858 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL);
5862 __get_sregs2(vcpu, u.sregs2);
5864 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2)))
5869 case KVM_SET_SREGS2: {
5870 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2));
5871 if (IS_ERR(u.sregs2)) {
5872 r = PTR_ERR(u.sregs2);
5876 r = __set_sregs2(vcpu, u.sregs2);
5879 case KVM_HAS_DEVICE_ATTR:
5880 case KVM_GET_DEVICE_ATTR:
5881 case KVM_SET_DEVICE_ATTR:
5882 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp);
5894 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5896 return VM_FAULT_SIGBUS;
5899 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
5903 if (addr > (unsigned int)(-3 * PAGE_SIZE))
5905 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr);
5909 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
5912 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr);
5915 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
5916 unsigned long kvm_nr_mmu_pages)
5918 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
5921 mutex_lock(&kvm->slots_lock);
5923 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
5924 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
5926 mutex_unlock(&kvm->slots_lock);
5930 static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
5932 return kvm->arch.n_max_mmu_pages;
5935 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5937 struct kvm_pic *pic = kvm->arch.vpic;
5941 switch (chip->chip_id) {
5942 case KVM_IRQCHIP_PIC_MASTER:
5943 memcpy(&chip->chip.pic, &pic->pics[0],
5944 sizeof(struct kvm_pic_state));
5946 case KVM_IRQCHIP_PIC_SLAVE:
5947 memcpy(&chip->chip.pic, &pic->pics[1],
5948 sizeof(struct kvm_pic_state));
5950 case KVM_IRQCHIP_IOAPIC:
5951 kvm_get_ioapic(kvm, &chip->chip.ioapic);
5960 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
5962 struct kvm_pic *pic = kvm->arch.vpic;
5966 switch (chip->chip_id) {
5967 case KVM_IRQCHIP_PIC_MASTER:
5968 spin_lock(&pic->lock);
5969 memcpy(&pic->pics[0], &chip->chip.pic,
5970 sizeof(struct kvm_pic_state));
5971 spin_unlock(&pic->lock);
5973 case KVM_IRQCHIP_PIC_SLAVE:
5974 spin_lock(&pic->lock);
5975 memcpy(&pic->pics[1], &chip->chip.pic,
5976 sizeof(struct kvm_pic_state));
5977 spin_unlock(&pic->lock);
5979 case KVM_IRQCHIP_IOAPIC:
5980 kvm_set_ioapic(kvm, &chip->chip.ioapic);
5986 kvm_pic_update_irq(pic);
5990 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
5992 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
5994 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
5996 mutex_lock(&kps->lock);
5997 memcpy(ps, &kps->channels, sizeof(*ps));
5998 mutex_unlock(&kps->lock);
6002 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6005 struct kvm_pit *pit = kvm->arch.vpit;
6007 mutex_lock(&pit->pit_state.lock);
6008 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
6009 for (i = 0; i < 3; i++)
6010 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
6011 mutex_unlock(&pit->pit_state.lock);
6015 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6017 mutex_lock(&kvm->arch.vpit->pit_state.lock);
6018 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
6019 sizeof(ps->channels));
6020 ps->flags = kvm->arch.vpit->pit_state.flags;
6021 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
6022 memset(&ps->reserved, 0, sizeof(ps->reserved));
6026 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6030 u32 prev_legacy, cur_legacy;
6031 struct kvm_pit *pit = kvm->arch.vpit;
6033 mutex_lock(&pit->pit_state.lock);
6034 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
6035 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
6036 if (!prev_legacy && cur_legacy)
6038 memcpy(&pit->pit_state.channels, &ps->channels,
6039 sizeof(pit->pit_state.channels));
6040 pit->pit_state.flags = ps->flags;
6041 for (i = 0; i < 3; i++)
6042 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
6044 mutex_unlock(&pit->pit_state.lock);
6048 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
6049 struct kvm_reinject_control *control)
6051 struct kvm_pit *pit = kvm->arch.vpit;
6053 /* pit->pit_state.lock was overloaded to prevent userspace from getting
6054 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
6055 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
6057 mutex_lock(&pit->pit_state.lock);
6058 kvm_pit_set_reinject(pit, control->pit_reinject);
6059 mutex_unlock(&pit->pit_state.lock);
6064 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
6068 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called
6069 * before reporting dirty_bitmap to userspace. KVM flushes the buffers
6070 * on all VM-Exits, thus we only need to kick running vCPUs to force a
6073 struct kvm_vcpu *vcpu;
6076 kvm_for_each_vcpu(i, vcpu, kvm)
6077 kvm_vcpu_kick(vcpu);
6080 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
6083 if (!irqchip_in_kernel(kvm))
6086 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
6087 irq_event->irq, irq_event->level,
6092 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
6093 struct kvm_enable_cap *cap)
6101 case KVM_CAP_DISABLE_QUIRKS2:
6103 if (cap->args[0] & ~KVM_X86_VALID_QUIRKS)
6106 case KVM_CAP_DISABLE_QUIRKS:
6107 kvm->arch.disabled_quirks = cap->args[0];
6110 case KVM_CAP_SPLIT_IRQCHIP: {
6111 mutex_lock(&kvm->lock);
6113 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
6114 goto split_irqchip_unlock;
6116 if (irqchip_in_kernel(kvm))
6117 goto split_irqchip_unlock;
6118 if (kvm->created_vcpus)
6119 goto split_irqchip_unlock;
6120 r = kvm_setup_empty_irq_routing(kvm);
6122 goto split_irqchip_unlock;
6123 /* Pairs with irqchip_in_kernel. */
6125 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
6126 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
6127 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6129 split_irqchip_unlock:
6130 mutex_unlock(&kvm->lock);
6133 case KVM_CAP_X2APIC_API:
6135 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
6138 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
6139 kvm->arch.x2apic_format = true;
6140 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
6141 kvm->arch.x2apic_broadcast_quirk_disabled = true;
6145 case KVM_CAP_X86_DISABLE_EXITS:
6147 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
6150 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
6151 kvm_can_mwait_in_guest())
6152 kvm->arch.mwait_in_guest = true;
6153 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
6154 kvm->arch.hlt_in_guest = true;
6155 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
6156 kvm->arch.pause_in_guest = true;
6157 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
6158 kvm->arch.cstate_in_guest = true;
6161 case KVM_CAP_MSR_PLATFORM_INFO:
6162 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
6165 case KVM_CAP_EXCEPTION_PAYLOAD:
6166 kvm->arch.exception_payload_enabled = cap->args[0];
6169 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
6170 kvm->arch.triple_fault_event = cap->args[0];
6173 case KVM_CAP_X86_USER_SPACE_MSR:
6174 kvm->arch.user_space_msr_mask = cap->args[0];
6177 case KVM_CAP_X86_BUS_LOCK_EXIT:
6179 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE)
6182 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) &&
6183 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
6186 if (kvm_caps.has_bus_lock_exit &&
6187 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
6188 kvm->arch.bus_lock_detection_enabled = true;
6191 #ifdef CONFIG_X86_SGX_KVM
6192 case KVM_CAP_SGX_ATTRIBUTE: {
6193 unsigned long allowed_attributes = 0;
6195 r = sgx_set_attribute(&allowed_attributes, cap->args[0]);
6199 /* KVM only supports the PROVISIONKEY privileged attribute. */
6200 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) &&
6201 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY))
6202 kvm->arch.sgx_provisioning_allowed = true;
6208 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
6210 if (!kvm_x86_ops.vm_copy_enc_context_from)
6213 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]);
6215 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
6217 if (!kvm_x86_ops.vm_move_enc_context_from)
6220 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]);
6222 case KVM_CAP_EXIT_HYPERCALL:
6223 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) {
6227 kvm->arch.hypercall_exit_enabled = cap->args[0];
6230 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
6232 if (cap->args[0] & ~1)
6234 kvm->arch.exit_on_emulation_error = cap->args[0];
6237 case KVM_CAP_PMU_CAPABILITY:
6239 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK))
6242 mutex_lock(&kvm->lock);
6243 if (!kvm->created_vcpus) {
6244 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE);
6247 mutex_unlock(&kvm->lock);
6249 case KVM_CAP_MAX_VCPU_ID:
6251 if (cap->args[0] > KVM_MAX_VCPU_IDS)
6254 mutex_lock(&kvm->lock);
6255 if (kvm->arch.max_vcpu_ids == cap->args[0]) {
6257 } else if (!kvm->arch.max_vcpu_ids) {
6258 kvm->arch.max_vcpu_ids = cap->args[0];
6261 mutex_unlock(&kvm->lock);
6263 case KVM_CAP_X86_NOTIFY_VMEXIT:
6265 if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS)
6267 if (!kvm_caps.has_notify_vmexit)
6269 if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED))
6271 mutex_lock(&kvm->lock);
6272 if (!kvm->created_vcpus) {
6273 kvm->arch.notify_window = cap->args[0] >> 32;
6274 kvm->arch.notify_vmexit_flags = (u32)cap->args[0];
6277 mutex_unlock(&kvm->lock);
6279 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
6283 * Since the risk of disabling NX hugepages is a guest crashing
6284 * the system, ensure the userspace process has permission to
6285 * reboot the system.
6287 * Note that unlike the reboot() syscall, the process must have
6288 * this capability in the root namespace because exposing
6289 * /dev/kvm into a container does not limit the scope of the
6290 * iTLB multihit bug to that container. In other words,
6291 * this must use capable(), not ns_capable().
6293 if (!capable(CAP_SYS_BOOT)) {
6301 mutex_lock(&kvm->lock);
6302 if (!kvm->created_vcpus) {
6303 kvm->arch.disable_nx_huge_pages = true;
6306 mutex_unlock(&kvm->lock);
6315 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow)
6317 struct kvm_x86_msr_filter *msr_filter;
6319 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT);
6323 msr_filter->default_allow = default_allow;
6327 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter)
6334 for (i = 0; i < msr_filter->count; i++)
6335 kfree(msr_filter->ranges[i].bitmap);
6340 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter,
6341 struct kvm_msr_filter_range *user_range)
6343 unsigned long *bitmap = NULL;
6346 if (!user_range->nmsrs)
6349 if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE))
6352 if (!user_range->flags)
6355 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
6356 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
6359 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
6361 return PTR_ERR(bitmap);
6363 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) {
6364 .flags = user_range->flags,
6365 .base = user_range->base,
6366 .nmsrs = user_range->nmsrs,
6370 msr_filter->count++;
6374 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp)
6376 struct kvm_msr_filter __user *user_msr_filter = argp;
6377 struct kvm_x86_msr_filter *new_filter, *old_filter;
6378 struct kvm_msr_filter filter;
6384 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
6387 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++)
6388 empty &= !filter.ranges[i].nmsrs;
6390 default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY);
6391 if (empty && !default_allow)
6394 new_filter = kvm_alloc_msr_filter(default_allow);
6398 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
6399 r = kvm_add_msr_filter(new_filter, &filter.ranges[i]);
6401 kvm_free_msr_filter(new_filter);
6406 mutex_lock(&kvm->lock);
6408 /* The per-VM filter is protected by kvm->lock... */
6409 old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1);
6411 rcu_assign_pointer(kvm->arch.msr_filter, new_filter);
6412 synchronize_srcu(&kvm->srcu);
6414 kvm_free_msr_filter(old_filter);
6416 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
6417 mutex_unlock(&kvm->lock);
6422 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER
6423 static int kvm_arch_suspend_notifier(struct kvm *kvm)
6425 struct kvm_vcpu *vcpu;
6429 mutex_lock(&kvm->lock);
6430 kvm_for_each_vcpu(i, vcpu, kvm) {
6431 if (!vcpu->arch.pv_time.active)
6434 ret = kvm_set_guest_paused(vcpu);
6436 kvm_err("Failed to pause guest VCPU%d: %d\n",
6437 vcpu->vcpu_id, ret);
6441 mutex_unlock(&kvm->lock);
6443 return ret ? NOTIFY_BAD : NOTIFY_DONE;
6446 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state)
6449 case PM_HIBERNATION_PREPARE:
6450 case PM_SUSPEND_PREPARE:
6451 return kvm_arch_suspend_notifier(kvm);
6456 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */
6458 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp)
6460 struct kvm_clock_data data = { 0 };
6462 get_kvmclock(kvm, &data);
6463 if (copy_to_user(argp, &data, sizeof(data)))
6469 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp)
6471 struct kvm_arch *ka = &kvm->arch;
6472 struct kvm_clock_data data;
6475 if (copy_from_user(&data, argp, sizeof(data)))
6479 * Only KVM_CLOCK_REALTIME is used, but allow passing the
6480 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK.
6482 if (data.flags & ~KVM_CLOCK_VALID_FLAGS)
6485 kvm_hv_request_tsc_page_update(kvm);
6486 kvm_start_pvclock_update(kvm);
6487 pvclock_update_vm_gtod_copy(kvm);
6490 * This pairs with kvm_guest_time_update(): when masterclock is
6491 * in use, we use master_kernel_ns + kvmclock_offset to set
6492 * unsigned 'system_time' so if we use get_kvmclock_ns() (which
6493 * is slightly ahead) here we risk going negative on unsigned
6494 * 'system_time' when 'data.clock' is very small.
6496 if (data.flags & KVM_CLOCK_REALTIME) {
6497 u64 now_real_ns = ktime_get_real_ns();
6500 * Avoid stepping the kvmclock backwards.
6502 if (now_real_ns > data.realtime)
6503 data.clock += now_real_ns - data.realtime;
6506 if (ka->use_master_clock)
6507 now_raw_ns = ka->master_kernel_ns;
6509 now_raw_ns = get_kvmclock_base_ns();
6510 ka->kvmclock_offset = data.clock - now_raw_ns;
6511 kvm_end_pvclock_update(kvm);
6515 long kvm_arch_vm_ioctl(struct file *filp,
6516 unsigned int ioctl, unsigned long arg)
6518 struct kvm *kvm = filp->private_data;
6519 void __user *argp = (void __user *)arg;
6522 * This union makes it completely explicit to gcc-3.x
6523 * that these two variables' stack usage should be
6524 * combined, not added together.
6527 struct kvm_pit_state ps;
6528 struct kvm_pit_state2 ps2;
6529 struct kvm_pit_config pit_config;
6533 case KVM_SET_TSS_ADDR:
6534 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
6536 case KVM_SET_IDENTITY_MAP_ADDR: {
6539 mutex_lock(&kvm->lock);
6541 if (kvm->created_vcpus)
6542 goto set_identity_unlock;
6544 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
6545 goto set_identity_unlock;
6546 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
6547 set_identity_unlock:
6548 mutex_unlock(&kvm->lock);
6551 case KVM_SET_NR_MMU_PAGES:
6552 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
6554 case KVM_GET_NR_MMU_PAGES:
6555 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
6557 case KVM_CREATE_IRQCHIP: {
6558 mutex_lock(&kvm->lock);
6561 if (irqchip_in_kernel(kvm))
6562 goto create_irqchip_unlock;
6565 if (kvm->created_vcpus)
6566 goto create_irqchip_unlock;
6568 r = kvm_pic_init(kvm);
6570 goto create_irqchip_unlock;
6572 r = kvm_ioapic_init(kvm);
6574 kvm_pic_destroy(kvm);
6575 goto create_irqchip_unlock;
6578 r = kvm_setup_default_irq_routing(kvm);
6580 kvm_ioapic_destroy(kvm);
6581 kvm_pic_destroy(kvm);
6582 goto create_irqchip_unlock;
6584 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
6586 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
6587 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6588 create_irqchip_unlock:
6589 mutex_unlock(&kvm->lock);
6592 case KVM_CREATE_PIT:
6593 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
6595 case KVM_CREATE_PIT2:
6597 if (copy_from_user(&u.pit_config, argp,
6598 sizeof(struct kvm_pit_config)))
6601 mutex_lock(&kvm->lock);
6604 goto create_pit_unlock;
6606 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
6610 mutex_unlock(&kvm->lock);
6612 case KVM_GET_IRQCHIP: {
6613 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6614 struct kvm_irqchip *chip;
6616 chip = memdup_user(argp, sizeof(*chip));
6623 if (!irqchip_kernel(kvm))
6624 goto get_irqchip_out;
6625 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
6627 goto get_irqchip_out;
6629 if (copy_to_user(argp, chip, sizeof(*chip)))
6630 goto get_irqchip_out;
6636 case KVM_SET_IRQCHIP: {
6637 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6638 struct kvm_irqchip *chip;
6640 chip = memdup_user(argp, sizeof(*chip));
6647 if (!irqchip_kernel(kvm))
6648 goto set_irqchip_out;
6649 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
6656 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
6659 if (!kvm->arch.vpit)
6661 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
6665 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
6672 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
6674 mutex_lock(&kvm->lock);
6676 if (!kvm->arch.vpit)
6678 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
6680 mutex_unlock(&kvm->lock);
6683 case KVM_GET_PIT2: {
6685 if (!kvm->arch.vpit)
6687 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
6691 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
6696 case KVM_SET_PIT2: {
6698 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
6700 mutex_lock(&kvm->lock);
6702 if (!kvm->arch.vpit)
6704 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
6706 mutex_unlock(&kvm->lock);
6709 case KVM_REINJECT_CONTROL: {
6710 struct kvm_reinject_control control;
6712 if (copy_from_user(&control, argp, sizeof(control)))
6715 if (!kvm->arch.vpit)
6717 r = kvm_vm_ioctl_reinject(kvm, &control);
6720 case KVM_SET_BOOT_CPU_ID:
6722 mutex_lock(&kvm->lock);
6723 if (kvm->created_vcpus)
6726 kvm->arch.bsp_vcpu_id = arg;
6727 mutex_unlock(&kvm->lock);
6729 #ifdef CONFIG_KVM_XEN
6730 case KVM_XEN_HVM_CONFIG: {
6731 struct kvm_xen_hvm_config xhc;
6733 if (copy_from_user(&xhc, argp, sizeof(xhc)))
6735 r = kvm_xen_hvm_config(kvm, &xhc);
6738 case KVM_XEN_HVM_GET_ATTR: {
6739 struct kvm_xen_hvm_attr xha;
6742 if (copy_from_user(&xha, argp, sizeof(xha)))
6744 r = kvm_xen_hvm_get_attr(kvm, &xha);
6745 if (!r && copy_to_user(argp, &xha, sizeof(xha)))
6749 case KVM_XEN_HVM_SET_ATTR: {
6750 struct kvm_xen_hvm_attr xha;
6753 if (copy_from_user(&xha, argp, sizeof(xha)))
6755 r = kvm_xen_hvm_set_attr(kvm, &xha);
6758 case KVM_XEN_HVM_EVTCHN_SEND: {
6759 struct kvm_irq_routing_xen_evtchn uxe;
6762 if (copy_from_user(&uxe, argp, sizeof(uxe)))
6764 r = kvm_xen_hvm_evtchn_send(kvm, &uxe);
6769 r = kvm_vm_ioctl_set_clock(kvm, argp);
6772 r = kvm_vm_ioctl_get_clock(kvm, argp);
6774 case KVM_SET_TSC_KHZ: {
6778 user_tsc_khz = (u32)arg;
6780 if (kvm_caps.has_tsc_control &&
6781 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
6784 if (user_tsc_khz == 0)
6785 user_tsc_khz = tsc_khz;
6787 WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz);
6792 case KVM_GET_TSC_KHZ: {
6793 r = READ_ONCE(kvm->arch.default_tsc_khz);
6796 case KVM_MEMORY_ENCRYPT_OP: {
6798 if (!kvm_x86_ops.mem_enc_ioctl)
6801 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp);
6804 case KVM_MEMORY_ENCRYPT_REG_REGION: {
6805 struct kvm_enc_region region;
6808 if (copy_from_user(®ion, argp, sizeof(region)))
6812 if (!kvm_x86_ops.mem_enc_register_region)
6815 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion);
6818 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
6819 struct kvm_enc_region region;
6822 if (copy_from_user(®ion, argp, sizeof(region)))
6826 if (!kvm_x86_ops.mem_enc_unregister_region)
6829 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion);
6832 case KVM_HYPERV_EVENTFD: {
6833 struct kvm_hyperv_eventfd hvevfd;
6836 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
6838 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
6841 case KVM_SET_PMU_EVENT_FILTER:
6842 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
6844 case KVM_X86_SET_MSR_FILTER:
6845 r = kvm_vm_ioctl_set_msr_filter(kvm, argp);
6854 static void kvm_init_msr_list(void)
6859 BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
6860 "Please update the fixed PMCs in msrs_to_saved_all[]");
6862 num_msrs_to_save = 0;
6863 num_emulated_msrs = 0;
6864 num_msr_based_features = 0;
6866 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
6867 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
6871 * Even MSRs that are valid in the host may not be exposed
6872 * to the guests in some cases.
6874 switch (msrs_to_save_all[i]) {
6875 case MSR_IA32_BNDCFGS:
6876 if (!kvm_mpx_supported())
6880 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) &&
6881 !kvm_cpu_cap_has(X86_FEATURE_RDPID))
6884 case MSR_IA32_UMWAIT_CONTROL:
6885 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
6888 case MSR_IA32_RTIT_CTL:
6889 case MSR_IA32_RTIT_STATUS:
6890 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
6893 case MSR_IA32_RTIT_CR3_MATCH:
6894 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
6895 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
6898 case MSR_IA32_RTIT_OUTPUT_BASE:
6899 case MSR_IA32_RTIT_OUTPUT_MASK:
6900 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
6901 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
6902 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
6905 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
6906 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
6907 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
6908 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
6911 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
6912 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
6913 min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp))
6916 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
6917 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
6918 min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp))
6922 case MSR_IA32_XFD_ERR:
6923 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
6930 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
6933 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
6934 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i]))
6937 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
6940 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
6941 struct kvm_msr_entry msr;
6943 msr.index = msr_based_features_all[i];
6944 if (kvm_get_msr_feature(&msr))
6947 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
6951 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
6959 if (!(lapic_in_kernel(vcpu) &&
6960 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
6961 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
6972 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
6979 if (!(lapic_in_kernel(vcpu) &&
6980 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
6982 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
6984 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
6994 static void kvm_set_segment(struct kvm_vcpu *vcpu,
6995 struct kvm_segment *var, int seg)
6997 static_call(kvm_x86_set_segment)(vcpu, var, seg);
7000 void kvm_get_segment(struct kvm_vcpu *vcpu,
7001 struct kvm_segment *var, int seg)
7003 static_call(kvm_x86_get_segment)(vcpu, var, seg);
7006 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
7007 struct x86_exception *exception)
7009 struct kvm_mmu *mmu = vcpu->arch.mmu;
7012 BUG_ON(!mmu_is_nested(vcpu));
7014 /* NPT walks are always user-walks */
7015 access |= PFERR_USER_MASK;
7016 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception);
7021 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
7022 struct x86_exception *exception)
7024 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7026 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7027 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7029 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read);
7031 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
7032 struct x86_exception *exception)
7034 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7036 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7037 access |= PFERR_FETCH_MASK;
7038 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7041 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
7042 struct x86_exception *exception)
7044 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7046 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7047 access |= PFERR_WRITE_MASK;
7048 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7050 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write);
7052 /* uses this to access any guest's mapped memory without checking CPL */
7053 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
7054 struct x86_exception *exception)
7056 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7058 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception);
7061 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7062 struct kvm_vcpu *vcpu, u64 access,
7063 struct x86_exception *exception)
7065 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7067 int r = X86EMUL_CONTINUE;
7070 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7071 unsigned offset = addr & (PAGE_SIZE-1);
7072 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
7075 if (gpa == UNMAPPED_GVA)
7076 return X86EMUL_PROPAGATE_FAULT;
7077 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
7080 r = X86EMUL_IO_NEEDED;
7092 /* used for instruction fetching */
7093 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
7094 gva_t addr, void *val, unsigned int bytes,
7095 struct x86_exception *exception)
7097 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7098 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7099 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7103 /* Inline kvm_read_guest_virt_helper for speed. */
7104 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK,
7106 if (unlikely(gpa == UNMAPPED_GVA))
7107 return X86EMUL_PROPAGATE_FAULT;
7109 offset = addr & (PAGE_SIZE-1);
7110 if (WARN_ON(offset + bytes > PAGE_SIZE))
7111 bytes = (unsigned)PAGE_SIZE - offset;
7112 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
7114 if (unlikely(ret < 0))
7115 return X86EMUL_IO_NEEDED;
7117 return X86EMUL_CONTINUE;
7120 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
7121 gva_t addr, void *val, unsigned int bytes,
7122 struct x86_exception *exception)
7124 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7127 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
7128 * is returned, but our callers are not ready for that and they blindly
7129 * call kvm_inject_page_fault. Ensure that they at least do not leak
7130 * uninitialized kernel stack memory into cr2 and error code.
7132 memset(exception, 0, sizeof(*exception));
7133 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
7136 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
7138 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
7139 gva_t addr, void *val, unsigned int bytes,
7140 struct x86_exception *exception, bool system)
7142 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7146 access |= PFERR_IMPLICIT_ACCESS;
7147 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7148 access |= PFERR_USER_MASK;
7150 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
7153 static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
7154 unsigned long addr, void *val, unsigned int bytes)
7156 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7157 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
7159 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
7162 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7163 struct kvm_vcpu *vcpu, u64 access,
7164 struct x86_exception *exception)
7166 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7168 int r = X86EMUL_CONTINUE;
7171 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7172 unsigned offset = addr & (PAGE_SIZE-1);
7173 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
7176 if (gpa == UNMAPPED_GVA)
7177 return X86EMUL_PROPAGATE_FAULT;
7178 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
7180 r = X86EMUL_IO_NEEDED;
7192 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
7193 unsigned int bytes, struct x86_exception *exception,
7196 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7197 u64 access = PFERR_WRITE_MASK;
7200 access |= PFERR_IMPLICIT_ACCESS;
7201 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7202 access |= PFERR_USER_MASK;
7204 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7208 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
7209 unsigned int bytes, struct x86_exception *exception)
7211 /* kvm_write_guest_virt_system can pull in tons of pages. */
7212 vcpu->arch.l1tf_flush_l1d = true;
7214 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7215 PFERR_WRITE_MASK, exception);
7217 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
7219 static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type,
7220 void *insn, int insn_len)
7222 return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type,
7226 int handle_ud(struct kvm_vcpu *vcpu)
7228 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
7229 int emul_type = EMULTYPE_TRAP_UD;
7230 char sig[5]; /* ud2; .ascii "kvm" */
7231 struct x86_exception e;
7233 if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0)))
7236 if (force_emulation_prefix &&
7237 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
7238 sig, sizeof(sig), &e) == 0 &&
7239 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
7240 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
7241 emul_type = EMULTYPE_TRAP_UD_FORCED;
7244 return kvm_emulate_instruction(vcpu, emul_type);
7246 EXPORT_SYMBOL_GPL(handle_ud);
7248 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7249 gpa_t gpa, bool write)
7251 /* For APIC access vmexit */
7252 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7255 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
7256 trace_vcpu_match_mmio(gva, gpa, write, true);
7263 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7264 gpa_t *gpa, struct x86_exception *exception,
7267 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7268 u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0)
7269 | (write ? PFERR_WRITE_MASK : 0);
7272 * currently PKRU is only applied to ept enabled guest so
7273 * there is no pkey in EPT page table for L1 guest or EPT
7274 * shadow page table for L2 guest.
7276 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) ||
7277 !permission_fault(vcpu, vcpu->arch.walk_mmu,
7278 vcpu->arch.mmio_access, 0, access))) {
7279 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
7280 (gva & (PAGE_SIZE - 1));
7281 trace_vcpu_match_mmio(gva, *gpa, write, false);
7285 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7287 if (*gpa == UNMAPPED_GVA)
7290 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
7293 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
7294 const void *val, int bytes)
7298 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
7301 kvm_page_track_write(vcpu, gpa, val, bytes);
7305 struct read_write_emulator_ops {
7306 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
7308 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
7309 void *val, int bytes);
7310 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7311 int bytes, void *val);
7312 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7313 void *val, int bytes);
7317 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
7319 if (vcpu->mmio_read_completed) {
7320 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
7321 vcpu->mmio_fragments[0].gpa, val);
7322 vcpu->mmio_read_completed = 0;
7329 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7330 void *val, int bytes)
7332 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
7335 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7336 void *val, int bytes)
7338 return emulator_write_phys(vcpu, gpa, val, bytes);
7341 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
7343 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
7344 return vcpu_mmio_write(vcpu, gpa, bytes, val);
7347 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7348 void *val, int bytes)
7350 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
7351 return X86EMUL_IO_NEEDED;
7354 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7355 void *val, int bytes)
7357 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
7359 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
7360 return X86EMUL_CONTINUE;
7363 static const struct read_write_emulator_ops read_emultor = {
7364 .read_write_prepare = read_prepare,
7365 .read_write_emulate = read_emulate,
7366 .read_write_mmio = vcpu_mmio_read,
7367 .read_write_exit_mmio = read_exit_mmio,
7370 static const struct read_write_emulator_ops write_emultor = {
7371 .read_write_emulate = write_emulate,
7372 .read_write_mmio = write_mmio,
7373 .read_write_exit_mmio = write_exit_mmio,
7377 static int emulator_read_write_onepage(unsigned long addr, void *val,
7379 struct x86_exception *exception,
7380 struct kvm_vcpu *vcpu,
7381 const struct read_write_emulator_ops *ops)
7385 bool write = ops->write;
7386 struct kvm_mmio_fragment *frag;
7387 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7390 * If the exit was due to a NPF we may already have a GPA.
7391 * If the GPA is present, use it to avoid the GVA to GPA table walk.
7392 * Note, this cannot be used on string operations since string
7393 * operation using rep will only have the initial GPA from the NPF
7396 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
7397 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
7398 gpa = ctxt->gpa_val;
7399 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
7401 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
7403 return X86EMUL_PROPAGATE_FAULT;
7406 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
7407 return X86EMUL_CONTINUE;
7410 * Is this MMIO handled locally?
7412 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
7413 if (handled == bytes)
7414 return X86EMUL_CONTINUE;
7420 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
7421 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
7425 return X86EMUL_CONTINUE;
7428 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
7430 void *val, unsigned int bytes,
7431 struct x86_exception *exception,
7432 const struct read_write_emulator_ops *ops)
7434 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7438 if (ops->read_write_prepare &&
7439 ops->read_write_prepare(vcpu, val, bytes))
7440 return X86EMUL_CONTINUE;
7442 vcpu->mmio_nr_fragments = 0;
7444 /* Crossing a page boundary? */
7445 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
7448 now = -addr & ~PAGE_MASK;
7449 rc = emulator_read_write_onepage(addr, val, now, exception,
7452 if (rc != X86EMUL_CONTINUE)
7455 if (ctxt->mode != X86EMUL_MODE_PROT64)
7461 rc = emulator_read_write_onepage(addr, val, bytes, exception,
7463 if (rc != X86EMUL_CONTINUE)
7466 if (!vcpu->mmio_nr_fragments)
7469 gpa = vcpu->mmio_fragments[0].gpa;
7471 vcpu->mmio_needed = 1;
7472 vcpu->mmio_cur_fragment = 0;
7474 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
7475 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
7476 vcpu->run->exit_reason = KVM_EXIT_MMIO;
7477 vcpu->run->mmio.phys_addr = gpa;
7479 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
7482 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
7486 struct x86_exception *exception)
7488 return emulator_read_write(ctxt, addr, val, bytes,
7489 exception, &read_emultor);
7492 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
7496 struct x86_exception *exception)
7498 return emulator_read_write(ctxt, addr, (void *)val, bytes,
7499 exception, &write_emultor);
7502 #define emulator_try_cmpxchg_user(t, ptr, old, new) \
7503 (__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t))
7505 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
7510 struct x86_exception *exception)
7512 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7518 /* guests cmpxchg8b have to be emulated atomically */
7519 if (bytes > 8 || (bytes & (bytes - 1)))
7522 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
7524 if (gpa == UNMAPPED_GVA ||
7525 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7529 * Emulate the atomic as a straight write to avoid #AC if SLD is
7530 * enabled in the host and the access splits a cache line.
7532 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
7533 page_line_mask = ~(cache_line_size() - 1);
7535 page_line_mask = PAGE_MASK;
7537 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
7540 hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa));
7541 if (kvm_is_error_hva(hva))
7544 hva += offset_in_page(gpa);
7548 r = emulator_try_cmpxchg_user(u8, hva, old, new);
7551 r = emulator_try_cmpxchg_user(u16, hva, old, new);
7554 r = emulator_try_cmpxchg_user(u32, hva, old, new);
7557 r = emulator_try_cmpxchg_user(u64, hva, old, new);
7564 return X86EMUL_UNHANDLEABLE;
7566 return X86EMUL_CMPXCHG_FAILED;
7568 kvm_page_track_write(vcpu, gpa, new, bytes);
7570 return X86EMUL_CONTINUE;
7573 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
7575 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
7578 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
7579 unsigned short port, void *data,
7580 unsigned int count, bool in)
7585 WARN_ON_ONCE(vcpu->arch.pio.count);
7586 for (i = 0; i < count; i++) {
7588 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data);
7590 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data);
7597 * Userspace must have unregistered the device while PIO
7598 * was running. Drop writes / read as 0.
7601 memset(data, 0, size * (count - i));
7610 vcpu->arch.pio.port = port;
7611 vcpu->arch.pio.in = in;
7612 vcpu->arch.pio.count = count;
7613 vcpu->arch.pio.size = size;
7616 memset(vcpu->arch.pio_data, 0, size * count);
7618 memcpy(vcpu->arch.pio_data, data, size * count);
7620 vcpu->run->exit_reason = KVM_EXIT_IO;
7621 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
7622 vcpu->run->io.size = size;
7623 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
7624 vcpu->run->io.count = count;
7625 vcpu->run->io.port = port;
7629 static int __emulator_pio_in(struct kvm_vcpu *vcpu, int size,
7630 unsigned short port, void *val, unsigned int count)
7632 int r = emulator_pio_in_out(vcpu, size, port, val, count, true);
7634 trace_kvm_pio(KVM_PIO_IN, port, size, count, val);
7639 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val)
7641 int size = vcpu->arch.pio.size;
7642 unsigned int count = vcpu->arch.pio.count;
7643 memcpy(val, vcpu->arch.pio_data, size * count);
7644 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data);
7645 vcpu->arch.pio.count = 0;
7648 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
7649 unsigned short port, void *val, unsigned int count)
7651 if (vcpu->arch.pio.count) {
7653 * Complete a previous iteration that required userspace I/O.
7654 * Note, @count isn't guaranteed to match pio.count as userspace
7655 * can modify ECX before rerunning the vCPU. Ignore any such
7656 * shenanigans as KVM doesn't support modifying the rep count,
7657 * and the emulator ensures @count doesn't overflow the buffer.
7659 complete_emulator_pio_in(vcpu, val);
7663 return __emulator_pio_in(vcpu, size, port, val, count);
7666 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
7667 int size, unsigned short port, void *val,
7670 return emulator_pio_in(emul_to_vcpu(ctxt), size, port, val, count);
7674 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
7675 unsigned short port, const void *val,
7678 trace_kvm_pio(KVM_PIO_OUT, port, size, count, val);
7679 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
7682 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
7683 int size, unsigned short port,
7684 const void *val, unsigned int count)
7686 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
7689 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
7691 return static_call(kvm_x86_get_segment_base)(vcpu, seg);
7694 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
7696 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
7699 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
7701 if (!need_emulate_wbinvd(vcpu))
7702 return X86EMUL_CONTINUE;
7704 if (static_call(kvm_x86_has_wbinvd_exit)()) {
7705 int cpu = get_cpu();
7707 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
7708 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask,
7709 wbinvd_ipi, NULL, 1);
7711 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
7714 return X86EMUL_CONTINUE;
7717 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
7719 kvm_emulate_wbinvd_noskip(vcpu);
7720 return kvm_skip_emulated_instruction(vcpu);
7722 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
7726 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
7728 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
7731 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
7732 unsigned long *dest)
7734 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
7737 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
7738 unsigned long value)
7741 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
7744 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
7746 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
7749 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
7751 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7752 unsigned long value;
7756 value = kvm_read_cr0(vcpu);
7759 value = vcpu->arch.cr2;
7762 value = kvm_read_cr3(vcpu);
7765 value = kvm_read_cr4(vcpu);
7768 value = kvm_get_cr8(vcpu);
7771 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7778 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
7780 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7785 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
7788 vcpu->arch.cr2 = val;
7791 res = kvm_set_cr3(vcpu, val);
7794 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
7797 res = kvm_set_cr8(vcpu, val);
7800 kvm_err("%s: unexpected cr %u\n", __func__, cr);
7807 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
7809 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt));
7812 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7814 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt);
7817 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7819 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt);
7822 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7824 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt);
7827 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
7829 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt);
7832 static unsigned long emulator_get_cached_segment_base(
7833 struct x86_emulate_ctxt *ctxt, int seg)
7835 return get_segment_base(emul_to_vcpu(ctxt), seg);
7838 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
7839 struct desc_struct *desc, u32 *base3,
7842 struct kvm_segment var;
7844 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
7845 *selector = var.selector;
7848 memset(desc, 0, sizeof(*desc));
7856 set_desc_limit(desc, var.limit);
7857 set_desc_base(desc, (unsigned long)var.base);
7858 #ifdef CONFIG_X86_64
7860 *base3 = var.base >> 32;
7862 desc->type = var.type;
7864 desc->dpl = var.dpl;
7865 desc->p = var.present;
7866 desc->avl = var.avl;
7874 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
7875 struct desc_struct *desc, u32 base3,
7878 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7879 struct kvm_segment var;
7881 var.selector = selector;
7882 var.base = get_desc_base(desc);
7883 #ifdef CONFIG_X86_64
7884 var.base |= ((u64)base3) << 32;
7886 var.limit = get_desc_limit(desc);
7888 var.limit = (var.limit << 12) | 0xfff;
7889 var.type = desc->type;
7890 var.dpl = desc->dpl;
7895 var.avl = desc->avl;
7896 var.present = desc->p;
7897 var.unusable = !var.present;
7900 kvm_set_segment(vcpu, &var, seg);
7904 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt,
7905 u32 msr_index, u64 *pdata)
7907 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7910 r = kvm_get_msr_with_filter(vcpu, msr_index, pdata);
7912 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0,
7913 complete_emulated_rdmsr, r)) {
7914 /* Bounce to user space */
7915 return X86EMUL_IO_NEEDED;
7921 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt,
7922 u32 msr_index, u64 data)
7924 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7927 r = kvm_set_msr_with_filter(vcpu, msr_index, data);
7929 if (r && kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data,
7930 complete_emulated_msr_access, r)) {
7931 /* Bounce to user space */
7932 return X86EMUL_IO_NEEDED;
7938 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
7939 u32 msr_index, u64 *pdata)
7941 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
7944 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
7945 u32 msr_index, u64 data)
7947 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
7950 static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
7952 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7954 return vcpu->arch.smbase;
7957 static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
7959 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7961 vcpu->arch.smbase = smbase;
7964 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
7967 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc))
7972 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
7973 u32 pmc, u64 *pdata)
7975 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
7978 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
7980 emul_to_vcpu(ctxt)->arch.halt_request = 1;
7983 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
7984 struct x86_instruction_info *info,
7985 enum x86_intercept_stage stage)
7987 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage,
7991 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
7992 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
7995 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
7998 static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
8000 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
8003 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
8005 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
8008 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
8010 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
8013 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt)
8015 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID);
8018 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
8020 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg);
8023 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
8025 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val);
8028 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
8030 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked);
8033 static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
8035 return emul_to_vcpu(ctxt)->arch.hflags;
8038 static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt)
8040 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8042 kvm_smm_changed(vcpu, false);
8045 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt,
8046 const char *smstate)
8048 return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate);
8051 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt)
8053 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt));
8056 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
8058 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
8061 static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt)
8063 struct kvm *kvm = emul_to_vcpu(ctxt)->kvm;
8065 if (!kvm->vm_bugged)
8069 static const struct x86_emulate_ops emulate_ops = {
8070 .vm_bugged = emulator_vm_bugged,
8071 .read_gpr = emulator_read_gpr,
8072 .write_gpr = emulator_write_gpr,
8073 .read_std = emulator_read_std,
8074 .write_std = emulator_write_std,
8075 .read_phys = kvm_read_guest_phys_system,
8076 .fetch = kvm_fetch_guest_virt,
8077 .read_emulated = emulator_read_emulated,
8078 .write_emulated = emulator_write_emulated,
8079 .cmpxchg_emulated = emulator_cmpxchg_emulated,
8080 .invlpg = emulator_invlpg,
8081 .pio_in_emulated = emulator_pio_in_emulated,
8082 .pio_out_emulated = emulator_pio_out_emulated,
8083 .get_segment = emulator_get_segment,
8084 .set_segment = emulator_set_segment,
8085 .get_cached_segment_base = emulator_get_cached_segment_base,
8086 .get_gdt = emulator_get_gdt,
8087 .get_idt = emulator_get_idt,
8088 .set_gdt = emulator_set_gdt,
8089 .set_idt = emulator_set_idt,
8090 .get_cr = emulator_get_cr,
8091 .set_cr = emulator_set_cr,
8092 .cpl = emulator_get_cpl,
8093 .get_dr = emulator_get_dr,
8094 .set_dr = emulator_set_dr,
8095 .get_smbase = emulator_get_smbase,
8096 .set_smbase = emulator_set_smbase,
8097 .set_msr_with_filter = emulator_set_msr_with_filter,
8098 .get_msr_with_filter = emulator_get_msr_with_filter,
8099 .set_msr = emulator_set_msr,
8100 .get_msr = emulator_get_msr,
8101 .check_pmc = emulator_check_pmc,
8102 .read_pmc = emulator_read_pmc,
8103 .halt = emulator_halt,
8104 .wbinvd = emulator_wbinvd,
8105 .fix_hypercall = emulator_fix_hypercall,
8106 .intercept = emulator_intercept,
8107 .get_cpuid = emulator_get_cpuid,
8108 .guest_has_long_mode = emulator_guest_has_long_mode,
8109 .guest_has_movbe = emulator_guest_has_movbe,
8110 .guest_has_fxsr = emulator_guest_has_fxsr,
8111 .guest_has_rdpid = emulator_guest_has_rdpid,
8112 .set_nmi_mask = emulator_set_nmi_mask,
8113 .get_hflags = emulator_get_hflags,
8114 .exiting_smm = emulator_exiting_smm,
8115 .leave_smm = emulator_leave_smm,
8116 .triple_fault = emulator_triple_fault,
8117 .set_xcr = emulator_set_xcr,
8120 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
8122 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8124 * an sti; sti; sequence only disable interrupts for the first
8125 * instruction. So, if the last instruction, be it emulated or
8126 * not, left the system with the INT_STI flag enabled, it
8127 * means that the last instruction is an sti. We should not
8128 * leave the flag on in this case. The same goes for mov ss
8130 if (int_shadow & mask)
8132 if (unlikely(int_shadow || mask)) {
8133 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask);
8135 kvm_make_request(KVM_REQ_EVENT, vcpu);
8139 static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
8141 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8142 if (ctxt->exception.vector == PF_VECTOR)
8143 return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
8145 if (ctxt->exception.error_code_valid)
8146 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
8147 ctxt->exception.error_code);
8149 kvm_queue_exception(vcpu, ctxt->exception.vector);
8153 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
8155 struct x86_emulate_ctxt *ctxt;
8157 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
8159 pr_err("kvm: failed to allocate vcpu's emulator\n");
8164 ctxt->ops = &emulate_ops;
8165 vcpu->arch.emulate_ctxt = ctxt;
8170 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
8172 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8175 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
8177 ctxt->gpa_available = false;
8178 ctxt->eflags = kvm_get_rflags(vcpu);
8179 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
8181 ctxt->eip = kvm_rip_read(vcpu);
8182 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
8183 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
8184 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
8185 cs_db ? X86EMUL_MODE_PROT32 :
8186 X86EMUL_MODE_PROT16;
8187 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
8188 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
8189 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
8191 ctxt->interruptibility = 0;
8192 ctxt->have_exception = false;
8193 ctxt->exception.vector = -1;
8194 ctxt->perm_ok = false;
8196 init_decode_cache(ctxt);
8197 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8200 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
8202 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8205 init_emulate_ctxt(vcpu);
8209 ctxt->_eip = ctxt->eip + inc_eip;
8210 ret = emulate_int_real(ctxt, irq);
8212 if (ret != X86EMUL_CONTINUE) {
8213 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8215 ctxt->eip = ctxt->_eip;
8216 kvm_rip_write(vcpu, ctxt->eip);
8217 kvm_set_rflags(vcpu, ctxt->eflags);
8220 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
8222 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8223 u8 ndata, u8 *insn_bytes, u8 insn_size)
8225 struct kvm_run *run = vcpu->run;
8230 * Zero the whole array used to retrieve the exit info, as casting to
8231 * u32 for select entries will leave some chunks uninitialized.
8233 memset(&info, 0, sizeof(info));
8235 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1],
8236 &info[2], (u32 *)&info[3],
8239 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8240 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION;
8243 * There's currently space for 13 entries, but 5 are used for the exit
8244 * reason and info. Restrict to 4 to reduce the maintenance burden
8245 * when expanding kvm_run.emulation_failure in the future.
8247 if (WARN_ON_ONCE(ndata > 4))
8250 /* Always include the flags as a 'data' entry. */
8252 run->emulation_failure.flags = 0;
8255 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) +
8256 sizeof(run->emulation_failure.insn_bytes) != 16));
8258 run->emulation_failure.flags |=
8259 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES;
8260 run->emulation_failure.insn_size = insn_size;
8261 memset(run->emulation_failure.insn_bytes, 0x90,
8262 sizeof(run->emulation_failure.insn_bytes));
8263 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size);
8266 memcpy(&run->internal.data[info_start], info, sizeof(info));
8267 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data,
8268 ndata * sizeof(data[0]));
8270 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata;
8273 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu)
8275 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8277 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data,
8278 ctxt->fetch.end - ctxt->fetch.data);
8281 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8284 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0);
8286 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit);
8288 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu)
8290 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0);
8292 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit);
8294 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
8296 struct kvm *kvm = vcpu->kvm;
8298 ++vcpu->stat.insn_emulation_fail;
8299 trace_kvm_emulate_insn_failed(vcpu);
8301 if (emulation_type & EMULTYPE_VMWARE_GP) {
8302 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8306 if (kvm->arch.exit_on_emulation_error ||
8307 (emulation_type & EMULTYPE_SKIP)) {
8308 prepare_emulation_ctxt_failure_exit(vcpu);
8312 kvm_queue_exception(vcpu, UD_VECTOR);
8314 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) {
8315 prepare_emulation_ctxt_failure_exit(vcpu);
8322 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8323 bool write_fault_to_shadow_pgtable,
8326 gpa_t gpa = cr2_or_gpa;
8329 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8332 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8333 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8336 if (!vcpu->arch.mmu->root_role.direct) {
8338 * Write permission should be allowed since only
8339 * write access need to be emulated.
8341 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8344 * If the mapping is invalid in guest, let cpu retry
8345 * it to generate fault.
8347 if (gpa == UNMAPPED_GVA)
8352 * Do not retry the unhandleable instruction if it faults on the
8353 * readonly host memory, otherwise it will goto a infinite loop:
8354 * retry instruction -> write #PF -> emulation fail -> retry
8355 * instruction -> ...
8357 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
8360 * If the instruction failed on the error pfn, it can not be fixed,
8361 * report the error to userspace.
8363 if (is_error_noslot_pfn(pfn))
8366 kvm_release_pfn_clean(pfn);
8368 /* The instructions are well-emulated on direct mmu. */
8369 if (vcpu->arch.mmu->root_role.direct) {
8370 unsigned int indirect_shadow_pages;
8372 write_lock(&vcpu->kvm->mmu_lock);
8373 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
8374 write_unlock(&vcpu->kvm->mmu_lock);
8376 if (indirect_shadow_pages)
8377 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8383 * if emulation was due to access to shadowed page table
8384 * and it failed try to unshadow page and re-enter the
8385 * guest to let CPU execute the instruction.
8387 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8390 * If the access faults on its page table, it can not
8391 * be fixed by unprotecting shadow page and it should
8392 * be reported to userspace.
8394 return !write_fault_to_shadow_pgtable;
8397 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
8398 gpa_t cr2_or_gpa, int emulation_type)
8400 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8401 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
8403 last_retry_eip = vcpu->arch.last_retry_eip;
8404 last_retry_addr = vcpu->arch.last_retry_addr;
8407 * If the emulation is caused by #PF and it is non-page_table
8408 * writing instruction, it means the VM-EXIT is caused by shadow
8409 * page protected, we can zap the shadow page and retry this
8410 * instruction directly.
8412 * Note: if the guest uses a non-page-table modifying instruction
8413 * on the PDE that points to the instruction, then we will unmap
8414 * the instruction and go to an infinite loop. So, we cache the
8415 * last retried eip and the last fault address, if we meet the eip
8416 * and the address again, we can break out of the potential infinite
8419 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
8421 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8424 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8425 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8428 if (x86_page_table_writing_insn(ctxt))
8431 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
8434 vcpu->arch.last_retry_eip = ctxt->eip;
8435 vcpu->arch.last_retry_addr = cr2_or_gpa;
8437 if (!vcpu->arch.mmu->root_role.direct)
8438 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8440 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8445 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
8446 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
8448 static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm)
8450 trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm);
8453 vcpu->arch.hflags |= HF_SMM_MASK;
8455 vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK);
8457 /* Process a latched INIT or SMI, if any. */
8458 kvm_make_request(KVM_REQ_EVENT, vcpu);
8461 * Even if KVM_SET_SREGS2 loaded PDPTRs out of band,
8462 * on SMM exit we still need to reload them from
8465 vcpu->arch.pdptrs_from_userspace = false;
8468 kvm_mmu_reset_context(vcpu);
8471 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
8480 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
8481 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
8486 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
8488 struct kvm_run *kvm_run = vcpu->run;
8490 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
8491 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW;
8492 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
8493 kvm_run->debug.arch.exception = DB_VECTOR;
8494 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8497 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
8501 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
8503 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8506 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu);
8510 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8513 * rflags is the old, "raw" value of the flags. The new value has
8514 * not been saved yet.
8516 * This is correct even for TF set by the guest, because "the
8517 * processor will not generate this exception after the instruction
8518 * that sets the TF flag".
8520 if (unlikely(rflags & X86_EFLAGS_TF))
8521 r = kvm_vcpu_do_singlestep(vcpu);
8524 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
8526 static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu, int *r)
8528 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
8529 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
8530 struct kvm_run *kvm_run = vcpu->run;
8531 unsigned long eip = kvm_get_linear_rip(vcpu);
8532 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8533 vcpu->arch.guest_debug_dr7,
8537 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
8538 kvm_run->debug.arch.pc = eip;
8539 kvm_run->debug.arch.exception = DB_VECTOR;
8540 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8546 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
8547 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
8548 unsigned long eip = kvm_get_linear_rip(vcpu);
8549 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8554 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
8563 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
8565 switch (ctxt->opcode_len) {
8572 case 0xe6: /* OUT */
8576 case 0x6c: /* INS */
8578 case 0x6e: /* OUTS */
8585 case 0x33: /* RDPMC */
8595 * Decode an instruction for emulation. The caller is responsible for handling
8596 * code breakpoints. Note, manually detecting code breakpoints is unnecessary
8597 * (and wrong) when emulating on an intercepted fault-like exception[*], as
8598 * code breakpoints have higher priority and thus have already been done by
8601 * [*] Except #MC, which is higher priority, but KVM should never emulate in
8602 * response to a machine check.
8604 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
8605 void *insn, int insn_len)
8607 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8610 init_emulate_ctxt(vcpu);
8612 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type);
8614 trace_kvm_emulate_insn_start(vcpu);
8615 ++vcpu->stat.insn_emulation;
8619 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction);
8621 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8622 int emulation_type, void *insn, int insn_len)
8625 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8626 bool writeback = true;
8627 bool write_fault_to_spt;
8629 if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len)))
8632 vcpu->arch.l1tf_flush_l1d = true;
8635 * Clear write_fault_to_shadow_pgtable here to ensure it is
8638 write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
8639 vcpu->arch.write_fault_to_shadow_pgtable = false;
8641 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8642 kvm_clear_exception_queue(vcpu);
8645 * Return immediately if RIP hits a code breakpoint, such #DBs
8646 * are fault-like and are higher priority than any faults on
8647 * the code fetch itself.
8649 if (!(emulation_type & EMULTYPE_SKIP) &&
8650 kvm_vcpu_check_code_breakpoint(vcpu, &r))
8653 r = x86_decode_emulated_instruction(vcpu, emulation_type,
8655 if (r != EMULATION_OK) {
8656 if ((emulation_type & EMULTYPE_TRAP_UD) ||
8657 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
8658 kvm_queue_exception(vcpu, UD_VECTOR);
8661 if (reexecute_instruction(vcpu, cr2_or_gpa,
8665 if (ctxt->have_exception) {
8667 * #UD should result in just EMULATION_FAILED, and trap-like
8668 * exception should not be encountered during decode.
8670 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
8671 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8672 inject_emulated_exception(vcpu);
8675 return handle_emulation_failure(vcpu, emulation_type);
8679 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
8680 !is_vmware_backdoor_opcode(ctxt)) {
8681 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8686 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for
8687 * use *only* by vendor callbacks for kvm_skip_emulated_instruction().
8688 * The caller is responsible for updating interruptibility state and
8689 * injecting single-step #DBs.
8691 if (emulation_type & EMULTYPE_SKIP) {
8692 if (ctxt->mode != X86EMUL_MODE_PROT64)
8693 ctxt->eip = (u32)ctxt->_eip;
8695 ctxt->eip = ctxt->_eip;
8697 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) {
8702 kvm_rip_write(vcpu, ctxt->eip);
8703 if (ctxt->eflags & X86_EFLAGS_RF)
8704 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
8708 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
8711 /* this is needed for vmware backdoor interface to work since it
8712 changes registers values during IO operation */
8713 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
8714 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8715 emulator_invalidate_register_cache(ctxt);
8719 if (emulation_type & EMULTYPE_PF) {
8720 /* Save the faulting GPA (cr2) in the address field */
8721 ctxt->exception.address = cr2_or_gpa;
8723 /* With shadow page tables, cr2 contains a GVA or nGPA. */
8724 if (vcpu->arch.mmu->root_role.direct) {
8725 ctxt->gpa_available = true;
8726 ctxt->gpa_val = cr2_or_gpa;
8729 /* Sanitize the address out of an abundance of paranoia. */
8730 ctxt->exception.address = 0;
8733 r = x86_emulate_insn(ctxt);
8735 if (r == EMULATION_INTERCEPTED)
8738 if (r == EMULATION_FAILED) {
8739 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
8743 return handle_emulation_failure(vcpu, emulation_type);
8746 if (ctxt->have_exception) {
8748 if (inject_emulated_exception(vcpu))
8750 } else if (vcpu->arch.pio.count) {
8751 if (!vcpu->arch.pio.in) {
8752 /* FIXME: return into emulator if single-stepping. */
8753 vcpu->arch.pio.count = 0;
8756 vcpu->arch.complete_userspace_io = complete_emulated_pio;
8759 } else if (vcpu->mmio_needed) {
8760 ++vcpu->stat.mmio_exits;
8762 if (!vcpu->mmio_is_write)
8765 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8766 } else if (vcpu->arch.complete_userspace_io) {
8769 } else if (r == EMULATION_RESTART)
8776 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8777 toggle_interruptibility(vcpu, ctxt->interruptibility);
8778 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8779 if (!ctxt->have_exception ||
8780 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
8781 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8782 if (ctxt->is_branch)
8783 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
8784 kvm_rip_write(vcpu, ctxt->eip);
8785 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
8786 r = kvm_vcpu_do_singlestep(vcpu);
8787 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu);
8788 __kvm_set_rflags(vcpu, ctxt->eflags);
8792 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
8793 * do nothing, and it will be requested again as soon as
8794 * the shadow expires. But we still need to check here,
8795 * because POPF has no interrupt shadow.
8797 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
8798 kvm_make_request(KVM_REQ_EVENT, vcpu);
8800 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
8805 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
8807 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
8809 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
8811 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
8812 void *insn, int insn_len)
8814 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
8816 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
8818 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
8820 vcpu->arch.pio.count = 0;
8824 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
8826 vcpu->arch.pio.count = 0;
8828 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
8831 return kvm_skip_emulated_instruction(vcpu);
8834 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
8835 unsigned short port)
8837 unsigned long val = kvm_rax_read(vcpu);
8838 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
8844 * Workaround userspace that relies on old KVM behavior of %rip being
8845 * incremented prior to exiting to userspace to handle "OUT 0x7e".
8848 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
8849 vcpu->arch.complete_userspace_io =
8850 complete_fast_pio_out_port_0x7e;
8851 kvm_skip_emulated_instruction(vcpu);
8853 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8854 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
8859 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
8863 /* We should only ever be called with arch.pio.count equal to 1 */
8864 BUG_ON(vcpu->arch.pio.count != 1);
8866 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
8867 vcpu->arch.pio.count = 0;
8871 /* For size less than 4 we merge, else we zero extend */
8872 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
8874 complete_emulator_pio_in(vcpu, &val);
8875 kvm_rax_write(vcpu, val);
8877 return kvm_skip_emulated_instruction(vcpu);
8880 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
8881 unsigned short port)
8886 /* For size less than 4 we merge, else we zero extend */
8887 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
8889 ret = __emulator_pio_in(vcpu, size, port, &val, 1);
8891 kvm_rax_write(vcpu, val);
8895 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8896 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
8901 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
8906 ret = kvm_fast_pio_in(vcpu, size, port);
8908 ret = kvm_fast_pio_out(vcpu, size, port);
8909 return ret && kvm_skip_emulated_instruction(vcpu);
8911 EXPORT_SYMBOL_GPL(kvm_fast_pio);
8913 static int kvmclock_cpu_down_prep(unsigned int cpu)
8915 __this_cpu_write(cpu_tsc_khz, 0);
8919 static void tsc_khz_changed(void *data)
8921 struct cpufreq_freqs *freq = data;
8922 unsigned long khz = 0;
8926 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
8927 khz = cpufreq_quick_get(raw_smp_processor_id());
8930 __this_cpu_write(cpu_tsc_khz, khz);
8933 #ifdef CONFIG_X86_64
8934 static void kvm_hyperv_tsc_notifier(void)
8939 mutex_lock(&kvm_lock);
8940 list_for_each_entry(kvm, &vm_list, vm_list)
8941 kvm_make_mclock_inprogress_request(kvm);
8943 /* no guest entries from this point */
8944 hyperv_stop_tsc_emulation();
8946 /* TSC frequency always matches when on Hyper-V */
8947 for_each_present_cpu(cpu)
8948 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
8949 kvm_caps.max_guest_tsc_khz = tsc_khz;
8951 list_for_each_entry(kvm, &vm_list, vm_list) {
8952 __kvm_start_pvclock_update(kvm);
8953 pvclock_update_vm_gtod_copy(kvm);
8954 kvm_end_pvclock_update(kvm);
8957 mutex_unlock(&kvm_lock);
8961 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
8964 struct kvm_vcpu *vcpu;
8969 * We allow guests to temporarily run on slowing clocks,
8970 * provided we notify them after, or to run on accelerating
8971 * clocks, provided we notify them before. Thus time never
8974 * However, we have a problem. We can't atomically update
8975 * the frequency of a given CPU from this function; it is
8976 * merely a notifier, which can be called from any CPU.
8977 * Changing the TSC frequency at arbitrary points in time
8978 * requires a recomputation of local variables related to
8979 * the TSC for each VCPU. We must flag these local variables
8980 * to be updated and be sure the update takes place with the
8981 * new frequency before any guests proceed.
8983 * Unfortunately, the combination of hotplug CPU and frequency
8984 * change creates an intractable locking scenario; the order
8985 * of when these callouts happen is undefined with respect to
8986 * CPU hotplug, and they can race with each other. As such,
8987 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
8988 * undefined; you can actually have a CPU frequency change take
8989 * place in between the computation of X and the setting of the
8990 * variable. To protect against this problem, all updates of
8991 * the per_cpu tsc_khz variable are done in an interrupt
8992 * protected IPI, and all callers wishing to update the value
8993 * must wait for a synchronous IPI to complete (which is trivial
8994 * if the caller is on the CPU already). This establishes the
8995 * necessary total order on variable updates.
8997 * Note that because a guest time update may take place
8998 * anytime after the setting of the VCPU's request bit, the
8999 * correct TSC value must be set before the request. However,
9000 * to ensure the update actually makes it to any guest which
9001 * starts running in hardware virtualization between the set
9002 * and the acquisition of the spinlock, we must also ping the
9003 * CPU after setting the request bit.
9007 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9009 mutex_lock(&kvm_lock);
9010 list_for_each_entry(kvm, &vm_list, vm_list) {
9011 kvm_for_each_vcpu(i, vcpu, kvm) {
9012 if (vcpu->cpu != cpu)
9014 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9015 if (vcpu->cpu != raw_smp_processor_id())
9019 mutex_unlock(&kvm_lock);
9021 if (freq->old < freq->new && send_ipi) {
9023 * We upscale the frequency. Must make the guest
9024 * doesn't see old kvmclock values while running with
9025 * the new frequency, otherwise we risk the guest sees
9026 * time go backwards.
9028 * In case we update the frequency for another cpu
9029 * (which might be in guest context) send an interrupt
9030 * to kick the cpu out of guest context. Next time
9031 * guest context is entered kvmclock will be updated,
9032 * so the guest will not see stale values.
9034 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9038 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
9041 struct cpufreq_freqs *freq = data;
9044 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
9046 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
9049 for_each_cpu(cpu, freq->policy->cpus)
9050 __kvmclock_cpufreq_notifier(freq, cpu);
9055 static struct notifier_block kvmclock_cpufreq_notifier_block = {
9056 .notifier_call = kvmclock_cpufreq_notifier
9059 static int kvmclock_cpu_online(unsigned int cpu)
9061 tsc_khz_changed(NULL);
9065 static void kvm_timer_init(void)
9067 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9068 max_tsc_khz = tsc_khz;
9070 if (IS_ENABLED(CONFIG_CPU_FREQ)) {
9071 struct cpufreq_policy *policy;
9075 policy = cpufreq_cpu_get(cpu);
9077 if (policy->cpuinfo.max_freq)
9078 max_tsc_khz = policy->cpuinfo.max_freq;
9079 cpufreq_cpu_put(policy);
9083 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
9084 CPUFREQ_TRANSITION_NOTIFIER);
9087 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
9088 kvmclock_cpu_online, kvmclock_cpu_down_prep);
9091 #ifdef CONFIG_X86_64
9092 static void pvclock_gtod_update_fn(struct work_struct *work)
9095 struct kvm_vcpu *vcpu;
9098 mutex_lock(&kvm_lock);
9099 list_for_each_entry(kvm, &vm_list, vm_list)
9100 kvm_for_each_vcpu(i, vcpu, kvm)
9101 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9102 atomic_set(&kvm_guest_has_master_clock, 0);
9103 mutex_unlock(&kvm_lock);
9106 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
9109 * Indirection to move queue_work() out of the tk_core.seq write held
9110 * region to prevent possible deadlocks against time accessors which
9111 * are invoked with work related locks held.
9113 static void pvclock_irq_work_fn(struct irq_work *w)
9115 queue_work(system_long_wq, &pvclock_gtod_work);
9118 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn);
9121 * Notification about pvclock gtod data update.
9123 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
9126 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
9127 struct timekeeper *tk = priv;
9129 update_pvclock_gtod(tk);
9132 * Disable master clock if host does not trust, or does not use,
9133 * TSC based clocksource. Delegate queue_work() to irq_work as
9134 * this is invoked with tk_core.seq write held.
9136 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
9137 atomic_read(&kvm_guest_has_master_clock) != 0)
9138 irq_work_queue(&pvclock_irq_work);
9142 static struct notifier_block pvclock_gtod_notifier = {
9143 .notifier_call = pvclock_gtod_notify,
9147 int kvm_arch_init(void *opaque)
9149 struct kvm_x86_init_ops *ops = opaque;
9152 if (kvm_x86_ops.hardware_enable) {
9153 pr_err("kvm: already loaded vendor module '%s'\n", kvm_x86_ops.name);
9158 if (!ops->cpu_has_kvm_support()) {
9159 pr_err_ratelimited("kvm: no hardware support for '%s'\n",
9160 ops->runtime_ops->name);
9164 if (ops->disabled_by_bios()) {
9165 pr_err_ratelimited("kvm: support for '%s' disabled by bios\n",
9166 ops->runtime_ops->name);
9172 * KVM explicitly assumes that the guest has an FPU and
9173 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
9174 * vCPU's FPU state as a fxregs_state struct.
9176 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
9177 printk(KERN_ERR "kvm: inadequate fpu\n");
9182 if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9183 pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n");
9190 x86_emulator_cache = kvm_alloc_emulator_cache();
9191 if (!x86_emulator_cache) {
9192 pr_err("kvm: failed to allocate cache for x86 emulator\n");
9196 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
9197 if (!user_return_msrs) {
9198 printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n");
9199 goto out_free_x86_emulator_cache;
9201 kvm_nr_uret_msrs = 0;
9203 r = kvm_mmu_vendor_module_init();
9205 goto out_free_percpu;
9209 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
9210 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
9211 kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
9214 if (pi_inject_timer == -1)
9215 pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER);
9216 #ifdef CONFIG_X86_64
9217 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
9219 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9220 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
9226 free_percpu(user_return_msrs);
9227 out_free_x86_emulator_cache:
9228 kmem_cache_destroy(x86_emulator_cache);
9233 void kvm_arch_exit(void)
9235 #ifdef CONFIG_X86_64
9236 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9237 clear_hv_tscchange_cb();
9241 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
9242 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
9243 CPUFREQ_TRANSITION_NOTIFIER);
9244 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
9245 #ifdef CONFIG_X86_64
9246 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
9247 irq_work_sync(&pvclock_irq_work);
9248 cancel_work_sync(&pvclock_gtod_work);
9250 kvm_x86_ops.hardware_enable = NULL;
9251 kvm_mmu_vendor_module_exit();
9252 free_percpu(user_return_msrs);
9253 kmem_cache_destroy(x86_emulator_cache);
9254 #ifdef CONFIG_KVM_XEN
9255 static_key_deferred_flush(&kvm_xen_enabled);
9256 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key));
9260 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason)
9263 * The vCPU has halted, e.g. executed HLT. Update the run state if the
9264 * local APIC is in-kernel, the run loop will detect the non-runnable
9265 * state and halt the vCPU. Exit to userspace if the local APIC is
9266 * managed by userspace, in which case userspace is responsible for
9267 * handling wake events.
9269 ++vcpu->stat.halt_exits;
9270 if (lapic_in_kernel(vcpu)) {
9271 vcpu->arch.mp_state = state;
9274 vcpu->run->exit_reason = reason;
9279 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu)
9281 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
9283 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip);
9285 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
9287 int ret = kvm_skip_emulated_instruction(vcpu);
9289 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
9290 * KVM_EXIT_DEBUG here.
9292 return kvm_emulate_halt_noskip(vcpu) && ret;
9294 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
9296 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
9298 int ret = kvm_skip_emulated_instruction(vcpu);
9300 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD,
9301 KVM_EXIT_AP_RESET_HOLD) && ret;
9303 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
9305 #ifdef CONFIG_X86_64
9306 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
9307 unsigned long clock_type)
9309 struct kvm_clock_pairing clock_pairing;
9310 struct timespec64 ts;
9314 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
9315 return -KVM_EOPNOTSUPP;
9318 * When tsc is in permanent catchup mode guests won't be able to use
9319 * pvclock_read_retry loop to get consistent view of pvclock
9321 if (vcpu->arch.tsc_always_catchup)
9322 return -KVM_EOPNOTSUPP;
9324 if (!kvm_get_walltime_and_clockread(&ts, &cycle))
9325 return -KVM_EOPNOTSUPP;
9327 clock_pairing.sec = ts.tv_sec;
9328 clock_pairing.nsec = ts.tv_nsec;
9329 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
9330 clock_pairing.flags = 0;
9331 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
9334 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
9335 sizeof(struct kvm_clock_pairing)))
9343 * kvm_pv_kick_cpu_op: Kick a vcpu.
9345 * @apicid - apicid of vcpu to be kicked.
9347 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid)
9349 struct kvm_lapic_irq lapic_irq;
9351 lapic_irq.shorthand = APIC_DEST_NOSHORT;
9352 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
9353 lapic_irq.level = 0;
9354 lapic_irq.dest_id = apicid;
9355 lapic_irq.msi_redir_hint = false;
9357 lapic_irq.delivery_mode = APIC_DM_REMRD;
9358 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
9361 bool kvm_apicv_activated(struct kvm *kvm)
9363 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
9365 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
9367 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu)
9369 ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons);
9370 ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu);
9372 return (vm_reasons | vcpu_reasons) == 0;
9374 EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated);
9376 static void set_or_clear_apicv_inhibit(unsigned long *inhibits,
9377 enum kvm_apicv_inhibit reason, bool set)
9380 __set_bit(reason, inhibits);
9382 __clear_bit(reason, inhibits);
9384 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits);
9387 static void kvm_apicv_init(struct kvm *kvm)
9389 unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons;
9391 init_rwsem(&kvm->arch.apicv_update_lock);
9393 set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true);
9396 set_or_clear_apicv_inhibit(inhibits,
9397 APICV_INHIBIT_REASON_DISABLE, true);
9400 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id)
9402 struct kvm_vcpu *target = NULL;
9403 struct kvm_apic_map *map;
9405 vcpu->stat.directed_yield_attempted++;
9407 if (single_task_running())
9411 map = rcu_dereference(vcpu->kvm->arch.apic_map);
9413 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
9414 target = map->phys_map[dest_id]->vcpu;
9418 if (!target || !READ_ONCE(target->ready))
9421 /* Ignore requests to yield to self */
9425 if (kvm_vcpu_yield_to(target) <= 0)
9428 vcpu->stat.directed_yield_successful++;
9434 static int complete_hypercall_exit(struct kvm_vcpu *vcpu)
9436 u64 ret = vcpu->run->hypercall.ret;
9438 if (!is_64_bit_mode(vcpu))
9440 kvm_rax_write(vcpu, ret);
9441 ++vcpu->stat.hypercalls;
9442 return kvm_skip_emulated_instruction(vcpu);
9445 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
9447 unsigned long nr, a0, a1, a2, a3, ret;
9450 if (kvm_xen_hypercall_enabled(vcpu->kvm))
9451 return kvm_xen_hypercall(vcpu);
9453 if (kvm_hv_hypercall_enabled(vcpu))
9454 return kvm_hv_hypercall(vcpu);
9456 nr = kvm_rax_read(vcpu);
9457 a0 = kvm_rbx_read(vcpu);
9458 a1 = kvm_rcx_read(vcpu);
9459 a2 = kvm_rdx_read(vcpu);
9460 a3 = kvm_rsi_read(vcpu);
9462 trace_kvm_hypercall(nr, a0, a1, a2, a3);
9464 op_64_bit = is_64_bit_hypercall(vcpu);
9473 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) {
9481 case KVM_HC_VAPIC_POLL_IRQ:
9484 case KVM_HC_KICK_CPU:
9485 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
9488 kvm_pv_kick_cpu_op(vcpu->kvm, a1);
9489 kvm_sched_yield(vcpu, a1);
9492 #ifdef CONFIG_X86_64
9493 case KVM_HC_CLOCK_PAIRING:
9494 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
9497 case KVM_HC_SEND_IPI:
9498 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
9501 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
9503 case KVM_HC_SCHED_YIELD:
9504 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
9507 kvm_sched_yield(vcpu, a0);
9510 case KVM_HC_MAP_GPA_RANGE: {
9511 u64 gpa = a0, npages = a1, attrs = a2;
9514 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE)))
9517 if (!PAGE_ALIGNED(gpa) || !npages ||
9518 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) {
9523 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL;
9524 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE;
9525 vcpu->run->hypercall.args[0] = gpa;
9526 vcpu->run->hypercall.args[1] = npages;
9527 vcpu->run->hypercall.args[2] = attrs;
9528 vcpu->run->hypercall.longmode = op_64_bit;
9529 vcpu->arch.complete_userspace_io = complete_hypercall_exit;
9539 kvm_rax_write(vcpu, ret);
9541 ++vcpu->stat.hypercalls;
9542 return kvm_skip_emulated_instruction(vcpu);
9544 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
9546 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
9548 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
9549 char instruction[3];
9550 unsigned long rip = kvm_rip_read(vcpu);
9553 * If the quirk is disabled, synthesize a #UD and let the guest pick up
9556 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) {
9557 ctxt->exception.error_code_valid = false;
9558 ctxt->exception.vector = UD_VECTOR;
9559 ctxt->have_exception = true;
9560 return X86EMUL_PROPAGATE_FAULT;
9563 static_call(kvm_x86_patch_hypercall)(vcpu, instruction);
9565 return emulator_write_emulated(ctxt, rip, instruction, 3,
9569 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
9571 return vcpu->run->request_interrupt_window &&
9572 likely(!pic_in_kernel(vcpu->kvm));
9575 /* Called within kvm->srcu read side. */
9576 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
9578 struct kvm_run *kvm_run = vcpu->run;
9580 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu);
9581 kvm_run->cr8 = kvm_get_cr8(vcpu);
9582 kvm_run->apic_base = kvm_get_apic_base(vcpu);
9584 kvm_run->ready_for_interrupt_injection =
9585 pic_in_kernel(vcpu->kvm) ||
9586 kvm_vcpu_ready_for_interrupt_injection(vcpu);
9589 kvm_run->flags |= KVM_RUN_X86_SMM;
9592 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
9596 if (!kvm_x86_ops.update_cr8_intercept)
9599 if (!lapic_in_kernel(vcpu))
9602 if (vcpu->arch.apic->apicv_active)
9605 if (!vcpu->arch.apic->vapic_addr)
9606 max_irr = kvm_lapic_find_highest_irr(vcpu);
9613 tpr = kvm_lapic_get_cr8(vcpu);
9615 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr);
9619 int kvm_check_nested_events(struct kvm_vcpu *vcpu)
9621 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
9622 kvm_x86_ops.nested_ops->triple_fault(vcpu);
9626 return kvm_x86_ops.nested_ops->check_events(vcpu);
9629 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
9631 trace_kvm_inj_exception(vcpu->arch.exception.nr,
9632 vcpu->arch.exception.has_error_code,
9633 vcpu->arch.exception.error_code,
9634 vcpu->arch.exception.injected);
9636 if (vcpu->arch.exception.error_code && !is_protmode(vcpu))
9637 vcpu->arch.exception.error_code = false;
9638 static_call(kvm_x86_queue_exception)(vcpu);
9641 static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit)
9644 bool can_inject = true;
9646 /* try to reinject previous events if any */
9648 if (vcpu->arch.exception.injected) {
9649 kvm_inject_exception(vcpu);
9653 * Do not inject an NMI or interrupt if there is a pending
9654 * exception. Exceptions and interrupts are recognized at
9655 * instruction boundaries, i.e. the start of an instruction.
9656 * Trap-like exceptions, e.g. #DB, have higher priority than
9657 * NMIs and interrupts, i.e. traps are recognized before an
9658 * NMI/interrupt that's pending on the same instruction.
9659 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
9660 * priority, but are only generated (pended) during instruction
9661 * execution, i.e. a pending fault-like exception means the
9662 * fault occurred on the *previous* instruction and must be
9663 * serviced prior to recognizing any new events in order to
9664 * fully complete the previous instruction.
9666 else if (!vcpu->arch.exception.pending) {
9667 if (vcpu->arch.nmi_injected) {
9668 static_call(kvm_x86_inject_nmi)(vcpu);
9670 } else if (vcpu->arch.interrupt.injected) {
9671 static_call(kvm_x86_inject_irq)(vcpu, true);
9676 WARN_ON_ONCE(vcpu->arch.exception.injected &&
9677 vcpu->arch.exception.pending);
9680 * Call check_nested_events() even if we reinjected a previous event
9681 * in order for caller to determine if it should require immediate-exit
9682 * from L2 to L1 due to pending L1 events which require exit
9685 if (is_guest_mode(vcpu)) {
9686 r = kvm_check_nested_events(vcpu);
9691 /* try to inject new event if pending */
9692 if (vcpu->arch.exception.pending) {
9693 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
9694 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
9697 if (vcpu->arch.exception.nr == DB_VECTOR) {
9698 kvm_deliver_exception_payload(vcpu);
9699 if (vcpu->arch.dr7 & DR7_GD) {
9700 vcpu->arch.dr7 &= ~DR7_GD;
9701 kvm_update_dr7(vcpu);
9705 kvm_inject_exception(vcpu);
9707 vcpu->arch.exception.pending = false;
9708 vcpu->arch.exception.injected = true;
9713 /* Don't inject interrupts if the user asked to avoid doing so */
9714 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ)
9718 * Finally, inject interrupt events. If an event cannot be injected
9719 * due to architectural conditions (e.g. IF=0) a window-open exit
9720 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
9721 * and can architecturally be injected, but we cannot do it right now:
9722 * an interrupt could have arrived just now and we have to inject it
9723 * as a vmexit, or there could already an event in the queue, which is
9724 * indicated by can_inject. In that case we request an immediate exit
9725 * in order to make progress and get back here for another iteration.
9726 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
9728 if (vcpu->arch.smi_pending) {
9729 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY;
9733 vcpu->arch.smi_pending = false;
9734 ++vcpu->arch.smi_count;
9738 static_call(kvm_x86_enable_smi_window)(vcpu);
9741 if (vcpu->arch.nmi_pending) {
9742 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY;
9746 --vcpu->arch.nmi_pending;
9747 vcpu->arch.nmi_injected = true;
9748 static_call(kvm_x86_inject_nmi)(vcpu);
9750 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0);
9752 if (vcpu->arch.nmi_pending)
9753 static_call(kvm_x86_enable_nmi_window)(vcpu);
9756 if (kvm_cpu_has_injectable_intr(vcpu)) {
9757 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY;
9761 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false);
9762 static_call(kvm_x86_inject_irq)(vcpu, false);
9763 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
9765 if (kvm_cpu_has_injectable_intr(vcpu))
9766 static_call(kvm_x86_enable_irq_window)(vcpu);
9769 if (is_guest_mode(vcpu) &&
9770 kvm_x86_ops.nested_ops->hv_timer_pending &&
9771 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
9772 *req_immediate_exit = true;
9774 WARN_ON(vcpu->arch.exception.pending);
9779 *req_immediate_exit = true;
9785 static void process_nmi(struct kvm_vcpu *vcpu)
9790 * x86 is limited to one NMI running, and one NMI pending after it.
9791 * If an NMI is already in progress, limit further NMIs to just one.
9792 * Otherwise, allow two (and we'll inject the first one immediately).
9794 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected)
9797 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
9798 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
9799 kvm_make_request(KVM_REQ_EVENT, vcpu);
9802 static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
9805 flags |= seg->g << 23;
9806 flags |= seg->db << 22;
9807 flags |= seg->l << 21;
9808 flags |= seg->avl << 20;
9809 flags |= seg->present << 15;
9810 flags |= seg->dpl << 13;
9811 flags |= seg->s << 12;
9812 flags |= seg->type << 8;
9816 static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
9818 struct kvm_segment seg;
9821 kvm_get_segment(vcpu, &seg, n);
9822 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
9825 offset = 0x7f84 + n * 12;
9827 offset = 0x7f2c + (n - 3) * 12;
9829 put_smstate(u32, buf, offset + 8, seg.base);
9830 put_smstate(u32, buf, offset + 4, seg.limit);
9831 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
9834 #ifdef CONFIG_X86_64
9835 static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
9837 struct kvm_segment seg;
9841 kvm_get_segment(vcpu, &seg, n);
9842 offset = 0x7e00 + n * 16;
9844 flags = enter_smm_get_segment_flags(&seg) >> 8;
9845 put_smstate(u16, buf, offset, seg.selector);
9846 put_smstate(u16, buf, offset + 2, flags);
9847 put_smstate(u32, buf, offset + 4, seg.limit);
9848 put_smstate(u64, buf, offset + 8, seg.base);
9852 static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
9855 struct kvm_segment seg;
9859 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
9860 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
9861 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
9862 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
9864 for (i = 0; i < 8; i++)
9865 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i));
9867 kvm_get_dr(vcpu, 6, &val);
9868 put_smstate(u32, buf, 0x7fcc, (u32)val);
9869 kvm_get_dr(vcpu, 7, &val);
9870 put_smstate(u32, buf, 0x7fc8, (u32)val);
9872 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
9873 put_smstate(u32, buf, 0x7fc4, seg.selector);
9874 put_smstate(u32, buf, 0x7f64, seg.base);
9875 put_smstate(u32, buf, 0x7f60, seg.limit);
9876 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
9878 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
9879 put_smstate(u32, buf, 0x7fc0, seg.selector);
9880 put_smstate(u32, buf, 0x7f80, seg.base);
9881 put_smstate(u32, buf, 0x7f7c, seg.limit);
9882 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
9884 static_call(kvm_x86_get_gdt)(vcpu, &dt);
9885 put_smstate(u32, buf, 0x7f74, dt.address);
9886 put_smstate(u32, buf, 0x7f70, dt.size);
9888 static_call(kvm_x86_get_idt)(vcpu, &dt);
9889 put_smstate(u32, buf, 0x7f58, dt.address);
9890 put_smstate(u32, buf, 0x7f54, dt.size);
9892 for (i = 0; i < 6; i++)
9893 enter_smm_save_seg_32(vcpu, buf, i);
9895 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
9898 put_smstate(u32, buf, 0x7efc, 0x00020000);
9899 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
9902 #ifdef CONFIG_X86_64
9903 static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
9906 struct kvm_segment seg;
9910 for (i = 0; i < 16; i++)
9911 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i));
9913 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
9914 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
9916 kvm_get_dr(vcpu, 6, &val);
9917 put_smstate(u64, buf, 0x7f68, val);
9918 kvm_get_dr(vcpu, 7, &val);
9919 put_smstate(u64, buf, 0x7f60, val);
9921 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
9922 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
9923 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
9925 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
9928 put_smstate(u32, buf, 0x7efc, 0x00020064);
9930 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
9932 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
9933 put_smstate(u16, buf, 0x7e90, seg.selector);
9934 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
9935 put_smstate(u32, buf, 0x7e94, seg.limit);
9936 put_smstate(u64, buf, 0x7e98, seg.base);
9938 static_call(kvm_x86_get_idt)(vcpu, &dt);
9939 put_smstate(u32, buf, 0x7e84, dt.size);
9940 put_smstate(u64, buf, 0x7e88, dt.address);
9942 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
9943 put_smstate(u16, buf, 0x7e70, seg.selector);
9944 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
9945 put_smstate(u32, buf, 0x7e74, seg.limit);
9946 put_smstate(u64, buf, 0x7e78, seg.base);
9948 static_call(kvm_x86_get_gdt)(vcpu, &dt);
9949 put_smstate(u32, buf, 0x7e64, dt.size);
9950 put_smstate(u64, buf, 0x7e68, dt.address);
9952 for (i = 0; i < 6; i++)
9953 enter_smm_save_seg_64(vcpu, buf, i);
9957 static void enter_smm(struct kvm_vcpu *vcpu)
9959 struct kvm_segment cs, ds;
9964 memset(buf, 0, 512);
9965 #ifdef CONFIG_X86_64
9966 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
9967 enter_smm_save_state_64(vcpu, buf);
9970 enter_smm_save_state_32(vcpu, buf);
9973 * Give enter_smm() a chance to make ISA-specific changes to the vCPU
9974 * state (e.g. leave guest mode) after we've saved the state into the
9975 * SMM state-save area.
9977 static_call(kvm_x86_enter_smm)(vcpu, buf);
9979 kvm_smm_changed(vcpu, true);
9980 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
9982 if (static_call(kvm_x86_get_nmi_mask)(vcpu))
9983 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
9985 static_call(kvm_x86_set_nmi_mask)(vcpu, true);
9987 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
9988 kvm_rip_write(vcpu, 0x8000);
9990 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
9991 static_call(kvm_x86_set_cr0)(vcpu, cr0);
9992 vcpu->arch.cr0 = cr0;
9994 static_call(kvm_x86_set_cr4)(vcpu, 0);
9996 /* Undocumented: IDT limit is set to zero on entry to SMM. */
9997 dt.address = dt.size = 0;
9998 static_call(kvm_x86_set_idt)(vcpu, &dt);
10000 kvm_set_dr(vcpu, 7, DR7_FIXED_1);
10002 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
10003 cs.base = vcpu->arch.smbase;
10008 cs.limit = ds.limit = 0xffffffff;
10009 cs.type = ds.type = 0x3;
10010 cs.dpl = ds.dpl = 0;
10015 cs.avl = ds.avl = 0;
10016 cs.present = ds.present = 1;
10017 cs.unusable = ds.unusable = 0;
10018 cs.padding = ds.padding = 0;
10020 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
10021 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
10022 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
10023 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
10024 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
10025 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
10027 #ifdef CONFIG_X86_64
10028 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
10029 static_call(kvm_x86_set_efer)(vcpu, 0);
10032 kvm_update_cpuid_runtime(vcpu);
10033 kvm_mmu_reset_context(vcpu);
10036 static void process_smi(struct kvm_vcpu *vcpu)
10038 vcpu->arch.smi_pending = true;
10039 kvm_make_request(KVM_REQ_EVENT, vcpu);
10042 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
10043 unsigned long *vcpu_bitmap)
10045 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap);
10048 void kvm_make_scan_ioapic_request(struct kvm *kvm)
10050 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
10053 void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10055 struct kvm_lapic *apic = vcpu->arch.apic;
10058 if (!lapic_in_kernel(vcpu))
10061 down_read(&vcpu->kvm->arch.apicv_update_lock);
10064 /* Do not activate APICV when APIC is disabled */
10065 activate = kvm_vcpu_apicv_activated(vcpu) &&
10066 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED);
10068 if (apic->apicv_active == activate)
10071 apic->apicv_active = activate;
10072 kvm_apic_update_apicv(vcpu);
10073 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
10076 * When APICv gets disabled, we may still have injected interrupts
10077 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was
10078 * still active when the interrupt got accepted. Make sure
10079 * inject_pending_event() is called to check for that.
10081 if (!apic->apicv_active)
10082 kvm_make_request(KVM_REQ_EVENT, vcpu);
10086 up_read(&vcpu->kvm->arch.apicv_update_lock);
10088 EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv);
10090 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10091 enum kvm_apicv_inhibit reason, bool set)
10093 unsigned long old, new;
10095 lockdep_assert_held_write(&kvm->arch.apicv_update_lock);
10097 if (!static_call(kvm_x86_check_apicv_inhibit_reasons)(reason))
10100 old = new = kvm->arch.apicv_inhibit_reasons;
10102 set_or_clear_apicv_inhibit(&new, reason, set);
10104 if (!!old != !!new) {
10106 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid
10107 * false positives in the sanity check WARN in svm_vcpu_run().
10108 * This task will wait for all vCPUs to ack the kick IRQ before
10109 * updating apicv_inhibit_reasons, and all other vCPUs will
10110 * block on acquiring apicv_update_lock so that vCPUs can't
10111 * redo svm_vcpu_run() without seeing the new inhibit state.
10113 * Note, holding apicv_update_lock and taking it in the read
10114 * side (handling the request) also prevents other vCPUs from
10115 * servicing the request with a stale apicv_inhibit_reasons.
10117 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
10118 kvm->arch.apicv_inhibit_reasons = new;
10120 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE);
10121 kvm_zap_gfn_range(kvm, gfn, gfn+1);
10124 kvm->arch.apicv_inhibit_reasons = new;
10128 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10129 enum kvm_apicv_inhibit reason, bool set)
10134 down_write(&kvm->arch.apicv_update_lock);
10135 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set);
10136 up_write(&kvm->arch.apicv_update_lock);
10138 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit);
10140 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
10142 if (!kvm_apic_present(vcpu))
10145 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
10147 if (irqchip_split(vcpu->kvm))
10148 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
10150 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10151 if (ioapic_in_kernel(vcpu->kvm))
10152 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
10155 if (is_guest_mode(vcpu))
10156 vcpu->arch.load_eoi_exitmap_pending = true;
10158 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
10161 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
10163 u64 eoi_exit_bitmap[4];
10165 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
10168 if (to_hv_vcpu(vcpu)) {
10169 bitmap_or((ulong *)eoi_exit_bitmap,
10170 vcpu->arch.ioapic_handled_vectors,
10171 to_hv_synic(vcpu)->vec_bitmap, 256);
10172 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap);
10176 static_call_cond(kvm_x86_load_eoi_exitmap)(
10177 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors);
10180 void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
10181 unsigned long start, unsigned long end)
10183 unsigned long apic_address;
10186 * The physical address of apic access page is stored in the VMCS.
10187 * Update it when it becomes invalid.
10189 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
10190 if (start <= apic_address && apic_address < end)
10191 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
10194 void kvm_arch_guest_memory_reclaimed(struct kvm *kvm)
10196 static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm);
10199 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
10201 if (!lapic_in_kernel(vcpu))
10204 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu);
10207 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
10209 smp_send_reschedule(vcpu->cpu);
10211 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
10214 * Called within kvm->srcu read side.
10215 * Returns 1 to let vcpu_run() continue the guest execution loop without
10216 * exiting to the userspace. Otherwise, the value will be returned to the
10219 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
10223 dm_request_for_irq_injection(vcpu) &&
10224 kvm_cpu_accept_dm_intr(vcpu);
10225 fastpath_t exit_fastpath;
10227 bool req_immediate_exit = false;
10229 /* Forbid vmenter if vcpu dirty ring is soft-full */
10230 if (unlikely(vcpu->kvm->dirty_ring_size &&
10231 kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) {
10232 vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL;
10233 trace_kvm_dirty_ring_exit(vcpu);
10238 if (kvm_request_pending(vcpu)) {
10239 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) {
10243 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
10244 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
10249 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu))
10250 kvm_mmu_free_obsolete_roots(vcpu);
10251 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
10252 __kvm_migrate_timers(vcpu);
10253 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
10254 kvm_update_masterclock(vcpu->kvm);
10255 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
10256 kvm_gen_kvmclock_update(vcpu);
10257 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
10258 r = kvm_guest_time_update(vcpu);
10262 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
10263 kvm_mmu_sync_roots(vcpu);
10264 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
10265 kvm_mmu_load_pgd(vcpu);
10266 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) {
10267 kvm_vcpu_flush_tlb_all(vcpu);
10269 /* Flushing all ASIDs flushes the current ASID... */
10270 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
10272 kvm_service_local_tlb_flush_requests(vcpu);
10274 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
10275 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
10279 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10280 if (is_guest_mode(vcpu)) {
10281 kvm_x86_ops.nested_ops->triple_fault(vcpu);
10283 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
10284 vcpu->mmio_needed = 0;
10289 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
10290 /* Page is swapped out. Do synthetic halt */
10291 vcpu->arch.apf.halted = true;
10295 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
10296 record_steal_time(vcpu);
10297 if (kvm_check_request(KVM_REQ_SMI, vcpu))
10299 if (kvm_check_request(KVM_REQ_NMI, vcpu))
10301 if (kvm_check_request(KVM_REQ_PMU, vcpu))
10302 kvm_pmu_handle_event(vcpu);
10303 if (kvm_check_request(KVM_REQ_PMI, vcpu))
10304 kvm_pmu_deliver_pmi(vcpu);
10305 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
10306 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
10307 if (test_bit(vcpu->arch.pending_ioapic_eoi,
10308 vcpu->arch.ioapic_handled_vectors)) {
10309 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
10310 vcpu->run->eoi.vector =
10311 vcpu->arch.pending_ioapic_eoi;
10316 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
10317 vcpu_scan_ioapic(vcpu);
10318 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
10319 vcpu_load_eoi_exitmap(vcpu);
10320 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
10321 kvm_vcpu_reload_apic_access_page(vcpu);
10322 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
10323 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10324 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
10325 vcpu->run->system_event.ndata = 0;
10329 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
10330 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10331 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
10332 vcpu->run->system_event.ndata = 0;
10336 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
10337 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
10339 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
10340 vcpu->run->hyperv = hv_vcpu->exit;
10346 * KVM_REQ_HV_STIMER has to be processed after
10347 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
10348 * depend on the guest clock being up-to-date
10350 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
10351 kvm_hv_process_stimers(vcpu);
10352 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
10353 kvm_vcpu_update_apicv(vcpu);
10354 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
10355 kvm_check_async_pf_completion(vcpu);
10356 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
10357 static_call(kvm_x86_msr_filter_changed)(vcpu);
10359 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
10360 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu);
10363 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win ||
10364 kvm_xen_has_interrupt(vcpu)) {
10365 ++vcpu->stat.req_event;
10366 r = kvm_apic_accept_events(vcpu);
10371 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
10376 r = inject_pending_event(vcpu, &req_immediate_exit);
10382 static_call(kvm_x86_enable_irq_window)(vcpu);
10384 if (kvm_lapic_enabled(vcpu)) {
10385 update_cr8_intercept(vcpu);
10386 kvm_lapic_sync_to_vapic(vcpu);
10390 r = kvm_mmu_reload(vcpu);
10392 goto cancel_injection;
10397 static_call(kvm_x86_prepare_switch_to_guest)(vcpu);
10400 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
10401 * IPI are then delayed after guest entry, which ensures that they
10402 * result in virtual interrupt delivery.
10404 local_irq_disable();
10406 /* Store vcpu->apicv_active before vcpu->mode. */
10407 smp_store_release(&vcpu->mode, IN_GUEST_MODE);
10409 kvm_vcpu_srcu_read_unlock(vcpu);
10412 * 1) We should set ->mode before checking ->requests. Please see
10413 * the comment in kvm_vcpu_exiting_guest_mode().
10415 * 2) For APICv, we should set ->mode before checking PID.ON. This
10416 * pairs with the memory barrier implicit in pi_test_and_set_on
10417 * (see vmx_deliver_posted_interrupt).
10419 * 3) This also orders the write to mode from any reads to the page
10420 * tables done while the VCPU is running. Please see the comment
10421 * in kvm_flush_remote_tlbs.
10423 smp_mb__after_srcu_read_unlock();
10426 * Process pending posted interrupts to handle the case where the
10427 * notification IRQ arrived in the host, or was never sent (because the
10428 * target vCPU wasn't running). Do this regardless of the vCPU's APICv
10429 * status, KVM doesn't update assigned devices when APICv is inhibited,
10430 * i.e. they can post interrupts even if APICv is temporarily disabled.
10432 if (kvm_lapic_enabled(vcpu))
10433 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10435 if (kvm_vcpu_exit_request(vcpu)) {
10436 vcpu->mode = OUTSIDE_GUEST_MODE;
10438 local_irq_enable();
10440 kvm_vcpu_srcu_read_lock(vcpu);
10442 goto cancel_injection;
10445 if (req_immediate_exit) {
10446 kvm_make_request(KVM_REQ_EVENT, vcpu);
10447 static_call(kvm_x86_request_immediate_exit)(vcpu);
10450 fpregs_assert_state_consistent();
10451 if (test_thread_flag(TIF_NEED_FPU_LOAD))
10452 switch_fpu_return();
10454 if (vcpu->arch.guest_fpu.xfd_err)
10455 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);
10457 if (unlikely(vcpu->arch.switch_db_regs)) {
10458 set_debugreg(0, 7);
10459 set_debugreg(vcpu->arch.eff_db[0], 0);
10460 set_debugreg(vcpu->arch.eff_db[1], 1);
10461 set_debugreg(vcpu->arch.eff_db[2], 2);
10462 set_debugreg(vcpu->arch.eff_db[3], 3);
10463 } else if (unlikely(hw_breakpoint_active())) {
10464 set_debugreg(0, 7);
10467 guest_timing_enter_irqoff();
10471 * Assert that vCPU vs. VM APICv state is consistent. An APICv
10472 * update must kick and wait for all vCPUs before toggling the
10473 * per-VM state, and responsing vCPUs must wait for the update
10474 * to complete before servicing KVM_REQ_APICV_UPDATE.
10476 WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) &&
10477 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED));
10479 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu);
10480 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST))
10483 if (kvm_lapic_enabled(vcpu))
10484 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10486 if (unlikely(kvm_vcpu_exit_request(vcpu))) {
10487 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
10493 * Do this here before restoring debug registers on the host. And
10494 * since we do this before handling the vmexit, a DR access vmexit
10495 * can (a) read the correct value of the debug registers, (b) set
10496 * KVM_DEBUGREG_WONT_EXIT again.
10498 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
10499 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
10500 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu);
10501 kvm_update_dr0123(vcpu);
10502 kvm_update_dr7(vcpu);
10506 * If the guest has used debug registers, at least dr7
10507 * will be disabled while returning to the host.
10508 * If we don't have active breakpoints in the host, we don't
10509 * care about the messed up debug address registers. But if
10510 * we have some of them active, restore the old state.
10512 if (hw_breakpoint_active())
10513 hw_breakpoint_restore();
10515 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
10516 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
10518 vcpu->mode = OUTSIDE_GUEST_MODE;
10522 * Sync xfd before calling handle_exit_irqoff() which may
10523 * rely on the fact that guest_fpu::xfd is up-to-date (e.g.
10524 * in #NM irqoff handler).
10526 if (vcpu->arch.xfd_no_write_intercept)
10527 fpu_sync_guest_vmexit_xfd_state();
10529 static_call(kvm_x86_handle_exit_irqoff)(vcpu);
10531 if (vcpu->arch.guest_fpu.xfd_err)
10532 wrmsrl(MSR_IA32_XFD_ERR, 0);
10535 * Consume any pending interrupts, including the possible source of
10536 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
10537 * An instruction is required after local_irq_enable() to fully unblock
10538 * interrupts on processors that implement an interrupt shadow, the
10539 * stat.exits increment will do nicely.
10541 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ);
10542 local_irq_enable();
10543 ++vcpu->stat.exits;
10544 local_irq_disable();
10545 kvm_after_interrupt(vcpu);
10548 * Wait until after servicing IRQs to account guest time so that any
10549 * ticks that occurred while running the guest are properly accounted
10550 * to the guest. Waiting until IRQs are enabled degrades the accuracy
10551 * of accounting via context tracking, but the loss of accuracy is
10552 * acceptable for all known use cases.
10554 guest_timing_exit_irqoff();
10556 local_irq_enable();
10559 kvm_vcpu_srcu_read_lock(vcpu);
10562 * Profile KVM exit RIPs:
10564 if (unlikely(prof_on == KVM_PROFILING)) {
10565 unsigned long rip = kvm_rip_read(vcpu);
10566 profile_hit(KVM_PROFILING, (void *)rip);
10569 if (unlikely(vcpu->arch.tsc_always_catchup))
10570 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10572 if (vcpu->arch.apic_attention)
10573 kvm_lapic_sync_from_vapic(vcpu);
10575 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath);
10579 if (req_immediate_exit)
10580 kvm_make_request(KVM_REQ_EVENT, vcpu);
10581 static_call(kvm_x86_cancel_injection)(vcpu);
10582 if (unlikely(vcpu->arch.apic_attention))
10583 kvm_lapic_sync_from_vapic(vcpu);
10588 /* Called within kvm->srcu read side. */
10589 static inline int vcpu_block(struct kvm_vcpu *vcpu)
10593 if (!kvm_arch_vcpu_runnable(vcpu)) {
10595 * Switch to the software timer before halt-polling/blocking as
10596 * the guest's timer may be a break event for the vCPU, and the
10597 * hypervisor timer runs only when the CPU is in guest mode.
10598 * Switch before halt-polling so that KVM recognizes an expired
10599 * timer before blocking.
10601 hv_timer = kvm_lapic_hv_timer_in_use(vcpu);
10603 kvm_lapic_switch_to_sw_timer(vcpu);
10605 kvm_vcpu_srcu_read_unlock(vcpu);
10606 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10607 kvm_vcpu_halt(vcpu);
10609 kvm_vcpu_block(vcpu);
10610 kvm_vcpu_srcu_read_lock(vcpu);
10613 kvm_lapic_switch_to_hv_timer(vcpu);
10615 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
10619 if (kvm_apic_accept_events(vcpu) < 0)
10621 switch(vcpu->arch.mp_state) {
10622 case KVM_MP_STATE_HALTED:
10623 case KVM_MP_STATE_AP_RESET_HOLD:
10624 vcpu->arch.pv.pv_unhalted = false;
10625 vcpu->arch.mp_state =
10626 KVM_MP_STATE_RUNNABLE;
10628 case KVM_MP_STATE_RUNNABLE:
10629 vcpu->arch.apf.halted = false;
10631 case KVM_MP_STATE_INIT_RECEIVED:
10639 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
10641 if (is_guest_mode(vcpu))
10642 kvm_check_nested_events(vcpu);
10644 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
10645 !vcpu->arch.apf.halted);
10648 /* Called within kvm->srcu read side. */
10649 static int vcpu_run(struct kvm_vcpu *vcpu)
10653 vcpu->arch.l1tf_flush_l1d = true;
10657 * If another guest vCPU requests a PV TLB flush in the middle
10658 * of instruction emulation, the rest of the emulation could
10659 * use a stale page translation. Assume that any code after
10660 * this point can start executing an instruction.
10662 vcpu->arch.at_instruction_boundary = false;
10663 if (kvm_vcpu_running(vcpu)) {
10664 r = vcpu_enter_guest(vcpu);
10666 r = vcpu_block(vcpu);
10672 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu);
10673 if (kvm_xen_has_pending_events(vcpu))
10674 kvm_xen_inject_pending_events(vcpu);
10676 if (kvm_cpu_has_pending_timer(vcpu))
10677 kvm_inject_pending_timer_irqs(vcpu);
10679 if (dm_request_for_irq_injection(vcpu) &&
10680 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
10682 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
10683 ++vcpu->stat.request_irq_exits;
10687 if (__xfer_to_guest_mode_work_pending()) {
10688 kvm_vcpu_srcu_read_unlock(vcpu);
10689 r = xfer_to_guest_mode_handle_work(vcpu);
10690 kvm_vcpu_srcu_read_lock(vcpu);
10699 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
10701 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
10704 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
10706 BUG_ON(!vcpu->arch.pio.count);
10708 return complete_emulated_io(vcpu);
10712 * Implements the following, as a state machine:
10715 * for each fragment
10716 * for each mmio piece in the fragment
10723 * for each fragment
10724 * for each mmio piece in the fragment
10729 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
10731 struct kvm_run *run = vcpu->run;
10732 struct kvm_mmio_fragment *frag;
10735 BUG_ON(!vcpu->mmio_needed);
10737 /* Complete previous fragment */
10738 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
10739 len = min(8u, frag->len);
10740 if (!vcpu->mmio_is_write)
10741 memcpy(frag->data, run->mmio.data, len);
10743 if (frag->len <= 8) {
10744 /* Switch to the next fragment. */
10746 vcpu->mmio_cur_fragment++;
10748 /* Go forward to the next mmio piece. */
10754 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
10755 vcpu->mmio_needed = 0;
10757 /* FIXME: return into emulator if single-stepping. */
10758 if (vcpu->mmio_is_write)
10760 vcpu->mmio_read_completed = 1;
10761 return complete_emulated_io(vcpu);
10764 run->exit_reason = KVM_EXIT_MMIO;
10765 run->mmio.phys_addr = frag->gpa;
10766 if (vcpu->mmio_is_write)
10767 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
10768 run->mmio.len = min(8u, frag->len);
10769 run->mmio.is_write = vcpu->mmio_is_write;
10770 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
10774 /* Swap (qemu) user FPU context for the guest FPU context. */
10775 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
10777 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */
10778 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true);
10782 /* When vcpu_run ends, restore user space FPU context. */
10783 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
10785 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false);
10786 ++vcpu->stat.fpu_reload;
10790 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
10792 struct kvm_run *kvm_run = vcpu->run;
10796 kvm_sigset_activate(vcpu);
10797 kvm_run->flags = 0;
10798 kvm_load_guest_fpu(vcpu);
10800 kvm_vcpu_srcu_read_lock(vcpu);
10801 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
10802 if (kvm_run->immediate_exit) {
10807 * It should be impossible for the hypervisor timer to be in
10808 * use before KVM has ever run the vCPU.
10810 WARN_ON_ONCE(kvm_lapic_hv_timer_in_use(vcpu));
10812 kvm_vcpu_srcu_read_unlock(vcpu);
10813 kvm_vcpu_block(vcpu);
10814 kvm_vcpu_srcu_read_lock(vcpu);
10816 if (kvm_apic_accept_events(vcpu) < 0) {
10820 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
10822 if (signal_pending(current)) {
10824 kvm_run->exit_reason = KVM_EXIT_INTR;
10825 ++vcpu->stat.signal_exits;
10830 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) ||
10831 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) {
10836 if (kvm_run->kvm_dirty_regs) {
10837 r = sync_regs(vcpu);
10842 /* re-sync apic's tpr */
10843 if (!lapic_in_kernel(vcpu)) {
10844 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
10850 if (unlikely(vcpu->arch.complete_userspace_io)) {
10851 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
10852 vcpu->arch.complete_userspace_io = NULL;
10857 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
10859 if (kvm_run->immediate_exit) {
10864 r = static_call(kvm_x86_vcpu_pre_run)(vcpu);
10868 r = vcpu_run(vcpu);
10871 kvm_put_guest_fpu(vcpu);
10872 if (kvm_run->kvm_valid_regs)
10874 post_kvm_run_save(vcpu);
10875 kvm_vcpu_srcu_read_unlock(vcpu);
10877 kvm_sigset_deactivate(vcpu);
10882 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10884 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
10886 * We are here if userspace calls get_regs() in the middle of
10887 * instruction emulation. Registers state needs to be copied
10888 * back from emulation context to vcpu. Userspace shouldn't do
10889 * that usually, but some bad designed PV devices (vmware
10890 * backdoor interface) need this to work
10892 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
10893 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
10895 regs->rax = kvm_rax_read(vcpu);
10896 regs->rbx = kvm_rbx_read(vcpu);
10897 regs->rcx = kvm_rcx_read(vcpu);
10898 regs->rdx = kvm_rdx_read(vcpu);
10899 regs->rsi = kvm_rsi_read(vcpu);
10900 regs->rdi = kvm_rdi_read(vcpu);
10901 regs->rsp = kvm_rsp_read(vcpu);
10902 regs->rbp = kvm_rbp_read(vcpu);
10903 #ifdef CONFIG_X86_64
10904 regs->r8 = kvm_r8_read(vcpu);
10905 regs->r9 = kvm_r9_read(vcpu);
10906 regs->r10 = kvm_r10_read(vcpu);
10907 regs->r11 = kvm_r11_read(vcpu);
10908 regs->r12 = kvm_r12_read(vcpu);
10909 regs->r13 = kvm_r13_read(vcpu);
10910 regs->r14 = kvm_r14_read(vcpu);
10911 regs->r15 = kvm_r15_read(vcpu);
10914 regs->rip = kvm_rip_read(vcpu);
10915 regs->rflags = kvm_get_rflags(vcpu);
10918 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10921 __get_regs(vcpu, regs);
10926 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10928 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
10929 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
10931 kvm_rax_write(vcpu, regs->rax);
10932 kvm_rbx_write(vcpu, regs->rbx);
10933 kvm_rcx_write(vcpu, regs->rcx);
10934 kvm_rdx_write(vcpu, regs->rdx);
10935 kvm_rsi_write(vcpu, regs->rsi);
10936 kvm_rdi_write(vcpu, regs->rdi);
10937 kvm_rsp_write(vcpu, regs->rsp);
10938 kvm_rbp_write(vcpu, regs->rbp);
10939 #ifdef CONFIG_X86_64
10940 kvm_r8_write(vcpu, regs->r8);
10941 kvm_r9_write(vcpu, regs->r9);
10942 kvm_r10_write(vcpu, regs->r10);
10943 kvm_r11_write(vcpu, regs->r11);
10944 kvm_r12_write(vcpu, regs->r12);
10945 kvm_r13_write(vcpu, regs->r13);
10946 kvm_r14_write(vcpu, regs->r14);
10947 kvm_r15_write(vcpu, regs->r15);
10950 kvm_rip_write(vcpu, regs->rip);
10951 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
10953 vcpu->arch.exception.pending = false;
10955 kvm_make_request(KVM_REQ_EVENT, vcpu);
10958 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
10961 __set_regs(vcpu, regs);
10966 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
10968 struct desc_ptr dt;
10970 if (vcpu->arch.guest_state_protected)
10971 goto skip_protected_regs;
10973 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
10974 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
10975 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
10976 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
10977 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
10978 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
10980 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
10981 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
10983 static_call(kvm_x86_get_idt)(vcpu, &dt);
10984 sregs->idt.limit = dt.size;
10985 sregs->idt.base = dt.address;
10986 static_call(kvm_x86_get_gdt)(vcpu, &dt);
10987 sregs->gdt.limit = dt.size;
10988 sregs->gdt.base = dt.address;
10990 sregs->cr2 = vcpu->arch.cr2;
10991 sregs->cr3 = kvm_read_cr3(vcpu);
10993 skip_protected_regs:
10994 sregs->cr0 = kvm_read_cr0(vcpu);
10995 sregs->cr4 = kvm_read_cr4(vcpu);
10996 sregs->cr8 = kvm_get_cr8(vcpu);
10997 sregs->efer = vcpu->arch.efer;
10998 sregs->apic_base = kvm_get_apic_base(vcpu);
11001 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11003 __get_sregs_common(vcpu, sregs);
11005 if (vcpu->arch.guest_state_protected)
11008 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
11009 set_bit(vcpu->arch.interrupt.nr,
11010 (unsigned long *)sregs->interrupt_bitmap);
11013 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11017 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2);
11019 if (vcpu->arch.guest_state_protected)
11022 if (is_pae_paging(vcpu)) {
11023 for (i = 0 ; i < 4 ; i++)
11024 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i);
11025 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
11029 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
11030 struct kvm_sregs *sregs)
11033 __get_sregs(vcpu, sregs);
11038 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
11039 struct kvm_mp_state *mp_state)
11044 if (kvm_mpx_supported())
11045 kvm_load_guest_fpu(vcpu);
11047 r = kvm_apic_accept_events(vcpu);
11052 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
11053 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
11054 vcpu->arch.pv.pv_unhalted)
11055 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
11057 mp_state->mp_state = vcpu->arch.mp_state;
11060 if (kvm_mpx_supported())
11061 kvm_put_guest_fpu(vcpu);
11066 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
11067 struct kvm_mp_state *mp_state)
11073 if (!lapic_in_kernel(vcpu) &&
11074 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
11078 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
11079 * INIT state; latched init should be reported using
11080 * KVM_SET_VCPU_EVENTS, so reject it here.
11082 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
11083 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
11084 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
11087 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
11088 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
11089 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
11091 vcpu->arch.mp_state = mp_state->mp_state;
11092 kvm_make_request(KVM_REQ_EVENT, vcpu);
11100 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
11101 int reason, bool has_error_code, u32 error_code)
11103 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
11106 init_emulate_ctxt(vcpu);
11108 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
11109 has_error_code, error_code);
11111 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11112 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11113 vcpu->run->internal.ndata = 0;
11117 kvm_rip_write(vcpu, ctxt->eip);
11118 kvm_set_rflags(vcpu, ctxt->eflags);
11121 EXPORT_SYMBOL_GPL(kvm_task_switch);
11123 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11125 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
11127 * When EFER.LME and CR0.PG are set, the processor is in
11128 * 64-bit mode (though maybe in a 32-bit code segment).
11129 * CR4.PAE and EFER.LMA must be set.
11131 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
11133 if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3))
11137 * Not in 64-bit mode: EFER.LMA is clear and the code
11138 * segment cannot be 64-bit.
11140 if (sregs->efer & EFER_LMA || sregs->cs.l)
11144 return kvm_is_valid_cr4(vcpu, sregs->cr4);
11147 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs,
11148 int *mmu_reset_needed, bool update_pdptrs)
11150 struct msr_data apic_base_msr;
11152 struct desc_ptr dt;
11154 if (!kvm_is_valid_sregs(vcpu, sregs))
11157 apic_base_msr.data = sregs->apic_base;
11158 apic_base_msr.host_initiated = true;
11159 if (kvm_set_apic_base(vcpu, &apic_base_msr))
11162 if (vcpu->arch.guest_state_protected)
11165 dt.size = sregs->idt.limit;
11166 dt.address = sregs->idt.base;
11167 static_call(kvm_x86_set_idt)(vcpu, &dt);
11168 dt.size = sregs->gdt.limit;
11169 dt.address = sregs->gdt.base;
11170 static_call(kvm_x86_set_gdt)(vcpu, &dt);
11172 vcpu->arch.cr2 = sregs->cr2;
11173 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
11174 vcpu->arch.cr3 = sregs->cr3;
11175 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11176 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3);
11178 kvm_set_cr8(vcpu, sregs->cr8);
11180 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
11181 static_call(kvm_x86_set_efer)(vcpu, sregs->efer);
11183 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
11184 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0);
11185 vcpu->arch.cr0 = sregs->cr0;
11187 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
11188 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4);
11190 if (update_pdptrs) {
11191 idx = srcu_read_lock(&vcpu->kvm->srcu);
11192 if (is_pae_paging(vcpu)) {
11193 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
11194 *mmu_reset_needed = 1;
11196 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11199 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11200 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11201 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11202 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11203 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11204 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11206 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11207 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11209 update_cr8_intercept(vcpu);
11211 /* Older userspace won't unhalt the vcpu on reset. */
11212 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
11213 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
11214 !is_protmode(vcpu))
11215 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11220 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11222 int pending_vec, max_bits;
11223 int mmu_reset_needed = 0;
11224 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true);
11229 if (mmu_reset_needed)
11230 kvm_mmu_reset_context(vcpu);
11232 max_bits = KVM_NR_INTERRUPTS;
11233 pending_vec = find_first_bit(
11234 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
11236 if (pending_vec < max_bits) {
11237 kvm_queue_interrupt(vcpu, pending_vec, false);
11238 pr_debug("Set back pending irq %d\n", pending_vec);
11239 kvm_make_request(KVM_REQ_EVENT, vcpu);
11244 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11246 int mmu_reset_needed = 0;
11247 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
11248 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) &&
11249 !(sregs2->efer & EFER_LMA);
11252 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID)
11255 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected))
11258 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2,
11259 &mmu_reset_needed, !valid_pdptrs);
11263 if (valid_pdptrs) {
11264 for (i = 0; i < 4 ; i++)
11265 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]);
11267 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
11268 mmu_reset_needed = 1;
11269 vcpu->arch.pdptrs_from_userspace = true;
11271 if (mmu_reset_needed)
11272 kvm_mmu_reset_context(vcpu);
11276 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
11277 struct kvm_sregs *sregs)
11282 ret = __set_sregs(vcpu, sregs);
11287 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm)
11290 struct kvm_vcpu *vcpu;
11296 down_write(&kvm->arch.apicv_update_lock);
11298 kvm_for_each_vcpu(i, vcpu, kvm) {
11299 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) {
11304 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set);
11305 up_write(&kvm->arch.apicv_update_lock);
11308 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
11309 struct kvm_guest_debug *dbg)
11311 unsigned long rflags;
11314 if (vcpu->arch.guest_state_protected)
11319 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
11321 if (vcpu->arch.exception.pending)
11323 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
11324 kvm_queue_exception(vcpu, DB_VECTOR);
11326 kvm_queue_exception(vcpu, BP_VECTOR);
11330 * Read rflags as long as potentially injected trace flags are still
11333 rflags = kvm_get_rflags(vcpu);
11335 vcpu->guest_debug = dbg->control;
11336 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
11337 vcpu->guest_debug = 0;
11339 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
11340 for (i = 0; i < KVM_NR_DB_REGS; ++i)
11341 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
11342 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
11344 for (i = 0; i < KVM_NR_DB_REGS; i++)
11345 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
11347 kvm_update_dr7(vcpu);
11349 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
11350 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu);
11353 * Trigger an rflags update that will inject or remove the trace
11356 kvm_set_rflags(vcpu, rflags);
11358 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11360 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm);
11370 * Translate a guest virtual address to a guest physical address.
11372 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
11373 struct kvm_translation *tr)
11375 unsigned long vaddr = tr->linear_address;
11381 idx = srcu_read_lock(&vcpu->kvm->srcu);
11382 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
11383 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11384 tr->physical_address = gpa;
11385 tr->valid = gpa != UNMAPPED_GVA;
11393 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11395 struct fxregs_state *fxsave;
11397 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11402 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11403 memcpy(fpu->fpr, fxsave->st_space, 128);
11404 fpu->fcw = fxsave->cwd;
11405 fpu->fsw = fxsave->swd;
11406 fpu->ftwx = fxsave->twd;
11407 fpu->last_opcode = fxsave->fop;
11408 fpu->last_ip = fxsave->rip;
11409 fpu->last_dp = fxsave->rdp;
11410 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
11416 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11418 struct fxregs_state *fxsave;
11420 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11425 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11427 memcpy(fxsave->st_space, fpu->fpr, 128);
11428 fxsave->cwd = fpu->fcw;
11429 fxsave->swd = fpu->fsw;
11430 fxsave->twd = fpu->ftwx;
11431 fxsave->fop = fpu->last_opcode;
11432 fxsave->rip = fpu->last_ip;
11433 fxsave->rdp = fpu->last_dp;
11434 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
11440 static void store_regs(struct kvm_vcpu *vcpu)
11442 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
11444 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
11445 __get_regs(vcpu, &vcpu->run->s.regs.regs);
11447 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
11448 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
11450 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
11451 kvm_vcpu_ioctl_x86_get_vcpu_events(
11452 vcpu, &vcpu->run->s.regs.events);
11455 static int sync_regs(struct kvm_vcpu *vcpu)
11457 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
11458 __set_regs(vcpu, &vcpu->run->s.regs.regs);
11459 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
11461 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
11462 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
11464 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
11466 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
11467 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
11468 vcpu, &vcpu->run->s.regs.events))
11470 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
11476 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
11478 if (kvm_check_tsc_unstable() && kvm->created_vcpus)
11479 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
11480 "guest TSC will not be reliable\n");
11482 if (!kvm->arch.max_vcpu_ids)
11483 kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS;
11485 if (id >= kvm->arch.max_vcpu_ids)
11488 return static_call(kvm_x86_vcpu_precreate)(kvm);
11491 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
11496 vcpu->arch.last_vmentry_cpu = -1;
11497 vcpu->arch.regs_avail = ~0;
11498 vcpu->arch.regs_dirty = ~0;
11500 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
11501 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11503 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
11505 r = kvm_mmu_create(vcpu);
11509 if (irqchip_in_kernel(vcpu->kvm)) {
11510 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
11512 goto fail_mmu_destroy;
11515 * Defer evaluating inhibits until the vCPU is first run, as
11516 * this vCPU will not get notified of any changes until this
11517 * vCPU is visible to other vCPUs (marked online and added to
11518 * the set of vCPUs). Opportunistically mark APICv active as
11519 * VMX in particularly is highly unlikely to have inhibits.
11520 * Ignore the current per-VM APICv state so that vCPU creation
11521 * is guaranteed to run with a deterministic value, the request
11522 * will ensure the vCPU gets the correct state before VM-Entry.
11524 if (enable_apicv) {
11525 vcpu->arch.apic->apicv_active = true;
11526 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu);
11529 static_branch_inc(&kvm_has_noapic_vcpu);
11533 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
11535 goto fail_free_lapic;
11536 vcpu->arch.pio_data = page_address(page);
11538 vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64),
11539 GFP_KERNEL_ACCOUNT);
11540 vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64),
11541 GFP_KERNEL_ACCOUNT);
11542 if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks)
11543 goto fail_free_pio_data;
11544 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
11546 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
11547 GFP_KERNEL_ACCOUNT))
11548 goto fail_free_mce_banks;
11550 if (!alloc_emulate_ctxt(vcpu))
11551 goto free_wbinvd_dirty_mask;
11553 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) {
11554 pr_err("kvm: failed to allocate vcpu's fpu\n");
11555 goto free_emulate_ctxt;
11558 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
11559 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
11561 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
11563 kvm_async_pf_hash_reset(vcpu);
11564 kvm_pmu_init(vcpu);
11566 vcpu->arch.pending_external_vector = -1;
11567 vcpu->arch.preempted_in_kernel = false;
11569 #if IS_ENABLED(CONFIG_HYPERV)
11570 vcpu->arch.hv_root_tdp = INVALID_PAGE;
11573 r = static_call(kvm_x86_vcpu_create)(vcpu);
11575 goto free_guest_fpu;
11577 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
11578 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
11579 kvm_xen_init_vcpu(vcpu);
11580 kvm_vcpu_mtrr_init(vcpu);
11582 kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz);
11583 kvm_vcpu_reset(vcpu, false);
11584 kvm_init_mmu(vcpu);
11589 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11591 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11592 free_wbinvd_dirty_mask:
11593 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11594 fail_free_mce_banks:
11595 kfree(vcpu->arch.mce_banks);
11596 kfree(vcpu->arch.mci_ctl2_banks);
11597 fail_free_pio_data:
11598 free_page((unsigned long)vcpu->arch.pio_data);
11600 kvm_free_lapic(vcpu);
11602 kvm_mmu_destroy(vcpu);
11606 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
11608 struct kvm *kvm = vcpu->kvm;
11610 if (mutex_lock_killable(&vcpu->mutex))
11613 kvm_synchronize_tsc(vcpu, 0);
11616 /* poll control enabled by default */
11617 vcpu->arch.msr_kvm_poll_control = 1;
11619 mutex_unlock(&vcpu->mutex);
11621 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
11622 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
11623 KVMCLOCK_SYNC_PERIOD);
11626 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
11630 kvmclock_reset(vcpu);
11632 static_call(kvm_x86_vcpu_free)(vcpu);
11634 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11635 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11636 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11638 kvm_xen_destroy_vcpu(vcpu);
11639 kvm_hv_vcpu_uninit(vcpu);
11640 kvm_pmu_destroy(vcpu);
11641 kfree(vcpu->arch.mce_banks);
11642 kfree(vcpu->arch.mci_ctl2_banks);
11643 kvm_free_lapic(vcpu);
11644 idx = srcu_read_lock(&vcpu->kvm->srcu);
11645 kvm_mmu_destroy(vcpu);
11646 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11647 free_page((unsigned long)vcpu->arch.pio_data);
11648 kvfree(vcpu->arch.cpuid_entries);
11649 if (!lapic_in_kernel(vcpu))
11650 static_branch_dec(&kvm_has_noapic_vcpu);
11653 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
11655 struct kvm_cpuid_entry2 *cpuid_0x1;
11656 unsigned long old_cr0 = kvm_read_cr0(vcpu);
11657 unsigned long new_cr0;
11660 * Several of the "set" flows, e.g. ->set_cr0(), read other registers
11661 * to handle side effects. RESET emulation hits those flows and relies
11662 * on emulated/virtualized registers, including those that are loaded
11663 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel
11664 * to detect improper or missing initialization.
11666 WARN_ON_ONCE(!init_event &&
11667 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu)));
11669 kvm_lapic_reset(vcpu, init_event);
11671 vcpu->arch.hflags = 0;
11673 vcpu->arch.smi_pending = 0;
11674 vcpu->arch.smi_count = 0;
11675 atomic_set(&vcpu->arch.nmi_queued, 0);
11676 vcpu->arch.nmi_pending = 0;
11677 vcpu->arch.nmi_injected = false;
11678 kvm_clear_interrupt_queue(vcpu);
11679 kvm_clear_exception_queue(vcpu);
11681 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
11682 kvm_update_dr0123(vcpu);
11683 vcpu->arch.dr6 = DR6_ACTIVE_LOW;
11684 vcpu->arch.dr7 = DR7_FIXED_1;
11685 kvm_update_dr7(vcpu);
11687 vcpu->arch.cr2 = 0;
11689 kvm_make_request(KVM_REQ_EVENT, vcpu);
11690 vcpu->arch.apf.msr_en_val = 0;
11691 vcpu->arch.apf.msr_int_val = 0;
11692 vcpu->arch.st.msr_val = 0;
11694 kvmclock_reset(vcpu);
11696 kvm_clear_async_pf_completion_queue(vcpu);
11697 kvm_async_pf_hash_reset(vcpu);
11698 vcpu->arch.apf.halted = false;
11700 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) {
11701 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate;
11704 * To avoid have the INIT path from kvm_apic_has_events() that be
11705 * called with loaded FPU and does not let userspace fix the state.
11708 kvm_put_guest_fpu(vcpu);
11710 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS);
11711 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR);
11714 kvm_load_guest_fpu(vcpu);
11718 kvm_pmu_reset(vcpu);
11719 vcpu->arch.smbase = 0x30000;
11721 vcpu->arch.msr_misc_features_enables = 0;
11722 vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |
11723 MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
11725 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP);
11726 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true);
11729 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */
11730 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
11731 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP);
11734 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon)
11735 * if no CPUID match is found. Note, it's impossible to get a match at
11736 * RESET since KVM emulates RESET before exposing the vCPU to userspace,
11737 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry
11738 * on RESET. But, go through the motions in case that's ever remedied.
11740 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1, 0);
11741 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600);
11743 static_call(kvm_x86_vcpu_reset)(vcpu, init_event);
11745 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
11746 kvm_rip_write(vcpu, 0xfff0);
11748 vcpu->arch.cr3 = 0;
11749 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11752 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions
11753 * of Intel's SDM list CD/NW as being set on INIT, but they contradict
11754 * (or qualify) that with a footnote stating that CD/NW are preserved.
11756 new_cr0 = X86_CR0_ET;
11758 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD));
11760 new_cr0 |= X86_CR0_NW | X86_CR0_CD;
11762 static_call(kvm_x86_set_cr0)(vcpu, new_cr0);
11763 static_call(kvm_x86_set_cr4)(vcpu, 0);
11764 static_call(kvm_x86_set_efer)(vcpu, 0);
11765 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11768 * On the standard CR0/CR4/EFER modification paths, there are several
11769 * complex conditions determining whether the MMU has to be reset and/or
11770 * which PCIDs have to be flushed. However, CR0.WP and the paging-related
11771 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush
11772 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as
11773 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here.
11775 if (old_cr0 & X86_CR0_PG) {
11776 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11777 kvm_mmu_reset_context(vcpu);
11781 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's
11782 * APM states the TLBs are untouched by INIT, but it also states that
11783 * the TLBs are flushed on "External initialization of the processor."
11784 * Flush the guest TLB regardless of vendor, there is no meaningful
11785 * benefit in relying on the guest to flush the TLB immediately after
11786 * INIT. A spurious TLB flush is benign and likely negligible from a
11787 * performance perspective.
11790 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11792 EXPORT_SYMBOL_GPL(kvm_vcpu_reset);
11794 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
11796 struct kvm_segment cs;
11798 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
11799 cs.selector = vector << 8;
11800 cs.base = vector << 12;
11801 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
11802 kvm_rip_write(vcpu, 0);
11804 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
11806 int kvm_arch_hardware_enable(void)
11809 struct kvm_vcpu *vcpu;
11814 bool stable, backwards_tsc = false;
11816 kvm_user_return_msr_cpu_online();
11817 ret = static_call(kvm_x86_hardware_enable)();
11821 local_tsc = rdtsc();
11822 stable = !kvm_check_tsc_unstable();
11823 list_for_each_entry(kvm, &vm_list, vm_list) {
11824 kvm_for_each_vcpu(i, vcpu, kvm) {
11825 if (!stable && vcpu->cpu == smp_processor_id())
11826 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
11827 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
11828 backwards_tsc = true;
11829 if (vcpu->arch.last_host_tsc > max_tsc)
11830 max_tsc = vcpu->arch.last_host_tsc;
11836 * Sometimes, even reliable TSCs go backwards. This happens on
11837 * platforms that reset TSC during suspend or hibernate actions, but
11838 * maintain synchronization. We must compensate. Fortunately, we can
11839 * detect that condition here, which happens early in CPU bringup,
11840 * before any KVM threads can be running. Unfortunately, we can't
11841 * bring the TSCs fully up to date with real time, as we aren't yet far
11842 * enough into CPU bringup that we know how much real time has actually
11843 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
11844 * variables that haven't been updated yet.
11846 * So we simply find the maximum observed TSC above, then record the
11847 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
11848 * the adjustment will be applied. Note that we accumulate
11849 * adjustments, in case multiple suspend cycles happen before some VCPU
11850 * gets a chance to run again. In the event that no KVM threads get a
11851 * chance to run, we will miss the entire elapsed period, as we'll have
11852 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
11853 * loose cycle time. This isn't too big a deal, since the loss will be
11854 * uniform across all VCPUs (not to mention the scenario is extremely
11855 * unlikely). It is possible that a second hibernate recovery happens
11856 * much faster than a first, causing the observed TSC here to be
11857 * smaller; this would require additional padding adjustment, which is
11858 * why we set last_host_tsc to the local tsc observed here.
11860 * N.B. - this code below runs only on platforms with reliable TSC,
11861 * as that is the only way backwards_tsc is set above. Also note
11862 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
11863 * have the same delta_cyc adjustment applied if backwards_tsc
11864 * is detected. Note further, this adjustment is only done once,
11865 * as we reset last_host_tsc on all VCPUs to stop this from being
11866 * called multiple times (one for each physical CPU bringup).
11868 * Platforms with unreliable TSCs don't have to deal with this, they
11869 * will be compensated by the logic in vcpu_load, which sets the TSC to
11870 * catchup mode. This will catchup all VCPUs to real time, but cannot
11871 * guarantee that they stay in perfect synchronization.
11873 if (backwards_tsc) {
11874 u64 delta_cyc = max_tsc - local_tsc;
11875 list_for_each_entry(kvm, &vm_list, vm_list) {
11876 kvm->arch.backwards_tsc_observed = true;
11877 kvm_for_each_vcpu(i, vcpu, kvm) {
11878 vcpu->arch.tsc_offset_adjustment += delta_cyc;
11879 vcpu->arch.last_host_tsc = local_tsc;
11880 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
11884 * We have to disable TSC offset matching.. if you were
11885 * booting a VM while issuing an S4 host suspend....
11886 * you may have some problem. Solving this issue is
11887 * left as an exercise to the reader.
11889 kvm->arch.last_tsc_nsec = 0;
11890 kvm->arch.last_tsc_write = 0;
11897 void kvm_arch_hardware_disable(void)
11899 static_call(kvm_x86_hardware_disable)();
11900 drop_user_return_notifiers();
11903 static inline void kvm_ops_update(struct kvm_x86_init_ops *ops)
11905 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
11907 #define __KVM_X86_OP(func) \
11908 static_call_update(kvm_x86_##func, kvm_x86_ops.func);
11909 #define KVM_X86_OP(func) \
11910 WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func)
11911 #define KVM_X86_OP_OPTIONAL __KVM_X86_OP
11912 #define KVM_X86_OP_OPTIONAL_RET0(func) \
11913 static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \
11914 (void *)__static_call_return0);
11915 #include <asm/kvm-x86-ops.h>
11916 #undef __KVM_X86_OP
11918 kvm_pmu_ops_update(ops->pmu_ops);
11921 int kvm_arch_hardware_setup(void *opaque)
11923 struct kvm_x86_init_ops *ops = opaque;
11926 rdmsrl_safe(MSR_EFER, &host_efer);
11928 if (boot_cpu_has(X86_FEATURE_XSAVES))
11929 rdmsrl(MSR_IA32_XSS, host_xss);
11931 kvm_init_pmu_capability();
11933 r = ops->hardware_setup();
11937 kvm_ops_update(ops);
11939 kvm_register_perf_callbacks(ops->handle_intel_pt_intr);
11941 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
11942 kvm_caps.supported_xss = 0;
11944 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
11945 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
11946 #undef __kvm_cpu_cap_has
11948 if (kvm_caps.has_tsc_control) {
11950 * Make sure the user can only configure tsc_khz values that
11951 * fit into a signed integer.
11952 * A min value is not calculated because it will always
11953 * be 1 on all machines.
11955 u64 max = min(0x7fffffffULL,
11956 __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz));
11957 kvm_caps.max_guest_tsc_khz = max;
11959 kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits;
11960 kvm_init_msr_list();
11964 void kvm_arch_hardware_unsetup(void)
11966 kvm_unregister_perf_callbacks();
11968 static_call(kvm_x86_hardware_unsetup)();
11971 int kvm_arch_check_processor_compat(void *opaque)
11973 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
11974 struct kvm_x86_init_ops *ops = opaque;
11976 WARN_ON(!irqs_disabled());
11978 if (__cr4_reserved_bits(cpu_has, c) !=
11979 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
11982 return ops->check_processor_compatibility();
11985 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
11987 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
11989 EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
11991 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
11993 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
11996 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
11997 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu);
11999 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
12001 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
12003 vcpu->arch.l1tf_flush_l1d = true;
12004 if (pmu->version && unlikely(pmu->event_count)) {
12005 pmu->need_cleanup = true;
12006 kvm_make_request(KVM_REQ_PMU, vcpu);
12008 static_call(kvm_x86_sched_in)(vcpu, cpu);
12011 void kvm_arch_free_vm(struct kvm *kvm)
12013 kfree(to_kvm_hv(kvm)->hv_pa_pg);
12014 __kvm_arch_free_vm(kvm);
12018 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
12021 unsigned long flags;
12026 ret = kvm_page_track_init(kvm);
12030 ret = kvm_mmu_init_vm(kvm);
12032 goto out_page_track;
12034 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
12035 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
12036 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
12038 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
12039 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
12040 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
12041 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
12042 &kvm->arch.irq_sources_bitmap);
12044 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
12045 mutex_init(&kvm->arch.apic_map_lock);
12046 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock);
12047 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
12049 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
12050 pvclock_update_vm_gtod_copy(kvm);
12051 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
12053 kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz;
12054 kvm->arch.guest_can_read_msr_platform_info = true;
12055 kvm->arch.enable_pmu = enable_pmu;
12057 #if IS_ENABLED(CONFIG_HYPERV)
12058 spin_lock_init(&kvm->arch.hv_root_tdp_lock);
12059 kvm->arch.hv_root_tdp = INVALID_PAGE;
12062 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
12063 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
12065 kvm_apicv_init(kvm);
12066 kvm_hv_init_vm(kvm);
12067 kvm_xen_init_vm(kvm);
12069 return static_call(kvm_x86_vm_init)(kvm);
12072 kvm_page_track_cleanup(kvm);
12077 int kvm_arch_post_init_vm(struct kvm *kvm)
12079 return kvm_mmu_post_init_vm(kvm);
12082 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
12085 kvm_mmu_unload(vcpu);
12089 static void kvm_unload_vcpu_mmus(struct kvm *kvm)
12092 struct kvm_vcpu *vcpu;
12094 kvm_for_each_vcpu(i, vcpu, kvm) {
12095 kvm_clear_async_pf_completion_queue(vcpu);
12096 kvm_unload_vcpu_mmu(vcpu);
12100 void kvm_arch_sync_events(struct kvm *kvm)
12102 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
12103 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
12108 * __x86_set_memory_region: Setup KVM internal memory slot
12110 * @kvm: the kvm pointer to the VM.
12111 * @id: the slot ID to setup.
12112 * @gpa: the GPA to install the slot (unused when @size == 0).
12113 * @size: the size of the slot. Set to zero to uninstall a slot.
12115 * This function helps to setup a KVM internal memory slot. Specify
12116 * @size > 0 to install a new slot, while @size == 0 to uninstall a
12117 * slot. The return code can be one of the following:
12119 * HVA: on success (uninstall will return a bogus HVA)
12122 * The caller should always use IS_ERR() to check the return value
12123 * before use. Note, the KVM internal memory slots are guaranteed to
12124 * remain valid and unchanged until the VM is destroyed, i.e., the
12125 * GPA->HVA translation will not change. However, the HVA is a user
12126 * address, i.e. its accessibility is not guaranteed, and must be
12127 * accessed via __copy_{to,from}_user().
12129 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
12133 unsigned long hva, old_npages;
12134 struct kvm_memslots *slots = kvm_memslots(kvm);
12135 struct kvm_memory_slot *slot;
12137 /* Called with kvm->slots_lock held. */
12138 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
12139 return ERR_PTR_USR(-EINVAL);
12141 slot = id_to_memslot(slots, id);
12143 if (slot && slot->npages)
12144 return ERR_PTR_USR(-EEXIST);
12147 * MAP_SHARED to prevent internal slot pages from being moved
12150 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
12151 MAP_SHARED | MAP_ANONYMOUS, 0);
12152 if (IS_ERR((void *)hva))
12153 return (void __user *)hva;
12155 if (!slot || !slot->npages)
12158 old_npages = slot->npages;
12159 hva = slot->userspace_addr;
12162 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
12163 struct kvm_userspace_memory_region m;
12165 m.slot = id | (i << 16);
12167 m.guest_phys_addr = gpa;
12168 m.userspace_addr = hva;
12169 m.memory_size = size;
12170 r = __kvm_set_memory_region(kvm, &m);
12172 return ERR_PTR_USR(r);
12176 vm_munmap(hva, old_npages * PAGE_SIZE);
12178 return (void __user *)hva;
12180 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
12182 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
12184 kvm_mmu_pre_destroy_vm(kvm);
12187 void kvm_arch_destroy_vm(struct kvm *kvm)
12189 if (current->mm == kvm->mm) {
12191 * Free memory regions allocated on behalf of userspace,
12192 * unless the memory map has changed due to process exit
12195 mutex_lock(&kvm->slots_lock);
12196 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
12198 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
12200 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
12201 mutex_unlock(&kvm->slots_lock);
12203 kvm_unload_vcpu_mmus(kvm);
12204 static_call_cond(kvm_x86_vm_destroy)(kvm);
12205 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1));
12206 kvm_pic_destroy(kvm);
12207 kvm_ioapic_destroy(kvm);
12208 kvm_destroy_vcpus(kvm);
12209 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
12210 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
12211 kvm_mmu_uninit_vm(kvm);
12212 kvm_page_track_cleanup(kvm);
12213 kvm_xen_destroy_vm(kvm);
12214 kvm_hv_destroy_vm(kvm);
12217 static void memslot_rmap_free(struct kvm_memory_slot *slot)
12221 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12222 kvfree(slot->arch.rmap[i]);
12223 slot->arch.rmap[i] = NULL;
12227 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
12231 memslot_rmap_free(slot);
12233 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12234 kvfree(slot->arch.lpage_info[i - 1]);
12235 slot->arch.lpage_info[i - 1] = NULL;
12238 kvm_page_track_free_memslot(slot);
12241 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages)
12243 const int sz = sizeof(*slot->arch.rmap[0]);
12246 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12248 int lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12250 if (slot->arch.rmap[i])
12253 slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT);
12254 if (!slot->arch.rmap[i]) {
12255 memslot_rmap_free(slot);
12263 static int kvm_alloc_memslot_metadata(struct kvm *kvm,
12264 struct kvm_memory_slot *slot)
12266 unsigned long npages = slot->npages;
12270 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
12271 * old arrays will be freed by __kvm_set_memory_region() if installing
12272 * the new memslot is successful.
12274 memset(&slot->arch, 0, sizeof(slot->arch));
12276 if (kvm_memslots_have_rmaps(kvm)) {
12277 r = memslot_rmap_alloc(slot, npages);
12282 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12283 struct kvm_lpage_info *linfo;
12284 unsigned long ugfn;
12288 lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12290 linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
12294 slot->arch.lpage_info[i - 1] = linfo;
12296 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
12297 linfo[0].disallow_lpage = 1;
12298 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
12299 linfo[lpages - 1].disallow_lpage = 1;
12300 ugfn = slot->userspace_addr >> PAGE_SHIFT;
12302 * If the gfn and userspace address are not aligned wrt each
12303 * other, disable large page support for this slot.
12305 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
12308 for (j = 0; j < lpages; ++j)
12309 linfo[j].disallow_lpage = 1;
12313 if (kvm_page_track_create_memslot(kvm, slot, npages))
12319 memslot_rmap_free(slot);
12321 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12322 kvfree(slot->arch.lpage_info[i - 1]);
12323 slot->arch.lpage_info[i - 1] = NULL;
12328 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
12330 struct kvm_vcpu *vcpu;
12334 * memslots->generation has been incremented.
12335 * mmio generation may have reached its maximum value.
12337 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
12339 /* Force re-initialization of steal_time cache */
12340 kvm_for_each_vcpu(i, vcpu, kvm)
12341 kvm_vcpu_kick(vcpu);
12344 int kvm_arch_prepare_memory_region(struct kvm *kvm,
12345 const struct kvm_memory_slot *old,
12346 struct kvm_memory_slot *new,
12347 enum kvm_mr_change change)
12349 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) {
12350 if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn())
12353 return kvm_alloc_memslot_metadata(kvm, new);
12356 if (change == KVM_MR_FLAGS_ONLY)
12357 memcpy(&new->arch, &old->arch, sizeof(old->arch));
12358 else if (WARN_ON_ONCE(change != KVM_MR_DELETE))
12365 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable)
12367 struct kvm_arch *ka = &kvm->arch;
12369 if (!kvm_x86_ops.cpu_dirty_log_size)
12372 if ((enable && ++ka->cpu_dirty_logging_count == 1) ||
12373 (!enable && --ka->cpu_dirty_logging_count == 0))
12374 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING);
12376 WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0);
12379 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
12380 struct kvm_memory_slot *old,
12381 const struct kvm_memory_slot *new,
12382 enum kvm_mr_change change)
12384 u32 old_flags = old ? old->flags : 0;
12385 u32 new_flags = new ? new->flags : 0;
12386 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES;
12389 * Update CPU dirty logging if dirty logging is being toggled. This
12390 * applies to all operations.
12392 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)
12393 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages);
12396 * Nothing more to do for RO slots (which can't be dirtied and can't be
12397 * made writable) or CREATE/MOVE/DELETE of a slot.
12399 * For a memslot with dirty logging disabled:
12400 * CREATE: No dirty mappings will already exist.
12401 * MOVE/DELETE: The old mappings will already have been cleaned up by
12402 * kvm_arch_flush_shadow_memslot()
12404 * For a memslot with dirty logging enabled:
12405 * CREATE: No shadow pages exist, thus nothing to write-protect
12406 * and no dirty bits to clear.
12407 * MOVE/DELETE: The old mappings will already have been cleaned up by
12408 * kvm_arch_flush_shadow_memslot().
12410 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY))
12414 * READONLY and non-flags changes were filtered out above, and the only
12415 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty
12416 * logging isn't being toggled on or off.
12418 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)))
12421 if (!log_dirty_pages) {
12423 * Dirty logging tracks sptes in 4k granularity, meaning that
12424 * large sptes have to be split. If live migration succeeds,
12425 * the guest in the source machine will be destroyed and large
12426 * sptes will be created in the destination. However, if the
12427 * guest continues to run in the source machine (for example if
12428 * live migration fails), small sptes will remain around and
12429 * cause bad performance.
12431 * Scan sptes if dirty logging has been stopped, dropping those
12432 * which can be collapsed into a single large-page spte. Later
12433 * page faults will create the large-page sptes.
12435 kvm_mmu_zap_collapsible_sptes(kvm, new);
12438 * Initially-all-set does not require write protecting any page,
12439 * because they're all assumed to be dirty.
12441 if (kvm_dirty_log_manual_protect_and_init_set(kvm))
12444 if (READ_ONCE(eager_page_split))
12445 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K);
12447 if (kvm_x86_ops.cpu_dirty_log_size) {
12448 kvm_mmu_slot_leaf_clear_dirty(kvm, new);
12449 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M);
12451 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K);
12456 void kvm_arch_commit_memory_region(struct kvm *kvm,
12457 struct kvm_memory_slot *old,
12458 const struct kvm_memory_slot *new,
12459 enum kvm_mr_change change)
12461 if (!kvm->arch.n_requested_mmu_pages &&
12462 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) {
12463 unsigned long nr_mmu_pages;
12465 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO;
12466 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
12467 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
12470 kvm_mmu_slot_apply_flags(kvm, old, new, change);
12472 /* Free the arrays associated with the old memslot. */
12473 if (change == KVM_MR_MOVE)
12474 kvm_arch_free_memslot(kvm, old);
12477 void kvm_arch_flush_shadow_all(struct kvm *kvm)
12479 kvm_mmu_zap_all(kvm);
12482 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
12483 struct kvm_memory_slot *slot)
12485 kvm_page_track_flush_slot(kvm, slot);
12488 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
12490 return (is_guest_mode(vcpu) &&
12491 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu));
12494 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
12496 if (!list_empty_careful(&vcpu->async_pf.done))
12499 if (kvm_apic_has_events(vcpu))
12502 if (vcpu->arch.pv.pv_unhalted)
12505 if (vcpu->arch.exception.pending)
12508 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12509 (vcpu->arch.nmi_pending &&
12510 static_call(kvm_x86_nmi_allowed)(vcpu, false)))
12513 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
12514 (vcpu->arch.smi_pending &&
12515 static_call(kvm_x86_smi_allowed)(vcpu, false)))
12518 if (kvm_arch_interrupt_allowed(vcpu) &&
12519 (kvm_cpu_has_interrupt(vcpu) ||
12520 kvm_guest_apic_has_interrupt(vcpu)))
12523 if (kvm_hv_has_stimer_pending(vcpu))
12526 if (is_guest_mode(vcpu) &&
12527 kvm_x86_ops.nested_ops->hv_timer_pending &&
12528 kvm_x86_ops.nested_ops->hv_timer_pending(vcpu))
12531 if (kvm_xen_has_pending_events(vcpu))
12534 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu))
12540 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
12542 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
12545 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu)
12547 if (kvm_vcpu_apicv_active(vcpu) &&
12548 static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
12554 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
12556 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
12559 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12560 kvm_test_request(KVM_REQ_SMI, vcpu) ||
12561 kvm_test_request(KVM_REQ_EVENT, vcpu))
12564 return kvm_arch_dy_has_pending_interrupt(vcpu);
12567 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
12569 if (vcpu->arch.guest_state_protected)
12572 return vcpu->arch.preempted_in_kernel;
12575 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu)
12577 return kvm_rip_read(vcpu);
12580 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
12582 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
12585 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
12587 return static_call(kvm_x86_interrupt_allowed)(vcpu, false);
12590 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
12592 /* Can't read the RIP when guest state is protected, just return 0 */
12593 if (vcpu->arch.guest_state_protected)
12596 if (is_64_bit_mode(vcpu))
12597 return kvm_rip_read(vcpu);
12598 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
12599 kvm_rip_read(vcpu));
12601 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
12603 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
12605 return kvm_get_linear_rip(vcpu) == linear_rip;
12607 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
12609 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
12611 unsigned long rflags;
12613 rflags = static_call(kvm_x86_get_rflags)(vcpu);
12614 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
12615 rflags &= ~X86_EFLAGS_TF;
12618 EXPORT_SYMBOL_GPL(kvm_get_rflags);
12620 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12622 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
12623 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
12624 rflags |= X86_EFLAGS_TF;
12625 static_call(kvm_x86_set_rflags)(vcpu, rflags);
12628 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12630 __kvm_set_rflags(vcpu, rflags);
12631 kvm_make_request(KVM_REQ_EVENT, vcpu);
12633 EXPORT_SYMBOL_GPL(kvm_set_rflags);
12635 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
12637 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
12639 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
12642 static inline u32 kvm_async_pf_next_probe(u32 key)
12644 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
12647 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12649 u32 key = kvm_async_pf_hash_fn(gfn);
12651 while (vcpu->arch.apf.gfns[key] != ~0)
12652 key = kvm_async_pf_next_probe(key);
12654 vcpu->arch.apf.gfns[key] = gfn;
12657 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
12660 u32 key = kvm_async_pf_hash_fn(gfn);
12662 for (i = 0; i < ASYNC_PF_PER_VCPU &&
12663 (vcpu->arch.apf.gfns[key] != gfn &&
12664 vcpu->arch.apf.gfns[key] != ~0); i++)
12665 key = kvm_async_pf_next_probe(key);
12670 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12672 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
12675 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
12679 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
12681 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
12685 vcpu->arch.apf.gfns[i] = ~0;
12687 j = kvm_async_pf_next_probe(j);
12688 if (vcpu->arch.apf.gfns[j] == ~0)
12690 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
12692 * k lies cyclically in ]i,j]
12694 * |....j i.k.| or |.k..j i...|
12696 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
12697 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
12702 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
12704 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
12706 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
12710 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
12712 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
12714 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
12715 &token, offset, sizeof(token));
12718 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
12720 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
12723 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
12724 &val, offset, sizeof(val)))
12730 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
12733 if (!kvm_pv_async_pf_enabled(vcpu))
12736 if (vcpu->arch.apf.send_user_only &&
12737 static_call(kvm_x86_get_cpl)(vcpu) == 0)
12740 if (is_guest_mode(vcpu)) {
12742 * L1 needs to opt into the special #PF vmexits that are
12743 * used to deliver async page faults.
12745 return vcpu->arch.apf.delivery_as_pf_vmexit;
12748 * Play it safe in case the guest temporarily disables paging.
12749 * The real mode IDT in particular is unlikely to have a #PF
12752 return is_paging(vcpu);
12756 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
12758 if (unlikely(!lapic_in_kernel(vcpu) ||
12759 kvm_event_needs_reinjection(vcpu) ||
12760 vcpu->arch.exception.pending))
12763 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
12767 * If interrupts are off we cannot even use an artificial
12770 return kvm_arch_interrupt_allowed(vcpu);
12773 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
12774 struct kvm_async_pf *work)
12776 struct x86_exception fault;
12778 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
12779 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
12781 if (kvm_can_deliver_async_pf(vcpu) &&
12782 !apf_put_user_notpresent(vcpu)) {
12783 fault.vector = PF_VECTOR;
12784 fault.error_code_valid = true;
12785 fault.error_code = 0;
12786 fault.nested_page_fault = false;
12787 fault.address = work->arch.token;
12788 fault.async_page_fault = true;
12789 kvm_inject_page_fault(vcpu, &fault);
12793 * It is not possible to deliver a paravirtualized asynchronous
12794 * page fault, but putting the guest in an artificial halt state
12795 * can be beneficial nevertheless: if an interrupt arrives, we
12796 * can deliver it timely and perhaps the guest will schedule
12797 * another process. When the instruction that triggered a page
12798 * fault is retried, hopefully the page will be ready in the host.
12800 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
12805 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
12806 struct kvm_async_pf *work)
12808 struct kvm_lapic_irq irq = {
12809 .delivery_mode = APIC_DM_FIXED,
12810 .vector = vcpu->arch.apf.vec
12813 if (work->wakeup_all)
12814 work->arch.token = ~0; /* broadcast wakeup */
12816 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
12817 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
12819 if ((work->wakeup_all || work->notpresent_injected) &&
12820 kvm_pv_async_pf_enabled(vcpu) &&
12821 !apf_put_user_ready(vcpu, work->arch.token)) {
12822 vcpu->arch.apf.pageready_pending = true;
12823 kvm_apic_set_irq(vcpu, &irq, NULL);
12826 vcpu->arch.apf.halted = false;
12827 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
12830 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
12832 kvm_make_request(KVM_REQ_APF_READY, vcpu);
12833 if (!vcpu->arch.apf.pageready_pending)
12834 kvm_vcpu_kick(vcpu);
12837 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
12839 if (!kvm_pv_async_pf_enabled(vcpu))
12842 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu);
12845 void kvm_arch_start_assignment(struct kvm *kvm)
12847 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1)
12848 static_call_cond(kvm_x86_pi_start_assignment)(kvm);
12850 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
12852 void kvm_arch_end_assignment(struct kvm *kvm)
12854 atomic_dec(&kvm->arch.assigned_device_count);
12856 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
12858 bool kvm_arch_has_assigned_device(struct kvm *kvm)
12860 return atomic_read(&kvm->arch.assigned_device_count);
12862 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
12864 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
12866 atomic_inc(&kvm->arch.noncoherent_dma_count);
12868 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
12870 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
12872 atomic_dec(&kvm->arch.noncoherent_dma_count);
12874 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
12876 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
12878 return atomic_read(&kvm->arch.noncoherent_dma_count);
12880 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
12882 bool kvm_arch_has_irq_bypass(void)
12887 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
12888 struct irq_bypass_producer *prod)
12890 struct kvm_kernel_irqfd *irqfd =
12891 container_of(cons, struct kvm_kernel_irqfd, consumer);
12894 irqfd->producer = prod;
12895 kvm_arch_start_assignment(irqfd->kvm);
12896 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm,
12897 prod->irq, irqfd->gsi, 1);
12900 kvm_arch_end_assignment(irqfd->kvm);
12905 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
12906 struct irq_bypass_producer *prod)
12909 struct kvm_kernel_irqfd *irqfd =
12910 container_of(cons, struct kvm_kernel_irqfd, consumer);
12912 WARN_ON(irqfd->producer != prod);
12913 irqfd->producer = NULL;
12916 * When producer of consumer is unregistered, we change back to
12917 * remapped mode, so we can re-use the current implementation
12918 * when the irq is masked/disabled or the consumer side (KVM
12919 * int this case doesn't want to receive the interrupts.
12921 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0);
12923 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
12924 " fails: %d\n", irqfd->consumer.token, ret);
12926 kvm_arch_end_assignment(irqfd->kvm);
12929 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
12930 uint32_t guest_irq, bool set)
12932 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set);
12935 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old,
12936 struct kvm_kernel_irq_routing_entry *new)
12938 if (new->type != KVM_IRQ_ROUTING_MSI)
12941 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi));
12944 bool kvm_vector_hashing_enabled(void)
12946 return vector_hashing;
12949 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
12951 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
12953 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
12956 int kvm_spec_ctrl_test_value(u64 value)
12959 * test that setting IA32_SPEC_CTRL to given value
12960 * is allowed by the host processor
12964 unsigned long flags;
12967 local_irq_save(flags);
12969 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
12971 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
12974 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
12976 local_irq_restore(flags);
12980 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
12982 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
12984 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
12985 struct x86_exception fault;
12986 u64 access = error_code &
12987 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
12989 if (!(error_code & PFERR_PRESENT_MASK) ||
12990 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != UNMAPPED_GVA) {
12992 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
12993 * tables probably do not match the TLB. Just proceed
12994 * with the error code that the processor gave.
12996 fault.vector = PF_VECTOR;
12997 fault.error_code_valid = true;
12998 fault.error_code = error_code;
12999 fault.nested_page_fault = false;
13000 fault.address = gva;
13002 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
13004 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
13007 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
13008 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
13009 * indicates whether exit to userspace is needed.
13011 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
13012 struct x86_exception *e)
13014 if (r == X86EMUL_PROPAGATE_FAULT) {
13015 kvm_inject_emulated_page_fault(vcpu, e);
13020 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
13021 * while handling a VMX instruction KVM could've handled the request
13022 * correctly by exiting to userspace and performing I/O but there
13023 * doesn't seem to be a real use-case behind such requests, just return
13024 * KVM_EXIT_INTERNAL_ERROR for now.
13026 kvm_prepare_emulation_failure_exit(vcpu);
13030 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
13032 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
13035 struct x86_exception e;
13042 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
13043 if (r != X86EMUL_CONTINUE)
13044 return kvm_handle_memory_failure(vcpu, r, &e);
13046 if (operand.pcid >> 12 != 0) {
13047 kvm_inject_gp(vcpu, 0);
13051 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
13054 case INVPCID_TYPE_INDIV_ADDR:
13055 if ((!pcid_enabled && (operand.pcid != 0)) ||
13056 is_noncanonical_address(operand.gla, vcpu)) {
13057 kvm_inject_gp(vcpu, 0);
13060 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
13061 return kvm_skip_emulated_instruction(vcpu);
13063 case INVPCID_TYPE_SINGLE_CTXT:
13064 if (!pcid_enabled && (operand.pcid != 0)) {
13065 kvm_inject_gp(vcpu, 0);
13069 kvm_invalidate_pcid(vcpu, operand.pcid);
13070 return kvm_skip_emulated_instruction(vcpu);
13072 case INVPCID_TYPE_ALL_NON_GLOBAL:
13074 * Currently, KVM doesn't mark global entries in the shadow
13075 * page tables, so a non-global flush just degenerates to a
13076 * global flush. If needed, we could optimize this later by
13077 * keeping track of global entries in shadow page tables.
13081 case INVPCID_TYPE_ALL_INCL_GLOBAL:
13082 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
13083 return kvm_skip_emulated_instruction(vcpu);
13086 kvm_inject_gp(vcpu, 0);
13090 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
13092 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
13094 struct kvm_run *run = vcpu->run;
13095 struct kvm_mmio_fragment *frag;
13098 BUG_ON(!vcpu->mmio_needed);
13100 /* Complete previous fragment */
13101 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
13102 len = min(8u, frag->len);
13103 if (!vcpu->mmio_is_write)
13104 memcpy(frag->data, run->mmio.data, len);
13106 if (frag->len <= 8) {
13107 /* Switch to the next fragment. */
13109 vcpu->mmio_cur_fragment++;
13111 /* Go forward to the next mmio piece. */
13117 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
13118 vcpu->mmio_needed = 0;
13120 // VMG change, at this point, we're always done
13121 // RIP has already been advanced
13125 // More MMIO is needed
13126 run->mmio.phys_addr = frag->gpa;
13127 run->mmio.len = min(8u, frag->len);
13128 run->mmio.is_write = vcpu->mmio_is_write;
13129 if (run->mmio.is_write)
13130 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
13131 run->exit_reason = KVM_EXIT_MMIO;
13133 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13138 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13142 struct kvm_mmio_fragment *frag;
13147 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13148 if (handled == bytes)
13155 /*TODO: Check if need to increment number of frags */
13156 frag = vcpu->mmio_fragments;
13157 vcpu->mmio_nr_fragments = 1;
13162 vcpu->mmio_needed = 1;
13163 vcpu->mmio_cur_fragment = 0;
13165 vcpu->run->mmio.phys_addr = gpa;
13166 vcpu->run->mmio.len = min(8u, frag->len);
13167 vcpu->run->mmio.is_write = 1;
13168 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
13169 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13171 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13175 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
13177 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13181 struct kvm_mmio_fragment *frag;
13186 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13187 if (handled == bytes)
13194 /*TODO: Check if need to increment number of frags */
13195 frag = vcpu->mmio_fragments;
13196 vcpu->mmio_nr_fragments = 1;
13201 vcpu->mmio_needed = 1;
13202 vcpu->mmio_cur_fragment = 0;
13204 vcpu->run->mmio.phys_addr = gpa;
13205 vcpu->run->mmio.len = min(8u, frag->len);
13206 vcpu->run->mmio.is_write = 0;
13207 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13209 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13213 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
13215 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13216 unsigned int port);
13218 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu)
13220 int size = vcpu->arch.pio.size;
13221 int port = vcpu->arch.pio.port;
13223 vcpu->arch.pio.count = 0;
13224 if (vcpu->arch.sev_pio_count)
13225 return kvm_sev_es_outs(vcpu, size, port);
13229 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13233 unsigned int count =
13234 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13235 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count);
13237 /* memcpy done already by emulator_pio_out. */
13238 vcpu->arch.sev_pio_count -= count;
13239 vcpu->arch.sev_pio_data += count * size;
13243 /* Emulation done by the kernel. */
13244 if (!vcpu->arch.sev_pio_count)
13248 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs;
13252 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13253 unsigned int port);
13255 static void advance_sev_es_emulated_ins(struct kvm_vcpu *vcpu, unsigned count, int size)
13257 vcpu->arch.sev_pio_count -= count;
13258 vcpu->arch.sev_pio_data += count * size;
13261 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
13263 unsigned count = vcpu->arch.pio.count;
13264 int size = vcpu->arch.pio.size;
13265 int port = vcpu->arch.pio.port;
13267 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data);
13268 advance_sev_es_emulated_ins(vcpu, count, size);
13269 if (vcpu->arch.sev_pio_count)
13270 return kvm_sev_es_ins(vcpu, size, port);
13274 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13278 unsigned int count =
13279 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13280 if (!__emulator_pio_in(vcpu, size, port, vcpu->arch.sev_pio_data, count))
13283 /* Emulation done by the kernel. */
13284 advance_sev_es_emulated_ins(vcpu, count, size);
13285 if (!vcpu->arch.sev_pio_count)
13289 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
13293 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
13294 unsigned int port, void *data, unsigned int count,
13297 vcpu->arch.sev_pio_data = data;
13298 vcpu->arch.sev_pio_count = count;
13299 return in ? kvm_sev_es_ins(vcpu, size, port)
13300 : kvm_sev_es_outs(vcpu, size, port);
13302 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
13304 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
13305 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
13306 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
13307 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
13308 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
13309 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
13310 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
13311 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
13312 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
13313 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
13314 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
13315 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
13316 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
13317 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
13318 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
13319 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
13320 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
13321 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
13322 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
13323 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
13324 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
13325 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
13326 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath);
13327 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell);
13328 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq);
13329 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
13330 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
13331 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
13332 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
13334 static int __init kvm_x86_init(void)
13336 kvm_mmu_x86_module_init();
13339 module_init(kvm_x86_init);
13341 static void __exit kvm_x86_exit(void)
13344 * If module_init() is implemented, module_exit() must also be
13345 * implemented to allow module unload.
13348 module_exit(kvm_x86_exit);