1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3 #include <linux/kvm_host.h>
7 #include "kvm_cache_regs.h"
13 #include <linux/module.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/kernel.h>
16 #include <linux/vmalloc.h>
17 #include <linux/highmem.h>
18 #include <linux/amd-iommu.h>
19 #include <linux/sched.h>
20 #include <linux/trace_events.h>
21 #include <linux/slab.h>
22 #include <linux/hashtable.h>
23 #include <linux/objtool.h>
24 #include <linux/psp-sev.h>
25 #include <linux/file.h>
26 #include <linux/pagemap.h>
27 #include <linux/swap.h>
28 #include <linux/rwsem.h>
29 #include <linux/cc_platform.h>
30 #include <linux/smp.h>
33 #include <asm/perf_event.h>
34 #include <asm/tlbflush.h>
36 #include <asm/debugreg.h>
37 #include <asm/kvm_para.h>
38 #include <asm/irq_remapping.h>
39 #include <asm/spec-ctrl.h>
40 #include <asm/cpu_device_id.h>
41 #include <asm/traps.h>
42 #include <asm/fpu/api.h>
44 #include <asm/virtext.h>
46 #include <trace/events/ipi.h>
53 #include "kvm_onhyperv.h"
54 #include "svm_onhyperv.h"
56 MODULE_AUTHOR("Qumranet");
57 MODULE_LICENSE("GPL");
60 static const struct x86_cpu_id svm_cpu_id[] = {
61 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
64 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
67 #define SEG_TYPE_LDT 2
68 #define SEG_TYPE_BUSY_TSS16 3
70 static bool erratum_383_found __read_mostly;
72 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
75 * Set osvw_len to higher value when updated Revision Guides
76 * are published and we know what the new status bits are
78 static uint64_t osvw_len = 4, osvw_status;
80 static DEFINE_PER_CPU(u64, current_tsc_ratio);
82 #define X2APIC_MSR(x) (APIC_BASE_MSR + (x >> 4))
84 static const struct svm_direct_access_msrs {
85 u32 index; /* Index of the MSR */
86 bool always; /* True if intercept is initially cleared */
87 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
88 { .index = MSR_STAR, .always = true },
89 { .index = MSR_IA32_SYSENTER_CS, .always = true },
90 { .index = MSR_IA32_SYSENTER_EIP, .always = false },
91 { .index = MSR_IA32_SYSENTER_ESP, .always = false },
93 { .index = MSR_GS_BASE, .always = true },
94 { .index = MSR_FS_BASE, .always = true },
95 { .index = MSR_KERNEL_GS_BASE, .always = true },
96 { .index = MSR_LSTAR, .always = true },
97 { .index = MSR_CSTAR, .always = true },
98 { .index = MSR_SYSCALL_MASK, .always = true },
100 { .index = MSR_IA32_SPEC_CTRL, .always = false },
101 { .index = MSR_IA32_PRED_CMD, .always = false },
102 { .index = MSR_IA32_FLUSH_CMD, .always = false },
103 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
104 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
105 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
106 { .index = MSR_IA32_LASTINTTOIP, .always = false },
107 { .index = MSR_EFER, .always = false },
108 { .index = MSR_IA32_CR_PAT, .always = false },
109 { .index = MSR_AMD64_SEV_ES_GHCB, .always = true },
110 { .index = MSR_TSC_AUX, .always = false },
111 { .index = X2APIC_MSR(APIC_ID), .always = false },
112 { .index = X2APIC_MSR(APIC_LVR), .always = false },
113 { .index = X2APIC_MSR(APIC_TASKPRI), .always = false },
114 { .index = X2APIC_MSR(APIC_ARBPRI), .always = false },
115 { .index = X2APIC_MSR(APIC_PROCPRI), .always = false },
116 { .index = X2APIC_MSR(APIC_EOI), .always = false },
117 { .index = X2APIC_MSR(APIC_RRR), .always = false },
118 { .index = X2APIC_MSR(APIC_LDR), .always = false },
119 { .index = X2APIC_MSR(APIC_DFR), .always = false },
120 { .index = X2APIC_MSR(APIC_SPIV), .always = false },
121 { .index = X2APIC_MSR(APIC_ISR), .always = false },
122 { .index = X2APIC_MSR(APIC_TMR), .always = false },
123 { .index = X2APIC_MSR(APIC_IRR), .always = false },
124 { .index = X2APIC_MSR(APIC_ESR), .always = false },
125 { .index = X2APIC_MSR(APIC_ICR), .always = false },
126 { .index = X2APIC_MSR(APIC_ICR2), .always = false },
130 * AMD does not virtualize APIC TSC-deadline timer mode, but it is
131 * emulated by KVM. When setting APIC LVTT (0x832) register bit 18,
132 * the AVIC hardware would generate GP fault. Therefore, always
133 * intercept the MSR 0x832, and do not setup direct_access_msr.
135 { .index = X2APIC_MSR(APIC_LVTTHMR), .always = false },
136 { .index = X2APIC_MSR(APIC_LVTPC), .always = false },
137 { .index = X2APIC_MSR(APIC_LVT0), .always = false },
138 { .index = X2APIC_MSR(APIC_LVT1), .always = false },
139 { .index = X2APIC_MSR(APIC_LVTERR), .always = false },
140 { .index = X2APIC_MSR(APIC_TMICT), .always = false },
141 { .index = X2APIC_MSR(APIC_TMCCT), .always = false },
142 { .index = X2APIC_MSR(APIC_TDCR), .always = false },
143 { .index = MSR_INVALID, .always = false },
147 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
148 * pause_filter_count: On processors that support Pause filtering(indicated
149 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
150 * count value. On VMRUN this value is loaded into an internal counter.
151 * Each time a pause instruction is executed, this counter is decremented
152 * until it reaches zero at which time a #VMEXIT is generated if pause
153 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
154 * Intercept Filtering for more details.
155 * This also indicate if ple logic enabled.
157 * pause_filter_thresh: In addition, some processor families support advanced
158 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
159 * the amount of time a guest is allowed to execute in a pause loop.
160 * In this mode, a 16-bit pause filter threshold field is added in the
161 * VMCB. The threshold value is a cycle count that is used to reset the
162 * pause counter. As with simple pause filtering, VMRUN loads the pause
163 * count value from VMCB into an internal counter. Then, on each pause
164 * instruction the hardware checks the elapsed number of cycles since
165 * the most recent pause instruction against the pause filter threshold.
166 * If the elapsed cycle count is greater than the pause filter threshold,
167 * then the internal pause count is reloaded from the VMCB and execution
168 * continues. If the elapsed cycle count is less than the pause filter
169 * threshold, then the internal pause count is decremented. If the count
170 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
171 * triggered. If advanced pause filtering is supported and pause filter
172 * threshold field is set to zero, the filter will operate in the simpler,
176 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
177 module_param(pause_filter_thresh, ushort, 0444);
179 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
180 module_param(pause_filter_count, ushort, 0444);
182 /* Default doubles per-vcpu window every exit. */
183 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
184 module_param(pause_filter_count_grow, ushort, 0444);
186 /* Default resets per-vcpu window every exit to pause_filter_count. */
187 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
188 module_param(pause_filter_count_shrink, ushort, 0444);
190 /* Default is to compute the maximum so we can never overflow. */
191 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
192 module_param(pause_filter_count_max, ushort, 0444);
195 * Use nested page tables by default. Note, NPT may get forced off by
196 * svm_hardware_setup() if it's unsupported by hardware or the host kernel.
198 bool npt_enabled = true;
199 module_param_named(npt, npt_enabled, bool, 0444);
201 /* allow nested virtualization in KVM/SVM */
202 static int nested = true;
203 module_param(nested, int, S_IRUGO);
205 /* enable/disable Next RIP Save */
206 static int nrips = true;
207 module_param(nrips, int, 0444);
209 /* enable/disable Virtual VMLOAD VMSAVE */
210 static int vls = true;
211 module_param(vls, int, 0444);
213 /* enable/disable Virtual GIF */
215 module_param(vgif, int, 0444);
217 /* enable/disable LBR virtualization */
218 static int lbrv = true;
219 module_param(lbrv, int, 0444);
221 static int tsc_scaling = true;
222 module_param(tsc_scaling, int, 0444);
225 * enable / disable AVIC. Because the defaults differ for APICv
226 * support between VMX and SVM we cannot use module_param_named.
229 module_param(avic, bool, 0444);
231 bool __read_mostly dump_invalid_vmcb;
232 module_param(dump_invalid_vmcb, bool, 0644);
235 bool intercept_smi = true;
236 module_param(intercept_smi, bool, 0444);
239 module_param(vnmi, bool, 0444);
241 static bool svm_gp_erratum_intercept = true;
243 static u8 rsm_ins_bytes[] = "\x0f\xaa";
245 static unsigned long iopm_base;
247 struct kvm_ldttss_desc {
250 unsigned base1:8, type:5, dpl:2, p:1;
251 unsigned limit1:4, zero0:3, g:1, base2:8;
254 } __attribute__((packed));
256 DEFINE_PER_CPU(struct svm_cpu_data, svm_data);
259 * Only MSR_TSC_AUX is switched via the user return hook. EFER is switched via
260 * the VMCB, and the SYSCALL/SYSENTER MSRs are handled by VMLOAD/VMSAVE.
262 * RDTSCP and RDPID are not used in the kernel, specifically to allow KVM to
263 * defer the restoration of TSC_AUX until the CPU returns to userspace.
265 static int tsc_aux_uret_slot __read_mostly = -1;
267 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
269 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
270 #define MSRS_RANGE_SIZE 2048
271 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
273 u32 svm_msrpm_offset(u32 msr)
278 for (i = 0; i < NUM_MSR_MAPS; i++) {
279 if (msr < msrpm_ranges[i] ||
280 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
283 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
284 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
286 /* Now we have the u8 offset - but need the u32 offset */
290 /* MSR not in any range */
294 static void svm_flush_tlb_current(struct kvm_vcpu *vcpu);
296 static int get_npt_level(void)
299 return pgtable_l5_enabled() ? PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
301 return PT32E_ROOT_LEVEL;
305 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
307 struct vcpu_svm *svm = to_svm(vcpu);
308 u64 old_efer = vcpu->arch.efer;
309 vcpu->arch.efer = efer;
312 /* Shadow paging assumes NX to be available. */
315 if (!(efer & EFER_LMA))
319 if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
320 if (!(efer & EFER_SVME)) {
321 svm_leave_nested(vcpu);
322 svm_set_gif(svm, true);
323 /* #GP intercept is still needed for vmware backdoor */
324 if (!enable_vmware_backdoor)
325 clr_exception_intercept(svm, GP_VECTOR);
328 * Free the nested guest state, unless we are in SMM.
329 * In this case we will return to the nested guest
330 * as soon as we leave SMM.
333 svm_free_nested(svm);
336 int ret = svm_allocate_nested(svm);
339 vcpu->arch.efer = old_efer;
344 * Never intercept #GP for SEV guests, KVM can't
345 * decrypt guest memory to workaround the erratum.
347 if (svm_gp_erratum_intercept && !sev_guest(vcpu->kvm))
348 set_exception_intercept(svm, GP_VECTOR);
352 svm->vmcb->save.efer = efer | EFER_SVME;
353 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
357 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
359 struct vcpu_svm *svm = to_svm(vcpu);
362 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
363 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
367 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
369 struct vcpu_svm *svm = to_svm(vcpu);
372 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
374 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
378 static int __svm_skip_emulated_instruction(struct kvm_vcpu *vcpu,
379 bool commit_side_effects)
381 struct vcpu_svm *svm = to_svm(vcpu);
382 unsigned long old_rflags;
385 * SEV-ES does not expose the next RIP. The RIP update is controlled by
386 * the type of exit and the #VC handler in the guest.
388 if (sev_es_guest(vcpu->kvm))
391 if (nrips && svm->vmcb->control.next_rip != 0) {
392 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
393 svm->next_rip = svm->vmcb->control.next_rip;
396 if (!svm->next_rip) {
397 if (unlikely(!commit_side_effects))
398 old_rflags = svm->vmcb->save.rflags;
400 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
403 if (unlikely(!commit_side_effects))
404 svm->vmcb->save.rflags = old_rflags;
406 kvm_rip_write(vcpu, svm->next_rip);
410 if (likely(commit_side_effects))
411 svm_set_interrupt_shadow(vcpu, 0);
416 static int svm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
418 return __svm_skip_emulated_instruction(vcpu, true);
421 static int svm_update_soft_interrupt_rip(struct kvm_vcpu *vcpu)
423 unsigned long rip, old_rip = kvm_rip_read(vcpu);
424 struct vcpu_svm *svm = to_svm(vcpu);
427 * Due to architectural shortcomings, the CPU doesn't always provide
428 * NextRIP, e.g. if KVM intercepted an exception that occurred while
429 * the CPU was vectoring an INTO/INT3 in the guest. Temporarily skip
430 * the instruction even if NextRIP is supported to acquire the next
431 * RIP so that it can be shoved into the NextRIP field, otherwise
432 * hardware will fail to advance guest RIP during event injection.
433 * Drop the exception/interrupt if emulation fails and effectively
434 * retry the instruction, it's the least awful option. If NRIPS is
435 * in use, the skip must not commit any side effects such as clearing
436 * the interrupt shadow or RFLAGS.RF.
438 if (!__svm_skip_emulated_instruction(vcpu, !nrips))
441 rip = kvm_rip_read(vcpu);
444 * Save the injection information, even when using next_rip, as the
445 * VMCB's next_rip will be lost (cleared on VM-Exit) if the injection
446 * doesn't complete due to a VM-Exit occurring while the CPU is
447 * vectoring the event. Decoding the instruction isn't guaranteed to
448 * work as there may be no backing instruction, e.g. if the event is
449 * being injected by L1 for L2, or if the guest is patching INT3 into
450 * a different instruction.
452 svm->soft_int_injected = true;
453 svm->soft_int_csbase = svm->vmcb->save.cs.base;
454 svm->soft_int_old_rip = old_rip;
455 svm->soft_int_next_rip = rip;
458 kvm_rip_write(vcpu, old_rip);
460 if (static_cpu_has(X86_FEATURE_NRIPS))
461 svm->vmcb->control.next_rip = rip;
466 static void svm_inject_exception(struct kvm_vcpu *vcpu)
468 struct kvm_queued_exception *ex = &vcpu->arch.exception;
469 struct vcpu_svm *svm = to_svm(vcpu);
471 kvm_deliver_exception_payload(vcpu, ex);
473 if (kvm_exception_is_soft(ex->vector) &&
474 svm_update_soft_interrupt_rip(vcpu))
477 svm->vmcb->control.event_inj = ex->vector
479 | (ex->has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
480 | SVM_EVTINJ_TYPE_EXEPT;
481 svm->vmcb->control.event_inj_err = ex->error_code;
484 static void svm_init_erratum_383(void)
490 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
493 /* Use _safe variants to not break nested virtualization */
494 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
500 low = lower_32_bits(val);
501 high = upper_32_bits(val);
503 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
505 erratum_383_found = true;
508 static void svm_init_osvw(struct kvm_vcpu *vcpu)
511 * Guests should see errata 400 and 415 as fixed (assuming that
512 * HLT and IO instructions are intercepted).
514 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
515 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
518 * By increasing VCPU's osvw.length to 3 we are telling the guest that
519 * all osvw.status bits inside that length, including bit 0 (which is
520 * reserved for erratum 298), are valid. However, if host processor's
521 * osvw_len is 0 then osvw_status[0] carries no information. We need to
522 * be conservative here and therefore we tell the guest that erratum 298
523 * is present (because we really don't know).
525 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
526 vcpu->arch.osvw.status |= 1;
529 static bool kvm_is_svm_supported(void)
531 int cpu = raw_smp_processor_id();
535 if (!cpu_has_svm(&msg)) {
536 pr_err("SVM not supported by CPU %d, %s\n", cpu, msg);
540 if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) {
541 pr_info("KVM is unsupported when running as an SEV guest\n");
545 rdmsrl(MSR_VM_CR, vm_cr);
546 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) {
547 pr_err("SVM disabled (by BIOS) in MSR_VM_CR on CPU %d\n", cpu);
554 static int svm_check_processor_compat(void)
556 if (!kvm_is_svm_supported())
562 void __svm_write_tsc_multiplier(u64 multiplier)
566 if (multiplier == __this_cpu_read(current_tsc_ratio))
569 wrmsrl(MSR_AMD64_TSC_RATIO, multiplier);
570 __this_cpu_write(current_tsc_ratio, multiplier);
575 static void svm_hardware_disable(void)
577 /* Make sure we clean up behind us */
579 __svm_write_tsc_multiplier(SVM_TSC_RATIO_DEFAULT);
583 amd_pmu_disable_virt();
586 static int svm_hardware_enable(void)
589 struct svm_cpu_data *sd;
591 struct desc_struct *gdt;
592 int me = raw_smp_processor_id();
594 rdmsrl(MSR_EFER, efer);
595 if (efer & EFER_SVME)
598 sd = per_cpu_ptr(&svm_data, me);
599 sd->asid_generation = 1;
600 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
601 sd->next_asid = sd->max_asid + 1;
602 sd->min_asid = max_sev_asid + 1;
604 gdt = get_current_gdt_rw();
605 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
607 wrmsrl(MSR_EFER, efer | EFER_SVME);
609 wrmsrl(MSR_VM_HSAVE_PA, sd->save_area_pa);
611 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
613 * Set the default value, even if we don't use TSC scaling
614 * to avoid having stale value in the msr
616 __svm_write_tsc_multiplier(SVM_TSC_RATIO_DEFAULT);
623 * Note that it is possible to have a system with mixed processor
624 * revisions and therefore different OSVW bits. If bits are not the same
625 * on different processors then choose the worst case (i.e. if erratum
626 * is present on one processor and not on another then assume that the
627 * erratum is present everywhere).
629 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
630 uint64_t len, status = 0;
633 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
635 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
639 osvw_status = osvw_len = 0;
643 osvw_status |= status;
644 osvw_status &= (1ULL << osvw_len) - 1;
647 osvw_status = osvw_len = 0;
649 svm_init_erratum_383();
651 amd_pmu_enable_virt();
656 static void svm_cpu_uninit(int cpu)
658 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu);
663 kfree(sd->sev_vmcbs);
664 __free_page(sd->save_area);
665 sd->save_area_pa = 0;
666 sd->save_area = NULL;
669 static int svm_cpu_init(int cpu)
671 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu);
674 memset(sd, 0, sizeof(struct svm_cpu_data));
675 sd->save_area = alloc_page(GFP_KERNEL | __GFP_ZERO);
679 ret = sev_cpu_init(sd);
683 sd->save_area_pa = __sme_page_pa(sd->save_area);
687 __free_page(sd->save_area);
688 sd->save_area = NULL;
693 static int direct_access_msr_slot(u32 msr)
697 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
698 if (direct_access_msrs[i].index == msr)
704 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
707 struct vcpu_svm *svm = to_svm(vcpu);
708 int slot = direct_access_msr_slot(msr);
713 /* Set the shadow bitmaps to the desired intercept states */
715 set_bit(slot, svm->shadow_msr_intercept.read);
717 clear_bit(slot, svm->shadow_msr_intercept.read);
720 set_bit(slot, svm->shadow_msr_intercept.write);
722 clear_bit(slot, svm->shadow_msr_intercept.write);
725 static bool valid_msr_intercept(u32 index)
727 return direct_access_msr_slot(index) != -ENOENT;
730 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
738 * For non-nested case:
739 * If the L01 MSR bitmap does not intercept the MSR, then we need to
743 * If the L02 MSR bitmap does not intercept the MSR, then we need to
746 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
749 offset = svm_msrpm_offset(msr);
750 bit_write = 2 * (msr & 0x0f) + 1;
753 BUG_ON(offset == MSR_INVALID);
755 return test_bit(bit_write, &tmp);
758 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
759 u32 msr, int read, int write)
761 struct vcpu_svm *svm = to_svm(vcpu);
762 u8 bit_read, bit_write;
767 * If this warning triggers extend the direct_access_msrs list at the
768 * beginning of the file
770 WARN_ON(!valid_msr_intercept(msr));
772 /* Enforce non allowed MSRs to trap */
773 if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
776 if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
779 offset = svm_msrpm_offset(msr);
780 bit_read = 2 * (msr & 0x0f);
781 bit_write = 2 * (msr & 0x0f) + 1;
784 BUG_ON(offset == MSR_INVALID);
786 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
787 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
791 svm_hv_vmcb_dirty_nested_enlightenments(vcpu);
792 svm->nested.force_msr_bitmap_recalc = true;
795 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
798 set_shadow_msr_intercept(vcpu, msr, read, write);
799 set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
802 u32 *svm_vcpu_alloc_msrpm(void)
804 unsigned int order = get_order(MSRPM_SIZE);
805 struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, order);
811 msrpm = page_address(pages);
812 memset(msrpm, 0xff, PAGE_SIZE * (1 << order));
817 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
821 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
822 if (!direct_access_msrs[i].always)
824 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
828 void svm_set_x2apic_msr_interception(struct vcpu_svm *svm, bool intercept)
832 if (intercept == svm->x2avic_msrs_intercepted)
835 if (!x2avic_enabled ||
836 !apic_x2apic_mode(svm->vcpu.arch.apic))
839 for (i = 0; i < MAX_DIRECT_ACCESS_MSRS; i++) {
840 int index = direct_access_msrs[i].index;
842 if ((index < APIC_BASE_MSR) ||
843 (index > APIC_BASE_MSR + 0xff))
845 set_msr_interception(&svm->vcpu, svm->msrpm, index,
846 !intercept, !intercept);
849 svm->x2avic_msrs_intercepted = intercept;
852 void svm_vcpu_free_msrpm(u32 *msrpm)
854 __free_pages(virt_to_page(msrpm), get_order(MSRPM_SIZE));
857 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
859 struct vcpu_svm *svm = to_svm(vcpu);
863 * Set intercept permissions for all direct access MSRs again. They
864 * will automatically get filtered through the MSR filter, so we are
865 * back in sync after this.
867 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
868 u32 msr = direct_access_msrs[i].index;
869 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
870 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
872 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
876 static void add_msr_offset(u32 offset)
880 for (i = 0; i < MSRPM_OFFSETS; ++i) {
882 /* Offset already in list? */
883 if (msrpm_offsets[i] == offset)
886 /* Slot used by another offset? */
887 if (msrpm_offsets[i] != MSR_INVALID)
890 /* Add offset to list */
891 msrpm_offsets[i] = offset;
897 * If this BUG triggers the msrpm_offsets table has an overflow. Just
898 * increase MSRPM_OFFSETS in this case.
903 static void init_msrpm_offsets(void)
907 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
909 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
912 offset = svm_msrpm_offset(direct_access_msrs[i].index);
913 BUG_ON(offset == MSR_INVALID);
915 add_msr_offset(offset);
919 void svm_copy_lbrs(struct vmcb *to_vmcb, struct vmcb *from_vmcb)
921 to_vmcb->save.dbgctl = from_vmcb->save.dbgctl;
922 to_vmcb->save.br_from = from_vmcb->save.br_from;
923 to_vmcb->save.br_to = from_vmcb->save.br_to;
924 to_vmcb->save.last_excp_from = from_vmcb->save.last_excp_from;
925 to_vmcb->save.last_excp_to = from_vmcb->save.last_excp_to;
927 vmcb_mark_dirty(to_vmcb, VMCB_LBR);
930 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
932 struct vcpu_svm *svm = to_svm(vcpu);
934 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
935 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
936 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
937 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
938 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
940 /* Move the LBR msrs to the vmcb02 so that the guest can see them. */
941 if (is_guest_mode(vcpu))
942 svm_copy_lbrs(svm->vmcb, svm->vmcb01.ptr);
945 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
947 struct vcpu_svm *svm = to_svm(vcpu);
949 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
950 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
951 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
952 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
953 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
956 * Move the LBR msrs back to the vmcb01 to avoid copying them
957 * on nested guest entries.
959 if (is_guest_mode(vcpu))
960 svm_copy_lbrs(svm->vmcb01.ptr, svm->vmcb);
963 static int svm_get_lbr_msr(struct vcpu_svm *svm, u32 index)
966 * If the LBR virtualization is disabled, the LBR msrs are always
967 * kept in the vmcb01 to avoid copying them on nested guest entries.
969 * If nested, and the LBR virtualization is enabled/disabled, the msrs
970 * are moved between the vmcb01 and vmcb02 as needed.
973 (svm->vmcb->control.virt_ext & LBR_CTL_ENABLE_MASK) ?
974 svm->vmcb : svm->vmcb01.ptr;
977 case MSR_IA32_DEBUGCTLMSR:
978 return vmcb->save.dbgctl;
979 case MSR_IA32_LASTBRANCHFROMIP:
980 return vmcb->save.br_from;
981 case MSR_IA32_LASTBRANCHTOIP:
982 return vmcb->save.br_to;
983 case MSR_IA32_LASTINTFROMIP:
984 return vmcb->save.last_excp_from;
985 case MSR_IA32_LASTINTTOIP:
986 return vmcb->save.last_excp_to;
988 KVM_BUG(false, svm->vcpu.kvm,
989 "%s: Unknown MSR 0x%x", __func__, index);
994 void svm_update_lbrv(struct kvm_vcpu *vcpu)
996 struct vcpu_svm *svm = to_svm(vcpu);
998 bool enable_lbrv = svm_get_lbr_msr(svm, MSR_IA32_DEBUGCTLMSR) &
1001 bool current_enable_lbrv = !!(svm->vmcb->control.virt_ext &
1002 LBR_CTL_ENABLE_MASK);
1004 if (unlikely(is_guest_mode(vcpu) && svm->lbrv_enabled))
1005 if (unlikely(svm->nested.ctl.virt_ext & LBR_CTL_ENABLE_MASK))
1008 if (enable_lbrv == current_enable_lbrv)
1012 svm_enable_lbrv(vcpu);
1014 svm_disable_lbrv(vcpu);
1017 void disable_nmi_singlestep(struct vcpu_svm *svm)
1019 svm->nmi_singlestep = false;
1021 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1022 /* Clear our flags if they were not set by the guest */
1023 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1024 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1025 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1026 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1030 static void grow_ple_window(struct kvm_vcpu *vcpu)
1032 struct vcpu_svm *svm = to_svm(vcpu);
1033 struct vmcb_control_area *control = &svm->vmcb->control;
1034 int old = control->pause_filter_count;
1036 if (kvm_pause_in_guest(vcpu->kvm))
1039 control->pause_filter_count = __grow_ple_window(old,
1041 pause_filter_count_grow,
1042 pause_filter_count_max);
1044 if (control->pause_filter_count != old) {
1045 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1046 trace_kvm_ple_window_update(vcpu->vcpu_id,
1047 control->pause_filter_count, old);
1051 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1053 struct vcpu_svm *svm = to_svm(vcpu);
1054 struct vmcb_control_area *control = &svm->vmcb->control;
1055 int old = control->pause_filter_count;
1057 if (kvm_pause_in_guest(vcpu->kvm))
1060 control->pause_filter_count =
1061 __shrink_ple_window(old,
1063 pause_filter_count_shrink,
1064 pause_filter_count);
1065 if (control->pause_filter_count != old) {
1066 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1067 trace_kvm_ple_window_update(vcpu->vcpu_id,
1068 control->pause_filter_count, old);
1072 static void svm_hardware_unsetup(void)
1076 sev_hardware_unsetup();
1078 for_each_possible_cpu(cpu)
1079 svm_cpu_uninit(cpu);
1081 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT),
1082 get_order(IOPM_SIZE));
1086 static void init_seg(struct vmcb_seg *seg)
1089 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1090 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1091 seg->limit = 0xffff;
1095 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1098 seg->attrib = SVM_SELECTOR_P_MASK | type;
1099 seg->limit = 0xffff;
1103 static u64 svm_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1105 struct vcpu_svm *svm = to_svm(vcpu);
1107 return svm->nested.ctl.tsc_offset;
1110 static u64 svm_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1112 struct vcpu_svm *svm = to_svm(vcpu);
1114 return svm->tsc_ratio_msr;
1117 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1119 struct vcpu_svm *svm = to_svm(vcpu);
1121 svm->vmcb01.ptr->control.tsc_offset = vcpu->arch.l1_tsc_offset;
1122 svm->vmcb->control.tsc_offset = offset;
1123 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1126 static void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1128 __svm_write_tsc_multiplier(multiplier);
1132 /* Evaluate instruction intercepts that depend on guest CPUID features. */
1133 static void svm_recalc_instruction_intercepts(struct kvm_vcpu *vcpu,
1134 struct vcpu_svm *svm)
1137 * Intercept INVPCID if shadow paging is enabled to sync/free shadow
1138 * roots, or if INVPCID is disabled in the guest to inject #UD.
1140 if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1142 !guest_cpuid_has(&svm->vcpu, X86_FEATURE_INVPCID))
1143 svm_set_intercept(svm, INTERCEPT_INVPCID);
1145 svm_clr_intercept(svm, INTERCEPT_INVPCID);
1148 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) {
1149 if (guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1150 svm_clr_intercept(svm, INTERCEPT_RDTSCP);
1152 svm_set_intercept(svm, INTERCEPT_RDTSCP);
1156 static inline void init_vmcb_after_set_cpuid(struct kvm_vcpu *vcpu)
1158 struct vcpu_svm *svm = to_svm(vcpu);
1160 if (guest_cpuid_is_intel(vcpu)) {
1162 * We must intercept SYSENTER_EIP and SYSENTER_ESP
1163 * accesses because the processor only stores 32 bits.
1164 * For the same reason we cannot use virtual VMLOAD/VMSAVE.
1166 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1167 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1168 svm->vmcb->control.virt_ext &= ~VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1170 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 0, 0);
1171 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 0, 0);
1173 svm->v_vmload_vmsave_enabled = false;
1176 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1177 * in VMCB and clear intercepts to avoid #VMEXIT.
1180 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1181 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
1182 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1184 /* No need to intercept these MSRs */
1185 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
1186 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
1190 static void init_vmcb(struct kvm_vcpu *vcpu)
1192 struct vcpu_svm *svm = to_svm(vcpu);
1193 struct vmcb *vmcb = svm->vmcb01.ptr;
1194 struct vmcb_control_area *control = &vmcb->control;
1195 struct vmcb_save_area *save = &vmcb->save;
1197 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1198 svm_set_intercept(svm, INTERCEPT_CR3_READ);
1199 svm_set_intercept(svm, INTERCEPT_CR4_READ);
1200 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1201 svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1202 svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1203 if (!kvm_vcpu_apicv_active(vcpu))
1204 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1206 set_dr_intercepts(svm);
1208 set_exception_intercept(svm, PF_VECTOR);
1209 set_exception_intercept(svm, UD_VECTOR);
1210 set_exception_intercept(svm, MC_VECTOR);
1211 set_exception_intercept(svm, AC_VECTOR);
1212 set_exception_intercept(svm, DB_VECTOR);
1214 * Guest access to VMware backdoor ports could legitimately
1215 * trigger #GP because of TSS I/O permission bitmap.
1216 * We intercept those #GP and allow access to them anyway
1217 * as VMware does. Don't intercept #GP for SEV guests as KVM can't
1218 * decrypt guest memory to decode the faulting instruction.
1220 if (enable_vmware_backdoor && !sev_guest(vcpu->kvm))
1221 set_exception_intercept(svm, GP_VECTOR);
1223 svm_set_intercept(svm, INTERCEPT_INTR);
1224 svm_set_intercept(svm, INTERCEPT_NMI);
1227 svm_set_intercept(svm, INTERCEPT_SMI);
1229 svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1230 svm_set_intercept(svm, INTERCEPT_RDPMC);
1231 svm_set_intercept(svm, INTERCEPT_CPUID);
1232 svm_set_intercept(svm, INTERCEPT_INVD);
1233 svm_set_intercept(svm, INTERCEPT_INVLPG);
1234 svm_set_intercept(svm, INTERCEPT_INVLPGA);
1235 svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1236 svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1237 svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1238 svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1239 svm_set_intercept(svm, INTERCEPT_VMRUN);
1240 svm_set_intercept(svm, INTERCEPT_VMMCALL);
1241 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1242 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1243 svm_set_intercept(svm, INTERCEPT_STGI);
1244 svm_set_intercept(svm, INTERCEPT_CLGI);
1245 svm_set_intercept(svm, INTERCEPT_SKINIT);
1246 svm_set_intercept(svm, INTERCEPT_WBINVD);
1247 svm_set_intercept(svm, INTERCEPT_XSETBV);
1248 svm_set_intercept(svm, INTERCEPT_RDPRU);
1249 svm_set_intercept(svm, INTERCEPT_RSM);
1251 if (!kvm_mwait_in_guest(vcpu->kvm)) {
1252 svm_set_intercept(svm, INTERCEPT_MONITOR);
1253 svm_set_intercept(svm, INTERCEPT_MWAIT);
1256 if (!kvm_hlt_in_guest(vcpu->kvm))
1257 svm_set_intercept(svm, INTERCEPT_HLT);
1259 control->iopm_base_pa = __sme_set(iopm_base);
1260 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1261 control->int_ctl = V_INTR_MASKING_MASK;
1263 init_seg(&save->es);
1264 init_seg(&save->ss);
1265 init_seg(&save->ds);
1266 init_seg(&save->fs);
1267 init_seg(&save->gs);
1269 save->cs.selector = 0xf000;
1270 save->cs.base = 0xffff0000;
1271 /* Executable/Readable Code Segment */
1272 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1273 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1274 save->cs.limit = 0xffff;
1276 save->gdtr.base = 0;
1277 save->gdtr.limit = 0xffff;
1278 save->idtr.base = 0;
1279 save->idtr.limit = 0xffff;
1281 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1282 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1285 /* Setup VMCB for Nested Paging */
1286 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1287 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1288 clr_exception_intercept(svm, PF_VECTOR);
1289 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1290 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1291 save->g_pat = vcpu->arch.pat;
1294 svm->current_vmcb->asid_generation = 0;
1297 svm->nested.vmcb12_gpa = INVALID_GPA;
1298 svm->nested.last_vmcb12_gpa = INVALID_GPA;
1300 if (!kvm_pause_in_guest(vcpu->kvm)) {
1301 control->pause_filter_count = pause_filter_count;
1302 if (pause_filter_thresh)
1303 control->pause_filter_thresh = pause_filter_thresh;
1304 svm_set_intercept(svm, INTERCEPT_PAUSE);
1306 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1309 svm_recalc_instruction_intercepts(vcpu, svm);
1312 * If the host supports V_SPEC_CTRL then disable the interception
1313 * of MSR_IA32_SPEC_CTRL.
1315 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
1316 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
1318 if (kvm_vcpu_apicv_active(vcpu))
1319 avic_init_vmcb(svm, vmcb);
1322 svm->vmcb->control.int_ctl |= V_NMI_ENABLE_MASK;
1325 svm_clr_intercept(svm, INTERCEPT_STGI);
1326 svm_clr_intercept(svm, INTERCEPT_CLGI);
1327 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1330 if (sev_guest(vcpu->kvm))
1333 svm_hv_init_vmcb(vmcb);
1334 init_vmcb_after_set_cpuid(vcpu);
1336 vmcb_mark_all_dirty(vmcb);
1341 static void __svm_vcpu_reset(struct kvm_vcpu *vcpu)
1343 struct vcpu_svm *svm = to_svm(vcpu);
1345 svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1347 svm_init_osvw(vcpu);
1348 vcpu->arch.microcode_version = 0x01000065;
1349 svm->tsc_ratio_msr = kvm_caps.default_tsc_scaling_ratio;
1351 svm->nmi_masked = false;
1352 svm->awaiting_iret_completion = false;
1354 if (sev_es_guest(vcpu->kvm))
1355 sev_es_vcpu_reset(svm);
1358 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1360 struct vcpu_svm *svm = to_svm(vcpu);
1363 svm->virt_spec_ctrl = 0;
1368 __svm_vcpu_reset(vcpu);
1371 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb)
1373 svm->current_vmcb = target_vmcb;
1374 svm->vmcb = target_vmcb->ptr;
1377 static int svm_vcpu_create(struct kvm_vcpu *vcpu)
1379 struct vcpu_svm *svm;
1380 struct page *vmcb01_page;
1381 struct page *vmsa_page = NULL;
1384 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1388 vmcb01_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1392 if (sev_es_guest(vcpu->kvm)) {
1394 * SEV-ES guests require a separate VMSA page used to contain
1395 * the encrypted register state of the guest.
1397 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1399 goto error_free_vmcb_page;
1402 * SEV-ES guests maintain an encrypted version of their FPU
1403 * state which is restored and saved on VMRUN and VMEXIT.
1404 * Mark vcpu->arch.guest_fpu->fpstate as scratch so it won't
1405 * do xsave/xrstor on it.
1407 fpstate_set_confidential(&vcpu->arch.guest_fpu);
1410 err = avic_init_vcpu(svm);
1412 goto error_free_vmsa_page;
1414 svm->msrpm = svm_vcpu_alloc_msrpm();
1417 goto error_free_vmsa_page;
1420 svm->x2avic_msrs_intercepted = true;
1422 svm->vmcb01.ptr = page_address(vmcb01_page);
1423 svm->vmcb01.pa = __sme_set(page_to_pfn(vmcb01_page) << PAGE_SHIFT);
1424 svm_switch_vmcb(svm, &svm->vmcb01);
1427 svm->sev_es.vmsa = page_address(vmsa_page);
1429 svm->guest_state_loaded = false;
1433 error_free_vmsa_page:
1435 __free_page(vmsa_page);
1436 error_free_vmcb_page:
1437 __free_page(vmcb01_page);
1442 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1446 for_each_online_cpu(i)
1447 cmpxchg(per_cpu_ptr(&svm_data.current_vmcb, i), vmcb, NULL);
1450 static void svm_vcpu_free(struct kvm_vcpu *vcpu)
1452 struct vcpu_svm *svm = to_svm(vcpu);
1455 * The vmcb page can be recycled, causing a false negative in
1456 * svm_vcpu_load(). So, ensure that no logical CPU has this
1457 * vmcb page recorded as its current vmcb.
1459 svm_clear_current_vmcb(svm->vmcb);
1461 svm_leave_nested(vcpu);
1462 svm_free_nested(svm);
1464 sev_free_vcpu(vcpu);
1466 __free_page(pfn_to_page(__sme_clr(svm->vmcb01.pa) >> PAGE_SHIFT));
1467 __free_pages(virt_to_page(svm->msrpm), get_order(MSRPM_SIZE));
1470 static void svm_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1472 struct vcpu_svm *svm = to_svm(vcpu);
1473 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, vcpu->cpu);
1475 if (sev_es_guest(vcpu->kvm))
1476 sev_es_unmap_ghcb(svm);
1478 if (svm->guest_state_loaded)
1482 * Save additional host state that will be restored on VMEXIT (sev-es)
1483 * or subsequent vmload of host save area.
1485 vmsave(sd->save_area_pa);
1486 if (sev_es_guest(vcpu->kvm)) {
1487 struct sev_es_save_area *hostsa;
1488 hostsa = (struct sev_es_save_area *)(page_address(sd->save_area) + 0x400);
1490 sev_es_prepare_switch_to_guest(hostsa);
1494 __svm_write_tsc_multiplier(vcpu->arch.tsc_scaling_ratio);
1496 if (likely(tsc_aux_uret_slot >= 0))
1497 kvm_set_user_return_msr(tsc_aux_uret_slot, svm->tsc_aux, -1ull);
1499 svm->guest_state_loaded = true;
1502 static void svm_prepare_host_switch(struct kvm_vcpu *vcpu)
1504 to_svm(vcpu)->guest_state_loaded = false;
1507 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1509 struct vcpu_svm *svm = to_svm(vcpu);
1510 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu);
1512 if (sd->current_vmcb != svm->vmcb) {
1513 sd->current_vmcb = svm->vmcb;
1514 indirect_branch_prediction_barrier();
1516 if (kvm_vcpu_apicv_active(vcpu))
1517 avic_vcpu_load(vcpu, cpu);
1520 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1522 if (kvm_vcpu_apicv_active(vcpu))
1523 avic_vcpu_put(vcpu);
1525 svm_prepare_host_switch(vcpu);
1527 ++vcpu->stat.host_state_reload;
1530 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1532 struct vcpu_svm *svm = to_svm(vcpu);
1533 unsigned long rflags = svm->vmcb->save.rflags;
1535 if (svm->nmi_singlestep) {
1536 /* Hide our flags if they were not set by the guest */
1537 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1538 rflags &= ~X86_EFLAGS_TF;
1539 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1540 rflags &= ~X86_EFLAGS_RF;
1545 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1547 if (to_svm(vcpu)->nmi_singlestep)
1548 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1551 * Any change of EFLAGS.VM is accompanied by a reload of SS
1552 * (caused by either a task switch or an inter-privilege IRET),
1553 * so we do not need to update the CPL here.
1555 to_svm(vcpu)->vmcb->save.rflags = rflags;
1558 static bool svm_get_if_flag(struct kvm_vcpu *vcpu)
1560 struct vmcb *vmcb = to_svm(vcpu)->vmcb;
1562 return sev_es_guest(vcpu->kvm)
1563 ? vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK
1564 : kvm_get_rflags(vcpu) & X86_EFLAGS_IF;
1567 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1569 kvm_register_mark_available(vcpu, reg);
1572 case VCPU_EXREG_PDPTR:
1574 * When !npt_enabled, mmu->pdptrs[] is already available since
1575 * it is always updated per SDM when moving to CRs.
1578 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
1581 KVM_BUG_ON(1, vcpu->kvm);
1585 static void svm_set_vintr(struct vcpu_svm *svm)
1587 struct vmcb_control_area *control;
1590 * The following fields are ignored when AVIC is enabled
1592 WARN_ON(kvm_vcpu_apicv_activated(&svm->vcpu));
1594 svm_set_intercept(svm, INTERCEPT_VINTR);
1597 * Recalculating intercepts may have cleared the VINTR intercept. If
1598 * V_INTR_MASKING is enabled in vmcb12, then the effective RFLAGS.IF
1599 * for L1 physical interrupts is L1's RFLAGS.IF at the time of VMRUN.
1600 * Requesting an interrupt window if save.RFLAGS.IF=0 is pointless as
1601 * interrupts will never be unblocked while L2 is running.
1603 if (!svm_is_intercept(svm, INTERCEPT_VINTR))
1607 * This is just a dummy VINTR to actually cause a vmexit to happen.
1608 * Actual injection of virtual interrupts happens through EVENTINJ.
1610 control = &svm->vmcb->control;
1611 control->int_vector = 0x0;
1612 control->int_ctl &= ~V_INTR_PRIO_MASK;
1613 control->int_ctl |= V_IRQ_MASK |
1614 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1615 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1618 static void svm_clear_vintr(struct vcpu_svm *svm)
1620 svm_clr_intercept(svm, INTERCEPT_VINTR);
1622 /* Drop int_ctl fields related to VINTR injection. */
1623 svm->vmcb->control.int_ctl &= ~V_IRQ_INJECTION_BITS_MASK;
1624 if (is_guest_mode(&svm->vcpu)) {
1625 svm->vmcb01.ptr->control.int_ctl &= ~V_IRQ_INJECTION_BITS_MASK;
1627 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1628 (svm->nested.ctl.int_ctl & V_TPR_MASK));
1630 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl &
1631 V_IRQ_INJECTION_BITS_MASK;
1633 svm->vmcb->control.int_vector = svm->nested.ctl.int_vector;
1636 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1639 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1641 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1642 struct vmcb_save_area *save01 = &to_svm(vcpu)->vmcb01.ptr->save;
1645 case VCPU_SREG_CS: return &save->cs;
1646 case VCPU_SREG_DS: return &save->ds;
1647 case VCPU_SREG_ES: return &save->es;
1648 case VCPU_SREG_FS: return &save01->fs;
1649 case VCPU_SREG_GS: return &save01->gs;
1650 case VCPU_SREG_SS: return &save->ss;
1651 case VCPU_SREG_TR: return &save01->tr;
1652 case VCPU_SREG_LDTR: return &save01->ldtr;
1658 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1660 struct vmcb_seg *s = svm_seg(vcpu, seg);
1665 static void svm_get_segment(struct kvm_vcpu *vcpu,
1666 struct kvm_segment *var, int seg)
1668 struct vmcb_seg *s = svm_seg(vcpu, seg);
1670 var->base = s->base;
1671 var->limit = s->limit;
1672 var->selector = s->selector;
1673 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1674 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1675 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1676 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1677 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1678 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1679 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1682 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1683 * However, the SVM spec states that the G bit is not observed by the
1684 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1685 * So let's synthesize a legal G bit for all segments, this helps
1686 * running KVM nested. It also helps cross-vendor migration, because
1687 * Intel's vmentry has a check on the 'G' bit.
1689 var->g = s->limit > 0xfffff;
1692 * AMD's VMCB does not have an explicit unusable field, so emulate it
1693 * for cross vendor migration purposes by "not present"
1695 var->unusable = !var->present;
1700 * Work around a bug where the busy flag in the tr selector
1710 * The accessed bit must always be set in the segment
1711 * descriptor cache, although it can be cleared in the
1712 * descriptor, the cached bit always remains at 1. Since
1713 * Intel has a check on this, set it here to support
1714 * cross-vendor migration.
1721 * On AMD CPUs sometimes the DB bit in the segment
1722 * descriptor is left as 1, although the whole segment has
1723 * been made unusable. Clear it here to pass an Intel VMX
1724 * entry check when cross vendor migrating.
1728 /* This is symmetric with svm_set_segment() */
1729 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1734 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1736 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1741 static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1743 struct kvm_segment cs;
1745 svm_get_segment(vcpu, &cs, VCPU_SREG_CS);
1750 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1752 struct vcpu_svm *svm = to_svm(vcpu);
1754 dt->size = svm->vmcb->save.idtr.limit;
1755 dt->address = svm->vmcb->save.idtr.base;
1758 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1760 struct vcpu_svm *svm = to_svm(vcpu);
1762 svm->vmcb->save.idtr.limit = dt->size;
1763 svm->vmcb->save.idtr.base = dt->address ;
1764 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1767 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1769 struct vcpu_svm *svm = to_svm(vcpu);
1771 dt->size = svm->vmcb->save.gdtr.limit;
1772 dt->address = svm->vmcb->save.gdtr.base;
1775 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1777 struct vcpu_svm *svm = to_svm(vcpu);
1779 svm->vmcb->save.gdtr.limit = dt->size;
1780 svm->vmcb->save.gdtr.base = dt->address ;
1781 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1784 static void sev_post_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1786 struct vcpu_svm *svm = to_svm(vcpu);
1789 * For guests that don't set guest_state_protected, the cr3 update is
1790 * handled via kvm_mmu_load() while entering the guest. For guests
1791 * that do (SEV-ES/SEV-SNP), the cr3 update needs to be written to
1792 * VMCB save area now, since the save area will become the initial
1793 * contents of the VMSA, and future VMCB save area updates won't be
1796 if (sev_es_guest(vcpu->kvm)) {
1797 svm->vmcb->save.cr3 = cr3;
1798 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1802 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1804 struct vcpu_svm *svm = to_svm(vcpu);
1806 bool old_paging = is_paging(vcpu);
1808 #ifdef CONFIG_X86_64
1809 if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1810 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1811 vcpu->arch.efer |= EFER_LMA;
1812 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1815 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1816 vcpu->arch.efer &= ~EFER_LMA;
1817 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1821 vcpu->arch.cr0 = cr0;
1824 hcr0 |= X86_CR0_PG | X86_CR0_WP;
1825 if (old_paging != is_paging(vcpu))
1826 svm_set_cr4(vcpu, kvm_read_cr4(vcpu));
1830 * re-enable caching here because the QEMU bios
1831 * does not do it - this results in some delay at
1834 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1835 hcr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1837 svm->vmcb->save.cr0 = hcr0;
1838 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1841 * SEV-ES guests must always keep the CR intercepts cleared. CR
1842 * tracking is done using the CR write traps.
1844 if (sev_es_guest(vcpu->kvm))
1848 /* Selective CR0 write remains on. */
1849 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1850 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1852 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1853 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1857 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1862 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1864 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1865 unsigned long old_cr4 = vcpu->arch.cr4;
1867 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1868 svm_flush_tlb_current(vcpu);
1870 vcpu->arch.cr4 = cr4;
1874 if (!is_paging(vcpu))
1875 cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
1877 cr4 |= host_cr4_mce;
1878 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1879 vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1881 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1882 kvm_update_cpuid_runtime(vcpu);
1885 static void svm_set_segment(struct kvm_vcpu *vcpu,
1886 struct kvm_segment *var, int seg)
1888 struct vcpu_svm *svm = to_svm(vcpu);
1889 struct vmcb_seg *s = svm_seg(vcpu, seg);
1891 s->base = var->base;
1892 s->limit = var->limit;
1893 s->selector = var->selector;
1894 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1895 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1896 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1897 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1898 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1899 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1900 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1901 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1904 * This is always accurate, except if SYSRET returned to a segment
1905 * with SS.DPL != 3. Intel does not have this quirk, and always
1906 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1907 * would entail passing the CPL to userspace and back.
1909 if (seg == VCPU_SREG_SS)
1910 /* This is symmetric with svm_get_segment() */
1911 svm->vmcb->save.cpl = (var->dpl & 3);
1913 vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1916 static void svm_update_exception_bitmap(struct kvm_vcpu *vcpu)
1918 struct vcpu_svm *svm = to_svm(vcpu);
1920 clr_exception_intercept(svm, BP_VECTOR);
1922 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1923 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1924 set_exception_intercept(svm, BP_VECTOR);
1928 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1930 if (sd->next_asid > sd->max_asid) {
1931 ++sd->asid_generation;
1932 sd->next_asid = sd->min_asid;
1933 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1934 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1937 svm->current_vmcb->asid_generation = sd->asid_generation;
1938 svm->asid = sd->next_asid++;
1941 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1943 struct vmcb *vmcb = svm->vmcb;
1945 if (svm->vcpu.arch.guest_state_protected)
1948 if (unlikely(value != vmcb->save.dr6)) {
1949 vmcb->save.dr6 = value;
1950 vmcb_mark_dirty(vmcb, VMCB_DR);
1954 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1956 struct vcpu_svm *svm = to_svm(vcpu);
1958 if (vcpu->arch.guest_state_protected)
1961 get_debugreg(vcpu->arch.db[0], 0);
1962 get_debugreg(vcpu->arch.db[1], 1);
1963 get_debugreg(vcpu->arch.db[2], 2);
1964 get_debugreg(vcpu->arch.db[3], 3);
1966 * We cannot reset svm->vmcb->save.dr6 to DR6_ACTIVE_LOW here,
1967 * because db_interception might need it. We can do it before vmentry.
1969 vcpu->arch.dr6 = svm->vmcb->save.dr6;
1970 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1971 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1972 set_dr_intercepts(svm);
1975 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1977 struct vcpu_svm *svm = to_svm(vcpu);
1979 if (vcpu->arch.guest_state_protected)
1982 svm->vmcb->save.dr7 = value;
1983 vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1986 static int pf_interception(struct kvm_vcpu *vcpu)
1988 struct vcpu_svm *svm = to_svm(vcpu);
1990 u64 fault_address = svm->vmcb->control.exit_info_2;
1991 u64 error_code = svm->vmcb->control.exit_info_1;
1993 return kvm_handle_page_fault(vcpu, error_code, fault_address,
1994 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1995 svm->vmcb->control.insn_bytes : NULL,
1996 svm->vmcb->control.insn_len);
1999 static int npf_interception(struct kvm_vcpu *vcpu)
2001 struct vcpu_svm *svm = to_svm(vcpu);
2003 u64 fault_address = svm->vmcb->control.exit_info_2;
2004 u64 error_code = svm->vmcb->control.exit_info_1;
2006 trace_kvm_page_fault(vcpu, fault_address, error_code);
2007 return kvm_mmu_page_fault(vcpu, fault_address, error_code,
2008 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2009 svm->vmcb->control.insn_bytes : NULL,
2010 svm->vmcb->control.insn_len);
2013 static int db_interception(struct kvm_vcpu *vcpu)
2015 struct kvm_run *kvm_run = vcpu->run;
2016 struct vcpu_svm *svm = to_svm(vcpu);
2018 if (!(vcpu->guest_debug &
2019 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2020 !svm->nmi_singlestep) {
2021 u32 payload = svm->vmcb->save.dr6 ^ DR6_ACTIVE_LOW;
2022 kvm_queue_exception_p(vcpu, DB_VECTOR, payload);
2026 if (svm->nmi_singlestep) {
2027 disable_nmi_singlestep(svm);
2028 /* Make sure we check for pending NMIs upon entry */
2029 kvm_make_request(KVM_REQ_EVENT, vcpu);
2032 if (vcpu->guest_debug &
2033 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2034 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2035 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
2036 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
2037 kvm_run->debug.arch.pc =
2038 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2039 kvm_run->debug.arch.exception = DB_VECTOR;
2046 static int bp_interception(struct kvm_vcpu *vcpu)
2048 struct vcpu_svm *svm = to_svm(vcpu);
2049 struct kvm_run *kvm_run = vcpu->run;
2051 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2052 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2053 kvm_run->debug.arch.exception = BP_VECTOR;
2057 static int ud_interception(struct kvm_vcpu *vcpu)
2059 return handle_ud(vcpu);
2062 static int ac_interception(struct kvm_vcpu *vcpu)
2064 kvm_queue_exception_e(vcpu, AC_VECTOR, 0);
2068 static bool is_erratum_383(void)
2073 if (!erratum_383_found)
2076 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2080 /* Bit 62 may or may not be set for this mce */
2081 value &= ~(1ULL << 62);
2083 if (value != 0xb600000000010015ULL)
2086 /* Clear MCi_STATUS registers */
2087 for (i = 0; i < 6; ++i)
2088 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2090 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2094 value &= ~(1ULL << 2);
2095 low = lower_32_bits(value);
2096 high = upper_32_bits(value);
2098 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2101 /* Flush tlb to evict multi-match entries */
2107 static void svm_handle_mce(struct kvm_vcpu *vcpu)
2109 if (is_erratum_383()) {
2111 * Erratum 383 triggered. Guest state is corrupt so kill the
2114 pr_err("Guest triggered AMD Erratum 383\n");
2116 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2122 * On an #MC intercept the MCE handler is not called automatically in
2123 * the host. So do it by hand here.
2125 kvm_machine_check();
2128 static int mc_interception(struct kvm_vcpu *vcpu)
2133 static int shutdown_interception(struct kvm_vcpu *vcpu)
2135 struct kvm_run *kvm_run = vcpu->run;
2136 struct vcpu_svm *svm = to_svm(vcpu);
2139 * The VM save area has already been encrypted so it
2140 * cannot be reinitialized - just terminate.
2142 if (sev_es_guest(vcpu->kvm))
2146 * VMCB is undefined after a SHUTDOWN intercept. INIT the vCPU to put
2147 * the VMCB in a known good state. Unfortuately, KVM doesn't have
2148 * KVM_MP_STATE_SHUTDOWN and can't add it without potentially breaking
2149 * userspace. At a platform view, INIT is acceptable behavior as
2150 * there exist bare metal platforms that automatically INIT the CPU
2151 * in response to shutdown.
2153 clear_page(svm->vmcb);
2154 kvm_vcpu_reset(vcpu, true);
2156 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2160 static int io_interception(struct kvm_vcpu *vcpu)
2162 struct vcpu_svm *svm = to_svm(vcpu);
2163 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2164 int size, in, string;
2167 ++vcpu->stat.io_exits;
2168 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2169 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2170 port = io_info >> 16;
2171 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2174 if (sev_es_guest(vcpu->kvm))
2175 return sev_es_string_io(svm, size, port, in);
2177 return kvm_emulate_instruction(vcpu, 0);
2180 svm->next_rip = svm->vmcb->control.exit_info_2;
2182 return kvm_fast_pio(vcpu, size, port, in);
2185 static int nmi_interception(struct kvm_vcpu *vcpu)
2190 static int smi_interception(struct kvm_vcpu *vcpu)
2195 static int intr_interception(struct kvm_vcpu *vcpu)
2197 ++vcpu->stat.irq_exits;
2201 static int vmload_vmsave_interception(struct kvm_vcpu *vcpu, bool vmload)
2203 struct vcpu_svm *svm = to_svm(vcpu);
2204 struct vmcb *vmcb12;
2205 struct kvm_host_map map;
2208 if (nested_svm_check_permissions(vcpu))
2211 ret = kvm_vcpu_map(vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2214 kvm_inject_gp(vcpu, 0);
2220 ret = kvm_skip_emulated_instruction(vcpu);
2223 svm_copy_vmloadsave_state(svm->vmcb, vmcb12);
2224 svm->sysenter_eip_hi = 0;
2225 svm->sysenter_esp_hi = 0;
2227 svm_copy_vmloadsave_state(vmcb12, svm->vmcb);
2230 kvm_vcpu_unmap(vcpu, &map, true);
2235 static int vmload_interception(struct kvm_vcpu *vcpu)
2237 return vmload_vmsave_interception(vcpu, true);
2240 static int vmsave_interception(struct kvm_vcpu *vcpu)
2242 return vmload_vmsave_interception(vcpu, false);
2245 static int vmrun_interception(struct kvm_vcpu *vcpu)
2247 if (nested_svm_check_permissions(vcpu))
2250 return nested_svm_vmrun(vcpu);
2260 /* Return NONE_SVM_INSTR if not SVM instrs, otherwise return decode result */
2261 static int svm_instr_opcode(struct kvm_vcpu *vcpu)
2263 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
2265 if (ctxt->b != 0x1 || ctxt->opcode_len != 2)
2266 return NONE_SVM_INSTR;
2268 switch (ctxt->modrm) {
2269 case 0xd8: /* VMRUN */
2270 return SVM_INSTR_VMRUN;
2271 case 0xda: /* VMLOAD */
2272 return SVM_INSTR_VMLOAD;
2273 case 0xdb: /* VMSAVE */
2274 return SVM_INSTR_VMSAVE;
2279 return NONE_SVM_INSTR;
2282 static int emulate_svm_instr(struct kvm_vcpu *vcpu, int opcode)
2284 const int guest_mode_exit_codes[] = {
2285 [SVM_INSTR_VMRUN] = SVM_EXIT_VMRUN,
2286 [SVM_INSTR_VMLOAD] = SVM_EXIT_VMLOAD,
2287 [SVM_INSTR_VMSAVE] = SVM_EXIT_VMSAVE,
2289 int (*const svm_instr_handlers[])(struct kvm_vcpu *vcpu) = {
2290 [SVM_INSTR_VMRUN] = vmrun_interception,
2291 [SVM_INSTR_VMLOAD] = vmload_interception,
2292 [SVM_INSTR_VMSAVE] = vmsave_interception,
2294 struct vcpu_svm *svm = to_svm(vcpu);
2297 if (is_guest_mode(vcpu)) {
2298 /* Returns '1' or -errno on failure, '0' on success. */
2299 ret = nested_svm_simple_vmexit(svm, guest_mode_exit_codes[opcode]);
2304 return svm_instr_handlers[opcode](vcpu);
2308 * #GP handling code. Note that #GP can be triggered under the following two
2310 * 1) SVM VM-related instructions (VMRUN/VMSAVE/VMLOAD) that trigger #GP on
2311 * some AMD CPUs when EAX of these instructions are in the reserved memory
2312 * regions (e.g. SMM memory on host).
2313 * 2) VMware backdoor
2315 static int gp_interception(struct kvm_vcpu *vcpu)
2317 struct vcpu_svm *svm = to_svm(vcpu);
2318 u32 error_code = svm->vmcb->control.exit_info_1;
2321 /* Both #GP cases have zero error_code */
2325 /* Decode the instruction for usage later */
2326 if (x86_decode_emulated_instruction(vcpu, 0, NULL, 0) != EMULATION_OK)
2329 opcode = svm_instr_opcode(vcpu);
2331 if (opcode == NONE_SVM_INSTR) {
2332 if (!enable_vmware_backdoor)
2336 * VMware backdoor emulation on #GP interception only handles
2337 * IN{S}, OUT{S}, and RDPMC.
2339 if (!is_guest_mode(vcpu))
2340 return kvm_emulate_instruction(vcpu,
2341 EMULTYPE_VMWARE_GP | EMULTYPE_NO_DECODE);
2343 /* All SVM instructions expect page aligned RAX */
2344 if (svm->vmcb->save.rax & ~PAGE_MASK)
2347 return emulate_svm_instr(vcpu, opcode);
2351 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2355 void svm_set_gif(struct vcpu_svm *svm, bool value)
2359 * If VGIF is enabled, the STGI intercept is only added to
2360 * detect the opening of the SMI/NMI window; remove it now.
2361 * Likewise, clear the VINTR intercept, we will set it
2362 * again while processing KVM_REQ_EVENT if needed.
2365 svm_clr_intercept(svm, INTERCEPT_STGI);
2366 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2367 svm_clear_vintr(svm);
2370 if (svm->vcpu.arch.smi_pending ||
2371 svm->vcpu.arch.nmi_pending ||
2372 kvm_cpu_has_injectable_intr(&svm->vcpu) ||
2373 kvm_apic_has_pending_init_or_sipi(&svm->vcpu))
2374 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2379 * After a CLGI no interrupts should come. But if vGIF is
2380 * in use, we still rely on the VINTR intercept (rather than
2381 * STGI) to detect an open interrupt window.
2384 svm_clear_vintr(svm);
2388 static int stgi_interception(struct kvm_vcpu *vcpu)
2392 if (nested_svm_check_permissions(vcpu))
2395 ret = kvm_skip_emulated_instruction(vcpu);
2396 svm_set_gif(to_svm(vcpu), true);
2400 static int clgi_interception(struct kvm_vcpu *vcpu)
2404 if (nested_svm_check_permissions(vcpu))
2407 ret = kvm_skip_emulated_instruction(vcpu);
2408 svm_set_gif(to_svm(vcpu), false);
2412 static int invlpga_interception(struct kvm_vcpu *vcpu)
2414 gva_t gva = kvm_rax_read(vcpu);
2415 u32 asid = kvm_rcx_read(vcpu);
2417 /* FIXME: Handle an address size prefix. */
2418 if (!is_long_mode(vcpu))
2421 trace_kvm_invlpga(to_svm(vcpu)->vmcb->save.rip, asid, gva);
2423 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2424 kvm_mmu_invlpg(vcpu, gva);
2426 return kvm_skip_emulated_instruction(vcpu);
2429 static int skinit_interception(struct kvm_vcpu *vcpu)
2431 trace_kvm_skinit(to_svm(vcpu)->vmcb->save.rip, kvm_rax_read(vcpu));
2433 kvm_queue_exception(vcpu, UD_VECTOR);
2437 static int task_switch_interception(struct kvm_vcpu *vcpu)
2439 struct vcpu_svm *svm = to_svm(vcpu);
2442 int int_type = svm->vmcb->control.exit_int_info &
2443 SVM_EXITINTINFO_TYPE_MASK;
2444 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2446 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2448 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2449 bool has_error_code = false;
2452 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2454 if (svm->vmcb->control.exit_info_2 &
2455 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2456 reason = TASK_SWITCH_IRET;
2457 else if (svm->vmcb->control.exit_info_2 &
2458 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2459 reason = TASK_SWITCH_JMP;
2461 reason = TASK_SWITCH_GATE;
2463 reason = TASK_SWITCH_CALL;
2465 if (reason == TASK_SWITCH_GATE) {
2467 case SVM_EXITINTINFO_TYPE_NMI:
2468 vcpu->arch.nmi_injected = false;
2470 case SVM_EXITINTINFO_TYPE_EXEPT:
2471 if (svm->vmcb->control.exit_info_2 &
2472 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2473 has_error_code = true;
2475 (u32)svm->vmcb->control.exit_info_2;
2477 kvm_clear_exception_queue(vcpu);
2479 case SVM_EXITINTINFO_TYPE_INTR:
2480 case SVM_EXITINTINFO_TYPE_SOFT:
2481 kvm_clear_interrupt_queue(vcpu);
2488 if (reason != TASK_SWITCH_GATE ||
2489 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2490 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2491 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2492 if (!svm_skip_emulated_instruction(vcpu))
2496 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2499 return kvm_task_switch(vcpu, tss_selector, int_vec, reason,
2500 has_error_code, error_code);
2503 static void svm_clr_iret_intercept(struct vcpu_svm *svm)
2505 if (!sev_es_guest(svm->vcpu.kvm))
2506 svm_clr_intercept(svm, INTERCEPT_IRET);
2509 static void svm_set_iret_intercept(struct vcpu_svm *svm)
2511 if (!sev_es_guest(svm->vcpu.kvm))
2512 svm_set_intercept(svm, INTERCEPT_IRET);
2515 static int iret_interception(struct kvm_vcpu *vcpu)
2517 struct vcpu_svm *svm = to_svm(vcpu);
2519 ++vcpu->stat.nmi_window_exits;
2520 svm->awaiting_iret_completion = true;
2522 svm_clr_iret_intercept(svm);
2523 if (!sev_es_guest(vcpu->kvm))
2524 svm->nmi_iret_rip = kvm_rip_read(vcpu);
2526 kvm_make_request(KVM_REQ_EVENT, vcpu);
2530 static int invlpg_interception(struct kvm_vcpu *vcpu)
2532 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2533 return kvm_emulate_instruction(vcpu, 0);
2535 kvm_mmu_invlpg(vcpu, to_svm(vcpu)->vmcb->control.exit_info_1);
2536 return kvm_skip_emulated_instruction(vcpu);
2539 static int emulate_on_interception(struct kvm_vcpu *vcpu)
2541 return kvm_emulate_instruction(vcpu, 0);
2544 static int rsm_interception(struct kvm_vcpu *vcpu)
2546 return kvm_emulate_instruction_from_buffer(vcpu, rsm_ins_bytes, 2);
2549 static bool check_selective_cr0_intercepted(struct kvm_vcpu *vcpu,
2552 struct vcpu_svm *svm = to_svm(vcpu);
2553 unsigned long cr0 = vcpu->arch.cr0;
2556 if (!is_guest_mode(vcpu) ||
2557 (!(vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2560 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2561 val &= ~SVM_CR0_SELECTIVE_MASK;
2564 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2565 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2571 #define CR_VALID (1ULL << 63)
2573 static int cr_interception(struct kvm_vcpu *vcpu)
2575 struct vcpu_svm *svm = to_svm(vcpu);
2580 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2581 return emulate_on_interception(vcpu);
2583 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2584 return emulate_on_interception(vcpu);
2586 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2587 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2588 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2590 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2593 if (cr >= 16) { /* mov to cr */
2595 val = kvm_register_read(vcpu, reg);
2596 trace_kvm_cr_write(cr, val);
2599 if (!check_selective_cr0_intercepted(vcpu, val))
2600 err = kvm_set_cr0(vcpu, val);
2606 err = kvm_set_cr3(vcpu, val);
2609 err = kvm_set_cr4(vcpu, val);
2612 err = kvm_set_cr8(vcpu, val);
2615 WARN(1, "unhandled write to CR%d", cr);
2616 kvm_queue_exception(vcpu, UD_VECTOR);
2619 } else { /* mov from cr */
2622 val = kvm_read_cr0(vcpu);
2625 val = vcpu->arch.cr2;
2628 val = kvm_read_cr3(vcpu);
2631 val = kvm_read_cr4(vcpu);
2634 val = kvm_get_cr8(vcpu);
2637 WARN(1, "unhandled read from CR%d", cr);
2638 kvm_queue_exception(vcpu, UD_VECTOR);
2641 kvm_register_write(vcpu, reg, val);
2642 trace_kvm_cr_read(cr, val);
2644 return kvm_complete_insn_gp(vcpu, err);
2647 static int cr_trap(struct kvm_vcpu *vcpu)
2649 struct vcpu_svm *svm = to_svm(vcpu);
2650 unsigned long old_value, new_value;
2654 new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2656 cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2659 old_value = kvm_read_cr0(vcpu);
2660 svm_set_cr0(vcpu, new_value);
2662 kvm_post_set_cr0(vcpu, old_value, new_value);
2665 old_value = kvm_read_cr4(vcpu);
2666 svm_set_cr4(vcpu, new_value);
2668 kvm_post_set_cr4(vcpu, old_value, new_value);
2671 ret = kvm_set_cr8(vcpu, new_value);
2674 WARN(1, "unhandled CR%d write trap", cr);
2675 kvm_queue_exception(vcpu, UD_VECTOR);
2679 return kvm_complete_insn_gp(vcpu, ret);
2682 static int dr_interception(struct kvm_vcpu *vcpu)
2684 struct vcpu_svm *svm = to_svm(vcpu);
2689 if (vcpu->guest_debug == 0) {
2691 * No more DR vmexits; force a reload of the debug registers
2692 * and reenter on this instruction. The next vmexit will
2693 * retrieve the full state of the debug registers.
2695 clr_dr_intercepts(svm);
2696 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2700 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2701 return emulate_on_interception(vcpu);
2703 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2704 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2705 if (dr >= 16) { /* mov to DRn */
2707 val = kvm_register_read(vcpu, reg);
2708 err = kvm_set_dr(vcpu, dr, val);
2710 kvm_get_dr(vcpu, dr, &val);
2711 kvm_register_write(vcpu, reg, val);
2714 return kvm_complete_insn_gp(vcpu, err);
2717 static int cr8_write_interception(struct kvm_vcpu *vcpu)
2721 u8 cr8_prev = kvm_get_cr8(vcpu);
2722 /* instruction emulation calls kvm_set_cr8() */
2723 r = cr_interception(vcpu);
2724 if (lapic_in_kernel(vcpu))
2726 if (cr8_prev <= kvm_get_cr8(vcpu))
2728 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2732 static int efer_trap(struct kvm_vcpu *vcpu)
2734 struct msr_data msr_info;
2738 * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2739 * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2740 * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2741 * the guest doesn't have X86_FEATURE_SVM.
2743 msr_info.host_initiated = false;
2744 msr_info.index = MSR_EFER;
2745 msr_info.data = to_svm(vcpu)->vmcb->control.exit_info_1 & ~EFER_SVME;
2746 ret = kvm_set_msr_common(vcpu, &msr_info);
2748 return kvm_complete_insn_gp(vcpu, ret);
2751 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2755 switch (msr->index) {
2756 case MSR_AMD64_DE_CFG:
2757 if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
2758 msr->data |= MSR_AMD64_DE_CFG_LFENCE_SERIALIZE;
2761 return KVM_MSR_RET_INVALID;
2767 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2769 struct vcpu_svm *svm = to_svm(vcpu);
2771 switch (msr_info->index) {
2772 case MSR_AMD64_TSC_RATIO:
2773 if (!msr_info->host_initiated && !svm->tsc_scaling_enabled)
2775 msr_info->data = svm->tsc_ratio_msr;
2778 msr_info->data = svm->vmcb01.ptr->save.star;
2780 #ifdef CONFIG_X86_64
2782 msr_info->data = svm->vmcb01.ptr->save.lstar;
2785 msr_info->data = svm->vmcb01.ptr->save.cstar;
2787 case MSR_KERNEL_GS_BASE:
2788 msr_info->data = svm->vmcb01.ptr->save.kernel_gs_base;
2790 case MSR_SYSCALL_MASK:
2791 msr_info->data = svm->vmcb01.ptr->save.sfmask;
2794 case MSR_IA32_SYSENTER_CS:
2795 msr_info->data = svm->vmcb01.ptr->save.sysenter_cs;
2797 case MSR_IA32_SYSENTER_EIP:
2798 msr_info->data = (u32)svm->vmcb01.ptr->save.sysenter_eip;
2799 if (guest_cpuid_is_intel(vcpu))
2800 msr_info->data |= (u64)svm->sysenter_eip_hi << 32;
2802 case MSR_IA32_SYSENTER_ESP:
2803 msr_info->data = svm->vmcb01.ptr->save.sysenter_esp;
2804 if (guest_cpuid_is_intel(vcpu))
2805 msr_info->data |= (u64)svm->sysenter_esp_hi << 32;
2808 msr_info->data = svm->tsc_aux;
2810 case MSR_IA32_DEBUGCTLMSR:
2811 case MSR_IA32_LASTBRANCHFROMIP:
2812 case MSR_IA32_LASTBRANCHTOIP:
2813 case MSR_IA32_LASTINTFROMIP:
2814 case MSR_IA32_LASTINTTOIP:
2815 msr_info->data = svm_get_lbr_msr(svm, msr_info->index);
2817 case MSR_VM_HSAVE_PA:
2818 msr_info->data = svm->nested.hsave_msr;
2821 msr_info->data = svm->nested.vm_cr_msr;
2823 case MSR_IA32_SPEC_CTRL:
2824 if (!msr_info->host_initiated &&
2825 !guest_has_spec_ctrl_msr(vcpu))
2828 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2829 msr_info->data = svm->vmcb->save.spec_ctrl;
2831 msr_info->data = svm->spec_ctrl;
2833 case MSR_AMD64_VIRT_SPEC_CTRL:
2834 if (!msr_info->host_initiated &&
2835 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2838 msr_info->data = svm->virt_spec_ctrl;
2840 case MSR_F15H_IC_CFG: {
2844 family = guest_cpuid_family(vcpu);
2845 model = guest_cpuid_model(vcpu);
2847 if (family < 0 || model < 0)
2848 return kvm_get_msr_common(vcpu, msr_info);
2852 if (family == 0x15 &&
2853 (model >= 0x2 && model < 0x20))
2854 msr_info->data = 0x1E;
2857 case MSR_AMD64_DE_CFG:
2858 msr_info->data = svm->msr_decfg;
2861 return kvm_get_msr_common(vcpu, msr_info);
2866 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2868 struct vcpu_svm *svm = to_svm(vcpu);
2869 if (!err || !sev_es_guest(vcpu->kvm) || WARN_ON_ONCE(!svm->sev_es.ghcb))
2870 return kvm_complete_insn_gp(vcpu, err);
2872 ghcb_set_sw_exit_info_1(svm->sev_es.ghcb, 1);
2873 ghcb_set_sw_exit_info_2(svm->sev_es.ghcb,
2875 SVM_EVTINJ_TYPE_EXEPT |
2880 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2882 struct vcpu_svm *svm = to_svm(vcpu);
2883 int svm_dis, chg_mask;
2885 if (data & ~SVM_VM_CR_VALID_MASK)
2888 chg_mask = SVM_VM_CR_VALID_MASK;
2890 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2891 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2893 svm->nested.vm_cr_msr &= ~chg_mask;
2894 svm->nested.vm_cr_msr |= (data & chg_mask);
2896 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2898 /* check for svm_disable while efer.svme is set */
2899 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2905 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2907 struct vcpu_svm *svm = to_svm(vcpu);
2910 u32 ecx = msr->index;
2911 u64 data = msr->data;
2913 case MSR_AMD64_TSC_RATIO:
2915 if (!svm->tsc_scaling_enabled) {
2917 if (!msr->host_initiated)
2920 * In case TSC scaling is not enabled, always
2921 * leave this MSR at the default value.
2923 * Due to bug in qemu 6.2.0, it would try to set
2924 * this msr to 0 if tsc scaling is not enabled.
2925 * Ignore this value as well.
2927 if (data != 0 && data != svm->tsc_ratio_msr)
2932 if (data & SVM_TSC_RATIO_RSVD)
2935 svm->tsc_ratio_msr = data;
2937 if (svm->tsc_scaling_enabled && is_guest_mode(vcpu))
2938 nested_svm_update_tsc_ratio_msr(vcpu);
2941 case MSR_IA32_CR_PAT:
2942 ret = kvm_set_msr_common(vcpu, msr);
2946 svm->vmcb01.ptr->save.g_pat = data;
2947 if (is_guest_mode(vcpu))
2948 nested_vmcb02_compute_g_pat(svm);
2949 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2951 case MSR_IA32_SPEC_CTRL:
2952 if (!msr->host_initiated &&
2953 !guest_has_spec_ctrl_msr(vcpu))
2956 if (kvm_spec_ctrl_test_value(data))
2959 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2960 svm->vmcb->save.spec_ctrl = data;
2962 svm->spec_ctrl = data;
2968 * When it's written (to non-zero) for the first time, pass
2972 * The handling of the MSR bitmap for L2 guests is done in
2973 * nested_svm_vmrun_msrpm.
2974 * We update the L1 MSR bit as well since it will end up
2975 * touching the MSR anyway now.
2977 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2979 case MSR_AMD64_VIRT_SPEC_CTRL:
2980 if (!msr->host_initiated &&
2981 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2984 if (data & ~SPEC_CTRL_SSBD)
2987 svm->virt_spec_ctrl = data;
2990 svm->vmcb01.ptr->save.star = data;
2992 #ifdef CONFIG_X86_64
2994 svm->vmcb01.ptr->save.lstar = data;
2997 svm->vmcb01.ptr->save.cstar = data;
2999 case MSR_KERNEL_GS_BASE:
3000 svm->vmcb01.ptr->save.kernel_gs_base = data;
3002 case MSR_SYSCALL_MASK:
3003 svm->vmcb01.ptr->save.sfmask = data;
3006 case MSR_IA32_SYSENTER_CS:
3007 svm->vmcb01.ptr->save.sysenter_cs = data;
3009 case MSR_IA32_SYSENTER_EIP:
3010 svm->vmcb01.ptr->save.sysenter_eip = (u32)data;
3012 * We only intercept the MSR_IA32_SYSENTER_{EIP|ESP} msrs
3013 * when we spoof an Intel vendor ID (for cross vendor migration).
3014 * In this case we use this intercept to track the high
3015 * 32 bit part of these msrs to support Intel's
3016 * implementation of SYSENTER/SYSEXIT.
3018 svm->sysenter_eip_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
3020 case MSR_IA32_SYSENTER_ESP:
3021 svm->vmcb01.ptr->save.sysenter_esp = (u32)data;
3022 svm->sysenter_esp_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
3026 * TSC_AUX is usually changed only during boot and never read
3027 * directly. Intercept TSC_AUX instead of exposing it to the
3028 * guest via direct_access_msrs, and switch it via user return.
3031 ret = kvm_set_user_return_msr(tsc_aux_uret_slot, data, -1ull);
3036 svm->tsc_aux = data;
3038 case MSR_IA32_DEBUGCTLMSR:
3040 kvm_pr_unimpl_wrmsr(vcpu, ecx, data);
3043 if (data & DEBUGCTL_RESERVED_BITS)
3046 if (svm->vmcb->control.virt_ext & LBR_CTL_ENABLE_MASK)
3047 svm->vmcb->save.dbgctl = data;
3049 svm->vmcb01.ptr->save.dbgctl = data;
3051 svm_update_lbrv(vcpu);
3054 case MSR_VM_HSAVE_PA:
3056 * Old kernels did not validate the value written to
3057 * MSR_VM_HSAVE_PA. Allow KVM_SET_MSR to set an invalid
3058 * value to allow live migrating buggy or malicious guests
3059 * originating from those kernels.
3061 if (!msr->host_initiated && !page_address_valid(vcpu, data))
3064 svm->nested.hsave_msr = data & PAGE_MASK;
3067 return svm_set_vm_cr(vcpu, data);
3069 kvm_pr_unimpl_wrmsr(vcpu, ecx, data);
3071 case MSR_AMD64_DE_CFG: {
3072 struct kvm_msr_entry msr_entry;
3074 msr_entry.index = msr->index;
3075 if (svm_get_msr_feature(&msr_entry))
3078 /* Check the supported bits */
3079 if (data & ~msr_entry.data)
3082 /* Don't allow the guest to change a bit, #GP */
3083 if (!msr->host_initiated && (data ^ msr_entry.data))
3086 svm->msr_decfg = data;
3090 return kvm_set_msr_common(vcpu, msr);
3095 static int msr_interception(struct kvm_vcpu *vcpu)
3097 if (to_svm(vcpu)->vmcb->control.exit_info_1)
3098 return kvm_emulate_wrmsr(vcpu);
3100 return kvm_emulate_rdmsr(vcpu);
3103 static int interrupt_window_interception(struct kvm_vcpu *vcpu)
3105 kvm_make_request(KVM_REQ_EVENT, vcpu);
3106 svm_clear_vintr(to_svm(vcpu));
3109 * If not running nested, for AVIC, the only reason to end up here is ExtINTs.
3110 * In this case AVIC was temporarily disabled for
3111 * requesting the IRQ window and we have to re-enable it.
3113 * If running nested, still remove the VM wide AVIC inhibit to
3114 * support case in which the interrupt window was requested when the
3115 * vCPU was not running nested.
3117 * All vCPUs which run still run nested, will remain to have their
3118 * AVIC still inhibited due to per-cpu AVIC inhibition.
3120 kvm_clear_apicv_inhibit(vcpu->kvm, APICV_INHIBIT_REASON_IRQWIN);
3122 ++vcpu->stat.irq_window_exits;
3126 static int pause_interception(struct kvm_vcpu *vcpu)
3130 * CPL is not made available for an SEV-ES guest, therefore
3131 * vcpu->arch.preempted_in_kernel can never be true. Just
3132 * set in_kernel to false as well.
3134 in_kernel = !sev_es_guest(vcpu->kvm) && svm_get_cpl(vcpu) == 0;
3136 grow_ple_window(vcpu);
3138 kvm_vcpu_on_spin(vcpu, in_kernel);
3139 return kvm_skip_emulated_instruction(vcpu);
3142 static int invpcid_interception(struct kvm_vcpu *vcpu)
3144 struct vcpu_svm *svm = to_svm(vcpu);
3148 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
3149 kvm_queue_exception(vcpu, UD_VECTOR);
3154 * For an INVPCID intercept:
3155 * EXITINFO1 provides the linear address of the memory operand.
3156 * EXITINFO2 provides the contents of the register operand.
3158 type = svm->vmcb->control.exit_info_2;
3159 gva = svm->vmcb->control.exit_info_1;
3161 return kvm_handle_invpcid(vcpu, type, gva);
3164 static int (*const svm_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3165 [SVM_EXIT_READ_CR0] = cr_interception,
3166 [SVM_EXIT_READ_CR3] = cr_interception,
3167 [SVM_EXIT_READ_CR4] = cr_interception,
3168 [SVM_EXIT_READ_CR8] = cr_interception,
3169 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3170 [SVM_EXIT_WRITE_CR0] = cr_interception,
3171 [SVM_EXIT_WRITE_CR3] = cr_interception,
3172 [SVM_EXIT_WRITE_CR4] = cr_interception,
3173 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3174 [SVM_EXIT_READ_DR0] = dr_interception,
3175 [SVM_EXIT_READ_DR1] = dr_interception,
3176 [SVM_EXIT_READ_DR2] = dr_interception,
3177 [SVM_EXIT_READ_DR3] = dr_interception,
3178 [SVM_EXIT_READ_DR4] = dr_interception,
3179 [SVM_EXIT_READ_DR5] = dr_interception,
3180 [SVM_EXIT_READ_DR6] = dr_interception,
3181 [SVM_EXIT_READ_DR7] = dr_interception,
3182 [SVM_EXIT_WRITE_DR0] = dr_interception,
3183 [SVM_EXIT_WRITE_DR1] = dr_interception,
3184 [SVM_EXIT_WRITE_DR2] = dr_interception,
3185 [SVM_EXIT_WRITE_DR3] = dr_interception,
3186 [SVM_EXIT_WRITE_DR4] = dr_interception,
3187 [SVM_EXIT_WRITE_DR5] = dr_interception,
3188 [SVM_EXIT_WRITE_DR6] = dr_interception,
3189 [SVM_EXIT_WRITE_DR7] = dr_interception,
3190 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3191 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3192 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3193 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3194 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3195 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
3196 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
3197 [SVM_EXIT_INTR] = intr_interception,
3198 [SVM_EXIT_NMI] = nmi_interception,
3199 [SVM_EXIT_SMI] = smi_interception,
3200 [SVM_EXIT_VINTR] = interrupt_window_interception,
3201 [SVM_EXIT_RDPMC] = kvm_emulate_rdpmc,
3202 [SVM_EXIT_CPUID] = kvm_emulate_cpuid,
3203 [SVM_EXIT_IRET] = iret_interception,
3204 [SVM_EXIT_INVD] = kvm_emulate_invd,
3205 [SVM_EXIT_PAUSE] = pause_interception,
3206 [SVM_EXIT_HLT] = kvm_emulate_halt,
3207 [SVM_EXIT_INVLPG] = invlpg_interception,
3208 [SVM_EXIT_INVLPGA] = invlpga_interception,
3209 [SVM_EXIT_IOIO] = io_interception,
3210 [SVM_EXIT_MSR] = msr_interception,
3211 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3212 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3213 [SVM_EXIT_VMRUN] = vmrun_interception,
3214 [SVM_EXIT_VMMCALL] = kvm_emulate_hypercall,
3215 [SVM_EXIT_VMLOAD] = vmload_interception,
3216 [SVM_EXIT_VMSAVE] = vmsave_interception,
3217 [SVM_EXIT_STGI] = stgi_interception,
3218 [SVM_EXIT_CLGI] = clgi_interception,
3219 [SVM_EXIT_SKINIT] = skinit_interception,
3220 [SVM_EXIT_RDTSCP] = kvm_handle_invalid_op,
3221 [SVM_EXIT_WBINVD] = kvm_emulate_wbinvd,
3222 [SVM_EXIT_MONITOR] = kvm_emulate_monitor,
3223 [SVM_EXIT_MWAIT] = kvm_emulate_mwait,
3224 [SVM_EXIT_XSETBV] = kvm_emulate_xsetbv,
3225 [SVM_EXIT_RDPRU] = kvm_handle_invalid_op,
3226 [SVM_EXIT_EFER_WRITE_TRAP] = efer_trap,
3227 [SVM_EXIT_CR0_WRITE_TRAP] = cr_trap,
3228 [SVM_EXIT_CR4_WRITE_TRAP] = cr_trap,
3229 [SVM_EXIT_CR8_WRITE_TRAP] = cr_trap,
3230 [SVM_EXIT_INVPCID] = invpcid_interception,
3231 [SVM_EXIT_NPF] = npf_interception,
3232 [SVM_EXIT_RSM] = rsm_interception,
3233 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
3234 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
3235 [SVM_EXIT_VMGEXIT] = sev_handle_vmgexit,
3238 static void dump_vmcb(struct kvm_vcpu *vcpu)
3240 struct vcpu_svm *svm = to_svm(vcpu);
3241 struct vmcb_control_area *control = &svm->vmcb->control;
3242 struct vmcb_save_area *save = &svm->vmcb->save;
3243 struct vmcb_save_area *save01 = &svm->vmcb01.ptr->save;
3245 if (!dump_invalid_vmcb) {
3246 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3250 pr_err("VMCB %p, last attempted VMRUN on CPU %d\n",
3251 svm->current_vmcb->ptr, vcpu->arch.last_vmentry_cpu);
3252 pr_err("VMCB Control Area:\n");
3253 pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3254 pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3255 pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3256 pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3257 pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3258 pr_err("%-20s%08x %08x\n", "intercepts:",
3259 control->intercepts[INTERCEPT_WORD3],
3260 control->intercepts[INTERCEPT_WORD4]);
3261 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3262 pr_err("%-20s%d\n", "pause filter threshold:",
3263 control->pause_filter_thresh);
3264 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3265 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3266 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3267 pr_err("%-20s%d\n", "asid:", control->asid);
3268 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3269 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3270 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3271 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3272 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3273 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3274 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3275 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3276 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3277 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3278 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3279 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3280 pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3281 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3282 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3283 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3284 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3285 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3286 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3287 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3288 pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
3289 pr_err("VMCB State Save Area:\n");
3290 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3292 save->es.selector, save->es.attrib,
3293 save->es.limit, save->es.base);
3294 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3296 save->cs.selector, save->cs.attrib,
3297 save->cs.limit, save->cs.base);
3298 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3300 save->ss.selector, save->ss.attrib,
3301 save->ss.limit, save->ss.base);
3302 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3304 save->ds.selector, save->ds.attrib,
3305 save->ds.limit, save->ds.base);
3306 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3308 save01->fs.selector, save01->fs.attrib,
3309 save01->fs.limit, save01->fs.base);
3310 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3312 save01->gs.selector, save01->gs.attrib,
3313 save01->gs.limit, save01->gs.base);
3314 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3316 save->gdtr.selector, save->gdtr.attrib,
3317 save->gdtr.limit, save->gdtr.base);
3318 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3320 save01->ldtr.selector, save01->ldtr.attrib,
3321 save01->ldtr.limit, save01->ldtr.base);
3322 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3324 save->idtr.selector, save->idtr.attrib,
3325 save->idtr.limit, save->idtr.base);
3326 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3328 save01->tr.selector, save01->tr.attrib,
3329 save01->tr.limit, save01->tr.base);
3330 pr_err("vmpl: %d cpl: %d efer: %016llx\n",
3331 save->vmpl, save->cpl, save->efer);
3332 pr_err("%-15s %016llx %-13s %016llx\n",
3333 "cr0:", save->cr0, "cr2:", save->cr2);
3334 pr_err("%-15s %016llx %-13s %016llx\n",
3335 "cr3:", save->cr3, "cr4:", save->cr4);
3336 pr_err("%-15s %016llx %-13s %016llx\n",
3337 "dr6:", save->dr6, "dr7:", save->dr7);
3338 pr_err("%-15s %016llx %-13s %016llx\n",
3339 "rip:", save->rip, "rflags:", save->rflags);
3340 pr_err("%-15s %016llx %-13s %016llx\n",
3341 "rsp:", save->rsp, "rax:", save->rax);
3342 pr_err("%-15s %016llx %-13s %016llx\n",
3343 "star:", save01->star, "lstar:", save01->lstar);
3344 pr_err("%-15s %016llx %-13s %016llx\n",
3345 "cstar:", save01->cstar, "sfmask:", save01->sfmask);
3346 pr_err("%-15s %016llx %-13s %016llx\n",
3347 "kernel_gs_base:", save01->kernel_gs_base,
3348 "sysenter_cs:", save01->sysenter_cs);
3349 pr_err("%-15s %016llx %-13s %016llx\n",
3350 "sysenter_esp:", save01->sysenter_esp,
3351 "sysenter_eip:", save01->sysenter_eip);
3352 pr_err("%-15s %016llx %-13s %016llx\n",
3353 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3354 pr_err("%-15s %016llx %-13s %016llx\n",
3355 "br_from:", save->br_from, "br_to:", save->br_to);
3356 pr_err("%-15s %016llx %-13s %016llx\n",
3357 "excp_from:", save->last_excp_from,
3358 "excp_to:", save->last_excp_to);
3361 static bool svm_check_exit_valid(u64 exit_code)
3363 return (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3364 svm_exit_handlers[exit_code]);
3367 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3369 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3371 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3372 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3373 vcpu->run->internal.ndata = 2;
3374 vcpu->run->internal.data[0] = exit_code;
3375 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3379 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code)
3381 if (!svm_check_exit_valid(exit_code))
3382 return svm_handle_invalid_exit(vcpu, exit_code);
3384 #ifdef CONFIG_RETPOLINE
3385 if (exit_code == SVM_EXIT_MSR)
3386 return msr_interception(vcpu);
3387 else if (exit_code == SVM_EXIT_VINTR)
3388 return interrupt_window_interception(vcpu);
3389 else if (exit_code == SVM_EXIT_INTR)
3390 return intr_interception(vcpu);
3391 else if (exit_code == SVM_EXIT_HLT)
3392 return kvm_emulate_halt(vcpu);
3393 else if (exit_code == SVM_EXIT_NPF)
3394 return npf_interception(vcpu);
3396 return svm_exit_handlers[exit_code](vcpu);
3399 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u32 *reason,
3400 u64 *info1, u64 *info2,
3401 u32 *intr_info, u32 *error_code)
3403 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3405 *reason = control->exit_code;
3406 *info1 = control->exit_info_1;
3407 *info2 = control->exit_info_2;
3408 *intr_info = control->exit_int_info;
3409 if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3410 (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3411 *error_code = control->exit_int_info_err;
3416 static int svm_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3418 struct vcpu_svm *svm = to_svm(vcpu);
3419 struct kvm_run *kvm_run = vcpu->run;
3420 u32 exit_code = svm->vmcb->control.exit_code;
3422 trace_kvm_exit(vcpu, KVM_ISA_SVM);
3424 /* SEV-ES guests must use the CR write traps to track CR registers. */
3425 if (!sev_es_guest(vcpu->kvm)) {
3426 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3427 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3429 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3432 if (is_guest_mode(vcpu)) {
3435 trace_kvm_nested_vmexit(vcpu, KVM_ISA_SVM);
3437 vmexit = nested_svm_exit_special(svm);
3439 if (vmexit == NESTED_EXIT_CONTINUE)
3440 vmexit = nested_svm_exit_handled(svm);
3442 if (vmexit == NESTED_EXIT_DONE)
3446 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3447 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3448 kvm_run->fail_entry.hardware_entry_failure_reason
3449 = svm->vmcb->control.exit_code;
3450 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3455 if (exit_fastpath != EXIT_FASTPATH_NONE)
3458 return svm_invoke_exit_handler(vcpu, exit_code);
3461 static void reload_tss(struct kvm_vcpu *vcpu)
3463 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, vcpu->cpu);
3465 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3469 static void pre_svm_run(struct kvm_vcpu *vcpu)
3471 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, vcpu->cpu);
3472 struct vcpu_svm *svm = to_svm(vcpu);
3475 * If the previous vmrun of the vmcb occurred on a different physical
3476 * cpu, then mark the vmcb dirty and assign a new asid. Hardware's
3477 * vmcb clean bits are per logical CPU, as are KVM's asid assignments.
3479 if (unlikely(svm->current_vmcb->cpu != vcpu->cpu)) {
3480 svm->current_vmcb->asid_generation = 0;
3481 vmcb_mark_all_dirty(svm->vmcb);
3482 svm->current_vmcb->cpu = vcpu->cpu;
3485 if (sev_guest(vcpu->kvm))
3486 return pre_sev_run(svm, vcpu->cpu);
3488 /* FIXME: handle wraparound of asid_generation */
3489 if (svm->current_vmcb->asid_generation != sd->asid_generation)
3493 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3495 struct vcpu_svm *svm = to_svm(vcpu);
3497 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3499 if (svm->nmi_l1_to_l2)
3502 svm->nmi_masked = true;
3503 svm_set_iret_intercept(svm);
3504 ++vcpu->stat.nmi_injections;
3507 static bool svm_is_vnmi_pending(struct kvm_vcpu *vcpu)
3509 struct vcpu_svm *svm = to_svm(vcpu);
3511 if (!is_vnmi_enabled(svm))
3514 return !!(svm->vmcb->control.int_ctl & V_NMI_PENDING_MASK);
3517 static bool svm_set_vnmi_pending(struct kvm_vcpu *vcpu)
3519 struct vcpu_svm *svm = to_svm(vcpu);
3521 if (!is_vnmi_enabled(svm))
3524 if (svm->vmcb->control.int_ctl & V_NMI_PENDING_MASK)
3527 svm->vmcb->control.int_ctl |= V_NMI_PENDING_MASK;
3528 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
3531 * Because the pending NMI is serviced by hardware, KVM can't know when
3532 * the NMI is "injected", but for all intents and purposes, passing the
3533 * NMI off to hardware counts as injection.
3535 ++vcpu->stat.nmi_injections;
3540 static void svm_inject_irq(struct kvm_vcpu *vcpu, bool reinjected)
3542 struct vcpu_svm *svm = to_svm(vcpu);
3545 if (vcpu->arch.interrupt.soft) {
3546 if (svm_update_soft_interrupt_rip(vcpu))
3549 type = SVM_EVTINJ_TYPE_SOFT;
3551 type = SVM_EVTINJ_TYPE_INTR;
3554 trace_kvm_inj_virq(vcpu->arch.interrupt.nr,
3555 vcpu->arch.interrupt.soft, reinjected);
3556 ++vcpu->stat.irq_injections;
3558 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3559 SVM_EVTINJ_VALID | type;
3562 void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_mode,
3563 int trig_mode, int vector)
3566 * apic->apicv_active must be read after vcpu->mode.
3567 * Pairs with smp_store_release in vcpu_enter_guest.
3569 bool in_guest_mode = (smp_load_acquire(&vcpu->mode) == IN_GUEST_MODE);
3571 /* Note, this is called iff the local APIC is in-kernel. */
3572 if (!READ_ONCE(vcpu->arch.apic->apicv_active)) {
3573 /* Process the interrupt via kvm_check_and_inject_events(). */
3574 kvm_make_request(KVM_REQ_EVENT, vcpu);
3575 kvm_vcpu_kick(vcpu);
3579 trace_kvm_apicv_accept_irq(vcpu->vcpu_id, delivery_mode, trig_mode, vector);
3580 if (in_guest_mode) {
3582 * Signal the doorbell to tell hardware to inject the IRQ. If
3583 * the vCPU exits the guest before the doorbell chimes, hardware
3584 * will automatically process AVIC interrupts at the next VMRUN.
3586 avic_ring_doorbell(vcpu);
3589 * Wake the vCPU if it was blocking. KVM will then detect the
3590 * pending IRQ when checking if the vCPU has a wake event.
3592 kvm_vcpu_wake_up(vcpu);
3596 static void svm_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode,
3597 int trig_mode, int vector)
3599 kvm_lapic_set_irr(vector, apic);
3602 * Pairs with the smp_mb_*() after setting vcpu->guest_mode in
3603 * vcpu_enter_guest() to ensure the write to the vIRR is ordered before
3604 * the read of guest_mode. This guarantees that either VMRUN will see
3605 * and process the new vIRR entry, or that svm_complete_interrupt_delivery
3606 * will signal the doorbell if the CPU has already entered the guest.
3608 smp_mb__after_atomic();
3609 svm_complete_interrupt_delivery(apic->vcpu, delivery_mode, trig_mode, vector);
3612 static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3614 struct vcpu_svm *svm = to_svm(vcpu);
3617 * SEV-ES guests must always keep the CR intercepts cleared. CR
3618 * tracking is done using the CR write traps.
3620 if (sev_es_guest(vcpu->kvm))
3623 if (nested_svm_virtualize_tpr(vcpu))
3626 svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3632 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3635 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3637 struct vcpu_svm *svm = to_svm(vcpu);
3639 if (is_vnmi_enabled(svm))
3640 return svm->vmcb->control.int_ctl & V_NMI_BLOCKING_MASK;
3642 return svm->nmi_masked;
3645 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3647 struct vcpu_svm *svm = to_svm(vcpu);
3649 if (is_vnmi_enabled(svm)) {
3651 svm->vmcb->control.int_ctl |= V_NMI_BLOCKING_MASK;
3653 svm->vmcb->control.int_ctl &= ~V_NMI_BLOCKING_MASK;
3656 svm->nmi_masked = masked;
3658 svm_set_iret_intercept(svm);
3660 svm_clr_iret_intercept(svm);
3664 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3666 struct vcpu_svm *svm = to_svm(vcpu);
3667 struct vmcb *vmcb = svm->vmcb;
3672 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3675 if (svm_get_nmi_mask(vcpu))
3678 return vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK;
3681 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3683 struct vcpu_svm *svm = to_svm(vcpu);
3684 if (svm->nested.nested_run_pending)
3687 if (svm_nmi_blocked(vcpu))
3690 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3691 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3696 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3698 struct vcpu_svm *svm = to_svm(vcpu);
3699 struct vmcb *vmcb = svm->vmcb;
3704 if (is_guest_mode(vcpu)) {
3705 /* As long as interrupts are being delivered... */
3706 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3707 ? !(svm->vmcb01.ptr->save.rflags & X86_EFLAGS_IF)
3708 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3711 /* ... vmexits aren't blocked by the interrupt shadow */
3712 if (nested_exit_on_intr(svm))
3715 if (!svm_get_if_flag(vcpu))
3719 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3722 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3724 struct vcpu_svm *svm = to_svm(vcpu);
3726 if (svm->nested.nested_run_pending)
3729 if (svm_interrupt_blocked(vcpu))
3733 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3734 * e.g. if the IRQ arrived asynchronously after checking nested events.
3736 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3742 static void svm_enable_irq_window(struct kvm_vcpu *vcpu)
3744 struct vcpu_svm *svm = to_svm(vcpu);
3747 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3748 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3749 * get that intercept, this function will be called again though and
3750 * we'll get the vintr intercept. However, if the vGIF feature is
3751 * enabled, the STGI interception will not occur. Enable the irq
3752 * window under the assumption that the hardware will set the GIF.
3754 if (vgif || gif_set(svm)) {
3756 * IRQ window is not needed when AVIC is enabled,
3757 * unless we have pending ExtINT since it cannot be injected
3758 * via AVIC. In such case, KVM needs to temporarily disable AVIC,
3759 * and fallback to injecting IRQ via V_IRQ.
3761 * If running nested, AVIC is already locally inhibited
3762 * on this vCPU, therefore there is no need to request
3763 * the VM wide AVIC inhibition.
3765 if (!is_guest_mode(vcpu))
3766 kvm_set_apicv_inhibit(vcpu->kvm, APICV_INHIBIT_REASON_IRQWIN);
3772 static void svm_enable_nmi_window(struct kvm_vcpu *vcpu)
3774 struct vcpu_svm *svm = to_svm(vcpu);
3777 * KVM should never request an NMI window when vNMI is enabled, as KVM
3778 * allows at most one to-be-injected NMI and one pending NMI, i.e. if
3779 * two NMIs arrive simultaneously, KVM will inject one and set
3780 * V_NMI_PENDING for the other. WARN, but continue with the standard
3781 * single-step approach to try and salvage the pending NMI.
3783 WARN_ON_ONCE(is_vnmi_enabled(svm));
3785 if (svm_get_nmi_mask(vcpu) && !svm->awaiting_iret_completion)
3786 return; /* IRET will cause a vm exit */
3788 if (!gif_set(svm)) {
3790 svm_set_intercept(svm, INTERCEPT_STGI);
3791 return; /* STGI will cause a vm exit */
3795 * Something prevents NMI from been injected. Single step over possible
3796 * problem (IRET or exception injection or interrupt shadow)
3798 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3799 svm->nmi_singlestep = true;
3800 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3803 static void svm_flush_tlb_asid(struct kvm_vcpu *vcpu)
3805 struct vcpu_svm *svm = to_svm(vcpu);
3808 * Unlike VMX, SVM doesn't provide a way to flush only NPT TLB entries.
3809 * A TLB flush for the current ASID flushes both "host" and "guest" TLB
3810 * entries, and thus is a superset of Hyper-V's fine grained flushing.
3812 kvm_hv_vcpu_purge_flush_tlb(vcpu);
3815 * Flush only the current ASID even if the TLB flush was invoked via
3816 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3817 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3818 * unconditionally does a TLB flush on both nested VM-Enter and nested
3819 * VM-Exit (via kvm_mmu_reset_context()).
3821 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3822 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3824 svm->current_vmcb->asid_generation--;
3827 static void svm_flush_tlb_current(struct kvm_vcpu *vcpu)
3829 hpa_t root_tdp = vcpu->arch.mmu->root.hpa;
3832 * When running on Hyper-V with EnlightenedNptTlb enabled, explicitly
3833 * flush the NPT mappings via hypercall as flushing the ASID only
3834 * affects virtual to physical mappings, it does not invalidate guest
3835 * physical to host physical mappings.
3837 if (svm_hv_is_enlightened_tlb_enabled(vcpu) && VALID_PAGE(root_tdp))
3838 hyperv_flush_guest_mapping(root_tdp);
3840 svm_flush_tlb_asid(vcpu);
3843 static void svm_flush_tlb_all(struct kvm_vcpu *vcpu)
3846 * When running on Hyper-V with EnlightenedNptTlb enabled, remote TLB
3847 * flushes should be routed to hv_flush_remote_tlbs() without requesting
3848 * a "regular" remote flush. Reaching this point means either there's
3849 * a KVM bug or a prior hv_flush_remote_tlbs() call failed, both of
3850 * which might be fatal to the guest. Yell, but try to recover.
3852 if (WARN_ON_ONCE(svm_hv_is_enlightened_tlb_enabled(vcpu)))
3853 hv_flush_remote_tlbs(vcpu->kvm);
3855 svm_flush_tlb_asid(vcpu);
3858 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3860 struct vcpu_svm *svm = to_svm(vcpu);
3862 invlpga(gva, svm->vmcb->control.asid);
3865 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3867 struct vcpu_svm *svm = to_svm(vcpu);
3869 if (nested_svm_virtualize_tpr(vcpu))
3872 if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3873 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3874 kvm_set_cr8(vcpu, cr8);
3878 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3880 struct vcpu_svm *svm = to_svm(vcpu);
3883 if (nested_svm_virtualize_tpr(vcpu) ||
3884 kvm_vcpu_apicv_active(vcpu))
3887 cr8 = kvm_get_cr8(vcpu);
3888 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3889 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3892 static void svm_complete_soft_interrupt(struct kvm_vcpu *vcpu, u8 vector,
3895 bool is_exception = (type == SVM_EXITINTINFO_TYPE_EXEPT);
3896 bool is_soft = (type == SVM_EXITINTINFO_TYPE_SOFT);
3897 struct vcpu_svm *svm = to_svm(vcpu);
3900 * If NRIPS is enabled, KVM must snapshot the pre-VMRUN next_rip that's
3901 * associated with the original soft exception/interrupt. next_rip is
3902 * cleared on all exits that can occur while vectoring an event, so KVM
3903 * needs to manually set next_rip for re-injection. Unlike the !nrips
3904 * case below, this needs to be done if and only if KVM is re-injecting
3905 * the same event, i.e. if the event is a soft exception/interrupt,
3906 * otherwise next_rip is unused on VMRUN.
3908 if (nrips && (is_soft || (is_exception && kvm_exception_is_soft(vector))) &&
3909 kvm_is_linear_rip(vcpu, svm->soft_int_old_rip + svm->soft_int_csbase))
3910 svm->vmcb->control.next_rip = svm->soft_int_next_rip;
3912 * If NRIPS isn't enabled, KVM must manually advance RIP prior to
3913 * injecting the soft exception/interrupt. That advancement needs to
3914 * be unwound if vectoring didn't complete. Note, the new event may
3915 * not be the injected event, e.g. if KVM injected an INTn, the INTn
3916 * hit a #NP in the guest, and the #NP encountered a #PF, the #NP will
3917 * be the reported vectored event, but RIP still needs to be unwound.
3919 else if (!nrips && (is_soft || is_exception) &&
3920 kvm_is_linear_rip(vcpu, svm->soft_int_next_rip + svm->soft_int_csbase))
3921 kvm_rip_write(vcpu, svm->soft_int_old_rip);
3924 static void svm_complete_interrupts(struct kvm_vcpu *vcpu)
3926 struct vcpu_svm *svm = to_svm(vcpu);
3929 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3930 bool nmi_l1_to_l2 = svm->nmi_l1_to_l2;
3931 bool soft_int_injected = svm->soft_int_injected;
3933 svm->nmi_l1_to_l2 = false;
3934 svm->soft_int_injected = false;
3937 * If we've made progress since setting HF_IRET_MASK, we've
3938 * executed an IRET and can allow NMI injection.
3940 if (svm->awaiting_iret_completion &&
3941 (sev_es_guest(vcpu->kvm) ||
3942 kvm_rip_read(vcpu) != svm->nmi_iret_rip)) {
3943 svm->awaiting_iret_completion = false;
3944 svm->nmi_masked = false;
3945 kvm_make_request(KVM_REQ_EVENT, vcpu);
3948 vcpu->arch.nmi_injected = false;
3949 kvm_clear_exception_queue(vcpu);
3950 kvm_clear_interrupt_queue(vcpu);
3952 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3955 kvm_make_request(KVM_REQ_EVENT, vcpu);
3957 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3958 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3960 if (soft_int_injected)
3961 svm_complete_soft_interrupt(vcpu, vector, type);
3964 case SVM_EXITINTINFO_TYPE_NMI:
3965 vcpu->arch.nmi_injected = true;
3966 svm->nmi_l1_to_l2 = nmi_l1_to_l2;
3968 case SVM_EXITINTINFO_TYPE_EXEPT:
3970 * Never re-inject a #VC exception.
3972 if (vector == X86_TRAP_VC)
3975 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3976 u32 err = svm->vmcb->control.exit_int_info_err;
3977 kvm_requeue_exception_e(vcpu, vector, err);
3980 kvm_requeue_exception(vcpu, vector);
3982 case SVM_EXITINTINFO_TYPE_INTR:
3983 kvm_queue_interrupt(vcpu, vector, false);
3985 case SVM_EXITINTINFO_TYPE_SOFT:
3986 kvm_queue_interrupt(vcpu, vector, true);
3994 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3996 struct vcpu_svm *svm = to_svm(vcpu);
3997 struct vmcb_control_area *control = &svm->vmcb->control;
3999 control->exit_int_info = control->event_inj;
4000 control->exit_int_info_err = control->event_inj_err;
4001 control->event_inj = 0;
4002 svm_complete_interrupts(vcpu);
4005 static int svm_vcpu_pre_run(struct kvm_vcpu *vcpu)
4010 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
4012 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4015 * Note, the next RIP must be provided as SRCU isn't held, i.e. KVM
4016 * can't read guest memory (dereference memslots) to decode the WRMSR.
4018 if (control->exit_code == SVM_EXIT_MSR && control->exit_info_1 &&
4019 nrips && control->next_rip)
4020 return handle_fastpath_set_msr_irqoff(vcpu);
4022 return EXIT_FASTPATH_NONE;
4025 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu, bool spec_ctrl_intercepted)
4027 struct vcpu_svm *svm = to_svm(vcpu);
4029 guest_state_enter_irqoff();
4031 if (sev_es_guest(vcpu->kvm))
4032 __svm_sev_es_vcpu_run(svm, spec_ctrl_intercepted);
4034 __svm_vcpu_run(svm, spec_ctrl_intercepted);
4036 guest_state_exit_irqoff();
4039 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
4041 struct vcpu_svm *svm = to_svm(vcpu);
4042 bool spec_ctrl_intercepted = msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL);
4044 trace_kvm_entry(vcpu);
4046 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4047 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4048 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4051 * Disable singlestep if we're injecting an interrupt/exception.
4052 * We don't want our modified rflags to be pushed on the stack where
4053 * we might not be able to easily reset them if we disabled NMI
4056 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
4058 * Event injection happens before external interrupts cause a
4059 * vmexit and interrupts are disabled here, so smp_send_reschedule
4060 * is enough to force an immediate vmexit.
4062 disable_nmi_singlestep(svm);
4063 smp_send_reschedule(vcpu->cpu);
4068 sync_lapic_to_cr8(vcpu);
4070 if (unlikely(svm->asid != svm->vmcb->control.asid)) {
4071 svm->vmcb->control.asid = svm->asid;
4072 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
4074 svm->vmcb->save.cr2 = vcpu->arch.cr2;
4076 svm_hv_update_vp_id(svm->vmcb, vcpu);
4079 * Run with all-zero DR6 unless needed, so that we can get the exact cause
4082 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
4083 svm_set_dr6(svm, vcpu->arch.dr6);
4085 svm_set_dr6(svm, DR6_ACTIVE_LOW);
4088 kvm_load_guest_xsave_state(vcpu);
4090 kvm_wait_lapic_expire(vcpu);
4093 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
4094 * it's non-zero. Since vmentry is serialising on affected CPUs, there
4095 * is no need to worry about the conditional branch over the wrmsr
4096 * being speculatively taken.
4098 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
4099 x86_spec_ctrl_set_guest(svm->virt_spec_ctrl);
4101 svm_vcpu_enter_exit(vcpu, spec_ctrl_intercepted);
4103 if (!sev_es_guest(vcpu->kvm))
4106 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
4107 x86_spec_ctrl_restore_host(svm->virt_spec_ctrl);
4109 if (!sev_es_guest(vcpu->kvm)) {
4110 vcpu->arch.cr2 = svm->vmcb->save.cr2;
4111 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4112 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4113 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4115 vcpu->arch.regs_dirty = 0;
4117 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4118 kvm_before_interrupt(vcpu, KVM_HANDLING_NMI);
4120 kvm_load_host_xsave_state(vcpu);
4123 /* Any pending NMI will happen here */
4125 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4126 kvm_after_interrupt(vcpu);
4128 sync_cr8_to_lapic(vcpu);
4131 if (is_guest_mode(vcpu)) {
4132 nested_sync_control_from_vmcb02(svm);
4134 /* Track VMRUNs that have made past consistency checking */
4135 if (svm->nested.nested_run_pending &&
4136 svm->vmcb->control.exit_code != SVM_EXIT_ERR)
4137 ++vcpu->stat.nested_run;
4139 svm->nested.nested_run_pending = 0;
4142 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4143 vmcb_mark_all_clean(svm->vmcb);
4145 /* if exit due to PF check for async PF */
4146 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4147 vcpu->arch.apf.host_apf_flags =
4148 kvm_read_and_reset_apf_flags();
4150 vcpu->arch.regs_avail &= ~SVM_REGS_LAZY_LOAD_SET;
4153 * We need to handle MC intercepts here before the vcpu has a chance to
4154 * change the physical cpu
4156 if (unlikely(svm->vmcb->control.exit_code ==
4157 SVM_EXIT_EXCP_BASE + MC_VECTOR))
4158 svm_handle_mce(vcpu);
4160 svm_complete_interrupts(vcpu);
4162 if (is_guest_mode(vcpu))
4163 return EXIT_FASTPATH_NONE;
4165 return svm_exit_handlers_fastpath(vcpu);
4168 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
4171 struct vcpu_svm *svm = to_svm(vcpu);
4175 svm->vmcb->control.nested_cr3 = __sme_set(root_hpa);
4176 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
4178 hv_track_root_tdp(vcpu, root_hpa);
4180 cr3 = vcpu->arch.cr3;
4181 } else if (root_level >= PT64_ROOT_4LEVEL) {
4182 cr3 = __sme_set(root_hpa) | kvm_get_active_pcid(vcpu);
4184 /* PCID in the guest should be impossible with a 32-bit MMU. */
4185 WARN_ON_ONCE(kvm_get_active_pcid(vcpu));
4189 svm->vmcb->save.cr3 = cr3;
4190 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
4194 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4197 * Patch in the VMMCALL instruction:
4199 hypercall[0] = 0x0f;
4200 hypercall[1] = 0x01;
4201 hypercall[2] = 0xd9;
4205 * The kvm parameter can be NULL (module initialization, or invocation before
4206 * VM creation). Be sure to check the kvm parameter before using it.
4208 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
4211 case MSR_IA32_MCG_EXT_CTL:
4212 case KVM_FIRST_EMULATED_VMX_MSR ... KVM_LAST_EMULATED_VMX_MSR:
4214 case MSR_IA32_SMBASE:
4215 if (!IS_ENABLED(CONFIG_KVM_SMM))
4217 /* SEV-ES guests do not support SMM, so report false */
4218 if (kvm && sev_es_guest(kvm))
4228 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
4230 struct vcpu_svm *svm = to_svm(vcpu);
4231 struct kvm_cpuid_entry2 *best;
4233 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4234 boot_cpu_has(X86_FEATURE_XSAVE) &&
4235 boot_cpu_has(X86_FEATURE_XSAVES);
4237 /* Update nrips enabled cache */
4238 svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
4239 guest_cpuid_has(vcpu, X86_FEATURE_NRIPS);
4241 svm->tsc_scaling_enabled = tsc_scaling && guest_cpuid_has(vcpu, X86_FEATURE_TSCRATEMSR);
4242 svm->lbrv_enabled = lbrv && guest_cpuid_has(vcpu, X86_FEATURE_LBRV);
4244 svm->v_vmload_vmsave_enabled = vls && guest_cpuid_has(vcpu, X86_FEATURE_V_VMSAVE_VMLOAD);
4246 svm->pause_filter_enabled = kvm_cpu_cap_has(X86_FEATURE_PAUSEFILTER) &&
4247 guest_cpuid_has(vcpu, X86_FEATURE_PAUSEFILTER);
4249 svm->pause_threshold_enabled = kvm_cpu_cap_has(X86_FEATURE_PFTHRESHOLD) &&
4250 guest_cpuid_has(vcpu, X86_FEATURE_PFTHRESHOLD);
4252 svm->vgif_enabled = vgif && guest_cpuid_has(vcpu, X86_FEATURE_VGIF);
4254 svm->vnmi_enabled = vnmi && guest_cpuid_has(vcpu, X86_FEATURE_VNMI);
4256 svm_recalc_instruction_intercepts(vcpu, svm);
4258 if (boot_cpu_has(X86_FEATURE_IBPB))
4259 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0,
4260 !!guest_has_pred_cmd_msr(vcpu));
4262 if (boot_cpu_has(X86_FEATURE_FLUSH_L1D))
4263 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_FLUSH_CMD, 0,
4264 !!guest_cpuid_has(vcpu, X86_FEATURE_FLUSH_L1D));
4266 /* For sev guests, the memory encryption bit is not reserved in CR3. */
4267 if (sev_guest(vcpu->kvm)) {
4268 best = kvm_find_cpuid_entry(vcpu, 0x8000001F);
4270 vcpu->arch.reserved_gpa_bits &= ~(1UL << (best->ebx & 0x3f));
4273 init_vmcb_after_set_cpuid(vcpu);
4276 static bool svm_has_wbinvd_exit(void)
4281 #define PRE_EX(exit) { .exit_code = (exit), \
4282 .stage = X86_ICPT_PRE_EXCEPT, }
4283 #define POST_EX(exit) { .exit_code = (exit), \
4284 .stage = X86_ICPT_POST_EXCEPT, }
4285 #define POST_MEM(exit) { .exit_code = (exit), \
4286 .stage = X86_ICPT_POST_MEMACCESS, }
4288 static const struct __x86_intercept {
4290 enum x86_intercept_stage stage;
4291 } x86_intercept_map[] = {
4292 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4293 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4294 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4295 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4296 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4297 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4298 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4299 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4300 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4301 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4302 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4303 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4304 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4305 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4306 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4307 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4308 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4309 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4310 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4311 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4312 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4313 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4314 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4315 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4316 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4317 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4318 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4319 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4320 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4321 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4322 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4323 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4324 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4325 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4326 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4327 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4328 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4329 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4330 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4331 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4332 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4333 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4334 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4335 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4336 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4337 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4338 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
4345 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4346 struct x86_instruction_info *info,
4347 enum x86_intercept_stage stage,
4348 struct x86_exception *exception)
4350 struct vcpu_svm *svm = to_svm(vcpu);
4351 int vmexit, ret = X86EMUL_CONTINUE;
4352 struct __x86_intercept icpt_info;
4353 struct vmcb *vmcb = svm->vmcb;
4355 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4358 icpt_info = x86_intercept_map[info->intercept];
4360 if (stage != icpt_info.stage)
4363 switch (icpt_info.exit_code) {
4364 case SVM_EXIT_READ_CR0:
4365 if (info->intercept == x86_intercept_cr_read)
4366 icpt_info.exit_code += info->modrm_reg;
4368 case SVM_EXIT_WRITE_CR0: {
4369 unsigned long cr0, val;
4371 if (info->intercept == x86_intercept_cr_write)
4372 icpt_info.exit_code += info->modrm_reg;
4374 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4375 info->intercept == x86_intercept_clts)
4378 if (!(vmcb12_is_intercept(&svm->nested.ctl,
4379 INTERCEPT_SELECTIVE_CR0)))
4382 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4383 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4385 if (info->intercept == x86_intercept_lmsw) {
4388 /* lmsw can't clear PE - catch this here */
4389 if (cr0 & X86_CR0_PE)
4394 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4398 case SVM_EXIT_READ_DR0:
4399 case SVM_EXIT_WRITE_DR0:
4400 icpt_info.exit_code += info->modrm_reg;
4403 if (info->intercept == x86_intercept_wrmsr)
4404 vmcb->control.exit_info_1 = 1;
4406 vmcb->control.exit_info_1 = 0;
4408 case SVM_EXIT_PAUSE:
4410 * We get this for NOP only, but pause
4411 * is rep not, check this here
4413 if (info->rep_prefix != REPE_PREFIX)
4416 case SVM_EXIT_IOIO: {
4420 if (info->intercept == x86_intercept_in ||
4421 info->intercept == x86_intercept_ins) {
4422 exit_info = ((info->src_val & 0xffff) << 16) |
4424 bytes = info->dst_bytes;
4426 exit_info = (info->dst_val & 0xffff) << 16;
4427 bytes = info->src_bytes;
4430 if (info->intercept == x86_intercept_outs ||
4431 info->intercept == x86_intercept_ins)
4432 exit_info |= SVM_IOIO_STR_MASK;
4434 if (info->rep_prefix)
4435 exit_info |= SVM_IOIO_REP_MASK;
4437 bytes = min(bytes, 4u);
4439 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4441 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4443 vmcb->control.exit_info_1 = exit_info;
4444 vmcb->control.exit_info_2 = info->next_rip;
4452 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4453 if (static_cpu_has(X86_FEATURE_NRIPS))
4454 vmcb->control.next_rip = info->next_rip;
4455 vmcb->control.exit_code = icpt_info.exit_code;
4456 vmexit = nested_svm_exit_handled(svm);
4458 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4465 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4467 if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_INTR)
4468 vcpu->arch.at_instruction_boundary = true;
4471 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4473 if (!kvm_pause_in_guest(vcpu->kvm))
4474 shrink_ple_window(vcpu);
4477 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4479 /* [63:9] are reserved. */
4480 vcpu->arch.mcg_cap &= 0x1ff;
4483 #ifdef CONFIG_KVM_SMM
4484 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4486 struct vcpu_svm *svm = to_svm(vcpu);
4488 /* Per APM Vol.2 15.22.2 "Response to SMI" */
4492 return is_smm(vcpu);
4495 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4497 struct vcpu_svm *svm = to_svm(vcpu);
4498 if (svm->nested.nested_run_pending)
4501 if (svm_smi_blocked(vcpu))
4504 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
4505 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4511 static int svm_enter_smm(struct kvm_vcpu *vcpu, union kvm_smram *smram)
4513 struct vcpu_svm *svm = to_svm(vcpu);
4514 struct kvm_host_map map_save;
4517 if (!is_guest_mode(vcpu))
4521 * 32-bit SMRAM format doesn't preserve EFER and SVM state. Userspace is
4522 * responsible for ensuring nested SVM and SMIs are mutually exclusive.
4525 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
4528 smram->smram64.svm_guest_flag = 1;
4529 smram->smram64.svm_guest_vmcb_gpa = svm->nested.vmcb12_gpa;
4531 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4532 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4533 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4535 ret = nested_svm_simple_vmexit(svm, SVM_EXIT_SW);
4540 * KVM uses VMCB01 to store L1 host state while L2 runs but
4541 * VMCB01 is going to be used during SMM and thus the state will
4542 * be lost. Temporary save non-VMLOAD/VMSAVE state to the host save
4543 * area pointed to by MSR_VM_HSAVE_PA. APM guarantees that the
4544 * format of the area is identical to guest save area offsetted
4545 * by 0x400 (matches the offset of 'struct vmcb_save_area'
4546 * within 'struct vmcb'). Note: HSAVE area may also be used by
4547 * L1 hypervisor to save additional host context (e.g. KVM does
4548 * that, see svm_prepare_switch_to_guest()) which must be
4551 if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr), &map_save))
4554 BUILD_BUG_ON(offsetof(struct vmcb, save) != 0x400);
4556 svm_copy_vmrun_state(map_save.hva + 0x400,
4557 &svm->vmcb01.ptr->save);
4559 kvm_vcpu_unmap(vcpu, &map_save, true);
4563 static int svm_leave_smm(struct kvm_vcpu *vcpu, const union kvm_smram *smram)
4565 struct vcpu_svm *svm = to_svm(vcpu);
4566 struct kvm_host_map map, map_save;
4567 struct vmcb *vmcb12;
4570 const struct kvm_smram_state_64 *smram64 = &smram->smram64;
4572 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
4575 /* Non-zero if SMI arrived while vCPU was in guest mode. */
4576 if (!smram64->svm_guest_flag)
4579 if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4582 if (!(smram64->efer & EFER_SVME))
4585 if (kvm_vcpu_map(vcpu, gpa_to_gfn(smram64->svm_guest_vmcb_gpa), &map))
4589 if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr), &map_save))
4592 if (svm_allocate_nested(svm))
4596 * Restore L1 host state from L1 HSAVE area as VMCB01 was
4597 * used during SMM (see svm_enter_smm())
4600 svm_copy_vmrun_state(&svm->vmcb01.ptr->save, map_save.hva + 0x400);
4603 * Enter the nested guest now
4606 vmcb_mark_all_dirty(svm->vmcb01.ptr);
4609 nested_copy_vmcb_control_to_cache(svm, &vmcb12->control);
4610 nested_copy_vmcb_save_to_cache(svm, &vmcb12->save);
4611 ret = enter_svm_guest_mode(vcpu, smram64->svm_guest_vmcb_gpa, vmcb12, false);
4616 svm->nested.nested_run_pending = 1;
4619 kvm_vcpu_unmap(vcpu, &map_save, true);
4621 kvm_vcpu_unmap(vcpu, &map, true);
4625 static void svm_enable_smi_window(struct kvm_vcpu *vcpu)
4627 struct vcpu_svm *svm = to_svm(vcpu);
4629 if (!gif_set(svm)) {
4631 svm_set_intercept(svm, INTERCEPT_STGI);
4632 /* STGI will cause a vm exit */
4634 /* We must be in SMM; RSM will cause a vmexit anyway. */
4639 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, int emul_type,
4640 void *insn, int insn_len)
4642 bool smep, smap, is_user;
4645 /* Emulation is always possible when KVM has access to all guest state. */
4646 if (!sev_guest(vcpu->kvm))
4649 /* #UD and #GP should never be intercepted for SEV guests. */
4650 WARN_ON_ONCE(emul_type & (EMULTYPE_TRAP_UD |
4651 EMULTYPE_TRAP_UD_FORCED |
4652 EMULTYPE_VMWARE_GP));
4655 * Emulation is impossible for SEV-ES guests as KVM doesn't have access
4656 * to guest register state.
4658 if (sev_es_guest(vcpu->kvm))
4662 * Emulation is possible if the instruction is already decoded, e.g.
4663 * when completing I/O after returning from userspace.
4665 if (emul_type & EMULTYPE_NO_DECODE)
4669 * Emulation is possible for SEV guests if and only if a prefilled
4670 * buffer containing the bytes of the intercepted instruction is
4671 * available. SEV guest memory is encrypted with a guest specific key
4672 * and cannot be decrypted by KVM, i.e. KVM would read cyphertext and
4675 * Inject #UD if KVM reached this point without an instruction buffer.
4676 * In practice, this path should never be hit by a well-behaved guest,
4677 * e.g. KVM doesn't intercept #UD or #GP for SEV guests, but this path
4678 * is still theoretically reachable, e.g. via unaccelerated fault-like
4679 * AVIC access, and needs to be handled by KVM to avoid putting the
4680 * guest into an infinite loop. Injecting #UD is somewhat arbitrary,
4681 * but its the least awful option given lack of insight into the guest.
4683 if (unlikely(!insn)) {
4684 kvm_queue_exception(vcpu, UD_VECTOR);
4689 * Emulate for SEV guests if the insn buffer is not empty. The buffer
4690 * will be empty if the DecodeAssist microcode cannot fetch bytes for
4691 * the faulting instruction because the code fetch itself faulted, e.g.
4692 * the guest attempted to fetch from emulated MMIO or a guest page
4693 * table used to translate CS:RIP resides in emulated MMIO.
4695 if (likely(insn_len))
4699 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4702 * When CPU raises #NPF on guest data access and vCPU CR4.SMAP=1, it is
4703 * possible that CPU microcode implementing DecodeAssist will fail to
4704 * read guest memory at CS:RIP and vmcb.GuestIntrBytes will incorrectly
4705 * be '0'. This happens because microcode reads CS:RIP using a _data_
4706 * loap uop with CPL=0 privileges. If the load hits a SMAP #PF, ucode
4707 * gives up and does not fill the instruction bytes buffer.
4709 * As above, KVM reaches this point iff the VM is an SEV guest, the CPU
4710 * supports DecodeAssist, a #NPF was raised, KVM's page fault handler
4711 * triggered emulation (e.g. for MMIO), and the CPU returned 0 in the
4712 * GuestIntrBytes field of the VMCB.
4714 * This does _not_ mean that the erratum has been encountered, as the
4715 * DecodeAssist will also fail if the load for CS:RIP hits a legitimate
4716 * #PF, e.g. if the guest attempt to execute from emulated MMIO and
4717 * encountered a reserved/not-present #PF.
4719 * To hit the erratum, the following conditions must be true:
4720 * 1. CR4.SMAP=1 (obviously).
4721 * 2. CR4.SMEP=0 || CPL=3. If SMEP=1 and CPL<3, the erratum cannot
4722 * have been hit as the guest would have encountered a SMEP
4723 * violation #PF, not a #NPF.
4724 * 3. The #NPF is not due to a code fetch, in which case failure to
4725 * retrieve the instruction bytes is legitimate (see abvoe).
4727 * In addition, don't apply the erratum workaround if the #NPF occurred
4728 * while translating guest page tables (see below).
4730 error_code = to_svm(vcpu)->vmcb->control.exit_info_1;
4731 if (error_code & (PFERR_GUEST_PAGE_MASK | PFERR_FETCH_MASK))
4734 smep = kvm_is_cr4_bit_set(vcpu, X86_CR4_SMEP);
4735 smap = kvm_is_cr4_bit_set(vcpu, X86_CR4_SMAP);
4736 is_user = svm_get_cpl(vcpu) == 3;
4737 if (smap && (!smep || is_user)) {
4738 pr_err_ratelimited("SEV Guest triggered AMD Erratum 1096\n");
4741 * If the fault occurred in userspace, arbitrarily inject #GP
4742 * to avoid killing the guest and to hopefully avoid confusing
4743 * the guest kernel too much, e.g. injecting #PF would not be
4744 * coherent with respect to the guest's page tables. Request
4745 * triple fault if the fault occurred in the kernel as there's
4746 * no fault that KVM can inject without confusing the guest.
4747 * In practice, the triple fault is moot as no sane SEV kernel
4748 * will execute from user memory while also running with SMAP=1.
4751 kvm_inject_gp(vcpu, 0);
4753 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4758 * If the erratum was not hit, simply resume the guest and let it fault
4759 * again. While awful, e.g. the vCPU may get stuck in an infinite loop
4760 * if the fault is at CPL=0, it's the lesser of all evils. Exiting to
4761 * userspace will kill the guest, and letting the emulator read garbage
4762 * will yield random behavior and potentially corrupt the guest.
4764 * Simply resuming the guest is technically not a violation of the SEV
4765 * architecture. AMD's APM states that all code fetches and page table
4766 * accesses for SEV guest are encrypted, regardless of the C-Bit. The
4767 * APM also states that encrypted accesses to MMIO are "ignored", but
4768 * doesn't explicitly define "ignored", i.e. doing nothing and letting
4769 * the guest spin is technically "ignoring" the access.
4774 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4776 struct vcpu_svm *svm = to_svm(vcpu);
4778 return !gif_set(svm);
4781 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
4783 if (!sev_es_guest(vcpu->kvm))
4784 return kvm_vcpu_deliver_sipi_vector(vcpu, vector);
4786 sev_vcpu_deliver_sipi_vector(vcpu, vector);
4789 static void svm_vm_destroy(struct kvm *kvm)
4791 avic_vm_destroy(kvm);
4792 sev_vm_destroy(kvm);
4795 static int svm_vm_init(struct kvm *kvm)
4797 if (!pause_filter_count || !pause_filter_thresh)
4798 kvm->arch.pause_in_guest = true;
4801 int ret = avic_vm_init(kvm);
4809 static struct kvm_x86_ops svm_x86_ops __initdata = {
4810 .name = KBUILD_MODNAME,
4812 .check_processor_compatibility = svm_check_processor_compat,
4814 .hardware_unsetup = svm_hardware_unsetup,
4815 .hardware_enable = svm_hardware_enable,
4816 .hardware_disable = svm_hardware_disable,
4817 .has_emulated_msr = svm_has_emulated_msr,
4819 .vcpu_create = svm_vcpu_create,
4820 .vcpu_free = svm_vcpu_free,
4821 .vcpu_reset = svm_vcpu_reset,
4823 .vm_size = sizeof(struct kvm_svm),
4824 .vm_init = svm_vm_init,
4825 .vm_destroy = svm_vm_destroy,
4827 .prepare_switch_to_guest = svm_prepare_switch_to_guest,
4828 .vcpu_load = svm_vcpu_load,
4829 .vcpu_put = svm_vcpu_put,
4830 .vcpu_blocking = avic_vcpu_blocking,
4831 .vcpu_unblocking = avic_vcpu_unblocking,
4833 .update_exception_bitmap = svm_update_exception_bitmap,
4834 .get_msr_feature = svm_get_msr_feature,
4835 .get_msr = svm_get_msr,
4836 .set_msr = svm_set_msr,
4837 .get_segment_base = svm_get_segment_base,
4838 .get_segment = svm_get_segment,
4839 .set_segment = svm_set_segment,
4840 .get_cpl = svm_get_cpl,
4841 .get_cs_db_l_bits = svm_get_cs_db_l_bits,
4842 .set_cr0 = svm_set_cr0,
4843 .post_set_cr3 = sev_post_set_cr3,
4844 .is_valid_cr4 = svm_is_valid_cr4,
4845 .set_cr4 = svm_set_cr4,
4846 .set_efer = svm_set_efer,
4847 .get_idt = svm_get_idt,
4848 .set_idt = svm_set_idt,
4849 .get_gdt = svm_get_gdt,
4850 .set_gdt = svm_set_gdt,
4851 .set_dr7 = svm_set_dr7,
4852 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4853 .cache_reg = svm_cache_reg,
4854 .get_rflags = svm_get_rflags,
4855 .set_rflags = svm_set_rflags,
4856 .get_if_flag = svm_get_if_flag,
4858 .flush_tlb_all = svm_flush_tlb_all,
4859 .flush_tlb_current = svm_flush_tlb_current,
4860 .flush_tlb_gva = svm_flush_tlb_gva,
4861 .flush_tlb_guest = svm_flush_tlb_asid,
4863 .vcpu_pre_run = svm_vcpu_pre_run,
4864 .vcpu_run = svm_vcpu_run,
4865 .handle_exit = svm_handle_exit,
4866 .skip_emulated_instruction = svm_skip_emulated_instruction,
4867 .update_emulated_instruction = NULL,
4868 .set_interrupt_shadow = svm_set_interrupt_shadow,
4869 .get_interrupt_shadow = svm_get_interrupt_shadow,
4870 .patch_hypercall = svm_patch_hypercall,
4871 .inject_irq = svm_inject_irq,
4872 .inject_nmi = svm_inject_nmi,
4873 .is_vnmi_pending = svm_is_vnmi_pending,
4874 .set_vnmi_pending = svm_set_vnmi_pending,
4875 .inject_exception = svm_inject_exception,
4876 .cancel_injection = svm_cancel_injection,
4877 .interrupt_allowed = svm_interrupt_allowed,
4878 .nmi_allowed = svm_nmi_allowed,
4879 .get_nmi_mask = svm_get_nmi_mask,
4880 .set_nmi_mask = svm_set_nmi_mask,
4881 .enable_nmi_window = svm_enable_nmi_window,
4882 .enable_irq_window = svm_enable_irq_window,
4883 .update_cr8_intercept = svm_update_cr8_intercept,
4884 .set_virtual_apic_mode = avic_refresh_virtual_apic_mode,
4885 .refresh_apicv_exec_ctrl = avic_refresh_apicv_exec_ctrl,
4886 .apicv_post_state_restore = avic_apicv_post_state_restore,
4887 .required_apicv_inhibits = AVIC_REQUIRED_APICV_INHIBITS,
4889 .get_exit_info = svm_get_exit_info,
4891 .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4893 .has_wbinvd_exit = svm_has_wbinvd_exit,
4895 .get_l2_tsc_offset = svm_get_l2_tsc_offset,
4896 .get_l2_tsc_multiplier = svm_get_l2_tsc_multiplier,
4897 .write_tsc_offset = svm_write_tsc_offset,
4898 .write_tsc_multiplier = svm_write_tsc_multiplier,
4900 .load_mmu_pgd = svm_load_mmu_pgd,
4902 .check_intercept = svm_check_intercept,
4903 .handle_exit_irqoff = svm_handle_exit_irqoff,
4905 .request_immediate_exit = __kvm_request_immediate_exit,
4907 .sched_in = svm_sched_in,
4909 .nested_ops = &svm_nested_ops,
4911 .deliver_interrupt = svm_deliver_interrupt,
4912 .pi_update_irte = avic_pi_update_irte,
4913 .setup_mce = svm_setup_mce,
4915 #ifdef CONFIG_KVM_SMM
4916 .smi_allowed = svm_smi_allowed,
4917 .enter_smm = svm_enter_smm,
4918 .leave_smm = svm_leave_smm,
4919 .enable_smi_window = svm_enable_smi_window,
4922 .mem_enc_ioctl = sev_mem_enc_ioctl,
4923 .mem_enc_register_region = sev_mem_enc_register_region,
4924 .mem_enc_unregister_region = sev_mem_enc_unregister_region,
4925 .guest_memory_reclaimed = sev_guest_memory_reclaimed,
4927 .vm_copy_enc_context_from = sev_vm_copy_enc_context_from,
4928 .vm_move_enc_context_from = sev_vm_move_enc_context_from,
4930 .can_emulate_instruction = svm_can_emulate_instruction,
4932 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4934 .msr_filter_changed = svm_msr_filter_changed,
4935 .complete_emulated_msr = svm_complete_emulated_msr,
4937 .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector,
4938 .vcpu_get_apicv_inhibit_reasons = avic_vcpu_get_apicv_inhibit_reasons,
4942 * The default MMIO mask is a single bit (excluding the present bit),
4943 * which could conflict with the memory encryption bit. Check for
4944 * memory encryption support and override the default MMIO mask if
4945 * memory encryption is enabled.
4947 static __init void svm_adjust_mmio_mask(void)
4949 unsigned int enc_bit, mask_bit;
4952 /* If there is no memory encryption support, use existing mask */
4953 if (cpuid_eax(0x80000000) < 0x8000001f)
4956 /* If memory encryption is not enabled, use existing mask */
4957 rdmsrl(MSR_AMD64_SYSCFG, msr);
4958 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
4961 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
4962 mask_bit = boot_cpu_data.x86_phys_bits;
4964 /* Increment the mask bit if it is the same as the encryption bit */
4965 if (enc_bit == mask_bit)
4969 * If the mask bit location is below 52, then some bits above the
4970 * physical addressing limit will always be reserved, so use the
4971 * rsvd_bits() function to generate the mask. This mask, along with
4972 * the present bit, will be used to generate a page fault with
4975 * If the mask bit location is 52 (or above), then clear the mask.
4977 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
4979 kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
4982 static __init void svm_set_cpu_caps(void)
4986 kvm_caps.supported_perf_cap = 0;
4987 kvm_caps.supported_xss = 0;
4989 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
4991 kvm_cpu_cap_set(X86_FEATURE_SVM);
4992 kvm_cpu_cap_set(X86_FEATURE_VMCBCLEAN);
4995 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
4998 kvm_cpu_cap_set(X86_FEATURE_NPT);
5001 kvm_cpu_cap_set(X86_FEATURE_TSCRATEMSR);
5004 kvm_cpu_cap_set(X86_FEATURE_V_VMSAVE_VMLOAD);
5006 kvm_cpu_cap_set(X86_FEATURE_LBRV);
5008 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER))
5009 kvm_cpu_cap_set(X86_FEATURE_PAUSEFILTER);
5011 if (boot_cpu_has(X86_FEATURE_PFTHRESHOLD))
5012 kvm_cpu_cap_set(X86_FEATURE_PFTHRESHOLD);
5015 kvm_cpu_cap_set(X86_FEATURE_VGIF);
5018 kvm_cpu_cap_set(X86_FEATURE_VNMI);
5020 /* Nested VM can receive #VMEXIT instead of triggering #GP */
5021 kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK);
5024 /* CPUID 0x80000008 */
5025 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
5026 boot_cpu_has(X86_FEATURE_AMD_SSBD))
5027 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
5029 /* AMD PMU PERFCTR_CORE CPUID */
5030 if (enable_pmu && boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
5031 kvm_cpu_cap_set(X86_FEATURE_PERFCTR_CORE);
5033 /* CPUID 0x8000001F (SME/SEV features) */
5037 static __init int svm_hardware_setup(void)
5040 struct page *iopm_pages;
5043 unsigned int order = get_order(IOPM_SIZE);
5046 * NX is required for shadow paging and for NPT if the NX huge pages
5047 * mitigation is enabled.
5049 if (!boot_cpu_has(X86_FEATURE_NX)) {
5050 pr_err_ratelimited("NX (Execute Disable) not supported\n");
5053 kvm_enable_efer_bits(EFER_NX);
5055 iopm_pages = alloc_pages(GFP_KERNEL, order);
5060 iopm_va = page_address(iopm_pages);
5061 memset(iopm_va, 0xff, PAGE_SIZE * (1 << order));
5062 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
5064 init_msrpm_offsets();
5066 kvm_caps.supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
5067 XFEATURE_MASK_BNDCSR);
5069 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
5070 kvm_enable_efer_bits(EFER_FFXSR);
5073 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
5074 tsc_scaling = false;
5076 pr_info("TSC scaling supported\n");
5077 kvm_caps.has_tsc_control = true;
5080 kvm_caps.max_tsc_scaling_ratio = SVM_TSC_RATIO_MAX;
5081 kvm_caps.tsc_scaling_ratio_frac_bits = 32;
5083 tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX);
5085 if (boot_cpu_has(X86_FEATURE_AUTOIBRS))
5086 kvm_enable_efer_bits(EFER_AUTOIBRS);
5088 /* Check for pause filtering support */
5089 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
5090 pause_filter_count = 0;
5091 pause_filter_thresh = 0;
5092 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
5093 pause_filter_thresh = 0;
5097 pr_info("Nested Virtualization enabled\n");
5098 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
5102 * KVM's MMU doesn't support using 2-level paging for itself, and thus
5103 * NPT isn't supported if the host is using 2-level paging since host
5104 * CR4 is unchanged on VMRUN.
5106 if (!IS_ENABLED(CONFIG_X86_64) && !IS_ENABLED(CONFIG_X86_PAE))
5107 npt_enabled = false;
5109 if (!boot_cpu_has(X86_FEATURE_NPT))
5110 npt_enabled = false;
5112 /* Force VM NPT level equal to the host's paging level */
5113 kvm_configure_mmu(npt_enabled, get_npt_level(),
5114 get_npt_level(), PG_LEVEL_1G);
5115 pr_info("Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
5117 /* Setup shadow_me_value and shadow_me_mask */
5118 kvm_mmu_set_me_spte_mask(sme_me_mask, sme_me_mask);
5120 svm_adjust_mmio_mask();
5123 * Note, SEV setup consumes npt_enabled and enable_mmio_caching (which
5124 * may be modified by svm_adjust_mmio_mask()).
5126 sev_hardware_setup();
5128 svm_hv_hardware_setup();
5130 for_each_possible_cpu(cpu) {
5131 r = svm_cpu_init(cpu);
5137 if (!boot_cpu_has(X86_FEATURE_NRIPS))
5141 enable_apicv = avic = avic && avic_hardware_setup();
5143 if (!enable_apicv) {
5144 svm_x86_ops.vcpu_blocking = NULL;
5145 svm_x86_ops.vcpu_unblocking = NULL;
5146 svm_x86_ops.vcpu_get_apicv_inhibit_reasons = NULL;
5147 } else if (!x2avic_enabled) {
5148 svm_x86_ops.allow_apicv_in_x2apic_without_x2apic_virtualization = true;
5153 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
5154 !IS_ENABLED(CONFIG_X86_64)) {
5157 pr_info("Virtual VMLOAD VMSAVE supported\n");
5161 if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
5162 svm_gp_erratum_intercept = false;
5165 if (!boot_cpu_has(X86_FEATURE_VGIF))
5168 pr_info("Virtual GIF supported\n");
5171 vnmi = vgif && vnmi && boot_cpu_has(X86_FEATURE_VNMI);
5173 pr_info("Virtual NMI enabled\n");
5176 svm_x86_ops.is_vnmi_pending = NULL;
5177 svm_x86_ops.set_vnmi_pending = NULL;
5182 if (!boot_cpu_has(X86_FEATURE_LBRV))
5185 pr_info("LBR virtualization supported\n");
5189 pr_info("PMU virtualization is disabled\n");
5194 * It seems that on AMD processors PTE's accessed bit is
5195 * being set by the CPU hardware before the NPF vmexit.
5196 * This is not expected behaviour and our tests fail because
5198 * A workaround here is to disable support for
5199 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
5200 * In this case userspace can know if there is support using
5201 * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
5203 * If future AMD CPU models change the behaviour described above,
5204 * this variable can be changed accordingly
5206 allow_smaller_maxphyaddr = !npt_enabled;
5211 svm_hardware_unsetup();
5216 static struct kvm_x86_init_ops svm_init_ops __initdata = {
5217 .hardware_setup = svm_hardware_setup,
5219 .runtime_ops = &svm_x86_ops,
5220 .pmu_ops = &amd_pmu_ops,
5223 static int __init svm_init(void)
5227 __unused_size_checks();
5229 if (!kvm_is_svm_supported())
5232 r = kvm_x86_vendor_init(&svm_init_ops);
5237 * Common KVM initialization _must_ come last, after this, /dev/kvm is
5238 * exposed to userspace!
5240 r = kvm_init(sizeof(struct vcpu_svm), __alignof__(struct vcpu_svm),
5248 kvm_x86_vendor_exit();
5252 static void __exit svm_exit(void)
5255 kvm_x86_vendor_exit();
5258 module_init(svm_init)
5259 module_exit(svm_exit)