1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3 #include <linux/kvm_host.h>
7 #include "kvm_cache_regs.h"
13 #include <linux/module.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/kernel.h>
16 #include <linux/vmalloc.h>
17 #include <linux/highmem.h>
18 #include <linux/amd-iommu.h>
19 #include <linux/sched.h>
20 #include <linux/trace_events.h>
21 #include <linux/slab.h>
22 #include <linux/hashtable.h>
23 #include <linux/objtool.h>
24 #include <linux/psp-sev.h>
25 #include <linux/file.h>
26 #include <linux/pagemap.h>
27 #include <linux/swap.h>
28 #include <linux/rwsem.h>
29 #include <linux/cc_platform.h>
32 #include <asm/perf_event.h>
33 #include <asm/tlbflush.h>
35 #include <asm/debugreg.h>
36 #include <asm/kvm_para.h>
37 #include <asm/irq_remapping.h>
38 #include <asm/spec-ctrl.h>
39 #include <asm/cpu_device_id.h>
40 #include <asm/traps.h>
41 #include <asm/fpu/api.h>
43 #include <asm/virtext.h>
49 #include "kvm_onhyperv.h"
50 #include "svm_onhyperv.h"
52 MODULE_AUTHOR("Qumranet");
53 MODULE_LICENSE("GPL");
56 static const struct x86_cpu_id svm_cpu_id[] = {
57 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
60 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
63 #define SEG_TYPE_LDT 2
64 #define SEG_TYPE_BUSY_TSS16 3
66 static bool erratum_383_found __read_mostly;
68 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
71 * Set osvw_len to higher value when updated Revision Guides
72 * are published and we know what the new status bits are
74 static uint64_t osvw_len = 4, osvw_status;
76 static DEFINE_PER_CPU(u64, current_tsc_ratio);
78 #define X2APIC_MSR(x) (APIC_BASE_MSR + (x >> 4))
80 static const struct svm_direct_access_msrs {
81 u32 index; /* Index of the MSR */
82 bool always; /* True if intercept is initially cleared */
83 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
84 { .index = MSR_STAR, .always = true },
85 { .index = MSR_IA32_SYSENTER_CS, .always = true },
86 { .index = MSR_IA32_SYSENTER_EIP, .always = false },
87 { .index = MSR_IA32_SYSENTER_ESP, .always = false },
89 { .index = MSR_GS_BASE, .always = true },
90 { .index = MSR_FS_BASE, .always = true },
91 { .index = MSR_KERNEL_GS_BASE, .always = true },
92 { .index = MSR_LSTAR, .always = true },
93 { .index = MSR_CSTAR, .always = true },
94 { .index = MSR_SYSCALL_MASK, .always = true },
96 { .index = MSR_IA32_SPEC_CTRL, .always = false },
97 { .index = MSR_IA32_PRED_CMD, .always = false },
98 { .index = MSR_IA32_FLUSH_CMD, .always = false },
99 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
100 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
101 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
102 { .index = MSR_IA32_LASTINTTOIP, .always = false },
103 { .index = MSR_EFER, .always = false },
104 { .index = MSR_IA32_CR_PAT, .always = false },
105 { .index = MSR_AMD64_SEV_ES_GHCB, .always = true },
106 { .index = MSR_TSC_AUX, .always = false },
107 { .index = X2APIC_MSR(APIC_ID), .always = false },
108 { .index = X2APIC_MSR(APIC_LVR), .always = false },
109 { .index = X2APIC_MSR(APIC_TASKPRI), .always = false },
110 { .index = X2APIC_MSR(APIC_ARBPRI), .always = false },
111 { .index = X2APIC_MSR(APIC_PROCPRI), .always = false },
112 { .index = X2APIC_MSR(APIC_EOI), .always = false },
113 { .index = X2APIC_MSR(APIC_RRR), .always = false },
114 { .index = X2APIC_MSR(APIC_LDR), .always = false },
115 { .index = X2APIC_MSR(APIC_DFR), .always = false },
116 { .index = X2APIC_MSR(APIC_SPIV), .always = false },
117 { .index = X2APIC_MSR(APIC_ISR), .always = false },
118 { .index = X2APIC_MSR(APIC_TMR), .always = false },
119 { .index = X2APIC_MSR(APIC_IRR), .always = false },
120 { .index = X2APIC_MSR(APIC_ESR), .always = false },
121 { .index = X2APIC_MSR(APIC_ICR), .always = false },
122 { .index = X2APIC_MSR(APIC_ICR2), .always = false },
126 * AMD does not virtualize APIC TSC-deadline timer mode, but it is
127 * emulated by KVM. When setting APIC LVTT (0x832) register bit 18,
128 * the AVIC hardware would generate GP fault. Therefore, always
129 * intercept the MSR 0x832, and do not setup direct_access_msr.
131 { .index = X2APIC_MSR(APIC_LVTTHMR), .always = false },
132 { .index = X2APIC_MSR(APIC_LVTPC), .always = false },
133 { .index = X2APIC_MSR(APIC_LVT0), .always = false },
134 { .index = X2APIC_MSR(APIC_LVT1), .always = false },
135 { .index = X2APIC_MSR(APIC_LVTERR), .always = false },
136 { .index = X2APIC_MSR(APIC_TMICT), .always = false },
137 { .index = X2APIC_MSR(APIC_TMCCT), .always = false },
138 { .index = X2APIC_MSR(APIC_TDCR), .always = false },
139 { .index = MSR_INVALID, .always = false },
143 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
144 * pause_filter_count: On processors that support Pause filtering(indicated
145 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
146 * count value. On VMRUN this value is loaded into an internal counter.
147 * Each time a pause instruction is executed, this counter is decremented
148 * until it reaches zero at which time a #VMEXIT is generated if pause
149 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
150 * Intercept Filtering for more details.
151 * This also indicate if ple logic enabled.
153 * pause_filter_thresh: In addition, some processor families support advanced
154 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
155 * the amount of time a guest is allowed to execute in a pause loop.
156 * In this mode, a 16-bit pause filter threshold field is added in the
157 * VMCB. The threshold value is a cycle count that is used to reset the
158 * pause counter. As with simple pause filtering, VMRUN loads the pause
159 * count value from VMCB into an internal counter. Then, on each pause
160 * instruction the hardware checks the elapsed number of cycles since
161 * the most recent pause instruction against the pause filter threshold.
162 * If the elapsed cycle count is greater than the pause filter threshold,
163 * then the internal pause count is reloaded from the VMCB and execution
164 * continues. If the elapsed cycle count is less than the pause filter
165 * threshold, then the internal pause count is decremented. If the count
166 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
167 * triggered. If advanced pause filtering is supported and pause filter
168 * threshold field is set to zero, the filter will operate in the simpler,
172 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
173 module_param(pause_filter_thresh, ushort, 0444);
175 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
176 module_param(pause_filter_count, ushort, 0444);
178 /* Default doubles per-vcpu window every exit. */
179 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
180 module_param(pause_filter_count_grow, ushort, 0444);
182 /* Default resets per-vcpu window every exit to pause_filter_count. */
183 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
184 module_param(pause_filter_count_shrink, ushort, 0444);
186 /* Default is to compute the maximum so we can never overflow. */
187 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
188 module_param(pause_filter_count_max, ushort, 0444);
191 * Use nested page tables by default. Note, NPT may get forced off by
192 * svm_hardware_setup() if it's unsupported by hardware or the host kernel.
194 bool npt_enabled = true;
195 module_param_named(npt, npt_enabled, bool, 0444);
197 /* allow nested virtualization in KVM/SVM */
198 static int nested = true;
199 module_param(nested, int, S_IRUGO);
201 /* enable/disable Next RIP Save */
202 static int nrips = true;
203 module_param(nrips, int, 0444);
205 /* enable/disable Virtual VMLOAD VMSAVE */
206 static int vls = true;
207 module_param(vls, int, 0444);
209 /* enable/disable Virtual GIF */
211 module_param(vgif, int, 0444);
213 /* enable/disable LBR virtualization */
214 static int lbrv = true;
215 module_param(lbrv, int, 0444);
217 static int tsc_scaling = true;
218 module_param(tsc_scaling, int, 0444);
221 * enable / disable AVIC. Because the defaults differ for APICv
222 * support between VMX and SVM we cannot use module_param_named.
225 module_param(avic, bool, 0444);
227 bool __read_mostly dump_invalid_vmcb;
228 module_param(dump_invalid_vmcb, bool, 0644);
231 bool intercept_smi = true;
232 module_param(intercept_smi, bool, 0444);
235 static bool svm_gp_erratum_intercept = true;
237 static u8 rsm_ins_bytes[] = "\x0f\xaa";
239 static unsigned long iopm_base;
241 struct kvm_ldttss_desc {
244 unsigned base1:8, type:5, dpl:2, p:1;
245 unsigned limit1:4, zero0:3, g:1, base2:8;
248 } __attribute__((packed));
250 DEFINE_PER_CPU(struct svm_cpu_data, svm_data);
253 * Only MSR_TSC_AUX is switched via the user return hook. EFER is switched via
254 * the VMCB, and the SYSCALL/SYSENTER MSRs are handled by VMLOAD/VMSAVE.
256 * RDTSCP and RDPID are not used in the kernel, specifically to allow KVM to
257 * defer the restoration of TSC_AUX until the CPU returns to userspace.
259 static int tsc_aux_uret_slot __read_mostly = -1;
261 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
263 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
264 #define MSRS_RANGE_SIZE 2048
265 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
267 u32 svm_msrpm_offset(u32 msr)
272 for (i = 0; i < NUM_MSR_MAPS; i++) {
273 if (msr < msrpm_ranges[i] ||
274 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
277 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
278 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
280 /* Now we have the u8 offset - but need the u32 offset */
284 /* MSR not in any range */
288 static void svm_flush_tlb_current(struct kvm_vcpu *vcpu);
290 static int get_npt_level(void)
293 return pgtable_l5_enabled() ? PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
295 return PT32E_ROOT_LEVEL;
299 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
301 struct vcpu_svm *svm = to_svm(vcpu);
302 u64 old_efer = vcpu->arch.efer;
303 vcpu->arch.efer = efer;
306 /* Shadow paging assumes NX to be available. */
309 if (!(efer & EFER_LMA))
313 if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
314 if (!(efer & EFER_SVME)) {
315 svm_leave_nested(vcpu);
316 svm_set_gif(svm, true);
317 /* #GP intercept is still needed for vmware backdoor */
318 if (!enable_vmware_backdoor)
319 clr_exception_intercept(svm, GP_VECTOR);
322 * Free the nested guest state, unless we are in SMM.
323 * In this case we will return to the nested guest
324 * as soon as we leave SMM.
327 svm_free_nested(svm);
330 int ret = svm_allocate_nested(svm);
333 vcpu->arch.efer = old_efer;
338 * Never intercept #GP for SEV guests, KVM can't
339 * decrypt guest memory to workaround the erratum.
341 if (svm_gp_erratum_intercept && !sev_guest(vcpu->kvm))
342 set_exception_intercept(svm, GP_VECTOR);
346 svm->vmcb->save.efer = efer | EFER_SVME;
347 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
351 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
353 struct vcpu_svm *svm = to_svm(vcpu);
356 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
357 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
361 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
363 struct vcpu_svm *svm = to_svm(vcpu);
366 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
368 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
372 static int __svm_skip_emulated_instruction(struct kvm_vcpu *vcpu,
373 bool commit_side_effects)
375 struct vcpu_svm *svm = to_svm(vcpu);
376 unsigned long old_rflags;
379 * SEV-ES does not expose the next RIP. The RIP update is controlled by
380 * the type of exit and the #VC handler in the guest.
382 if (sev_es_guest(vcpu->kvm))
385 if (nrips && svm->vmcb->control.next_rip != 0) {
386 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
387 svm->next_rip = svm->vmcb->control.next_rip;
390 if (!svm->next_rip) {
391 if (unlikely(!commit_side_effects))
392 old_rflags = svm->vmcb->save.rflags;
394 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
397 if (unlikely(!commit_side_effects))
398 svm->vmcb->save.rflags = old_rflags;
400 kvm_rip_write(vcpu, svm->next_rip);
404 if (likely(commit_side_effects))
405 svm_set_interrupt_shadow(vcpu, 0);
410 static int svm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
412 return __svm_skip_emulated_instruction(vcpu, true);
415 static int svm_update_soft_interrupt_rip(struct kvm_vcpu *vcpu)
417 unsigned long rip, old_rip = kvm_rip_read(vcpu);
418 struct vcpu_svm *svm = to_svm(vcpu);
421 * Due to architectural shortcomings, the CPU doesn't always provide
422 * NextRIP, e.g. if KVM intercepted an exception that occurred while
423 * the CPU was vectoring an INTO/INT3 in the guest. Temporarily skip
424 * the instruction even if NextRIP is supported to acquire the next
425 * RIP so that it can be shoved into the NextRIP field, otherwise
426 * hardware will fail to advance guest RIP during event injection.
427 * Drop the exception/interrupt if emulation fails and effectively
428 * retry the instruction, it's the least awful option. If NRIPS is
429 * in use, the skip must not commit any side effects such as clearing
430 * the interrupt shadow or RFLAGS.RF.
432 if (!__svm_skip_emulated_instruction(vcpu, !nrips))
435 rip = kvm_rip_read(vcpu);
438 * Save the injection information, even when using next_rip, as the
439 * VMCB's next_rip will be lost (cleared on VM-Exit) if the injection
440 * doesn't complete due to a VM-Exit occurring while the CPU is
441 * vectoring the event. Decoding the instruction isn't guaranteed to
442 * work as there may be no backing instruction, e.g. if the event is
443 * being injected by L1 for L2, or if the guest is patching INT3 into
444 * a different instruction.
446 svm->soft_int_injected = true;
447 svm->soft_int_csbase = svm->vmcb->save.cs.base;
448 svm->soft_int_old_rip = old_rip;
449 svm->soft_int_next_rip = rip;
452 kvm_rip_write(vcpu, old_rip);
454 if (static_cpu_has(X86_FEATURE_NRIPS))
455 svm->vmcb->control.next_rip = rip;
460 static void svm_inject_exception(struct kvm_vcpu *vcpu)
462 struct kvm_queued_exception *ex = &vcpu->arch.exception;
463 struct vcpu_svm *svm = to_svm(vcpu);
465 kvm_deliver_exception_payload(vcpu, ex);
467 if (kvm_exception_is_soft(ex->vector) &&
468 svm_update_soft_interrupt_rip(vcpu))
471 svm->vmcb->control.event_inj = ex->vector
473 | (ex->has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
474 | SVM_EVTINJ_TYPE_EXEPT;
475 svm->vmcb->control.event_inj_err = ex->error_code;
478 static void svm_init_erratum_383(void)
484 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
487 /* Use _safe variants to not break nested virtualization */
488 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
494 low = lower_32_bits(val);
495 high = upper_32_bits(val);
497 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
499 erratum_383_found = true;
502 static void svm_init_osvw(struct kvm_vcpu *vcpu)
505 * Guests should see errata 400 and 415 as fixed (assuming that
506 * HLT and IO instructions are intercepted).
508 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
509 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
512 * By increasing VCPU's osvw.length to 3 we are telling the guest that
513 * all osvw.status bits inside that length, including bit 0 (which is
514 * reserved for erratum 298), are valid. However, if host processor's
515 * osvw_len is 0 then osvw_status[0] carries no information. We need to
516 * be conservative here and therefore we tell the guest that erratum 298
517 * is present (because we really don't know).
519 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
520 vcpu->arch.osvw.status |= 1;
523 static bool kvm_is_svm_supported(void)
525 int cpu = raw_smp_processor_id();
529 if (!cpu_has_svm(&msg)) {
530 pr_err("SVM not supported by CPU %d, %s\n", cpu, msg);
534 if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) {
535 pr_info("KVM is unsupported when running as an SEV guest\n");
539 rdmsrl(MSR_VM_CR, vm_cr);
540 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) {
541 pr_err("SVM disabled (by BIOS) in MSR_VM_CR on CPU %d\n", cpu);
548 static int svm_check_processor_compat(void)
550 if (!kvm_is_svm_supported())
556 void __svm_write_tsc_multiplier(u64 multiplier)
560 if (multiplier == __this_cpu_read(current_tsc_ratio))
563 wrmsrl(MSR_AMD64_TSC_RATIO, multiplier);
564 __this_cpu_write(current_tsc_ratio, multiplier);
569 static void svm_hardware_disable(void)
571 /* Make sure we clean up behind us */
573 __svm_write_tsc_multiplier(SVM_TSC_RATIO_DEFAULT);
577 amd_pmu_disable_virt();
580 static int svm_hardware_enable(void)
583 struct svm_cpu_data *sd;
585 struct desc_struct *gdt;
586 int me = raw_smp_processor_id();
588 rdmsrl(MSR_EFER, efer);
589 if (efer & EFER_SVME)
592 sd = per_cpu_ptr(&svm_data, me);
593 sd->asid_generation = 1;
594 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
595 sd->next_asid = sd->max_asid + 1;
596 sd->min_asid = max_sev_asid + 1;
598 gdt = get_current_gdt_rw();
599 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
601 wrmsrl(MSR_EFER, efer | EFER_SVME);
603 wrmsrl(MSR_VM_HSAVE_PA, sd->save_area_pa);
605 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
607 * Set the default value, even if we don't use TSC scaling
608 * to avoid having stale value in the msr
610 __svm_write_tsc_multiplier(SVM_TSC_RATIO_DEFAULT);
617 * Note that it is possible to have a system with mixed processor
618 * revisions and therefore different OSVW bits. If bits are not the same
619 * on different processors then choose the worst case (i.e. if erratum
620 * is present on one processor and not on another then assume that the
621 * erratum is present everywhere).
623 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
624 uint64_t len, status = 0;
627 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
629 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
633 osvw_status = osvw_len = 0;
637 osvw_status |= status;
638 osvw_status &= (1ULL << osvw_len) - 1;
641 osvw_status = osvw_len = 0;
643 svm_init_erratum_383();
645 amd_pmu_enable_virt();
650 static void svm_cpu_uninit(int cpu)
652 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu);
657 kfree(sd->sev_vmcbs);
658 __free_page(sd->save_area);
659 sd->save_area_pa = 0;
660 sd->save_area = NULL;
663 static int svm_cpu_init(int cpu)
665 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu);
668 memset(sd, 0, sizeof(struct svm_cpu_data));
669 sd->save_area = alloc_page(GFP_KERNEL | __GFP_ZERO);
673 ret = sev_cpu_init(sd);
677 sd->save_area_pa = __sme_page_pa(sd->save_area);
681 __free_page(sd->save_area);
682 sd->save_area = NULL;
687 static int direct_access_msr_slot(u32 msr)
691 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
692 if (direct_access_msrs[i].index == msr)
698 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
701 struct vcpu_svm *svm = to_svm(vcpu);
702 int slot = direct_access_msr_slot(msr);
707 /* Set the shadow bitmaps to the desired intercept states */
709 set_bit(slot, svm->shadow_msr_intercept.read);
711 clear_bit(slot, svm->shadow_msr_intercept.read);
714 set_bit(slot, svm->shadow_msr_intercept.write);
716 clear_bit(slot, svm->shadow_msr_intercept.write);
719 static bool valid_msr_intercept(u32 index)
721 return direct_access_msr_slot(index) != -ENOENT;
724 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
732 * For non-nested case:
733 * If the L01 MSR bitmap does not intercept the MSR, then we need to
737 * If the L02 MSR bitmap does not intercept the MSR, then we need to
740 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
743 offset = svm_msrpm_offset(msr);
744 bit_write = 2 * (msr & 0x0f) + 1;
747 BUG_ON(offset == MSR_INVALID);
749 return !!test_bit(bit_write, &tmp);
752 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
753 u32 msr, int read, int write)
755 struct vcpu_svm *svm = to_svm(vcpu);
756 u8 bit_read, bit_write;
761 * If this warning triggers extend the direct_access_msrs list at the
762 * beginning of the file
764 WARN_ON(!valid_msr_intercept(msr));
766 /* Enforce non allowed MSRs to trap */
767 if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
770 if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
773 offset = svm_msrpm_offset(msr);
774 bit_read = 2 * (msr & 0x0f);
775 bit_write = 2 * (msr & 0x0f) + 1;
778 BUG_ON(offset == MSR_INVALID);
780 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
781 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
785 svm_hv_vmcb_dirty_nested_enlightenments(vcpu);
786 svm->nested.force_msr_bitmap_recalc = true;
789 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
792 set_shadow_msr_intercept(vcpu, msr, read, write);
793 set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
796 u32 *svm_vcpu_alloc_msrpm(void)
798 unsigned int order = get_order(MSRPM_SIZE);
799 struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, order);
805 msrpm = page_address(pages);
806 memset(msrpm, 0xff, PAGE_SIZE * (1 << order));
811 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
815 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
816 if (!direct_access_msrs[i].always)
818 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
822 void svm_set_x2apic_msr_interception(struct vcpu_svm *svm, bool intercept)
826 if (intercept == svm->x2avic_msrs_intercepted)
829 if (!x2avic_enabled ||
830 !apic_x2apic_mode(svm->vcpu.arch.apic))
833 for (i = 0; i < MAX_DIRECT_ACCESS_MSRS; i++) {
834 int index = direct_access_msrs[i].index;
836 if ((index < APIC_BASE_MSR) ||
837 (index > APIC_BASE_MSR + 0xff))
839 set_msr_interception(&svm->vcpu, svm->msrpm, index,
840 !intercept, !intercept);
843 svm->x2avic_msrs_intercepted = intercept;
846 void svm_vcpu_free_msrpm(u32 *msrpm)
848 __free_pages(virt_to_page(msrpm), get_order(MSRPM_SIZE));
851 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
853 struct vcpu_svm *svm = to_svm(vcpu);
857 * Set intercept permissions for all direct access MSRs again. They
858 * will automatically get filtered through the MSR filter, so we are
859 * back in sync after this.
861 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
862 u32 msr = direct_access_msrs[i].index;
863 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
864 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
866 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
870 static void add_msr_offset(u32 offset)
874 for (i = 0; i < MSRPM_OFFSETS; ++i) {
876 /* Offset already in list? */
877 if (msrpm_offsets[i] == offset)
880 /* Slot used by another offset? */
881 if (msrpm_offsets[i] != MSR_INVALID)
884 /* Add offset to list */
885 msrpm_offsets[i] = offset;
891 * If this BUG triggers the msrpm_offsets table has an overflow. Just
892 * increase MSRPM_OFFSETS in this case.
897 static void init_msrpm_offsets(void)
901 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
903 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
906 offset = svm_msrpm_offset(direct_access_msrs[i].index);
907 BUG_ON(offset == MSR_INVALID);
909 add_msr_offset(offset);
913 void svm_copy_lbrs(struct vmcb *to_vmcb, struct vmcb *from_vmcb)
915 to_vmcb->save.dbgctl = from_vmcb->save.dbgctl;
916 to_vmcb->save.br_from = from_vmcb->save.br_from;
917 to_vmcb->save.br_to = from_vmcb->save.br_to;
918 to_vmcb->save.last_excp_from = from_vmcb->save.last_excp_from;
919 to_vmcb->save.last_excp_to = from_vmcb->save.last_excp_to;
921 vmcb_mark_dirty(to_vmcb, VMCB_LBR);
924 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
926 struct vcpu_svm *svm = to_svm(vcpu);
928 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
929 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
930 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
931 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
932 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
934 /* Move the LBR msrs to the vmcb02 so that the guest can see them. */
935 if (is_guest_mode(vcpu))
936 svm_copy_lbrs(svm->vmcb, svm->vmcb01.ptr);
939 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
941 struct vcpu_svm *svm = to_svm(vcpu);
943 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
944 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
945 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
946 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
947 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
950 * Move the LBR msrs back to the vmcb01 to avoid copying them
951 * on nested guest entries.
953 if (is_guest_mode(vcpu))
954 svm_copy_lbrs(svm->vmcb01.ptr, svm->vmcb);
957 static int svm_get_lbr_msr(struct vcpu_svm *svm, u32 index)
960 * If the LBR virtualization is disabled, the LBR msrs are always
961 * kept in the vmcb01 to avoid copying them on nested guest entries.
963 * If nested, and the LBR virtualization is enabled/disabled, the msrs
964 * are moved between the vmcb01 and vmcb02 as needed.
967 (svm->vmcb->control.virt_ext & LBR_CTL_ENABLE_MASK) ?
968 svm->vmcb : svm->vmcb01.ptr;
971 case MSR_IA32_DEBUGCTLMSR:
972 return vmcb->save.dbgctl;
973 case MSR_IA32_LASTBRANCHFROMIP:
974 return vmcb->save.br_from;
975 case MSR_IA32_LASTBRANCHTOIP:
976 return vmcb->save.br_to;
977 case MSR_IA32_LASTINTFROMIP:
978 return vmcb->save.last_excp_from;
979 case MSR_IA32_LASTINTTOIP:
980 return vmcb->save.last_excp_to;
982 KVM_BUG(false, svm->vcpu.kvm,
983 "%s: Unknown MSR 0x%x", __func__, index);
988 void svm_update_lbrv(struct kvm_vcpu *vcpu)
990 struct vcpu_svm *svm = to_svm(vcpu);
992 bool enable_lbrv = svm_get_lbr_msr(svm, MSR_IA32_DEBUGCTLMSR) &
995 bool current_enable_lbrv = !!(svm->vmcb->control.virt_ext &
996 LBR_CTL_ENABLE_MASK);
998 if (unlikely(is_guest_mode(vcpu) && svm->lbrv_enabled))
999 if (unlikely(svm->nested.ctl.virt_ext & LBR_CTL_ENABLE_MASK))
1002 if (enable_lbrv == current_enable_lbrv)
1006 svm_enable_lbrv(vcpu);
1008 svm_disable_lbrv(vcpu);
1011 void disable_nmi_singlestep(struct vcpu_svm *svm)
1013 svm->nmi_singlestep = false;
1015 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1016 /* Clear our flags if they were not set by the guest */
1017 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1018 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1019 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1020 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1024 static void grow_ple_window(struct kvm_vcpu *vcpu)
1026 struct vcpu_svm *svm = to_svm(vcpu);
1027 struct vmcb_control_area *control = &svm->vmcb->control;
1028 int old = control->pause_filter_count;
1030 if (kvm_pause_in_guest(vcpu->kvm))
1033 control->pause_filter_count = __grow_ple_window(old,
1035 pause_filter_count_grow,
1036 pause_filter_count_max);
1038 if (control->pause_filter_count != old) {
1039 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1040 trace_kvm_ple_window_update(vcpu->vcpu_id,
1041 control->pause_filter_count, old);
1045 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1047 struct vcpu_svm *svm = to_svm(vcpu);
1048 struct vmcb_control_area *control = &svm->vmcb->control;
1049 int old = control->pause_filter_count;
1051 if (kvm_pause_in_guest(vcpu->kvm))
1054 control->pause_filter_count =
1055 __shrink_ple_window(old,
1057 pause_filter_count_shrink,
1058 pause_filter_count);
1059 if (control->pause_filter_count != old) {
1060 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1061 trace_kvm_ple_window_update(vcpu->vcpu_id,
1062 control->pause_filter_count, old);
1066 static void svm_hardware_unsetup(void)
1070 sev_hardware_unsetup();
1072 for_each_possible_cpu(cpu)
1073 svm_cpu_uninit(cpu);
1075 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT),
1076 get_order(IOPM_SIZE));
1080 static void init_seg(struct vmcb_seg *seg)
1083 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1084 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1085 seg->limit = 0xffff;
1089 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1092 seg->attrib = SVM_SELECTOR_P_MASK | type;
1093 seg->limit = 0xffff;
1097 static u64 svm_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1099 struct vcpu_svm *svm = to_svm(vcpu);
1101 return svm->nested.ctl.tsc_offset;
1104 static u64 svm_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1106 struct vcpu_svm *svm = to_svm(vcpu);
1108 return svm->tsc_ratio_msr;
1111 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1113 struct vcpu_svm *svm = to_svm(vcpu);
1115 svm->vmcb01.ptr->control.tsc_offset = vcpu->arch.l1_tsc_offset;
1116 svm->vmcb->control.tsc_offset = offset;
1117 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1120 static void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1122 __svm_write_tsc_multiplier(multiplier);
1126 /* Evaluate instruction intercepts that depend on guest CPUID features. */
1127 static void svm_recalc_instruction_intercepts(struct kvm_vcpu *vcpu,
1128 struct vcpu_svm *svm)
1131 * Intercept INVPCID if shadow paging is enabled to sync/free shadow
1132 * roots, or if INVPCID is disabled in the guest to inject #UD.
1134 if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1136 !guest_cpuid_has(&svm->vcpu, X86_FEATURE_INVPCID))
1137 svm_set_intercept(svm, INTERCEPT_INVPCID);
1139 svm_clr_intercept(svm, INTERCEPT_INVPCID);
1142 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) {
1143 if (guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1144 svm_clr_intercept(svm, INTERCEPT_RDTSCP);
1146 svm_set_intercept(svm, INTERCEPT_RDTSCP);
1150 static inline void init_vmcb_after_set_cpuid(struct kvm_vcpu *vcpu)
1152 struct vcpu_svm *svm = to_svm(vcpu);
1154 if (guest_cpuid_is_intel(vcpu)) {
1156 * We must intercept SYSENTER_EIP and SYSENTER_ESP
1157 * accesses because the processor only stores 32 bits.
1158 * For the same reason we cannot use virtual VMLOAD/VMSAVE.
1160 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1161 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1162 svm->vmcb->control.virt_ext &= ~VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1164 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 0, 0);
1165 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 0, 0);
1167 svm->v_vmload_vmsave_enabled = false;
1170 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1171 * in VMCB and clear intercepts to avoid #VMEXIT.
1174 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1175 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
1176 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1178 /* No need to intercept these MSRs */
1179 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
1180 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
1184 static void init_vmcb(struct kvm_vcpu *vcpu)
1186 struct vcpu_svm *svm = to_svm(vcpu);
1187 struct vmcb *vmcb = svm->vmcb01.ptr;
1188 struct vmcb_control_area *control = &vmcb->control;
1189 struct vmcb_save_area *save = &vmcb->save;
1191 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1192 svm_set_intercept(svm, INTERCEPT_CR3_READ);
1193 svm_set_intercept(svm, INTERCEPT_CR4_READ);
1194 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1195 svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1196 svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1197 if (!kvm_vcpu_apicv_active(vcpu))
1198 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1200 set_dr_intercepts(svm);
1202 set_exception_intercept(svm, PF_VECTOR);
1203 set_exception_intercept(svm, UD_VECTOR);
1204 set_exception_intercept(svm, MC_VECTOR);
1205 set_exception_intercept(svm, AC_VECTOR);
1206 set_exception_intercept(svm, DB_VECTOR);
1208 * Guest access to VMware backdoor ports could legitimately
1209 * trigger #GP because of TSS I/O permission bitmap.
1210 * We intercept those #GP and allow access to them anyway
1211 * as VMware does. Don't intercept #GP for SEV guests as KVM can't
1212 * decrypt guest memory to decode the faulting instruction.
1214 if (enable_vmware_backdoor && !sev_guest(vcpu->kvm))
1215 set_exception_intercept(svm, GP_VECTOR);
1217 svm_set_intercept(svm, INTERCEPT_INTR);
1218 svm_set_intercept(svm, INTERCEPT_NMI);
1221 svm_set_intercept(svm, INTERCEPT_SMI);
1223 svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1224 svm_set_intercept(svm, INTERCEPT_RDPMC);
1225 svm_set_intercept(svm, INTERCEPT_CPUID);
1226 svm_set_intercept(svm, INTERCEPT_INVD);
1227 svm_set_intercept(svm, INTERCEPT_INVLPG);
1228 svm_set_intercept(svm, INTERCEPT_INVLPGA);
1229 svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1230 svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1231 svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1232 svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1233 svm_set_intercept(svm, INTERCEPT_VMRUN);
1234 svm_set_intercept(svm, INTERCEPT_VMMCALL);
1235 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1236 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1237 svm_set_intercept(svm, INTERCEPT_STGI);
1238 svm_set_intercept(svm, INTERCEPT_CLGI);
1239 svm_set_intercept(svm, INTERCEPT_SKINIT);
1240 svm_set_intercept(svm, INTERCEPT_WBINVD);
1241 svm_set_intercept(svm, INTERCEPT_XSETBV);
1242 svm_set_intercept(svm, INTERCEPT_RDPRU);
1243 svm_set_intercept(svm, INTERCEPT_RSM);
1245 if (!kvm_mwait_in_guest(vcpu->kvm)) {
1246 svm_set_intercept(svm, INTERCEPT_MONITOR);
1247 svm_set_intercept(svm, INTERCEPT_MWAIT);
1250 if (!kvm_hlt_in_guest(vcpu->kvm))
1251 svm_set_intercept(svm, INTERCEPT_HLT);
1253 control->iopm_base_pa = __sme_set(iopm_base);
1254 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1255 control->int_ctl = V_INTR_MASKING_MASK;
1257 init_seg(&save->es);
1258 init_seg(&save->ss);
1259 init_seg(&save->ds);
1260 init_seg(&save->fs);
1261 init_seg(&save->gs);
1263 save->cs.selector = 0xf000;
1264 save->cs.base = 0xffff0000;
1265 /* Executable/Readable Code Segment */
1266 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1267 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1268 save->cs.limit = 0xffff;
1270 save->gdtr.base = 0;
1271 save->gdtr.limit = 0xffff;
1272 save->idtr.base = 0;
1273 save->idtr.limit = 0xffff;
1275 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1276 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1279 /* Setup VMCB for Nested Paging */
1280 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1281 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1282 clr_exception_intercept(svm, PF_VECTOR);
1283 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1284 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1285 save->g_pat = vcpu->arch.pat;
1288 svm->current_vmcb->asid_generation = 0;
1291 svm->nested.vmcb12_gpa = INVALID_GPA;
1292 svm->nested.last_vmcb12_gpa = INVALID_GPA;
1294 if (!kvm_pause_in_guest(vcpu->kvm)) {
1295 control->pause_filter_count = pause_filter_count;
1296 if (pause_filter_thresh)
1297 control->pause_filter_thresh = pause_filter_thresh;
1298 svm_set_intercept(svm, INTERCEPT_PAUSE);
1300 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1303 svm_recalc_instruction_intercepts(vcpu, svm);
1306 * If the host supports V_SPEC_CTRL then disable the interception
1307 * of MSR_IA32_SPEC_CTRL.
1309 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
1310 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
1312 if (kvm_vcpu_apicv_active(vcpu))
1313 avic_init_vmcb(svm, vmcb);
1316 svm_clr_intercept(svm, INTERCEPT_STGI);
1317 svm_clr_intercept(svm, INTERCEPT_CLGI);
1318 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1321 if (sev_guest(vcpu->kvm))
1324 svm_hv_init_vmcb(vmcb);
1325 init_vmcb_after_set_cpuid(vcpu);
1327 vmcb_mark_all_dirty(vmcb);
1332 static void __svm_vcpu_reset(struct kvm_vcpu *vcpu)
1334 struct vcpu_svm *svm = to_svm(vcpu);
1336 svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1338 svm_init_osvw(vcpu);
1339 vcpu->arch.microcode_version = 0x01000065;
1340 svm->tsc_ratio_msr = kvm_caps.default_tsc_scaling_ratio;
1342 svm->nmi_masked = false;
1343 svm->awaiting_iret_completion = false;
1345 if (sev_es_guest(vcpu->kvm))
1346 sev_es_vcpu_reset(svm);
1349 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1351 struct vcpu_svm *svm = to_svm(vcpu);
1354 svm->virt_spec_ctrl = 0;
1359 __svm_vcpu_reset(vcpu);
1362 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb)
1364 svm->current_vmcb = target_vmcb;
1365 svm->vmcb = target_vmcb->ptr;
1368 static int svm_vcpu_create(struct kvm_vcpu *vcpu)
1370 struct vcpu_svm *svm;
1371 struct page *vmcb01_page;
1372 struct page *vmsa_page = NULL;
1375 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1379 vmcb01_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1383 if (sev_es_guest(vcpu->kvm)) {
1385 * SEV-ES guests require a separate VMSA page used to contain
1386 * the encrypted register state of the guest.
1388 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1390 goto error_free_vmcb_page;
1393 * SEV-ES guests maintain an encrypted version of their FPU
1394 * state which is restored and saved on VMRUN and VMEXIT.
1395 * Mark vcpu->arch.guest_fpu->fpstate as scratch so it won't
1396 * do xsave/xrstor on it.
1398 fpstate_set_confidential(&vcpu->arch.guest_fpu);
1401 err = avic_init_vcpu(svm);
1403 goto error_free_vmsa_page;
1405 svm->msrpm = svm_vcpu_alloc_msrpm();
1408 goto error_free_vmsa_page;
1411 svm->x2avic_msrs_intercepted = true;
1413 svm->vmcb01.ptr = page_address(vmcb01_page);
1414 svm->vmcb01.pa = __sme_set(page_to_pfn(vmcb01_page) << PAGE_SHIFT);
1415 svm_switch_vmcb(svm, &svm->vmcb01);
1418 svm->sev_es.vmsa = page_address(vmsa_page);
1420 svm->guest_state_loaded = false;
1424 error_free_vmsa_page:
1426 __free_page(vmsa_page);
1427 error_free_vmcb_page:
1428 __free_page(vmcb01_page);
1433 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1437 for_each_online_cpu(i)
1438 cmpxchg(per_cpu_ptr(&svm_data.current_vmcb, i), vmcb, NULL);
1441 static void svm_vcpu_free(struct kvm_vcpu *vcpu)
1443 struct vcpu_svm *svm = to_svm(vcpu);
1446 * The vmcb page can be recycled, causing a false negative in
1447 * svm_vcpu_load(). So, ensure that no logical CPU has this
1448 * vmcb page recorded as its current vmcb.
1450 svm_clear_current_vmcb(svm->vmcb);
1452 svm_leave_nested(vcpu);
1453 svm_free_nested(svm);
1455 sev_free_vcpu(vcpu);
1457 __free_page(pfn_to_page(__sme_clr(svm->vmcb01.pa) >> PAGE_SHIFT));
1458 __free_pages(virt_to_page(svm->msrpm), get_order(MSRPM_SIZE));
1461 static void svm_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1463 struct vcpu_svm *svm = to_svm(vcpu);
1464 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, vcpu->cpu);
1466 if (sev_es_guest(vcpu->kvm))
1467 sev_es_unmap_ghcb(svm);
1469 if (svm->guest_state_loaded)
1473 * Save additional host state that will be restored on VMEXIT (sev-es)
1474 * or subsequent vmload of host save area.
1476 vmsave(sd->save_area_pa);
1477 if (sev_es_guest(vcpu->kvm)) {
1478 struct sev_es_save_area *hostsa;
1479 hostsa = (struct sev_es_save_area *)(page_address(sd->save_area) + 0x400);
1481 sev_es_prepare_switch_to_guest(hostsa);
1485 __svm_write_tsc_multiplier(vcpu->arch.tsc_scaling_ratio);
1487 if (likely(tsc_aux_uret_slot >= 0))
1488 kvm_set_user_return_msr(tsc_aux_uret_slot, svm->tsc_aux, -1ull);
1490 svm->guest_state_loaded = true;
1493 static void svm_prepare_host_switch(struct kvm_vcpu *vcpu)
1495 to_svm(vcpu)->guest_state_loaded = false;
1498 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1500 struct vcpu_svm *svm = to_svm(vcpu);
1501 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu);
1503 if (sd->current_vmcb != svm->vmcb) {
1504 sd->current_vmcb = svm->vmcb;
1505 indirect_branch_prediction_barrier();
1507 if (kvm_vcpu_apicv_active(vcpu))
1508 avic_vcpu_load(vcpu, cpu);
1511 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1513 if (kvm_vcpu_apicv_active(vcpu))
1514 avic_vcpu_put(vcpu);
1516 svm_prepare_host_switch(vcpu);
1518 ++vcpu->stat.host_state_reload;
1521 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1523 struct vcpu_svm *svm = to_svm(vcpu);
1524 unsigned long rflags = svm->vmcb->save.rflags;
1526 if (svm->nmi_singlestep) {
1527 /* Hide our flags if they were not set by the guest */
1528 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1529 rflags &= ~X86_EFLAGS_TF;
1530 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1531 rflags &= ~X86_EFLAGS_RF;
1536 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1538 if (to_svm(vcpu)->nmi_singlestep)
1539 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1542 * Any change of EFLAGS.VM is accompanied by a reload of SS
1543 * (caused by either a task switch or an inter-privilege IRET),
1544 * so we do not need to update the CPL here.
1546 to_svm(vcpu)->vmcb->save.rflags = rflags;
1549 static bool svm_get_if_flag(struct kvm_vcpu *vcpu)
1551 struct vmcb *vmcb = to_svm(vcpu)->vmcb;
1553 return sev_es_guest(vcpu->kvm)
1554 ? vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK
1555 : kvm_get_rflags(vcpu) & X86_EFLAGS_IF;
1558 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1560 kvm_register_mark_available(vcpu, reg);
1563 case VCPU_EXREG_PDPTR:
1565 * When !npt_enabled, mmu->pdptrs[] is already available since
1566 * it is always updated per SDM when moving to CRs.
1569 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
1572 KVM_BUG_ON(1, vcpu->kvm);
1576 static void svm_set_vintr(struct vcpu_svm *svm)
1578 struct vmcb_control_area *control;
1581 * The following fields are ignored when AVIC is enabled
1583 WARN_ON(kvm_vcpu_apicv_activated(&svm->vcpu));
1585 svm_set_intercept(svm, INTERCEPT_VINTR);
1588 * This is just a dummy VINTR to actually cause a vmexit to happen.
1589 * Actual injection of virtual interrupts happens through EVENTINJ.
1591 control = &svm->vmcb->control;
1592 control->int_vector = 0x0;
1593 control->int_ctl &= ~V_INTR_PRIO_MASK;
1594 control->int_ctl |= V_IRQ_MASK |
1595 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1596 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1599 static void svm_clear_vintr(struct vcpu_svm *svm)
1601 svm_clr_intercept(svm, INTERCEPT_VINTR);
1603 /* Drop int_ctl fields related to VINTR injection. */
1604 svm->vmcb->control.int_ctl &= ~V_IRQ_INJECTION_BITS_MASK;
1605 if (is_guest_mode(&svm->vcpu)) {
1606 svm->vmcb01.ptr->control.int_ctl &= ~V_IRQ_INJECTION_BITS_MASK;
1608 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1609 (svm->nested.ctl.int_ctl & V_TPR_MASK));
1611 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl &
1612 V_IRQ_INJECTION_BITS_MASK;
1614 svm->vmcb->control.int_vector = svm->nested.ctl.int_vector;
1617 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1620 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1622 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1623 struct vmcb_save_area *save01 = &to_svm(vcpu)->vmcb01.ptr->save;
1626 case VCPU_SREG_CS: return &save->cs;
1627 case VCPU_SREG_DS: return &save->ds;
1628 case VCPU_SREG_ES: return &save->es;
1629 case VCPU_SREG_FS: return &save01->fs;
1630 case VCPU_SREG_GS: return &save01->gs;
1631 case VCPU_SREG_SS: return &save->ss;
1632 case VCPU_SREG_TR: return &save01->tr;
1633 case VCPU_SREG_LDTR: return &save01->ldtr;
1639 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1641 struct vmcb_seg *s = svm_seg(vcpu, seg);
1646 static void svm_get_segment(struct kvm_vcpu *vcpu,
1647 struct kvm_segment *var, int seg)
1649 struct vmcb_seg *s = svm_seg(vcpu, seg);
1651 var->base = s->base;
1652 var->limit = s->limit;
1653 var->selector = s->selector;
1654 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1655 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1656 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1657 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1658 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1659 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1660 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1663 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1664 * However, the SVM spec states that the G bit is not observed by the
1665 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1666 * So let's synthesize a legal G bit for all segments, this helps
1667 * running KVM nested. It also helps cross-vendor migration, because
1668 * Intel's vmentry has a check on the 'G' bit.
1670 var->g = s->limit > 0xfffff;
1673 * AMD's VMCB does not have an explicit unusable field, so emulate it
1674 * for cross vendor migration purposes by "not present"
1676 var->unusable = !var->present;
1681 * Work around a bug where the busy flag in the tr selector
1691 * The accessed bit must always be set in the segment
1692 * descriptor cache, although it can be cleared in the
1693 * descriptor, the cached bit always remains at 1. Since
1694 * Intel has a check on this, set it here to support
1695 * cross-vendor migration.
1702 * On AMD CPUs sometimes the DB bit in the segment
1703 * descriptor is left as 1, although the whole segment has
1704 * been made unusable. Clear it here to pass an Intel VMX
1705 * entry check when cross vendor migrating.
1709 /* This is symmetric with svm_set_segment() */
1710 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1715 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1717 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1722 static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1724 struct kvm_segment cs;
1726 svm_get_segment(vcpu, &cs, VCPU_SREG_CS);
1731 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1733 struct vcpu_svm *svm = to_svm(vcpu);
1735 dt->size = svm->vmcb->save.idtr.limit;
1736 dt->address = svm->vmcb->save.idtr.base;
1739 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1741 struct vcpu_svm *svm = to_svm(vcpu);
1743 svm->vmcb->save.idtr.limit = dt->size;
1744 svm->vmcb->save.idtr.base = dt->address ;
1745 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1748 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1750 struct vcpu_svm *svm = to_svm(vcpu);
1752 dt->size = svm->vmcb->save.gdtr.limit;
1753 dt->address = svm->vmcb->save.gdtr.base;
1756 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1758 struct vcpu_svm *svm = to_svm(vcpu);
1760 svm->vmcb->save.gdtr.limit = dt->size;
1761 svm->vmcb->save.gdtr.base = dt->address ;
1762 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1765 static void sev_post_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1767 struct vcpu_svm *svm = to_svm(vcpu);
1770 * For guests that don't set guest_state_protected, the cr3 update is
1771 * handled via kvm_mmu_load() while entering the guest. For guests
1772 * that do (SEV-ES/SEV-SNP), the cr3 update needs to be written to
1773 * VMCB save area now, since the save area will become the initial
1774 * contents of the VMSA, and future VMCB save area updates won't be
1777 if (sev_es_guest(vcpu->kvm)) {
1778 svm->vmcb->save.cr3 = cr3;
1779 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1783 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1785 struct vcpu_svm *svm = to_svm(vcpu);
1787 bool old_paging = is_paging(vcpu);
1789 #ifdef CONFIG_X86_64
1790 if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1791 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1792 vcpu->arch.efer |= EFER_LMA;
1793 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1796 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1797 vcpu->arch.efer &= ~EFER_LMA;
1798 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1802 vcpu->arch.cr0 = cr0;
1805 hcr0 |= X86_CR0_PG | X86_CR0_WP;
1806 if (old_paging != is_paging(vcpu))
1807 svm_set_cr4(vcpu, kvm_read_cr4(vcpu));
1811 * re-enable caching here because the QEMU bios
1812 * does not do it - this results in some delay at
1815 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1816 hcr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1818 svm->vmcb->save.cr0 = hcr0;
1819 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1822 * SEV-ES guests must always keep the CR intercepts cleared. CR
1823 * tracking is done using the CR write traps.
1825 if (sev_es_guest(vcpu->kvm))
1829 /* Selective CR0 write remains on. */
1830 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1831 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1833 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1834 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1838 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1843 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1845 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1846 unsigned long old_cr4 = vcpu->arch.cr4;
1848 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1849 svm_flush_tlb_current(vcpu);
1851 vcpu->arch.cr4 = cr4;
1855 if (!is_paging(vcpu))
1856 cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
1858 cr4 |= host_cr4_mce;
1859 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1860 vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1862 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1863 kvm_update_cpuid_runtime(vcpu);
1866 static void svm_set_segment(struct kvm_vcpu *vcpu,
1867 struct kvm_segment *var, int seg)
1869 struct vcpu_svm *svm = to_svm(vcpu);
1870 struct vmcb_seg *s = svm_seg(vcpu, seg);
1872 s->base = var->base;
1873 s->limit = var->limit;
1874 s->selector = var->selector;
1875 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1876 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1877 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1878 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1879 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1880 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1881 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1882 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1885 * This is always accurate, except if SYSRET returned to a segment
1886 * with SS.DPL != 3. Intel does not have this quirk, and always
1887 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1888 * would entail passing the CPL to userspace and back.
1890 if (seg == VCPU_SREG_SS)
1891 /* This is symmetric with svm_get_segment() */
1892 svm->vmcb->save.cpl = (var->dpl & 3);
1894 vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1897 static void svm_update_exception_bitmap(struct kvm_vcpu *vcpu)
1899 struct vcpu_svm *svm = to_svm(vcpu);
1901 clr_exception_intercept(svm, BP_VECTOR);
1903 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1904 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1905 set_exception_intercept(svm, BP_VECTOR);
1909 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1911 if (sd->next_asid > sd->max_asid) {
1912 ++sd->asid_generation;
1913 sd->next_asid = sd->min_asid;
1914 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1915 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1918 svm->current_vmcb->asid_generation = sd->asid_generation;
1919 svm->asid = sd->next_asid++;
1922 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1924 struct vmcb *vmcb = svm->vmcb;
1926 if (svm->vcpu.arch.guest_state_protected)
1929 if (unlikely(value != vmcb->save.dr6)) {
1930 vmcb->save.dr6 = value;
1931 vmcb_mark_dirty(vmcb, VMCB_DR);
1935 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1937 struct vcpu_svm *svm = to_svm(vcpu);
1939 if (vcpu->arch.guest_state_protected)
1942 get_debugreg(vcpu->arch.db[0], 0);
1943 get_debugreg(vcpu->arch.db[1], 1);
1944 get_debugreg(vcpu->arch.db[2], 2);
1945 get_debugreg(vcpu->arch.db[3], 3);
1947 * We cannot reset svm->vmcb->save.dr6 to DR6_ACTIVE_LOW here,
1948 * because db_interception might need it. We can do it before vmentry.
1950 vcpu->arch.dr6 = svm->vmcb->save.dr6;
1951 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1952 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1953 set_dr_intercepts(svm);
1956 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1958 struct vcpu_svm *svm = to_svm(vcpu);
1960 if (vcpu->arch.guest_state_protected)
1963 svm->vmcb->save.dr7 = value;
1964 vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1967 static int pf_interception(struct kvm_vcpu *vcpu)
1969 struct vcpu_svm *svm = to_svm(vcpu);
1971 u64 fault_address = svm->vmcb->control.exit_info_2;
1972 u64 error_code = svm->vmcb->control.exit_info_1;
1974 return kvm_handle_page_fault(vcpu, error_code, fault_address,
1975 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1976 svm->vmcb->control.insn_bytes : NULL,
1977 svm->vmcb->control.insn_len);
1980 static int npf_interception(struct kvm_vcpu *vcpu)
1982 struct vcpu_svm *svm = to_svm(vcpu);
1984 u64 fault_address = svm->vmcb->control.exit_info_2;
1985 u64 error_code = svm->vmcb->control.exit_info_1;
1987 trace_kvm_page_fault(vcpu, fault_address, error_code);
1988 return kvm_mmu_page_fault(vcpu, fault_address, error_code,
1989 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1990 svm->vmcb->control.insn_bytes : NULL,
1991 svm->vmcb->control.insn_len);
1994 static int db_interception(struct kvm_vcpu *vcpu)
1996 struct kvm_run *kvm_run = vcpu->run;
1997 struct vcpu_svm *svm = to_svm(vcpu);
1999 if (!(vcpu->guest_debug &
2000 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2001 !svm->nmi_singlestep) {
2002 u32 payload = svm->vmcb->save.dr6 ^ DR6_ACTIVE_LOW;
2003 kvm_queue_exception_p(vcpu, DB_VECTOR, payload);
2007 if (svm->nmi_singlestep) {
2008 disable_nmi_singlestep(svm);
2009 /* Make sure we check for pending NMIs upon entry */
2010 kvm_make_request(KVM_REQ_EVENT, vcpu);
2013 if (vcpu->guest_debug &
2014 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2015 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2016 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
2017 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
2018 kvm_run->debug.arch.pc =
2019 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2020 kvm_run->debug.arch.exception = DB_VECTOR;
2027 static int bp_interception(struct kvm_vcpu *vcpu)
2029 struct vcpu_svm *svm = to_svm(vcpu);
2030 struct kvm_run *kvm_run = vcpu->run;
2032 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2033 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2034 kvm_run->debug.arch.exception = BP_VECTOR;
2038 static int ud_interception(struct kvm_vcpu *vcpu)
2040 return handle_ud(vcpu);
2043 static int ac_interception(struct kvm_vcpu *vcpu)
2045 kvm_queue_exception_e(vcpu, AC_VECTOR, 0);
2049 static bool is_erratum_383(void)
2054 if (!erratum_383_found)
2057 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2061 /* Bit 62 may or may not be set for this mce */
2062 value &= ~(1ULL << 62);
2064 if (value != 0xb600000000010015ULL)
2067 /* Clear MCi_STATUS registers */
2068 for (i = 0; i < 6; ++i)
2069 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2071 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2075 value &= ~(1ULL << 2);
2076 low = lower_32_bits(value);
2077 high = upper_32_bits(value);
2079 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2082 /* Flush tlb to evict multi-match entries */
2088 static void svm_handle_mce(struct kvm_vcpu *vcpu)
2090 if (is_erratum_383()) {
2092 * Erratum 383 triggered. Guest state is corrupt so kill the
2095 pr_err("Guest triggered AMD Erratum 383\n");
2097 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2103 * On an #MC intercept the MCE handler is not called automatically in
2104 * the host. So do it by hand here.
2106 kvm_machine_check();
2109 static int mc_interception(struct kvm_vcpu *vcpu)
2114 static int shutdown_interception(struct kvm_vcpu *vcpu)
2116 struct kvm_run *kvm_run = vcpu->run;
2117 struct vcpu_svm *svm = to_svm(vcpu);
2120 * The VM save area has already been encrypted so it
2121 * cannot be reinitialized - just terminate.
2123 if (sev_es_guest(vcpu->kvm))
2127 * VMCB is undefined after a SHUTDOWN intercept. INIT the vCPU to put
2128 * the VMCB in a known good state. Unfortuately, KVM doesn't have
2129 * KVM_MP_STATE_SHUTDOWN and can't add it without potentially breaking
2130 * userspace. At a platform view, INIT is acceptable behavior as
2131 * there exist bare metal platforms that automatically INIT the CPU
2132 * in response to shutdown.
2134 clear_page(svm->vmcb);
2135 kvm_vcpu_reset(vcpu, true);
2137 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2141 static int io_interception(struct kvm_vcpu *vcpu)
2143 struct vcpu_svm *svm = to_svm(vcpu);
2144 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2145 int size, in, string;
2148 ++vcpu->stat.io_exits;
2149 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2150 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2151 port = io_info >> 16;
2152 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2155 if (sev_es_guest(vcpu->kvm))
2156 return sev_es_string_io(svm, size, port, in);
2158 return kvm_emulate_instruction(vcpu, 0);
2161 svm->next_rip = svm->vmcb->control.exit_info_2;
2163 return kvm_fast_pio(vcpu, size, port, in);
2166 static int nmi_interception(struct kvm_vcpu *vcpu)
2171 static int smi_interception(struct kvm_vcpu *vcpu)
2176 static int intr_interception(struct kvm_vcpu *vcpu)
2178 ++vcpu->stat.irq_exits;
2182 static int vmload_vmsave_interception(struct kvm_vcpu *vcpu, bool vmload)
2184 struct vcpu_svm *svm = to_svm(vcpu);
2185 struct vmcb *vmcb12;
2186 struct kvm_host_map map;
2189 if (nested_svm_check_permissions(vcpu))
2192 ret = kvm_vcpu_map(vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2195 kvm_inject_gp(vcpu, 0);
2201 ret = kvm_skip_emulated_instruction(vcpu);
2204 svm_copy_vmloadsave_state(svm->vmcb, vmcb12);
2205 svm->sysenter_eip_hi = 0;
2206 svm->sysenter_esp_hi = 0;
2208 svm_copy_vmloadsave_state(vmcb12, svm->vmcb);
2211 kvm_vcpu_unmap(vcpu, &map, true);
2216 static int vmload_interception(struct kvm_vcpu *vcpu)
2218 return vmload_vmsave_interception(vcpu, true);
2221 static int vmsave_interception(struct kvm_vcpu *vcpu)
2223 return vmload_vmsave_interception(vcpu, false);
2226 static int vmrun_interception(struct kvm_vcpu *vcpu)
2228 if (nested_svm_check_permissions(vcpu))
2231 return nested_svm_vmrun(vcpu);
2241 /* Return NONE_SVM_INSTR if not SVM instrs, otherwise return decode result */
2242 static int svm_instr_opcode(struct kvm_vcpu *vcpu)
2244 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
2246 if (ctxt->b != 0x1 || ctxt->opcode_len != 2)
2247 return NONE_SVM_INSTR;
2249 switch (ctxt->modrm) {
2250 case 0xd8: /* VMRUN */
2251 return SVM_INSTR_VMRUN;
2252 case 0xda: /* VMLOAD */
2253 return SVM_INSTR_VMLOAD;
2254 case 0xdb: /* VMSAVE */
2255 return SVM_INSTR_VMSAVE;
2260 return NONE_SVM_INSTR;
2263 static int emulate_svm_instr(struct kvm_vcpu *vcpu, int opcode)
2265 const int guest_mode_exit_codes[] = {
2266 [SVM_INSTR_VMRUN] = SVM_EXIT_VMRUN,
2267 [SVM_INSTR_VMLOAD] = SVM_EXIT_VMLOAD,
2268 [SVM_INSTR_VMSAVE] = SVM_EXIT_VMSAVE,
2270 int (*const svm_instr_handlers[])(struct kvm_vcpu *vcpu) = {
2271 [SVM_INSTR_VMRUN] = vmrun_interception,
2272 [SVM_INSTR_VMLOAD] = vmload_interception,
2273 [SVM_INSTR_VMSAVE] = vmsave_interception,
2275 struct vcpu_svm *svm = to_svm(vcpu);
2278 if (is_guest_mode(vcpu)) {
2279 /* Returns '1' or -errno on failure, '0' on success. */
2280 ret = nested_svm_simple_vmexit(svm, guest_mode_exit_codes[opcode]);
2285 return svm_instr_handlers[opcode](vcpu);
2289 * #GP handling code. Note that #GP can be triggered under the following two
2291 * 1) SVM VM-related instructions (VMRUN/VMSAVE/VMLOAD) that trigger #GP on
2292 * some AMD CPUs when EAX of these instructions are in the reserved memory
2293 * regions (e.g. SMM memory on host).
2294 * 2) VMware backdoor
2296 static int gp_interception(struct kvm_vcpu *vcpu)
2298 struct vcpu_svm *svm = to_svm(vcpu);
2299 u32 error_code = svm->vmcb->control.exit_info_1;
2302 /* Both #GP cases have zero error_code */
2306 /* Decode the instruction for usage later */
2307 if (x86_decode_emulated_instruction(vcpu, 0, NULL, 0) != EMULATION_OK)
2310 opcode = svm_instr_opcode(vcpu);
2312 if (opcode == NONE_SVM_INSTR) {
2313 if (!enable_vmware_backdoor)
2317 * VMware backdoor emulation on #GP interception only handles
2318 * IN{S}, OUT{S}, and RDPMC.
2320 if (!is_guest_mode(vcpu))
2321 return kvm_emulate_instruction(vcpu,
2322 EMULTYPE_VMWARE_GP | EMULTYPE_NO_DECODE);
2324 /* All SVM instructions expect page aligned RAX */
2325 if (svm->vmcb->save.rax & ~PAGE_MASK)
2328 return emulate_svm_instr(vcpu, opcode);
2332 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2336 void svm_set_gif(struct vcpu_svm *svm, bool value)
2340 * If VGIF is enabled, the STGI intercept is only added to
2341 * detect the opening of the SMI/NMI window; remove it now.
2342 * Likewise, clear the VINTR intercept, we will set it
2343 * again while processing KVM_REQ_EVENT if needed.
2346 svm_clr_intercept(svm, INTERCEPT_STGI);
2347 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2348 svm_clear_vintr(svm);
2351 if (svm->vcpu.arch.smi_pending ||
2352 svm->vcpu.arch.nmi_pending ||
2353 kvm_cpu_has_injectable_intr(&svm->vcpu) ||
2354 kvm_apic_has_pending_init_or_sipi(&svm->vcpu))
2355 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2360 * After a CLGI no interrupts should come. But if vGIF is
2361 * in use, we still rely on the VINTR intercept (rather than
2362 * STGI) to detect an open interrupt window.
2365 svm_clear_vintr(svm);
2369 static int stgi_interception(struct kvm_vcpu *vcpu)
2373 if (nested_svm_check_permissions(vcpu))
2376 ret = kvm_skip_emulated_instruction(vcpu);
2377 svm_set_gif(to_svm(vcpu), true);
2381 static int clgi_interception(struct kvm_vcpu *vcpu)
2385 if (nested_svm_check_permissions(vcpu))
2388 ret = kvm_skip_emulated_instruction(vcpu);
2389 svm_set_gif(to_svm(vcpu), false);
2393 static int invlpga_interception(struct kvm_vcpu *vcpu)
2395 gva_t gva = kvm_rax_read(vcpu);
2396 u32 asid = kvm_rcx_read(vcpu);
2398 /* FIXME: Handle an address size prefix. */
2399 if (!is_long_mode(vcpu))
2402 trace_kvm_invlpga(to_svm(vcpu)->vmcb->save.rip, asid, gva);
2404 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2405 kvm_mmu_invlpg(vcpu, gva);
2407 return kvm_skip_emulated_instruction(vcpu);
2410 static int skinit_interception(struct kvm_vcpu *vcpu)
2412 trace_kvm_skinit(to_svm(vcpu)->vmcb->save.rip, kvm_rax_read(vcpu));
2414 kvm_queue_exception(vcpu, UD_VECTOR);
2418 static int task_switch_interception(struct kvm_vcpu *vcpu)
2420 struct vcpu_svm *svm = to_svm(vcpu);
2423 int int_type = svm->vmcb->control.exit_int_info &
2424 SVM_EXITINTINFO_TYPE_MASK;
2425 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2427 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2429 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2430 bool has_error_code = false;
2433 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2435 if (svm->vmcb->control.exit_info_2 &
2436 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2437 reason = TASK_SWITCH_IRET;
2438 else if (svm->vmcb->control.exit_info_2 &
2439 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2440 reason = TASK_SWITCH_JMP;
2442 reason = TASK_SWITCH_GATE;
2444 reason = TASK_SWITCH_CALL;
2446 if (reason == TASK_SWITCH_GATE) {
2448 case SVM_EXITINTINFO_TYPE_NMI:
2449 vcpu->arch.nmi_injected = false;
2451 case SVM_EXITINTINFO_TYPE_EXEPT:
2452 if (svm->vmcb->control.exit_info_2 &
2453 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2454 has_error_code = true;
2456 (u32)svm->vmcb->control.exit_info_2;
2458 kvm_clear_exception_queue(vcpu);
2460 case SVM_EXITINTINFO_TYPE_INTR:
2461 case SVM_EXITINTINFO_TYPE_SOFT:
2462 kvm_clear_interrupt_queue(vcpu);
2469 if (reason != TASK_SWITCH_GATE ||
2470 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2471 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2472 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2473 if (!svm_skip_emulated_instruction(vcpu))
2477 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2480 return kvm_task_switch(vcpu, tss_selector, int_vec, reason,
2481 has_error_code, error_code);
2484 static int iret_interception(struct kvm_vcpu *vcpu)
2486 struct vcpu_svm *svm = to_svm(vcpu);
2488 ++vcpu->stat.nmi_window_exits;
2489 svm->awaiting_iret_completion = true;
2490 if (!sev_es_guest(vcpu->kvm)) {
2491 svm_clr_intercept(svm, INTERCEPT_IRET);
2492 svm->nmi_iret_rip = kvm_rip_read(vcpu);
2494 kvm_make_request(KVM_REQ_EVENT, vcpu);
2498 static int invlpg_interception(struct kvm_vcpu *vcpu)
2500 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2501 return kvm_emulate_instruction(vcpu, 0);
2503 kvm_mmu_invlpg(vcpu, to_svm(vcpu)->vmcb->control.exit_info_1);
2504 return kvm_skip_emulated_instruction(vcpu);
2507 static int emulate_on_interception(struct kvm_vcpu *vcpu)
2509 return kvm_emulate_instruction(vcpu, 0);
2512 static int rsm_interception(struct kvm_vcpu *vcpu)
2514 return kvm_emulate_instruction_from_buffer(vcpu, rsm_ins_bytes, 2);
2517 static bool check_selective_cr0_intercepted(struct kvm_vcpu *vcpu,
2520 struct vcpu_svm *svm = to_svm(vcpu);
2521 unsigned long cr0 = vcpu->arch.cr0;
2524 if (!is_guest_mode(vcpu) ||
2525 (!(vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2528 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2529 val &= ~SVM_CR0_SELECTIVE_MASK;
2532 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2533 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2539 #define CR_VALID (1ULL << 63)
2541 static int cr_interception(struct kvm_vcpu *vcpu)
2543 struct vcpu_svm *svm = to_svm(vcpu);
2548 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2549 return emulate_on_interception(vcpu);
2551 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2552 return emulate_on_interception(vcpu);
2554 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2555 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2556 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2558 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2561 if (cr >= 16) { /* mov to cr */
2563 val = kvm_register_read(vcpu, reg);
2564 trace_kvm_cr_write(cr, val);
2567 if (!check_selective_cr0_intercepted(vcpu, val))
2568 err = kvm_set_cr0(vcpu, val);
2574 err = kvm_set_cr3(vcpu, val);
2577 err = kvm_set_cr4(vcpu, val);
2580 err = kvm_set_cr8(vcpu, val);
2583 WARN(1, "unhandled write to CR%d", cr);
2584 kvm_queue_exception(vcpu, UD_VECTOR);
2587 } else { /* mov from cr */
2590 val = kvm_read_cr0(vcpu);
2593 val = vcpu->arch.cr2;
2596 val = kvm_read_cr3(vcpu);
2599 val = kvm_read_cr4(vcpu);
2602 val = kvm_get_cr8(vcpu);
2605 WARN(1, "unhandled read from CR%d", cr);
2606 kvm_queue_exception(vcpu, UD_VECTOR);
2609 kvm_register_write(vcpu, reg, val);
2610 trace_kvm_cr_read(cr, val);
2612 return kvm_complete_insn_gp(vcpu, err);
2615 static int cr_trap(struct kvm_vcpu *vcpu)
2617 struct vcpu_svm *svm = to_svm(vcpu);
2618 unsigned long old_value, new_value;
2622 new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2624 cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2627 old_value = kvm_read_cr0(vcpu);
2628 svm_set_cr0(vcpu, new_value);
2630 kvm_post_set_cr0(vcpu, old_value, new_value);
2633 old_value = kvm_read_cr4(vcpu);
2634 svm_set_cr4(vcpu, new_value);
2636 kvm_post_set_cr4(vcpu, old_value, new_value);
2639 ret = kvm_set_cr8(vcpu, new_value);
2642 WARN(1, "unhandled CR%d write trap", cr);
2643 kvm_queue_exception(vcpu, UD_VECTOR);
2647 return kvm_complete_insn_gp(vcpu, ret);
2650 static int dr_interception(struct kvm_vcpu *vcpu)
2652 struct vcpu_svm *svm = to_svm(vcpu);
2657 if (vcpu->guest_debug == 0) {
2659 * No more DR vmexits; force a reload of the debug registers
2660 * and reenter on this instruction. The next vmexit will
2661 * retrieve the full state of the debug registers.
2663 clr_dr_intercepts(svm);
2664 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2668 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2669 return emulate_on_interception(vcpu);
2671 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2672 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2673 if (dr >= 16) { /* mov to DRn */
2675 val = kvm_register_read(vcpu, reg);
2676 err = kvm_set_dr(vcpu, dr, val);
2678 kvm_get_dr(vcpu, dr, &val);
2679 kvm_register_write(vcpu, reg, val);
2682 return kvm_complete_insn_gp(vcpu, err);
2685 static int cr8_write_interception(struct kvm_vcpu *vcpu)
2689 u8 cr8_prev = kvm_get_cr8(vcpu);
2690 /* instruction emulation calls kvm_set_cr8() */
2691 r = cr_interception(vcpu);
2692 if (lapic_in_kernel(vcpu))
2694 if (cr8_prev <= kvm_get_cr8(vcpu))
2696 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2700 static int efer_trap(struct kvm_vcpu *vcpu)
2702 struct msr_data msr_info;
2706 * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2707 * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2708 * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2709 * the guest doesn't have X86_FEATURE_SVM.
2711 msr_info.host_initiated = false;
2712 msr_info.index = MSR_EFER;
2713 msr_info.data = to_svm(vcpu)->vmcb->control.exit_info_1 & ~EFER_SVME;
2714 ret = kvm_set_msr_common(vcpu, &msr_info);
2716 return kvm_complete_insn_gp(vcpu, ret);
2719 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2723 switch (msr->index) {
2724 case MSR_AMD64_DE_CFG:
2725 if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
2726 msr->data |= MSR_AMD64_DE_CFG_LFENCE_SERIALIZE;
2729 return KVM_MSR_RET_INVALID;
2735 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2737 struct vcpu_svm *svm = to_svm(vcpu);
2739 switch (msr_info->index) {
2740 case MSR_AMD64_TSC_RATIO:
2741 if (!msr_info->host_initiated && !svm->tsc_scaling_enabled)
2743 msr_info->data = svm->tsc_ratio_msr;
2746 msr_info->data = svm->vmcb01.ptr->save.star;
2748 #ifdef CONFIG_X86_64
2750 msr_info->data = svm->vmcb01.ptr->save.lstar;
2753 msr_info->data = svm->vmcb01.ptr->save.cstar;
2755 case MSR_KERNEL_GS_BASE:
2756 msr_info->data = svm->vmcb01.ptr->save.kernel_gs_base;
2758 case MSR_SYSCALL_MASK:
2759 msr_info->data = svm->vmcb01.ptr->save.sfmask;
2762 case MSR_IA32_SYSENTER_CS:
2763 msr_info->data = svm->vmcb01.ptr->save.sysenter_cs;
2765 case MSR_IA32_SYSENTER_EIP:
2766 msr_info->data = (u32)svm->vmcb01.ptr->save.sysenter_eip;
2767 if (guest_cpuid_is_intel(vcpu))
2768 msr_info->data |= (u64)svm->sysenter_eip_hi << 32;
2770 case MSR_IA32_SYSENTER_ESP:
2771 msr_info->data = svm->vmcb01.ptr->save.sysenter_esp;
2772 if (guest_cpuid_is_intel(vcpu))
2773 msr_info->data |= (u64)svm->sysenter_esp_hi << 32;
2776 msr_info->data = svm->tsc_aux;
2778 case MSR_IA32_DEBUGCTLMSR:
2779 case MSR_IA32_LASTBRANCHFROMIP:
2780 case MSR_IA32_LASTBRANCHTOIP:
2781 case MSR_IA32_LASTINTFROMIP:
2782 case MSR_IA32_LASTINTTOIP:
2783 msr_info->data = svm_get_lbr_msr(svm, msr_info->index);
2785 case MSR_VM_HSAVE_PA:
2786 msr_info->data = svm->nested.hsave_msr;
2789 msr_info->data = svm->nested.vm_cr_msr;
2791 case MSR_IA32_SPEC_CTRL:
2792 if (!msr_info->host_initiated &&
2793 !guest_has_spec_ctrl_msr(vcpu))
2796 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2797 msr_info->data = svm->vmcb->save.spec_ctrl;
2799 msr_info->data = svm->spec_ctrl;
2801 case MSR_AMD64_VIRT_SPEC_CTRL:
2802 if (!msr_info->host_initiated &&
2803 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2806 msr_info->data = svm->virt_spec_ctrl;
2808 case MSR_F15H_IC_CFG: {
2812 family = guest_cpuid_family(vcpu);
2813 model = guest_cpuid_model(vcpu);
2815 if (family < 0 || model < 0)
2816 return kvm_get_msr_common(vcpu, msr_info);
2820 if (family == 0x15 &&
2821 (model >= 0x2 && model < 0x20))
2822 msr_info->data = 0x1E;
2825 case MSR_AMD64_DE_CFG:
2826 msr_info->data = svm->msr_decfg;
2829 return kvm_get_msr_common(vcpu, msr_info);
2834 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2836 struct vcpu_svm *svm = to_svm(vcpu);
2837 if (!err || !sev_es_guest(vcpu->kvm) || WARN_ON_ONCE(!svm->sev_es.ghcb))
2838 return kvm_complete_insn_gp(vcpu, err);
2840 ghcb_set_sw_exit_info_1(svm->sev_es.ghcb, 1);
2841 ghcb_set_sw_exit_info_2(svm->sev_es.ghcb,
2843 SVM_EVTINJ_TYPE_EXEPT |
2848 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2850 struct vcpu_svm *svm = to_svm(vcpu);
2851 int svm_dis, chg_mask;
2853 if (data & ~SVM_VM_CR_VALID_MASK)
2856 chg_mask = SVM_VM_CR_VALID_MASK;
2858 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2859 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2861 svm->nested.vm_cr_msr &= ~chg_mask;
2862 svm->nested.vm_cr_msr |= (data & chg_mask);
2864 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2866 /* check for svm_disable while efer.svme is set */
2867 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2873 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2875 struct vcpu_svm *svm = to_svm(vcpu);
2878 u32 ecx = msr->index;
2879 u64 data = msr->data;
2881 case MSR_AMD64_TSC_RATIO:
2883 if (!svm->tsc_scaling_enabled) {
2885 if (!msr->host_initiated)
2888 * In case TSC scaling is not enabled, always
2889 * leave this MSR at the default value.
2891 * Due to bug in qemu 6.2.0, it would try to set
2892 * this msr to 0 if tsc scaling is not enabled.
2893 * Ignore this value as well.
2895 if (data != 0 && data != svm->tsc_ratio_msr)
2900 if (data & SVM_TSC_RATIO_RSVD)
2903 svm->tsc_ratio_msr = data;
2905 if (svm->tsc_scaling_enabled && is_guest_mode(vcpu))
2906 nested_svm_update_tsc_ratio_msr(vcpu);
2909 case MSR_IA32_CR_PAT:
2910 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2912 vcpu->arch.pat = data;
2913 svm->vmcb01.ptr->save.g_pat = data;
2914 if (is_guest_mode(vcpu))
2915 nested_vmcb02_compute_g_pat(svm);
2916 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2918 case MSR_IA32_SPEC_CTRL:
2919 if (!msr->host_initiated &&
2920 !guest_has_spec_ctrl_msr(vcpu))
2923 if (kvm_spec_ctrl_test_value(data))
2926 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2927 svm->vmcb->save.spec_ctrl = data;
2929 svm->spec_ctrl = data;
2935 * When it's written (to non-zero) for the first time, pass
2939 * The handling of the MSR bitmap for L2 guests is done in
2940 * nested_svm_vmrun_msrpm.
2941 * We update the L1 MSR bit as well since it will end up
2942 * touching the MSR anyway now.
2944 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2946 case MSR_AMD64_VIRT_SPEC_CTRL:
2947 if (!msr->host_initiated &&
2948 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2951 if (data & ~SPEC_CTRL_SSBD)
2954 svm->virt_spec_ctrl = data;
2957 svm->vmcb01.ptr->save.star = data;
2959 #ifdef CONFIG_X86_64
2961 svm->vmcb01.ptr->save.lstar = data;
2964 svm->vmcb01.ptr->save.cstar = data;
2966 case MSR_KERNEL_GS_BASE:
2967 svm->vmcb01.ptr->save.kernel_gs_base = data;
2969 case MSR_SYSCALL_MASK:
2970 svm->vmcb01.ptr->save.sfmask = data;
2973 case MSR_IA32_SYSENTER_CS:
2974 svm->vmcb01.ptr->save.sysenter_cs = data;
2976 case MSR_IA32_SYSENTER_EIP:
2977 svm->vmcb01.ptr->save.sysenter_eip = (u32)data;
2979 * We only intercept the MSR_IA32_SYSENTER_{EIP|ESP} msrs
2980 * when we spoof an Intel vendor ID (for cross vendor migration).
2981 * In this case we use this intercept to track the high
2982 * 32 bit part of these msrs to support Intel's
2983 * implementation of SYSENTER/SYSEXIT.
2985 svm->sysenter_eip_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2987 case MSR_IA32_SYSENTER_ESP:
2988 svm->vmcb01.ptr->save.sysenter_esp = (u32)data;
2989 svm->sysenter_esp_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2993 * TSC_AUX is usually changed only during boot and never read
2994 * directly. Intercept TSC_AUX instead of exposing it to the
2995 * guest via direct_access_msrs, and switch it via user return.
2998 ret = kvm_set_user_return_msr(tsc_aux_uret_slot, data, -1ull);
3003 svm->tsc_aux = data;
3005 case MSR_IA32_DEBUGCTLMSR:
3007 kvm_pr_unimpl_wrmsr(vcpu, ecx, data);
3010 if (data & DEBUGCTL_RESERVED_BITS)
3013 if (svm->vmcb->control.virt_ext & LBR_CTL_ENABLE_MASK)
3014 svm->vmcb->save.dbgctl = data;
3016 svm->vmcb01.ptr->save.dbgctl = data;
3018 svm_update_lbrv(vcpu);
3021 case MSR_VM_HSAVE_PA:
3023 * Old kernels did not validate the value written to
3024 * MSR_VM_HSAVE_PA. Allow KVM_SET_MSR to set an invalid
3025 * value to allow live migrating buggy or malicious guests
3026 * originating from those kernels.
3028 if (!msr->host_initiated && !page_address_valid(vcpu, data))
3031 svm->nested.hsave_msr = data & PAGE_MASK;
3034 return svm_set_vm_cr(vcpu, data);
3036 kvm_pr_unimpl_wrmsr(vcpu, ecx, data);
3038 case MSR_AMD64_DE_CFG: {
3039 struct kvm_msr_entry msr_entry;
3041 msr_entry.index = msr->index;
3042 if (svm_get_msr_feature(&msr_entry))
3045 /* Check the supported bits */
3046 if (data & ~msr_entry.data)
3049 /* Don't allow the guest to change a bit, #GP */
3050 if (!msr->host_initiated && (data ^ msr_entry.data))
3053 svm->msr_decfg = data;
3057 return kvm_set_msr_common(vcpu, msr);
3062 static int msr_interception(struct kvm_vcpu *vcpu)
3064 if (to_svm(vcpu)->vmcb->control.exit_info_1)
3065 return kvm_emulate_wrmsr(vcpu);
3067 return kvm_emulate_rdmsr(vcpu);
3070 static int interrupt_window_interception(struct kvm_vcpu *vcpu)
3072 kvm_make_request(KVM_REQ_EVENT, vcpu);
3073 svm_clear_vintr(to_svm(vcpu));
3076 * If not running nested, for AVIC, the only reason to end up here is ExtINTs.
3077 * In this case AVIC was temporarily disabled for
3078 * requesting the IRQ window and we have to re-enable it.
3080 * If running nested, still remove the VM wide AVIC inhibit to
3081 * support case in which the interrupt window was requested when the
3082 * vCPU was not running nested.
3084 * All vCPUs which run still run nested, will remain to have their
3085 * AVIC still inhibited due to per-cpu AVIC inhibition.
3087 kvm_clear_apicv_inhibit(vcpu->kvm, APICV_INHIBIT_REASON_IRQWIN);
3089 ++vcpu->stat.irq_window_exits;
3093 static int pause_interception(struct kvm_vcpu *vcpu)
3097 * CPL is not made available for an SEV-ES guest, therefore
3098 * vcpu->arch.preempted_in_kernel can never be true. Just
3099 * set in_kernel to false as well.
3101 in_kernel = !sev_es_guest(vcpu->kvm) && svm_get_cpl(vcpu) == 0;
3103 grow_ple_window(vcpu);
3105 kvm_vcpu_on_spin(vcpu, in_kernel);
3106 return kvm_skip_emulated_instruction(vcpu);
3109 static int invpcid_interception(struct kvm_vcpu *vcpu)
3111 struct vcpu_svm *svm = to_svm(vcpu);
3115 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
3116 kvm_queue_exception(vcpu, UD_VECTOR);
3121 * For an INVPCID intercept:
3122 * EXITINFO1 provides the linear address of the memory operand.
3123 * EXITINFO2 provides the contents of the register operand.
3125 type = svm->vmcb->control.exit_info_2;
3126 gva = svm->vmcb->control.exit_info_1;
3128 return kvm_handle_invpcid(vcpu, type, gva);
3131 static int (*const svm_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3132 [SVM_EXIT_READ_CR0] = cr_interception,
3133 [SVM_EXIT_READ_CR3] = cr_interception,
3134 [SVM_EXIT_READ_CR4] = cr_interception,
3135 [SVM_EXIT_READ_CR8] = cr_interception,
3136 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3137 [SVM_EXIT_WRITE_CR0] = cr_interception,
3138 [SVM_EXIT_WRITE_CR3] = cr_interception,
3139 [SVM_EXIT_WRITE_CR4] = cr_interception,
3140 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3141 [SVM_EXIT_READ_DR0] = dr_interception,
3142 [SVM_EXIT_READ_DR1] = dr_interception,
3143 [SVM_EXIT_READ_DR2] = dr_interception,
3144 [SVM_EXIT_READ_DR3] = dr_interception,
3145 [SVM_EXIT_READ_DR4] = dr_interception,
3146 [SVM_EXIT_READ_DR5] = dr_interception,
3147 [SVM_EXIT_READ_DR6] = dr_interception,
3148 [SVM_EXIT_READ_DR7] = dr_interception,
3149 [SVM_EXIT_WRITE_DR0] = dr_interception,
3150 [SVM_EXIT_WRITE_DR1] = dr_interception,
3151 [SVM_EXIT_WRITE_DR2] = dr_interception,
3152 [SVM_EXIT_WRITE_DR3] = dr_interception,
3153 [SVM_EXIT_WRITE_DR4] = dr_interception,
3154 [SVM_EXIT_WRITE_DR5] = dr_interception,
3155 [SVM_EXIT_WRITE_DR6] = dr_interception,
3156 [SVM_EXIT_WRITE_DR7] = dr_interception,
3157 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3158 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3159 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3160 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3161 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3162 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
3163 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
3164 [SVM_EXIT_INTR] = intr_interception,
3165 [SVM_EXIT_NMI] = nmi_interception,
3166 [SVM_EXIT_SMI] = smi_interception,
3167 [SVM_EXIT_VINTR] = interrupt_window_interception,
3168 [SVM_EXIT_RDPMC] = kvm_emulate_rdpmc,
3169 [SVM_EXIT_CPUID] = kvm_emulate_cpuid,
3170 [SVM_EXIT_IRET] = iret_interception,
3171 [SVM_EXIT_INVD] = kvm_emulate_invd,
3172 [SVM_EXIT_PAUSE] = pause_interception,
3173 [SVM_EXIT_HLT] = kvm_emulate_halt,
3174 [SVM_EXIT_INVLPG] = invlpg_interception,
3175 [SVM_EXIT_INVLPGA] = invlpga_interception,
3176 [SVM_EXIT_IOIO] = io_interception,
3177 [SVM_EXIT_MSR] = msr_interception,
3178 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3179 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3180 [SVM_EXIT_VMRUN] = vmrun_interception,
3181 [SVM_EXIT_VMMCALL] = kvm_emulate_hypercall,
3182 [SVM_EXIT_VMLOAD] = vmload_interception,
3183 [SVM_EXIT_VMSAVE] = vmsave_interception,
3184 [SVM_EXIT_STGI] = stgi_interception,
3185 [SVM_EXIT_CLGI] = clgi_interception,
3186 [SVM_EXIT_SKINIT] = skinit_interception,
3187 [SVM_EXIT_RDTSCP] = kvm_handle_invalid_op,
3188 [SVM_EXIT_WBINVD] = kvm_emulate_wbinvd,
3189 [SVM_EXIT_MONITOR] = kvm_emulate_monitor,
3190 [SVM_EXIT_MWAIT] = kvm_emulate_mwait,
3191 [SVM_EXIT_XSETBV] = kvm_emulate_xsetbv,
3192 [SVM_EXIT_RDPRU] = kvm_handle_invalid_op,
3193 [SVM_EXIT_EFER_WRITE_TRAP] = efer_trap,
3194 [SVM_EXIT_CR0_WRITE_TRAP] = cr_trap,
3195 [SVM_EXIT_CR4_WRITE_TRAP] = cr_trap,
3196 [SVM_EXIT_CR8_WRITE_TRAP] = cr_trap,
3197 [SVM_EXIT_INVPCID] = invpcid_interception,
3198 [SVM_EXIT_NPF] = npf_interception,
3199 [SVM_EXIT_RSM] = rsm_interception,
3200 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
3201 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
3202 [SVM_EXIT_VMGEXIT] = sev_handle_vmgexit,
3205 static void dump_vmcb(struct kvm_vcpu *vcpu)
3207 struct vcpu_svm *svm = to_svm(vcpu);
3208 struct vmcb_control_area *control = &svm->vmcb->control;
3209 struct vmcb_save_area *save = &svm->vmcb->save;
3210 struct vmcb_save_area *save01 = &svm->vmcb01.ptr->save;
3212 if (!dump_invalid_vmcb) {
3213 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3217 pr_err("VMCB %p, last attempted VMRUN on CPU %d\n",
3218 svm->current_vmcb->ptr, vcpu->arch.last_vmentry_cpu);
3219 pr_err("VMCB Control Area:\n");
3220 pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3221 pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3222 pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3223 pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3224 pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3225 pr_err("%-20s%08x %08x\n", "intercepts:",
3226 control->intercepts[INTERCEPT_WORD3],
3227 control->intercepts[INTERCEPT_WORD4]);
3228 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3229 pr_err("%-20s%d\n", "pause filter threshold:",
3230 control->pause_filter_thresh);
3231 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3232 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3233 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3234 pr_err("%-20s%d\n", "asid:", control->asid);
3235 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3236 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3237 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3238 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3239 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3240 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3241 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3242 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3243 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3244 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3245 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3246 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3247 pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3248 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3249 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3250 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3251 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3252 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3253 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3254 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3255 pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
3256 pr_err("VMCB State Save Area:\n");
3257 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3259 save->es.selector, save->es.attrib,
3260 save->es.limit, save->es.base);
3261 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3263 save->cs.selector, save->cs.attrib,
3264 save->cs.limit, save->cs.base);
3265 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3267 save->ss.selector, save->ss.attrib,
3268 save->ss.limit, save->ss.base);
3269 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3271 save->ds.selector, save->ds.attrib,
3272 save->ds.limit, save->ds.base);
3273 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3275 save01->fs.selector, save01->fs.attrib,
3276 save01->fs.limit, save01->fs.base);
3277 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3279 save01->gs.selector, save01->gs.attrib,
3280 save01->gs.limit, save01->gs.base);
3281 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3283 save->gdtr.selector, save->gdtr.attrib,
3284 save->gdtr.limit, save->gdtr.base);
3285 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3287 save01->ldtr.selector, save01->ldtr.attrib,
3288 save01->ldtr.limit, save01->ldtr.base);
3289 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3291 save->idtr.selector, save->idtr.attrib,
3292 save->idtr.limit, save->idtr.base);
3293 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3295 save01->tr.selector, save01->tr.attrib,
3296 save01->tr.limit, save01->tr.base);
3297 pr_err("vmpl: %d cpl: %d efer: %016llx\n",
3298 save->vmpl, save->cpl, save->efer);
3299 pr_err("%-15s %016llx %-13s %016llx\n",
3300 "cr0:", save->cr0, "cr2:", save->cr2);
3301 pr_err("%-15s %016llx %-13s %016llx\n",
3302 "cr3:", save->cr3, "cr4:", save->cr4);
3303 pr_err("%-15s %016llx %-13s %016llx\n",
3304 "dr6:", save->dr6, "dr7:", save->dr7);
3305 pr_err("%-15s %016llx %-13s %016llx\n",
3306 "rip:", save->rip, "rflags:", save->rflags);
3307 pr_err("%-15s %016llx %-13s %016llx\n",
3308 "rsp:", save->rsp, "rax:", save->rax);
3309 pr_err("%-15s %016llx %-13s %016llx\n",
3310 "star:", save01->star, "lstar:", save01->lstar);
3311 pr_err("%-15s %016llx %-13s %016llx\n",
3312 "cstar:", save01->cstar, "sfmask:", save01->sfmask);
3313 pr_err("%-15s %016llx %-13s %016llx\n",
3314 "kernel_gs_base:", save01->kernel_gs_base,
3315 "sysenter_cs:", save01->sysenter_cs);
3316 pr_err("%-15s %016llx %-13s %016llx\n",
3317 "sysenter_esp:", save01->sysenter_esp,
3318 "sysenter_eip:", save01->sysenter_eip);
3319 pr_err("%-15s %016llx %-13s %016llx\n",
3320 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3321 pr_err("%-15s %016llx %-13s %016llx\n",
3322 "br_from:", save->br_from, "br_to:", save->br_to);
3323 pr_err("%-15s %016llx %-13s %016llx\n",
3324 "excp_from:", save->last_excp_from,
3325 "excp_to:", save->last_excp_to);
3328 static bool svm_check_exit_valid(u64 exit_code)
3330 return (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3331 svm_exit_handlers[exit_code]);
3334 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3336 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3338 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3339 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3340 vcpu->run->internal.ndata = 2;
3341 vcpu->run->internal.data[0] = exit_code;
3342 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3346 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code)
3348 if (!svm_check_exit_valid(exit_code))
3349 return svm_handle_invalid_exit(vcpu, exit_code);
3351 #ifdef CONFIG_RETPOLINE
3352 if (exit_code == SVM_EXIT_MSR)
3353 return msr_interception(vcpu);
3354 else if (exit_code == SVM_EXIT_VINTR)
3355 return interrupt_window_interception(vcpu);
3356 else if (exit_code == SVM_EXIT_INTR)
3357 return intr_interception(vcpu);
3358 else if (exit_code == SVM_EXIT_HLT)
3359 return kvm_emulate_halt(vcpu);
3360 else if (exit_code == SVM_EXIT_NPF)
3361 return npf_interception(vcpu);
3363 return svm_exit_handlers[exit_code](vcpu);
3366 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u32 *reason,
3367 u64 *info1, u64 *info2,
3368 u32 *intr_info, u32 *error_code)
3370 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3372 *reason = control->exit_code;
3373 *info1 = control->exit_info_1;
3374 *info2 = control->exit_info_2;
3375 *intr_info = control->exit_int_info;
3376 if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3377 (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3378 *error_code = control->exit_int_info_err;
3383 static int svm_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3385 struct vcpu_svm *svm = to_svm(vcpu);
3386 struct kvm_run *kvm_run = vcpu->run;
3387 u32 exit_code = svm->vmcb->control.exit_code;
3389 trace_kvm_exit(vcpu, KVM_ISA_SVM);
3391 /* SEV-ES guests must use the CR write traps to track CR registers. */
3392 if (!sev_es_guest(vcpu->kvm)) {
3393 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3394 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3396 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3399 if (is_guest_mode(vcpu)) {
3402 trace_kvm_nested_vmexit(vcpu, KVM_ISA_SVM);
3404 vmexit = nested_svm_exit_special(svm);
3406 if (vmexit == NESTED_EXIT_CONTINUE)
3407 vmexit = nested_svm_exit_handled(svm);
3409 if (vmexit == NESTED_EXIT_DONE)
3413 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3414 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3415 kvm_run->fail_entry.hardware_entry_failure_reason
3416 = svm->vmcb->control.exit_code;
3417 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3422 if (exit_fastpath != EXIT_FASTPATH_NONE)
3425 return svm_invoke_exit_handler(vcpu, exit_code);
3428 static void reload_tss(struct kvm_vcpu *vcpu)
3430 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, vcpu->cpu);
3432 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3436 static void pre_svm_run(struct kvm_vcpu *vcpu)
3438 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, vcpu->cpu);
3439 struct vcpu_svm *svm = to_svm(vcpu);
3442 * If the previous vmrun of the vmcb occurred on a different physical
3443 * cpu, then mark the vmcb dirty and assign a new asid. Hardware's
3444 * vmcb clean bits are per logical CPU, as are KVM's asid assignments.
3446 if (unlikely(svm->current_vmcb->cpu != vcpu->cpu)) {
3447 svm->current_vmcb->asid_generation = 0;
3448 vmcb_mark_all_dirty(svm->vmcb);
3449 svm->current_vmcb->cpu = vcpu->cpu;
3452 if (sev_guest(vcpu->kvm))
3453 return pre_sev_run(svm, vcpu->cpu);
3455 /* FIXME: handle wraparound of asid_generation */
3456 if (svm->current_vmcb->asid_generation != sd->asid_generation)
3460 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3462 struct vcpu_svm *svm = to_svm(vcpu);
3464 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3466 if (svm->nmi_l1_to_l2)
3469 svm->nmi_masked = true;
3470 if (!sev_es_guest(vcpu->kvm))
3471 svm_set_intercept(svm, INTERCEPT_IRET);
3472 ++vcpu->stat.nmi_injections;
3475 static void svm_inject_irq(struct kvm_vcpu *vcpu, bool reinjected)
3477 struct vcpu_svm *svm = to_svm(vcpu);
3480 if (vcpu->arch.interrupt.soft) {
3481 if (svm_update_soft_interrupt_rip(vcpu))
3484 type = SVM_EVTINJ_TYPE_SOFT;
3486 type = SVM_EVTINJ_TYPE_INTR;
3489 trace_kvm_inj_virq(vcpu->arch.interrupt.nr,
3490 vcpu->arch.interrupt.soft, reinjected);
3491 ++vcpu->stat.irq_injections;
3493 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3494 SVM_EVTINJ_VALID | type;
3497 void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_mode,
3498 int trig_mode, int vector)
3501 * apic->apicv_active must be read after vcpu->mode.
3502 * Pairs with smp_store_release in vcpu_enter_guest.
3504 bool in_guest_mode = (smp_load_acquire(&vcpu->mode) == IN_GUEST_MODE);
3506 /* Note, this is called iff the local APIC is in-kernel. */
3507 if (!READ_ONCE(vcpu->arch.apic->apicv_active)) {
3508 /* Process the interrupt via kvm_check_and_inject_events(). */
3509 kvm_make_request(KVM_REQ_EVENT, vcpu);
3510 kvm_vcpu_kick(vcpu);
3514 trace_kvm_apicv_accept_irq(vcpu->vcpu_id, delivery_mode, trig_mode, vector);
3515 if (in_guest_mode) {
3517 * Signal the doorbell to tell hardware to inject the IRQ. If
3518 * the vCPU exits the guest before the doorbell chimes, hardware
3519 * will automatically process AVIC interrupts at the next VMRUN.
3521 avic_ring_doorbell(vcpu);
3524 * Wake the vCPU if it was blocking. KVM will then detect the
3525 * pending IRQ when checking if the vCPU has a wake event.
3527 kvm_vcpu_wake_up(vcpu);
3531 static void svm_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode,
3532 int trig_mode, int vector)
3534 kvm_lapic_set_irr(vector, apic);
3537 * Pairs with the smp_mb_*() after setting vcpu->guest_mode in
3538 * vcpu_enter_guest() to ensure the write to the vIRR is ordered before
3539 * the read of guest_mode. This guarantees that either VMRUN will see
3540 * and process the new vIRR entry, or that svm_complete_interrupt_delivery
3541 * will signal the doorbell if the CPU has already entered the guest.
3543 smp_mb__after_atomic();
3544 svm_complete_interrupt_delivery(apic->vcpu, delivery_mode, trig_mode, vector);
3547 static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3549 struct vcpu_svm *svm = to_svm(vcpu);
3552 * SEV-ES guests must always keep the CR intercepts cleared. CR
3553 * tracking is done using the CR write traps.
3555 if (sev_es_guest(vcpu->kvm))
3558 if (nested_svm_virtualize_tpr(vcpu))
3561 svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3567 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3570 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3572 struct vcpu_svm *svm = to_svm(vcpu);
3573 struct vmcb *vmcb = svm->vmcb;
3578 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3581 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3585 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3587 struct vcpu_svm *svm = to_svm(vcpu);
3588 if (svm->nested.nested_run_pending)
3591 if (svm_nmi_blocked(vcpu))
3594 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3595 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3600 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3602 return to_svm(vcpu)->nmi_masked;
3605 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3607 struct vcpu_svm *svm = to_svm(vcpu);
3610 svm->nmi_masked = true;
3611 if (!sev_es_guest(vcpu->kvm))
3612 svm_set_intercept(svm, INTERCEPT_IRET);
3614 svm->nmi_masked = false;
3615 if (!sev_es_guest(vcpu->kvm))
3616 svm_clr_intercept(svm, INTERCEPT_IRET);
3620 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3622 struct vcpu_svm *svm = to_svm(vcpu);
3623 struct vmcb *vmcb = svm->vmcb;
3628 if (is_guest_mode(vcpu)) {
3629 /* As long as interrupts are being delivered... */
3630 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3631 ? !(svm->vmcb01.ptr->save.rflags & X86_EFLAGS_IF)
3632 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3635 /* ... vmexits aren't blocked by the interrupt shadow */
3636 if (nested_exit_on_intr(svm))
3639 if (!svm_get_if_flag(vcpu))
3643 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3646 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3648 struct vcpu_svm *svm = to_svm(vcpu);
3650 if (svm->nested.nested_run_pending)
3653 if (svm_interrupt_blocked(vcpu))
3657 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3658 * e.g. if the IRQ arrived asynchronously after checking nested events.
3660 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3666 static void svm_enable_irq_window(struct kvm_vcpu *vcpu)
3668 struct vcpu_svm *svm = to_svm(vcpu);
3671 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3672 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3673 * get that intercept, this function will be called again though and
3674 * we'll get the vintr intercept. However, if the vGIF feature is
3675 * enabled, the STGI interception will not occur. Enable the irq
3676 * window under the assumption that the hardware will set the GIF.
3678 if (vgif || gif_set(svm)) {
3680 * IRQ window is not needed when AVIC is enabled,
3681 * unless we have pending ExtINT since it cannot be injected
3682 * via AVIC. In such case, KVM needs to temporarily disable AVIC,
3683 * and fallback to injecting IRQ via V_IRQ.
3685 * If running nested, AVIC is already locally inhibited
3686 * on this vCPU, therefore there is no need to request
3687 * the VM wide AVIC inhibition.
3689 if (!is_guest_mode(vcpu))
3690 kvm_set_apicv_inhibit(vcpu->kvm, APICV_INHIBIT_REASON_IRQWIN);
3696 static void svm_enable_nmi_window(struct kvm_vcpu *vcpu)
3698 struct vcpu_svm *svm = to_svm(vcpu);
3700 if (svm->nmi_masked && !svm->awaiting_iret_completion)
3701 return; /* IRET will cause a vm exit */
3703 if (!gif_set(svm)) {
3705 svm_set_intercept(svm, INTERCEPT_STGI);
3706 return; /* STGI will cause a vm exit */
3710 * Something prevents NMI from been injected. Single step over possible
3711 * problem (IRET or exception injection or interrupt shadow)
3713 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3714 svm->nmi_singlestep = true;
3715 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3718 static void svm_flush_tlb_current(struct kvm_vcpu *vcpu)
3720 struct vcpu_svm *svm = to_svm(vcpu);
3723 * Unlike VMX, SVM doesn't provide a way to flush only NPT TLB entries.
3724 * A TLB flush for the current ASID flushes both "host" and "guest" TLB
3725 * entries, and thus is a superset of Hyper-V's fine grained flushing.
3727 kvm_hv_vcpu_purge_flush_tlb(vcpu);
3730 * Flush only the current ASID even if the TLB flush was invoked via
3731 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3732 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3733 * unconditionally does a TLB flush on both nested VM-Enter and nested
3734 * VM-Exit (via kvm_mmu_reset_context()).
3736 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3737 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3739 svm->current_vmcb->asid_generation--;
3742 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3744 struct vcpu_svm *svm = to_svm(vcpu);
3746 invlpga(gva, svm->vmcb->control.asid);
3749 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3751 struct vcpu_svm *svm = to_svm(vcpu);
3753 if (nested_svm_virtualize_tpr(vcpu))
3756 if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3757 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3758 kvm_set_cr8(vcpu, cr8);
3762 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3764 struct vcpu_svm *svm = to_svm(vcpu);
3767 if (nested_svm_virtualize_tpr(vcpu) ||
3768 kvm_vcpu_apicv_active(vcpu))
3771 cr8 = kvm_get_cr8(vcpu);
3772 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3773 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3776 static void svm_complete_soft_interrupt(struct kvm_vcpu *vcpu, u8 vector,
3779 bool is_exception = (type == SVM_EXITINTINFO_TYPE_EXEPT);
3780 bool is_soft = (type == SVM_EXITINTINFO_TYPE_SOFT);
3781 struct vcpu_svm *svm = to_svm(vcpu);
3784 * If NRIPS is enabled, KVM must snapshot the pre-VMRUN next_rip that's
3785 * associated with the original soft exception/interrupt. next_rip is
3786 * cleared on all exits that can occur while vectoring an event, so KVM
3787 * needs to manually set next_rip for re-injection. Unlike the !nrips
3788 * case below, this needs to be done if and only if KVM is re-injecting
3789 * the same event, i.e. if the event is a soft exception/interrupt,
3790 * otherwise next_rip is unused on VMRUN.
3792 if (nrips && (is_soft || (is_exception && kvm_exception_is_soft(vector))) &&
3793 kvm_is_linear_rip(vcpu, svm->soft_int_old_rip + svm->soft_int_csbase))
3794 svm->vmcb->control.next_rip = svm->soft_int_next_rip;
3796 * If NRIPS isn't enabled, KVM must manually advance RIP prior to
3797 * injecting the soft exception/interrupt. That advancement needs to
3798 * be unwound if vectoring didn't complete. Note, the new event may
3799 * not be the injected event, e.g. if KVM injected an INTn, the INTn
3800 * hit a #NP in the guest, and the #NP encountered a #PF, the #NP will
3801 * be the reported vectored event, but RIP still needs to be unwound.
3803 else if (!nrips && (is_soft || is_exception) &&
3804 kvm_is_linear_rip(vcpu, svm->soft_int_next_rip + svm->soft_int_csbase))
3805 kvm_rip_write(vcpu, svm->soft_int_old_rip);
3808 static void svm_complete_interrupts(struct kvm_vcpu *vcpu)
3810 struct vcpu_svm *svm = to_svm(vcpu);
3813 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3814 bool nmi_l1_to_l2 = svm->nmi_l1_to_l2;
3815 bool soft_int_injected = svm->soft_int_injected;
3817 svm->nmi_l1_to_l2 = false;
3818 svm->soft_int_injected = false;
3821 * If we've made progress since setting HF_IRET_MASK, we've
3822 * executed an IRET and can allow NMI injection.
3824 if (svm->awaiting_iret_completion &&
3825 (sev_es_guest(vcpu->kvm) ||
3826 kvm_rip_read(vcpu) != svm->nmi_iret_rip)) {
3827 svm->awaiting_iret_completion = false;
3828 svm->nmi_masked = false;
3829 kvm_make_request(KVM_REQ_EVENT, vcpu);
3832 vcpu->arch.nmi_injected = false;
3833 kvm_clear_exception_queue(vcpu);
3834 kvm_clear_interrupt_queue(vcpu);
3836 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3839 kvm_make_request(KVM_REQ_EVENT, vcpu);
3841 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3842 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3844 if (soft_int_injected)
3845 svm_complete_soft_interrupt(vcpu, vector, type);
3848 case SVM_EXITINTINFO_TYPE_NMI:
3849 vcpu->arch.nmi_injected = true;
3850 svm->nmi_l1_to_l2 = nmi_l1_to_l2;
3852 case SVM_EXITINTINFO_TYPE_EXEPT:
3854 * Never re-inject a #VC exception.
3856 if (vector == X86_TRAP_VC)
3859 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3860 u32 err = svm->vmcb->control.exit_int_info_err;
3861 kvm_requeue_exception_e(vcpu, vector, err);
3864 kvm_requeue_exception(vcpu, vector);
3866 case SVM_EXITINTINFO_TYPE_INTR:
3867 kvm_queue_interrupt(vcpu, vector, false);
3869 case SVM_EXITINTINFO_TYPE_SOFT:
3870 kvm_queue_interrupt(vcpu, vector, true);
3878 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3880 struct vcpu_svm *svm = to_svm(vcpu);
3881 struct vmcb_control_area *control = &svm->vmcb->control;
3883 control->exit_int_info = control->event_inj;
3884 control->exit_int_info_err = control->event_inj_err;
3885 control->event_inj = 0;
3886 svm_complete_interrupts(vcpu);
3889 static int svm_vcpu_pre_run(struct kvm_vcpu *vcpu)
3894 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3896 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3899 * Note, the next RIP must be provided as SRCU isn't held, i.e. KVM
3900 * can't read guest memory (dereference memslots) to decode the WRMSR.
3902 if (control->exit_code == SVM_EXIT_MSR && control->exit_info_1 &&
3903 nrips && control->next_rip)
3904 return handle_fastpath_set_msr_irqoff(vcpu);
3906 return EXIT_FASTPATH_NONE;
3909 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu, bool spec_ctrl_intercepted)
3911 struct vcpu_svm *svm = to_svm(vcpu);
3913 guest_state_enter_irqoff();
3915 if (sev_es_guest(vcpu->kvm))
3916 __svm_sev_es_vcpu_run(svm, spec_ctrl_intercepted);
3918 __svm_vcpu_run(svm, spec_ctrl_intercepted);
3920 guest_state_exit_irqoff();
3923 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3925 struct vcpu_svm *svm = to_svm(vcpu);
3926 bool spec_ctrl_intercepted = msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL);
3928 trace_kvm_entry(vcpu);
3930 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3931 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3932 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3935 * Disable singlestep if we're injecting an interrupt/exception.
3936 * We don't want our modified rflags to be pushed on the stack where
3937 * we might not be able to easily reset them if we disabled NMI
3940 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3942 * Event injection happens before external interrupts cause a
3943 * vmexit and interrupts are disabled here, so smp_send_reschedule
3944 * is enough to force an immediate vmexit.
3946 disable_nmi_singlestep(svm);
3947 smp_send_reschedule(vcpu->cpu);
3952 sync_lapic_to_cr8(vcpu);
3954 if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3955 svm->vmcb->control.asid = svm->asid;
3956 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3958 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3960 svm_hv_update_vp_id(svm->vmcb, vcpu);
3963 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3966 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3967 svm_set_dr6(svm, vcpu->arch.dr6);
3969 svm_set_dr6(svm, DR6_ACTIVE_LOW);
3972 kvm_load_guest_xsave_state(vcpu);
3974 kvm_wait_lapic_expire(vcpu);
3977 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3978 * it's non-zero. Since vmentry is serialising on affected CPUs, there
3979 * is no need to worry about the conditional branch over the wrmsr
3980 * being speculatively taken.
3982 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3983 x86_spec_ctrl_set_guest(svm->virt_spec_ctrl);
3985 svm_vcpu_enter_exit(vcpu, spec_ctrl_intercepted);
3987 if (!sev_es_guest(vcpu->kvm))
3990 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3991 x86_spec_ctrl_restore_host(svm->virt_spec_ctrl);
3993 if (!sev_es_guest(vcpu->kvm)) {
3994 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3995 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3996 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3997 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3999 vcpu->arch.regs_dirty = 0;
4001 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4002 kvm_before_interrupt(vcpu, KVM_HANDLING_NMI);
4004 kvm_load_host_xsave_state(vcpu);
4007 /* Any pending NMI will happen here */
4009 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4010 kvm_after_interrupt(vcpu);
4012 sync_cr8_to_lapic(vcpu);
4015 if (is_guest_mode(vcpu)) {
4016 nested_sync_control_from_vmcb02(svm);
4018 /* Track VMRUNs that have made past consistency checking */
4019 if (svm->nested.nested_run_pending &&
4020 svm->vmcb->control.exit_code != SVM_EXIT_ERR)
4021 ++vcpu->stat.nested_run;
4023 svm->nested.nested_run_pending = 0;
4026 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4027 vmcb_mark_all_clean(svm->vmcb);
4029 /* if exit due to PF check for async PF */
4030 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4031 vcpu->arch.apf.host_apf_flags =
4032 kvm_read_and_reset_apf_flags();
4034 vcpu->arch.regs_avail &= ~SVM_REGS_LAZY_LOAD_SET;
4037 * We need to handle MC intercepts here before the vcpu has a chance to
4038 * change the physical cpu
4040 if (unlikely(svm->vmcb->control.exit_code ==
4041 SVM_EXIT_EXCP_BASE + MC_VECTOR))
4042 svm_handle_mce(vcpu);
4044 svm_complete_interrupts(vcpu);
4046 if (is_guest_mode(vcpu))
4047 return EXIT_FASTPATH_NONE;
4049 return svm_exit_handlers_fastpath(vcpu);
4052 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
4055 struct vcpu_svm *svm = to_svm(vcpu);
4059 svm->vmcb->control.nested_cr3 = __sme_set(root_hpa);
4060 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
4062 hv_track_root_tdp(vcpu, root_hpa);
4064 cr3 = vcpu->arch.cr3;
4065 } else if (root_level >= PT64_ROOT_4LEVEL) {
4066 cr3 = __sme_set(root_hpa) | kvm_get_active_pcid(vcpu);
4068 /* PCID in the guest should be impossible with a 32-bit MMU. */
4069 WARN_ON_ONCE(kvm_get_active_pcid(vcpu));
4073 svm->vmcb->save.cr3 = cr3;
4074 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
4078 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4081 * Patch in the VMMCALL instruction:
4083 hypercall[0] = 0x0f;
4084 hypercall[1] = 0x01;
4085 hypercall[2] = 0xd9;
4089 * The kvm parameter can be NULL (module initialization, or invocation before
4090 * VM creation). Be sure to check the kvm parameter before using it.
4092 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
4095 case MSR_IA32_MCG_EXT_CTL:
4096 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4098 case MSR_IA32_SMBASE:
4099 if (!IS_ENABLED(CONFIG_KVM_SMM))
4101 /* SEV-ES guests do not support SMM, so report false */
4102 if (kvm && sev_es_guest(kvm))
4112 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
4114 struct vcpu_svm *svm = to_svm(vcpu);
4115 struct kvm_cpuid_entry2 *best;
4117 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4118 boot_cpu_has(X86_FEATURE_XSAVE) &&
4119 boot_cpu_has(X86_FEATURE_XSAVES);
4121 /* Update nrips enabled cache */
4122 svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
4123 guest_cpuid_has(vcpu, X86_FEATURE_NRIPS);
4125 svm->tsc_scaling_enabled = tsc_scaling && guest_cpuid_has(vcpu, X86_FEATURE_TSCRATEMSR);
4126 svm->lbrv_enabled = lbrv && guest_cpuid_has(vcpu, X86_FEATURE_LBRV);
4128 svm->v_vmload_vmsave_enabled = vls && guest_cpuid_has(vcpu, X86_FEATURE_V_VMSAVE_VMLOAD);
4130 svm->pause_filter_enabled = kvm_cpu_cap_has(X86_FEATURE_PAUSEFILTER) &&
4131 guest_cpuid_has(vcpu, X86_FEATURE_PAUSEFILTER);
4133 svm->pause_threshold_enabled = kvm_cpu_cap_has(X86_FEATURE_PFTHRESHOLD) &&
4134 guest_cpuid_has(vcpu, X86_FEATURE_PFTHRESHOLD);
4136 svm->vgif_enabled = vgif && guest_cpuid_has(vcpu, X86_FEATURE_VGIF);
4138 svm_recalc_instruction_intercepts(vcpu, svm);
4140 if (boot_cpu_has(X86_FEATURE_IBPB))
4141 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0,
4142 !!guest_has_pred_cmd_msr(vcpu));
4144 if (boot_cpu_has(X86_FEATURE_FLUSH_L1D))
4145 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_FLUSH_CMD, 0,
4146 !!guest_cpuid_has(vcpu, X86_FEATURE_FLUSH_L1D));
4148 /* For sev guests, the memory encryption bit is not reserved in CR3. */
4149 if (sev_guest(vcpu->kvm)) {
4150 best = kvm_find_cpuid_entry(vcpu, 0x8000001F);
4152 vcpu->arch.reserved_gpa_bits &= ~(1UL << (best->ebx & 0x3f));
4155 init_vmcb_after_set_cpuid(vcpu);
4158 static bool svm_has_wbinvd_exit(void)
4163 #define PRE_EX(exit) { .exit_code = (exit), \
4164 .stage = X86_ICPT_PRE_EXCEPT, }
4165 #define POST_EX(exit) { .exit_code = (exit), \
4166 .stage = X86_ICPT_POST_EXCEPT, }
4167 #define POST_MEM(exit) { .exit_code = (exit), \
4168 .stage = X86_ICPT_POST_MEMACCESS, }
4170 static const struct __x86_intercept {
4172 enum x86_intercept_stage stage;
4173 } x86_intercept_map[] = {
4174 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4175 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4176 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4177 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4178 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4179 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4180 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4181 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4182 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4183 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4184 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4185 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4186 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4187 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4188 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4189 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4190 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4191 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4192 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4193 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4194 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4195 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4196 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4197 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4198 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4199 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4200 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4201 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4202 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4203 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4204 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4205 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4206 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4207 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4208 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4209 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4210 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4211 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4212 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4213 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4214 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4215 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4216 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4217 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4218 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4219 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4220 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
4227 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4228 struct x86_instruction_info *info,
4229 enum x86_intercept_stage stage,
4230 struct x86_exception *exception)
4232 struct vcpu_svm *svm = to_svm(vcpu);
4233 int vmexit, ret = X86EMUL_CONTINUE;
4234 struct __x86_intercept icpt_info;
4235 struct vmcb *vmcb = svm->vmcb;
4237 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4240 icpt_info = x86_intercept_map[info->intercept];
4242 if (stage != icpt_info.stage)
4245 switch (icpt_info.exit_code) {
4246 case SVM_EXIT_READ_CR0:
4247 if (info->intercept == x86_intercept_cr_read)
4248 icpt_info.exit_code += info->modrm_reg;
4250 case SVM_EXIT_WRITE_CR0: {
4251 unsigned long cr0, val;
4253 if (info->intercept == x86_intercept_cr_write)
4254 icpt_info.exit_code += info->modrm_reg;
4256 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4257 info->intercept == x86_intercept_clts)
4260 if (!(vmcb12_is_intercept(&svm->nested.ctl,
4261 INTERCEPT_SELECTIVE_CR0)))
4264 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4265 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4267 if (info->intercept == x86_intercept_lmsw) {
4270 /* lmsw can't clear PE - catch this here */
4271 if (cr0 & X86_CR0_PE)
4276 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4280 case SVM_EXIT_READ_DR0:
4281 case SVM_EXIT_WRITE_DR0:
4282 icpt_info.exit_code += info->modrm_reg;
4285 if (info->intercept == x86_intercept_wrmsr)
4286 vmcb->control.exit_info_1 = 1;
4288 vmcb->control.exit_info_1 = 0;
4290 case SVM_EXIT_PAUSE:
4292 * We get this for NOP only, but pause
4293 * is rep not, check this here
4295 if (info->rep_prefix != REPE_PREFIX)
4298 case SVM_EXIT_IOIO: {
4302 if (info->intercept == x86_intercept_in ||
4303 info->intercept == x86_intercept_ins) {
4304 exit_info = ((info->src_val & 0xffff) << 16) |
4306 bytes = info->dst_bytes;
4308 exit_info = (info->dst_val & 0xffff) << 16;
4309 bytes = info->src_bytes;
4312 if (info->intercept == x86_intercept_outs ||
4313 info->intercept == x86_intercept_ins)
4314 exit_info |= SVM_IOIO_STR_MASK;
4316 if (info->rep_prefix)
4317 exit_info |= SVM_IOIO_REP_MASK;
4319 bytes = min(bytes, 4u);
4321 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4323 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4325 vmcb->control.exit_info_1 = exit_info;
4326 vmcb->control.exit_info_2 = info->next_rip;
4334 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4335 if (static_cpu_has(X86_FEATURE_NRIPS))
4336 vmcb->control.next_rip = info->next_rip;
4337 vmcb->control.exit_code = icpt_info.exit_code;
4338 vmexit = nested_svm_exit_handled(svm);
4340 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4347 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4349 if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_INTR)
4350 vcpu->arch.at_instruction_boundary = true;
4353 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4355 if (!kvm_pause_in_guest(vcpu->kvm))
4356 shrink_ple_window(vcpu);
4359 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4361 /* [63:9] are reserved. */
4362 vcpu->arch.mcg_cap &= 0x1ff;
4365 #ifdef CONFIG_KVM_SMM
4366 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4368 struct vcpu_svm *svm = to_svm(vcpu);
4370 /* Per APM Vol.2 15.22.2 "Response to SMI" */
4374 return is_smm(vcpu);
4377 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4379 struct vcpu_svm *svm = to_svm(vcpu);
4380 if (svm->nested.nested_run_pending)
4383 if (svm_smi_blocked(vcpu))
4386 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
4387 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4393 static int svm_enter_smm(struct kvm_vcpu *vcpu, union kvm_smram *smram)
4395 struct vcpu_svm *svm = to_svm(vcpu);
4396 struct kvm_host_map map_save;
4399 if (!is_guest_mode(vcpu))
4403 * 32-bit SMRAM format doesn't preserve EFER and SVM state. Userspace is
4404 * responsible for ensuring nested SVM and SMIs are mutually exclusive.
4407 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
4410 smram->smram64.svm_guest_flag = 1;
4411 smram->smram64.svm_guest_vmcb_gpa = svm->nested.vmcb12_gpa;
4413 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4414 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4415 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4417 ret = nested_svm_simple_vmexit(svm, SVM_EXIT_SW);
4422 * KVM uses VMCB01 to store L1 host state while L2 runs but
4423 * VMCB01 is going to be used during SMM and thus the state will
4424 * be lost. Temporary save non-VMLOAD/VMSAVE state to the host save
4425 * area pointed to by MSR_VM_HSAVE_PA. APM guarantees that the
4426 * format of the area is identical to guest save area offsetted
4427 * by 0x400 (matches the offset of 'struct vmcb_save_area'
4428 * within 'struct vmcb'). Note: HSAVE area may also be used by
4429 * L1 hypervisor to save additional host context (e.g. KVM does
4430 * that, see svm_prepare_switch_to_guest()) which must be
4433 if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr), &map_save))
4436 BUILD_BUG_ON(offsetof(struct vmcb, save) != 0x400);
4438 svm_copy_vmrun_state(map_save.hva + 0x400,
4439 &svm->vmcb01.ptr->save);
4441 kvm_vcpu_unmap(vcpu, &map_save, true);
4445 static int svm_leave_smm(struct kvm_vcpu *vcpu, const union kvm_smram *smram)
4447 struct vcpu_svm *svm = to_svm(vcpu);
4448 struct kvm_host_map map, map_save;
4449 struct vmcb *vmcb12;
4452 const struct kvm_smram_state_64 *smram64 = &smram->smram64;
4454 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
4457 /* Non-zero if SMI arrived while vCPU was in guest mode. */
4458 if (!smram64->svm_guest_flag)
4461 if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4464 if (!(smram64->efer & EFER_SVME))
4467 if (kvm_vcpu_map(vcpu, gpa_to_gfn(smram64->svm_guest_vmcb_gpa), &map))
4471 if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr), &map_save))
4474 if (svm_allocate_nested(svm))
4478 * Restore L1 host state from L1 HSAVE area as VMCB01 was
4479 * used during SMM (see svm_enter_smm())
4482 svm_copy_vmrun_state(&svm->vmcb01.ptr->save, map_save.hva + 0x400);
4485 * Enter the nested guest now
4488 vmcb_mark_all_dirty(svm->vmcb01.ptr);
4491 nested_copy_vmcb_control_to_cache(svm, &vmcb12->control);
4492 nested_copy_vmcb_save_to_cache(svm, &vmcb12->save);
4493 ret = enter_svm_guest_mode(vcpu, smram64->svm_guest_vmcb_gpa, vmcb12, false);
4498 svm->nested.nested_run_pending = 1;
4501 kvm_vcpu_unmap(vcpu, &map_save, true);
4503 kvm_vcpu_unmap(vcpu, &map, true);
4507 static void svm_enable_smi_window(struct kvm_vcpu *vcpu)
4509 struct vcpu_svm *svm = to_svm(vcpu);
4511 if (!gif_set(svm)) {
4513 svm_set_intercept(svm, INTERCEPT_STGI);
4514 /* STGI will cause a vm exit */
4516 /* We must be in SMM; RSM will cause a vmexit anyway. */
4521 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, int emul_type,
4522 void *insn, int insn_len)
4524 bool smep, smap, is_user;
4527 /* Emulation is always possible when KVM has access to all guest state. */
4528 if (!sev_guest(vcpu->kvm))
4531 /* #UD and #GP should never be intercepted for SEV guests. */
4532 WARN_ON_ONCE(emul_type & (EMULTYPE_TRAP_UD |
4533 EMULTYPE_TRAP_UD_FORCED |
4534 EMULTYPE_VMWARE_GP));
4537 * Emulation is impossible for SEV-ES guests as KVM doesn't have access
4538 * to guest register state.
4540 if (sev_es_guest(vcpu->kvm))
4544 * Emulation is possible if the instruction is already decoded, e.g.
4545 * when completing I/O after returning from userspace.
4547 if (emul_type & EMULTYPE_NO_DECODE)
4551 * Emulation is possible for SEV guests if and only if a prefilled
4552 * buffer containing the bytes of the intercepted instruction is
4553 * available. SEV guest memory is encrypted with a guest specific key
4554 * and cannot be decrypted by KVM, i.e. KVM would read cyphertext and
4557 * Inject #UD if KVM reached this point without an instruction buffer.
4558 * In practice, this path should never be hit by a well-behaved guest,
4559 * e.g. KVM doesn't intercept #UD or #GP for SEV guests, but this path
4560 * is still theoretically reachable, e.g. via unaccelerated fault-like
4561 * AVIC access, and needs to be handled by KVM to avoid putting the
4562 * guest into an infinite loop. Injecting #UD is somewhat arbitrary,
4563 * but its the least awful option given lack of insight into the guest.
4565 if (unlikely(!insn)) {
4566 kvm_queue_exception(vcpu, UD_VECTOR);
4571 * Emulate for SEV guests if the insn buffer is not empty. The buffer
4572 * will be empty if the DecodeAssist microcode cannot fetch bytes for
4573 * the faulting instruction because the code fetch itself faulted, e.g.
4574 * the guest attempted to fetch from emulated MMIO or a guest page
4575 * table used to translate CS:RIP resides in emulated MMIO.
4577 if (likely(insn_len))
4581 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4584 * When CPU raises #NPF on guest data access and vCPU CR4.SMAP=1, it is
4585 * possible that CPU microcode implementing DecodeAssist will fail to
4586 * read guest memory at CS:RIP and vmcb.GuestIntrBytes will incorrectly
4587 * be '0'. This happens because microcode reads CS:RIP using a _data_
4588 * loap uop with CPL=0 privileges. If the load hits a SMAP #PF, ucode
4589 * gives up and does not fill the instruction bytes buffer.
4591 * As above, KVM reaches this point iff the VM is an SEV guest, the CPU
4592 * supports DecodeAssist, a #NPF was raised, KVM's page fault handler
4593 * triggered emulation (e.g. for MMIO), and the CPU returned 0 in the
4594 * GuestIntrBytes field of the VMCB.
4596 * This does _not_ mean that the erratum has been encountered, as the
4597 * DecodeAssist will also fail if the load for CS:RIP hits a legitimate
4598 * #PF, e.g. if the guest attempt to execute from emulated MMIO and
4599 * encountered a reserved/not-present #PF.
4601 * To hit the erratum, the following conditions must be true:
4602 * 1. CR4.SMAP=1 (obviously).
4603 * 2. CR4.SMEP=0 || CPL=3. If SMEP=1 and CPL<3, the erratum cannot
4604 * have been hit as the guest would have encountered a SMEP
4605 * violation #PF, not a #NPF.
4606 * 3. The #NPF is not due to a code fetch, in which case failure to
4607 * retrieve the instruction bytes is legitimate (see abvoe).
4609 * In addition, don't apply the erratum workaround if the #NPF occurred
4610 * while translating guest page tables (see below).
4612 error_code = to_svm(vcpu)->vmcb->control.exit_info_1;
4613 if (error_code & (PFERR_GUEST_PAGE_MASK | PFERR_FETCH_MASK))
4616 smep = kvm_is_cr4_bit_set(vcpu, X86_CR4_SMEP);
4617 smap = kvm_is_cr4_bit_set(vcpu, X86_CR4_SMAP);
4618 is_user = svm_get_cpl(vcpu) == 3;
4619 if (smap && (!smep || is_user)) {
4620 pr_err_ratelimited("SEV Guest triggered AMD Erratum 1096\n");
4623 * If the fault occurred in userspace, arbitrarily inject #GP
4624 * to avoid killing the guest and to hopefully avoid confusing
4625 * the guest kernel too much, e.g. injecting #PF would not be
4626 * coherent with respect to the guest's page tables. Request
4627 * triple fault if the fault occurred in the kernel as there's
4628 * no fault that KVM can inject without confusing the guest.
4629 * In practice, the triple fault is moot as no sane SEV kernel
4630 * will execute from user memory while also running with SMAP=1.
4633 kvm_inject_gp(vcpu, 0);
4635 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4640 * If the erratum was not hit, simply resume the guest and let it fault
4641 * again. While awful, e.g. the vCPU may get stuck in an infinite loop
4642 * if the fault is at CPL=0, it's the lesser of all evils. Exiting to
4643 * userspace will kill the guest, and letting the emulator read garbage
4644 * will yield random behavior and potentially corrupt the guest.
4646 * Simply resuming the guest is technically not a violation of the SEV
4647 * architecture. AMD's APM states that all code fetches and page table
4648 * accesses for SEV guest are encrypted, regardless of the C-Bit. The
4649 * APM also states that encrypted accesses to MMIO are "ignored", but
4650 * doesn't explicitly define "ignored", i.e. doing nothing and letting
4651 * the guest spin is technically "ignoring" the access.
4656 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4658 struct vcpu_svm *svm = to_svm(vcpu);
4660 return !gif_set(svm);
4663 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
4665 if (!sev_es_guest(vcpu->kvm))
4666 return kvm_vcpu_deliver_sipi_vector(vcpu, vector);
4668 sev_vcpu_deliver_sipi_vector(vcpu, vector);
4671 static void svm_vm_destroy(struct kvm *kvm)
4673 avic_vm_destroy(kvm);
4674 sev_vm_destroy(kvm);
4677 static int svm_vm_init(struct kvm *kvm)
4679 if (!pause_filter_count || !pause_filter_thresh)
4680 kvm->arch.pause_in_guest = true;
4683 int ret = avic_vm_init(kvm);
4691 static struct kvm_x86_ops svm_x86_ops __initdata = {
4692 .name = KBUILD_MODNAME,
4694 .check_processor_compatibility = svm_check_processor_compat,
4696 .hardware_unsetup = svm_hardware_unsetup,
4697 .hardware_enable = svm_hardware_enable,
4698 .hardware_disable = svm_hardware_disable,
4699 .has_emulated_msr = svm_has_emulated_msr,
4701 .vcpu_create = svm_vcpu_create,
4702 .vcpu_free = svm_vcpu_free,
4703 .vcpu_reset = svm_vcpu_reset,
4705 .vm_size = sizeof(struct kvm_svm),
4706 .vm_init = svm_vm_init,
4707 .vm_destroy = svm_vm_destroy,
4709 .prepare_switch_to_guest = svm_prepare_switch_to_guest,
4710 .vcpu_load = svm_vcpu_load,
4711 .vcpu_put = svm_vcpu_put,
4712 .vcpu_blocking = avic_vcpu_blocking,
4713 .vcpu_unblocking = avic_vcpu_unblocking,
4715 .update_exception_bitmap = svm_update_exception_bitmap,
4716 .get_msr_feature = svm_get_msr_feature,
4717 .get_msr = svm_get_msr,
4718 .set_msr = svm_set_msr,
4719 .get_segment_base = svm_get_segment_base,
4720 .get_segment = svm_get_segment,
4721 .set_segment = svm_set_segment,
4722 .get_cpl = svm_get_cpl,
4723 .get_cs_db_l_bits = svm_get_cs_db_l_bits,
4724 .set_cr0 = svm_set_cr0,
4725 .post_set_cr3 = sev_post_set_cr3,
4726 .is_valid_cr4 = svm_is_valid_cr4,
4727 .set_cr4 = svm_set_cr4,
4728 .set_efer = svm_set_efer,
4729 .get_idt = svm_get_idt,
4730 .set_idt = svm_set_idt,
4731 .get_gdt = svm_get_gdt,
4732 .set_gdt = svm_set_gdt,
4733 .set_dr7 = svm_set_dr7,
4734 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4735 .cache_reg = svm_cache_reg,
4736 .get_rflags = svm_get_rflags,
4737 .set_rflags = svm_set_rflags,
4738 .get_if_flag = svm_get_if_flag,
4740 .flush_tlb_all = svm_flush_tlb_current,
4741 .flush_tlb_current = svm_flush_tlb_current,
4742 .flush_tlb_gva = svm_flush_tlb_gva,
4743 .flush_tlb_guest = svm_flush_tlb_current,
4745 .vcpu_pre_run = svm_vcpu_pre_run,
4746 .vcpu_run = svm_vcpu_run,
4747 .handle_exit = svm_handle_exit,
4748 .skip_emulated_instruction = svm_skip_emulated_instruction,
4749 .update_emulated_instruction = NULL,
4750 .set_interrupt_shadow = svm_set_interrupt_shadow,
4751 .get_interrupt_shadow = svm_get_interrupt_shadow,
4752 .patch_hypercall = svm_patch_hypercall,
4753 .inject_irq = svm_inject_irq,
4754 .inject_nmi = svm_inject_nmi,
4755 .inject_exception = svm_inject_exception,
4756 .cancel_injection = svm_cancel_injection,
4757 .interrupt_allowed = svm_interrupt_allowed,
4758 .nmi_allowed = svm_nmi_allowed,
4759 .get_nmi_mask = svm_get_nmi_mask,
4760 .set_nmi_mask = svm_set_nmi_mask,
4761 .enable_nmi_window = svm_enable_nmi_window,
4762 .enable_irq_window = svm_enable_irq_window,
4763 .update_cr8_intercept = svm_update_cr8_intercept,
4764 .set_virtual_apic_mode = avic_refresh_virtual_apic_mode,
4765 .refresh_apicv_exec_ctrl = avic_refresh_apicv_exec_ctrl,
4766 .apicv_post_state_restore = avic_apicv_post_state_restore,
4767 .required_apicv_inhibits = AVIC_REQUIRED_APICV_INHIBITS,
4769 .get_exit_info = svm_get_exit_info,
4771 .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4773 .has_wbinvd_exit = svm_has_wbinvd_exit,
4775 .get_l2_tsc_offset = svm_get_l2_tsc_offset,
4776 .get_l2_tsc_multiplier = svm_get_l2_tsc_multiplier,
4777 .write_tsc_offset = svm_write_tsc_offset,
4778 .write_tsc_multiplier = svm_write_tsc_multiplier,
4780 .load_mmu_pgd = svm_load_mmu_pgd,
4782 .check_intercept = svm_check_intercept,
4783 .handle_exit_irqoff = svm_handle_exit_irqoff,
4785 .request_immediate_exit = __kvm_request_immediate_exit,
4787 .sched_in = svm_sched_in,
4789 .nested_ops = &svm_nested_ops,
4791 .deliver_interrupt = svm_deliver_interrupt,
4792 .pi_update_irte = avic_pi_update_irte,
4793 .setup_mce = svm_setup_mce,
4795 #ifdef CONFIG_KVM_SMM
4796 .smi_allowed = svm_smi_allowed,
4797 .enter_smm = svm_enter_smm,
4798 .leave_smm = svm_leave_smm,
4799 .enable_smi_window = svm_enable_smi_window,
4802 .mem_enc_ioctl = sev_mem_enc_ioctl,
4803 .mem_enc_register_region = sev_mem_enc_register_region,
4804 .mem_enc_unregister_region = sev_mem_enc_unregister_region,
4805 .guest_memory_reclaimed = sev_guest_memory_reclaimed,
4807 .vm_copy_enc_context_from = sev_vm_copy_enc_context_from,
4808 .vm_move_enc_context_from = sev_vm_move_enc_context_from,
4810 .can_emulate_instruction = svm_can_emulate_instruction,
4812 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4814 .msr_filter_changed = svm_msr_filter_changed,
4815 .complete_emulated_msr = svm_complete_emulated_msr,
4817 .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector,
4818 .vcpu_get_apicv_inhibit_reasons = avic_vcpu_get_apicv_inhibit_reasons,
4822 * The default MMIO mask is a single bit (excluding the present bit),
4823 * which could conflict with the memory encryption bit. Check for
4824 * memory encryption support and override the default MMIO mask if
4825 * memory encryption is enabled.
4827 static __init void svm_adjust_mmio_mask(void)
4829 unsigned int enc_bit, mask_bit;
4832 /* If there is no memory encryption support, use existing mask */
4833 if (cpuid_eax(0x80000000) < 0x8000001f)
4836 /* If memory encryption is not enabled, use existing mask */
4837 rdmsrl(MSR_AMD64_SYSCFG, msr);
4838 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
4841 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
4842 mask_bit = boot_cpu_data.x86_phys_bits;
4844 /* Increment the mask bit if it is the same as the encryption bit */
4845 if (enc_bit == mask_bit)
4849 * If the mask bit location is below 52, then some bits above the
4850 * physical addressing limit will always be reserved, so use the
4851 * rsvd_bits() function to generate the mask. This mask, along with
4852 * the present bit, will be used to generate a page fault with
4855 * If the mask bit location is 52 (or above), then clear the mask.
4857 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
4859 kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
4862 static __init void svm_set_cpu_caps(void)
4866 kvm_caps.supported_perf_cap = 0;
4867 kvm_caps.supported_xss = 0;
4869 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
4871 kvm_cpu_cap_set(X86_FEATURE_SVM);
4872 kvm_cpu_cap_set(X86_FEATURE_VMCBCLEAN);
4875 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
4878 kvm_cpu_cap_set(X86_FEATURE_NPT);
4881 kvm_cpu_cap_set(X86_FEATURE_TSCRATEMSR);
4884 kvm_cpu_cap_set(X86_FEATURE_V_VMSAVE_VMLOAD);
4886 kvm_cpu_cap_set(X86_FEATURE_LBRV);
4888 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER))
4889 kvm_cpu_cap_set(X86_FEATURE_PAUSEFILTER);
4891 if (boot_cpu_has(X86_FEATURE_PFTHRESHOLD))
4892 kvm_cpu_cap_set(X86_FEATURE_PFTHRESHOLD);
4895 kvm_cpu_cap_set(X86_FEATURE_VGIF);
4897 /* Nested VM can receive #VMEXIT instead of triggering #GP */
4898 kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK);
4901 /* CPUID 0x80000008 */
4902 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
4903 boot_cpu_has(X86_FEATURE_AMD_SSBD))
4904 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
4906 /* AMD PMU PERFCTR_CORE CPUID */
4907 if (enable_pmu && boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
4908 kvm_cpu_cap_set(X86_FEATURE_PERFCTR_CORE);
4910 /* CPUID 0x8000001F (SME/SEV features) */
4914 static __init int svm_hardware_setup(void)
4917 struct page *iopm_pages;
4920 unsigned int order = get_order(IOPM_SIZE);
4923 * NX is required for shadow paging and for NPT if the NX huge pages
4924 * mitigation is enabled.
4926 if (!boot_cpu_has(X86_FEATURE_NX)) {
4927 pr_err_ratelimited("NX (Execute Disable) not supported\n");
4930 kvm_enable_efer_bits(EFER_NX);
4932 iopm_pages = alloc_pages(GFP_KERNEL, order);
4937 iopm_va = page_address(iopm_pages);
4938 memset(iopm_va, 0xff, PAGE_SIZE * (1 << order));
4939 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
4941 init_msrpm_offsets();
4943 kvm_caps.supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
4944 XFEATURE_MASK_BNDCSR);
4946 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
4947 kvm_enable_efer_bits(EFER_FFXSR);
4950 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
4951 tsc_scaling = false;
4953 pr_info("TSC scaling supported\n");
4954 kvm_caps.has_tsc_control = true;
4957 kvm_caps.max_tsc_scaling_ratio = SVM_TSC_RATIO_MAX;
4958 kvm_caps.tsc_scaling_ratio_frac_bits = 32;
4960 tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX);
4962 if (boot_cpu_has(X86_FEATURE_AUTOIBRS))
4963 kvm_enable_efer_bits(EFER_AUTOIBRS);
4965 /* Check for pause filtering support */
4966 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
4967 pause_filter_count = 0;
4968 pause_filter_thresh = 0;
4969 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
4970 pause_filter_thresh = 0;
4974 pr_info("Nested Virtualization enabled\n");
4975 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
4979 * KVM's MMU doesn't support using 2-level paging for itself, and thus
4980 * NPT isn't supported if the host is using 2-level paging since host
4981 * CR4 is unchanged on VMRUN.
4983 if (!IS_ENABLED(CONFIG_X86_64) && !IS_ENABLED(CONFIG_X86_PAE))
4984 npt_enabled = false;
4986 if (!boot_cpu_has(X86_FEATURE_NPT))
4987 npt_enabled = false;
4989 /* Force VM NPT level equal to the host's paging level */
4990 kvm_configure_mmu(npt_enabled, get_npt_level(),
4991 get_npt_level(), PG_LEVEL_1G);
4992 pr_info("Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
4994 /* Setup shadow_me_value and shadow_me_mask */
4995 kvm_mmu_set_me_spte_mask(sme_me_mask, sme_me_mask);
4997 svm_adjust_mmio_mask();
5000 * Note, SEV setup consumes npt_enabled and enable_mmio_caching (which
5001 * may be modified by svm_adjust_mmio_mask()).
5003 sev_hardware_setup();
5005 svm_hv_hardware_setup();
5007 for_each_possible_cpu(cpu) {
5008 r = svm_cpu_init(cpu);
5014 if (!boot_cpu_has(X86_FEATURE_NRIPS))
5018 enable_apicv = avic = avic && avic_hardware_setup();
5020 if (!enable_apicv) {
5021 svm_x86_ops.vcpu_blocking = NULL;
5022 svm_x86_ops.vcpu_unblocking = NULL;
5023 svm_x86_ops.vcpu_get_apicv_inhibit_reasons = NULL;
5024 } else if (!x2avic_enabled) {
5025 svm_x86_ops.allow_apicv_in_x2apic_without_x2apic_virtualization = true;
5030 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
5031 !IS_ENABLED(CONFIG_X86_64)) {
5034 pr_info("Virtual VMLOAD VMSAVE supported\n");
5038 if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
5039 svm_gp_erratum_intercept = false;
5042 if (!boot_cpu_has(X86_FEATURE_VGIF))
5045 pr_info("Virtual GIF supported\n");
5049 if (!boot_cpu_has(X86_FEATURE_LBRV))
5052 pr_info("LBR virtualization supported\n");
5056 pr_info("PMU virtualization is disabled\n");
5061 * It seems that on AMD processors PTE's accessed bit is
5062 * being set by the CPU hardware before the NPF vmexit.
5063 * This is not expected behaviour and our tests fail because
5065 * A workaround here is to disable support for
5066 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
5067 * In this case userspace can know if there is support using
5068 * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
5070 * If future AMD CPU models change the behaviour described above,
5071 * this variable can be changed accordingly
5073 allow_smaller_maxphyaddr = !npt_enabled;
5078 svm_hardware_unsetup();
5083 static struct kvm_x86_init_ops svm_init_ops __initdata = {
5084 .hardware_setup = svm_hardware_setup,
5086 .runtime_ops = &svm_x86_ops,
5087 .pmu_ops = &amd_pmu_ops,
5090 static int __init svm_init(void)
5094 __unused_size_checks();
5096 if (!kvm_is_svm_supported())
5099 r = kvm_x86_vendor_init(&svm_init_ops);
5104 * Common KVM initialization _must_ come last, after this, /dev/kvm is
5105 * exposed to userspace!
5107 r = kvm_init(sizeof(struct vcpu_svm), __alignof__(struct vcpu_svm),
5115 kvm_x86_vendor_exit();
5119 static void __exit svm_exit(void)
5122 kvm_x86_vendor_exit();
5125 module_init(svm_init)
5126 module_exit(svm_exit)