1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Yaniv Kamay <yaniv@qumranet.com>
12 * Avi Kivity <avi@qumranet.com>
15 #define pr_fmt(fmt) "SVM: " fmt
17 #include <linux/kvm_types.h>
18 #include <linux/hashtable.h>
19 #include <linux/amd-iommu.h>
20 #include <linux/kvm_host.h>
22 #include <asm/irq_remapping.h>
30 /* AVIC GATAG is encoded using VM and VCPU IDs */
31 #define AVIC_VCPU_ID_BITS 8
32 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
34 #define AVIC_VM_ID_BITS 24
35 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
36 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
38 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
39 (y & AVIC_VCPU_ID_MASK))
40 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
41 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
44 * This hash table is used to map VM_ID to a struct kvm_svm,
45 * when handling AMD IOMMU GALOG notification to schedule in
48 #define SVM_VM_DATA_HASH_BITS 8
49 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
50 static u32 next_vm_id = 0;
51 static bool next_vm_id_wrapped = 0;
52 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
55 * This is a wrapper of struct amd_iommu_ir_data.
57 struct amd_svm_iommu_ir {
58 struct list_head node; /* Used by SVM for per-vcpu ir_list */
59 void *data; /* Storing pointer to struct amd_ir_data */
64 * This function is called from IOMMU driver to notify
65 * SVM to schedule in a particular vCPU of a particular VM.
67 int avic_ga_log_notifier(u32 ga_tag)
70 struct kvm_svm *kvm_svm;
71 struct kvm_vcpu *vcpu = NULL;
72 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
73 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
75 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
76 trace_kvm_avic_ga_log(vm_id, vcpu_id);
78 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
79 hash_for_each_possible(svm_vm_data_hash, kvm_svm, hnode, vm_id) {
80 if (kvm_svm->avic_vm_id != vm_id)
82 vcpu = kvm_get_vcpu_by_id(&kvm_svm->kvm, vcpu_id);
85 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
88 * At this point, the IOMMU should have already set the pending
89 * bit in the vAPIC backing page. So, we just need to schedule
93 kvm_vcpu_wake_up(vcpu);
98 void avic_vm_destroy(struct kvm *kvm)
101 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
106 if (kvm_svm->avic_logical_id_table_page)
107 __free_page(kvm_svm->avic_logical_id_table_page);
108 if (kvm_svm->avic_physical_id_table_page)
109 __free_page(kvm_svm->avic_physical_id_table_page);
111 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
112 hash_del(&kvm_svm->hnode);
113 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
116 int avic_vm_init(struct kvm *kvm)
120 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
129 /* Allocating physical APIC ID table (4KB) */
130 p_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
134 kvm_svm->avic_physical_id_table_page = p_page;
136 /* Allocating logical APIC ID table (4KB) */
137 l_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
141 kvm_svm->avic_logical_id_table_page = l_page;
143 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
145 vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
146 if (vm_id == 0) { /* id is 1-based, zero is not okay */
147 next_vm_id_wrapped = 1;
150 /* Is it still in use? Only possible if wrapped at least once */
151 if (next_vm_id_wrapped) {
152 hash_for_each_possible(svm_vm_data_hash, k2, hnode, vm_id) {
153 if (k2->avic_vm_id == vm_id)
157 kvm_svm->avic_vm_id = vm_id;
158 hash_add(svm_vm_data_hash, &kvm_svm->hnode, kvm_svm->avic_vm_id);
159 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
164 avic_vm_destroy(kvm);
168 void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *vmcb)
170 struct kvm_svm *kvm_svm = to_kvm_svm(svm->vcpu.kvm);
171 phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
172 phys_addr_t lpa = __sme_set(page_to_phys(kvm_svm->avic_logical_id_table_page));
173 phys_addr_t ppa = __sme_set(page_to_phys(kvm_svm->avic_physical_id_table_page));
175 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
176 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
177 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
178 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
179 vmcb->control.avic_vapic_bar = APIC_DEFAULT_PHYS_BASE & VMCB_AVIC_APIC_BAR_MASK;
181 if (kvm_apicv_activated(svm->vcpu.kvm))
182 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
184 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
187 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
190 u64 *avic_physical_id_table;
191 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
193 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
196 avic_physical_id_table = page_address(kvm_svm->avic_physical_id_table_page);
198 return &avic_physical_id_table[index];
203 * AVIC hardware walks the nested page table to check permissions,
204 * but does not use the SPA address specified in the leaf page
205 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
206 * field of the VMCB. Therefore, we set up the
207 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
209 static int avic_alloc_access_page(struct kvm *kvm)
214 mutex_lock(&kvm->slots_lock);
216 if (kvm->arch.apic_access_memslot_enabled)
219 ret = __x86_set_memory_region(kvm,
220 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
221 APIC_DEFAULT_PHYS_BASE,
228 kvm->arch.apic_access_memslot_enabled = true;
230 mutex_unlock(&kvm->slots_lock);
234 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
236 u64 *entry, new_entry;
237 int id = vcpu->vcpu_id;
238 struct vcpu_svm *svm = to_svm(vcpu);
240 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
243 if (!vcpu->arch.apic->regs)
246 if (kvm_apicv_activated(vcpu->kvm)) {
249 ret = avic_alloc_access_page(vcpu->kvm);
254 svm->avic_backing_page = virt_to_page(vcpu->arch.apic->regs);
256 /* Setting AVIC backing page address in the phy APIC ID table */
257 entry = avic_get_physical_id_entry(vcpu, id);
261 new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
262 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
263 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
264 WRITE_ONCE(*entry, new_entry);
266 svm->avic_physical_id_cache = entry;
271 void avic_ring_doorbell(struct kvm_vcpu *vcpu)
274 * Note, the vCPU could get migrated to a different pCPU at any point,
275 * which could result in signalling the wrong/previous pCPU. But if
276 * that happens the vCPU is guaranteed to do a VMRUN (after being
277 * migrated) and thus will process pending interrupts, i.e. a doorbell
278 * is not needed (and the spurious one is harmless).
280 int cpu = READ_ONCE(vcpu->cpu);
282 if (cpu != get_cpu())
283 wrmsrl(MSR_AMD64_SVM_AVIC_DOORBELL, kvm_cpu_get_apicid(cpu));
288 * A fast-path version of avic_kick_target_vcpus(), which attempts to match
289 * destination APIC ID to vCPU without looping through all vCPUs.
291 static int avic_kick_target_vcpus_fast(struct kvm *kvm, struct kvm_lapic *source,
292 u32 icrl, u32 icrh, u32 index)
294 u32 l1_physical_id, dest;
295 struct kvm_vcpu *target_vcpu;
296 int dest_mode = icrl & APIC_DEST_MASK;
297 int shorthand = icrl & APIC_SHORT_MASK;
298 struct kvm_svm *kvm_svm = to_kvm_svm(kvm);
300 if (shorthand != APIC_DEST_NOSHORT)
303 if (apic_x2apic_mode(source))
306 dest = GET_APIC_DEST_FIELD(icrh);
308 if (dest_mode == APIC_DEST_PHYSICAL) {
309 /* broadcast destination, use slow path */
310 if (apic_x2apic_mode(source) && dest == X2APIC_BROADCAST)
312 if (!apic_x2apic_mode(source) && dest == APIC_BROADCAST)
315 l1_physical_id = dest;
317 if (WARN_ON_ONCE(l1_physical_id != index))
324 if (apic_x2apic_mode(source)) {
325 /* 16 bit dest mask, 16 bit cluster id */
326 bitmap = dest & 0xFFFF0000;
327 cluster = (dest >> 16) << 4;
328 } else if (kvm_lapic_get_reg(source, APIC_DFR) == APIC_DFR_FLAT) {
333 /* 4 bit desk mask, 4 bit cluster id */
335 cluster = (dest >> 4) << 2;
338 if (unlikely(!bitmap))
339 /* guest bug: nobody to send the logical interrupt to */
342 if (!is_power_of_2(bitmap))
343 /* multiple logical destinations, use slow path */
346 logid_index = cluster + __ffs(bitmap);
348 if (apic_x2apic_mode(source)) {
349 l1_physical_id = logid_index;
351 u32 *avic_logical_id_table =
352 page_address(kvm_svm->avic_logical_id_table_page);
354 u32 logid_entry = avic_logical_id_table[logid_index];
356 if (WARN_ON_ONCE(index != logid_index))
359 /* guest bug: non existing/reserved logical destination */
360 if (unlikely(!(logid_entry & AVIC_LOGICAL_ID_ENTRY_VALID_MASK)))
363 l1_physical_id = logid_entry &
364 AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
368 target_vcpu = kvm_get_vcpu_by_id(kvm, l1_physical_id);
369 if (unlikely(!target_vcpu))
370 /* guest bug: non existing vCPU is a target of this IPI*/
373 target_vcpu->arch.apic->irr_pending = true;
374 svm_complete_interrupt_delivery(target_vcpu,
375 icrl & APIC_MODE_MASK,
376 icrl & APIC_INT_LEVELTRIG,
377 icrl & APIC_VECTOR_MASK);
381 static void avic_kick_target_vcpus(struct kvm *kvm, struct kvm_lapic *source,
382 u32 icrl, u32 icrh, u32 index)
385 struct kvm_vcpu *vcpu;
387 if (!avic_kick_target_vcpus_fast(kvm, source, icrl, icrh, index))
390 trace_kvm_avic_kick_vcpu_slowpath(icrh, icrl, index);
393 * Wake any target vCPUs that are blocking, i.e. waiting for a wake
394 * event. There's no need to signal doorbells, as hardware has handled
395 * vCPUs that were in guest at the time of the IPI, and vCPUs that have
396 * since entered the guest will have processed pending IRQs at VMRUN.
398 kvm_for_each_vcpu(i, vcpu, kvm) {
399 if (kvm_apic_match_dest(vcpu, source, icrl & APIC_SHORT_MASK,
400 GET_APIC_DEST_FIELD(icrh),
401 icrl & APIC_DEST_MASK)) {
402 vcpu->arch.apic->irr_pending = true;
403 svm_complete_interrupt_delivery(vcpu,
404 icrl & APIC_MODE_MASK,
405 icrl & APIC_INT_LEVELTRIG,
406 icrl & APIC_VECTOR_MASK);
411 int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu)
413 struct vcpu_svm *svm = to_svm(vcpu);
414 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
415 u32 icrl = svm->vmcb->control.exit_info_1;
416 u32 id = svm->vmcb->control.exit_info_2 >> 32;
417 u32 index = svm->vmcb->control.exit_info_2 & 0x1FF;
418 struct kvm_lapic *apic = vcpu->arch.apic;
420 trace_kvm_avic_incomplete_ipi(vcpu->vcpu_id, icrh, icrl, id, index);
423 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
425 * Emulate IPIs that are not handled by AVIC hardware, which
426 * only virtualizes Fixed, Edge-Triggered INTRs. The exit is
427 * a trap, e.g. ICR holds the correct value and RIP has been
428 * advanced, KVM is responsible only for emulating the IPI.
429 * Sadly, hardware may sometimes leave the BUSY flag set, in
430 * which case KVM needs to emulate the ICR write as well in
431 * order to clear the BUSY flag.
433 if (icrl & APIC_ICR_BUSY)
434 kvm_apic_write_nodecode(vcpu, APIC_ICR);
436 kvm_apic_send_ipi(apic, icrl, icrh);
438 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING:
440 * At this point, we expect that the AVIC HW has already
441 * set the appropriate IRR bits on the valid target
442 * vcpus. So, we just need to kick the appropriate vcpu.
444 avic_kick_target_vcpus(vcpu->kvm, apic, icrl, icrh, index);
446 case AVIC_IPI_FAILURE_INVALID_TARGET:
448 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
449 WARN_ONCE(1, "Invalid backing page\n");
452 pr_err("Unknown IPI interception\n");
458 unsigned long avic_vcpu_get_apicv_inhibit_reasons(struct kvm_vcpu *vcpu)
460 if (is_guest_mode(vcpu))
461 return APICV_INHIBIT_REASON_NESTED;
465 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
467 struct kvm_svm *kvm_svm = to_kvm_svm(vcpu->kvm);
469 u32 *logical_apic_id_table;
470 int dlid = GET_APIC_LOGICAL_ID(ldr);
475 if (flat) { /* flat */
476 index = ffs(dlid) - 1;
479 } else { /* cluster */
480 int cluster = (dlid & 0xf0) >> 4;
481 int apic = ffs(dlid & 0x0f) - 1;
483 if ((apic < 0) || (apic > 7) ||
486 index = (cluster << 2) + apic;
489 logical_apic_id_table = (u32 *) page_address(kvm_svm->avic_logical_id_table_page);
491 return &logical_apic_id_table[index];
494 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr)
497 u32 *entry, new_entry;
499 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
500 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
504 new_entry = READ_ONCE(*entry);
505 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
506 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
507 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
508 WRITE_ONCE(*entry, new_entry);
513 static void avic_invalidate_logical_id_entry(struct kvm_vcpu *vcpu)
515 struct vcpu_svm *svm = to_svm(vcpu);
516 bool flat = svm->dfr_reg == APIC_DFR_FLAT;
517 u32 *entry = avic_get_logical_id_entry(vcpu, svm->ldr_reg, flat);
520 clear_bit(AVIC_LOGICAL_ID_ENTRY_VALID_BIT, (unsigned long *)entry);
523 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
526 struct vcpu_svm *svm = to_svm(vcpu);
527 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
528 u32 id = kvm_xapic_id(vcpu->arch.apic);
530 if (ldr == svm->ldr_reg)
533 avic_invalidate_logical_id_entry(vcpu);
536 ret = avic_ldr_write(vcpu, id, ldr);
544 static void avic_handle_dfr_update(struct kvm_vcpu *vcpu)
546 struct vcpu_svm *svm = to_svm(vcpu);
547 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
549 if (svm->dfr_reg == dfr)
552 avic_invalidate_logical_id_entry(vcpu);
556 static int avic_unaccel_trap_write(struct kvm_vcpu *vcpu)
558 u32 offset = to_svm(vcpu)->vmcb->control.exit_info_1 &
559 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
563 if (avic_handle_ldr_update(vcpu))
567 avic_handle_dfr_update(vcpu);
573 kvm_apic_write_nodecode(vcpu, offset);
577 static bool is_avic_unaccelerated_access_trap(u32 offset)
606 int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu)
608 struct vcpu_svm *svm = to_svm(vcpu);
610 u32 offset = svm->vmcb->control.exit_info_1 &
611 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
612 u32 vector = svm->vmcb->control.exit_info_2 &
613 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
614 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
615 AVIC_UNACCEL_ACCESS_WRITE_MASK;
616 bool trap = is_avic_unaccelerated_access_trap(offset);
618 trace_kvm_avic_unaccelerated_access(vcpu->vcpu_id, offset,
619 trap, write, vector);
622 WARN_ONCE(!write, "svm: Handling trap read.\n");
623 ret = avic_unaccel_trap_write(vcpu);
626 ret = kvm_emulate_instruction(vcpu, 0);
632 int avic_init_vcpu(struct vcpu_svm *svm)
635 struct kvm_vcpu *vcpu = &svm->vcpu;
637 if (!enable_apicv || !irqchip_in_kernel(vcpu->kvm))
640 ret = avic_init_backing_page(vcpu);
644 INIT_LIST_HEAD(&svm->ir_list);
645 spin_lock_init(&svm->ir_list_lock);
646 svm->dfr_reg = APIC_DFR_FLAT;
651 void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu)
653 avic_handle_dfr_update(vcpu);
654 avic_handle_ldr_update(vcpu);
657 static int avic_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate)
661 struct amd_svm_iommu_ir *ir;
662 struct vcpu_svm *svm = to_svm(vcpu);
664 if (!kvm_arch_has_assigned_device(vcpu->kvm))
668 * Here, we go through the per-vcpu ir_list to update all existing
669 * interrupt remapping table entry targeting this vcpu.
671 spin_lock_irqsave(&svm->ir_list_lock, flags);
673 if (list_empty(&svm->ir_list))
676 list_for_each_entry(ir, &svm->ir_list, node) {
678 ret = amd_iommu_activate_guest_mode(ir->data);
680 ret = amd_iommu_deactivate_guest_mode(ir->data);
685 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
689 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
692 struct amd_svm_iommu_ir *cur;
694 spin_lock_irqsave(&svm->ir_list_lock, flags);
695 list_for_each_entry(cur, &svm->ir_list, node) {
696 if (cur->data != pi->ir_data)
698 list_del(&cur->node);
702 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
705 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
709 struct amd_svm_iommu_ir *ir;
712 * In some cases, the existing irte is updated and re-set,
713 * so we need to check here if it's already been * added
716 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
717 struct kvm *kvm = svm->vcpu.kvm;
718 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
719 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
720 struct vcpu_svm *prev_svm;
727 prev_svm = to_svm(prev_vcpu);
728 svm_ir_list_del(prev_svm, pi);
732 * Allocating new amd_iommu_pi_data, which will get
733 * add to the per-vcpu ir_list.
735 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL_ACCOUNT);
740 ir->data = pi->ir_data;
742 spin_lock_irqsave(&svm->ir_list_lock, flags);
743 list_add(&ir->node, &svm->ir_list);
744 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
751 * The HW cannot support posting multicast/broadcast
752 * interrupts to a vCPU. So, we still use legacy interrupt
753 * remapping for these kind of interrupts.
755 * For lowest-priority interrupts, we only support
756 * those with single CPU as the destination, e.g. user
757 * configures the interrupts via /proc/irq or uses
758 * irqbalance to make the interrupts single-CPU.
761 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
762 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
764 struct kvm_lapic_irq irq;
765 struct kvm_vcpu *vcpu = NULL;
767 kvm_set_msi_irq(kvm, e, &irq);
769 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) ||
770 !kvm_irq_is_postable(&irq)) {
771 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
772 __func__, irq.vector);
776 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
779 vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
780 vcpu_info->vector = irq.vector;
786 * avic_pi_update_irte - set IRTE for Posted-Interrupts
789 * @host_irq: host irq of the interrupt
790 * @guest_irq: gsi of the interrupt
791 * @set: set or unset PI
792 * returns 0 on success, < 0 on failure
794 int avic_pi_update_irte(struct kvm *kvm, unsigned int host_irq,
795 uint32_t guest_irq, bool set)
797 struct kvm_kernel_irq_routing_entry *e;
798 struct kvm_irq_routing_table *irq_rt;
801 if (!kvm_arch_has_assigned_device(kvm) ||
802 !irq_remapping_cap(IRQ_POSTING_CAP))
805 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
806 __func__, host_irq, guest_irq, set);
808 idx = srcu_read_lock(&kvm->irq_srcu);
809 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
811 if (guest_irq >= irq_rt->nr_rt_entries ||
812 hlist_empty(&irq_rt->map[guest_irq])) {
813 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
814 guest_irq, irq_rt->nr_rt_entries);
818 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
819 struct vcpu_data vcpu_info;
820 struct vcpu_svm *svm = NULL;
822 if (e->type != KVM_IRQ_ROUTING_MSI)
826 * Here, we setup with legacy mode in the following cases:
827 * 1. When cannot target interrupt to a specific vcpu.
828 * 2. Unsetting posted interrupt.
829 * 3. APIC virtualization is disabled for the vcpu.
830 * 4. IRQ has incompatible delivery mode (SMI, INIT, etc)
832 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
833 kvm_vcpu_apicv_active(&svm->vcpu)) {
834 struct amd_iommu_pi_data pi;
836 /* Try to enable guest_mode in IRTE */
837 pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
839 pi.ga_tag = AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id,
841 pi.is_guest_mode = true;
842 pi.vcpu_data = &vcpu_info;
843 ret = irq_set_vcpu_affinity(host_irq, &pi);
846 * Here, we successfully setting up vcpu affinity in
847 * IOMMU guest mode. Now, we need to store the posted
848 * interrupt information in a per-vcpu ir_list so that
849 * we can reference to them directly when we update vcpu
850 * scheduling information in IOMMU irte.
852 if (!ret && pi.is_guest_mode)
853 svm_ir_list_add(svm, &pi);
855 /* Use legacy mode in IRTE */
856 struct amd_iommu_pi_data pi;
859 * Here, pi is used to:
860 * - Tell IOMMU to use legacy mode for this interrupt.
861 * - Retrieve ga_tag of prior interrupt remapping data.
864 pi.is_guest_mode = false;
865 ret = irq_set_vcpu_affinity(host_irq, &pi);
868 * Check if the posted interrupt was previously
869 * setup with the guest_mode by checking if the ga_tag
870 * was cached. If so, we need to clean up the per-vcpu
873 if (!ret && pi.prev_ga_tag) {
874 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
875 struct kvm_vcpu *vcpu;
877 vcpu = kvm_get_vcpu_by_id(kvm, id);
879 svm_ir_list_del(to_svm(vcpu), &pi);
884 trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id,
885 e->gsi, vcpu_info.vector,
886 vcpu_info.pi_desc_addr, set);
890 pr_err("%s: failed to update PI IRTE\n", __func__);
897 srcu_read_unlock(&kvm->irq_srcu, idx);
901 bool avic_check_apicv_inhibit_reasons(enum kvm_apicv_inhibit reason)
903 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) |
904 BIT(APICV_INHIBIT_REASON_ABSENT) |
905 BIT(APICV_INHIBIT_REASON_HYPERV) |
906 BIT(APICV_INHIBIT_REASON_NESTED) |
907 BIT(APICV_INHIBIT_REASON_IRQWIN) |
908 BIT(APICV_INHIBIT_REASON_PIT_REINJ) |
909 BIT(APICV_INHIBIT_REASON_X2APIC) |
910 BIT(APICV_INHIBIT_REASON_BLOCKIRQ) |
911 BIT(APICV_INHIBIT_REASON_SEV) |
912 BIT(APICV_INHIBIT_REASON_APIC_ID_MODIFIED) |
913 BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED);
915 return supported & BIT(reason);
920 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
924 struct amd_svm_iommu_ir *ir;
925 struct vcpu_svm *svm = to_svm(vcpu);
927 if (!kvm_arch_has_assigned_device(vcpu->kvm))
931 * Here, we go through the per-vcpu ir_list to update all existing
932 * interrupt remapping table entry targeting this vcpu.
934 spin_lock_irqsave(&svm->ir_list_lock, flags);
936 if (list_empty(&svm->ir_list))
939 list_for_each_entry(ir, &svm->ir_list, node) {
940 ret = amd_iommu_update_ga(cpu, r, ir->data);
945 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
949 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
952 int h_physical_id = kvm_cpu_get_apicid(cpu);
953 struct vcpu_svm *svm = to_svm(vcpu);
955 lockdep_assert_preemption_disabled();
957 if (WARN_ON(h_physical_id & ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK))
961 * No need to update anything if the vCPU is blocking, i.e. if the vCPU
962 * is being scheduled in after being preempted. The CPU entries in the
963 * Physical APIC table and IRTE are consumed iff IsRun{ning} is '1'.
964 * If the vCPU was migrated, its new CPU value will be stuffed when the
967 if (kvm_vcpu_is_blocking(vcpu))
970 entry = READ_ONCE(*(svm->avic_physical_id_cache));
971 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
973 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
974 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
975 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
977 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
978 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, true);
981 void avic_vcpu_put(struct kvm_vcpu *vcpu)
984 struct vcpu_svm *svm = to_svm(vcpu);
986 lockdep_assert_preemption_disabled();
988 entry = READ_ONCE(*(svm->avic_physical_id_cache));
990 /* Nothing to do if IsRunning == '0' due to vCPU blocking. */
991 if (!(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK))
994 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
996 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
997 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1001 void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
1003 struct vcpu_svm *svm = to_svm(vcpu);
1004 struct vmcb *vmcb = svm->vmcb01.ptr;
1005 bool activated = kvm_vcpu_apicv_active(vcpu);
1012 * During AVIC temporary deactivation, guest could update
1013 * APIC ID, DFR and LDR registers, which would not be trapped
1014 * by avic_unaccelerated_access_interception(). In this case,
1015 * we need to check and update the AVIC logical APIC ID table
1016 * accordingly before re-activating.
1018 avic_apicv_post_state_restore(vcpu);
1019 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1021 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
1023 vmcb_mark_dirty(vmcb, VMCB_AVIC);
1026 avic_vcpu_load(vcpu, vcpu->cpu);
1028 avic_vcpu_put(vcpu);
1030 avic_set_pi_irte_mode(vcpu, activated);
1033 void avic_vcpu_blocking(struct kvm_vcpu *vcpu)
1035 if (!kvm_vcpu_apicv_active(vcpu))
1039 * Unload the AVIC when the vCPU is about to block, _before_
1040 * the vCPU actually blocks.
1042 * Any IRQs that arrive before IsRunning=0 will not cause an
1043 * incomplete IPI vmexit on the source, therefore vIRR will also
1044 * be checked by kvm_vcpu_check_block() before blocking. The
1045 * memory barrier implicit in set_current_state orders writing
1046 * IsRunning=0 before reading the vIRR. The processor needs a
1047 * matching memory barrier on interrupt delivery between writing
1048 * IRR and reading IsRunning; the lack of this barrier might be
1049 * the cause of errata #1235).
1051 avic_vcpu_put(vcpu);
1054 void avic_vcpu_unblocking(struct kvm_vcpu *vcpu)
1056 if (!kvm_vcpu_apicv_active(vcpu))
1059 avic_vcpu_load(vcpu, vcpu->cpu);